diff --git a/arch/arm/arm-v6m/common/tos_cpu.c b/arch/arm/arm-v6m/common/tos_cpu.c index 5b94d7b8..2dc1ef25 100644 --- a/arch/arm/arm-v6m/common/tos_cpu.c +++ b/arch/arm/arm-v6m/common/tos_cpu.c @@ -15,7 +15,7 @@ * within TencentOS. *---------------------------------------------------------------------------*/ -#include +#include "tos_k.h" __API__ uint32_t tos_cpu_clz(uint32_t val) { diff --git a/arch/arm/arm-v6m/cortex-m0/gcc/port_s.S b/arch/arm/arm-v6m/cortex-m0/gcc/port_s.S index 28e5520b..45cd6571 100644 --- a/arch/arm/arm-v6m/cortex-m0/gcc/port_s.S +++ b/arch/arm/arm-v6m/cortex-m0/gcc/port_s.S @@ -58,7 +58,7 @@ port_sched_start: LDR R1, =NVIC_PENDSV_PRI - + STR R1, [R0] MOVS R0, #0 @@ -102,7 +102,7 @@ PendSV_Handler: SUBS R0, R0, #0x20 STMIA R0!, {R4 - R7} - MOV R4, R8 + MOV R4, R8 MOV R5, R9 MOV R6, R10 MOV R7, R11 @@ -123,11 +123,11 @@ PendSVHandler_nosave: LDMIA R0!, {R4 - R7} LDMIA R0!, {R2 - R3} - MOV R8, R2 + MOV R8, R2 MOV R9, R3 - LDMIA R0!, {R2 - R3} - MOV R10, R2 - MOV R11, R3 + LDMIA R0!, {R2 - R3} + MOV R10, R2 + MOV R11, R3 MSR PSP, R0 MOV R0, R14 diff --git a/arch/arm/arm-v7a/common/include/tos_arm.h b/arch/arm/arm-v7a/common/include/tos_arm.h new file mode 100644 index 00000000..2c3dd1e2 --- /dev/null +++ b/arch/arm/arm-v7a/common/include/tos_arm.h @@ -0,0 +1,43 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_ARM_H_ +#define _TOS_ARM_H_ + +#define DSB __ASM__ __VOLATILE__("dsb" ::: "memory") +#define DMB __ASM__ __VOLATILE__("dmb" ::: "memory") +#define ISB __ASM__ __VOLATILE__("isb" ::: "memory") + +#define __STRINGIFY(x) #x + +#define ARM_MCR(coproc, opcode_1, src, CRn, CRm, opcode_2) \ + __ASM__ __VOLATILE__ ("MCR " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \ + "%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " \ + __STRINGIFY(opcode_2) \ + : : "r" (src) ) + +#define ARM_MRC(coproc, opcode_1, CRn, CRm, opcode_2) \ + ({ \ + uint32_t __dst; \ + __ASM__ __VOLATILE__ ("MRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \ + "%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " \ + __STRINGIFY(opcode_2) \ + : "=r" (__dst) ); \ + __dst; \ + }) + +#endif /* _TOS_ARM_H_ */ diff --git a/arch/arm/arm-v7a/common/include/tos_chip.h b/arch/arm/arm-v7a/common/include/tos_chip.h new file mode 100644 index 00000000..f6d5bb61 --- /dev/null +++ b/arch/arm/arm-v7a/common/include/tos_chip.h @@ -0,0 +1,27 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_CHIP_H_ +#define _TOS_CHIP_H_ + +#include "chip/gic.h" +#include "chip/chip.h" + +void chip_init(void); + +#endif /* _TOS_CHIP_H_ */ + diff --git a/arch/arm/arm-v7a/common/include/tos_cpu.h b/arch/arm/arm-v7a/common/include/tos_cpu.h new file mode 100644 index 00000000..625af65e --- /dev/null +++ b/arch/arm/arm-v7a/common/include/tos_cpu.h @@ -0,0 +1,145 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_CPU_H_ +#define _TOS_CPU_H_ + +#include "tos_arm.h" +#include "tos_chip.h" +#include "tos_gic.h" +#include "tos_interrupt.h" + +typedef struct cpu_context_st { + cpu_data_t r0; + cpu_data_t r1; + cpu_data_t r2; + cpu_data_t r3; + cpu_data_t r4; + cpu_data_t r5; + cpu_data_t r6; + cpu_data_t r7; + cpu_data_t r8; + cpu_data_t r9; + cpu_data_t r10; + cpu_data_t r11; + cpu_data_t r12; + + cpu_data_t lr; + + cpu_data_t pc; + cpu_data_t cpsr; +} cpu_context_t; + +__API__ uint32_t tos_cpu_clz(uint32_t val); + +__API__ void tos_cpu_int_disable(void); + +__API__ void tos_cpu_int_enable(void); + +__API__ cpu_cpsr_t tos_cpu_cpsr_save(void); + +__API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr); + +#if (TOS_CFG_CPU_HRTIMER_EN > 0u) + +__API__ void tos_cpu_hrtimer_init(void); + +__API__ cpu_hrtimer_t tos_cpu_hrtimer_read(void); + +#endif + +__KERNEL__ void cpu_init(void); + +__KERNEL__ void cpu_reset(void); + +__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick); + +__KERNEL__ void cpu_sched_start(void); + +__KERNEL__ void cpu_context_switch(void); + +__KERNEL__ void cpu_irq_context_switch(void); + +#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u + +__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth); + +#endif + +__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, + void *arg, + void *exit, + k_stack_t *stk_base, + size_t stk_size); + +#if TOS_CFG_TICKLESS_EN > 0u + +__KERNEL__ void cpu_systick_resume(void); + +__KERNEL__ void cpu_systick_suspend(void); + +__KERNEL__ void cpu_systick_reload_reset(void); + +__KERNEL__ void cpu_systick_pending_reset(void); + +__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void); + +__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond); + +__KERNEL__ void cpu_systick_reset(void); + +#endif + +#if TOS_CFG_PWR_MGR_EN > 0u + +__KERNEL__ void cpu_sleep_mode_enter(void); + +__KERNEL__ void cpu_stop_mode_enter(void); + +__KERNEL__ void cpu_standby_mode_enter(void); + +#endif + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u + +#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) + +__KERNEL__ void cpu_flush_fpu(void); + +#endif /* TOS_CFG_CPU_ARM_FPU_EN */ + +__KERNEL__ void cpu_fault_diagnosis(void); + +#endif + +/* Allocates CPU status register word. */ +#define TOS_CPU_CPSR_ALLOC() cpu_cpsr_t cpu_cpsr = (cpu_cpsr_t)0u + +/* Save CPU status word & disable interrupts.*/ +#define TOS_CPU_INT_DISABLE() \ + do { \ + cpu_cpsr = tos_cpu_cpsr_save(); \ + } while (0) + +/* Restore CPU status word. */ +#define TOS_CPU_INT_ENABLE() \ + do { \ + tos_cpu_cpsr_restore(cpu_cpsr); \ + } while (0) + +#endif /* _TOS_CPU_H_ */ + diff --git a/arch/arm/arm-v7a/common/include/tos_cpu_def.h b/arch/arm/arm-v7a/common/include/tos_cpu_def.h new file mode 100644 index 00000000..f71d7c8e --- /dev/null +++ b/arch/arm/arm-v7a/common/include/tos_cpu_def.h @@ -0,0 +1,34 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_CPU_DEF_H_ +#define _TOS_CPU_DEF_H_ + +enum CPU_WORD_SIZE { + CPU_WORD_SIZE_08, + CPU_WORD_SIZE_16, + CPU_WORD_SIZE_32, + CPU_WORD_SIZE_64, +}; + +enum CPU_STK_GROWTH { + CPU_STK_GROWTH_ASCENDING, + CPU_STK_GROWTH_DESCENDING, +}; + +#endif /* _TOS_CPU_DEF_H_ */ + diff --git a/arch/arm/arm-v7a/common/include/tos_cpu_types.h b/arch/arm/arm-v7a/common/include/tos_cpu_types.h new file mode 100644 index 00000000..62d9e014 --- /dev/null +++ b/arch/arm/arm-v7a/common/include/tos_cpu_types.h @@ -0,0 +1,57 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_CPU_TYPES_H_ +#define _TOS_CPU_TYPES_H_ + +/* CPU address type based on address bus size. */ +#if (TOS_CFG_CPU_ADDR_SIZE == CPU_WORD_SIZE_32) +typedef uint32_t cpu_addr_t; +#elif (TOS_CFG_CPU_ADDR_SIZE == CPU_WORD_SIZE_16) +typedef uint16_t cpu_addr_t; +#else +typedef uint8_t cpu_addr_t; +#endif + +/* CPU data type based on data bus size. */ +#if (TOS_CFG_CPU_DATA_SIZE == CPU_WORD_SIZE_32) +typedef uint32_t cpu_data_t; +#elif (TOS_CFG_CPU_DATA_SIZE == CPU_WORD_SIZE_16) +typedef uint16_t cpu_data_t; +#else +typedef uint8_t cpu_data_t; +#endif + +#if (TOS_CFG_CPU_HRTIMER_EN > 0) +#if (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_08) +typedef uint8_t cpu_hrtimer_t; +#elif (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_16) +typedef uint16_t cpu_hrtimer_t; +#elif (TOS_CFG_CPU_HRTIMER_SIZE == CPU_WORD_SIZE_64) +typedef uint64_t cpu_hrtimer_t; +#else +typedef uint32_t cpu_hrtimer_t; +#endif +#else +typedef uint32_t cpu_hrtimer_t; +#endif + +//typedef cpu_addr_t size_t; +typedef cpu_addr_t cpu_cpsr_t; + +#endif + diff --git a/arch/arm/arm-v7a/common/include/tos_fault.h b/arch/arm/arm-v7a/common/include/tos_fault.h new file mode 100644 index 00000000..784c5f9d --- /dev/null +++ b/arch/arm/arm-v7a/common/include/tos_fault.h @@ -0,0 +1,236 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_FAULT_H_ +#define _TOS_FAULT_H_ + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u + +typedef int (*k_fault_log_writer_t)(const char *format, ...); + +#define K_FAULT_STACK_DUMP_DEPTH 10u + +#define K_FAULT_CALL_STACK_BACKTRACE_DEPTH 5u + +#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) +typedef struct fault_fpu_frame_st { + cpu_data_t s0; + cpu_data_t s1; + cpu_data_t s2; + cpu_data_t s3; + cpu_data_t s4; + cpu_data_t s5; + cpu_data_t s6; + cpu_data_t s7; + cpu_data_t s8; + cpu_data_t s9; + cpu_data_t s10; + cpu_data_t s11; + cpu_data_t s12; + cpu_data_t s13; + cpu_data_t s14; + cpu_data_t s15; + cpu_data_t fpscr; +} fault_fpu_frame_t; +#endif + +typedef struct fault_cpu_frame_st { + cpu_data_t r0; + cpu_data_t r1; + cpu_data_t r2; + cpu_data_t r3; + cpu_data_t r12; + cpu_data_t lr; + cpu_data_t pc; + cpu_data_t spsr; +} fault_cpu_frame_t; + +typedef struct fault_exc_frame_st { + fault_cpu_frame_t cpu_frame; + +#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) + fault_fpu_frame_t fpu_frame; +#endif +} fault_exc_frame_t; + +/** + * information we need to do fault backtrace + */ +typedef struct fault_information_st { + int is_thumb : 1; /**< whether it is thumb we use when we fall into fault? */ + int is_on_task : 1; /**< whether we are on a task when fall into fault? */ + int is_stk_ovrf : 1; /**< whether we get a stack overflow */ + +#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) + int is_ext_stk_frm : 1; /**< whether it is a extended stack frame?(whether the cpu has pushed fpu registers onto the stack) */ +#endif + + cpu_addr_t pc; /**< just where fault happens */ + + cpu_addr_t sp_before_fault; /**< original sp just before the cpu push the fault exception frame */ + + /** + * we need main_stack_start & main_stack_limit to do call stack backtrace + * when we fall into fault during a task, we should do the call stack backtrace on the task's stack + * but if not, which means we are in kernel, we should do the call stack backtrace on the main stack + * in arm v7-m, this should be the MSP's start and limit + * in arm v7-a, call stack backtrace is another story(much more elegant because we have FP). + */ + cpu_addr_t stack_start; /**< current sp start address we use. if on task, it'll be the task's stack, otherwise it'll be the msp */ + cpu_addr_t stack_limit; /**< current sp limit address */ + cpu_addr_t code_start; /**< current code start address */ + cpu_addr_t code_limit; /**< current code limit address */ +} fault_info_t; + +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + +#define DEFAULT_CODE_SECTION_NAME ER_IROM1 +#define DEFAULT_CSTACK_SECTION_NAME STACK + +#define SECTION_START(_name_) _name_##$$Base +#define SECTION_END(_name_) _name_##$$Limit +#define IMAGE_SECTION_START(_name_) Image$$##_name_##$$Base +#define IMAGE_SECTION_END(_name_) Image$$##_name_##$$Limit +#define CSTACK_BLOCK_START(_name_) SECTION_START(_name_) +#define CSTACK_BLOCK_END(_name_) SECTION_END(_name_) +#define CODE_SECTION_START(_name_) IMAGE_SECTION_START(_name_) +#define CODE_SECTION_END(_name_) IMAGE_SECTION_END(_name_) + +extern const int CSTACK_BLOCK_START(DEFAULT_CSTACK_SECTION_NAME); +extern const int CSTACK_BLOCK_END(DEFAULT_CSTACK_SECTION_NAME); +extern const int CODE_SECTION_START(DEFAULT_CODE_SECTION_NAME); +extern const int CODE_SECTION_END(DEFAULT_CODE_SECTION_NAME); + +__STATIC_INLINE__ cpu_addr_t fault_code_start(void) +{ + return (cpu_addr_t)&CODE_SECTION_START(DEFAULT_CODE_SECTION_NAME); +} + +__STATIC_INLINE__ cpu_addr_t fault_code_limit(void) +{ + return (cpu_addr_t)&CODE_SECTION_END(DEFAULT_CODE_SECTION_NAME); +} + +__STATIC_INLINE__ cpu_addr_t fault_msp_start(void) +{ + return (cpu_addr_t)&CSTACK_BLOCK_START(DEFAULT_CSTACK_SECTION_NAME); +} + +__STATIC_INLINE__ cpu_addr_t fault_msp_limit(void) +{ + return (cpu_addr_t)&CSTACK_BLOCK_END(DEFAULT_CSTACK_SECTION_NAME); +} + +#elif defined(__ICCARM__) + +#define DEFAULT_CODE_SECTION_NAME ".text" +#define DEFAULT_CSTACK_SECTION_NAME "CSTACK" + +#pragma section=DEFAULT_CSTACK_SECTION_NAME +#pragma section=DEFAULT_CODE_SECTION_NAME + +__STATIC_INLINE__ cpu_addr_t fault_code_start(void) +{ + return (cpu_addr_t)__section_begin(DEFAULT_CODE_SECTION_NAME); +} + +__STATIC_INLINE__ cpu_addr_t fault_code_limit(void) +{ + return (cpu_addr_t)__section_end(DEFAULT_CODE_SECTION_NAME); +} + +__STATIC_INLINE__ cpu_addr_t fault_msp_start(void) +{ + return (cpu_addr_t)__section_begin(DEFAULT_CSTACK_SECTION_NAME); +} + +__STATIC_INLINE__ cpu_addr_t fault_msp_limit(void) +{ + return (cpu_addr_t)__section_end(DEFAULT_CSTACK_SECTION_NAME); +} + +#elif defined(__GNUC__) + +/** + * if we are using keil(armcc) or mdk(iccarm), we probably use the defult link script supplied by the IDE. + * the way to locate the text/stack section start and limit is to find them in default link script. + * but if we build our project by makefile(or something like scons, cmake, etc), we probably need to write + * our own link scrpit, if so, we should do like this(just a demo): + * + _stext = .; + .text : { + *(.text.startup) + *(.text) + *(.text.*) + } + _etext = .; + + __bss_start = .; + .bss : { + *(.bss) + *(.bss.*) + *(COMMON) + _sstack = .; + *(.cstack) + _estack = .; + } + __bss_end = .; + * by this, we can locate text/stack section start and limit by _stext/_etext and _sstack/_estack + */ +#define DEFAULT_CODE_SECTION_START _stext +#define DEFAULT_CODE_SECTION_END _etext +#define DEFAULT_CSTACK_SECTION_START _sstack +#define DEFAULT_CSTACK_SECTION_END _estack + +extern const int DEFAULT_CODE_SECTION_START; +extern const int DEFAULT_CODE_SECTION_END; + +extern const int DEFAULT_CSTACK_SECTION_START; +extern const int DEFAULT_CSTACK_SECTION_END; + +__STATIC_INLINE__ cpu_addr_t fault_code_start(void) +{ + return (cpu_addr_t)(&(DEFAULT_CODE_SECTION_START)); +} + +__STATIC_INLINE__ cpu_addr_t fault_code_limit(void) +{ + return (cpu_addr_t)(&(DEFAULT_CODE_SECTION_END)); +} + +__STATIC_INLINE__ cpu_addr_t fault_msp_start(void) +{ + return (cpu_addr_t)(&(DEFAULT_CSTACK_SECTION_START)); +} + +__STATIC_INLINE__ cpu_addr_t fault_msp_limit(void) +{ + return (cpu_addr_t)(&(DEFAULT_CSTACK_SECTION_END)); +} + +#endif + +__API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer); + +__KERNEL__ int fault_default_log_writer(const char *format, ...); + +__KERNEL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame); + +#endif + +#endif /* _TOS_FAULT_H_ */ + diff --git a/arch/arm/arm-v7a/common/include/tos_gic.h b/arch/arm/arm-v7a/common/include/tos_gic.h new file mode 100644 index 00000000..3017833a --- /dev/null +++ b/arch/arm/arm-v7a/common/include/tos_gic.h @@ -0,0 +1,106 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_GIC_H_ +#define _TOS_GIC_H_ + +typedef struct gic_distributor_registers_st { + uint32_t D_CTLR; /*!< Offset: 0x1000 (R/W) Distributor Control Register */ + uint32_t D_TYPER; /*!< Offset: 0x1004 (R/ ) Interrupt Controller Type Register */ + uint32_t D_IIDR; /*!< Offset: 0x1008 (R/ ) Distributor Implementer Identification Register */ + uint32_t RESERVED1[29]; + uint32_t D_IGROUPR[16]; /*!< Offset: 0x1080 - 0x0BC (R/W) Interrupt Group Registers */ + uint32_t RESERVED2[16]; + uint32_t D_ISENABLER[16]; /*!< Offset: 0x1100 - 0x13C (R/W) Interrupt Set-Enable Registers */ + uint32_t RESERVED3[16]; + uint32_t D_ICENABLER[16]; /*!< Offset: 0x1180 - 0x1BC (R/W) Interrupt Clear-Enable Registers */ + uint32_t RESERVED4[16]; + uint32_t D_ISPENDR[16]; /*!< Offset: 0x1200 - 0x23C (R/W) Interrupt Set-Pending Registers */ + uint32_t RESERVED5[16]; + uint32_t D_ICPENDR[16]; /*!< Offset: 0x1280 - 0x2BC (R/W) Interrupt Clear-Pending Registers */ + uint32_t RESERVED6[16]; + uint32_t D_ISACTIVER[16]; /*!< Offset: 0x1300 - 0x33C (R/W) Interrupt Set-Active Registers */ + uint32_t RESERVED7[16]; + uint32_t D_ICACTIVER[16]; /*!< Offset: 0x1380 - 0x3BC (R/W) Interrupt Clear-Active Registers */ + uint32_t RESERVED8[16]; + uint8_t D_IPRIORITYR[512]; /*!< Offset: 0x1400 - 0x5FC (R/W) Interrupt Priority Registers */ + uint32_t RESERVED9[128]; + uint8_t D_ITARGETSR[512]; /*!< Offset: 0x1800 - 0x9FC (R/W) Interrupt Targets Registers */ + uint32_t RESERVED10[128]; + uint32_t D_ICFGR[32]; /*!< Offset: 0x1C00 - 0xC7C (R/W) Interrupt configuration registers */ + uint32_t RESERVED11[32]; + uint32_t D_PPISR; /*!< Offset: 0x1D00 (R/ ) Private Peripheral Interrupt Status Register */ + uint32_t D_SPISR[15]; /*!< Offset: 0x1D04 - 0xD3C (R/ ) Shared Peripheral Interrupt Status Registers */ + uint32_t RESERVED12[112]; + uint32_t D_SGIR; /*!< Offset: 0x1F00 ( /W) Software Generated Interrupt Register */ + uint32_t RESERVED13[3]; + uint8_t D_CPENDSGIR[16]; /*!< Offset: 0x1F10 - 0xF1C (R/W) SGI Clear-Pending Registers */ + uint8_t D_SPENDSGIR[16]; /*!< Offset: 0x1F20 - 0xF2C (R/W) SGI Set-Pending Registers */ + uint32_t RESERVED14[40]; + uint32_t D_PIDR4; /*!< Offset: 0x1FD0 (R/ ) Peripheral ID4 Register */ + uint32_t D_PIDR5; /*!< Offset: 0x1FD4 (R/ ) Peripheral ID5 Register */ + uint32_t D_PIDR6; /*!< Offset: 0x1FD8 (R/ ) Peripheral ID6 Register */ + uint32_t D_PIDR7; /*!< Offset: 0x1FDC (R/ ) Peripheral ID7 Register */ + uint32_t D_PIDR0; /*!< Offset: 0x1FE0 (R/ ) Peripheral ID0 Register */ + uint32_t D_PIDR1; /*!< Offset: 0x1FE4 (R/ ) Peripheral ID1 Register */ + uint32_t D_PIDR2; /*!< Offset: 0x1FE8 (R/ ) Peripheral ID2 Register */ + uint32_t D_PIDR3; /*!< Offset: 0x1FEC (R/ ) Peripheral ID3 Register */ + uint32_t D_CIDR0; /*!< Offset: 0x1FF0 (R/ ) Component ID0 Register */ + uint32_t D_CIDR1; /*!< Offset: 0x1FF4 (R/ ) Component ID1 Register */ + uint32_t D_CIDR2; /*!< Offset: 0x1FF8 (R/ ) Component ID2 Register */ + uint32_t D_CIDR3; /*!< Offset: 0x1FFC (R/ ) Component ID3 Register */ +} gic_dist_t; + +typedef struct gic_cpu_interface_registers_st { + uint32_t C_CTLR; /*!< Offset: 0x2000 (R/W) CPU Interface Control Register */ + uint32_t C_PMR; /*!< Offset: 0x2004 (R/W) Interrupt Priority Mask Register */ + uint32_t C_BPR; /*!< Offset: 0x2008 (R/W) Binary Point Register */ + uint32_t C_IAR; /*!< Offset: 0x200C (R/ ) Interrupt Acknowledge Register */ + uint32_t C_EOIR; /*!< Offset: 0x2010 ( /W) End Of Interrupt Register */ + uint32_t C_RPR; /*!< Offset: 0x2014 (R/ ) Running Priority Register */ + uint32_t C_HPPIR; /*!< Offset: 0x2018 (R/ ) Highest Priority Pending Interrupt Register */ + uint32_t C_ABPR; /*!< Offset: 0x201C (R/W) Aliased Binary Point Register */ + uint32_t C_AIAR; /*!< Offset: 0x2020 (R/ ) Aliased Interrupt Acknowledge Register */ + uint32_t C_AEOIR; /*!< Offset: 0x2024 ( /W) Aliased End Of Interrupt Register */ + uint32_t C_AHPPIR; /*!< Offset: 0x2028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ + uint32_t RESERVED15[41]; + uint32_t C_APR0; /*!< Offset: 0x20D0 (R/W) Active Priority Register */ + uint32_t RESERVED16[3]; + uint32_t C_NSAPR0; /*!< Offset: 0x20E0 (R/W) Non-secure Active Priority Register */ + uint32_t RESERVED17[6]; + uint32_t C_IIDR; /*!< Offset: 0x20FC (R/ ) CPU Interface Identification Register */ + uint32_t RESERVED18[960]; + uint32_t C_DIR; /*!< Offset: 0x3000 ( /W) Deactivate Interrupt Register */ +} gic_cpu_t; + +typedef struct gic_data_st { + gic_dist_t *dist; + gic_cpu_t *cpu; +} gic_data_t; + +__KERNEL__ uint32_t gic_interrupt_id_get(uint32_t gic_nr); + +__KERNEL__ void gic_interrupt_end(uint32_t gic_nr, uint32_t vector); + +__KERNEL__ int gic_init(uint32_t gic_nr); + +__KERNEL__ void gic_interrupt_enable(uint32_t gic_nr, uint32_t vector); + +__KERNEL__ void gic_interrupt_disable(uint32_t gic_nr, uint32_t vector); + +#endif /* _TOS_GIC_H_ */ + diff --git a/arch/arm/arm-v7a/common/include/tos_interrupt.h b/arch/arm/arm-v7a/common/include/tos_interrupt.h new file mode 100644 index 00000000..682a01ad --- /dev/null +++ b/arch/arm/arm-v7a/common/include/tos_interrupt.h @@ -0,0 +1,65 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _TOS_INTERRUPT_H_ +#define _TOS_INTERRUPT_H_ + +typedef void (*int_handler_t)(void *arg); + +typedef struct int_handle_st { + int_handler_t handler; + void *arg; +} int_handle_t; + +typedef struct int_frame_st { +#if 0 +#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) + uint32_t fpexc; +#endif +#endif + cpu_data_t r0; + cpu_data_t r1; + cpu_data_t r2; + cpu_data_t r3; + cpu_data_t r4; + cpu_data_t r5; + cpu_data_t r6; + cpu_data_t r7; + cpu_data_t r8; + cpu_data_t r9; + cpu_data_t r10; + cpu_data_t r11; + cpu_data_t r12; + + cpu_data_t lr; + + cpu_data_t pc; + cpu_data_t spsr; +} int_frame_t; + +__KERNEL__ void interrupt_irq(int_frame_t *int_frame); + +__KERNEL__ int interrupt_init(void); + +__API__ int tos_interrupt_handler_register(uint32_t vector, int_handler_t handler, void *arg); + +__API__ void tos_interrupt_enable(uint32_t vector); + +__API__ void tos_interrupt_disable(uint32_t vector); + +#endif /* _TOS_INTERRUPT_H_ */ + diff --git a/arch/arm/arm-v7a/common/tos_chip.c b/arch/arm/arm-v7a/common/tos_chip.c new file mode 100644 index 00000000..d7dd88a4 --- /dev/null +++ b/arch/arm/arm-v7a/common/tos_chip.c @@ -0,0 +1,25 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +#define __STUB__ __WEAK__ + +__STUB__ void chip_init(void) +{ +} + diff --git a/arch/arm/arm-v7a/common/tos_cpu.c b/arch/arm/arm-v7a/common/tos_cpu.c new file mode 100644 index 00000000..968b7332 --- /dev/null +++ b/arch/arm/arm-v7a/common/tos_cpu.c @@ -0,0 +1,286 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +__API__ uint32_t tos_cpu_clz(uint32_t val) +{ +#if defined(TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT) && (TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT == 0u) + uint32_t nbr_lead_zeros = 0; + + if (!(val & 0XFFFF0000)) { + val <<= 16; + nbr_lead_zeros += 16; + } + + if (!(val & 0XFF000000)) { + val <<= 8; + nbr_lead_zeros += 8; + } + + if (!(val & 0XF0000000)) { + val <<= 4; + nbr_lead_zeros += 4; + } + + if (!(val & 0XC0000000)) { + val <<= 2; + nbr_lead_zeros += 2; + } + + if (!(val & 0X80000000)) { + nbr_lead_zeros += 1; + } + + if (!val) { + nbr_lead_zeros += 1; + } + + return (nbr_lead_zeros); +#else + return port_clz(val); +#endif +} + +__API__ void tos_cpu_int_disable(void) +{ + port_int_disable(); +} + +__API__ void tos_cpu_int_enable(void) +{ + port_int_enable(); +} + +__API__ cpu_cpsr_t tos_cpu_cpsr_save(void) +{ + return port_cpsr_save(); +} + +__API__ void tos_cpu_cpsr_restore(cpu_cpsr_t cpsr) +{ + port_cpsr_restore(cpsr); +} + +__KERNEL__ void cpu_init(void) +{ + k_cpu_cycle_per_tick = TOS_CFG_CPU_CLOCK / k_cpu_tick_per_second; + + interrupt_init(); + chip_init(); +} + +__KERNEL__ void cpu_reset(void) +{ + port_cpu_reset(); +} + +__KERNEL__ void cpu_sched_start(void) +{ + port_sched_start(); +} + +__KERNEL__ void cpu_context_switch(void) +{ + port_context_switch(); +} + +__KERNEL__ void cpu_irq_context_switch(void) +{ + port_irq_context_switch(); +} + +__KERNEL__ void cpu_systick_init(k_cycle_t cycle_per_tick) +{ + port_systick_priority_set(TOS_CFG_CPU_SYSTICK_PRIO); + port_systick_config(cycle_per_tick); +} + +#if TOS_CFG_TICKLESS_EN > 0u + +/** + * @brief Set value to systick reload value register + * + * @param cycles The value set to register + * + * @return None + */ +__STATIC_INLINE__ void cpu_systick_reload(k_cycle_t cycle_per_tick) +{ + port_systick_reload(cycle_per_tick); +} + +/** + * @brief Enable systick interrupt + * + * @return None + */ +__KERNEL__ void cpu_systick_resume(void) +{ + port_systick_resume(); +} + +/** + * @brief Disable systick interrupt + * + * @return None + */ +__KERNEL__ void cpu_systick_suspend(void) +{ + port_systick_suspend(); +} + +__KERNEL__ k_time_t cpu_systick_max_delay_millisecond(void) +{ + return port_systick_max_delay_millisecond(); +} + +__KERNEL__ void cpu_systick_expires_set(k_time_t millisecond) +{ + k_cycle_t cycles; + + cycles = (k_cycle_t)((uint64_t)millisecond * TOS_CFG_CPU_CLOCK / K_TIME_MILLISEC_PER_SEC); /* CLOCK means cycle per second */ + + cpu_systick_reload(cycles - 12); /* interrupt delay */ +} + +__KERNEL__ void cpu_systick_pending_reset(void) +{ + port_systick_pending_reset(); +} + +__KERNEL__ void cpu_systick_reset(void) +{ + cpu_systick_reload(k_cpu_cycle_per_tick); +} + +#endif /* TOS_CFG_TICKLESS_EN */ + +#if TOS_CFG_PWR_MGR_EN > 0u + +__KERNEL__ void cpu_sleep_mode_enter(void) +{ + port_sleep_mode_enter(); +} + +__KERNEL__ void cpu_stop_mode_enter(void) +{ + port_stop_mode_enter(); +} + +__KERNEL__ void cpu_standby_mode_enter(void) +{ + port_standby_mode_enter(); +} + +#endif /* TOS_CFG_PWR_MGR_EN */ + +__KERNEL__ k_stack_t *cpu_task_stk_init(void *entry, + void *arg, + void *exit, + k_stack_t *stk_base, + size_t stk_size) +{ + cpu_data_t *sp; + cpu_context_t *context; + + sp = (cpu_data_t *)&stk_base[stk_size]; + sp = (cpu_data_t *)((cpu_addr_t)sp & 0xFFFFFFF8); + +#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u + uint8_t *slot = (uint8_t *)&stk_base[0]; + for (; slot < (uint8_t *)sp; ++slot) { + *slot = 0xCC; + } +#endif + + context = (cpu_context_t *)sp; + --context; + +#define CPSR_SVC_MODE 0x13 +#define CPSR_BIT_T 0x20 + /* we donnot set the irq bit, so first time context switch should enable irq */ + context->cpsr = CPSR_SVC_MODE; + if ((cpu_addr_t)entry & 1) { + context->cpsr |= CPSR_BIT_T; + } + + context->pc = (cpu_data_t)entry; + context->lr = (cpu_data_t)exit; + + context->r12 = (cpu_data_t)0x12121212u; + context->r11 = (cpu_data_t)0x11111111u; + context->r10 = (cpu_data_t)0x10101010u; + context->r9 = (cpu_data_t)0x09090909u; + context->r8 = (cpu_data_t)0x08080808u; + context->r7 = (cpu_data_t)0x07070707u; + context->r6 = (cpu_data_t)0x06060606u; + context->r5 = (cpu_data_t)0x05050505u; + context->r4 = (cpu_data_t)0x04040404u; + context->r3 = (cpu_data_t)0x03030303u; + context->r2 = (cpu_data_t)0x02020202u; + context->r1 = (cpu_data_t)0x01010101u; + context->r0 = (cpu_data_t)arg; + + return (k_stack_t *)context; +} + +#if TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN > 0u + +__KERNEL__ k_err_t cpu_task_stack_draught_depth(k_stack_t *stk_base, size_t stk_size, int *depth) +{ + uint8_t *slot; + uint8_t *sp, *bp; + int the_depth = 0; + + bp = (uint8_t *)&stk_base[0]; + + sp = &stk_base[stk_size]; + sp = (uint8_t *)((cpu_addr_t)sp & 0xFFFFFFF8); + + for (slot = sp - 1; slot >= bp; --slot) { + if (*slot != 0xCC) { + the_depth = sp - slot; + } + } + + *depth = the_depth; + if (the_depth == stk_size) { + return K_ERR_TASK_STK_OVERFLOW; + } + + return K_ERR_NONE; +} + +#endif + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u + +#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) +__KERNEL__ void cpu_flush_fpu(void) +{ + (void)__get_FPSCR(); +} +#endif + +__KERNEL__ void cpu_fault_diagnosis(void) +{ + port_fault_diagnosis(); +} + +#endif /* TOS_CFG_FAULT_BACKTRACE_EN */ + diff --git a/arch/arm/arm-v7a/common/tos_fault.c b/arch/arm/arm-v7a/common/tos_fault.c new file mode 100644 index 00000000..908264ee --- /dev/null +++ b/arch/arm/arm-v7a/common/tos_fault.c @@ -0,0 +1,392 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u + +__STATIC_INLINE__ void fault_spin(void) +{ + tos_knl_sched_lock(); + tos_cpu_int_disable(); + while (K_TRUE) { + ; + } +} + +/* EXC_RETURN: + 31 - 28 : EXC_RETURN flag + 27 - 5 : reserved + 4 : 1, basic stack frame; 0, extended stack frame + 3 : 1, return to Thread mode; 0, return to Handler mode + 2 : 1, return to PSP; 0, return to MSP + 1 : reserved, 0 + 0 : reserved, 1 + */ +__STATIC_INLINE__ int fault_is_on_task(cpu_data_t lr) +{ + return (lr & (1u << 2)) != 0; +} + +__STATIC_INLINE__ int fault_is_thumb(cpu_data_t psr) +{ + return (psr & (1u << 24)) != 0; +} + +__STATIC_INLINE__ int fault_is_code(fault_info_t *info, cpu_data_t value) +{ + return value >= info->code_start && value <= info->code_limit; +} + +#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) +__STATIC_INLINE__ int fault_is_extended_stack_frame(cpu_data_t lr) +{ + return (lr & (1u << 4)) == 0; +} + +__STATIC__ void fault_dump_fpu_frame(fault_fpu_frame_t *fpu_frame) +{ + /* + * As known, v7-m has a feature named "LAZY PUSH", for the reason we do not do any float + * operation in fault_backtrace, cpu will not do the real fpu register push to the stack. + * that means the value we dump in fault_dump_fpu_frame will not be the correct value of + * each FPU register. + * We define a function here which access to FPSCR, if this function involved, cpu will do + * the real FPU register push so we will get the correct dump. + * I know it's ugly, but it works. If you know a better way, please tell me. + */ + cpu_flush_fpu(); + + k_fault_log_writer("\n\n====================== FPU Registers =======================\n"); + k_fault_log_writer(" %s: %08x\n", "FPSCR", fpu_frame->fpscr); + k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n", + "S0 ", fpu_frame->s0, + "S1 ", fpu_frame->s1, + "S2 ", fpu_frame->s2, + "S3 ", fpu_frame->s3); + k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n", + "S4 ", fpu_frame->s4, + "S5 ", fpu_frame->s5, + "S6 ", fpu_frame->s6, + "S7 ", fpu_frame->s7); + k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n", + "S8 ", fpu_frame->s8, + "S9 ", fpu_frame->s9, + "S10", fpu_frame->s10, + "S11", fpu_frame->s11); + k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n", + "S12", fpu_frame->s12, + "S13", fpu_frame->s13, + "S14", fpu_frame->s14, + "S15", fpu_frame->s15); +} + +#endif + +__STATIC__ void fault_dump_cpu_frame(fault_cpu_frame_t *cpu_frame) +{ + k_fault_log_writer("\n\n====================== CPU Registers =======================\n"); + k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n", + "R0 ", cpu_frame->r0, + "R1 ", cpu_frame->r1, + "R2 ", cpu_frame->r2, + "R3 ", cpu_frame->r3); + k_fault_log_writer(" %s: %08x %s: %08x %s: %08x %s: %08x\n", + "R12", cpu_frame->r12, + "LR ", cpu_frame->lr, + "PC ", cpu_frame->pc, + "PSR", cpu_frame->spsr); +} + +__STATIC__ void fault_dump_stack(fault_info_t *info, size_t depth) +{ + cpu_addr_t sp = info->sp_before_fault;; + + k_fault_log_writer("\nTASK STACK DUMP:\n"); + while (sp <= info->stack_limit && depth--) { + k_fault_log_writer(" addr: %08x data: %08x\n", sp, (cpu_data_t)*(cpu_data_t *)sp); + sp += sizeof(cpu_addr_t); + } +} + +__STATIC__ void fault_call_stack_backtrace(fault_info_t *info, size_t depth) +{ + cpu_data_t value; + cpu_addr_t sp = info->sp_before_fault; + + if (info->is_stk_ovrf) { + return; + } + + k_fault_log_writer("\n\n====================== Dump Call Stack =====================\n"); + + k_fault_log_writer(" %x\n", info->pc); + + /* walk through the stack, check every content on stack whether is a instruction(code) */ + for (; sp < info->stack_limit && depth; sp += sizeof(cpu_addr_t)) { + value = *((cpu_addr_t *)sp) - sizeof(cpu_addr_t); + + /* if thumb, a instruction's first bit must be 1 */ + if (info->is_thumb && !(value & 1)) { + continue; + } + + if (fault_is_code(info, value)) { + k_fault_log_writer(" %x\n", value); + --depth; + } + } +} + +__STATIC__ void fault_dump_task(fault_info_t *info) +{ + k_task_t *task; + + if (!info->is_on_task) { + return; + } + + task = k_curr_task; + k_fault_log_writer("\n\n====================== Fault on task =======================\n"); + k_fault_log_writer(" TASK NAME: %s\n", task->name); + k_fault_log_writer(" STK BASE: %x\n", info->stack_start); + k_fault_log_writer(" STK SIZE: %x\n", task->stk_size * sizeof(k_stack_t)); + k_fault_log_writer(" STK LIMIT: %x\n", info->stack_limit); + + if (!info->is_stk_ovrf) { + fault_dump_stack(info, K_FAULT_STACK_DUMP_DEPTH); + } +} + +__STATIC__ void fault_dump_information(fault_info_t *info) +{ + k_fault_log_writer("\n\n================== Dump Fault Information ==================\n"); + k_fault_log_writer(" THUMB: %s\n", info->is_thumb ? "TRUE" : "FALSE"); + k_fault_log_writer(" ON TASK: %s\n", info->is_on_task? "TRUE" : "FALSE"); + k_fault_log_writer(" STK OVRF: %s\n", info->is_stk_ovrf? "TRUE" : "FALSE"); + +#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) + k_fault_log_writer(" EXT STK: %s\n", info->is_ext_stk_frm? "TRUE" : "FALSE"); +#endif + + k_fault_log_writer(" PC: %08x\n", info->pc); + k_fault_log_writer(" SP: %08x\n", info->sp_before_fault); + k_fault_log_writer(" STK START: %08x\n", info->stack_start); + k_fault_log_writer(" STK LIMIT: %08x\n", info->stack_limit); + k_fault_log_writer(" COD START: %08x\n", info->code_start); + k_fault_log_writer(" COD LIMIT: %08x\n", info->code_limit); +} + +__STATIC__ void fault_gather_information(cpu_data_t lr, fault_exc_frame_t *frame, fault_info_t *info) +{ + info->is_thumb = fault_is_thumb(frame->cpu_frame.spsr); + info->is_on_task = fault_is_on_task(lr); + + info->pc = frame->cpu_frame.pc; + + info->sp_before_fault = (cpu_addr_t)frame + sizeof(fault_cpu_frame_t); + +#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) + info->is_ext_stk_frm = fault_is_extended_stack_frame(lr); + + if (info->is_ext_stk_frm) { + info->sp_before_fault += sizeof(fault_fpu_frame_t); + } +#endif + + info->code_start = fault_code_start(); + info->code_limit = fault_code_limit(); + + if (info->is_on_task) { + info->stack_start = (cpu_addr_t)k_curr_task->stk_base; + info->stack_limit = info->stack_start + k_curr_task->stk_size * sizeof(k_task_t); + } else { + info->stack_start = fault_msp_start(); + info->stack_limit = fault_msp_limit(); + } + + info->is_stk_ovrf = (info->sp_before_fault < info->stack_start || info->sp_before_fault > info->stack_limit); +} + +__KERNEL__ int fault_default_log_writer(const char *format, ...) +{ + int len; + va_list ap; + + va_start(ap, format); + len = vprintf(format, ap); + va_end(ap); + + return len; +} + +__API__ void tos_fault_log_writer_set(k_fault_log_writer_t log_writer) +{ + k_fault_log_writer = log_writer; +} + +__KERNEL__ void fault_backtrace(cpu_addr_t lr, fault_exc_frame_t *frame) +{ + fault_info_t info; + + fault_gather_information(lr, frame, &info); + + fault_dump_information(&info); + + fault_dump_task(&info); + + fault_dump_cpu_frame(&frame->cpu_frame); + +#if defined (TOS_CFG_CPU_ARM_FPU_EN) && (TOS_CFG_CPU_ARM_FPU_EN == 1U) + if (info.is_ext_stk_frm) { + fault_dump_fpu_frame(&frame->fpu_frame); + } +#endif + + fault_call_stack_backtrace(&info, K_FAULT_CALL_STACK_BACKTRACE_DEPTH); + + cpu_fault_diagnosis(); + + fault_spin(); +} + +#endif + +struct arm_iframe { +#if 0 // VFP + uint32_t fpexc; +#endif + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r12; + uint32_t lr; + uint32_t pc; + uint32_t spsr; +}; + +struct arm_fault_frame { +#if 0 // VFP + uint32_t fpexc; +#endif + + uint32_t r[13]; + uint32_t lr; + uint32_t pc; + uint32_t spsr; +}; + +#define CPSR_MODE_MASK 0x1f +#define CPSR_MODE_USR 0x10 +#define CPSR_MODE_FIQ 0x11 +#define CPSR_MODE_IRQ 0x12 +#define CPSR_MODE_SVC 0x13 +#define CPSR_MODE_MON 0x16 +#define CPSR_MODE_ABT 0x17 +#define CPSR_MODE_UND 0x1b +#define CPSR_MODE_SYS 0x1f + +static void dump_fault_frame(struct arm_fault_frame *frame) +{ + printf("r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n", frame->r[0], frame->r[1], frame->r[2], frame->r[3]); + printf("r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", frame->r[4], frame->r[5], frame->r[6], frame->r[7]); + printf("r8 0x%08x r9 0x%08x r10 0x%08x r11 0x%08x\n", frame->r[8], frame->r[9], frame->r[10], frame->r[11]); + printf("r12 0x%08x pc 0x%08x\n", frame->r[12], frame->pc); + printf("spsr 0x%08x\n", frame->spsr); + + while (1); +} + +static void dump_iframe(struct arm_iframe *frame) +{ + printf("r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n", frame->r0, frame->r1, frame->r2, frame->r3); + printf("r12 0x%08x pc 0x%08x\n", frame->r12, frame->pc); + printf("spsr 0x%08x\n", frame->spsr); +} + +static void exception_die_iframe(struct arm_iframe *frame, const char *msg) +{ + printf("%s", msg); + dump_iframe(frame); + + while (1); +} + +void arm_undefined_handler(struct arm_iframe *frame) +{ + printf("undefined\r\n"); + + /* look at the undefined instruction, figure out if it's something we can handle */ + int in_thumb = frame->spsr & (1<<5); + if (in_thumb) { + frame->pc -= 2; + } else { + frame->pc -= 4; + } + + uint32_t opcode = *(uint32_t *)frame->pc; + printf("undefined opcode 0x%x\n", opcode); + +#if 0 // VFP + if (in_thumb) { + /* look for a 32bit thumb instruction */ + if (opcode & 0x0000e800) { + /* swap the 16bit words */ + opcode = (opcode >> 16) | (opcode << 16); + } + + if (((opcode & 0xec000e00) == 0xec000a00) || // vfp + ((opcode & 0xef000000) == 0xef000000) || // advanced simd data processing + ((opcode & 0xff100000) == 0xf9000000)) { // VLD + + //printf("vfp/neon thumb instruction 0x%08x at 0x%x\n", opcode, frame->pc); + goto fpu; + } + } else { + /* look for arm vfp/neon coprocessor instructions */ + if (((opcode & 0x0c000e00) == 0x0c000a00) || // vfp + ((opcode & 0xfe000000) == 0xf2000000) || // advanced simd data processing + ((opcode & 0xff100000) == 0xf4000000)) { // VLD + //printf("vfp/neon arm instruction 0x%08x at 0x%x\n", opcode, frame->pc); + goto fpu; + } + } +#endif + + + exception_die_iframe(frame, "undefined abort, halting\n"); + return; + +#if 0 // VFP +fpu: + arm_fpu_undefined_instruction(frame); +#endif +} + +void arm_data_abort_handler(struct arm_fault_frame *frame) +{ + printf("data abort!!\r\n"); + dump_fault_frame(frame); +} + +void arm_prefetch_abort_handler(struct arm_fault_frame *frame) +{ + printf("prefetch abort!!\r\n"); + dump_fault_frame(frame); +} + diff --git a/arch/arm/arm-v7a/common/tos_gic.c b/arch/arm/arm-v7a/common/tos_gic.c new file mode 100644 index 00000000..0a941420 --- /dev/null +++ b/arch/arm/arm-v7a/common/tos_gic.c @@ -0,0 +1,150 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +__STATIC__ gic_data_t gic_data[GIC_NRS]; + +__STATIC_INLINE__ cpu_addr_t gic_base_get(void) +{ + /* read CBAR */ + return (ARM_MRC(15, 4, 15, 0, 0) & 0xFFFF0000UL); +} + +__STATIC__ void gic_data_init(gic_data_t *gic) +{ + cpu_addr_t gic_base; + + gic_base = gic_base_get(); + + gic->dist = (gic_dist_t *)(gic_base + GICD_OFFSET); /* distributor */ + gic->cpu = (gic_cpu_t *)(gic_base + GICC_OFFSET); /* cpu interface */ +} + +__STATIC__ void gic_dist_init(gic_dist_t *gic_dist) +{ + uint32_t i = 0, int_id_max = 0; + + // let's make it simple here, maybe SMP someday, but not now +#define IT_LINES_NUMBER(d_type) ((d_type) & 0x1FUL) + int_id_max = IT_LINES_NUMBER(gic_dist->D_TYPER) + 1; + + /* Disable all PPI, SGI and SPI */ + for (i = 0; i < int_id_max; ++i) { + gic_dist->D_ICENABLER[i] = 0xFFFFFFFFUL; + } + + /* Enable group0 distribution */ + gic_dist->D_CTLR = 1UL; +} + +__STATIC__ void gic_cpu_init(gic_cpu_t *gic_cpu) +{ + /* Make all interrupts have higher priority */ + gic_cpu->C_PMR = (0xFFUL << (8 - GIC_PRIO_BITS)) & 0xFFUL; + + /* No subpriority, all priority level allows preemption */ + gic_cpu->C_BPR = 7 - GIC_PRIO_BITS; + + /* Enable group0 signaling */ + gic_cpu->C_CTLR = 1UL; +} + +__STATIC_INLINE__ gic_data_t *gic_get(uint32_t gic_nr) +{ + gic_data_t *gic; + + if (gic_nr >= GIC_NRS) { + return K_NULL; + } + + gic = &gic_data[gic_nr]; + + if (gic->cpu && gic->dist) { + return gic; + } + + return K_NULL; +} + +__KERNEL__ uint32_t gic_interrupt_id_get(uint32_t gic_nr) +{ + gic_data_t *gic = gic_get(gic_nr); + + if (gic) { +#define INTERRUPT_ID(iar) ((iar) & 0x3FFUL) + return INTERRUPT_ID(gic->cpu->C_IAR); + } + + return (uint32_t)-1; +} + +__KERNEL__ void gic_interrupt_end(uint32_t gic_nr, uint32_t vector) +{ + gic_data_t *gic = gic_get(gic_nr); + + if (gic) { + gic->cpu->C_EOIR = vector; + } +} + +__KERNEL__ int gic_init(uint32_t gic_nr) +{ + gic_data_t *gic; + + if (gic_nr >= GIC_NRS) { + return -1; + } + + gic = &gic_data[gic_nr]; + + gic_data_init(gic); + gic_dist_init(gic->dist); + gic_cpu_init(gic->cpu); + + return 0; +} + +__KERNEL__ void gic_interrupt_enable(uint32_t gic_nr, uint32_t vector) +{ + int reg; + uint32_t mask; + gic_data_t *gic; + + gic = gic_get(gic_nr); + if (gic) { + reg = vector / 32; + mask = 1ULL << (vector % 32); + + gic->dist->D_ISENABLER[reg] = mask; + } +} + +__KERNEL__ void gic_interrupt_disable(uint32_t gic_nr, uint32_t vector) +{ + int reg; + uint32_t mask; + gic_data_t *gic; + + gic = gic_get(gic_nr); + if (gic) { + reg = vector / 32; + mask = 1ULL << (vector % 32); + gic->dist->D_ICENABLER[reg] = mask; + } +} + diff --git a/arch/arm/arm-v7a/common/tos_interrupt.c b/arch/arm/arm-v7a/common/tos_interrupt.c new file mode 100644 index 00000000..ebd5f86f --- /dev/null +++ b/arch/arm/arm-v7a/common/tos_interrupt.c @@ -0,0 +1,67 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +__STATIC__ int_handle_t int_handle_table[INTERRUPT_MAX]; + +__KERNEL__ void interrupt_irq(int_frame_t *int_frame) +{ + uint32_t vector; + int_handle_t *handle; + + vector = gic_interrupt_id_get(0u); + + if (vector > INTERRUPT_MAX || vector == (uint32_t)-1) { + return; + } + + handle = &int_handle_table[vector]; + if (handle->handler) { + handle->handler(handle->arg); + } + + gic_interrupt_end(0u, vector); +} + +__KERNEL__ int interrupt_init(void) +{ + gic_init(0u); + return 0; +} + +__API__ int tos_interrupt_handler_register(uint32_t vector, int_handler_t handler, void *arg) +{ + if (vector < INTERRUPT_MAX) { + int_handle_table[vector].handler = handler; + int_handle_table[vector].arg = arg; + return 0; + } + + return -1; +} + +__API__ void tos_interrupt_enable(uint32_t vector) +{ + gic_interrupt_enable(0u, vector); +} + +__API__ void tos_interrupt_disable(uint32_t vector) +{ + gic_interrupt_disable(0u, vector); +} + diff --git a/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/clock.c b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/clock.c new file mode 100644 index 00000000..1dd74041 --- /dev/null +++ b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/clock.c @@ -0,0 +1,62 @@ +#include "tos_k.h" +#include "imx6ul.h" + +/* set the core clock to 528MHz */ +void clock_init(void) +{ + unsigned int reg = 0; + + if ((((CCM->CCSR) >> 2) & 0x1) == 0) { + CCM->CCSR &= ~(1 << 8); + CCM->CCSR |= (1 << 2); + } + + CCM_ANALOG->PLL_ARM = (1 << 13) | ((88 << 0) & 0X7F); + CCM->CCSR &= ~(1 << 2); + CCM->CACRR = 1; + + reg = CCM_ANALOG->PFD_528; + reg &= ~(0X3F3F3F3F); + reg |= 32 << 24; + reg |= 24 << 16; + reg |= 16 << 8; + reg |= 27 << 0; + CCM_ANALOG->PFD_528 = reg; + + reg = 0; + reg = CCM_ANALOG->PFD_480; + reg &= ~(0X3F3F3F3F); + reg |= 19 << 24; + reg |= 17 << 16; + reg |= 16 << 8; + reg |= 12 << 0; + CCM_ANALOG->PFD_480 = reg; + + CCM->CBCMR &= ~(3 << 18); + CCM->CBCMR |= (1 << 18); + CCM->CBCDR &= ~(1 << 25); + while(CCM->CDHIPR & (1 << 5)) { + ; + } + + CCM->CBCDR &= ~(3 << 8); + CCM->CBCDR |= 1 << 8; + + CCM->CSCMR1 &= ~(1 << 6); + CCM->CSCMR1 &= ~(7 << 0); + + CCM->CSCDR1 &= ~(1 << 6); + CCM->CSCDR1 &= ~0X3F; +} + +void clock_enable(void) +{ + CCM->CCGR0 = 0XFFFFFFFF; + CCM->CCGR1 = 0XFFFFFFFF; + CCM->CCGR2 = 0XFFFFFFFF; + CCM->CCGR3 = 0XFFFFFFFF; + CCM->CCGR4 = 0XFFFFFFFF; + CCM->CCGR5 = 0XFFFFFFFF; + CCM->CCGR6 = 0XFFFFFFFF; +} + diff --git a/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/imx6ul.c b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/imx6ul.c new file mode 100644 index 00000000..04056555 --- /dev/null +++ b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/imx6ul.c @@ -0,0 +1,27 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" +#include "imx6ul.h" + +__KERNEL__ void chip_init(void) +{ + clock_init(); + clock_enable(); + systick_init(k_cpu_tick_per_second); +} + diff --git a/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/MCIMX6Y2.h b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/MCIMX6Y2.h new file mode 100644 index 00000000..cc2d519d --- /dev/null +++ b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/MCIMX6Y2.h @@ -0,0 +1,42095 @@ +#ifndef _MCIMX6Y2_H_ +#define _MCIMX6Y2_H_ /**< Symbol preventing repeated inclusion */ + +#include "cc.h" /* cc.h为自行添加的文件 */ + + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0300U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 160 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + Software0_IRQn = 0, /**< Cortex-A7 Software Generated Interrupt 0 */ + Software1_IRQn = 1, /**< Cortex-A7 Software Generated Interrupt 1 */ + Software2_IRQn = 2, /**< Cortex-A7 Software Generated Interrupt 2 */ + Software3_IRQn = 3, /**< Cortex-A7 Software Generated Interrupt 3 */ + Software4_IRQn = 4, /**< Cortex-A7 Software Generated Interrupt 4 */ + Software5_IRQn = 5, /**< Cortex-A7 Software Generated Interrupt 5 */ + Software6_IRQn = 6, /**< Cortex-A7 Software Generated Interrupt 6 */ + Software7_IRQn = 7, /**< Cortex-A7 Software Generated Interrupt 7 */ + Software8_IRQn = 8, /**< Cortex-A7 Software Generated Interrupt 8 */ + Software9_IRQn = 9, /**< Cortex-A7 Software Generated Interrupt 9 */ + Software10_IRQn = 10, /**< Cortex-A7 Software Generated Interrupt 10 */ + Software11_IRQn = 11, /**< Cortex-A7 Software Generated Interrupt 11 */ + Software12_IRQn = 12, /**< Cortex-A7 Software Generated Interrupt 12 */ + Software13_IRQn = 13, /**< Cortex-A7 Software Generated Interrupt 13 */ + Software14_IRQn = 14, /**< Cortex-A7 Software Generated Interrupt 14 */ + Software15_IRQn = 15, /**< Cortex-A7 Software Generated Interrupt 15 */ + VirtualMaintenance_IRQn = 25, /**< Cortex-A7 Virtual Maintenance Interrupt */ + HypervisorTimer_IRQn = 26, /**< Cortex-A7 Hypervisor Timer Interrupt */ + VirtualTimer_IRQn = 27, /**< Cortex-A7 Virtual Timer Interrupt */ + LegacyFastInt_IRQn = 28, /**< Cortex-A7 Legacy nFIQ signal Interrupt */ + SecurePhyTimer_IRQn = 29, /**< Cortex-A7 Secure Physical Timer Interrupt */ + NonSecurePhyTimer_IRQn = 30, /**< Cortex-A7 Non-secure Physical Timer Interrupt */ + LegacyIRQ_IRQn = 31, /**< Cortex-A7 Legacy nIRQ Interrupt */ + + /* Device specific interrupts */ + IOMUXC_IRQn = 32, /**< General Purpose Register 1 from IOMUXC. Used to notify cores on exception condition while boot. */ + DAP_IRQn = 33, /**< Debug Access Port interrupt request. */ + SDMA_IRQn = 34, /**< SDMA interrupt request from all channels. */ + TSC_IRQn = 35, /**< TSC interrupt. */ + SNVS_IRQn = 36, /**< Logic OR of SNVS_LP and SNVS_HP interrupts. */ + LCDIF_IRQn = 37, /**< LCDIF sync interrupt. */ + RNGB_IRQn = 38, /**< RNGB interrupt. */ + CSI_IRQn = 39, /**< CMOS Sensor Interface interrupt request. */ + PXP_IRQ0_IRQn = 40, /**< PXP interrupt pxp_irq_0. */ + SCTR_IRQ0_IRQn = 41, /**< SCTR compare interrupt ipi_int[0]. */ + SCTR_IRQ1_IRQn = 42, /**< SCTR compare interrupt ipi_int[1]. */ + WDOG3_IRQn = 43, /**< WDOG3 timer reset interrupt request. */ + Reserved44_IRQn = 44, /**< Reserved */ + APBH_IRQn = 45, /**< DMA Logical OR of APBH DMA channels 0-3 completion and error interrupts. */ + WEIM_IRQn = 46, /**< WEIM interrupt request. */ + RAWNAND_BCH_IRQn = 47, /**< BCH operation complete interrupt. */ + RAWNAND_GPMI_IRQn = 48, /**< GPMI operation timeout error interrupt. */ + UART6_IRQn = 49, /**< UART6 interrupt request. */ + PXP_IRQ1_IRQn = 50, /**< PXP interrupt pxp_irq_1. */ + SNVS_Consolidated_IRQn = 51, /**< SNVS consolidated interrupt. */ + SNVS_Security_IRQn = 52, /**< SNVS security interrupt. */ + CSU_IRQn = 53, /**< CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted. */ + USDHC1_IRQn = 54, /**< USDHC1 (Enhanced SDHC) interrupt request. */ + USDHC2_IRQn = 55, /**< USDHC2 (Enhanced SDHC) interrupt request. */ + SAI3_RX_IRQn = 56, /**< SAI3 interrupt ipi_int_sai_rx. */ + SAI3_TX_IRQn = 57, /**< SAI3 interrupt ipi_int_sai_tx. */ + UART1_IRQn = 58, /**< UART1 interrupt request. */ + UART2_IRQn = 59, /**< UART2 interrupt request. */ + UART3_IRQn = 60, /**< UART3 interrupt request. */ + UART4_IRQn = 61, /**< UART4 interrupt request. */ + UART5_IRQn = 62, /**< UART5 interrupt request. */ + eCSPI1_IRQn = 63, /**< eCSPI1 interrupt request. */ + eCSPI2_IRQn = 64, /**< eCSPI2 interrupt request. */ + eCSPI3_IRQn = 65, /**< eCSPI3 interrupt request. */ + eCSPI4_IRQn = 66, /**< eCSPI4 interrupt request. */ + I2C4_IRQn = 67, /**< I2C4 interrupt request. */ + I2C1_IRQn = 68, /**< I2C1 interrupt request. */ + I2C2_IRQn = 69, /**< I2C2 interrupt request. */ + I2C3_IRQn = 70, /**< I2C3 interrupt request. */ + UART7_IRQn = 71, /**< UART-7 ORed interrupt. */ + UART8_IRQn = 72, /**< UART-8 ORed interrupt. */ + Reserved73_IRQn = 73, /**< Reserved */ + USB_OTG2_IRQn = 74, /**< USBO2 USB OTG2 */ + USB_OTG1_IRQn = 75, /**< USBO2 USB OTG1 */ + USB_PHY1_IRQn = 76, /**< UTMI0 interrupt request. */ + USB_PHY2_IRQn = 77, /**< UTMI1 interrupt request. */ + DCP_IRQ_IRQn = 78, /**< DCP interrupt request dcp_irq. */ + DCP_VMI_IRQ_IRQn = 79, /**< DCP interrupt request dcp_vmi_irq. */ + DCP_SEC_IRQ_IRQn = 80, /**< DCP interrupt request secure_irq. */ + TEMPMON_IRQn = 81, /**< Temperature Monitor Temperature Sensor (temperature greater than threshold) interrupt request. */ + ASRC_IRQn = 82, /**< ASRC interrupt request. */ + ESAI_IRQn = 83, /**< ESAI interrupt request. */ + SPDIF_IRQn = 84, /**< SPDIF interrupt. */ + Reserved85_IRQn = 85, /**< Reserved */ + PMU_IRQ1_IRQn = 86, /**< Brown-out event on either the 1.1, 2.5 or 3.0 regulators. */ + GPT1_IRQn = 87, /**< Logical OR of GPT1 rollover interrupt line, input capture 1 and 2 lines, output compare 1, 2, and 3 interrupt lines. */ + EPIT1_IRQn = 88, /**< EPIT1 output compare interrupt. */ + EPIT2_IRQn = 89, /**< EPIT2 output compare interrupt. */ + GPIO1_INT7_IRQn = 90, /**< INT7 interrupt request. */ + GPIO1_INT6_IRQn = 91, /**< INT6 interrupt request. */ + GPIO1_INT5_IRQn = 92, /**< INT5 interrupt request. */ + GPIO1_INT4_IRQn = 93, /**< INT4 interrupt request. */ + GPIO1_INT3_IRQn = 94, /**< INT3 interrupt request. */ + GPIO1_INT2_IRQn = 95, /**< INT2 interrupt request. */ + GPIO1_INT1_IRQn = 96, /**< INT1 interrupt request. */ + GPIO1_INT0_IRQn = 97, /**< INT0 interrupt request. */ + GPIO1_Combined_0_15_IRQn = 98, /**< Combined interrupt indication for GPIO1 signals 0 - 15. */ + GPIO1_Combined_16_31_IRQn = 99, /**< Combined interrupt indication for GPIO1 signals 16 - 31. */ + GPIO2_Combined_0_15_IRQn = 100, /**< Combined interrupt indication for GPIO2 signals 0 - 15. */ + GPIO2_Combined_16_31_IRQn = 101, /**< Combined interrupt indication for GPIO2 signals 16 - 31. */ + GPIO3_Combined_0_15_IRQn = 102, /**< Combined interrupt indication for GPIO3 signals 0 - 15. */ + GPIO3_Combined_16_31_IRQn = 103, /**< Combined interrupt indication for GPIO3 signals 16 - 31. */ + GPIO4_Combined_0_15_IRQn = 104, /**< Combined interrupt indication for GPIO4 signals 0 - 15. */ + GPIO4_Combined_16_31_IRQn = 105, /**< Combined interrupt indication for GPIO4 signals 16 - 31. */ + GPIO5_Combined_0_15_IRQn = 106, /**< Combined interrupt indication for GPIO5 signals 0 - 15. */ + GPIO5_Combined_16_31_IRQn = 107, /**< Combined interrupt indication for GPIO5 signals 16 - 31. */ + Reserved108_IRQn = 108, /**< Reserved */ + Reserved109_IRQn = 109, /**< Reserved */ + Reserved110_IRQn = 110, /**< Reserved */ + Reserved111_IRQn = 111, /**< Reserved */ + WDOG1_IRQn = 112, /**< WDOG1 timer reset interrupt request. */ + WDOG2_IRQn = 113, /**< WDOG2 timer reset interrupt request. */ + KPP_IRQn = 114, /**< Key Pad interrupt request. */ + PWM1_IRQn = 115, /**< hasRegInstance(`PWM1`)?`Cumulative interrupt line for PWM1. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.`:`Reserved`) */ + PWM2_IRQn = 116, /**< hasRegInstance(`PWM2`)?`Cumulative interrupt line for PWM2. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.`:`Reserved`) */ + PWM3_IRQn = 117, /**< hasRegInstance(`PWM3`)?`Cumulative interrupt line for PWM3. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.`:`Reserved`) */ + PWM4_IRQn = 118, /**< hasRegInstance(`PWM4`)?`Cumulative interrupt line for PWM4. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.`:`Reserved`) */ + CCM_IRQ1_IRQn = 119, /**< CCM interrupt request ipi_int_1. */ + CCM_IRQ2_IRQn = 120, /**< CCM interrupt request ipi_int_2. */ + GPC_IRQn = 121, /**< GPC interrupt request 1. */ + Reserved122_IRQn = 122, /**< Reserved */ + SRC_IRQn = 123, /**< SRC interrupt request src_ipi_int_1. */ + Reserved124_IRQn = 124, /**< Reserved */ + Reserved125_IRQn = 125, /**< Reserved */ + CPU_PerformanceUnit_IRQn = 126, /**< Performance Unit interrupt ~ipi_pmu_irq_b. */ + CPU_CTI_Trigger_IRQn = 127, /**< CTI trigger outputs interrupt ~ipi_cti_irq_b. */ + SRC_Combined_IRQn = 128, /**< Combined CPU wdog interrupts (4x) out of SRC. */ + SAI1_IRQn = 129, /**< SAI1 interrupt request. */ + SAI2_IRQn = 130, /**< SAI2 interrupt request. */ + Reserved131_IRQn = 131, /**< Reserved */ + ADC1_IRQn = 132, /**< ADC1 interrupt request. */ + ADC_5HC_IRQn = 133, /**< ADC_5HC interrupt request. */ + Reserved134_IRQn = 134, /**< Reserved */ + Reserved135_IRQn = 135, /**< Reserved */ + SJC_IRQn = 136, /**< SJC interrupt from General Purpose register. */ + CAAM_Job_Ring0_IRQn = 137, /**< CAAM job ring 0 interrupt ipi_caam_irq0. */ + CAAM_Job_Ring1_IRQn = 138, /**< CAAM job ring 1 interrupt ipi_caam_irq1. */ + QSPI_IRQn = 139, /**< QSPI1 interrupt request ipi_int_ored. */ + TZASC_IRQn = 140, /**< TZASC (PL380) interrupt request. */ + GPT2_IRQn = 141, /**< Logical OR of GPT2 rollover interrupt line, input capture 1 and 2 lines, output compare 1, 2 and 3 interrupt lines. */ + CAN1_IRQn = 142, /**< Combined interrupt of ini_int_busoff,ini_int_error,ipi_int_mbor,ipi_int_txwarning and ipi_int_waken */ + CAN2_IRQn = 143, /**< Combined interrupt of ini_int_busoff,ini_int_error,ipi_int_mbor,ipi_int_txwarning and ipi_int_waken */ + Reserved144_IRQn = 144, /**< Reserved */ + Reserved145_IRQn = 145, /**< Reserved */ + PWM5_IRQn = 146, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM6_IRQn = 147, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM7_IRQn = 148, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM8_IRQn = 149, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + ENET1_IRQn = 150, /**< ENET1 interrupt */ + ENET1_1588_IRQn = 151, /**< ENET1 1588 Timer interrupt [synchronous] request. */ + ENET2_IRQn = 152, /**< ENET2 interrupt */ + ENET2_1588_IRQn = 153, /**< MAC 0 1588 Timer interrupt [synchronous] request. */ + Reserved154_IRQn = 154, /**< Reserved */ + Reserved155_IRQn = 155, /**< Reserved */ + Reserved156_IRQn = 156, /**< Reserved */ + Reserved157_IRQn = 157, /**< Reserved */ + Reserved158_IRQn = 158, /**< Reserved */ + PMU_IRQ2_IRQn = 159 /**< Brown-out event on either core, gpu or soc regulators. */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Configuration of the Cortex-A7 Processor and Core Peripherals + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-A7 Processor and Core Peripherals + * @{ + */ + +#define __CA7_REV 0x0005 /**< Core revision r0p5 */ +#define __GIC_PRIO_BITS 5 /**< Number of Bits used for Priority Levels */ +#define __FPU_PRESENT 1 /**< FPU present or not */ + + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_mux_ctl_pad +{ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_MOD = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TMS = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TDO = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TDI = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TCK = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TRST_B = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART1_CTS_B = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART1_RTS_B = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART2_CTS_B = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART2_RTS_B = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART4_TX_DATA = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART4_RX_DATA = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART5_TX_DATA = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART5_RX_DATA = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_RX_DATA0 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_RX_DATA1 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_RX_EN = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_TX_DATA0 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_TX_DATA1 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_TX_EN = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_RX_ER = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_RX_DATA0 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_RX_DATA1 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_RX_EN = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_TX_DATA0 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_TX_DATA1 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_TX_EN = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_RX_ER = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_CLK = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_RESET = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA00 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA01 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA02 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA03 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA04 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA05 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA06 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA07 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA08 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA09 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA10 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA11 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA12 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA13 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA14 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA15 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA16 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA17 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA18 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA19 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA20 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA21 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA22 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA23 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_RE_B = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_WE_B = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_ALE = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_WP_B = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_READY_B = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_CLE = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DQS = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_CMD = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_CLK = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_MCLK = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA00 = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA01 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA02 = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA03 = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA04 = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA05 = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA06 = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA07 = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */ +} iomuxc_sw_mux_ctl_pad_t; + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD_DDR + * + * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD_DDR collections. + */ +typedef enum _iomuxc_sw_pad_ctl_pad_ddr +{ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 = 16U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 = 17U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B = 18U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B = 19U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B = 20U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B = 21U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B = 22U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 = 23U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 = 24U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 = 25U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 = 26U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 = 27U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 = 28U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 = 29U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P = 30U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P = 31U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P = 32U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_RESET = 33U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ +} iomuxc_sw_pad_ctl_pad_ddr_t; + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_pad_ctl_pad +{ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_MOD = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TMS = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDO = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDI = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TCK = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART1_CTS_B = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART1_RTS_B = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART2_CTS_B = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART2_RTS_B = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART4_TX_DATA = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART4_RX_DATA = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART5_TX_DATA = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART5_RX_DATA = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_RX_DATA0 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_RX_DATA1 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_RX_EN = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_TX_DATA0 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_TX_DATA1 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_TX_EN = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_RX_ER = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_RX_DATA0 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_RX_DATA1 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_RX_EN = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_TX_DATA0 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_TX_DATA1 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_TX_EN = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_RX_ER = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_CLK = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_RESET = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA00 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA01 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA02 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA03 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA04 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA05 = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA06 = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA07 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA08 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA09 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA10 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA11 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA12 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA13 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA14 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA15 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA16 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA17 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA18 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA19 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA20 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA21 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA22 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA23 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_RE_B = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_WE_B = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_ALE = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_WP_B = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_READY_B = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_CLE = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DQS = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_CMD = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_CLK = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_MCLK = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA00 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA01 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA02 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA03 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA04 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA05 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA06 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA07 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */ +} iomuxc_sw_pad_ctl_pad_t; + +/*! + * @brief Enumeration for the IOMUXC select input + * + * Defines the enumeration for the IOMUXC select input collections. + */ +typedef enum _iomuxc_select_input +{ + kIOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG2_ID_SELECT_INPUT = 1U, /**< IOMUXC select input index */ + kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA05_SELECT_INPUT = 5U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA00_SELECT_INPUT = 6U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA01_SELECT_INPUT = 7U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA04_SELECT_INPUT = 8U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA06_SELECT_INPUT = 9U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA07_SELECT_INPUT = 10U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA08_SELECT_INPUT = 11U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA09_SELECT_INPUT = 12U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA10_SELECT_INPUT = 13U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA11_SELECT_INPUT = 14U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA12_SELECT_INPUT = 15U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA13_SELECT_INPUT = 16U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA14_SELECT_INPUT = 17U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA15_SELECT_INPUT = 18U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA16_SELECT_INPUT = 19U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA17_SELECT_INPUT = 20U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA18_SELECT_INPUT = 21U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA19_SELECT_INPUT = 22U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA20_SELECT_INPUT = 23U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA21_SELECT_INPUT = 24U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA22_SELECT_INPUT = 25U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA23_SELECT_INPUT = 26U, /**< IOMUXC select input index */ + kIOMUXC_CSI_HSYNC_SELECT_INPUT = 27U, /**< IOMUXC select input index */ + kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 28U, /**< IOMUXC select input index */ + kIOMUXC_CSI_VSYNC_SELECT_INPUT = 29U, /**< IOMUXC select input index */ + kIOMUXC_CSI_FIELD_SELECT_INPUT = 30U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI1_SCLK_SELECT_INPUT = 31U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI1_MISO_SELECT_INPUT = 32U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI1_MOSI_SELECT_INPUT = 33U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI1_SS0_B_SELECT_INPUT = 34U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI2_SCLK_SELECT_INPUT = 35U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI2_MISO_SELECT_INPUT = 36U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI2_MOSI_SELECT_INPUT = 37U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI2_SS0_B_SELECT_INPUT = 38U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI3_SCLK_SELECT_INPUT = 39U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI3_MISO_SELECT_INPUT = 40U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI3_MOSI_SELECT_INPUT = 41U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI3_SS0_B_SELECT_INPUT = 42U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI4_SCLK_SELECT_INPUT = 43U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI4_MISO_SELECT_INPUT = 44U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI4_MOSI_SELECT_INPUT = 45U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI4_SS0_B_SELECT_INPUT = 46U, /**< IOMUXC select input index */ + kIOMUXC_ENET1_REF_CLK1_SELECT_INPUT = 47U, /**< IOMUXC select input index */ + kIOMUXC_ENET1_MAC0_MDIO_SELECT_INPUT = 48U, /**< IOMUXC select input index */ + kIOMUXC_ENET2_REF_CLK2_SELECT_INPUT = 49U, /**< IOMUXC select input index */ + kIOMUXC_ENET2_MAC0_MDIO_SELECT_INPUT = 50U, /**< IOMUXC select input index */ + kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 51U, /**< IOMUXC select input index */ + kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 52U, /**< IOMUXC select input index */ + kIOMUXC_GPT1_CAPTURE1_SELECT_INPUT = 53U, /**< IOMUXC select input index */ + kIOMUXC_GPT1_CAPTURE2_SELECT_INPUT = 54U, /**< IOMUXC select input index */ + kIOMUXC_GPT1_CLK_SELECT_INPUT = 55U, /**< IOMUXC select input index */ + kIOMUXC_GPT2_CAPTURE1_SELECT_INPUT = 56U, /**< IOMUXC select input index */ + kIOMUXC_GPT2_CAPTURE2_SELECT_INPUT = 57U, /**< IOMUXC select input index */ + kIOMUXC_GPT2_CLK_SELECT_INPUT = 58U, /**< IOMUXC select input index */ + kIOMUXC_I2C1_SCL_SELECT_INPUT = 59U, /**< IOMUXC select input index */ + kIOMUXC_I2C1_SDA_SELECT_INPUT = 60U, /**< IOMUXC select input index */ + kIOMUXC_I2C2_SCL_SELECT_INPUT = 61U, /**< IOMUXC select input index */ + kIOMUXC_I2C2_SDA_SELECT_INPUT = 62U, /**< IOMUXC select input index */ + kIOMUXC_I2C3_SCL_SELECT_INPUT = 63U, /**< IOMUXC select input index */ + kIOMUXC_I2C3_SDA_SELECT_INPUT = 64U, /**< IOMUXC select input index */ + kIOMUXC_I2C4_SCL_SELECT_INPUT = 65U, /**< IOMUXC select input index */ + kIOMUXC_I2C4_SDA_SELECT_INPUT = 66U, /**< IOMUXC select input index */ + kIOMUXC_KPP_COL0_SELECT_INPUT = 67U, /**< IOMUXC select input index */ + kIOMUXC_KPP_COL1_SELECT_INPUT = 68U, /**< IOMUXC select input index */ + kIOMUXC_KPP_COL2_SELECT_INPUT = 69U, /**< IOMUXC select input index */ + kIOMUXC_KPP_ROW0_SELECT_INPUT = 70U, /**< IOMUXC select input index */ + kIOMUXC_KPP_ROW1_SELECT_INPUT = 71U, /**< IOMUXC select input index */ + kIOMUXC_KPP_ROW2_SELECT_INPUT = 72U, /**< IOMUXC select input index */ + kIOMUXC_LCD_BUSY_SELECT_INPUT = 73U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_MCLK_SELECT_INPUT = 74U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA_SELECT_INPUT = 75U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 76U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 77U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_MCLK_SELECT_INPUT = 78U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_RX_DATA_SELECT_INPUT = 79U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 80U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 81U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_MCLK_SELECT_INPUT = 82U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_RX_DATA_SELECT_INPUT = 83U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_TX_BCLK_SELECT_INPUT = 84U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_TX_SYNC_SELECT_INPUT = 85U, /**< IOMUXC select input index */ + kIOMUXC_SDMA_EVENTS0_SELECT_INPUT = 86U, /**< IOMUXC select input index */ + kIOMUXC_SDMA_EVENTS1_SELECT_INPUT = 87U, /**< IOMUXC select input index */ + kIOMUXC_SPDIF_IN_SELECT_INPUT = 88U, /**< IOMUXC select input index */ + kIOMUXC_SPDIF_EXT_CLK_SELECT_INPUT = 89U, /**< IOMUXC select input index */ + kIOMUXC_UART1_RTS_B_SELECT_INPUT = 90U, /**< IOMUXC select input index */ + kIOMUXC_UART1_RX_DATA_SELECT_INPUT = 91U, /**< IOMUXC select input index */ + kIOMUXC_UART2_RTS_B_SELECT_INPUT = 92U, /**< IOMUXC select input index */ + kIOMUXC_UART2_RX_DATA_SELECT_INPUT = 93U, /**< IOMUXC select input index */ + kIOMUXC_UART3_RTS_B_SELECT_INPUT = 94U, /**< IOMUXC select input index */ + kIOMUXC_UART3_RX_DATA_SELECT_INPUT = 95U, /**< IOMUXC select input index */ + kIOMUXC_UART4_RTS_B_SELECT_INPUT = 96U, /**< IOMUXC select input index */ + kIOMUXC_UART4_RX_DATA_SELECT_INPUT = 97U, /**< IOMUXC select input index */ + kIOMUXC_UART5_RTS_B_SELECT_INPUT = 98U, /**< IOMUXC select input index */ + kIOMUXC_UART5_RX_DATA_SELECT_INPUT = 99U, /**< IOMUXC select input index */ + kIOMUXC_UART6_RTS_B_SELECT_INPUT = 100U, /**< IOMUXC select input index */ + kIOMUXC_UART6_RX_DATA_SELECT_INPUT = 101U, /**< IOMUXC select input index */ + kIOMUXC_UART7_RTS_B_SELECT_INPUT = 102U, /**< IOMUXC select input index */ + kIOMUXC_UART7_RX_DATA_SELECT_INPUT = 103U, /**< IOMUXC select input index */ + kIOMUXC_UART8_RTS_B_SELECT_INPUT = 104U, /**< IOMUXC select input index */ + kIOMUXC_UART8_RX_DATA_SELECT_INPUT = 105U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 106U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG_OC_SELECT_INPUT = 107U, /**< IOMUXC select input index */ + kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 108U, /**< IOMUXC select input index */ + kIOMUXC_USDHC1_WP_SELECT_INPUT = 109U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CLK_SELECT_INPUT = 110U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 111U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CMD_SELECT_INPUT = 112U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 113U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 114U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 115U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 116U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 117U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 118U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 119U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 120U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_WP_SELECT_INPUT = 121U, /**< IOMUXC select input index */ +} iomuxc_select_input_t; + +/* @} */ + +/*! + * @brief Enumeration for the IOMUXC group + * + * Defines the enumeration for the IOMUXC group collections. + */ +typedef enum _iomuxc_grp +{ + kIOMUXC_SW_PAD_CTL_GRP_ADDDS = 0U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL = 1U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_B0DS = 2U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRPK = 3U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_CTLDS = 4U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_B1DS = 5U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRHYS = 6U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRPKE = 7U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRMODE = 8U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDR_TYPE = 9U, /**< IOMUXC group index */ +} iomuxc_grp_t; + +/* @} */ + +/*! + * @addtogroup iomuxc_snvs_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC_SNVS SW_MUX_CTL_PAD + * + * Defines the enumeration for the IOMUXC_SNVS SW_MUX_CTL_PAD collections. + */ +typedef enum _iomuxc_snvs_sw_mux_ctl_pad +{ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_BOOT_MODE0 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_BOOT_MODE1 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER0 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER1 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER2 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER3 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER4 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER5 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER6 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER7 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER8 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER9 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ +} iomuxc_snvs_sw_mux_ctl_pad_t; + +/*! + * @addtogroup iomuxc_snvs_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC_SNVS SW_PAD_CTL_PAD + * + * Defines the enumeration for the IOMUXC_SNVS SW_PAD_CTL_PAD collections. + */ +typedef enum _iomuxc_snvs_sw_pad_ctl_pad +{ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_PMIC_ON_REQ = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_CCM_PMIC_STBY_REQ = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_BOOT_MODE0 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_BOOT_MODE1 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER0 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER1 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER2 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER3 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER4 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER5 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER6 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER7 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER8 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER9 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ +} iomuxc_snvs_sw_pad_ctl_pad_t; + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t HC[1]; /**< Control register, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[4]; + __I uint32_t HS; /**< Status register, offset: 0x8 */ + __I uint32_t R[1]; /**< Data result register, array offset: 0xC, array step: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CFG; /**< Configuration register, offset: 0x14 */ + __IO uint32_t GC; /**< General control register, offset: 0x18 */ + __IO uint32_t GS; /**< General status register, offset: 0x1C */ + __IO uint32_t CV; /**< Compare value register, offset: 0x20 */ + __IO uint32_t OFS; /**< Offset correction value register, offset: 0x24 */ + __IO uint32_t CAL; /**< Calibration value register, offset: 0x28 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name HC - Control register */ +#define ADC_HC_ADCH_MASK (0x1FU) +#define ADC_HC_ADCH_SHIFT (0U) +#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) +#define ADC_HC_AIEN_MASK (0x80U) +#define ADC_HC_AIEN_SHIFT (7U) +#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK) + +/* The count of ADC_HC */ +#define ADC_HC_COUNT (1U) + +/*! @name HS - Status register */ +#define ADC_HS_COCO0_MASK (0x1U) +#define ADC_HS_COCO0_SHIFT (0U) +#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK) + +/*! @name R - Data result register */ +#define ADC_R_CDATA_MASK (0xFFFU) +#define ADC_R_CDATA_SHIFT (0U) +#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK) + +/* The count of ADC_R */ +#define ADC_R_COUNT (1U) + +/*! @name CFG - Configuration register */ +#define ADC_CFG_ADICLK_MASK (0x3U) +#define ADC_CFG_ADICLK_SHIFT (0U) +#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) +#define ADC_CFG_MODE_MASK (0xCU) +#define ADC_CFG_MODE_SHIFT (2U) +#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) +#define ADC_CFG_ADLSMP_MASK (0x10U) +#define ADC_CFG_ADLSMP_SHIFT (4U) +#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) +#define ADC_CFG_ADIV_MASK (0x60U) +#define ADC_CFG_ADIV_SHIFT (5U) +#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) +#define ADC_CFG_ADLPC_MASK (0x80U) +#define ADC_CFG_ADLPC_SHIFT (7U) +#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) +#define ADC_CFG_ADSTS_MASK (0x300U) +#define ADC_CFG_ADSTS_SHIFT (8U) +#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) +#define ADC_CFG_ADHSC_MASK (0x400U) +#define ADC_CFG_ADHSC_SHIFT (10U) +#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) +#define ADC_CFG_REFSEL_MASK (0x1800U) +#define ADC_CFG_REFSEL_SHIFT (11U) +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) +#define ADC_CFG_ADTRG_MASK (0x2000U) +#define ADC_CFG_ADTRG_SHIFT (13U) +#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) +#define ADC_CFG_AVGS_MASK (0xC000U) +#define ADC_CFG_AVGS_SHIFT (14U) +#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) +#define ADC_CFG_OVWREN_MASK (0x10000U) +#define ADC_CFG_OVWREN_SHIFT (16U) +#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) + +/*! @name GC - General control register */ +#define ADC_GC_ADACKEN_MASK (0x1U) +#define ADC_GC_ADACKEN_SHIFT (0U) +#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) +#define ADC_GC_DMAEN_MASK (0x2U) +#define ADC_GC_DMAEN_SHIFT (1U) +#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) +#define ADC_GC_ACREN_MASK (0x4U) +#define ADC_GC_ACREN_SHIFT (2U) +#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) +#define ADC_GC_ACFGT_MASK (0x8U) +#define ADC_GC_ACFGT_SHIFT (3U) +#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) +#define ADC_GC_ACFE_MASK (0x10U) +#define ADC_GC_ACFE_SHIFT (4U) +#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) +#define ADC_GC_AVGE_MASK (0x20U) +#define ADC_GC_AVGE_SHIFT (5U) +#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) +#define ADC_GC_ADCO_MASK (0x40U) +#define ADC_GC_ADCO_SHIFT (6U) +#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) +#define ADC_GC_CAL_MASK (0x80U) +#define ADC_GC_CAL_SHIFT (7U) +#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) + +/*! @name GS - General status register */ +#define ADC_GS_ADACT_MASK (0x1U) +#define ADC_GS_ADACT_SHIFT (0U) +#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) +#define ADC_GS_CALF_MASK (0x2U) +#define ADC_GS_CALF_SHIFT (1U) +#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) +#define ADC_GS_AWKST_MASK (0x4U) +#define ADC_GS_AWKST_SHIFT (2U) +#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) + +/*! @name CV - Compare value register */ +#define ADC_CV_CV1_MASK (0xFFFU) +#define ADC_CV_CV1_SHIFT (0U) +#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) +#define ADC_CV_CV2_MASK (0xFFF0000U) +#define ADC_CV_CV2_SHIFT (16U) +#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) + +/*! @name OFS - Offset correction value register */ +#define ADC_OFS_OFS_MASK (0xFFFU) +#define ADC_OFS_OFS_SHIFT (0U) +#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) +#define ADC_OFS_SIGN_MASK (0x1000U) +#define ADC_OFS_SIGN_SHIFT (12U) +#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) + +/*! @name CAL - Calibration value register */ +#define ADC_CAL_CAL_CODE_MASK (0xFU) +#define ADC_CAL_CAL_CODE_SHIFT (0U) +#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x2198000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { 0u, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ADC_5HC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_5HC_Peripheral_Access_Layer ADC_5HC Peripheral Access Layer + * @{ + */ + +/** ADC_5HC - Register Layout Typedef */ +typedef struct { + __IO uint32_t HC[5]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */ + __I uint32_t HS; /**< Status register for HW triggers, offset: 0x14 */ + __I uint32_t R[5]; /**< Data result register for HW triggers, array offset: 0x18, array step: 0x4 */ + __IO uint32_t CFG; /**< Configuration register, offset: 0x2C */ + __IO uint32_t GC; /**< General control register, offset: 0x30 */ + __IO uint32_t GS; /**< General status register, offset: 0x34 */ + __IO uint32_t CV; /**< Compare value register, offset: 0x38 */ + __IO uint32_t OFS; /**< Offset correction value register, offset: 0x3C */ + __IO uint32_t CAL; /**< Calibration value register, offset: 0x40 */ +} ADC_5HC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC_5HC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_5HC_Register_Masks ADC_5HC Register Masks + * @{ + */ + +/*! @name HC - Control register for hardware triggers */ +#define ADC_5HC_HC_ADCH_MASK (0x1FU) +#define ADC_5HC_HC_ADCH_SHIFT (0U) +#define ADC_5HC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HC_ADCH_SHIFT)) & ADC_5HC_HC_ADCH_MASK) +#define ADC_5HC_HC_AIEN_MASK (0x80U) +#define ADC_5HC_HC_AIEN_SHIFT (7U) +#define ADC_5HC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HC_AIEN_SHIFT)) & ADC_5HC_HC_AIEN_MASK) + +/* The count of ADC_5HC_HC */ +#define ADC_5HC_HC_COUNT (5U) + +/*! @name HS - Status register for HW triggers */ +#define ADC_5HC_HS_COCO0_MASK (0x1U) +#define ADC_5HC_HS_COCO0_SHIFT (0U) +#define ADC_5HC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO0_SHIFT)) & ADC_5HC_HS_COCO0_MASK) +#define ADC_5HC_HS_COCO1_MASK (0x2U) +#define ADC_5HC_HS_COCO1_SHIFT (1U) +#define ADC_5HC_HS_COCO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO1_SHIFT)) & ADC_5HC_HS_COCO1_MASK) +#define ADC_5HC_HS_COCO2_MASK (0x4U) +#define ADC_5HC_HS_COCO2_SHIFT (2U) +#define ADC_5HC_HS_COCO2(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO2_SHIFT)) & ADC_5HC_HS_COCO2_MASK) +#define ADC_5HC_HS_COCO3_MASK (0x8U) +#define ADC_5HC_HS_COCO3_SHIFT (3U) +#define ADC_5HC_HS_COCO3(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO3_SHIFT)) & ADC_5HC_HS_COCO3_MASK) +#define ADC_5HC_HS_COCO4_MASK (0x10U) +#define ADC_5HC_HS_COCO4_SHIFT (4U) +#define ADC_5HC_HS_COCO4(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO4_SHIFT)) & ADC_5HC_HS_COCO4_MASK) + +/*! @name R - Data result register for HW triggers */ +#define ADC_5HC_R_CDATA_MASK (0xFFFU) +#define ADC_5HC_R_CDATA_SHIFT (0U) +#define ADC_5HC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_R_CDATA_SHIFT)) & ADC_5HC_R_CDATA_MASK) + +/* The count of ADC_5HC_R */ +#define ADC_5HC_R_COUNT (5U) + +/*! @name CFG - Configuration register */ +#define ADC_5HC_CFG_ADICLK_MASK (0x3U) +#define ADC_5HC_CFG_ADICLK_SHIFT (0U) +#define ADC_5HC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADICLK_SHIFT)) & ADC_5HC_CFG_ADICLK_MASK) +#define ADC_5HC_CFG_MODE_MASK (0xCU) +#define ADC_5HC_CFG_MODE_SHIFT (2U) +#define ADC_5HC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_MODE_SHIFT)) & ADC_5HC_CFG_MODE_MASK) +#define ADC_5HC_CFG_ADLSMP_MASK (0x10U) +#define ADC_5HC_CFG_ADLSMP_SHIFT (4U) +#define ADC_5HC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADLSMP_SHIFT)) & ADC_5HC_CFG_ADLSMP_MASK) +#define ADC_5HC_CFG_ADIV_MASK (0x60U) +#define ADC_5HC_CFG_ADIV_SHIFT (5U) +#define ADC_5HC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADIV_SHIFT)) & ADC_5HC_CFG_ADIV_MASK) +#define ADC_5HC_CFG_ADLPC_MASK (0x80U) +#define ADC_5HC_CFG_ADLPC_SHIFT (7U) +#define ADC_5HC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADLPC_SHIFT)) & ADC_5HC_CFG_ADLPC_MASK) +#define ADC_5HC_CFG_ADSTS_MASK (0x300U) +#define ADC_5HC_CFG_ADSTS_SHIFT (8U) +#define ADC_5HC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADSTS_SHIFT)) & ADC_5HC_CFG_ADSTS_MASK) +#define ADC_5HC_CFG_ADHSC_MASK (0x400U) +#define ADC_5HC_CFG_ADHSC_SHIFT (10U) +#define ADC_5HC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADHSC_SHIFT)) & ADC_5HC_CFG_ADHSC_MASK) +#define ADC_5HC_CFG_REFSEL_MASK (0x1800U) +#define ADC_5HC_CFG_REFSEL_SHIFT (11U) +#define ADC_5HC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_REFSEL_SHIFT)) & ADC_5HC_CFG_REFSEL_MASK) +#define ADC_5HC_CFG_ADTRG_MASK (0x2000U) +#define ADC_5HC_CFG_ADTRG_SHIFT (13U) +#define ADC_5HC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADTRG_SHIFT)) & ADC_5HC_CFG_ADTRG_MASK) +#define ADC_5HC_CFG_AVGS_MASK (0xC000U) +#define ADC_5HC_CFG_AVGS_SHIFT (14U) +#define ADC_5HC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_AVGS_SHIFT)) & ADC_5HC_CFG_AVGS_MASK) +#define ADC_5HC_CFG_OVWREN_MASK (0x10000U) +#define ADC_5HC_CFG_OVWREN_SHIFT (16U) +#define ADC_5HC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_OVWREN_SHIFT)) & ADC_5HC_CFG_OVWREN_MASK) + +/*! @name GC - General control register */ +#define ADC_5HC_GC_ADACKEN_MASK (0x1U) +#define ADC_5HC_GC_ADACKEN_SHIFT (0U) +#define ADC_5HC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ADACKEN_SHIFT)) & ADC_5HC_GC_ADACKEN_MASK) +#define ADC_5HC_GC_DMAEN_MASK (0x2U) +#define ADC_5HC_GC_DMAEN_SHIFT (1U) +#define ADC_5HC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_DMAEN_SHIFT)) & ADC_5HC_GC_DMAEN_MASK) +#define ADC_5HC_GC_ACREN_MASK (0x4U) +#define ADC_5HC_GC_ACREN_SHIFT (2U) +#define ADC_5HC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ACREN_SHIFT)) & ADC_5HC_GC_ACREN_MASK) +#define ADC_5HC_GC_ACFGT_MASK (0x8U) +#define ADC_5HC_GC_ACFGT_SHIFT (3U) +#define ADC_5HC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ACFGT_SHIFT)) & ADC_5HC_GC_ACFGT_MASK) +#define ADC_5HC_GC_ACFE_MASK (0x10U) +#define ADC_5HC_GC_ACFE_SHIFT (4U) +#define ADC_5HC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ACFE_SHIFT)) & ADC_5HC_GC_ACFE_MASK) +#define ADC_5HC_GC_AVGE_MASK (0x20U) +#define ADC_5HC_GC_AVGE_SHIFT (5U) +#define ADC_5HC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_AVGE_SHIFT)) & ADC_5HC_GC_AVGE_MASK) +#define ADC_5HC_GC_ADCO_MASK (0x40U) +#define ADC_5HC_GC_ADCO_SHIFT (6U) +#define ADC_5HC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ADCO_SHIFT)) & ADC_5HC_GC_ADCO_MASK) +#define ADC_5HC_GC_CAL_MASK (0x80U) +#define ADC_5HC_GC_CAL_SHIFT (7U) +#define ADC_5HC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_CAL_SHIFT)) & ADC_5HC_GC_CAL_MASK) + +/*! @name GS - General status register */ +#define ADC_5HC_GS_ADACT_MASK (0x1U) +#define ADC_5HC_GS_ADACT_SHIFT (0U) +#define ADC_5HC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GS_ADACT_SHIFT)) & ADC_5HC_GS_ADACT_MASK) +#define ADC_5HC_GS_CALF_MASK (0x2U) +#define ADC_5HC_GS_CALF_SHIFT (1U) +#define ADC_5HC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GS_CALF_SHIFT)) & ADC_5HC_GS_CALF_MASK) +#define ADC_5HC_GS_AWKST_MASK (0x4U) +#define ADC_5HC_GS_AWKST_SHIFT (2U) +#define ADC_5HC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GS_AWKST_SHIFT)) & ADC_5HC_GS_AWKST_MASK) + +/*! @name CV - Compare value register */ +#define ADC_5HC_CV_CV1_MASK (0xFFFU) +#define ADC_5HC_CV_CV1_SHIFT (0U) +#define ADC_5HC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CV_CV1_SHIFT)) & ADC_5HC_CV_CV1_MASK) +#define ADC_5HC_CV_CV2_MASK (0xFFF0000U) +#define ADC_5HC_CV_CV2_SHIFT (16U) +#define ADC_5HC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CV_CV2_SHIFT)) & ADC_5HC_CV_CV2_MASK) + +/*! @name OFS - Offset correction value register */ +#define ADC_5HC_OFS_OFS_MASK (0xFFFU) +#define ADC_5HC_OFS_OFS_SHIFT (0U) +#define ADC_5HC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_OFS_OFS_SHIFT)) & ADC_5HC_OFS_OFS_MASK) +#define ADC_5HC_OFS_SIGN_MASK (0x1000U) +#define ADC_5HC_OFS_SIGN_SHIFT (12U) +#define ADC_5HC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_OFS_SIGN_SHIFT)) & ADC_5HC_OFS_SIGN_MASK) + +/*! @name CAL - Calibration value register */ +#define ADC_5HC_CAL_CAL_CODE_MASK (0xFU) +#define ADC_5HC_CAL_CAL_CODE_SHIFT (0U) +#define ADC_5HC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CAL_CAL_CODE_SHIFT)) & ADC_5HC_CAL_CAL_CODE_MASK) + + +/*! + * @} + */ /* end of group ADC_5HC_Register_Masks */ + + +/* ADC_5HC - Peripheral instance base addresses */ +/** Peripheral ADC_5HC base address */ +#define ADC_5HC_BASE (0x219C000u) +/** Peripheral ADC_5HC base pointer */ +#define ADC_5HC ((ADC_5HC_Type *)ADC_5HC_BASE) +/** Array initializer of ADC_5HC peripheral base addresses */ +#define ADC_5HC_BASE_ADDRS { ADC_5HC_BASE } +/** Array initializer of ADC_5HC peripheral base pointers */ +#define ADC_5HC_BASE_PTRS { ADC_5HC } +/** Interrupt vectors for the ADC_5HC peripheral type */ +#define ADC_5HC_IRQS { ADC_5HC_IRQn } + +/*! + * @} + */ /* end of group ADC_5HC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer + * @{ + */ + +/** AIPSTZ - Register Layout Typedef */ +typedef struct { + __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */ + __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */ + __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */ + __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */ + __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */ +} AIPSTZ_Type; + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks + * @{ + */ + +/*! @name MPR - Master Priviledge Registers */ +#define AIPSTZ_MPR_MPROT5_MASK (0xF00U) +#define AIPSTZ_MPR_MPROT5_SHIFT (8U) +#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) +#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U) +#define AIPSTZ_MPR_MPROT3_SHIFT (16U) +#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) +#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U) +#define AIPSTZ_MPR_MPROT2_SHIFT (20U) +#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) +#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U) +#define AIPSTZ_MPR_MPROT1_SHIFT (24U) +#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) +#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) +#define AIPSTZ_MPR_MPROT0_SHIFT (28U) +#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) + +/*! @name OPACR - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR_OPAC7_MASK (0xFU) +#define AIPSTZ_OPACR_OPAC7_SHIFT (0U) +#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) +#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U) +#define AIPSTZ_OPACR_OPAC6_SHIFT (4U) +#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK) +#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U) +#define AIPSTZ_OPACR_OPAC5_SHIFT (8U) +#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK) +#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U) +#define AIPSTZ_OPACR_OPAC4_SHIFT (12U) +#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK) +#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U) +#define AIPSTZ_OPACR_OPAC3_SHIFT (16U) +#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK) +#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U) +#define AIPSTZ_OPACR_OPAC2_SHIFT (20U) +#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK) +#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U) +#define AIPSTZ_OPACR_OPAC1_SHIFT (24U) +#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK) +#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) +#define AIPSTZ_OPACR_OPAC0_SHIFT (28U) +#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) + +/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) +#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) +#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) +#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U) +#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U) +#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK) +#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U) +#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U) +#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK) +#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U) +#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U) +#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK) +#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U) +#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U) +#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK) +#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U) +#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U) +#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK) +#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U) +#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U) +#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK) +#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) +#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) +#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) + +/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) +#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) +#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) +#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U) +#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U) +#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK) +#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U) +#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U) +#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK) +#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U) +#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U) +#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK) +#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U) +#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U) +#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK) +#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U) +#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U) +#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK) +#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U) +#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U) +#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK) +#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) +#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) +#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) + +/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) +#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) +#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) +#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U) +#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U) +#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK) +#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U) +#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U) +#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK) +#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U) +#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U) +#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK) +#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U) +#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U) +#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK) +#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U) +#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U) +#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK) +#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U) +#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U) +#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK) +#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) +#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) +#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) + +/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) +#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) +#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) +#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) +#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) +#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) + + +/*! + * @} + */ /* end of group AIPSTZ_Register_Masks */ + + +/* AIPSTZ - Peripheral instance base addresses */ +/** Peripheral AIPSTZ1 base address */ +#define AIPSTZ1_BASE (0x207C000u) +/** Peripheral AIPSTZ1 base pointer */ +#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE) +/** Peripheral AIPSTZ2 base address */ +#define AIPSTZ2_BASE (0x217C000u) +/** Peripheral AIPSTZ2 base pointer */ +#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE) +/** Peripheral AIPSTZ3 base address */ +#define AIPSTZ3_BASE (0x227C000u) +/** Peripheral AIPSTZ3 base pointer */ +#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE) +/** Array initializer of AIPSTZ peripheral base addresses */ +#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE } +/** Array initializer of AIPSTZ peripheral base pointers */ +#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3 } + +/*! + * @} + */ /* end of group AIPSTZ_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- APBH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer + * @{ + */ + +/** APBH - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */ + __IO uint32_t CTRL0_SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */ + __IO uint32_t CTRL0_CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */ + __IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */ + __IO uint32_t CTRL1; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */ + __IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */ + __IO uint32_t CTRL1_CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */ + __IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */ + __IO uint32_t CTRL2; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */ + __IO uint32_t CTRL2_SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */ + __IO uint32_t CTRL2_CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */ + __IO uint32_t CTRL2_TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */ + __IO uint32_t CHANNEL_CTRL; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */ + __IO uint32_t CHANNEL_CTRL_SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */ + __IO uint32_t CHANNEL_CTRL_CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */ + __IO uint32_t CHANNEL_CTRL_TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */ + __I uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */ + uint8_t RESERVED_1[12]; + __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */ + uint8_t RESERVED_2[156]; + __I uint32_t CH0_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x100 */ + uint8_t RESERVED_3[12]; + __IO uint32_t CH0_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x110 */ + uint8_t RESERVED_4[12]; + __I uint32_t CH0_CMD; /**< APBH DMA Channel n Command Register, offset: 0x120 */ + uint8_t RESERVED_5[12]; + __I uint32_t CH0_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x130 */ + uint8_t RESERVED_6[12]; + __IO uint32_t CH0_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x140 */ + uint8_t RESERVED_7[12]; + __I uint32_t CH0_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x150 */ + uint8_t RESERVED_8[12]; + __I uint32_t CH0_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x160 */ + uint8_t RESERVED_9[12]; + __I uint32_t CH1_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x170 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CH1_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x180 */ + uint8_t RESERVED_11[12]; + __I uint32_t CH1_CMD; /**< APBH DMA Channel n Command Register, offset: 0x190 */ + uint8_t RESERVED_12[12]; + __I uint32_t CH1_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x1A0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CH1_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x1B0 */ + uint8_t RESERVED_14[12]; + __I uint32_t CH1_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1C0 */ + uint8_t RESERVED_15[12]; + __I uint32_t CH1_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1D0 */ + uint8_t RESERVED_16[12]; + __I uint32_t CH2_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x1E0 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CH2_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x1F0 */ + uint8_t RESERVED_18[12]; + __I uint32_t CH2_CMD; /**< APBH DMA Channel n Command Register, offset: 0x200 */ + uint8_t RESERVED_19[12]; + __I uint32_t CH2_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x210 */ + uint8_t RESERVED_20[12]; + __IO uint32_t CH2_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x220 */ + uint8_t RESERVED_21[12]; + __I uint32_t CH2_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x230 */ + uint8_t RESERVED_22[12]; + __I uint32_t CH2_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x240 */ + uint8_t RESERVED_23[12]; + __I uint32_t CH3_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x250 */ + uint8_t RESERVED_24[12]; + __IO uint32_t CH3_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x260 */ + uint8_t RESERVED_25[12]; + __I uint32_t CH3_CMD; /**< APBH DMA Channel n Command Register, offset: 0x270 */ + uint8_t RESERVED_26[12]; + __I uint32_t CH3_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x280 */ + uint8_t RESERVED_27[12]; + __IO uint32_t CH3_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x290 */ + uint8_t RESERVED_28[12]; + __I uint32_t CH3_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2A0 */ + uint8_t RESERVED_29[12]; + __I uint32_t CH3_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2B0 */ + uint8_t RESERVED_30[12]; + __I uint32_t CH4_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x2C0 */ + uint8_t RESERVED_31[12]; + __IO uint32_t CH4_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x2D0 */ + uint8_t RESERVED_32[12]; + __I uint32_t CH4_CMD; /**< APBH DMA Channel n Command Register, offset: 0x2E0 */ + uint8_t RESERVED_33[12]; + __I uint32_t CH4_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x2F0 */ + uint8_t RESERVED_34[12]; + __IO uint32_t CH4_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x300 */ + uint8_t RESERVED_35[12]; + __I uint32_t CH4_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x310 */ + uint8_t RESERVED_36[12]; + __I uint32_t CH4_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x320 */ + uint8_t RESERVED_37[12]; + __I uint32_t CH5_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x330 */ + uint8_t RESERVED_38[12]; + __IO uint32_t CH5_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x340 */ + uint8_t RESERVED_39[12]; + __I uint32_t CH5_CMD; /**< APBH DMA Channel n Command Register, offset: 0x350 */ + uint8_t RESERVED_40[12]; + __I uint32_t CH5_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x360 */ + uint8_t RESERVED_41[12]; + __IO uint32_t CH5_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x370 */ + uint8_t RESERVED_42[12]; + __I uint32_t CH5_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x380 */ + uint8_t RESERVED_43[12]; + __I uint32_t CH5_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x390 */ + uint8_t RESERVED_44[12]; + __I uint32_t CH6_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x3A0 */ + uint8_t RESERVED_45[12]; + __IO uint32_t CH6_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x3B0 */ + uint8_t RESERVED_46[12]; + __I uint32_t CH6_CMD; /**< APBH DMA Channel n Command Register, offset: 0x3C0 */ + uint8_t RESERVED_47[12]; + __I uint32_t CH6_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x3D0 */ + uint8_t RESERVED_48[12]; + __IO uint32_t CH6_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x3E0 */ + uint8_t RESERVED_49[12]; + __I uint32_t CH6_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x3F0 */ + uint8_t RESERVED_50[12]; + __I uint32_t CH6_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x400 */ + uint8_t RESERVED_51[12]; + __I uint32_t CH7_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x410 */ + uint8_t RESERVED_52[12]; + __IO uint32_t CH7_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x420 */ + uint8_t RESERVED_53[12]; + __I uint32_t CH7_CMD; /**< APBH DMA Channel n Command Register, offset: 0x430 */ + uint8_t RESERVED_54[12]; + __I uint32_t CH7_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x440 */ + uint8_t RESERVED_55[12]; + __IO uint32_t CH7_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x450 */ + uint8_t RESERVED_56[12]; + __I uint32_t CH7_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x460 */ + uint8_t RESERVED_57[12]; + __I uint32_t CH7_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x470 */ + uint8_t RESERVED_58[12]; + __I uint32_t CH8_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x480 */ + uint8_t RESERVED_59[12]; + __IO uint32_t CH8_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x490 */ + uint8_t RESERVED_60[12]; + __I uint32_t CH8_CMD; /**< APBH DMA Channel n Command Register, offset: 0x4A0 */ + uint8_t RESERVED_61[12]; + __I uint32_t CH8_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x4B0 */ + uint8_t RESERVED_62[12]; + __IO uint32_t CH8_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x4C0 */ + uint8_t RESERVED_63[12]; + __I uint32_t CH8_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4D0 */ + uint8_t RESERVED_64[12]; + __I uint32_t CH8_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4E0 */ + uint8_t RESERVED_65[12]; + __I uint32_t CH9_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x4F0 */ + uint8_t RESERVED_66[12]; + __IO uint32_t CH9_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x500 */ + uint8_t RESERVED_67[12]; + __I uint32_t CH9_CMD; /**< APBH DMA Channel n Command Register, offset: 0x510 */ + uint8_t RESERVED_68[12]; + __I uint32_t CH9_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x520 */ + uint8_t RESERVED_69[12]; + __IO uint32_t CH9_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x530 */ + uint8_t RESERVED_70[12]; + __I uint32_t CH9_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x540 */ + uint8_t RESERVED_71[12]; + __I uint32_t CH9_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x550 */ + uint8_t RESERVED_72[12]; + __I uint32_t CH10_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x560 */ + uint8_t RESERVED_73[12]; + __IO uint32_t CH10_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x570 */ + uint8_t RESERVED_74[12]; + __I uint32_t CH10_CMD; /**< APBH DMA Channel n Command Register, offset: 0x580 */ + uint8_t RESERVED_75[12]; + __I uint32_t CH10_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x590 */ + uint8_t RESERVED_76[12]; + __IO uint32_t CH10_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x5A0 */ + uint8_t RESERVED_77[12]; + __I uint32_t CH10_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5B0 */ + uint8_t RESERVED_78[12]; + __I uint32_t CH10_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5C0 */ + uint8_t RESERVED_79[12]; + __I uint32_t CH11_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x5D0 */ + uint8_t RESERVED_80[12]; + __IO uint32_t CH11_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x5E0 */ + uint8_t RESERVED_81[12]; + __I uint32_t CH11_CMD; /**< APBH DMA Channel n Command Register, offset: 0x5F0 */ + uint8_t RESERVED_82[12]; + __I uint32_t CH11_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x600 */ + uint8_t RESERVED_83[12]; + __IO uint32_t CH11_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x610 */ + uint8_t RESERVED_84[12]; + __I uint32_t CH11_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x620 */ + uint8_t RESERVED_85[12]; + __I uint32_t CH11_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x630 */ + uint8_t RESERVED_86[12]; + __I uint32_t CH12_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x640 */ + uint8_t RESERVED_87[12]; + __IO uint32_t CH12_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x650 */ + uint8_t RESERVED_88[12]; + __I uint32_t CH12_CMD; /**< APBH DMA Channel n Command Register, offset: 0x660 */ + uint8_t RESERVED_89[12]; + __I uint32_t CH12_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x670 */ + uint8_t RESERVED_90[12]; + __IO uint32_t CH12_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x680 */ + uint8_t RESERVED_91[12]; + __I uint32_t CH12_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x690 */ + uint8_t RESERVED_92[12]; + __I uint32_t CH12_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x6A0 */ + uint8_t RESERVED_93[12]; + __I uint32_t CH13_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x6B0 */ + uint8_t RESERVED_94[12]; + __IO uint32_t CH13_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x6C0 */ + uint8_t RESERVED_95[12]; + __I uint32_t CH13_CMD; /**< APBH DMA Channel n Command Register, offset: 0x6D0 */ + uint8_t RESERVED_96[12]; + __I uint32_t CH13_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x6E0 */ + uint8_t RESERVED_97[12]; + __IO uint32_t CH13_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x6F0 */ + uint8_t RESERVED_98[12]; + __I uint32_t CH13_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x700 */ + uint8_t RESERVED_99[12]; + __I uint32_t CH13_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x710 */ + uint8_t RESERVED_100[12]; + __I uint32_t CH14_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x720 */ + uint8_t RESERVED_101[12]; + __IO uint32_t CH14_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x730 */ + uint8_t RESERVED_102[12]; + __I uint32_t CH14_CMD; /**< APBH DMA Channel n Command Register, offset: 0x740 */ + uint8_t RESERVED_103[12]; + __I uint32_t CH14_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x750 */ + uint8_t RESERVED_104[12]; + __IO uint32_t CH14_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x760 */ + uint8_t RESERVED_105[12]; + __I uint32_t CH14_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x770 */ + uint8_t RESERVED_106[12]; + __I uint32_t CH14_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x780 */ + uint8_t RESERVED_107[12]; + __I uint32_t CH15_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x790 */ + uint8_t RESERVED_108[12]; + __IO uint32_t CH15_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x7A0 */ + uint8_t RESERVED_109[12]; + __I uint32_t CH15_CMD; /**< APBH DMA Channel n Command Register, offset: 0x7B0 */ + uint8_t RESERVED_110[12]; + __I uint32_t CH15_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x7C0 */ + uint8_t RESERVED_111[12]; + __IO uint32_t CH15_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x7D0 */ + uint8_t RESERVED_112[12]; + __I uint32_t CH15_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7E0 */ + uint8_t RESERVED_113[12]; + __I uint32_t CH15_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7F0 */ + uint8_t RESERVED_114[12]; + __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */ +} APBH_Type; + +/* ---------------------------------------------------------------------------- + -- APBH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup APBH_Register_Masks APBH Register Masks + * @{ + */ + +/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */ +#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U) +#define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_RSVD0_SHIFT (16U) +#define APBH_CTRL0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_RSVD0_SHIFT)) & APBH_CTRL0_RSVD0_MASK) +#define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK) +#define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK) +#define APBH_CTRL0_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK) +#define APBH_CTRL0_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_SFTRST_SHIFT (31U) +#define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK) + +/*! @name CTRL0_SET - AHB to APBH Bridge Control and Status Register 0 */ +#define APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT (0U) +#define APBH_CTRL0_SET_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_SET_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_SET_RSVD0_SHIFT (16U) +#define APBH_CTRL0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_RSVD0_SHIFT)) & APBH_CTRL0_SET_RSVD0_MASK) +#define APBH_CTRL0_SET_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_SET_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_SET_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_APB_BURST_EN_SHIFT)) & APBH_CTRL0_SET_APB_BURST_EN_MASK) +#define APBH_CTRL0_SET_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_SET_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_SET_AHB_BURST8_EN_MASK) +#define APBH_CTRL0_SET_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_SET_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_SHIFT)) & APBH_CTRL0_SET_CLKGATE_MASK) +#define APBH_CTRL0_SET_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_SET_SFTRST_SHIFT (31U) +#define APBH_CTRL0_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_SFTRST_SHIFT)) & APBH_CTRL0_SET_SFTRST_MASK) + +/*! @name CTRL0_CLR - AHB to APBH Bridge Control and Status Register 0 */ +#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT (0U) +#define APBH_CTRL0_CLR_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_CLR_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_CLR_RSVD0_SHIFT (16U) +#define APBH_CTRL0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_RSVD0_SHIFT)) & APBH_CTRL0_CLR_RSVD0_MASK) +#define APBH_CTRL0_CLR_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_CLR_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_CLR_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_APB_BURST_EN_SHIFT)) & APBH_CTRL0_CLR_APB_BURST_EN_MASK) +#define APBH_CTRL0_CLR_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_CLR_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_CLR_AHB_BURST8_EN_MASK) +#define APBH_CTRL0_CLR_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_CLR_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_MASK) +#define APBH_CTRL0_CLR_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_CLR_SFTRST_SHIFT (31U) +#define APBH_CTRL0_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_SFTRST_SHIFT)) & APBH_CTRL0_CLR_SFTRST_MASK) + +/*! @name CTRL0_TOG - AHB to APBH Bridge Control and Status Register 0 */ +#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT (0U) +#define APBH_CTRL0_TOG_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_TOG_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_TOG_RSVD0_SHIFT (16U) +#define APBH_CTRL0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_RSVD0_SHIFT)) & APBH_CTRL0_TOG_RSVD0_MASK) +#define APBH_CTRL0_TOG_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_TOG_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_TOG_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_APB_BURST_EN_SHIFT)) & APBH_CTRL0_TOG_APB_BURST_EN_MASK) +#define APBH_CTRL0_TOG_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_TOG_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_TOG_AHB_BURST8_EN_MASK) +#define APBH_CTRL0_TOG_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_TOG_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_MASK) +#define APBH_CTRL0_TOG_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_TOG_SFTRST_SHIFT (31U) +#define APBH_CTRL0_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_SFTRST_SHIFT)) & APBH_CTRL0_TOG_SFTRST_MASK) + +/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */ +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK) + +/*! @name CTRL1_SET - AHB to APBH Bridge Control and Status Register 1 */ +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK) + +/*! @name CTRL1_CLR - AHB to APBH Bridge Control and Status Register 1 */ +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK) + +/*! @name CTRL1_TOG - AHB to APBH Bridge Control and Status Register 1 */ +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK) + +/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */ +#define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U) +#define APBH_CTRL2_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U) +#define APBH_CTRL2_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U) +#define APBH_CTRL2_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U) +#define APBH_CTRL2_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U) +#define APBH_CTRL2_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U) +#define APBH_CTRL2_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U) +#define APBH_CTRL2_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U) +#define APBH_CTRL2_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U) +#define APBH_CTRL2_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U) +#define APBH_CTRL2_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U) +#define APBH_CTRL2_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U) +#define APBH_CTRL2_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U) +#define APBH_CTRL2_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U) +#define APBH_CTRL2_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U) +#define APBH_CTRL2_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U) +#define APBH_CTRL2_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK) + +/*! @name CTRL2_SET - AHB to APBH Bridge Control and Status Register 2 */ +#define APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_SET_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_SET_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_SET_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_SET_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_SET_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_SET_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_SET_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_SET_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_SET_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_SET_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_SET_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_SET_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_SET_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_SET_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_SET_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_SET_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT (16U) +#define APBH_CTRL2_SET_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT (17U) +#define APBH_CTRL2_SET_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT (18U) +#define APBH_CTRL2_SET_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT (19U) +#define APBH_CTRL2_SET_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT (20U) +#define APBH_CTRL2_SET_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT (21U) +#define APBH_CTRL2_SET_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT (22U) +#define APBH_CTRL2_SET_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT (23U) +#define APBH_CTRL2_SET_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT (24U) +#define APBH_CTRL2_SET_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT (25U) +#define APBH_CTRL2_SET_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT (26U) +#define APBH_CTRL2_SET_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT (27U) +#define APBH_CTRL2_SET_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT (28U) +#define APBH_CTRL2_SET_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT (29U) +#define APBH_CTRL2_SET_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT (30U) +#define APBH_CTRL2_SET_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT (31U) +#define APBH_CTRL2_SET_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK) + +/*! @name CTRL2_CLR - AHB to APBH Bridge Control and Status Register 2 */ +#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_CLR_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_CLR_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_CLR_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_CLR_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_CLR_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_CLR_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_CLR_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_CLR_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_CLR_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_CLR_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_CLR_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_CLR_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_CLR_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_CLR_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_CLR_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_CLR_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT (16U) +#define APBH_CTRL2_CLR_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT (17U) +#define APBH_CTRL2_CLR_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT (18U) +#define APBH_CTRL2_CLR_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT (19U) +#define APBH_CTRL2_CLR_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT (20U) +#define APBH_CTRL2_CLR_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT (21U) +#define APBH_CTRL2_CLR_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT (22U) +#define APBH_CTRL2_CLR_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT (23U) +#define APBH_CTRL2_CLR_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT (24U) +#define APBH_CTRL2_CLR_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT (25U) +#define APBH_CTRL2_CLR_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT (26U) +#define APBH_CTRL2_CLR_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT (27U) +#define APBH_CTRL2_CLR_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT (28U) +#define APBH_CTRL2_CLR_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT (29U) +#define APBH_CTRL2_CLR_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT (30U) +#define APBH_CTRL2_CLR_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT (31U) +#define APBH_CTRL2_CLR_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK) + +/*! @name CTRL2_TOG - AHB to APBH Bridge Control and Status Register 2 */ +#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_TOG_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_TOG_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_TOG_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_TOG_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_TOG_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_TOG_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_TOG_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_TOG_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_TOG_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_TOG_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_TOG_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_TOG_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_TOG_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_TOG_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_TOG_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_TOG_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT (16U) +#define APBH_CTRL2_TOG_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT (17U) +#define APBH_CTRL2_TOG_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT (18U) +#define APBH_CTRL2_TOG_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT (19U) +#define APBH_CTRL2_TOG_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT (20U) +#define APBH_CTRL2_TOG_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT (21U) +#define APBH_CTRL2_TOG_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT (22U) +#define APBH_CTRL2_TOG_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT (23U) +#define APBH_CTRL2_TOG_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT (24U) +#define APBH_CTRL2_TOG_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT (25U) +#define APBH_CTRL2_TOG_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT (26U) +#define APBH_CTRL2_TOG_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT (27U) +#define APBH_CTRL2_TOG_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT (28U) +#define APBH_CTRL2_TOG_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT (29U) +#define APBH_CTRL2_TOG_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT (30U) +#define APBH_CTRL2_TOG_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT (31U) +#define APBH_CTRL2_TOG_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK) + +/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */ +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U) +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK) + +/*! @name CHANNEL_CTRL_SET - AHB to APBH Bridge Channel Register */ +#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT (0U) +#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT (16U) +#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK) + +/*! @name CHANNEL_CTRL_CLR - AHB to APBH Bridge Channel Register */ +#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT (0U) +#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT (16U) +#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK) + +/*! @name CHANNEL_CTRL_TOG - AHB to APBH Bridge Channel Register */ +#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT (0U) +#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT (16U) +#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK) + +/*! @name DEVSEL - AHB to APBH DMA Device Assignment Register */ +#define APBH_DEVSEL_CH0_MASK (0x3U) +#define APBH_DEVSEL_CH0_SHIFT (0U) +#define APBH_DEVSEL_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH0_SHIFT)) & APBH_DEVSEL_CH0_MASK) +#define APBH_DEVSEL_CH1_MASK (0xCU) +#define APBH_DEVSEL_CH1_SHIFT (2U) +#define APBH_DEVSEL_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH1_SHIFT)) & APBH_DEVSEL_CH1_MASK) +#define APBH_DEVSEL_CH2_MASK (0x30U) +#define APBH_DEVSEL_CH2_SHIFT (4U) +#define APBH_DEVSEL_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH2_SHIFT)) & APBH_DEVSEL_CH2_MASK) +#define APBH_DEVSEL_CH3_MASK (0xC0U) +#define APBH_DEVSEL_CH3_SHIFT (6U) +#define APBH_DEVSEL_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH3_SHIFT)) & APBH_DEVSEL_CH3_MASK) +#define APBH_DEVSEL_CH4_MASK (0x300U) +#define APBH_DEVSEL_CH4_SHIFT (8U) +#define APBH_DEVSEL_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH4_SHIFT)) & APBH_DEVSEL_CH4_MASK) +#define APBH_DEVSEL_CH5_MASK (0xC00U) +#define APBH_DEVSEL_CH5_SHIFT (10U) +#define APBH_DEVSEL_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH5_SHIFT)) & APBH_DEVSEL_CH5_MASK) +#define APBH_DEVSEL_CH6_MASK (0x3000U) +#define APBH_DEVSEL_CH6_SHIFT (12U) +#define APBH_DEVSEL_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH6_SHIFT)) & APBH_DEVSEL_CH6_MASK) +#define APBH_DEVSEL_CH7_MASK (0xC000U) +#define APBH_DEVSEL_CH7_SHIFT (14U) +#define APBH_DEVSEL_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH7_SHIFT)) & APBH_DEVSEL_CH7_MASK) +#define APBH_DEVSEL_CH8_MASK (0x30000U) +#define APBH_DEVSEL_CH8_SHIFT (16U) +#define APBH_DEVSEL_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH8_SHIFT)) & APBH_DEVSEL_CH8_MASK) +#define APBH_DEVSEL_CH9_MASK (0xC0000U) +#define APBH_DEVSEL_CH9_SHIFT (18U) +#define APBH_DEVSEL_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH9_SHIFT)) & APBH_DEVSEL_CH9_MASK) +#define APBH_DEVSEL_CH10_MASK (0x300000U) +#define APBH_DEVSEL_CH10_SHIFT (20U) +#define APBH_DEVSEL_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH10_SHIFT)) & APBH_DEVSEL_CH10_MASK) +#define APBH_DEVSEL_CH11_MASK (0xC00000U) +#define APBH_DEVSEL_CH11_SHIFT (22U) +#define APBH_DEVSEL_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH11_SHIFT)) & APBH_DEVSEL_CH11_MASK) +#define APBH_DEVSEL_CH12_MASK (0x3000000U) +#define APBH_DEVSEL_CH12_SHIFT (24U) +#define APBH_DEVSEL_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH12_SHIFT)) & APBH_DEVSEL_CH12_MASK) +#define APBH_DEVSEL_CH13_MASK (0xC000000U) +#define APBH_DEVSEL_CH13_SHIFT (26U) +#define APBH_DEVSEL_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH13_SHIFT)) & APBH_DEVSEL_CH13_MASK) +#define APBH_DEVSEL_CH14_MASK (0x30000000U) +#define APBH_DEVSEL_CH14_SHIFT (28U) +#define APBH_DEVSEL_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH14_SHIFT)) & APBH_DEVSEL_CH14_MASK) +#define APBH_DEVSEL_CH15_MASK (0xC0000000U) +#define APBH_DEVSEL_CH15_SHIFT (30U) +#define APBH_DEVSEL_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH15_SHIFT)) & APBH_DEVSEL_CH15_MASK) + +/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */ +#define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U) +#define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U) +#define APBH_DMA_BURST_SIZE_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK) +#define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU) +#define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U) +#define APBH_DMA_BURST_SIZE_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK) +#define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U) +#define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U) +#define APBH_DMA_BURST_SIZE_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK) +#define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U) +#define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U) +#define APBH_DMA_BURST_SIZE_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK) +#define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U) +#define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U) +#define APBH_DMA_BURST_SIZE_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK) +#define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U) +#define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U) +#define APBH_DMA_BURST_SIZE_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK) +#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U) +#define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U) +#define APBH_DMA_BURST_SIZE_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK) +#define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U) +#define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U) +#define APBH_DMA_BURST_SIZE_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK) +#define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U) +#define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U) +#define APBH_DMA_BURST_SIZE_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK) +#define APBH_DMA_BURST_SIZE_CH9_MASK (0xC0000U) +#define APBH_DMA_BURST_SIZE_CH9_SHIFT (18U) +#define APBH_DMA_BURST_SIZE_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH9_SHIFT)) & APBH_DMA_BURST_SIZE_CH9_MASK) +#define APBH_DMA_BURST_SIZE_CH10_MASK (0x300000U) +#define APBH_DMA_BURST_SIZE_CH10_SHIFT (20U) +#define APBH_DMA_BURST_SIZE_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH10_SHIFT)) & APBH_DMA_BURST_SIZE_CH10_MASK) +#define APBH_DMA_BURST_SIZE_CH11_MASK (0xC00000U) +#define APBH_DMA_BURST_SIZE_CH11_SHIFT (22U) +#define APBH_DMA_BURST_SIZE_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH11_SHIFT)) & APBH_DMA_BURST_SIZE_CH11_MASK) +#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3000000U) +#define APBH_DMA_BURST_SIZE_CH12_SHIFT (24U) +#define APBH_DMA_BURST_SIZE_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH12_SHIFT)) & APBH_DMA_BURST_SIZE_CH12_MASK) +#define APBH_DMA_BURST_SIZE_CH13_MASK (0xC000000U) +#define APBH_DMA_BURST_SIZE_CH13_SHIFT (26U) +#define APBH_DMA_BURST_SIZE_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH13_SHIFT)) & APBH_DMA_BURST_SIZE_CH13_MASK) +#define APBH_DMA_BURST_SIZE_CH14_MASK (0x30000000U) +#define APBH_DMA_BURST_SIZE_CH14_SHIFT (28U) +#define APBH_DMA_BURST_SIZE_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH14_SHIFT)) & APBH_DMA_BURST_SIZE_CH14_MASK) +#define APBH_DMA_BURST_SIZE_CH15_MASK (0xC0000000U) +#define APBH_DMA_BURST_SIZE_CH15_SHIFT (30U) +#define APBH_DMA_BURST_SIZE_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH15_SHIFT)) & APBH_DMA_BURST_SIZE_CH15_MASK) + +/*! @name DEBUG - AHB to APBH DMA Debug Register */ +#define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U) +#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U) +#define APBH_DEBUG_GPMI_ONE_FIFO(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK) + +/*! @name CH0_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH0_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH0_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH0_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH0_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH0_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH0_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH0_CMD_COMMAND_MASK (0x3U) +#define APBH_CH0_CMD_COMMAND_SHIFT (0U) +#define APBH_CH0_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_COMMAND_SHIFT)) & APBH_CH0_CMD_COMMAND_MASK) +#define APBH_CH0_CMD_CHAIN_MASK (0x4U) +#define APBH_CH0_CMD_CHAIN_SHIFT (2U) +#define APBH_CH0_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CHAIN_SHIFT)) & APBH_CH0_CMD_CHAIN_MASK) +#define APBH_CH0_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH0_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH0_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_IRQONCMPLT_SHIFT)) & APBH_CH0_CMD_IRQONCMPLT_MASK) +#define APBH_CH0_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH0_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH0_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDLOCK_SHIFT)) & APBH_CH0_CMD_NANDLOCK_MASK) +#define APBH_CH0_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH0_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH0_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH0_CMD_NANDWAIT4READY_MASK) +#define APBH_CH0_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH0_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH0_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_SEMAPHORE_SHIFT)) & APBH_CH0_CMD_SEMAPHORE_MASK) +#define APBH_CH0_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH0_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH0_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH0_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH0_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH0_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH0_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH0_CMD_HALTONTERMINATE_MASK) +#define APBH_CH0_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH0_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH0_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CMDWORDS_SHIFT)) & APBH_CH0_CMD_CMDWORDS_MASK) +#define APBH_CH0_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH0_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH0_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_XFER_COUNT_SHIFT)) & APBH_CH0_CMD_XFER_COUNT_MASK) + +/*! @name CH0_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH0_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH0_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH0_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_BAR_ADDRESS_SHIFT)) & APBH_CH0_BAR_ADDRESS_MASK) + +/*! @name CH0_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH0_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH0_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH0_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH0_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH0_SEMA_PHORE_SHIFT (16U) +#define APBH_CH0_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_PHORE_SHIFT)) & APBH_CH0_SEMA_PHORE_MASK) + +/*! @name CH0_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH0_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH0_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH0_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH0_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH0_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH0_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH0_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RSVD1_SHIFT)) & APBH_CH0_DEBUG1_RSVD1_MASK) +#define APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH0_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH0_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH0_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH0_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH0_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_LOCK_SHIFT)) & APBH_CH0_DEBUG1_LOCK_MASK) +#define APBH_CH0_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH0_DEBUG1_READY_SHIFT (26U) +#define APBH_CH0_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_READY_SHIFT)) & APBH_CH0_DEBUG1_READY_MASK) +#define APBH_CH0_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH0_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH0_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_SENSE_SHIFT)) & APBH_CH0_DEBUG1_SENSE_MASK) +#define APBH_CH0_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH0_DEBUG1_END_SHIFT (28U) +#define APBH_CH0_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_END_SHIFT)) & APBH_CH0_DEBUG1_END_MASK) +#define APBH_CH0_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH0_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH0_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_KICK_SHIFT)) & APBH_CH0_DEBUG1_KICK_MASK) +#define APBH_CH0_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH0_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH0_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_BURST_SHIFT)) & APBH_CH0_DEBUG1_BURST_MASK) +#define APBH_CH0_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH0_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH0_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_REQ_SHIFT)) & APBH_CH0_DEBUG1_REQ_MASK) + +/*! @name CH0_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH0_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH0_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH0_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH0_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH0_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH0_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_APB_BYTES_MASK) + +/*! @name CH1_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH1_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH1_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH1_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH1_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH1_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH1_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH1_CMD_COMMAND_MASK (0x3U) +#define APBH_CH1_CMD_COMMAND_SHIFT (0U) +#define APBH_CH1_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_COMMAND_SHIFT)) & APBH_CH1_CMD_COMMAND_MASK) +#define APBH_CH1_CMD_CHAIN_MASK (0x4U) +#define APBH_CH1_CMD_CHAIN_SHIFT (2U) +#define APBH_CH1_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CHAIN_SHIFT)) & APBH_CH1_CMD_CHAIN_MASK) +#define APBH_CH1_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH1_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH1_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_IRQONCMPLT_SHIFT)) & APBH_CH1_CMD_IRQONCMPLT_MASK) +#define APBH_CH1_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH1_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH1_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDLOCK_SHIFT)) & APBH_CH1_CMD_NANDLOCK_MASK) +#define APBH_CH1_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH1_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH1_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH1_CMD_NANDWAIT4READY_MASK) +#define APBH_CH1_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH1_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH1_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_SEMAPHORE_SHIFT)) & APBH_CH1_CMD_SEMAPHORE_MASK) +#define APBH_CH1_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH1_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH1_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH1_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH1_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH1_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH1_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH1_CMD_HALTONTERMINATE_MASK) +#define APBH_CH1_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH1_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH1_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CMDWORDS_SHIFT)) & APBH_CH1_CMD_CMDWORDS_MASK) +#define APBH_CH1_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH1_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH1_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_XFER_COUNT_SHIFT)) & APBH_CH1_CMD_XFER_COUNT_MASK) + +/*! @name CH1_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH1_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH1_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH1_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_BAR_ADDRESS_SHIFT)) & APBH_CH1_BAR_ADDRESS_MASK) + +/*! @name CH1_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH1_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH1_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH1_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH1_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH1_SEMA_PHORE_SHIFT (16U) +#define APBH_CH1_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_PHORE_SHIFT)) & APBH_CH1_SEMA_PHORE_MASK) + +/*! @name CH1_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH1_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH1_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH1_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH1_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH1_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH1_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH1_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RSVD1_SHIFT)) & APBH_CH1_DEBUG1_RSVD1_MASK) +#define APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH1_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH1_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH1_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH1_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH1_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_LOCK_SHIFT)) & APBH_CH1_DEBUG1_LOCK_MASK) +#define APBH_CH1_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH1_DEBUG1_READY_SHIFT (26U) +#define APBH_CH1_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_READY_SHIFT)) & APBH_CH1_DEBUG1_READY_MASK) +#define APBH_CH1_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH1_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH1_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_SENSE_SHIFT)) & APBH_CH1_DEBUG1_SENSE_MASK) +#define APBH_CH1_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH1_DEBUG1_END_SHIFT (28U) +#define APBH_CH1_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_END_SHIFT)) & APBH_CH1_DEBUG1_END_MASK) +#define APBH_CH1_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH1_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH1_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_KICK_SHIFT)) & APBH_CH1_DEBUG1_KICK_MASK) +#define APBH_CH1_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH1_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH1_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_BURST_SHIFT)) & APBH_CH1_DEBUG1_BURST_MASK) +#define APBH_CH1_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH1_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH1_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_REQ_SHIFT)) & APBH_CH1_DEBUG1_REQ_MASK) + +/*! @name CH1_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH1_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH1_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH1_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH1_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH1_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH1_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_APB_BYTES_MASK) + +/*! @name CH2_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH2_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH2_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH2_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH2_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH2_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH2_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH2_CMD_COMMAND_MASK (0x3U) +#define APBH_CH2_CMD_COMMAND_SHIFT (0U) +#define APBH_CH2_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_COMMAND_SHIFT)) & APBH_CH2_CMD_COMMAND_MASK) +#define APBH_CH2_CMD_CHAIN_MASK (0x4U) +#define APBH_CH2_CMD_CHAIN_SHIFT (2U) +#define APBH_CH2_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CHAIN_SHIFT)) & APBH_CH2_CMD_CHAIN_MASK) +#define APBH_CH2_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH2_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH2_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_IRQONCMPLT_SHIFT)) & APBH_CH2_CMD_IRQONCMPLT_MASK) +#define APBH_CH2_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH2_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH2_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDLOCK_SHIFT)) & APBH_CH2_CMD_NANDLOCK_MASK) +#define APBH_CH2_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH2_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH2_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH2_CMD_NANDWAIT4READY_MASK) +#define APBH_CH2_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH2_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH2_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_SEMAPHORE_SHIFT)) & APBH_CH2_CMD_SEMAPHORE_MASK) +#define APBH_CH2_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH2_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH2_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH2_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH2_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH2_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH2_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH2_CMD_HALTONTERMINATE_MASK) +#define APBH_CH2_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH2_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH2_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CMDWORDS_SHIFT)) & APBH_CH2_CMD_CMDWORDS_MASK) +#define APBH_CH2_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH2_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH2_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_XFER_COUNT_SHIFT)) & APBH_CH2_CMD_XFER_COUNT_MASK) + +/*! @name CH2_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH2_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH2_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH2_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_BAR_ADDRESS_SHIFT)) & APBH_CH2_BAR_ADDRESS_MASK) + +/*! @name CH2_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH2_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH2_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH2_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH2_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH2_SEMA_PHORE_SHIFT (16U) +#define APBH_CH2_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_PHORE_SHIFT)) & APBH_CH2_SEMA_PHORE_MASK) + +/*! @name CH2_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH2_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH2_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH2_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH2_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH2_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH2_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH2_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RSVD1_SHIFT)) & APBH_CH2_DEBUG1_RSVD1_MASK) +#define APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH2_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH2_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH2_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH2_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH2_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_LOCK_SHIFT)) & APBH_CH2_DEBUG1_LOCK_MASK) +#define APBH_CH2_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH2_DEBUG1_READY_SHIFT (26U) +#define APBH_CH2_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_READY_SHIFT)) & APBH_CH2_DEBUG1_READY_MASK) +#define APBH_CH2_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH2_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH2_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_SENSE_SHIFT)) & APBH_CH2_DEBUG1_SENSE_MASK) +#define APBH_CH2_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH2_DEBUG1_END_SHIFT (28U) +#define APBH_CH2_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_END_SHIFT)) & APBH_CH2_DEBUG1_END_MASK) +#define APBH_CH2_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH2_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH2_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_KICK_SHIFT)) & APBH_CH2_DEBUG1_KICK_MASK) +#define APBH_CH2_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH2_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH2_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_BURST_SHIFT)) & APBH_CH2_DEBUG1_BURST_MASK) +#define APBH_CH2_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH2_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH2_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_REQ_SHIFT)) & APBH_CH2_DEBUG1_REQ_MASK) + +/*! @name CH2_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH2_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH2_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH2_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH2_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH2_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH2_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_APB_BYTES_MASK) + +/*! @name CH3_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH3_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH3_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH3_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH3_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH3_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH3_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH3_CMD_COMMAND_MASK (0x3U) +#define APBH_CH3_CMD_COMMAND_SHIFT (0U) +#define APBH_CH3_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_COMMAND_SHIFT)) & APBH_CH3_CMD_COMMAND_MASK) +#define APBH_CH3_CMD_CHAIN_MASK (0x4U) +#define APBH_CH3_CMD_CHAIN_SHIFT (2U) +#define APBH_CH3_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CHAIN_SHIFT)) & APBH_CH3_CMD_CHAIN_MASK) +#define APBH_CH3_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH3_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH3_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_IRQONCMPLT_SHIFT)) & APBH_CH3_CMD_IRQONCMPLT_MASK) +#define APBH_CH3_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH3_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH3_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDLOCK_SHIFT)) & APBH_CH3_CMD_NANDLOCK_MASK) +#define APBH_CH3_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH3_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH3_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH3_CMD_NANDWAIT4READY_MASK) +#define APBH_CH3_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH3_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH3_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_SEMAPHORE_SHIFT)) & APBH_CH3_CMD_SEMAPHORE_MASK) +#define APBH_CH3_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH3_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH3_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH3_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH3_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH3_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH3_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH3_CMD_HALTONTERMINATE_MASK) +#define APBH_CH3_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH3_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH3_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CMDWORDS_SHIFT)) & APBH_CH3_CMD_CMDWORDS_MASK) +#define APBH_CH3_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH3_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH3_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_XFER_COUNT_SHIFT)) & APBH_CH3_CMD_XFER_COUNT_MASK) + +/*! @name CH3_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH3_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH3_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH3_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_BAR_ADDRESS_SHIFT)) & APBH_CH3_BAR_ADDRESS_MASK) + +/*! @name CH3_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH3_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH3_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH3_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH3_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH3_SEMA_PHORE_SHIFT (16U) +#define APBH_CH3_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_PHORE_SHIFT)) & APBH_CH3_SEMA_PHORE_MASK) + +/*! @name CH3_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH3_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH3_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH3_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH3_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH3_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH3_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH3_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RSVD1_SHIFT)) & APBH_CH3_DEBUG1_RSVD1_MASK) +#define APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH3_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH3_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH3_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH3_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH3_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_LOCK_SHIFT)) & APBH_CH3_DEBUG1_LOCK_MASK) +#define APBH_CH3_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH3_DEBUG1_READY_SHIFT (26U) +#define APBH_CH3_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_READY_SHIFT)) & APBH_CH3_DEBUG1_READY_MASK) +#define APBH_CH3_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH3_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH3_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_SENSE_SHIFT)) & APBH_CH3_DEBUG1_SENSE_MASK) +#define APBH_CH3_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH3_DEBUG1_END_SHIFT (28U) +#define APBH_CH3_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_END_SHIFT)) & APBH_CH3_DEBUG1_END_MASK) +#define APBH_CH3_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH3_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH3_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_KICK_SHIFT)) & APBH_CH3_DEBUG1_KICK_MASK) +#define APBH_CH3_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH3_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH3_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_BURST_SHIFT)) & APBH_CH3_DEBUG1_BURST_MASK) +#define APBH_CH3_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH3_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH3_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_REQ_SHIFT)) & APBH_CH3_DEBUG1_REQ_MASK) + +/*! @name CH3_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH3_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH3_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH3_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH3_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH3_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH3_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_APB_BYTES_MASK) + +/*! @name CH4_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH4_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH4_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH4_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH4_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH4_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH4_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH4_CMD_COMMAND_MASK (0x3U) +#define APBH_CH4_CMD_COMMAND_SHIFT (0U) +#define APBH_CH4_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_COMMAND_SHIFT)) & APBH_CH4_CMD_COMMAND_MASK) +#define APBH_CH4_CMD_CHAIN_MASK (0x4U) +#define APBH_CH4_CMD_CHAIN_SHIFT (2U) +#define APBH_CH4_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CHAIN_SHIFT)) & APBH_CH4_CMD_CHAIN_MASK) +#define APBH_CH4_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH4_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH4_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_IRQONCMPLT_SHIFT)) & APBH_CH4_CMD_IRQONCMPLT_MASK) +#define APBH_CH4_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH4_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH4_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDLOCK_SHIFT)) & APBH_CH4_CMD_NANDLOCK_MASK) +#define APBH_CH4_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH4_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH4_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH4_CMD_NANDWAIT4READY_MASK) +#define APBH_CH4_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH4_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH4_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_SEMAPHORE_SHIFT)) & APBH_CH4_CMD_SEMAPHORE_MASK) +#define APBH_CH4_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH4_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH4_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH4_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH4_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH4_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH4_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH4_CMD_HALTONTERMINATE_MASK) +#define APBH_CH4_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH4_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH4_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CMDWORDS_SHIFT)) & APBH_CH4_CMD_CMDWORDS_MASK) +#define APBH_CH4_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH4_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH4_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_XFER_COUNT_SHIFT)) & APBH_CH4_CMD_XFER_COUNT_MASK) + +/*! @name CH4_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH4_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH4_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH4_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_BAR_ADDRESS_SHIFT)) & APBH_CH4_BAR_ADDRESS_MASK) + +/*! @name CH4_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH4_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH4_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH4_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH4_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH4_SEMA_PHORE_SHIFT (16U) +#define APBH_CH4_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_PHORE_SHIFT)) & APBH_CH4_SEMA_PHORE_MASK) + +/*! @name CH4_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH4_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH4_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH4_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH4_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH4_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH4_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH4_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RSVD1_SHIFT)) & APBH_CH4_DEBUG1_RSVD1_MASK) +#define APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH4_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH4_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH4_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH4_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH4_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_LOCK_SHIFT)) & APBH_CH4_DEBUG1_LOCK_MASK) +#define APBH_CH4_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH4_DEBUG1_READY_SHIFT (26U) +#define APBH_CH4_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_READY_SHIFT)) & APBH_CH4_DEBUG1_READY_MASK) +#define APBH_CH4_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH4_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH4_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_SENSE_SHIFT)) & APBH_CH4_DEBUG1_SENSE_MASK) +#define APBH_CH4_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH4_DEBUG1_END_SHIFT (28U) +#define APBH_CH4_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_END_SHIFT)) & APBH_CH4_DEBUG1_END_MASK) +#define APBH_CH4_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH4_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH4_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_KICK_SHIFT)) & APBH_CH4_DEBUG1_KICK_MASK) +#define APBH_CH4_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH4_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH4_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_BURST_SHIFT)) & APBH_CH4_DEBUG1_BURST_MASK) +#define APBH_CH4_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH4_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH4_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_REQ_SHIFT)) & APBH_CH4_DEBUG1_REQ_MASK) + +/*! @name CH4_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH4_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH4_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH4_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH4_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH4_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH4_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_APB_BYTES_MASK) + +/*! @name CH5_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH5_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH5_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH5_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH5_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH5_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH5_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH5_CMD_COMMAND_MASK (0x3U) +#define APBH_CH5_CMD_COMMAND_SHIFT (0U) +#define APBH_CH5_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_COMMAND_SHIFT)) & APBH_CH5_CMD_COMMAND_MASK) +#define APBH_CH5_CMD_CHAIN_MASK (0x4U) +#define APBH_CH5_CMD_CHAIN_SHIFT (2U) +#define APBH_CH5_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CHAIN_SHIFT)) & APBH_CH5_CMD_CHAIN_MASK) +#define APBH_CH5_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH5_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH5_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_IRQONCMPLT_SHIFT)) & APBH_CH5_CMD_IRQONCMPLT_MASK) +#define APBH_CH5_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH5_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH5_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK) +#define APBH_CH5_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH5_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH5_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH5_CMD_NANDWAIT4READY_MASK) +#define APBH_CH5_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH5_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH5_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_SEMAPHORE_SHIFT)) & APBH_CH5_CMD_SEMAPHORE_MASK) +#define APBH_CH5_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH5_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH5_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH5_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH5_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH5_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH5_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH5_CMD_HALTONTERMINATE_MASK) +#define APBH_CH5_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH5_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH5_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CMDWORDS_SHIFT)) & APBH_CH5_CMD_CMDWORDS_MASK) +#define APBH_CH5_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH5_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH5_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_XFER_COUNT_SHIFT)) & APBH_CH5_CMD_XFER_COUNT_MASK) + +/*! @name CH5_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH5_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH5_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH5_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_BAR_ADDRESS_SHIFT)) & APBH_CH5_BAR_ADDRESS_MASK) + +/*! @name CH5_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH5_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH5_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH5_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH5_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH5_SEMA_PHORE_SHIFT (16U) +#define APBH_CH5_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_PHORE_SHIFT)) & APBH_CH5_SEMA_PHORE_MASK) + +/*! @name CH5_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH5_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH5_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH5_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH5_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH5_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH5_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH5_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RSVD1_SHIFT)) & APBH_CH5_DEBUG1_RSVD1_MASK) +#define APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH5_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH5_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH5_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH5_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH5_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_LOCK_SHIFT)) & APBH_CH5_DEBUG1_LOCK_MASK) +#define APBH_CH5_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH5_DEBUG1_READY_SHIFT (26U) +#define APBH_CH5_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_READY_SHIFT)) & APBH_CH5_DEBUG1_READY_MASK) +#define APBH_CH5_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH5_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH5_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_SENSE_SHIFT)) & APBH_CH5_DEBUG1_SENSE_MASK) +#define APBH_CH5_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH5_DEBUG1_END_SHIFT (28U) +#define APBH_CH5_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_END_SHIFT)) & APBH_CH5_DEBUG1_END_MASK) +#define APBH_CH5_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH5_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH5_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_KICK_SHIFT)) & APBH_CH5_DEBUG1_KICK_MASK) +#define APBH_CH5_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH5_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH5_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_BURST_SHIFT)) & APBH_CH5_DEBUG1_BURST_MASK) +#define APBH_CH5_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH5_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH5_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_REQ_SHIFT)) & APBH_CH5_DEBUG1_REQ_MASK) + +/*! @name CH5_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH5_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH5_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH5_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH5_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH5_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH5_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_APB_BYTES_MASK) + +/*! @name CH6_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH6_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH6_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH6_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH6_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH6_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH6_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH6_CMD_COMMAND_MASK (0x3U) +#define APBH_CH6_CMD_COMMAND_SHIFT (0U) +#define APBH_CH6_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_COMMAND_SHIFT)) & APBH_CH6_CMD_COMMAND_MASK) +#define APBH_CH6_CMD_CHAIN_MASK (0x4U) +#define APBH_CH6_CMD_CHAIN_SHIFT (2U) +#define APBH_CH6_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CHAIN_SHIFT)) & APBH_CH6_CMD_CHAIN_MASK) +#define APBH_CH6_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH6_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH6_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_IRQONCMPLT_SHIFT)) & APBH_CH6_CMD_IRQONCMPLT_MASK) +#define APBH_CH6_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH6_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH6_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDLOCK_SHIFT)) & APBH_CH6_CMD_NANDLOCK_MASK) +#define APBH_CH6_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH6_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH6_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH6_CMD_NANDWAIT4READY_MASK) +#define APBH_CH6_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH6_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH6_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_SEMAPHORE_SHIFT)) & APBH_CH6_CMD_SEMAPHORE_MASK) +#define APBH_CH6_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH6_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH6_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH6_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH6_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH6_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH6_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH6_CMD_HALTONTERMINATE_MASK) +#define APBH_CH6_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH6_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH6_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CMDWORDS_SHIFT)) & APBH_CH6_CMD_CMDWORDS_MASK) +#define APBH_CH6_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH6_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH6_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_XFER_COUNT_SHIFT)) & APBH_CH6_CMD_XFER_COUNT_MASK) + +/*! @name CH6_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH6_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH6_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH6_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_BAR_ADDRESS_SHIFT)) & APBH_CH6_BAR_ADDRESS_MASK) + +/*! @name CH6_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH6_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH6_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH6_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH6_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH6_SEMA_PHORE_SHIFT (16U) +#define APBH_CH6_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_PHORE_SHIFT)) & APBH_CH6_SEMA_PHORE_MASK) + +/*! @name CH6_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH6_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH6_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH6_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH6_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH6_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH6_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH6_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RSVD1_SHIFT)) & APBH_CH6_DEBUG1_RSVD1_MASK) +#define APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH6_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH6_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH6_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH6_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH6_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_LOCK_SHIFT)) & APBH_CH6_DEBUG1_LOCK_MASK) +#define APBH_CH6_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH6_DEBUG1_READY_SHIFT (26U) +#define APBH_CH6_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_READY_SHIFT)) & APBH_CH6_DEBUG1_READY_MASK) +#define APBH_CH6_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH6_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH6_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_SENSE_SHIFT)) & APBH_CH6_DEBUG1_SENSE_MASK) +#define APBH_CH6_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH6_DEBUG1_END_SHIFT (28U) +#define APBH_CH6_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_END_SHIFT)) & APBH_CH6_DEBUG1_END_MASK) +#define APBH_CH6_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH6_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH6_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_KICK_SHIFT)) & APBH_CH6_DEBUG1_KICK_MASK) +#define APBH_CH6_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH6_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH6_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_BURST_SHIFT)) & APBH_CH6_DEBUG1_BURST_MASK) +#define APBH_CH6_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH6_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH6_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_REQ_SHIFT)) & APBH_CH6_DEBUG1_REQ_MASK) + +/*! @name CH6_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH6_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH6_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH6_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH6_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH6_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH6_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_APB_BYTES_MASK) + +/*! @name CH7_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH7_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH7_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH7_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH7_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH7_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH7_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH7_CMD_COMMAND_MASK (0x3U) +#define APBH_CH7_CMD_COMMAND_SHIFT (0U) +#define APBH_CH7_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_COMMAND_SHIFT)) & APBH_CH7_CMD_COMMAND_MASK) +#define APBH_CH7_CMD_CHAIN_MASK (0x4U) +#define APBH_CH7_CMD_CHAIN_SHIFT (2U) +#define APBH_CH7_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CHAIN_SHIFT)) & APBH_CH7_CMD_CHAIN_MASK) +#define APBH_CH7_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH7_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH7_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_IRQONCMPLT_SHIFT)) & APBH_CH7_CMD_IRQONCMPLT_MASK) +#define APBH_CH7_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH7_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH7_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_NANDLOCK_SHIFT)) & APBH_CH7_CMD_NANDLOCK_MASK) +#define APBH_CH7_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH7_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH7_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH7_CMD_NANDWAIT4READY_MASK) +#define APBH_CH7_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH7_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH7_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_SEMAPHORE_SHIFT)) & APBH_CH7_CMD_SEMAPHORE_MASK) +#define APBH_CH7_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH7_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH7_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH7_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH7_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH7_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH7_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH7_CMD_HALTONTERMINATE_MASK) +#define APBH_CH7_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH7_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH7_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CMDWORDS_SHIFT)) & APBH_CH7_CMD_CMDWORDS_MASK) +#define APBH_CH7_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH7_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH7_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_XFER_COUNT_SHIFT)) & APBH_CH7_CMD_XFER_COUNT_MASK) + +/*! @name CH7_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH7_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH7_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH7_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_BAR_ADDRESS_SHIFT)) & APBH_CH7_BAR_ADDRESS_MASK) + +/*! @name CH7_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH7_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH7_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH7_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH7_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH7_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH7_SEMA_PHORE_SHIFT (16U) +#define APBH_CH7_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_SEMA_PHORE_SHIFT)) & APBH_CH7_SEMA_PHORE_MASK) + +/*! @name CH7_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH7_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH7_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH7_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH7_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH7_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH7_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH7_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RSVD1_SHIFT)) & APBH_CH7_DEBUG1_RSVD1_MASK) +#define APBH_CH7_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH7_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH7_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH7_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH7_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH7_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH7_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH7_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH7_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH7_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH7_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH7_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH7_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH7_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_LOCK_SHIFT)) & APBH_CH7_DEBUG1_LOCK_MASK) +#define APBH_CH7_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH7_DEBUG1_READY_SHIFT (26U) +#define APBH_CH7_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_READY_SHIFT)) & APBH_CH7_DEBUG1_READY_MASK) +#define APBH_CH7_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH7_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH7_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_SENSE_SHIFT)) & APBH_CH7_DEBUG1_SENSE_MASK) +#define APBH_CH7_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH7_DEBUG1_END_SHIFT (28U) +#define APBH_CH7_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_END_SHIFT)) & APBH_CH7_DEBUG1_END_MASK) +#define APBH_CH7_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH7_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH7_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_KICK_SHIFT)) & APBH_CH7_DEBUG1_KICK_MASK) +#define APBH_CH7_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH7_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH7_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_BURST_SHIFT)) & APBH_CH7_DEBUG1_BURST_MASK) +#define APBH_CH7_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH7_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH7_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_REQ_SHIFT)) & APBH_CH7_DEBUG1_REQ_MASK) + +/*! @name CH7_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH7_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH7_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH7_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH7_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH7_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH7_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH7_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH7_DEBUG2_APB_BYTES_MASK) + +/*! @name CH8_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH8_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH8_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH8_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH8_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH8_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH8_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH8_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH8_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH8_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH8_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH8_CMD_COMMAND_MASK (0x3U) +#define APBH_CH8_CMD_COMMAND_SHIFT (0U) +#define APBH_CH8_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_COMMAND_SHIFT)) & APBH_CH8_CMD_COMMAND_MASK) +#define APBH_CH8_CMD_CHAIN_MASK (0x4U) +#define APBH_CH8_CMD_CHAIN_SHIFT (2U) +#define APBH_CH8_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_CHAIN_SHIFT)) & APBH_CH8_CMD_CHAIN_MASK) +#define APBH_CH8_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH8_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH8_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_IRQONCMPLT_SHIFT)) & APBH_CH8_CMD_IRQONCMPLT_MASK) +#define APBH_CH8_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH8_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH8_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_NANDLOCK_SHIFT)) & APBH_CH8_CMD_NANDLOCK_MASK) +#define APBH_CH8_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH8_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH8_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH8_CMD_NANDWAIT4READY_MASK) +#define APBH_CH8_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH8_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH8_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_SEMAPHORE_SHIFT)) & APBH_CH8_CMD_SEMAPHORE_MASK) +#define APBH_CH8_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH8_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH8_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH8_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH8_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH8_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH8_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH8_CMD_HALTONTERMINATE_MASK) +#define APBH_CH8_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH8_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH8_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_CMDWORDS_SHIFT)) & APBH_CH8_CMD_CMDWORDS_MASK) +#define APBH_CH8_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH8_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH8_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_XFER_COUNT_SHIFT)) & APBH_CH8_CMD_XFER_COUNT_MASK) + +/*! @name CH8_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH8_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH8_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH8_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_BAR_ADDRESS_SHIFT)) & APBH_CH8_BAR_ADDRESS_MASK) + +/*! @name CH8_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH8_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH8_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH8_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH8_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH8_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH8_SEMA_PHORE_SHIFT (16U) +#define APBH_CH8_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_SEMA_PHORE_SHIFT)) & APBH_CH8_SEMA_PHORE_MASK) + +/*! @name CH8_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH8_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH8_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH8_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH8_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH8_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH8_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH8_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RSVD1_SHIFT)) & APBH_CH8_DEBUG1_RSVD1_MASK) +#define APBH_CH8_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH8_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH8_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH8_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH8_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH8_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH8_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH8_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH8_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH8_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH8_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH8_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH8_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH8_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_LOCK_SHIFT)) & APBH_CH8_DEBUG1_LOCK_MASK) +#define APBH_CH8_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH8_DEBUG1_READY_SHIFT (26U) +#define APBH_CH8_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_READY_SHIFT)) & APBH_CH8_DEBUG1_READY_MASK) +#define APBH_CH8_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH8_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH8_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_SENSE_SHIFT)) & APBH_CH8_DEBUG1_SENSE_MASK) +#define APBH_CH8_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH8_DEBUG1_END_SHIFT (28U) +#define APBH_CH8_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_END_SHIFT)) & APBH_CH8_DEBUG1_END_MASK) +#define APBH_CH8_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH8_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH8_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_KICK_SHIFT)) & APBH_CH8_DEBUG1_KICK_MASK) +#define APBH_CH8_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH8_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH8_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_BURST_SHIFT)) & APBH_CH8_DEBUG1_BURST_MASK) +#define APBH_CH8_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH8_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH8_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_REQ_SHIFT)) & APBH_CH8_DEBUG1_REQ_MASK) + +/*! @name CH8_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH8_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH8_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH8_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH8_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH8_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH8_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH8_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH8_DEBUG2_APB_BYTES_MASK) + +/*! @name CH9_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH9_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH9_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH9_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH9_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH9_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH9_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH9_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH9_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH9_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH9_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH9_CMD_COMMAND_MASK (0x3U) +#define APBH_CH9_CMD_COMMAND_SHIFT (0U) +#define APBH_CH9_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_COMMAND_SHIFT)) & APBH_CH9_CMD_COMMAND_MASK) +#define APBH_CH9_CMD_CHAIN_MASK (0x4U) +#define APBH_CH9_CMD_CHAIN_SHIFT (2U) +#define APBH_CH9_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_CHAIN_SHIFT)) & APBH_CH9_CMD_CHAIN_MASK) +#define APBH_CH9_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH9_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH9_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_IRQONCMPLT_SHIFT)) & APBH_CH9_CMD_IRQONCMPLT_MASK) +#define APBH_CH9_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH9_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH9_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_NANDLOCK_SHIFT)) & APBH_CH9_CMD_NANDLOCK_MASK) +#define APBH_CH9_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH9_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH9_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH9_CMD_NANDWAIT4READY_MASK) +#define APBH_CH9_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH9_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH9_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_SEMAPHORE_SHIFT)) & APBH_CH9_CMD_SEMAPHORE_MASK) +#define APBH_CH9_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH9_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH9_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH9_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH9_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH9_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH9_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH9_CMD_HALTONTERMINATE_MASK) +#define APBH_CH9_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH9_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH9_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_CMDWORDS_SHIFT)) & APBH_CH9_CMD_CMDWORDS_MASK) +#define APBH_CH9_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH9_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH9_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_XFER_COUNT_SHIFT)) & APBH_CH9_CMD_XFER_COUNT_MASK) + +/*! @name CH9_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH9_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH9_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH9_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_BAR_ADDRESS_SHIFT)) & APBH_CH9_BAR_ADDRESS_MASK) + +/*! @name CH9_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH9_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH9_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH9_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH9_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH9_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH9_SEMA_PHORE_SHIFT (16U) +#define APBH_CH9_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_SEMA_PHORE_SHIFT)) & APBH_CH9_SEMA_PHORE_MASK) + +/*! @name CH9_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH9_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH9_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH9_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH9_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH9_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH9_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH9_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RSVD1_SHIFT)) & APBH_CH9_DEBUG1_RSVD1_MASK) +#define APBH_CH9_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH9_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH9_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH9_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH9_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH9_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH9_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH9_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH9_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH9_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH9_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH9_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH9_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH9_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_LOCK_SHIFT)) & APBH_CH9_DEBUG1_LOCK_MASK) +#define APBH_CH9_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH9_DEBUG1_READY_SHIFT (26U) +#define APBH_CH9_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_READY_SHIFT)) & APBH_CH9_DEBUG1_READY_MASK) +#define APBH_CH9_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH9_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH9_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_SENSE_SHIFT)) & APBH_CH9_DEBUG1_SENSE_MASK) +#define APBH_CH9_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH9_DEBUG1_END_SHIFT (28U) +#define APBH_CH9_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_END_SHIFT)) & APBH_CH9_DEBUG1_END_MASK) +#define APBH_CH9_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH9_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH9_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_KICK_SHIFT)) & APBH_CH9_DEBUG1_KICK_MASK) +#define APBH_CH9_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH9_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH9_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_BURST_SHIFT)) & APBH_CH9_DEBUG1_BURST_MASK) +#define APBH_CH9_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH9_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH9_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_REQ_SHIFT)) & APBH_CH9_DEBUG1_REQ_MASK) + +/*! @name CH9_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH9_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH9_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH9_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH9_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH9_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH9_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH9_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH9_DEBUG2_APB_BYTES_MASK) + +/*! @name CH10_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH10_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH10_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH10_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH10_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH10_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH10_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH10_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH10_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH10_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH10_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH10_CMD_COMMAND_MASK (0x3U) +#define APBH_CH10_CMD_COMMAND_SHIFT (0U) +#define APBH_CH10_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_COMMAND_SHIFT)) & APBH_CH10_CMD_COMMAND_MASK) +#define APBH_CH10_CMD_CHAIN_MASK (0x4U) +#define APBH_CH10_CMD_CHAIN_SHIFT (2U) +#define APBH_CH10_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_CHAIN_SHIFT)) & APBH_CH10_CMD_CHAIN_MASK) +#define APBH_CH10_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH10_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH10_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_IRQONCMPLT_SHIFT)) & APBH_CH10_CMD_IRQONCMPLT_MASK) +#define APBH_CH10_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH10_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH10_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_NANDLOCK_SHIFT)) & APBH_CH10_CMD_NANDLOCK_MASK) +#define APBH_CH10_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH10_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH10_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH10_CMD_NANDWAIT4READY_MASK) +#define APBH_CH10_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH10_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH10_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_SEMAPHORE_SHIFT)) & APBH_CH10_CMD_SEMAPHORE_MASK) +#define APBH_CH10_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH10_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH10_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH10_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH10_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH10_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH10_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH10_CMD_HALTONTERMINATE_MASK) +#define APBH_CH10_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH10_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH10_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_CMDWORDS_SHIFT)) & APBH_CH10_CMD_CMDWORDS_MASK) +#define APBH_CH10_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH10_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH10_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_XFER_COUNT_SHIFT)) & APBH_CH10_CMD_XFER_COUNT_MASK) + +/*! @name CH10_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH10_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH10_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH10_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_BAR_ADDRESS_SHIFT)) & APBH_CH10_BAR_ADDRESS_MASK) + +/*! @name CH10_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH10_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH10_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH10_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH10_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH10_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH10_SEMA_PHORE_SHIFT (16U) +#define APBH_CH10_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_SEMA_PHORE_SHIFT)) & APBH_CH10_SEMA_PHORE_MASK) + +/*! @name CH10_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH10_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH10_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH10_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH10_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH10_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH10_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH10_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RSVD1_SHIFT)) & APBH_CH10_DEBUG1_RSVD1_MASK) +#define APBH_CH10_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH10_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH10_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH10_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH10_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH10_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH10_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH10_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH10_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH10_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH10_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH10_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH10_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH10_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_LOCK_SHIFT)) & APBH_CH10_DEBUG1_LOCK_MASK) +#define APBH_CH10_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH10_DEBUG1_READY_SHIFT (26U) +#define APBH_CH10_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_READY_SHIFT)) & APBH_CH10_DEBUG1_READY_MASK) +#define APBH_CH10_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH10_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH10_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_SENSE_SHIFT)) & APBH_CH10_DEBUG1_SENSE_MASK) +#define APBH_CH10_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH10_DEBUG1_END_SHIFT (28U) +#define APBH_CH10_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_END_SHIFT)) & APBH_CH10_DEBUG1_END_MASK) +#define APBH_CH10_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH10_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH10_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_KICK_SHIFT)) & APBH_CH10_DEBUG1_KICK_MASK) +#define APBH_CH10_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH10_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH10_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_BURST_SHIFT)) & APBH_CH10_DEBUG1_BURST_MASK) +#define APBH_CH10_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH10_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH10_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_REQ_SHIFT)) & APBH_CH10_DEBUG1_REQ_MASK) + +/*! @name CH10_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH10_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH10_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH10_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH10_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH10_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH10_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH10_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH10_DEBUG2_APB_BYTES_MASK) + +/*! @name CH11_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH11_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH11_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH11_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH11_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH11_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH11_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH11_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH11_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH11_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH11_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH11_CMD_COMMAND_MASK (0x3U) +#define APBH_CH11_CMD_COMMAND_SHIFT (0U) +#define APBH_CH11_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_COMMAND_SHIFT)) & APBH_CH11_CMD_COMMAND_MASK) +#define APBH_CH11_CMD_CHAIN_MASK (0x4U) +#define APBH_CH11_CMD_CHAIN_SHIFT (2U) +#define APBH_CH11_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_CHAIN_SHIFT)) & APBH_CH11_CMD_CHAIN_MASK) +#define APBH_CH11_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH11_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH11_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_IRQONCMPLT_SHIFT)) & APBH_CH11_CMD_IRQONCMPLT_MASK) +#define APBH_CH11_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH11_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH11_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_NANDLOCK_SHIFT)) & APBH_CH11_CMD_NANDLOCK_MASK) +#define APBH_CH11_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH11_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH11_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH11_CMD_NANDWAIT4READY_MASK) +#define APBH_CH11_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH11_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH11_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_SEMAPHORE_SHIFT)) & APBH_CH11_CMD_SEMAPHORE_MASK) +#define APBH_CH11_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH11_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH11_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH11_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH11_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH11_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH11_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH11_CMD_HALTONTERMINATE_MASK) +#define APBH_CH11_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH11_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH11_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_CMDWORDS_SHIFT)) & APBH_CH11_CMD_CMDWORDS_MASK) +#define APBH_CH11_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH11_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH11_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_XFER_COUNT_SHIFT)) & APBH_CH11_CMD_XFER_COUNT_MASK) + +/*! @name CH11_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH11_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH11_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH11_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_BAR_ADDRESS_SHIFT)) & APBH_CH11_BAR_ADDRESS_MASK) + +/*! @name CH11_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH11_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH11_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH11_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH11_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH11_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH11_SEMA_PHORE_SHIFT (16U) +#define APBH_CH11_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_SEMA_PHORE_SHIFT)) & APBH_CH11_SEMA_PHORE_MASK) + +/*! @name CH11_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH11_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH11_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH11_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH11_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH11_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH11_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH11_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RSVD1_SHIFT)) & APBH_CH11_DEBUG1_RSVD1_MASK) +#define APBH_CH11_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH11_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH11_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH11_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH11_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH11_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH11_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH11_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH11_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH11_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH11_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH11_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH11_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH11_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_LOCK_SHIFT)) & APBH_CH11_DEBUG1_LOCK_MASK) +#define APBH_CH11_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH11_DEBUG1_READY_SHIFT (26U) +#define APBH_CH11_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_READY_SHIFT)) & APBH_CH11_DEBUG1_READY_MASK) +#define APBH_CH11_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH11_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH11_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_SENSE_SHIFT)) & APBH_CH11_DEBUG1_SENSE_MASK) +#define APBH_CH11_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH11_DEBUG1_END_SHIFT (28U) +#define APBH_CH11_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_END_SHIFT)) & APBH_CH11_DEBUG1_END_MASK) +#define APBH_CH11_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH11_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH11_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_KICK_SHIFT)) & APBH_CH11_DEBUG1_KICK_MASK) +#define APBH_CH11_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH11_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH11_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_BURST_SHIFT)) & APBH_CH11_DEBUG1_BURST_MASK) +#define APBH_CH11_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH11_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH11_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_REQ_SHIFT)) & APBH_CH11_DEBUG1_REQ_MASK) + +/*! @name CH11_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH11_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH11_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH11_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH11_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH11_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH11_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH11_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH11_DEBUG2_APB_BYTES_MASK) + +/*! @name CH12_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH12_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH12_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH12_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH12_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH12_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH12_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH12_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH12_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH12_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH12_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH12_CMD_COMMAND_MASK (0x3U) +#define APBH_CH12_CMD_COMMAND_SHIFT (0U) +#define APBH_CH12_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_COMMAND_SHIFT)) & APBH_CH12_CMD_COMMAND_MASK) +#define APBH_CH12_CMD_CHAIN_MASK (0x4U) +#define APBH_CH12_CMD_CHAIN_SHIFT (2U) +#define APBH_CH12_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_CHAIN_SHIFT)) & APBH_CH12_CMD_CHAIN_MASK) +#define APBH_CH12_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH12_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH12_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_IRQONCMPLT_SHIFT)) & APBH_CH12_CMD_IRQONCMPLT_MASK) +#define APBH_CH12_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH12_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH12_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_NANDLOCK_SHIFT)) & APBH_CH12_CMD_NANDLOCK_MASK) +#define APBH_CH12_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH12_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH12_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH12_CMD_NANDWAIT4READY_MASK) +#define APBH_CH12_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH12_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH12_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_SEMAPHORE_SHIFT)) & APBH_CH12_CMD_SEMAPHORE_MASK) +#define APBH_CH12_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH12_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH12_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH12_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH12_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH12_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH12_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH12_CMD_HALTONTERMINATE_MASK) +#define APBH_CH12_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH12_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH12_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_CMDWORDS_SHIFT)) & APBH_CH12_CMD_CMDWORDS_MASK) +#define APBH_CH12_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH12_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH12_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_XFER_COUNT_SHIFT)) & APBH_CH12_CMD_XFER_COUNT_MASK) + +/*! @name CH12_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH12_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH12_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH12_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_BAR_ADDRESS_SHIFT)) & APBH_CH12_BAR_ADDRESS_MASK) + +/*! @name CH12_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH12_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH12_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH12_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH12_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH12_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH12_SEMA_PHORE_SHIFT (16U) +#define APBH_CH12_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_SEMA_PHORE_SHIFT)) & APBH_CH12_SEMA_PHORE_MASK) + +/*! @name CH12_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH12_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH12_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH12_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH12_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH12_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH12_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH12_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RSVD1_SHIFT)) & APBH_CH12_DEBUG1_RSVD1_MASK) +#define APBH_CH12_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH12_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH12_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH12_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH12_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH12_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH12_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH12_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH12_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH12_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH12_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH12_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH12_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH12_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_LOCK_SHIFT)) & APBH_CH12_DEBUG1_LOCK_MASK) +#define APBH_CH12_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH12_DEBUG1_READY_SHIFT (26U) +#define APBH_CH12_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_READY_SHIFT)) & APBH_CH12_DEBUG1_READY_MASK) +#define APBH_CH12_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH12_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH12_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_SENSE_SHIFT)) & APBH_CH12_DEBUG1_SENSE_MASK) +#define APBH_CH12_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH12_DEBUG1_END_SHIFT (28U) +#define APBH_CH12_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_END_SHIFT)) & APBH_CH12_DEBUG1_END_MASK) +#define APBH_CH12_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH12_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH12_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_KICK_SHIFT)) & APBH_CH12_DEBUG1_KICK_MASK) +#define APBH_CH12_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH12_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH12_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_BURST_SHIFT)) & APBH_CH12_DEBUG1_BURST_MASK) +#define APBH_CH12_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH12_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH12_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_REQ_SHIFT)) & APBH_CH12_DEBUG1_REQ_MASK) + +/*! @name CH12_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH12_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH12_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH12_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH12_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH12_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH12_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH12_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH12_DEBUG2_APB_BYTES_MASK) + +/*! @name CH13_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH13_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH13_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH13_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH13_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH13_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH13_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH13_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH13_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH13_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH13_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH13_CMD_COMMAND_MASK (0x3U) +#define APBH_CH13_CMD_COMMAND_SHIFT (0U) +#define APBH_CH13_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_COMMAND_SHIFT)) & APBH_CH13_CMD_COMMAND_MASK) +#define APBH_CH13_CMD_CHAIN_MASK (0x4U) +#define APBH_CH13_CMD_CHAIN_SHIFT (2U) +#define APBH_CH13_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_CHAIN_SHIFT)) & APBH_CH13_CMD_CHAIN_MASK) +#define APBH_CH13_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH13_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH13_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_IRQONCMPLT_SHIFT)) & APBH_CH13_CMD_IRQONCMPLT_MASK) +#define APBH_CH13_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH13_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH13_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_NANDLOCK_SHIFT)) & APBH_CH13_CMD_NANDLOCK_MASK) +#define APBH_CH13_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH13_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH13_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH13_CMD_NANDWAIT4READY_MASK) +#define APBH_CH13_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH13_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH13_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_SEMAPHORE_SHIFT)) & APBH_CH13_CMD_SEMAPHORE_MASK) +#define APBH_CH13_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH13_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH13_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH13_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH13_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH13_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH13_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH13_CMD_HALTONTERMINATE_MASK) +#define APBH_CH13_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH13_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH13_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_CMDWORDS_SHIFT)) & APBH_CH13_CMD_CMDWORDS_MASK) +#define APBH_CH13_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH13_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH13_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_XFER_COUNT_SHIFT)) & APBH_CH13_CMD_XFER_COUNT_MASK) + +/*! @name CH13_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH13_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH13_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH13_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_BAR_ADDRESS_SHIFT)) & APBH_CH13_BAR_ADDRESS_MASK) + +/*! @name CH13_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH13_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH13_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH13_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH13_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH13_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH13_SEMA_PHORE_SHIFT (16U) +#define APBH_CH13_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_SEMA_PHORE_SHIFT)) & APBH_CH13_SEMA_PHORE_MASK) + +/*! @name CH13_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH13_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH13_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH13_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH13_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH13_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH13_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH13_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RSVD1_SHIFT)) & APBH_CH13_DEBUG1_RSVD1_MASK) +#define APBH_CH13_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH13_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH13_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH13_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH13_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH13_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH13_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH13_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH13_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH13_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH13_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH13_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH13_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH13_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_LOCK_SHIFT)) & APBH_CH13_DEBUG1_LOCK_MASK) +#define APBH_CH13_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH13_DEBUG1_READY_SHIFT (26U) +#define APBH_CH13_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_READY_SHIFT)) & APBH_CH13_DEBUG1_READY_MASK) +#define APBH_CH13_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH13_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH13_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_SENSE_SHIFT)) & APBH_CH13_DEBUG1_SENSE_MASK) +#define APBH_CH13_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH13_DEBUG1_END_SHIFT (28U) +#define APBH_CH13_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_END_SHIFT)) & APBH_CH13_DEBUG1_END_MASK) +#define APBH_CH13_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH13_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH13_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_KICK_SHIFT)) & APBH_CH13_DEBUG1_KICK_MASK) +#define APBH_CH13_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH13_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH13_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_BURST_SHIFT)) & APBH_CH13_DEBUG1_BURST_MASK) +#define APBH_CH13_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH13_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH13_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_REQ_SHIFT)) & APBH_CH13_DEBUG1_REQ_MASK) + +/*! @name CH13_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH13_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH13_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH13_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH13_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH13_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH13_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH13_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH13_DEBUG2_APB_BYTES_MASK) + +/*! @name CH14_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH14_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH14_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH14_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH14_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH14_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH14_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH14_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH14_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH14_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH14_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH14_CMD_COMMAND_MASK (0x3U) +#define APBH_CH14_CMD_COMMAND_SHIFT (0U) +#define APBH_CH14_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_COMMAND_SHIFT)) & APBH_CH14_CMD_COMMAND_MASK) +#define APBH_CH14_CMD_CHAIN_MASK (0x4U) +#define APBH_CH14_CMD_CHAIN_SHIFT (2U) +#define APBH_CH14_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_CHAIN_SHIFT)) & APBH_CH14_CMD_CHAIN_MASK) +#define APBH_CH14_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH14_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH14_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_IRQONCMPLT_SHIFT)) & APBH_CH14_CMD_IRQONCMPLT_MASK) +#define APBH_CH14_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH14_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH14_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_NANDLOCK_SHIFT)) & APBH_CH14_CMD_NANDLOCK_MASK) +#define APBH_CH14_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH14_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH14_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH14_CMD_NANDWAIT4READY_MASK) +#define APBH_CH14_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH14_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH14_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_SEMAPHORE_SHIFT)) & APBH_CH14_CMD_SEMAPHORE_MASK) +#define APBH_CH14_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH14_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH14_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH14_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH14_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH14_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH14_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH14_CMD_HALTONTERMINATE_MASK) +#define APBH_CH14_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH14_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH14_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_CMDWORDS_SHIFT)) & APBH_CH14_CMD_CMDWORDS_MASK) +#define APBH_CH14_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH14_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH14_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_XFER_COUNT_SHIFT)) & APBH_CH14_CMD_XFER_COUNT_MASK) + +/*! @name CH14_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH14_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH14_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH14_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_BAR_ADDRESS_SHIFT)) & APBH_CH14_BAR_ADDRESS_MASK) + +/*! @name CH14_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH14_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH14_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH14_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH14_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH14_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH14_SEMA_PHORE_SHIFT (16U) +#define APBH_CH14_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_SEMA_PHORE_SHIFT)) & APBH_CH14_SEMA_PHORE_MASK) + +/*! @name CH14_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH14_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH14_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH14_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH14_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH14_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH14_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH14_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RSVD1_SHIFT)) & APBH_CH14_DEBUG1_RSVD1_MASK) +#define APBH_CH14_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH14_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH14_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH14_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH14_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH14_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH14_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH14_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH14_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH14_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH14_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH14_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH14_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH14_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_LOCK_SHIFT)) & APBH_CH14_DEBUG1_LOCK_MASK) +#define APBH_CH14_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH14_DEBUG1_READY_SHIFT (26U) +#define APBH_CH14_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_READY_SHIFT)) & APBH_CH14_DEBUG1_READY_MASK) +#define APBH_CH14_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH14_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH14_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_SENSE_SHIFT)) & APBH_CH14_DEBUG1_SENSE_MASK) +#define APBH_CH14_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH14_DEBUG1_END_SHIFT (28U) +#define APBH_CH14_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_END_SHIFT)) & APBH_CH14_DEBUG1_END_MASK) +#define APBH_CH14_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH14_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH14_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_KICK_SHIFT)) & APBH_CH14_DEBUG1_KICK_MASK) +#define APBH_CH14_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH14_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH14_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_BURST_SHIFT)) & APBH_CH14_DEBUG1_BURST_MASK) +#define APBH_CH14_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH14_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH14_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_REQ_SHIFT)) & APBH_CH14_DEBUG1_REQ_MASK) + +/*! @name CH14_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH14_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH14_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH14_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH14_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH14_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH14_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH14_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH14_DEBUG2_APB_BYTES_MASK) + +/*! @name CH15_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH15_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH15_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH15_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH15_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH15_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH15_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH15_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH15_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH15_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH15_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH15_CMD_COMMAND_MASK (0x3U) +#define APBH_CH15_CMD_COMMAND_SHIFT (0U) +#define APBH_CH15_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_COMMAND_SHIFT)) & APBH_CH15_CMD_COMMAND_MASK) +#define APBH_CH15_CMD_CHAIN_MASK (0x4U) +#define APBH_CH15_CMD_CHAIN_SHIFT (2U) +#define APBH_CH15_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_CHAIN_SHIFT)) & APBH_CH15_CMD_CHAIN_MASK) +#define APBH_CH15_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH15_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH15_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_IRQONCMPLT_SHIFT)) & APBH_CH15_CMD_IRQONCMPLT_MASK) +#define APBH_CH15_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH15_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH15_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_NANDLOCK_SHIFT)) & APBH_CH15_CMD_NANDLOCK_MASK) +#define APBH_CH15_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH15_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH15_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH15_CMD_NANDWAIT4READY_MASK) +#define APBH_CH15_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH15_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH15_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_SEMAPHORE_SHIFT)) & APBH_CH15_CMD_SEMAPHORE_MASK) +#define APBH_CH15_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH15_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH15_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH15_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH15_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH15_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH15_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH15_CMD_HALTONTERMINATE_MASK) +#define APBH_CH15_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH15_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH15_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_CMDWORDS_SHIFT)) & APBH_CH15_CMD_CMDWORDS_MASK) +#define APBH_CH15_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH15_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH15_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_XFER_COUNT_SHIFT)) & APBH_CH15_CMD_XFER_COUNT_MASK) + +/*! @name CH15_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH15_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH15_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH15_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_BAR_ADDRESS_SHIFT)) & APBH_CH15_BAR_ADDRESS_MASK) + +/*! @name CH15_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH15_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH15_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH15_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH15_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH15_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH15_SEMA_PHORE_SHIFT (16U) +#define APBH_CH15_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_SEMA_PHORE_SHIFT)) & APBH_CH15_SEMA_PHORE_MASK) + +/*! @name CH15_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH15_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH15_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH15_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH15_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH15_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH15_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH15_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RSVD1_SHIFT)) & APBH_CH15_DEBUG1_RSVD1_MASK) +#define APBH_CH15_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH15_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH15_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH15_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH15_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH15_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH15_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH15_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH15_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH15_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH15_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH15_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH15_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH15_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_LOCK_SHIFT)) & APBH_CH15_DEBUG1_LOCK_MASK) +#define APBH_CH15_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH15_DEBUG1_READY_SHIFT (26U) +#define APBH_CH15_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_READY_SHIFT)) & APBH_CH15_DEBUG1_READY_MASK) +#define APBH_CH15_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH15_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH15_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_SENSE_SHIFT)) & APBH_CH15_DEBUG1_SENSE_MASK) +#define APBH_CH15_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH15_DEBUG1_END_SHIFT (28U) +#define APBH_CH15_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_END_SHIFT)) & APBH_CH15_DEBUG1_END_MASK) +#define APBH_CH15_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH15_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH15_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_KICK_SHIFT)) & APBH_CH15_DEBUG1_KICK_MASK) +#define APBH_CH15_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH15_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH15_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_BURST_SHIFT)) & APBH_CH15_DEBUG1_BURST_MASK) +#define APBH_CH15_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH15_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH15_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_REQ_SHIFT)) & APBH_CH15_DEBUG1_REQ_MASK) + +/*! @name CH15_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH15_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH15_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH15_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH15_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH15_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH15_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH15_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH15_DEBUG2_APB_BYTES_MASK) + +/*! @name VERSION - APBH Bridge Version Register */ +#define APBH_VERSION_STEP_MASK (0xFFFFU) +#define APBH_VERSION_STEP_SHIFT (0U) +#define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK) +#define APBH_VERSION_MINOR_MASK (0xFF0000U) +#define APBH_VERSION_MINOR_SHIFT (16U) +#define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK) +#define APBH_VERSION_MAJOR_MASK (0xFF000000U) +#define APBH_VERSION_MAJOR_SHIFT (24U) +#define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK) + + +/*! + * @} + */ /* end of group APBH_Register_Masks */ + + +/* APBH - Peripheral instance base addresses */ +/** Peripheral APBH base address */ +#define APBH_BASE (0x1804000u) +/** Peripheral APBH base pointer */ +#define APBH ((APBH_Type *)APBH_BASE) +/** Array initializer of APBH peripheral base addresses */ +#define APBH_BASE_ADDRS { APBH_BASE } +/** Array initializer of APBH peripheral base pointers */ +#define APBH_BASE_PTRS { APBH } +/** Interrupt vectors for the APBH peripheral type */ +#define APBH_IRQS { APBH_IRQn } + +/*! + * @} + */ /* end of group APBH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ASRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer + * @{ + */ + +/** ASRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t ASRCTR; /**< ASRC Control Register, offset: 0x0 */ + __IO uint32_t ASRIER; /**< ASRC Interrupt Enable Register, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ASRCNCR; /**< ASRC Channel Number Configuration Register, offset: 0xC */ + __IO uint32_t ASRCFG; /**< ASRC Filter Configuration Status Register, offset: 0x10 */ + __IO uint32_t ASRCSR; /**< ASRC Clock Source Register, offset: 0x14 */ + __IO uint32_t ASRCDR1; /**< ASRC Clock Divider Register 1, offset: 0x18 */ + __IO uint32_t ASRCDR2; /**< ASRC Clock Divider Register 2, offset: 0x1C */ + __I uint32_t ASRSTR; /**< ASRC Status Register, offset: 0x20 */ + uint8_t RESERVED_1[28]; + __IO uint32_t ASRPMn[5]; /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */ + __IO uint32_t ASRTFR1; /**< ASRC ASRC Task Queue FIFO Register 1, offset: 0x54 */ + uint8_t RESERVED_2[4]; + __IO uint32_t ASRCCR; /**< ASRC Channel Counter Register, offset: 0x5C */ + __IO uint32_t ASRDIA; /**< ASRC Data Input Register for Pair x, offset: 0x60 */ + __I uint32_t ASRDOA; /**< ASRC Data Output Register for Pair x, offset: 0x64 */ + __IO uint32_t ASRDIB; /**< ASRC Data Input Register for Pair x, offset: 0x68 */ + __I uint32_t ASRDOB; /**< ASRC Data Output Register for Pair x, offset: 0x6C */ + __IO uint32_t ASRDIC; /**< ASRC Data Input Register for Pair x, offset: 0x70 */ + __I uint32_t ASRDOC; /**< ASRC Data Output Register for Pair x, offset: 0x74 */ + uint8_t RESERVED_3[8]; + __IO uint32_t ASRIDRHA; /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */ + __IO uint32_t ASRIDRLA; /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */ + __IO uint32_t ASRIDRHB; /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */ + __IO uint32_t ASRIDRLB; /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */ + __IO uint32_t ASRIDRHC; /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */ + __IO uint32_t ASRIDRLC; /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */ + __IO uint32_t ASR76K; /**< ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98 */ + __IO uint32_t ASR56K; /**< ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C */ + __IO uint32_t ASRMCRA; /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */ + __I uint32_t ASRFSTA; /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */ + __IO uint32_t ASRMCRB; /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */ + __I uint32_t ASRFSTB; /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */ + __IO uint32_t ASRMCRC; /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */ + __I uint32_t ASRFSTC; /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */ + uint8_t RESERVED_4[8]; + __IO uint32_t ASRMCR1[3]; /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */ +} ASRC_Type; + +/* ---------------------------------------------------------------------------- + -- ASRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASRC_Register_Masks ASRC Register Masks + * @{ + */ + +/*! @name ASRCTR - ASRC Control Register */ +#define ASRC_ASRCTR_ASRCEN_MASK (0x1U) +#define ASRC_ASRCTR_ASRCEN_SHIFT (0U) +#define ASRC_ASRCTR_ASRCEN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK) +#define ASRC_ASRCTR_ASREA_MASK (0x2U) +#define ASRC_ASRCTR_ASREA_SHIFT (1U) +#define ASRC_ASRCTR_ASREA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK) +#define ASRC_ASRCTR_ASREB_MASK (0x4U) +#define ASRC_ASRCTR_ASREB_SHIFT (2U) +#define ASRC_ASRCTR_ASREB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK) +#define ASRC_ASRCTR_ASREC_MASK (0x8U) +#define ASRC_ASRCTR_ASREC_SHIFT (3U) +#define ASRC_ASRCTR_ASREC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK) +#define ASRC_ASRCTR_SRST_MASK (0x10U) +#define ASRC_ASRCTR_SRST_SHIFT (4U) +#define ASRC_ASRCTR_SRST(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK) +#define ASRC_ASRCTR_IDRA_MASK (0x2000U) +#define ASRC_ASRCTR_IDRA_SHIFT (13U) +#define ASRC_ASRCTR_IDRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK) +#define ASRC_ASRCTR_USRA_MASK (0x4000U) +#define ASRC_ASRCTR_USRA_SHIFT (14U) +#define ASRC_ASRCTR_USRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK) +#define ASRC_ASRCTR_IDRB_MASK (0x8000U) +#define ASRC_ASRCTR_IDRB_SHIFT (15U) +#define ASRC_ASRCTR_IDRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK) +#define ASRC_ASRCTR_USRB_MASK (0x10000U) +#define ASRC_ASRCTR_USRB_SHIFT (16U) +#define ASRC_ASRCTR_USRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK) +#define ASRC_ASRCTR_IDRC_MASK (0x20000U) +#define ASRC_ASRCTR_IDRC_SHIFT (17U) +#define ASRC_ASRCTR_IDRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK) +#define ASRC_ASRCTR_USRC_MASK (0x40000U) +#define ASRC_ASRCTR_USRC_SHIFT (18U) +#define ASRC_ASRCTR_USRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK) +#define ASRC_ASRCTR_ATSA_MASK (0x100000U) +#define ASRC_ASRCTR_ATSA_SHIFT (20U) +#define ASRC_ASRCTR_ATSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK) +#define ASRC_ASRCTR_ATSB_MASK (0x200000U) +#define ASRC_ASRCTR_ATSB_SHIFT (21U) +#define ASRC_ASRCTR_ATSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK) +#define ASRC_ASRCTR_ATSC_MASK (0x400000U) +#define ASRC_ASRCTR_ATSC_SHIFT (22U) +#define ASRC_ASRCTR_ATSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK) + +/*! @name ASRIER - ASRC Interrupt Enable Register */ +#define ASRC_ASRIER_ADIEA_MASK (0x1U) +#define ASRC_ASRIER_ADIEA_SHIFT (0U) +#define ASRC_ASRIER_ADIEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK) +#define ASRC_ASRIER_ADIEB_MASK (0x2U) +#define ASRC_ASRIER_ADIEB_SHIFT (1U) +#define ASRC_ASRIER_ADIEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK) +#define ASRC_ASRIER_ADIEC_MASK (0x4U) +#define ASRC_ASRIER_ADIEC_SHIFT (2U) +#define ASRC_ASRIER_ADIEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK) +#define ASRC_ASRIER_ADOEA_MASK (0x8U) +#define ASRC_ASRIER_ADOEA_SHIFT (3U) +#define ASRC_ASRIER_ADOEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK) +#define ASRC_ASRIER_ADOEB_MASK (0x10U) +#define ASRC_ASRIER_ADOEB_SHIFT (4U) +#define ASRC_ASRIER_ADOEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK) +#define ASRC_ASRIER_ADOEC_MASK (0x20U) +#define ASRC_ASRIER_ADOEC_SHIFT (5U) +#define ASRC_ASRIER_ADOEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK) +#define ASRC_ASRIER_AOLIE_MASK (0x40U) +#define ASRC_ASRIER_AOLIE_SHIFT (6U) +#define ASRC_ASRIER_AOLIE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK) +#define ASRC_ASRIER_AFPWE_MASK (0x80U) +#define ASRC_ASRIER_AFPWE_SHIFT (7U) +#define ASRC_ASRIER_AFPWE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK) + +/*! @name ASRCNCR - ASRC Channel Number Configuration Register */ +#define ASRC_ASRCNCR_ANCA_MASK (0xFU) +#define ASRC_ASRCNCR_ANCA_SHIFT (0U) +#define ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK) +#define ASRC_ASRCNCR_ANCB_MASK (0xF0U) +#define ASRC_ASRCNCR_ANCB_SHIFT (4U) +#define ASRC_ASRCNCR_ANCB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK) +#define ASRC_ASRCNCR_ANCC_MASK (0xF00U) +#define ASRC_ASRCNCR_ANCC_SHIFT (8U) +#define ASRC_ASRCNCR_ANCC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK) + +/*! @name ASRCFG - ASRC Filter Configuration Status Register */ +#define ASRC_ASRCFG_PREMODA_MASK (0xC0U) +#define ASRC_ASRCFG_PREMODA_SHIFT (6U) +#define ASRC_ASRCFG_PREMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK) +#define ASRC_ASRCFG_POSTMODA_MASK (0x300U) +#define ASRC_ASRCFG_POSTMODA_SHIFT (8U) +#define ASRC_ASRCFG_POSTMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK) +#define ASRC_ASRCFG_PREMODB_MASK (0xC00U) +#define ASRC_ASRCFG_PREMODB_SHIFT (10U) +#define ASRC_ASRCFG_PREMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK) +#define ASRC_ASRCFG_POSTMODB_MASK (0x3000U) +#define ASRC_ASRCFG_POSTMODB_SHIFT (12U) +#define ASRC_ASRCFG_POSTMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK) +#define ASRC_ASRCFG_PREMODC_MASK (0xC000U) +#define ASRC_ASRCFG_PREMODC_SHIFT (14U) +#define ASRC_ASRCFG_PREMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK) +#define ASRC_ASRCFG_POSTMODC_MASK (0x30000U) +#define ASRC_ASRCFG_POSTMODC_SHIFT (16U) +#define ASRC_ASRCFG_POSTMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK) +#define ASRC_ASRCFG_NDPRA_MASK (0x40000U) +#define ASRC_ASRCFG_NDPRA_SHIFT (18U) +#define ASRC_ASRCFG_NDPRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK) +#define ASRC_ASRCFG_NDPRB_MASK (0x80000U) +#define ASRC_ASRCFG_NDPRB_SHIFT (19U) +#define ASRC_ASRCFG_NDPRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK) +#define ASRC_ASRCFG_NDPRC_MASK (0x100000U) +#define ASRC_ASRCFG_NDPRC_SHIFT (20U) +#define ASRC_ASRCFG_NDPRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK) +#define ASRC_ASRCFG_INIRQA_MASK (0x200000U) +#define ASRC_ASRCFG_INIRQA_SHIFT (21U) +#define ASRC_ASRCFG_INIRQA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK) +#define ASRC_ASRCFG_INIRQB_MASK (0x400000U) +#define ASRC_ASRCFG_INIRQB_SHIFT (22U) +#define ASRC_ASRCFG_INIRQB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK) +#define ASRC_ASRCFG_INIRQC_MASK (0x800000U) +#define ASRC_ASRCFG_INIRQC_SHIFT (23U) +#define ASRC_ASRCFG_INIRQC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK) + +/*! @name ASRCSR - ASRC Clock Source Register */ +#define ASRC_ASRCSR_AICSA_MASK (0xFU) +#define ASRC_ASRCSR_AICSA_SHIFT (0U) +#define ASRC_ASRCSR_AICSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK) +#define ASRC_ASRCSR_AICSB_MASK (0xF0U) +#define ASRC_ASRCSR_AICSB_SHIFT (4U) +#define ASRC_ASRCSR_AICSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK) +#define ASRC_ASRCSR_AICSC_MASK (0xF00U) +#define ASRC_ASRCSR_AICSC_SHIFT (8U) +#define ASRC_ASRCSR_AICSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK) +#define ASRC_ASRCSR_AOCSA_MASK (0xF000U) +#define ASRC_ASRCSR_AOCSA_SHIFT (12U) +#define ASRC_ASRCSR_AOCSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK) +#define ASRC_ASRCSR_AOCSB_MASK (0xF0000U) +#define ASRC_ASRCSR_AOCSB_SHIFT (16U) +#define ASRC_ASRCSR_AOCSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK) +#define ASRC_ASRCSR_AOCSC_MASK (0xF00000U) +#define ASRC_ASRCSR_AOCSC_SHIFT (20U) +#define ASRC_ASRCSR_AOCSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK) + +/*! @name ASRCDR1 - ASRC Clock Divider Register 1 */ +#define ASRC_ASRCDR1_AICPA_MASK (0x7U) +#define ASRC_ASRCDR1_AICPA_SHIFT (0U) +#define ASRC_ASRCDR1_AICPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK) +#define ASRC_ASRCDR1_AICDA_MASK (0x38U) +#define ASRC_ASRCDR1_AICDA_SHIFT (3U) +#define ASRC_ASRCDR1_AICDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK) +#define ASRC_ASRCDR1_AICPB_MASK (0x1C0U) +#define ASRC_ASRCDR1_AICPB_SHIFT (6U) +#define ASRC_ASRCDR1_AICPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK) +#define ASRC_ASRCDR1_AICDB_MASK (0xE00U) +#define ASRC_ASRCDR1_AICDB_SHIFT (9U) +#define ASRC_ASRCDR1_AICDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK) +#define ASRC_ASRCDR1_AOCPA_MASK (0x7000U) +#define ASRC_ASRCDR1_AOCPA_SHIFT (12U) +#define ASRC_ASRCDR1_AOCPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK) +#define ASRC_ASRCDR1_AOCDA_MASK (0x38000U) +#define ASRC_ASRCDR1_AOCDA_SHIFT (15U) +#define ASRC_ASRCDR1_AOCDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK) +#define ASRC_ASRCDR1_AOCPB_MASK (0x1C0000U) +#define ASRC_ASRCDR1_AOCPB_SHIFT (18U) +#define ASRC_ASRCDR1_AOCPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK) +#define ASRC_ASRCDR1_AOCDB_MASK (0xE00000U) +#define ASRC_ASRCDR1_AOCDB_SHIFT (21U) +#define ASRC_ASRCDR1_AOCDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK) + +/*! @name ASRCDR2 - ASRC Clock Divider Register 2 */ +#define ASRC_ASRCDR2_AICPC_MASK (0x7U) +#define ASRC_ASRCDR2_AICPC_SHIFT (0U) +#define ASRC_ASRCDR2_AICPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK) +#define ASRC_ASRCDR2_AICDC_MASK (0x38U) +#define ASRC_ASRCDR2_AICDC_SHIFT (3U) +#define ASRC_ASRCDR2_AICDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK) +#define ASRC_ASRCDR2_AOCPC_MASK (0x1C0U) +#define ASRC_ASRCDR2_AOCPC_SHIFT (6U) +#define ASRC_ASRCDR2_AOCPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK) +#define ASRC_ASRCDR2_AOCDC_MASK (0xE00U) +#define ASRC_ASRCDR2_AOCDC_SHIFT (9U) +#define ASRC_ASRCDR2_AOCDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK) + +/*! @name ASRSTR - ASRC Status Register */ +#define ASRC_ASRSTR_AIDEA_MASK (0x1U) +#define ASRC_ASRSTR_AIDEA_SHIFT (0U) +#define ASRC_ASRSTR_AIDEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK) +#define ASRC_ASRSTR_AIDEB_MASK (0x2U) +#define ASRC_ASRSTR_AIDEB_SHIFT (1U) +#define ASRC_ASRSTR_AIDEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK) +#define ASRC_ASRSTR_AIDEC_MASK (0x4U) +#define ASRC_ASRSTR_AIDEC_SHIFT (2U) +#define ASRC_ASRSTR_AIDEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK) +#define ASRC_ASRSTR_AODFA_MASK (0x8U) +#define ASRC_ASRSTR_AODFA_SHIFT (3U) +#define ASRC_ASRSTR_AODFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK) +#define ASRC_ASRSTR_AODFB_MASK (0x10U) +#define ASRC_ASRSTR_AODFB_SHIFT (4U) +#define ASRC_ASRSTR_AODFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK) +#define ASRC_ASRSTR_AODFC_MASK (0x20U) +#define ASRC_ASRSTR_AODFC_SHIFT (5U) +#define ASRC_ASRSTR_AODFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK) +#define ASRC_ASRSTR_AOLE_MASK (0x40U) +#define ASRC_ASRSTR_AOLE_SHIFT (6U) +#define ASRC_ASRSTR_AOLE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK) +#define ASRC_ASRSTR_FPWT_MASK (0x80U) +#define ASRC_ASRSTR_FPWT_SHIFT (7U) +#define ASRC_ASRSTR_FPWT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK) +#define ASRC_ASRSTR_AIDUA_MASK (0x100U) +#define ASRC_ASRSTR_AIDUA_SHIFT (8U) +#define ASRC_ASRSTR_AIDUA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK) +#define ASRC_ASRSTR_AIDUB_MASK (0x200U) +#define ASRC_ASRSTR_AIDUB_SHIFT (9U) +#define ASRC_ASRSTR_AIDUB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK) +#define ASRC_ASRSTR_AIDUC_MASK (0x400U) +#define ASRC_ASRSTR_AIDUC_SHIFT (10U) +#define ASRC_ASRSTR_AIDUC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK) +#define ASRC_ASRSTR_AODOA_MASK (0x800U) +#define ASRC_ASRSTR_AODOA_SHIFT (11U) +#define ASRC_ASRSTR_AODOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK) +#define ASRC_ASRSTR_AODOB_MASK (0x1000U) +#define ASRC_ASRSTR_AODOB_SHIFT (12U) +#define ASRC_ASRSTR_AODOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK) +#define ASRC_ASRSTR_AODOC_MASK (0x2000U) +#define ASRC_ASRSTR_AODOC_SHIFT (13U) +#define ASRC_ASRSTR_AODOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK) +#define ASRC_ASRSTR_AIOLA_MASK (0x4000U) +#define ASRC_ASRSTR_AIOLA_SHIFT (14U) +#define ASRC_ASRSTR_AIOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK) +#define ASRC_ASRSTR_AIOLB_MASK (0x8000U) +#define ASRC_ASRSTR_AIOLB_SHIFT (15U) +#define ASRC_ASRSTR_AIOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK) +#define ASRC_ASRSTR_AIOLC_MASK (0x10000U) +#define ASRC_ASRSTR_AIOLC_SHIFT (16U) +#define ASRC_ASRSTR_AIOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK) +#define ASRC_ASRSTR_AOOLA_MASK (0x20000U) +#define ASRC_ASRSTR_AOOLA_SHIFT (17U) +#define ASRC_ASRSTR_AOOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK) +#define ASRC_ASRSTR_AOOLB_MASK (0x40000U) +#define ASRC_ASRSTR_AOOLB_SHIFT (18U) +#define ASRC_ASRSTR_AOOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK) +#define ASRC_ASRSTR_AOOLC_MASK (0x80000U) +#define ASRC_ASRSTR_AOOLC_SHIFT (19U) +#define ASRC_ASRSTR_AOOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK) +#define ASRC_ASRSTR_ATQOL_MASK (0x100000U) +#define ASRC_ASRSTR_ATQOL_SHIFT (20U) +#define ASRC_ASRSTR_ATQOL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK) +#define ASRC_ASRSTR_DSLCNT_MASK (0x200000U) +#define ASRC_ASRSTR_DSLCNT_SHIFT (21U) +#define ASRC_ASRSTR_DSLCNT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK) + +/*! @name ASRPMn - ASRC Parameter Register n */ +#define ASRC_ASRPMn_PARAMETER_VALUE_MASK (0xFFFFFFU) +#define ASRC_ASRPMn_PARAMETER_VALUE_SHIFT (0U) +#define ASRC_ASRPMn_PARAMETER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPMn_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPMn_PARAMETER_VALUE_MASK) + +/* The count of ASRC_ASRPMn */ +#define ASRC_ASRPMn_COUNT (5U) + +/*! @name ASRTFR1 - ASRC ASRC Task Queue FIFO Register 1 */ +#define ASRC_ASRTFR1_TF_BASE_MASK (0x1FC0U) +#define ASRC_ASRTFR1_TF_BASE_SHIFT (6U) +#define ASRC_ASRTFR1_TF_BASE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK) +#define ASRC_ASRTFR1_TF_FILL_MASK (0xFE000U) +#define ASRC_ASRTFR1_TF_FILL_SHIFT (13U) +#define ASRC_ASRTFR1_TF_FILL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK) + +/*! @name ASRCCR - ASRC Channel Counter Register */ +#define ASRC_ASRCCR_ACIA_MASK (0xFU) +#define ASRC_ASRCCR_ACIA_SHIFT (0U) +#define ASRC_ASRCCR_ACIA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK) +#define ASRC_ASRCCR_ACIB_MASK (0xF0U) +#define ASRC_ASRCCR_ACIB_SHIFT (4U) +#define ASRC_ASRCCR_ACIB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK) +#define ASRC_ASRCCR_ACIC_MASK (0xF00U) +#define ASRC_ASRCCR_ACIC_SHIFT (8U) +#define ASRC_ASRCCR_ACIC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK) +#define ASRC_ASRCCR_ACOA_MASK (0xF000U) +#define ASRC_ASRCCR_ACOA_SHIFT (12U) +#define ASRC_ASRCCR_ACOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK) +#define ASRC_ASRCCR_ACOB_MASK (0xF0000U) +#define ASRC_ASRCCR_ACOB_SHIFT (16U) +#define ASRC_ASRCCR_ACOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK) +#define ASRC_ASRCCR_ACOC_MASK (0xF00000U) +#define ASRC_ASRCCR_ACOC_SHIFT (20U) +#define ASRC_ASRCCR_ACOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK) + +/*! @name ASRDIA - ASRC Data Input Register for Pair x */ +#define ASRC_ASRDIA_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDIA_DATA_SHIFT (0U) +#define ASRC_ASRDIA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK) + +/*! @name ASRDOA - ASRC Data Output Register for Pair x */ +#define ASRC_ASRDOA_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDOA_DATA_SHIFT (0U) +#define ASRC_ASRDOA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK) + +/*! @name ASRDIB - ASRC Data Input Register for Pair x */ +#define ASRC_ASRDIB_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDIB_DATA_SHIFT (0U) +#define ASRC_ASRDIB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK) + +/*! @name ASRDOB - ASRC Data Output Register for Pair x */ +#define ASRC_ASRDOB_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDOB_DATA_SHIFT (0U) +#define ASRC_ASRDOB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK) + +/*! @name ASRDIC - ASRC Data Input Register for Pair x */ +#define ASRC_ASRDIC_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDIC_DATA_SHIFT (0U) +#define ASRC_ASRDIC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK) + +/*! @name ASRDOC - ASRC Data Output Register for Pair x */ +#define ASRC_ASRDOC_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDOC_DATA_SHIFT (0U) +#define ASRC_ASRDOC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK) + +/*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */ +#define ASRC_ASRIDRHA_IDRATIOA_H_MASK (0xFFU) +#define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT (0U) +#define ASRC_ASRIDRHA_IDRATIOA_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK) + +/*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */ +#define ASRC_ASRIDRLA_IDRATIOA_L_MASK (0xFFFFFFU) +#define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT (0U) +#define ASRC_ASRIDRLA_IDRATIOA_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK) + +/*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */ +#define ASRC_ASRIDRHB_IDRATIOB_H_MASK (0xFFU) +#define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT (0U) +#define ASRC_ASRIDRHB_IDRATIOB_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK) + +/*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */ +#define ASRC_ASRIDRLB_IDRATIOB_L_MASK (0xFFFFFFU) +#define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT (0U) +#define ASRC_ASRIDRLB_IDRATIOB_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK) + +/*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */ +#define ASRC_ASRIDRHC_IDRATIOC_H_MASK (0xFFU) +#define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT (0U) +#define ASRC_ASRIDRHC_IDRATIOC_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK) + +/*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */ +#define ASRC_ASRIDRLC_IDRATIOC_L_MASK (0xFFFFFFU) +#define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT (0U) +#define ASRC_ASRIDRLC_IDRATIOC_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK) + +/*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */ +#define ASRC_ASR76K_ASR76K_MASK (0x1FFFFU) +#define ASRC_ASR76K_ASR76K_SHIFT (0U) +#define ASRC_ASR76K_ASR76K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK) + +/*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */ +#define ASRC_ASR56K_ASR56K_MASK (0x1FFFFU) +#define ASRC_ASR56K_ASR56K_SHIFT (0U) +#define ASRC_ASR56K_ASR56K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK) + +/*! @name ASRMCRA - ASRC Misc Control Register for Pair A */ +#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK (0x3FU) +#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT (0U) +#define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK) +#define ASRC_ASRMCRA_RSYNOFA_MASK (0x400U) +#define ASRC_ASRMCRA_RSYNOFA_SHIFT (10U) +#define ASRC_ASRMCRA_RSYNOFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK) +#define ASRC_ASRMCRA_RSYNIFA_MASK (0x800U) +#define ASRC_ASRMCRA_RSYNIFA_SHIFT (11U) +#define ASRC_ASRMCRA_RSYNIFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK) +#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK (0x3F000U) +#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT (12U) +#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK) +#define ASRC_ASRMCRA_BYPASSPOLYA_MASK (0x100000U) +#define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT (20U) +#define ASRC_ASRMCRA_BYPASSPOLYA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK) +#define ASRC_ASRMCRA_BUFSTALLA_MASK (0x200000U) +#define ASRC_ASRMCRA_BUFSTALLA_SHIFT (21U) +#define ASRC_ASRMCRA_BUFSTALLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK) +#define ASRC_ASRMCRA_EXTTHRSHA_MASK (0x400000U) +#define ASRC_ASRMCRA_EXTTHRSHA_SHIFT (22U) +#define ASRC_ASRMCRA_EXTTHRSHA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK) +#define ASRC_ASRMCRA_ZEROBUFA_MASK (0x800000U) +#define ASRC_ASRMCRA_ZEROBUFA_SHIFT (23U) +#define ASRC_ASRMCRA_ZEROBUFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK) + +/*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */ +#define ASRC_ASRFSTA_INFIFO_FILLA_MASK (0x7FU) +#define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT (0U) +#define ASRC_ASRFSTA_INFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK) +#define ASRC_ASRFSTA_IAEA_MASK (0x800U) +#define ASRC_ASRFSTA_IAEA_SHIFT (11U) +#define ASRC_ASRFSTA_IAEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK) +#define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK (0x7F000U) +#define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT (12U) +#define ASRC_ASRFSTA_OUTFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK) +#define ASRC_ASRFSTA_OAFA_MASK (0x800000U) +#define ASRC_ASRFSTA_OAFA_SHIFT (23U) +#define ASRC_ASRFSTA_OAFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK) + +/*! @name ASRMCRB - ASRC Misc Control Register for Pair B */ +#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK (0x3FU) +#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT (0U) +#define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK) +#define ASRC_ASRMCRB_RSYNOFB_MASK (0x400U) +#define ASRC_ASRMCRB_RSYNOFB_SHIFT (10U) +#define ASRC_ASRMCRB_RSYNOFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK) +#define ASRC_ASRMCRB_RSYNIFB_MASK (0x800U) +#define ASRC_ASRMCRB_RSYNIFB_SHIFT (11U) +#define ASRC_ASRMCRB_RSYNIFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK) +#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK (0x3F000U) +#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT (12U) +#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK) +#define ASRC_ASRMCRB_BYPASSPOLYB_MASK (0x100000U) +#define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT (20U) +#define ASRC_ASRMCRB_BYPASSPOLYB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK) +#define ASRC_ASRMCRB_BUFSTALLB_MASK (0x200000U) +#define ASRC_ASRMCRB_BUFSTALLB_SHIFT (21U) +#define ASRC_ASRMCRB_BUFSTALLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK) +#define ASRC_ASRMCRB_EXTTHRSHB_MASK (0x400000U) +#define ASRC_ASRMCRB_EXTTHRSHB_SHIFT (22U) +#define ASRC_ASRMCRB_EXTTHRSHB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK) +#define ASRC_ASRMCRB_ZEROBUFB_MASK (0x800000U) +#define ASRC_ASRMCRB_ZEROBUFB_SHIFT (23U) +#define ASRC_ASRMCRB_ZEROBUFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK) + +/*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */ +#define ASRC_ASRFSTB_INFIFO_FILLB_MASK (0x7FU) +#define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT (0U) +#define ASRC_ASRFSTB_INFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK) +#define ASRC_ASRFSTB_IAEB_MASK (0x800U) +#define ASRC_ASRFSTB_IAEB_SHIFT (11U) +#define ASRC_ASRFSTB_IAEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK) +#define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK (0x7F000U) +#define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT (12U) +#define ASRC_ASRFSTB_OUTFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK) +#define ASRC_ASRFSTB_OAFB_MASK (0x800000U) +#define ASRC_ASRFSTB_OAFB_SHIFT (23U) +#define ASRC_ASRFSTB_OAFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK) + +/*! @name ASRMCRC - ASRC Misc Control Register for Pair C */ +#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK (0x3FU) +#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT (0U) +#define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK) +#define ASRC_ASRMCRC_RSYNOFC_MASK (0x400U) +#define ASRC_ASRMCRC_RSYNOFC_SHIFT (10U) +#define ASRC_ASRMCRC_RSYNOFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK) +#define ASRC_ASRMCRC_RSYNIFC_MASK (0x800U) +#define ASRC_ASRMCRC_RSYNIFC_SHIFT (11U) +#define ASRC_ASRMCRC_RSYNIFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK) +#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK (0x3F000U) +#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT (12U) +#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK) +#define ASRC_ASRMCRC_BYPASSPOLYC_MASK (0x100000U) +#define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT (20U) +#define ASRC_ASRMCRC_BYPASSPOLYC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK) +#define ASRC_ASRMCRC_BUFSTALLC_MASK (0x200000U) +#define ASRC_ASRMCRC_BUFSTALLC_SHIFT (21U) +#define ASRC_ASRMCRC_BUFSTALLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK) +#define ASRC_ASRMCRC_EXTTHRSHC_MASK (0x400000U) +#define ASRC_ASRMCRC_EXTTHRSHC_SHIFT (22U) +#define ASRC_ASRMCRC_EXTTHRSHC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK) +#define ASRC_ASRMCRC_ZEROBUFC_MASK (0x800000U) +#define ASRC_ASRMCRC_ZEROBUFC_SHIFT (23U) +#define ASRC_ASRMCRC_ZEROBUFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK) + +/*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */ +#define ASRC_ASRFSTC_INFIFO_FILLC_MASK (0x7FU) +#define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT (0U) +#define ASRC_ASRFSTC_INFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK) +#define ASRC_ASRFSTC_IAEC_MASK (0x800U) +#define ASRC_ASRFSTC_IAEC_SHIFT (11U) +#define ASRC_ASRFSTC_IAEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK) +#define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK (0x7F000U) +#define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT (12U) +#define ASRC_ASRFSTC_OUTFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK) +#define ASRC_ASRFSTC_OAFC_MASK (0x800000U) +#define ASRC_ASRFSTC_OAFC_SHIFT (23U) +#define ASRC_ASRFSTC_OAFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK) + +/*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */ +#define ASRC_ASRMCR1_OW16_MASK (0x1U) +#define ASRC_ASRMCR1_OW16_SHIFT (0U) +#define ASRC_ASRMCR1_OW16(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK) +#define ASRC_ASRMCR1_OSGN_MASK (0x2U) +#define ASRC_ASRMCR1_OSGN_SHIFT (1U) +#define ASRC_ASRMCR1_OSGN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK) +#define ASRC_ASRMCR1_OMSB_MASK (0x4U) +#define ASRC_ASRMCR1_OMSB_SHIFT (2U) +#define ASRC_ASRMCR1_OMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK) +#define ASRC_ASRMCR1_IMSB_MASK (0x100U) +#define ASRC_ASRMCR1_IMSB_SHIFT (8U) +#define ASRC_ASRMCR1_IMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK) +#define ASRC_ASRMCR1_IWD_MASK (0xE00U) +#define ASRC_ASRMCR1_IWD_SHIFT (9U) +#define ASRC_ASRMCR1_IWD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK) + +/* The count of ASRC_ASRMCR1 */ +#define ASRC_ASRMCR1_COUNT (3U) + + +/*! + * @} + */ /* end of group ASRC_Register_Masks */ + + +/* ASRC - Peripheral instance base addresses */ +/** Peripheral ASRC base address */ +#define ASRC_BASE (0x2034000u) +/** Peripheral ASRC base pointer */ +#define ASRC ((ASRC_Type *)ASRC_BASE) +/** Array initializer of ASRC peripheral base addresses */ +#define ASRC_BASE_ADDRS { ASRC_BASE } +/** Array initializer of ASRC peripheral base pointers */ +#define ASRC_BASE_PTRS { ASRC } +/** Interrupt vectors for the ASRC peripheral type */ +#define ASRC_IRQS { ASRC_IRQn } + +/*! + * @} + */ /* end of group ASRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BCH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer + * @{ + */ + +/** BCH - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */ + __I uint32_t STATUS0; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */ + __I uint32_t STATUS0_SET; /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */ + __I uint32_t STATUS0_CLR; /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */ + __I uint32_t STATUS0_TOG; /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */ + __IO uint32_t MODE; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */ + __IO uint32_t MODE_SET; /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */ + __IO uint32_t MODE_CLR; /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */ + __IO uint32_t MODE_TOG; /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */ + __IO uint32_t ENCODEPTR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */ + __IO uint32_t ENCODEPTR_SET; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */ + __IO uint32_t ENCODEPTR_CLR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */ + __IO uint32_t ENCODEPTR_TOG; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */ + __IO uint32_t DATAPTR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */ + __IO uint32_t DATAPTR_SET; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */ + __IO uint32_t DATAPTR_CLR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */ + __IO uint32_t DATAPTR_TOG; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */ + __IO uint32_t METAPTR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */ + __IO uint32_t METAPTR_SET; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */ + __IO uint32_t METAPTR_CLR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */ + __IO uint32_t METAPTR_TOG; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */ + uint8_t RESERVED_0[16]; + __IO uint32_t LAYOUTSELECT; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */ + __IO uint32_t LAYOUTSELECT_SET; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */ + __IO uint32_t LAYOUTSELECT_CLR; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */ + __IO uint32_t LAYOUTSELECT_TOG; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */ + __IO uint32_t FLASH0LAYOUT0; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */ + __IO uint32_t FLASH0LAYOUT0_SET; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */ + __IO uint32_t FLASH0LAYOUT0_CLR; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */ + __IO uint32_t FLASH0LAYOUT0_TOG; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */ + __IO uint32_t FLASH0LAYOUT1; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */ + __IO uint32_t FLASH0LAYOUT1_SET; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */ + __IO uint32_t FLASH0LAYOUT1_CLR; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */ + __IO uint32_t FLASH0LAYOUT1_TOG; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */ + __IO uint32_t FLASH1LAYOUT0; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */ + __IO uint32_t FLASH1LAYOUT0_SET; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */ + __IO uint32_t FLASH1LAYOUT0_CLR; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */ + __IO uint32_t FLASH1LAYOUT0_TOG; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */ + __IO uint32_t FLASH1LAYOUT1; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */ + __IO uint32_t FLASH1LAYOUT1_SET; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */ + __IO uint32_t FLASH1LAYOUT1_CLR; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */ + __IO uint32_t FLASH1LAYOUT1_TOG; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */ + __IO uint32_t FLASH2LAYOUT0; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */ + __IO uint32_t FLASH2LAYOUT0_SET; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */ + __IO uint32_t FLASH2LAYOUT0_CLR; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */ + __IO uint32_t FLASH2LAYOUT0_TOG; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */ + __IO uint32_t FLASH2LAYOUT1; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */ + __IO uint32_t FLASH2LAYOUT1_SET; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */ + __IO uint32_t FLASH2LAYOUT1_CLR; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */ + __IO uint32_t FLASH2LAYOUT1_TOG; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */ + __IO uint32_t FLASH3LAYOUT0; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */ + __IO uint32_t FLASH3LAYOUT0_SET; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */ + __IO uint32_t FLASH3LAYOUT0_CLR; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */ + __IO uint32_t FLASH3LAYOUT0_TOG; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */ + __IO uint32_t FLASH3LAYOUT1; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */ + __IO uint32_t FLASH3LAYOUT1_SET; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */ + __IO uint32_t FLASH3LAYOUT1_CLR; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */ + __IO uint32_t FLASH3LAYOUT1_TOG; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */ + __IO uint32_t DEBUG0; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */ + __IO uint32_t DEBUG0_SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */ + __IO uint32_t DEBUG0_CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */ + __IO uint32_t DEBUG0_TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */ + __I uint32_t DBGKESREAD; /**< KES Debug Read Register, offset: 0x110 */ + __I uint32_t DBGKESREAD_SET; /**< KES Debug Read Register, offset: 0x114 */ + __I uint32_t DBGKESREAD_CLR; /**< KES Debug Read Register, offset: 0x118 */ + __I uint32_t DBGKESREAD_TOG; /**< KES Debug Read Register, offset: 0x11C */ + __I uint32_t DBGCSFEREAD; /**< Chien Search Debug Read Register, offset: 0x120 */ + __I uint32_t DBGCSFEREAD_SET; /**< Chien Search Debug Read Register, offset: 0x124 */ + __I uint32_t DBGCSFEREAD_CLR; /**< Chien Search Debug Read Register, offset: 0x128 */ + __I uint32_t DBGCSFEREAD_TOG; /**< Chien Search Debug Read Register, offset: 0x12C */ + __I uint32_t DBGSYNDGENREAD; /**< Syndrome Generator Debug Read Register, offset: 0x130 */ + __I uint32_t DBGSYNDGENREAD_SET; /**< Syndrome Generator Debug Read Register, offset: 0x134 */ + __I uint32_t DBGSYNDGENREAD_CLR; /**< Syndrome Generator Debug Read Register, offset: 0x138 */ + __I uint32_t DBGSYNDGENREAD_TOG; /**< Syndrome Generator Debug Read Register, offset: 0x13C */ + __I uint32_t DBGAHBMREAD; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */ + __I uint32_t DBGAHBMREAD_SET; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */ + __I uint32_t DBGAHBMREAD_CLR; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */ + __I uint32_t DBGAHBMREAD_TOG; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */ + __I uint32_t BLOCKNAME; /**< Block Name Register, offset: 0x150 */ + __I uint32_t BLOCKNAME_SET; /**< Block Name Register, offset: 0x154 */ + __I uint32_t BLOCKNAME_CLR; /**< Block Name Register, offset: 0x158 */ + __I uint32_t BLOCKNAME_TOG; /**< Block Name Register, offset: 0x15C */ + __I uint32_t VERSION; /**< BCH Version Register, offset: 0x160 */ + __I uint32_t VERSION_SET; /**< BCH Version Register, offset: 0x164 */ + __I uint32_t VERSION_CLR; /**< BCH Version Register, offset: 0x168 */ + __I uint32_t VERSION_TOG; /**< BCH Version Register, offset: 0x16C */ + __IO uint32_t DEBUG1; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */ + __IO uint32_t DEBUG1_SET; /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */ + __IO uint32_t DEBUG1_CLR; /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */ + __IO uint32_t DEBUG1_TOG; /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */ +} BCH_Type; + +/* ---------------------------------------------------------------------------- + -- BCH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BCH_Register_Masks BCH Register Masks + * @{ + */ + +/*! @name CTRL - Hardware BCH ECC Accelerator Control Register */ +#define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK) +#define BCH_CTRL_RSVD0_MASK (0x2U) +#define BCH_CTRL_RSVD0_SHIFT (1U) +#define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK) +#define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK) +#define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK) +#define BCH_CTRL_RSVD1_MASK (0xF0U) +#define BCH_CTRL_RSVD1_SHIFT (4U) +#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK) +#define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK) +#define BCH_CTRL_RSVD2_MASK (0x200U) +#define BCH_CTRL_RSVD2_SHIFT (9U) +#define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK) +#define BCH_CTRL_RSVD3_MASK (0xF800U) +#define BCH_CTRL_RSVD3_SHIFT (11U) +#define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK) +#define BCH_CTRL_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK) +#define BCH_CTRL_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK) +#define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK) +#define BCH_CTRL_RSVD4_MASK (0x300000U) +#define BCH_CTRL_RSVD4_SHIFT (20U) +#define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK) +#define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK) +#define BCH_CTRL_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_RSVD5_SHIFT (23U) +#define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK) +#define BCH_CTRL_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_CLKGATE_SHIFT (30U) +#define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK) +#define BCH_CTRL_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_SFTRST_SHIFT (31U) +#define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK) + +/*! @name CTRL_SET - Hardware BCH ECC Accelerator Control Register */ +#define BCH_CTRL_SET_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_SET_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_SET_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_MASK) +#define BCH_CTRL_SET_RSVD0_MASK (0x2U) +#define BCH_CTRL_SET_RSVD0_SHIFT (1U) +#define BCH_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD0_SHIFT)) & BCH_CTRL_SET_RSVD0_MASK) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK) +#define BCH_CTRL_SET_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_SET_BM_ERROR_IRQ_MASK) +#define BCH_CTRL_SET_RSVD1_MASK (0xF0U) +#define BCH_CTRL_SET_RSVD1_SHIFT (4U) +#define BCH_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD1_SHIFT)) & BCH_CTRL_SET_RSVD1_MASK) +#define BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_SET_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK) +#define BCH_CTRL_SET_RSVD2_MASK (0x200U) +#define BCH_CTRL_SET_RSVD2_SHIFT (9U) +#define BCH_CTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD2_SHIFT)) & BCH_CTRL_SET_RSVD2_MASK) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK) +#define BCH_CTRL_SET_RSVD3_MASK (0xF800U) +#define BCH_CTRL_SET_RSVD3_SHIFT (11U) +#define BCH_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD3_SHIFT)) & BCH_CTRL_SET_RSVD3_MASK) +#define BCH_CTRL_SET_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_SET_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_SET_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENABLE_SHIFT)) & BCH_CTRL_SET_M2M_ENABLE_MASK) +#define BCH_CTRL_SET_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_SET_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_SET_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENCODE_SHIFT)) & BCH_CTRL_SET_M2M_ENCODE_MASK) +#define BCH_CTRL_SET_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_SET_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_SET_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_LAYOUT_SHIFT)) & BCH_CTRL_SET_M2M_LAYOUT_MASK) +#define BCH_CTRL_SET_RSVD4_MASK (0x300000U) +#define BCH_CTRL_SET_RSVD4_SHIFT (20U) +#define BCH_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD4_SHIFT)) & BCH_CTRL_SET_RSVD4_MASK) +#define BCH_CTRL_SET_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_SET_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_SET_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_SET_DEBUGSYNDROME_MASK) +#define BCH_CTRL_SET_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_SET_RSVD5_SHIFT (23U) +#define BCH_CTRL_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD5_SHIFT)) & BCH_CTRL_SET_RSVD5_MASK) +#define BCH_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_SET_CLKGATE_SHIFT (30U) +#define BCH_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_CLKGATE_SHIFT)) & BCH_CTRL_SET_CLKGATE_MASK) +#define BCH_CTRL_SET_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_SET_SFTRST_SHIFT (31U) +#define BCH_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_SFTRST_SHIFT)) & BCH_CTRL_SET_SFTRST_MASK) + +/*! @name CTRL_CLR - Hardware BCH ECC Accelerator Control Register */ +#define BCH_CTRL_CLR_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_CLR_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_MASK) +#define BCH_CTRL_CLR_RSVD0_MASK (0x2U) +#define BCH_CTRL_CLR_RSVD0_SHIFT (1U) +#define BCH_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD0_SHIFT)) & BCH_CTRL_CLR_RSVD0_MASK) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK) +#define BCH_CTRL_CLR_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_CLR_BM_ERROR_IRQ_MASK) +#define BCH_CTRL_CLR_RSVD1_MASK (0xF0U) +#define BCH_CTRL_CLR_RSVD1_SHIFT (4U) +#define BCH_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD1_SHIFT)) & BCH_CTRL_CLR_RSVD1_MASK) +#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_CLR_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK) +#define BCH_CTRL_CLR_RSVD2_MASK (0x200U) +#define BCH_CTRL_CLR_RSVD2_SHIFT (9U) +#define BCH_CTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD2_SHIFT)) & BCH_CTRL_CLR_RSVD2_MASK) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK) +#define BCH_CTRL_CLR_RSVD3_MASK (0xF800U) +#define BCH_CTRL_CLR_RSVD3_SHIFT (11U) +#define BCH_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD3_SHIFT)) & BCH_CTRL_CLR_RSVD3_MASK) +#define BCH_CTRL_CLR_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_CLR_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_CLR_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENABLE_SHIFT)) & BCH_CTRL_CLR_M2M_ENABLE_MASK) +#define BCH_CTRL_CLR_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_CLR_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_CLR_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENCODE_SHIFT)) & BCH_CTRL_CLR_M2M_ENCODE_MASK) +#define BCH_CTRL_CLR_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_CLR_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_CLR_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_LAYOUT_SHIFT)) & BCH_CTRL_CLR_M2M_LAYOUT_MASK) +#define BCH_CTRL_CLR_RSVD4_MASK (0x300000U) +#define BCH_CTRL_CLR_RSVD4_SHIFT (20U) +#define BCH_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD4_SHIFT)) & BCH_CTRL_CLR_RSVD4_MASK) +#define BCH_CTRL_CLR_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_CLR_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_CLR_DEBUGSYNDROME_MASK) +#define BCH_CTRL_CLR_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_CLR_RSVD5_SHIFT (23U) +#define BCH_CTRL_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD5_SHIFT)) & BCH_CTRL_CLR_RSVD5_MASK) +#define BCH_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_CLR_CLKGATE_SHIFT (30U) +#define BCH_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_CLKGATE_SHIFT)) & BCH_CTRL_CLR_CLKGATE_MASK) +#define BCH_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_CLR_SFTRST_SHIFT (31U) +#define BCH_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_SFTRST_SHIFT)) & BCH_CTRL_CLR_SFTRST_MASK) + +/*! @name CTRL_TOG - Hardware BCH ECC Accelerator Control Register */ +#define BCH_CTRL_TOG_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_TOG_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_MASK) +#define BCH_CTRL_TOG_RSVD0_MASK (0x2U) +#define BCH_CTRL_TOG_RSVD0_SHIFT (1U) +#define BCH_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD0_SHIFT)) & BCH_CTRL_TOG_RSVD0_MASK) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK) +#define BCH_CTRL_TOG_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_TOG_BM_ERROR_IRQ_MASK) +#define BCH_CTRL_TOG_RSVD1_MASK (0xF0U) +#define BCH_CTRL_TOG_RSVD1_SHIFT (4U) +#define BCH_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD1_SHIFT)) & BCH_CTRL_TOG_RSVD1_MASK) +#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_TOG_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK) +#define BCH_CTRL_TOG_RSVD2_MASK (0x200U) +#define BCH_CTRL_TOG_RSVD2_SHIFT (9U) +#define BCH_CTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD2_SHIFT)) & BCH_CTRL_TOG_RSVD2_MASK) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK) +#define BCH_CTRL_TOG_RSVD3_MASK (0xF800U) +#define BCH_CTRL_TOG_RSVD3_SHIFT (11U) +#define BCH_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD3_SHIFT)) & BCH_CTRL_TOG_RSVD3_MASK) +#define BCH_CTRL_TOG_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_TOG_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_TOG_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENABLE_SHIFT)) & BCH_CTRL_TOG_M2M_ENABLE_MASK) +#define BCH_CTRL_TOG_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_TOG_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_TOG_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENCODE_SHIFT)) & BCH_CTRL_TOG_M2M_ENCODE_MASK) +#define BCH_CTRL_TOG_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_TOG_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_TOG_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_LAYOUT_SHIFT)) & BCH_CTRL_TOG_M2M_LAYOUT_MASK) +#define BCH_CTRL_TOG_RSVD4_MASK (0x300000U) +#define BCH_CTRL_TOG_RSVD4_SHIFT (20U) +#define BCH_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD4_SHIFT)) & BCH_CTRL_TOG_RSVD4_MASK) +#define BCH_CTRL_TOG_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_TOG_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_TOG_DEBUGSYNDROME_MASK) +#define BCH_CTRL_TOG_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_TOG_RSVD5_SHIFT (23U) +#define BCH_CTRL_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD5_SHIFT)) & BCH_CTRL_TOG_RSVD5_MASK) +#define BCH_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_TOG_CLKGATE_SHIFT (30U) +#define BCH_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_CLKGATE_SHIFT)) & BCH_CTRL_TOG_CLKGATE_MASK) +#define BCH_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_TOG_SFTRST_SHIFT (31U) +#define BCH_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_SFTRST_SHIFT)) & BCH_CTRL_TOG_SFTRST_MASK) + +/*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */ +#define BCH_STATUS0_RSVD0_MASK (0x3U) +#define BCH_STATUS0_RSVD0_SHIFT (0U) +#define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK) +#define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK) +#define BCH_STATUS0_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK) +#define BCH_STATUS0_ALLONES_MASK (0x10U) +#define BCH_STATUS0_ALLONES_SHIFT (4U) +#define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK) +#define BCH_STATUS0_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_RSVD1_SHIFT (5U) +#define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK) +#define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_STATUS_BLK0_SHIFT (8U) +#define BCH_STATUS0_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK) +#define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK) +#define BCH_STATUS0_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_HANDLE_SHIFT (20U) +#define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK) + +/*! @name STATUS0_SET - Hardware ECC Accelerator Status Register 0 */ +#define BCH_STATUS0_SET_RSVD0_MASK (0x3U) +#define BCH_STATUS0_SET_RSVD0_SHIFT (0U) +#define BCH_STATUS0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_RSVD0_SHIFT)) & BCH_STATUS0_SET_RSVD0_MASK) +#define BCH_STATUS0_SET_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_SET_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_SET_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_SET_UNCORRECTABLE_MASK) +#define BCH_STATUS0_SET_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_SET_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_SET_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_CORRECTED_SHIFT)) & BCH_STATUS0_SET_CORRECTED_MASK) +#define BCH_STATUS0_SET_ALLONES_MASK (0x10U) +#define BCH_STATUS0_SET_ALLONES_SHIFT (4U) +#define BCH_STATUS0_SET_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_ALLONES_SHIFT)) & BCH_STATUS0_SET_ALLONES_MASK) +#define BCH_STATUS0_SET_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_SET_RSVD1_SHIFT (5U) +#define BCH_STATUS0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_RSVD1_SHIFT)) & BCH_STATUS0_SET_RSVD1_MASK) +#define BCH_STATUS0_SET_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_SET_STATUS_BLK0_SHIFT (8U) +#define BCH_STATUS0_SET_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_STATUS_BLK0_SHIFT)) & BCH_STATUS0_SET_STATUS_BLK0_MASK) +#define BCH_STATUS0_SET_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_SET_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_SET_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_COMPLETED_CE_SHIFT)) & BCH_STATUS0_SET_COMPLETED_CE_MASK) +#define BCH_STATUS0_SET_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_SET_HANDLE_SHIFT (20U) +#define BCH_STATUS0_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_HANDLE_SHIFT)) & BCH_STATUS0_SET_HANDLE_MASK) + +/*! @name STATUS0_CLR - Hardware ECC Accelerator Status Register 0 */ +#define BCH_STATUS0_CLR_RSVD0_MASK (0x3U) +#define BCH_STATUS0_CLR_RSVD0_SHIFT (0U) +#define BCH_STATUS0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD0_SHIFT)) & BCH_STATUS0_CLR_RSVD0_MASK) +#define BCH_STATUS0_CLR_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_CLR_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_CLR_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_CLR_UNCORRECTABLE_MASK) +#define BCH_STATUS0_CLR_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_CLR_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_CLR_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_CORRECTED_SHIFT)) & BCH_STATUS0_CLR_CORRECTED_MASK) +#define BCH_STATUS0_CLR_ALLONES_MASK (0x10U) +#define BCH_STATUS0_CLR_ALLONES_SHIFT (4U) +#define BCH_STATUS0_CLR_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_ALLONES_SHIFT)) & BCH_STATUS0_CLR_ALLONES_MASK) +#define BCH_STATUS0_CLR_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_CLR_RSVD1_SHIFT (5U) +#define BCH_STATUS0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD1_SHIFT)) & BCH_STATUS0_CLR_RSVD1_MASK) +#define BCH_STATUS0_CLR_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_CLR_STATUS_BLK0_SHIFT (8U) +#define BCH_STATUS0_CLR_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_STATUS_BLK0_SHIFT)) & BCH_STATUS0_CLR_STATUS_BLK0_MASK) +#define BCH_STATUS0_CLR_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_CLR_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_CLR_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_COMPLETED_CE_SHIFT)) & BCH_STATUS0_CLR_COMPLETED_CE_MASK) +#define BCH_STATUS0_CLR_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_CLR_HANDLE_SHIFT (20U) +#define BCH_STATUS0_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_HANDLE_SHIFT)) & BCH_STATUS0_CLR_HANDLE_MASK) + +/*! @name STATUS0_TOG - Hardware ECC Accelerator Status Register 0 */ +#define BCH_STATUS0_TOG_RSVD0_MASK (0x3U) +#define BCH_STATUS0_TOG_RSVD0_SHIFT (0U) +#define BCH_STATUS0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_RSVD0_SHIFT)) & BCH_STATUS0_TOG_RSVD0_MASK) +#define BCH_STATUS0_TOG_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_TOG_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_TOG_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_TOG_UNCORRECTABLE_MASK) +#define BCH_STATUS0_TOG_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_TOG_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_TOG_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_CORRECTED_SHIFT)) & BCH_STATUS0_TOG_CORRECTED_MASK) +#define BCH_STATUS0_TOG_ALLONES_MASK (0x10U) +#define BCH_STATUS0_TOG_ALLONES_SHIFT (4U) +#define BCH_STATUS0_TOG_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_ALLONES_SHIFT)) & BCH_STATUS0_TOG_ALLONES_MASK) +#define BCH_STATUS0_TOG_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_TOG_RSVD1_SHIFT (5U) +#define BCH_STATUS0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_RSVD1_SHIFT)) & BCH_STATUS0_TOG_RSVD1_MASK) +#define BCH_STATUS0_TOG_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_TOG_STATUS_BLK0_SHIFT (8U) +#define BCH_STATUS0_TOG_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_STATUS_BLK0_SHIFT)) & BCH_STATUS0_TOG_STATUS_BLK0_MASK) +#define BCH_STATUS0_TOG_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_TOG_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_TOG_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_COMPLETED_CE_SHIFT)) & BCH_STATUS0_TOG_COMPLETED_CE_MASK) +#define BCH_STATUS0_TOG_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_TOG_HANDLE_SHIFT (20U) +#define BCH_STATUS0_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_HANDLE_SHIFT)) & BCH_STATUS0_TOG_HANDLE_MASK) + +/*! @name MODE - Hardware ECC Accelerator Mode Register */ +#define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK) +#define BCH_MODE_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_RSVD_SHIFT (8U) +#define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK) + +/*! @name MODE_SET - Hardware ECC Accelerator Mode Register */ +#define BCH_MODE_SET_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_SET_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_SET_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_SET_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_SET_ERASE_THRESHOLD_MASK) +#define BCH_MODE_SET_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_SET_RSVD_SHIFT (8U) +#define BCH_MODE_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_SET_RSVD_SHIFT)) & BCH_MODE_SET_RSVD_MASK) + +/*! @name MODE_CLR - Hardware ECC Accelerator Mode Register */ +#define BCH_MODE_CLR_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_CLR_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_CLR_ERASE_THRESHOLD_MASK) +#define BCH_MODE_CLR_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_CLR_RSVD_SHIFT (8U) +#define BCH_MODE_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_CLR_RSVD_SHIFT)) & BCH_MODE_CLR_RSVD_MASK) + +/*! @name MODE_TOG - Hardware ECC Accelerator Mode Register */ +#define BCH_MODE_TOG_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_TOG_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_TOG_ERASE_THRESHOLD_MASK) +#define BCH_MODE_TOG_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_TOG_RSVD_SHIFT (8U) +#define BCH_MODE_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_TOG_RSVD_SHIFT)) & BCH_MODE_TOG_RSVD_MASK) + +/*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */ +#define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK) + +/*! @name ENCODEPTR_SET - Hardware BCH ECC Loopback Encode Buffer Register */ +#define BCH_ENCODEPTR_SET_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_SET_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_SET_ADDR_SHIFT)) & BCH_ENCODEPTR_SET_ADDR_MASK) + +/*! @name ENCODEPTR_CLR - Hardware BCH ECC Loopback Encode Buffer Register */ +#define BCH_ENCODEPTR_CLR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_CLR_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_CLR_ADDR_SHIFT)) & BCH_ENCODEPTR_CLR_ADDR_MASK) + +/*! @name ENCODEPTR_TOG - Hardware BCH ECC Loopback Encode Buffer Register */ +#define BCH_ENCODEPTR_TOG_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_TOG_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_TOG_ADDR_SHIFT)) & BCH_ENCODEPTR_TOG_ADDR_MASK) + +/*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */ +#define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_ADDR_SHIFT (0U) +#define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK) + +/*! @name DATAPTR_SET - Hardware BCH ECC Loopback Data Buffer Register */ +#define BCH_DATAPTR_SET_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_SET_ADDR_SHIFT (0U) +#define BCH_DATAPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_SET_ADDR_SHIFT)) & BCH_DATAPTR_SET_ADDR_MASK) + +/*! @name DATAPTR_CLR - Hardware BCH ECC Loopback Data Buffer Register */ +#define BCH_DATAPTR_CLR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_CLR_ADDR_SHIFT (0U) +#define BCH_DATAPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_CLR_ADDR_SHIFT)) & BCH_DATAPTR_CLR_ADDR_MASK) + +/*! @name DATAPTR_TOG - Hardware BCH ECC Loopback Data Buffer Register */ +#define BCH_DATAPTR_TOG_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_TOG_ADDR_SHIFT (0U) +#define BCH_DATAPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_TOG_ADDR_SHIFT)) & BCH_DATAPTR_TOG_ADDR_MASK) + +/*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */ +#define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_ADDR_SHIFT (0U) +#define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK) + +/*! @name METAPTR_SET - Hardware BCH ECC Loopback Metadata Buffer Register */ +#define BCH_METAPTR_SET_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_SET_ADDR_SHIFT (0U) +#define BCH_METAPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_SET_ADDR_SHIFT)) & BCH_METAPTR_SET_ADDR_MASK) + +/*! @name METAPTR_CLR - Hardware BCH ECC Loopback Metadata Buffer Register */ +#define BCH_METAPTR_CLR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_CLR_ADDR_SHIFT (0U) +#define BCH_METAPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_CLR_ADDR_SHIFT)) & BCH_METAPTR_CLR_ADDR_MASK) + +/*! @name METAPTR_TOG - Hardware BCH ECC Loopback Metadata Buffer Register */ +#define BCH_METAPTR_TOG_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_TOG_ADDR_SHIFT (0U) +#define BCH_METAPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_TOG_ADDR_SHIFT)) & BCH_METAPTR_TOG_ADDR_MASK) + +/*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */ +#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK) + +/*! @name LAYOUTSELECT_SET - Hardware ECC Accelerator Layout Select Register */ +#define BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_SET_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_SET_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_SET_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_SET_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_SET_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_SET_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_SET_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_SET_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_SET_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_SET_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_SET_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_SET_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_SET_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_SET_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_SET_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_SET_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK) + +/*! @name LAYOUTSELECT_CLR - Hardware ECC Accelerator Layout Select Register */ +#define BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_CLR_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_CLR_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_CLR_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_CLR_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_CLR_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_CLR_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_CLR_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_CLR_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_CLR_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_CLR_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_CLR_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_CLR_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_CLR_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_CLR_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_CLR_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_CLR_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK) + +/*! @name LAYOUTSELECT_TOG - Hardware ECC Accelerator Layout Select Register */ +#define BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_TOG_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_TOG_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_TOG_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_TOG_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_TOG_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_TOG_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_TOG_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_TOG_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_TOG_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_TOG_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_TOG_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_TOG_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_TOG_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_TOG_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_TOG_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_TOG_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK) + +/*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */ +#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_ECC0_SHIFT (11U) +#define BCH_FLASH0LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK) + +/*! @name FLASH0LAYOUT0_SET - Hardware BCH ECC Flash 0 Layout 0 Register */ +#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT (11U) +#define BCH_FLASH0LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK) + +/*! @name FLASH0LAYOUT0_CLR - Hardware BCH ECC Flash 0 Layout 0 Register */ +#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT (11U) +#define BCH_FLASH0LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK) + +/*! @name FLASH0LAYOUT0_TOG - Hardware BCH ECC Flash 0 Layout 0 Register */ +#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT (11U) +#define BCH_FLASH0LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK) + +/*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */ +#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_ECCN_SHIFT (11U) +#define BCH_FLASH0LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK) + +/*! @name FLASH0LAYOUT1_SET - Hardware BCH ECC Flash 0 Layout 1 Register */ +#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT (11U) +#define BCH_FLASH0LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK) + +/*! @name FLASH0LAYOUT1_CLR - Hardware BCH ECC Flash 0 Layout 1 Register */ +#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT (11U) +#define BCH_FLASH0LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK) + +/*! @name FLASH0LAYOUT1_TOG - Hardware BCH ECC Flash 0 Layout 1 Register */ +#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT (11U) +#define BCH_FLASH0LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK) + +/*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */ +#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_ECC0_SHIFT (11U) +#define BCH_FLASH1LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK) + +/*! @name FLASH1LAYOUT0_SET - Hardware BCH ECC Flash 1 Layout 0 Register */ +#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT (11U) +#define BCH_FLASH1LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK) + +/*! @name FLASH1LAYOUT0_CLR - Hardware BCH ECC Flash 1 Layout 0 Register */ +#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT (11U) +#define BCH_FLASH1LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK) + +/*! @name FLASH1LAYOUT0_TOG - Hardware BCH ECC Flash 1 Layout 0 Register */ +#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT (11U) +#define BCH_FLASH1LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK) + +/*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */ +#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_ECCN_SHIFT (11U) +#define BCH_FLASH1LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK) + +/*! @name FLASH1LAYOUT1_SET - Hardware BCH ECC Flash 1 Layout 1 Register */ +#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT (11U) +#define BCH_FLASH1LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK) + +/*! @name FLASH1LAYOUT1_CLR - Hardware BCH ECC Flash 1 Layout 1 Register */ +#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT (11U) +#define BCH_FLASH1LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK) + +/*! @name FLASH1LAYOUT1_TOG - Hardware BCH ECC Flash 1 Layout 1 Register */ +#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT (11U) +#define BCH_FLASH1LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK) + +/*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */ +#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_ECC0_SHIFT (11U) +#define BCH_FLASH2LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK) + +/*! @name FLASH2LAYOUT0_SET - Hardware BCH ECC Flash 2 Layout 0 Register */ +#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT (11U) +#define BCH_FLASH2LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK) + +/*! @name FLASH2LAYOUT0_CLR - Hardware BCH ECC Flash 2 Layout 0 Register */ +#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT (11U) +#define BCH_FLASH2LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK) + +/*! @name FLASH2LAYOUT0_TOG - Hardware BCH ECC Flash 2 Layout 0 Register */ +#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT (11U) +#define BCH_FLASH2LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK) + +/*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */ +#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_ECCN_SHIFT (11U) +#define BCH_FLASH2LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK) + +/*! @name FLASH2LAYOUT1_SET - Hardware BCH ECC Flash 2 Layout 1 Register */ +#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT (11U) +#define BCH_FLASH2LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK) + +/*! @name FLASH2LAYOUT1_CLR - Hardware BCH ECC Flash 2 Layout 1 Register */ +#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT (11U) +#define BCH_FLASH2LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK) + +/*! @name FLASH2LAYOUT1_TOG - Hardware BCH ECC Flash 2 Layout 1 Register */ +#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT (11U) +#define BCH_FLASH2LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK) + +/*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */ +#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_ECC0_SHIFT (11U) +#define BCH_FLASH3LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK) + +/*! @name FLASH3LAYOUT0_SET - Hardware BCH ECC Flash 3 Layout 0 Register */ +#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT (11U) +#define BCH_FLASH3LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK) + +/*! @name FLASH3LAYOUT0_CLR - Hardware BCH ECC Flash 3 Layout 0 Register */ +#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT (11U) +#define BCH_FLASH3LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK) + +/*! @name FLASH3LAYOUT0_TOG - Hardware BCH ECC Flash 3 Layout 0 Register */ +#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT (11U) +#define BCH_FLASH3LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK) + +/*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */ +#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_ECCN_SHIFT (11U) +#define BCH_FLASH3LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK) + +/*! @name FLASH3LAYOUT1_SET - Hardware BCH ECC Flash 3 Layout 1 Register */ +#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT (11U) +#define BCH_FLASH3LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK) + +/*! @name FLASH3LAYOUT1_CLR - Hardware BCH ECC Flash 3 Layout 1 Register */ +#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT (11U) +#define BCH_FLASH3LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK) + +/*! @name FLASH3LAYOUT1_TOG - Hardware BCH ECC Flash 3 Layout 1 Register */ +#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT (11U) +#define BCH_FLASH3LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK) + +/*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */ +#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_RSVD0_SHIFT (6U) +#define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT (8U) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK) +#define BCH_DEBUG0_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT (9U) +#define BCH_DEBUG0_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK) +#define BCH_DEBUG0_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK) +#define BCH_DEBUG0_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_KES_STANDALONE_SHIFT (11U) +#define BCH_DEBUG0_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK) +#define BCH_DEBUG0_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK) +#define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT (13U) +#define BCH_DEBUG0_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK) +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_RSVD1_SHIFT (25U) +#define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK) + +/*! @name DEBUG0_SET - Hardware BCH ECC Debug Register0 */ +#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_SET_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_SET_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_SET_RSVD0_SHIFT (6U) +#define BCH_DEBUG0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD0_SHIFT)) & BCH_DEBUG0_SET_RSVD0_MASK) +#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT (8U) +#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT (9U) +#define BCH_DEBUG0_SET_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_SET_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK) +#define BCH_DEBUG0_SET_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_SET_KES_STANDALONE_SHIFT (11U) +#define BCH_DEBUG0_SET_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_SET_KES_STANDALONE_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_SET_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT (13U) +#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_SET_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_SET_RSVD1_SHIFT (25U) +#define BCH_DEBUG0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD1_SHIFT)) & BCH_DEBUG0_SET_RSVD1_MASK) + +/*! @name DEBUG0_CLR - Hardware BCH ECC Debug Register0 */ +#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_CLR_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_CLR_RSVD0_SHIFT (6U) +#define BCH_DEBUG0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD0_SHIFT)) & BCH_DEBUG0_CLR_RSVD0_MASK) +#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT (8U) +#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT (9U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK) +#define BCH_DEBUG0_CLR_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT (11U) +#define BCH_DEBUG0_CLR_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_CLR_KES_STANDALONE_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_CLR_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT (13U) +#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_CLR_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_CLR_RSVD1_SHIFT (25U) +#define BCH_DEBUG0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD1_SHIFT)) & BCH_DEBUG0_CLR_RSVD1_MASK) + +/*! @name DEBUG0_TOG - Hardware BCH ECC Debug Register0 */ +#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_TOG_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_TOG_RSVD0_SHIFT (6U) +#define BCH_DEBUG0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD0_SHIFT)) & BCH_DEBUG0_TOG_RSVD0_MASK) +#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT (8U) +#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT (9U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK) +#define BCH_DEBUG0_TOG_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT (11U) +#define BCH_DEBUG0_TOG_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_TOG_KES_STANDALONE_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_TOG_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT (13U) +#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_TOG_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_TOG_RSVD1_SHIFT (25U) +#define BCH_DEBUG0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD1_SHIFT)) & BCH_DEBUG0_TOG_RSVD1_MASK) + +/*! @name DBGKESREAD - KES Debug Read Register */ +#define BCH_DBGKESREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK) + +/*! @name DBGKESREAD_SET - KES Debug Read Register */ +#define BCH_DBGKESREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_SET_VALUES_SHIFT)) & BCH_DBGKESREAD_SET_VALUES_MASK) + +/*! @name DBGKESREAD_CLR - KES Debug Read Register */ +#define BCH_DBGKESREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_CLR_VALUES_SHIFT)) & BCH_DBGKESREAD_CLR_VALUES_MASK) + +/*! @name DBGKESREAD_TOG - KES Debug Read Register */ +#define BCH_DBGKESREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_TOG_VALUES_SHIFT)) & BCH_DBGKESREAD_TOG_VALUES_MASK) + +/*! @name DBGCSFEREAD - Chien Search Debug Read Register */ +#define BCH_DBGCSFEREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK) + +/*! @name DBGCSFEREAD_SET - Chien Search Debug Read Register */ +#define BCH_DBGCSFEREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_SET_VALUES_SHIFT)) & BCH_DBGCSFEREAD_SET_VALUES_MASK) + +/*! @name DBGCSFEREAD_CLR - Chien Search Debug Read Register */ +#define BCH_DBGCSFEREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_CLR_VALUES_SHIFT)) & BCH_DBGCSFEREAD_CLR_VALUES_MASK) + +/*! @name DBGCSFEREAD_TOG - Chien Search Debug Read Register */ +#define BCH_DBGCSFEREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_TOG_VALUES_SHIFT)) & BCH_DBGCSFEREAD_TOG_VALUES_MASK) + +/*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */ +#define BCH_DBGSYNDGENREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK) + +/*! @name DBGSYNDGENREAD_SET - Syndrome Generator Debug Read Register */ +#define BCH_DBGSYNDGENREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_SET_VALUES_MASK) + +/*! @name DBGSYNDGENREAD_CLR - Syndrome Generator Debug Read Register */ +#define BCH_DBGSYNDGENREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_CLR_VALUES_MASK) + +/*! @name DBGSYNDGENREAD_TOG - Syndrome Generator Debug Read Register */ +#define BCH_DBGSYNDGENREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_TOG_VALUES_MASK) + +/*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */ +#define BCH_DBGAHBMREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK) + +/*! @name DBGAHBMREAD_SET - Bus Master and ECC Controller Debug Read Register */ +#define BCH_DBGAHBMREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_SET_VALUES_SHIFT)) & BCH_DBGAHBMREAD_SET_VALUES_MASK) + +/*! @name DBGAHBMREAD_CLR - Bus Master and ECC Controller Debug Read Register */ +#define BCH_DBGAHBMREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_CLR_VALUES_SHIFT)) & BCH_DBGAHBMREAD_CLR_VALUES_MASK) + +/*! @name DBGAHBMREAD_TOG - Bus Master and ECC Controller Debug Read Register */ +#define BCH_DBGAHBMREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_TOG_VALUES_SHIFT)) & BCH_DBGAHBMREAD_TOG_VALUES_MASK) + +/*! @name BLOCKNAME - Block Name Register */ +#define BCH_BLOCKNAME_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK) + +/*! @name BLOCKNAME_SET - Block Name Register */ +#define BCH_BLOCKNAME_SET_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_SET_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_SET_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_SET_NAME_SHIFT)) & BCH_BLOCKNAME_SET_NAME_MASK) + +/*! @name BLOCKNAME_CLR - Block Name Register */ +#define BCH_BLOCKNAME_CLR_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_CLR_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_CLR_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_CLR_NAME_SHIFT)) & BCH_BLOCKNAME_CLR_NAME_MASK) + +/*! @name BLOCKNAME_TOG - Block Name Register */ +#define BCH_BLOCKNAME_TOG_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_TOG_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_TOG_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_TOG_NAME_SHIFT)) & BCH_BLOCKNAME_TOG_NAME_MASK) + +/*! @name VERSION - BCH Version Register */ +#define BCH_VERSION_STEP_MASK (0xFFFFU) +#define BCH_VERSION_STEP_SHIFT (0U) +#define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK) +#define BCH_VERSION_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_MINOR_SHIFT (16U) +#define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK) +#define BCH_VERSION_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_MAJOR_SHIFT (24U) +#define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK) + +/*! @name VERSION_SET - BCH Version Register */ +#define BCH_VERSION_SET_STEP_MASK (0xFFFFU) +#define BCH_VERSION_SET_STEP_SHIFT (0U) +#define BCH_VERSION_SET_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_STEP_SHIFT)) & BCH_VERSION_SET_STEP_MASK) +#define BCH_VERSION_SET_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_SET_MINOR_SHIFT (16U) +#define BCH_VERSION_SET_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_MINOR_SHIFT)) & BCH_VERSION_SET_MINOR_MASK) +#define BCH_VERSION_SET_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_SET_MAJOR_SHIFT (24U) +#define BCH_VERSION_SET_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_MAJOR_SHIFT)) & BCH_VERSION_SET_MAJOR_MASK) + +/*! @name VERSION_CLR - BCH Version Register */ +#define BCH_VERSION_CLR_STEP_MASK (0xFFFFU) +#define BCH_VERSION_CLR_STEP_SHIFT (0U) +#define BCH_VERSION_CLR_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_STEP_SHIFT)) & BCH_VERSION_CLR_STEP_MASK) +#define BCH_VERSION_CLR_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_CLR_MINOR_SHIFT (16U) +#define BCH_VERSION_CLR_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_MINOR_SHIFT)) & BCH_VERSION_CLR_MINOR_MASK) +#define BCH_VERSION_CLR_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_CLR_MAJOR_SHIFT (24U) +#define BCH_VERSION_CLR_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_MAJOR_SHIFT)) & BCH_VERSION_CLR_MAJOR_MASK) + +/*! @name VERSION_TOG - BCH Version Register */ +#define BCH_VERSION_TOG_STEP_MASK (0xFFFFU) +#define BCH_VERSION_TOG_STEP_SHIFT (0U) +#define BCH_VERSION_TOG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_STEP_SHIFT)) & BCH_VERSION_TOG_STEP_MASK) +#define BCH_VERSION_TOG_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_TOG_MINOR_SHIFT (16U) +#define BCH_VERSION_TOG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_MINOR_SHIFT)) & BCH_VERSION_TOG_MINOR_MASK) +#define BCH_VERSION_TOG_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_TOG_MAJOR_SHIFT (24U) +#define BCH_VERSION_TOG_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_MAJOR_SHIFT)) & BCH_VERSION_TOG_MAJOR_MASK) + +/*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */ +#define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_RSVD_SHIFT (9U) +#define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK) +#define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT (31U) +#define BCH_DEBUG1_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK) + +/*! @name DEBUG1_SET - Hardware BCH ECC Debug Register 1 */ +#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_SET_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_SET_RSVD_SHIFT (9U) +#define BCH_DEBUG1_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_RSVD_SHIFT)) & BCH_DEBUG1_SET_RSVD_MASK) +#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_SHIFT (31U) +#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_SET_DEBUG1_PREERASECHK_MASK) + +/*! @name DEBUG1_CLR - Hardware BCH ECC Debug Register 1 */ +#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_CLR_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_CLR_RSVD_SHIFT (9U) +#define BCH_DEBUG1_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_RSVD_SHIFT)) & BCH_DEBUG1_CLR_RSVD_MASK) +#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_SHIFT (31U) +#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_MASK) + +/*! @name DEBUG1_TOG - Hardware BCH ECC Debug Register 1 */ +#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_TOG_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_TOG_RSVD_SHIFT (9U) +#define BCH_DEBUG1_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_RSVD_SHIFT)) & BCH_DEBUG1_TOG_RSVD_MASK) +#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_SHIFT (31U) +#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_MASK) + + +/*! + * @} + */ /* end of group BCH_Register_Masks */ + + +/* BCH - Peripheral instance base addresses */ +/** Peripheral BCH base address */ +#define BCH_BASE (0x1808000u) +/** Peripheral BCH base pointer */ +#define BCH ((BCH_Type *)BCH_BASE) +/** Array initializer of BCH peripheral base addresses */ +#define BCH_BASE_ADDRS { BCH_BASE } +/** Array initializer of BCH peripheral base pointers */ +#define BCH_BASE_PTRS { BCH } +/** Interrupt vectors for the BCH peripheral type */ +#define BCH_IRQS { RAWNAND_BCH_IRQn } + +/*! + * @} + */ /* end of group BCH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free Running Timer Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ + __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ + __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ + __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */ + __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ + uint8_t RESERVED_1[8]; + __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */ + __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ + uint8_t RESERVED_2[48]; + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ + __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ + } MB[64]; + uint8_t RESERVED_3[1024]; + __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_4[96]; + __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +#define CAN_MCR_MAXMB_MASK (0x7FU) +#define CAN_MCR_MAXMB_SHIFT (0U) +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) +#define CAN_MCR_IDAM_MASK (0x300U) +#define CAN_MCR_IDAM_SHIFT (8U) +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) +#define CAN_MCR_AEN_MASK (0x1000U) +#define CAN_MCR_AEN_SHIFT (12U) +#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) +#define CAN_MCR_LPRIOEN_MASK (0x2000U) +#define CAN_MCR_LPRIOEN_SHIFT (13U) +#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) +#define CAN_MCR_IRMQ_MASK (0x10000U) +#define CAN_MCR_IRMQ_SHIFT (16U) +#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) +#define CAN_MCR_SRXDIS_MASK (0x20000U) +#define CAN_MCR_SRXDIS_SHIFT (17U) +#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) +#define CAN_MCR_WAKSRC_MASK (0x80000U) +#define CAN_MCR_WAKSRC_SHIFT (19U) +#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) +#define CAN_MCR_LPMACK_MASK (0x100000U) +#define CAN_MCR_LPMACK_SHIFT (20U) +#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) +#define CAN_MCR_WRNEN_MASK (0x200000U) +#define CAN_MCR_WRNEN_SHIFT (21U) +#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) +#define CAN_MCR_SLFWAK_MASK (0x400000U) +#define CAN_MCR_SLFWAK_SHIFT (22U) +#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) +#define CAN_MCR_SUPV_MASK (0x800000U) +#define CAN_MCR_SUPV_SHIFT (23U) +#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) +#define CAN_MCR_FRZACK_MASK (0x1000000U) +#define CAN_MCR_FRZACK_SHIFT (24U) +#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) +#define CAN_MCR_SOFTRST_MASK (0x2000000U) +#define CAN_MCR_SOFTRST_SHIFT (25U) +#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) +#define CAN_MCR_WAKMSK_MASK (0x4000000U) +#define CAN_MCR_WAKMSK_SHIFT (26U) +#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) +#define CAN_MCR_NOTRDY_MASK (0x8000000U) +#define CAN_MCR_NOTRDY_SHIFT (27U) +#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) +#define CAN_MCR_HALT_MASK (0x10000000U) +#define CAN_MCR_HALT_SHIFT (28U) +#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) +#define CAN_MCR_RFEN_MASK (0x20000000U) +#define CAN_MCR_RFEN_SHIFT (29U) +#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) +#define CAN_MCR_FRZ_MASK (0x40000000U) +#define CAN_MCR_FRZ_SHIFT (30U) +#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) +#define CAN_MCR_MDIS_MASK (0x80000000U) +#define CAN_MCR_MDIS_SHIFT (31U) +#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) + +/*! @name CTRL1 - Control 1 Register */ +#define CAN_CTRL1_PROPSEG_MASK (0x7U) +#define CAN_CTRL1_PROPSEG_SHIFT (0U) +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) +#define CAN_CTRL1_LOM_MASK (0x8U) +#define CAN_CTRL1_LOM_SHIFT (3U) +#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) +#define CAN_CTRL1_LBUF_MASK (0x10U) +#define CAN_CTRL1_LBUF_SHIFT (4U) +#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) +#define CAN_CTRL1_TSYN_MASK (0x20U) +#define CAN_CTRL1_TSYN_SHIFT (5U) +#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) +#define CAN_CTRL1_BOFFREC_MASK (0x40U) +#define CAN_CTRL1_BOFFREC_SHIFT (6U) +#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) +#define CAN_CTRL1_SMP_MASK (0x80U) +#define CAN_CTRL1_SMP_SHIFT (7U) +#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) +#define CAN_CTRL1_RWRNMSK_MASK (0x400U) +#define CAN_CTRL1_RWRNMSK_SHIFT (10U) +#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) +#define CAN_CTRL1_TWRNMSK_MASK (0x800U) +#define CAN_CTRL1_TWRNMSK_SHIFT (11U) +#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) +#define CAN_CTRL1_LPB_MASK (0x1000U) +#define CAN_CTRL1_LPB_SHIFT (12U) +#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) +#define CAN_CTRL1_ERRMSK_MASK (0x4000U) +#define CAN_CTRL1_ERRMSK_SHIFT (14U) +#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) +#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) +#define CAN_CTRL1_BOFFMSK_SHIFT (15U) +#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) +#define CAN_CTRL1_PSEG2_MASK (0x70000U) +#define CAN_CTRL1_PSEG2_SHIFT (16U) +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) +#define CAN_CTRL1_PSEG1_MASK (0x380000U) +#define CAN_CTRL1_PSEG1_SHIFT (19U) +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) +#define CAN_CTRL1_RJW_MASK (0xC00000U) +#define CAN_CTRL1_RJW_SHIFT (22U) +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) +#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) +#define CAN_CTRL1_PRESDIV_SHIFT (24U) +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) + +/*! @name TIMER - Free Running Timer Register */ +#define CAN_TIMER_TIMER_MASK (0xFFFFU) +#define CAN_TIMER_TIMER_SHIFT (0U) +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) + +/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) +#define CAN_RXMGMASK_MG_SHIFT (0U) +#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) + +/*! @name RX14MASK - Rx Buffer 14 Mask Register */ +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) +#define CAN_RX14MASK_RX14M_SHIFT (0U) +#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) + +/*! @name RX15MASK - Rx Buffer 15 Mask Register */ +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) +#define CAN_RX15MASK_RX15M_SHIFT (0U) +#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) + +/*! @name ECR - Error Counter Register */ +#define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU) +#define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U) +#define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK) +#define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U) +#define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U) +#define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK) + +/*! @name ESR1 - Error and Status 1 Register */ +#define CAN_ESR1_WAKINT_MASK (0x1U) +#define CAN_ESR1_WAKINT_SHIFT (0U) +#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) +#define CAN_ESR1_ERRINT_MASK (0x2U) +#define CAN_ESR1_ERRINT_SHIFT (1U) +#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) +#define CAN_ESR1_BOFFINT_MASK (0x4U) +#define CAN_ESR1_BOFFINT_SHIFT (2U) +#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) +#define CAN_ESR1_RX_MASK (0x8U) +#define CAN_ESR1_RX_SHIFT (3U) +#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) +#define CAN_ESR1_FLTCONF_MASK (0x30U) +#define CAN_ESR1_FLTCONF_SHIFT (4U) +#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) +#define CAN_ESR1_TX_MASK (0x40U) +#define CAN_ESR1_TX_SHIFT (6U) +#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) +#define CAN_ESR1_IDLE_MASK (0x80U) +#define CAN_ESR1_IDLE_SHIFT (7U) +#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) +#define CAN_ESR1_RXWRN_MASK (0x100U) +#define CAN_ESR1_RXWRN_SHIFT (8U) +#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) +#define CAN_ESR1_TXWRN_MASK (0x200U) +#define CAN_ESR1_TXWRN_SHIFT (9U) +#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) +#define CAN_ESR1_STFERR_MASK (0x400U) +#define CAN_ESR1_STFERR_SHIFT (10U) +#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) +#define CAN_ESR1_FRMERR_MASK (0x800U) +#define CAN_ESR1_FRMERR_SHIFT (11U) +#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) +#define CAN_ESR1_CRCERR_MASK (0x1000U) +#define CAN_ESR1_CRCERR_SHIFT (12U) +#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) +#define CAN_ESR1_ACKERR_MASK (0x2000U) +#define CAN_ESR1_ACKERR_SHIFT (13U) +#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) +#define CAN_ESR1_BIT0ERR_MASK (0x4000U) +#define CAN_ESR1_BIT0ERR_SHIFT (14U) +#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) +#define CAN_ESR1_BIT1ERR_MASK (0x8000U) +#define CAN_ESR1_BIT1ERR_SHIFT (15U) +#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) +#define CAN_ESR1_RWRNINT_MASK (0x10000U) +#define CAN_ESR1_RWRNINT_SHIFT (16U) +#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) +#define CAN_ESR1_TWRNINT_MASK (0x20000U) +#define CAN_ESR1_TWRNINT_SHIFT (17U) +#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) +#define CAN_ESR1_SYNCH_MASK (0x40000U) +#define CAN_ESR1_SYNCH_SHIFT (18U) +#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) + +/*! @name IMASK2 - Interrupt Masks 2 Register */ +#define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU) +#define CAN_IMASK2_BUFHM_SHIFT (0U) +#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK) + +/*! @name IMASK1 - Interrupt Masks 1 Register */ +#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUFLM_SHIFT (0U) +#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) + +/*! @name IFLAG2 - Interrupt Flags 2 Register */ +#define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU) +#define CAN_IFLAG2_BUFHI_SHIFT (0U) +#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK) + +/*! @name IFLAG1 - Interrupt Flags 1 Register */ +#define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU) +#define CAN_IFLAG1_BUF4TO0I_SHIFT (0U) +#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK) +#define CAN_IFLAG1_BUF5I_MASK (0x20U) +#define CAN_IFLAG1_BUF5I_SHIFT (5U) +#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) +#define CAN_IFLAG1_BUF6I_MASK (0x40U) +#define CAN_IFLAG1_BUF6I_SHIFT (6U) +#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) +#define CAN_IFLAG1_BUF7I_MASK (0x80U) +#define CAN_IFLAG1_BUF7I_SHIFT (7U) +#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) + +/*! @name CTRL2 - Control 2 Register */ +#define CAN_CTRL2_EACEN_MASK (0x10000U) +#define CAN_CTRL2_EACEN_SHIFT (16U) +#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) +#define CAN_CTRL2_RRS_MASK (0x20000U) +#define CAN_CTRL2_RRS_SHIFT (17U) +#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) +#define CAN_CTRL2_MRP_MASK (0x40000U) +#define CAN_CTRL2_MRP_SHIFT (18U) +#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) +#define CAN_CTRL2_TASD_MASK (0xF80000U) +#define CAN_CTRL2_TASD_SHIFT (19U) +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) +#define CAN_CTRL2_RFFN_MASK (0xF000000U) +#define CAN_CTRL2_RFFN_SHIFT (24U) +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) +#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) +#define CAN_CTRL2_WRMFRZ_SHIFT (28U) +#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) + +/*! @name ESR2 - Error and Status 2 Register */ +#define CAN_ESR2_IMB_MASK (0x2000U) +#define CAN_ESR2_IMB_SHIFT (13U) +#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) +#define CAN_ESR2_VPS_MASK (0x4000U) +#define CAN_ESR2_VPS_SHIFT (14U) +#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) +#define CAN_ESR2_LPTM_MASK (0x7F0000U) +#define CAN_ESR2_LPTM_SHIFT (16U) +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) + +/*! @name CRCR - CRC Register */ +#define CAN_CRCR_TXCRC_MASK (0x7FFFU) +#define CAN_CRCR_TXCRC_SHIFT (0U) +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) +#define CAN_CRCR_MBCRC_MASK (0x7F0000U) +#define CAN_CRCR_MBCRC_SHIFT (16U) +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) + +/*! @name RXFGMASK - Rx FIFO Global Mask Register */ +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) +#define CAN_RXFGMASK_FGM_SHIFT (0U) +#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) + +/*! @name RXFIR - Rx FIFO Information Register */ +#define CAN_RXFIR_IDHIT_MASK (0x1FFU) +#define CAN_RXFIR_IDHIT_SHIFT (0U) +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) + +/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */ +#define CAN_CS_TIME_STAMP_MASK (0xFFFFU) +#define CAN_CS_TIME_STAMP_SHIFT (0U) +#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) +#define CAN_CS_DLC_MASK (0xF0000U) +#define CAN_CS_DLC_SHIFT (16U) +#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) +#define CAN_CS_RTR_MASK (0x100000U) +#define CAN_CS_RTR_SHIFT (20U) +#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) +#define CAN_CS_IDE_MASK (0x200000U) +#define CAN_CS_IDE_SHIFT (21U) +#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) +#define CAN_CS_SRR_MASK (0x400000U) +#define CAN_CS_SRR_SHIFT (22U) +#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) +#define CAN_CS_CODE_MASK (0xF000000U) +#define CAN_CS_CODE_SHIFT (24U) +#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT (64U) + +/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */ +#define CAN_ID_EXT_MASK (0x3FFFFU) +#define CAN_ID_EXT_SHIFT (0U) +#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) +#define CAN_ID_STD_MASK (0x1FFC0000U) +#define CAN_ID_STD_SHIFT (18U) +#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) +#define CAN_ID_PRIO_MASK (0xE0000000U) +#define CAN_ID_PRIO_SHIFT (29U) +#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT (64U) + +/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */ +#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) +#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) +#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) +#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) +#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) +#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) +#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) +#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) + +/* The count of CAN_WORD0 */ +#define CAN_WORD0_COUNT (64U) + +/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */ +#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) +#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) +#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) +#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) +#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) +#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) +#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) +#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) + +/* The count of CAN_WORD1 */ +#define CAN_WORD1_COUNT (64U) + +/*! @name RXIMR - Rx Individual Mask Registers */ +#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) +#define CAN_RXIMR_MI_SHIFT (0U) +#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) + +/* The count of CAN_RXIMR */ +#define CAN_RXIMR_COUNT (64U) + +/*! @name GFWR - Glitch Filter Width Registers */ +#define CAN_GFWR_GFWR_MASK (0xFFU) +#define CAN_GFWR_GFWR_SHIFT (0U) +#define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK) + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN1 base address */ +#define CAN1_BASE (0x2090000u) +/** Peripheral CAN1 base pointer */ +#define CAN1 ((CAN_Type *)CAN1_BASE) +/** Peripheral CAN2 base address */ +#define CAN2_BASE (0x2094000u) +/** Peripheral CAN2 base pointer */ +#define CAN2 ((CAN_Type *)CAN2_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +/* Backward compatibility */ +#define CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASK +#define CAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFT +#define CAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x) +#define CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASK +#define CAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFT +#define CAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x) + + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer + * @{ + */ + +/** CCM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */ + __IO uint32_t CCDR; /**< CCM Control Divider Register, offset: 0x4 */ + __I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */ + __IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */ + __IO uint32_t CACRR; /**< CCM Arm Clock Root Register, offset: 0x10 */ + __IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */ + __IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */ + __IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */ + __IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */ + __IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */ + __IO uint32_t CS1CDR; /**< CCM SAI1 Clock Divider Register, offset: 0x28 */ + __IO uint32_t CS2CDR; /**< CCM SAI2 Clock Divider Register, offset: 0x2C */ + __IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */ + __IO uint32_t CHSCCDR; /**< CCM HSC Clock Divider Register, offset: 0x34 */ + __IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */ + __IO uint32_t CSCDR3; /**< CCM Serial Clock Divider Register 3, offset: 0x3C */ + uint8_t RESERVED_0[8]; + __I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */ + uint8_t RESERVED_1[8]; + __IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */ + __IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */ + __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ + __IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */ + __IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */ + __IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */ + __IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */ + __IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */ + __IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */ + __IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */ + __IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */ + __IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */ + uint8_t RESERVED_2[4]; + __IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */ +} CCM_Type; + +/* ---------------------------------------------------------------------------- + -- CCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Masks CCM Register Masks + * @{ + */ + +/*! @name CCR - CCM Control Register */ +#define CCM_CCR_OSCNT_MASK (0x7FU) +#define CCM_CCR_OSCNT_SHIFT (0U) +#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK) +#define CCM_CCR_COSC_EN_MASK (0x1000U) +#define CCM_CCR_COSC_EN_SHIFT (12U) +#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK) +#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U) +#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U) +#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK) +#define CCM_CCR_RBC_EN_MASK (0x8000000U) +#define CCM_CCR_RBC_EN_SHIFT (27U) +#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK) + +/*! @name CCDR - CCM Control Divider Register */ +#define CCM_CCDR_MMDC_CH1_MASK_MASK (0x10000U) +#define CCM_CCDR_MMDC_CH1_MASK_SHIFT (16U) +#define CCM_CCDR_MMDC_CH1_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCDR_MMDC_CH1_MASK_SHIFT)) & CCM_CCDR_MMDC_CH1_MASK_MASK) +#define CCM_CCDR_MMDC_CH0_MASK_MASK (0x20000U) +#define CCM_CCDR_MMDC_CH0_MASK_SHIFT (17U) +#define CCM_CCDR_MMDC_CH0_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCDR_MMDC_CH0_MASK_SHIFT)) & CCM_CCDR_MMDC_CH0_MASK_MASK) + +/*! @name CSR - CCM Status Register */ +#define CCM_CSR_REF_EN_B_MASK (0x1U) +#define CCM_CSR_REF_EN_B_SHIFT (0U) +#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK) +#define CCM_CSR_COSC_READY_MASK (0x20U) +#define CCM_CSR_COSC_READY_SHIFT (5U) +#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK) + +/*! @name CCSR - CCM Clock Switcher Register */ +#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U) +#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U) +#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK) +#define CCM_CCSR_PLL1_SW_CLK_SEL_MASK (0x4U) +#define CCM_CCSR_PLL1_SW_CLK_SEL_SHIFT (2U) +#define CCM_CCSR_PLL1_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL1_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL1_SW_CLK_SEL_MASK) +#define CCM_CCSR_SECONDARY_CLK_SEL_MASK (0x8U) +#define CCM_CCSR_SECONDARY_CLK_SEL_SHIFT (3U) +#define CCM_CCSR_SECONDARY_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_SECONDARY_CLK_SEL_SHIFT)) & CCM_CCSR_SECONDARY_CLK_SEL_MASK) +#define CCM_CCSR_STEP_SEL_MASK (0x100U) +#define CCM_CCSR_STEP_SEL_SHIFT (8U) +#define CCM_CCSR_STEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_STEP_SEL_SHIFT)) & CCM_CCSR_STEP_SEL_MASK) + +/*! @name CACRR - CCM Arm Clock Root Register */ +#define CCM_CACRR_ARM_PODF_MASK (0x7U) +#define CCM_CACRR_ARM_PODF_SHIFT (0U) +#define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK) + +/*! @name CBCDR - CCM Bus Clock Divider Register */ +#define CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7U) +#define CCM_CBCDR_PERIPH2_CLK2_PODF_SHIFT (0U) +#define CCM_CBCDR_PERIPH2_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH2_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) +#define CCM_CBCDR_FABRIC_MMDC_PODF_MASK (0x38U) +#define CCM_CBCDR_FABRIC_MMDC_PODF_SHIFT (3U) +#define CCM_CBCDR_FABRIC_MMDC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_FABRIC_MMDC_PODF_SHIFT)) & CCM_CBCDR_FABRIC_MMDC_PODF_MASK) +#define CCM_CBCDR_AXI_SEL_MASK (0x40U) +#define CCM_CBCDR_AXI_SEL_SHIFT (6U) +#define CCM_CBCDR_AXI_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AXI_SEL_SHIFT)) & CCM_CBCDR_AXI_SEL_MASK) +#define CCM_CBCDR_AXI_ALT_SEL_MASK (0x80U) +#define CCM_CBCDR_AXI_ALT_SEL_SHIFT (7U) +#define CCM_CBCDR_AXI_ALT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AXI_ALT_SEL_SHIFT)) & CCM_CBCDR_AXI_ALT_SEL_MASK) +#define CCM_CBCDR_IPG_PODF_MASK (0x300U) +#define CCM_CBCDR_IPG_PODF_SHIFT (8U) +#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK) +#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U) +#define CCM_CBCDR_AHB_PODF_SHIFT (10U) +#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK) +#define CCM_CBCDR_AXI_PODF_MASK (0x70000U) +#define CCM_CBCDR_AXI_PODF_SHIFT (16U) +#define CCM_CBCDR_AXI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AXI_PODF_SHIFT)) & CCM_CBCDR_AXI_PODF_MASK) +#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U) +#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U) +#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK) +#define CCM_CBCDR_PERIPH2_CLK_SEL_MASK (0x4000000U) +#define CCM_CBCDR_PERIPH2_CLK_SEL_SHIFT (26U) +#define CCM_CBCDR_PERIPH2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH2_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH2_CLK_SEL_MASK) +#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U) +#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U) +#define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) + +/*! @name CBCMR - CCM Bus Clock Multiplexer Register */ +#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U) +#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U) +#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) +#define CCM_CBCMR_PERIPH2_CLK2_SEL_MASK (0x100000U) +#define CCM_CBCMR_PERIPH2_CLK2_SEL_SHIFT (20U) +#define CCM_CBCMR_PERIPH2_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH2_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH2_CLK2_SEL_MASK) +#define CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x600000U) +#define CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT (21U) +#define CCM_CBCMR_PRE_PERIPH2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) +#define CCM_CBCMR_LCDIF1_PODF_MASK (0x3800000U) +#define CCM_CBCMR_LCDIF1_PODF_SHIFT (23U) +#define CCM_CBCMR_LCDIF1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF1_PODF_SHIFT)) & CCM_CBCMR_LCDIF1_PODF_MASK) + +/*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */ +#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU) +#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U) +#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK) +#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U) +#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U) +#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) +#define CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x380U) +#define CCM_CSCMR1_QSPI1_CLK_SEL_SHIFT (7U) +#define CCM_CSCMR1_QSPI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_QSPI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_QSPI1_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U) +#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U) +#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U) +#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U) +#define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U) +#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U) +#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK) +#define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U) +#define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U) +#define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK) +#define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U) +#define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U) +#define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK) +#define CCM_CSCMR1_BCH_CLK_SEL_MASK (0x40000U) +#define CCM_CSCMR1_BCH_CLK_SEL_SHIFT (18U) +#define CCM_CSCMR1_BCH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_BCH_CLK_SEL_SHIFT)) & CCM_CSCMR1_BCH_CLK_SEL_MASK) +#define CCM_CSCMR1_GPMI_CLK_SEL_MASK (0x80000U) +#define CCM_CSCMR1_GPMI_CLK_SEL_SHIFT (19U) +#define CCM_CSCMR1_GPMI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_GPMI_CLK_SEL_SHIFT)) & CCM_CSCMR1_GPMI_CLK_SEL_MASK) +#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF_MASK (0x3800000U) +#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF_SHIFT (23U) +#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_ACLK_EIM_SLOW_PODF_SHIFT)) & CCM_CSCMR1_ACLK_EIM_SLOW_PODF_MASK) +#define CCM_CSCMR1_QSPI1_PODF_MASK (0x1C000000U) +#define CCM_CSCMR1_QSPI1_PODF_SHIFT (26U) +#define CCM_CSCMR1_QSPI1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_QSPI1_PODF_SHIFT)) & CCM_CSCMR1_QSPI1_PODF_MASK) +#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL_MASK (0x60000000U) +#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL_SHIFT (29U) +#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_ACLK_EIM_SLOW_SEL_SHIFT)) & CCM_CSCMR1_ACLK_EIM_SLOW_SEL_MASK) + +/*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */ +#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU) +#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U) +#define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK) +#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U) +#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U) +#define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK) +#define CCM_CSCMR2_LDB_DI0_DIV_MASK (0x400U) +#define CCM_CSCMR2_LDB_DI0_DIV_SHIFT (10U) +#define CCM_CSCMR2_LDB_DI0_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_LDB_DI0_DIV_SHIFT)) & CCM_CSCMR2_LDB_DI0_DIV_MASK) +#define CCM_CSCMR2_LDB_DI1_DIV_MASK (0x800U) +#define CCM_CSCMR2_LDB_DI1_DIV_SHIFT (11U) +#define CCM_CSCMR2_LDB_DI1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_LDB_DI1_DIV_SHIFT)) & CCM_CSCMR2_LDB_DI1_DIV_MASK) +#define CCM_CSCMR2_ESAI_CLK_SEL_MASK (0x180000U) +#define CCM_CSCMR2_ESAI_CLK_SEL_SHIFT (19U) +#define CCM_CSCMR2_ESAI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_ESAI_CLK_SEL_SHIFT)) & CCM_CSCMR2_ESAI_CLK_SEL_MASK) +#define CCM_CSCMR2_VID_CLK_SEL_MASK (0xE00000U) +#define CCM_CSCMR2_VID_CLK_SEL_SHIFT (21U) +#define CCM_CSCMR2_VID_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_VID_CLK_SEL_SHIFT)) & CCM_CSCMR2_VID_CLK_SEL_MASK) +#define CCM_CSCMR2_VID_CLK_PRE_PODF_MASK (0x3000000U) +#define CCM_CSCMR2_VID_CLK_PRE_PODF_SHIFT (24U) +#define CCM_CSCMR2_VID_CLK_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_VID_CLK_PRE_PODF_SHIFT)) & CCM_CSCMR2_VID_CLK_PRE_PODF_MASK) +#define CCM_CSCMR2_VID_CLK_PODF_MASK (0x1C000000U) +#define CCM_CSCMR2_VID_CLK_PODF_SHIFT (26U) +#define CCM_CSCMR2_VID_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_VID_CLK_PODF_SHIFT)) & CCM_CSCMR2_VID_CLK_PODF_MASK) + +/*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */ +#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU) +#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U) +#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK) +#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U) +#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U) +#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK) +#define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U) +#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U) +#define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK) +#define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U) +#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U) +#define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK) +#define CCM_CSCDR1_BCH_PODF_MASK (0x380000U) +#define CCM_CSCDR1_BCH_PODF_SHIFT (19U) +#define CCM_CSCDR1_BCH_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_BCH_PODF_SHIFT)) & CCM_CSCDR1_BCH_PODF_MASK) +#define CCM_CSCDR1_GPMI_PODF_MASK (0x1C00000U) +#define CCM_CSCDR1_GPMI_PODF_SHIFT (22U) +#define CCM_CSCDR1_GPMI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_GPMI_PODF_SHIFT)) & CCM_CSCDR1_GPMI_PODF_MASK) + +/*! @name CS1CDR - CCM SAI1 Clock Divider Register */ +#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU) +#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U) +#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK) +#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U) +#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U) +#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK) +#define CCM_CS1CDR_ESAI_CLK_PRED_MASK (0xE00U) +#define CCM_CS1CDR_ESAI_CLK_PRED_SHIFT (9U) +#define CCM_CS1CDR_ESAI_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_ESAI_CLK_PRED_SHIFT)) & CCM_CS1CDR_ESAI_CLK_PRED_MASK) +#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U) +#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U) +#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK) +#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U) +#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U) +#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK) +#define CCM_CS1CDR_ESAI_CLK_PODF_MASK (0xE000000U) +#define CCM_CS1CDR_ESAI_CLK_PODF_SHIFT (25U) +#define CCM_CS1CDR_ESAI_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_ESAI_CLK_PODF_SHIFT)) & CCM_CS1CDR_ESAI_CLK_PODF_MASK) + +/*! @name CS2CDR - CCM SAI2 Clock Divider Register */ +#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU) +#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U) +#define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK) +#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U) +#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U) +#define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK) +#define CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0xE00U) +#define CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT (9U) +#define CCM_CS2CDR_LDB_DI0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT)) & CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK) +#define CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x38000U) +#define CCM_CS2CDR_ENFC_CLK_SEL_SHIFT (15U) +#define CCM_CS2CDR_ENFC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_ENFC_CLK_SEL_SHIFT)) & CCM_CS2CDR_ENFC_CLK_SEL_MASK) +#define CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x1C0000U) +#define CCM_CS2CDR_ENFC_CLK_PRED_SHIFT (18U) +#define CCM_CS2CDR_ENFC_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_ENFC_CLK_PRED_SHIFT)) & CCM_CS2CDR_ENFC_CLK_PRED_MASK) +#define CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x7E00000U) +#define CCM_CS2CDR_ENFC_CLK_PODF_SHIFT (21U) +#define CCM_CS2CDR_ENFC_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_ENFC_CLK_PODF_SHIFT)) & CCM_CS2CDR_ENFC_CLK_PODF_MASK) + +/*! @name CDCDR - CCM D1 Clock Divider Register */ +#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U) +#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U) +#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK) +#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U) +#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U) +#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK) +#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U) +#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U) +#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK) + +/*! @name CHSCCDR - CCM HSC Clock Divider Register */ +#define CCM_CHSCCDR_EPDC_CLK_SEL_MASK (0xE00U) +#define CCM_CHSCCDR_EPDC_CLK_SEL_SHIFT (9U) +#define CCM_CHSCCDR_EPDC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CHSCCDR_EPDC_CLK_SEL_SHIFT)) & CCM_CHSCCDR_EPDC_CLK_SEL_MASK) +#define CCM_CHSCCDR_EPDC_PODF_MASK (0x7000U) +#define CCM_CHSCCDR_EPDC_PODF_SHIFT (12U) +#define CCM_CHSCCDR_EPDC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CHSCCDR_EPDC_PODF_SHIFT)) & CCM_CHSCCDR_EPDC_PODF_MASK) +#define CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x38000U) +#define CCM_CHSCCDR_EPDC_PRE_CLK_SEL_SHIFT (15U) +#define CCM_CHSCCDR_EPDC_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CHSCCDR_EPDC_PRE_CLK_SEL_SHIFT)) & CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK) + +/*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */ +#define CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0xE00U) +#define CCM_CSCDR2_LCDIF1_CLK_SEL_SHIFT (9U) +#define CCM_CSCDR2_LCDIF1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF1_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) +#define CCM_CSCDR2_LCDIF1_PRED_MASK (0x7000U) +#define CCM_CSCDR2_LCDIF1_PRED_SHIFT (12U) +#define CCM_CSCDR2_LCDIF1_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF1_PRED_SHIFT)) & CCM_CSCDR2_LCDIF1_PRED_MASK) +#define CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_MASK (0x38000U) +#define CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_SHIFT (15U) +#define CCM_CSCDR2_LCDIF1_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_MASK) +#define CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x40000U) +#define CCM_CSCDR2_ECSPI_CLK_SEL_SHIFT (18U) +#define CCM_CSCDR2_ECSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_ECSPI_CLK_SEL_SHIFT)) & CCM_CSCDR2_ECSPI_CLK_SEL_MASK) +#define CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x1F80000U) +#define CCM_CSCDR2_ECSPI_CLK_PODF_SHIFT (19U) +#define CCM_CSCDR2_ECSPI_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_ECSPI_CLK_PODF_SHIFT)) & CCM_CSCDR2_ECSPI_CLK_PODF_MASK) + +/*! @name CSCDR3 - CCM Serial Clock Divider Register 3 */ +#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U) +#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U) +#define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK) +#define CCM_CSCDR3_CSI_PODF_MASK (0x3800U) +#define CCM_CSCDR3_CSI_PODF_SHIFT (11U) +#define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK) + +/*! @name CDHIPR - CCM Divider Handshake In-Process Register */ +#define CCM_CDHIPR_AXI_PODF_BUSY_MASK (0x1U) +#define CCM_CDHIPR_AXI_PODF_BUSY_SHIFT (0U) +#define CCM_CDHIPR_AXI_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AXI_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AXI_PODF_BUSY_MASK) +#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U) +#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U) +#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK) +#define CCM_CDHIPR_MMDC_PODF_BUSY_MASK (0x4U) +#define CCM_CDHIPR_MMDC_PODF_BUSY_SHIFT (2U) +#define CCM_CDHIPR_MMDC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_MMDC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_MMDC_PODF_BUSY_MASK) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK) +#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U) +#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U) +#define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK) + +/*! @name CLPCR - CCM Low Power Control Register */ +#define CCM_CLPCR_LPM_MASK (0x3U) +#define CCM_CLPCR_LPM_SHIFT (0U) +#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK) +#define CCM_CLPCR_SBYOS_MASK (0x40U) +#define CCM_CLPCR_SBYOS_SHIFT (6U) +#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK) +#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U) +#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U) +#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK) +#define CCM_CLPCR_VSTBY_MASK (0x100U) +#define CCM_CLPCR_VSTBY_SHIFT (8U) +#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK) +#define CCM_CLPCR_STBY_COUNT_MASK (0x600U) +#define CCM_CLPCR_STBY_COUNT_SHIFT (9U) +#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK) +#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U) +#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U) +#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK) +#define CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS_MASK (0x80000U) +#define CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS_SHIFT (19U) +#define CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS_SHIFT)) & CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS_MASK) +#define CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS_MASK (0x200000U) +#define CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS_SHIFT (21U) +#define CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS_SHIFT)) & CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS_MASK) +#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U) +#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U) +#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK) +#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U) +#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U) +#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK) +#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U) +#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U) +#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK) + +/*! @name CISR - CCM Interrupt Status Register */ +#define CCM_CISR_LRF_PLL_MASK (0x1U) +#define CCM_CISR_LRF_PLL_SHIFT (0U) +#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK) +#define CCM_CISR_COSC_READY_MASK (0x40U) +#define CCM_CISR_COSC_READY_SHIFT (6U) +#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK) +#define CCM_CISR_AXI_PODF_LOADED_MASK (0x20000U) +#define CCM_CISR_AXI_PODF_LOADED_SHIFT (17U) +#define CCM_CISR_AXI_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AXI_PODF_LOADED_SHIFT)) & CCM_CISR_AXI_PODF_LOADED_MASK) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK) +#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U) +#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U) +#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK) +#define CCM_CISR_MMDC_PODF_LOADED_MASK (0x200000U) +#define CCM_CISR_MMDC_PODF_LOADED_SHIFT (21U) +#define CCM_CISR_MMDC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_MMDC_PODF_LOADED_SHIFT)) & CCM_CISR_MMDC_PODF_LOADED_MASK) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK) +#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U) +#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U) +#define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK) + +/*! @name CIMR - CCM Interrupt Mask Register */ +#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U) +#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U) +#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK) +#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U) +#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U) +#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK) +#define CCM_CIMR_MASK_AXI_PODF_LOADED_MASK (0x20000U) +#define CCM_CIMR_MASK_AXI_PODF_LOADED_SHIFT (17U) +#define CCM_CIMR_MASK_AXI_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AXI_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AXI_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK) +#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U) +#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U) +#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_MMDC_PODF_LOADED_MASK (0x200000U) +#define CCM_CIMR_MASK_MMDC_PODF_LOADED_SHIFT (21U) +#define CCM_CIMR_MASK_MMDC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_MMDC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_MMDC_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK) +#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U) +#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U) +#define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK) + +/*! @name CCOSR - CCM Clock Output Source Register */ +#define CCM_CCOSR_CLKO_SEL_MASK (0xFU) +#define CCM_CCOSR_CLKO_SEL_SHIFT (0U) +#define CCM_CCOSR_CLKO_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO_SEL_SHIFT)) & CCM_CCOSR_CLKO_SEL_MASK) +#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U) +#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U) +#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK) +#define CCM_CCOSR_CLKO1_EN_MASK (0x80U) +#define CCM_CCOSR_CLKO1_EN_SHIFT (7U) +#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK) +#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U) +#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U) +#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK) +#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U) +#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U) +#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK) +#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U) +#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U) +#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK) +#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U) +#define CCM_CCOSR_CLKO2_EN_SHIFT (24U) +#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK) + +/*! @name CGPR - CCM General Purpose Register */ +#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U) +#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U) +#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK) +#define CCM_CGPR_MMDC_EXT_CLK_DIS_MASK (0x4U) +#define CCM_CGPR_MMDC_EXT_CLK_DIS_SHIFT (2U) +#define CCM_CGPR_MMDC_EXT_CLK_DIS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_MMDC_EXT_CLK_DIS_SHIFT)) & CCM_CGPR_MMDC_EXT_CLK_DIS_MASK) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK) +#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U) +#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U) +#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK) +#define CCM_CGPR_FPL_MASK (0x10000U) +#define CCM_CGPR_FPL_SHIFT (16U) +#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK) +#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U) +#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U) +#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK) + +/*! @name CCGR0 - CCM Clock Gating Register 0 */ +#define CCM_CCGR0_CG0_MASK (0x3U) +#define CCM_CCGR0_CG0_SHIFT (0U) +#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK) +#define CCM_CCGR0_CG1_MASK (0xCU) +#define CCM_CCGR0_CG1_SHIFT (2U) +#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK) +#define CCM_CCGR0_CG2_MASK (0x30U) +#define CCM_CCGR0_CG2_SHIFT (4U) +#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK) +#define CCM_CCGR0_CG3_MASK (0xC0U) +#define CCM_CCGR0_CG3_SHIFT (6U) +#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK) +#define CCM_CCGR0_CG4_MASK (0x300U) +#define CCM_CCGR0_CG4_SHIFT (8U) +#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK) +#define CCM_CCGR0_CG5_MASK (0xC00U) +#define CCM_CCGR0_CG5_SHIFT (10U) +#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK) +#define CCM_CCGR0_CG6_MASK (0x3000U) +#define CCM_CCGR0_CG6_SHIFT (12U) +#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK) +#define CCM_CCGR0_CG7_MASK (0xC000U) +#define CCM_CCGR0_CG7_SHIFT (14U) +#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK) +#define CCM_CCGR0_CG8_MASK (0x30000U) +#define CCM_CCGR0_CG8_SHIFT (16U) +#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK) +#define CCM_CCGR0_CG9_MASK (0xC0000U) +#define CCM_CCGR0_CG9_SHIFT (18U) +#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK) +#define CCM_CCGR0_CG10_MASK (0x300000U) +#define CCM_CCGR0_CG10_SHIFT (20U) +#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK) +#define CCM_CCGR0_CG11_MASK (0xC00000U) +#define CCM_CCGR0_CG11_SHIFT (22U) +#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK) +#define CCM_CCGR0_CG12_MASK (0x3000000U) +#define CCM_CCGR0_CG12_SHIFT (24U) +#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK) +#define CCM_CCGR0_CG13_MASK (0xC000000U) +#define CCM_CCGR0_CG13_SHIFT (26U) +#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK) +#define CCM_CCGR0_CG14_MASK (0x30000000U) +#define CCM_CCGR0_CG14_SHIFT (28U) +#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK) +#define CCM_CCGR0_CG15_MASK (0xC0000000U) +#define CCM_CCGR0_CG15_SHIFT (30U) +#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK) + +/*! @name CCGR1 - CCM Clock Gating Register 1 */ +#define CCM_CCGR1_CG0_MASK (0x3U) +#define CCM_CCGR1_CG0_SHIFT (0U) +#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK) +#define CCM_CCGR1_CG1_MASK (0xCU) +#define CCM_CCGR1_CG1_SHIFT (2U) +#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK) +#define CCM_CCGR1_CG2_MASK (0x30U) +#define CCM_CCGR1_CG2_SHIFT (4U) +#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK) +#define CCM_CCGR1_CG3_MASK (0xC0U) +#define CCM_CCGR1_CG3_SHIFT (6U) +#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK) +#define CCM_CCGR1_CG4_MASK (0x300U) +#define CCM_CCGR1_CG4_SHIFT (8U) +#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK) +#define CCM_CCGR1_CG5_MASK (0xC00U) +#define CCM_CCGR1_CG5_SHIFT (10U) +#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK) +#define CCM_CCGR1_CG6_MASK (0x3000U) +#define CCM_CCGR1_CG6_SHIFT (12U) +#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK) +#define CCM_CCGR1_CG7_MASK (0xC000U) +#define CCM_CCGR1_CG7_SHIFT (14U) +#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK) +#define CCM_CCGR1_CG8_MASK (0x30000U) +#define CCM_CCGR1_CG8_SHIFT (16U) +#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK) +#define CCM_CCGR1_CG9_MASK (0xC0000U) +#define CCM_CCGR1_CG9_SHIFT (18U) +#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK) +#define CCM_CCGR1_CG10_MASK (0x300000U) +#define CCM_CCGR1_CG10_SHIFT (20U) +#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK) +#define CCM_CCGR1_CG11_MASK (0xC00000U) +#define CCM_CCGR1_CG11_SHIFT (22U) +#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK) +#define CCM_CCGR1_CG12_MASK (0x3000000U) +#define CCM_CCGR1_CG12_SHIFT (24U) +#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK) +#define CCM_CCGR1_CG13_MASK (0xC000000U) +#define CCM_CCGR1_CG13_SHIFT (26U) +#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK) +#define CCM_CCGR1_CG14_MASK (0x30000000U) +#define CCM_CCGR1_CG14_SHIFT (28U) +#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK) +#define CCM_CCGR1_CG15_MASK (0xC0000000U) +#define CCM_CCGR1_CG15_SHIFT (30U) +#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK) + +/*! @name CCGR2 - CCM Clock Gating Register 2 */ +#define CCM_CCGR2_CG0_MASK (0x3U) +#define CCM_CCGR2_CG0_SHIFT (0U) +#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK) +#define CCM_CCGR2_CG1_MASK (0xCU) +#define CCM_CCGR2_CG1_SHIFT (2U) +#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK) +#define CCM_CCGR2_CG2_MASK (0x30U) +#define CCM_CCGR2_CG2_SHIFT (4U) +#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK) +#define CCM_CCGR2_CG3_MASK (0xC0U) +#define CCM_CCGR2_CG3_SHIFT (6U) +#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK) +#define CCM_CCGR2_CG4_MASK (0x300U) +#define CCM_CCGR2_CG4_SHIFT (8U) +#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK) +#define CCM_CCGR2_CG5_MASK (0xC00U) +#define CCM_CCGR2_CG5_SHIFT (10U) +#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK) +#define CCM_CCGR2_CG6_MASK (0x3000U) +#define CCM_CCGR2_CG6_SHIFT (12U) +#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK) +#define CCM_CCGR2_CG7_MASK (0xC000U) +#define CCM_CCGR2_CG7_SHIFT (14U) +#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK) +#define CCM_CCGR2_CG8_MASK (0x30000U) +#define CCM_CCGR2_CG8_SHIFT (16U) +#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK) +#define CCM_CCGR2_CG9_MASK (0xC0000U) +#define CCM_CCGR2_CG9_SHIFT (18U) +#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK) +#define CCM_CCGR2_CG10_MASK (0x300000U) +#define CCM_CCGR2_CG10_SHIFT (20U) +#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK) +#define CCM_CCGR2_CG11_MASK (0xC00000U) +#define CCM_CCGR2_CG11_SHIFT (22U) +#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK) +#define CCM_CCGR2_CG12_MASK (0x3000000U) +#define CCM_CCGR2_CG12_SHIFT (24U) +#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK) +#define CCM_CCGR2_CG13_MASK (0xC000000U) +#define CCM_CCGR2_CG13_SHIFT (26U) +#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK) +#define CCM_CCGR2_CG14_MASK (0x30000000U) +#define CCM_CCGR2_CG14_SHIFT (28U) +#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK) +#define CCM_CCGR2_CG15_MASK (0xC0000000U) +#define CCM_CCGR2_CG15_SHIFT (30U) +#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK) + +/*! @name CCGR3 - CCM Clock Gating Register 3 */ +#define CCM_CCGR3_CG0_MASK (0x3U) +#define CCM_CCGR3_CG0_SHIFT (0U) +#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK) +#define CCM_CCGR3_CG1_MASK (0xCU) +#define CCM_CCGR3_CG1_SHIFT (2U) +#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK) +#define CCM_CCGR3_CG2_MASK (0x30U) +#define CCM_CCGR3_CG2_SHIFT (4U) +#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK) +#define CCM_CCGR3_CG3_MASK (0xC0U) +#define CCM_CCGR3_CG3_SHIFT (6U) +#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK) +#define CCM_CCGR3_CG4_MASK (0x300U) +#define CCM_CCGR3_CG4_SHIFT (8U) +#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK) +#define CCM_CCGR3_CG5_MASK (0xC00U) +#define CCM_CCGR3_CG5_SHIFT (10U) +#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK) +#define CCM_CCGR3_CG6_MASK (0x3000U) +#define CCM_CCGR3_CG6_SHIFT (12U) +#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK) +#define CCM_CCGR3_CG7_MASK (0xC000U) +#define CCM_CCGR3_CG7_SHIFT (14U) +#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK) +#define CCM_CCGR3_CG8_MASK (0x30000U) +#define CCM_CCGR3_CG8_SHIFT (16U) +#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK) +#define CCM_CCGR3_CG9_MASK (0xC0000U) +#define CCM_CCGR3_CG9_SHIFT (18U) +#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK) +#define CCM_CCGR3_CG10_MASK (0x300000U) +#define CCM_CCGR3_CG10_SHIFT (20U) +#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK) +#define CCM_CCGR3_CG11_MASK (0xC00000U) +#define CCM_CCGR3_CG11_SHIFT (22U) +#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK) +#define CCM_CCGR3_CG12_MASK (0x3000000U) +#define CCM_CCGR3_CG12_SHIFT (24U) +#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK) +#define CCM_CCGR3_CG13_MASK (0xC000000U) +#define CCM_CCGR3_CG13_SHIFT (26U) +#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK) +#define CCM_CCGR3_CG14_MASK (0x30000000U) +#define CCM_CCGR3_CG14_SHIFT (28U) +#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK) +#define CCM_CCGR3_CG15_MASK (0xC0000000U) +#define CCM_CCGR3_CG15_SHIFT (30U) +#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK) + +/*! @name CCGR4 - CCM Clock Gating Register 4 */ +#define CCM_CCGR4_CG0_MASK (0x3U) +#define CCM_CCGR4_CG0_SHIFT (0U) +#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK) +#define CCM_CCGR4_CG1_MASK (0xCU) +#define CCM_CCGR4_CG1_SHIFT (2U) +#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK) +#define CCM_CCGR4_CG2_MASK (0x30U) +#define CCM_CCGR4_CG2_SHIFT (4U) +#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK) +#define CCM_CCGR4_CG3_MASK (0xC0U) +#define CCM_CCGR4_CG3_SHIFT (6U) +#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK) +#define CCM_CCGR4_CG4_MASK (0x300U) +#define CCM_CCGR4_CG4_SHIFT (8U) +#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK) +#define CCM_CCGR4_CG5_MASK (0xC00U) +#define CCM_CCGR4_CG5_SHIFT (10U) +#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK) +#define CCM_CCGR4_CG6_MASK (0x3000U) +#define CCM_CCGR4_CG6_SHIFT (12U) +#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK) +#define CCM_CCGR4_CG7_MASK (0xC000U) +#define CCM_CCGR4_CG7_SHIFT (14U) +#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK) +#define CCM_CCGR4_CG8_MASK (0x30000U) +#define CCM_CCGR4_CG8_SHIFT (16U) +#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK) +#define CCM_CCGR4_CG9_MASK (0xC0000U) +#define CCM_CCGR4_CG9_SHIFT (18U) +#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK) +#define CCM_CCGR4_CG10_MASK (0x300000U) +#define CCM_CCGR4_CG10_SHIFT (20U) +#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK) +#define CCM_CCGR4_CG11_MASK (0xC00000U) +#define CCM_CCGR4_CG11_SHIFT (22U) +#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK) +#define CCM_CCGR4_CG12_MASK (0x3000000U) +#define CCM_CCGR4_CG12_SHIFT (24U) +#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK) +#define CCM_CCGR4_CG13_MASK (0xC000000U) +#define CCM_CCGR4_CG13_SHIFT (26U) +#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK) +#define CCM_CCGR4_CG14_MASK (0x30000000U) +#define CCM_CCGR4_CG14_SHIFT (28U) +#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK) +#define CCM_CCGR4_CG15_MASK (0xC0000000U) +#define CCM_CCGR4_CG15_SHIFT (30U) +#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK) + +/*! @name CCGR5 - CCM Clock Gating Register 5 */ +#define CCM_CCGR5_CG0_MASK (0x3U) +#define CCM_CCGR5_CG0_SHIFT (0U) +#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK) +#define CCM_CCGR5_CG1_MASK (0xCU) +#define CCM_CCGR5_CG1_SHIFT (2U) +#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK) +#define CCM_CCGR5_CG2_MASK (0x30U) +#define CCM_CCGR5_CG2_SHIFT (4U) +#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK) +#define CCM_CCGR5_CG3_MASK (0xC0U) +#define CCM_CCGR5_CG3_SHIFT (6U) +#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK) +#define CCM_CCGR5_CG4_MASK (0x300U) +#define CCM_CCGR5_CG4_SHIFT (8U) +#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK) +#define CCM_CCGR5_CG5_MASK (0xC00U) +#define CCM_CCGR5_CG5_SHIFT (10U) +#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK) +#define CCM_CCGR5_CG6_MASK (0x3000U) +#define CCM_CCGR5_CG6_SHIFT (12U) +#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK) +#define CCM_CCGR5_CG7_MASK (0xC000U) +#define CCM_CCGR5_CG7_SHIFT (14U) +#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK) +#define CCM_CCGR5_CG8_MASK (0x30000U) +#define CCM_CCGR5_CG8_SHIFT (16U) +#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK) +#define CCM_CCGR5_CG9_MASK (0xC0000U) +#define CCM_CCGR5_CG9_SHIFT (18U) +#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK) +#define CCM_CCGR5_CG10_MASK (0x300000U) +#define CCM_CCGR5_CG10_SHIFT (20U) +#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK) +#define CCM_CCGR5_CG11_MASK (0xC00000U) +#define CCM_CCGR5_CG11_SHIFT (22U) +#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK) +#define CCM_CCGR5_CG12_MASK (0x3000000U) +#define CCM_CCGR5_CG12_SHIFT (24U) +#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK) +#define CCM_CCGR5_CG13_MASK (0xC000000U) +#define CCM_CCGR5_CG13_SHIFT (26U) +#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK) +#define CCM_CCGR5_CG14_MASK (0x30000000U) +#define CCM_CCGR5_CG14_SHIFT (28U) +#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK) +#define CCM_CCGR5_CG15_MASK (0xC0000000U) +#define CCM_CCGR5_CG15_SHIFT (30U) +#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK) + +/*! @name CCGR6 - CCM Clock Gating Register 6 */ +#define CCM_CCGR6_CG0_MASK (0x3U) +#define CCM_CCGR6_CG0_SHIFT (0U) +#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK) +#define CCM_CCGR6_CG1_MASK (0xCU) +#define CCM_CCGR6_CG1_SHIFT (2U) +#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK) +#define CCM_CCGR6_CG2_MASK (0x30U) +#define CCM_CCGR6_CG2_SHIFT (4U) +#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK) +#define CCM_CCGR6_CG3_MASK (0xC0U) +#define CCM_CCGR6_CG3_SHIFT (6U) +#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK) +#define CCM_CCGR6_CG4_MASK (0x300U) +#define CCM_CCGR6_CG4_SHIFT (8U) +#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK) +#define CCM_CCGR6_CG5_MASK (0xC00U) +#define CCM_CCGR6_CG5_SHIFT (10U) +#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK) +#define CCM_CCGR6_CG6_MASK (0x3000U) +#define CCM_CCGR6_CG6_SHIFT (12U) +#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK) +#define CCM_CCGR6_CG7_MASK (0xC000U) +#define CCM_CCGR6_CG7_SHIFT (14U) +#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK) +#define CCM_CCGR6_CG8_MASK (0x30000U) +#define CCM_CCGR6_CG8_SHIFT (16U) +#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK) +#define CCM_CCGR6_CG9_MASK (0xC0000U) +#define CCM_CCGR6_CG9_SHIFT (18U) +#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK) +#define CCM_CCGR6_CG10_MASK (0x300000U) +#define CCM_CCGR6_CG10_SHIFT (20U) +#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK) +#define CCM_CCGR6_CG11_MASK (0xC00000U) +#define CCM_CCGR6_CG11_SHIFT (22U) +#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK) +#define CCM_CCGR6_CG12_MASK (0x3000000U) +#define CCM_CCGR6_CG12_SHIFT (24U) +#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK) +#define CCM_CCGR6_CG13_MASK (0xC000000U) +#define CCM_CCGR6_CG13_SHIFT (26U) +#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK) +#define CCM_CCGR6_CG14_MASK (0x30000000U) +#define CCM_CCGR6_CG14_SHIFT (28U) +#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK) +#define CCM_CCGR6_CG15_MASK (0xC0000000U) +#define CCM_CCGR6_CG15_SHIFT (30U) +#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK) + +/*! @name CMEOR - CCM Module Enable Overide Register */ +#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U) +#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U) +#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK) +#define CCM_CMEOR_MOD_EN_OV_EPIT_MASK (0x40U) +#define CCM_CMEOR_MOD_EN_OV_EPIT_SHIFT (6U) +#define CCM_CMEOR_MOD_EN_OV_EPIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_EPIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_EPIT_MASK) +#define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U) +#define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U) +#define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK) + + +/*! + * @} + */ /* end of group CCM_Register_Masks */ + + +/* CCM - Peripheral instance base addresses */ +/** Peripheral CCM base address */ +#define CCM_BASE (0x20C4000u) +/** Peripheral CCM base pointer */ +#define CCM ((CCM_Type *)CCM_BASE) +/** Array initializer of CCM peripheral base addresses */ +#define CCM_BASE_ADDRS { CCM_BASE } +/** Array initializer of CCM peripheral base pointers */ +#define CCM_BASE_PTRS { CCM } +/** Interrupt vectors for the CCM peripheral type */ +#define CCM_IRQS { CCM_IRQ1_IRQn, CCM_IRQ2_IRQn } + +/*! + * @} + */ /* end of group CCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer + * @{ + */ + +/** CCM_ANALOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t PLL_ARM; /**< Analog ARM PLL control Register, offset: 0x0 */ + __IO uint32_t PLL_ARM_SET; /**< Analog ARM PLL control Register, offset: 0x4 */ + __IO uint32_t PLL_ARM_CLR; /**< Analog ARM PLL control Register, offset: 0x8 */ + __IO uint32_t PLL_ARM_TOG; /**< Analog ARM PLL control Register, offset: 0xC */ + __IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */ + __IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */ + __IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */ + __IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */ + __IO uint32_t PLL_USB2; /**< Analog USB2 480MHz PLL Control Register, offset: 0x20 */ + __IO uint32_t PLL_USB2_SET; /**< Analog USB2 480MHz PLL Control Register, offset: 0x24 */ + __IO uint32_t PLL_USB2_CLR; /**< Analog USB2 480MHz PLL Control Register, offset: 0x28 */ + __IO uint32_t PLL_USB2_TOG; /**< Analog USB2 480MHz PLL Control Register, offset: 0x2C */ + __IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */ + __IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */ + __IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */ + __IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */ + __IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PLL_SYS_NUM; /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PLL_SYS_DENOM; /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */ + uint8_t RESERVED_2[12]; + __IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */ + __IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */ + __IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */ + __IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */ + __IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */ + uint8_t RESERVED_3[12]; + __IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */ + uint8_t RESERVED_4[12]; + __IO uint32_t PLL_VIDEO; /**< Analog Video PLL control Register, offset: 0xA0 */ + __IO uint32_t PLL_VIDEO_SET; /**< Analog Video PLL control Register, offset: 0xA4 */ + __IO uint32_t PLL_VIDEO_CLR; /**< Analog Video PLL control Register, offset: 0xA8 */ + __IO uint32_t PLL_VIDEO_TOG; /**< Analog Video PLL control Register, offset: 0xAC */ + __IO uint32_t PLL_VIDEO_NUM; /**< Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0 */ + uint8_t RESERVED_5[12]; + __IO uint32_t PLL_VIDEO_DENOM; /**< Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0 */ + uint8_t RESERVED_6[28]; + __IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */ + __IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */ + __IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */ + __IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */ + __IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */ + __IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */ + __IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */ + __IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */ + __IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */ + __IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */ + __IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */ + __IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */ + uint8_t RESERVED_7[64]; + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ + __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ + __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ + __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ + __IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */ + __IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */ + __IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */ + __IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */ +} CCM_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks + * @{ + */ + +/*! @name PLL_ARM - Analog ARM PLL control Register */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK) + +/*! @name PLL_ARM_SET - Analog ARM PLL control Register */ +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK) + +/*! @name PLL_ARM_CLR - Analog ARM PLL control Register */ +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK) + +/*! @name PLL_ARM_TOG - Analog ARM PLL control Register */ +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK) + +/*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK) + +/*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK) + +/*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK) + +/*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK) + +/*! @name PLL_USB2 - Analog USB2 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK) + +/*! @name PLL_USB2_SET - Analog USB2 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK) + +/*! @name PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK) + +/*! @name PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK) + +/*! @name PLL_SYS - Analog System PLL Control Register */ +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK) + +/*! @name PLL_SYS_SET - Analog System PLL Control Register */ +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK) + +/*! @name PLL_SYS_CLR - Analog System PLL Control Register */ +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK) + +/*! @name PLL_SYS_TOG - Analog System PLL Control Register */ +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK) + +/*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */ +#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU) +#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U) +#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK) + +/*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK) + +/*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK) + +/*! @name PLL_AUDIO - Analog Audio PLL control Register */ +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) + +/*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */ +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK) + +/*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */ +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK) + +/*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */ +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK) + +/*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) + +/*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) + +/*! @name PLL_VIDEO - Analog Video PLL control Register */ +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) + +/*! @name PLL_VIDEO_SET - Analog Video PLL control Register */ +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK) + +/*! @name PLL_VIDEO_CLR - Analog Video PLL control Register */ +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK) + +/*! @name PLL_VIDEO_TOG - Analog Video PLL control Register */ +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK) + +/*! @name PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) + +/*! @name PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) + +/*! @name PLL_ENET - Analog ENET PLL Control Register */ +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (2U) +#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK (0x80000U) +#define CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT (19U) +#define CCM_ANALOG_PLL_ENET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK) +#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK) + +/*! @name PLL_ENET_SET - Analog ENET PLL Control Register */ +#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT (2U) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK (0x80000U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT (19U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK) + +/*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */ +#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT (2U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK (0x80000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT (19U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK) + +/*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */ +#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT (2U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK (0x80000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT (19U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK) + +/*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK) + +/*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK) + +/*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK) + +/*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK) + +/*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK) + +/*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK) + +/*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK) + +/*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK) + +/*! @name MISC0 - Miscellaneous Register 0 */ +#define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK) +#define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK) +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT (31U) +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK) + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK) +#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) +#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) +#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK) + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK) +#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) +#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) +#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK) + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK) +#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) +#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) +#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK) + +/*! @name MISC1 - Miscellaneous Register 1 */ +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK) + +/*! @name MISC1_SET - Miscellaneous Register 1 */ +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK) + +/*! @name MISC1_CLR - Miscellaneous Register 1 */ +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK) + +/*! @name MISC1_TOG - Miscellaneous Register 1 */ +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK) + +/*! @name MISC2 - Miscellaneous Register 2 */ +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) + +/*! @name MISC2_SET - Miscellaneous Register 2 */ +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_SET_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK) + +/*! @name MISC2_CLR - Miscellaneous Register 2 */ +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK) + +/*! @name MISC2_TOG - Miscellaneous Register 2 */ +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK) + + +/*! + * @} + */ /* end of group CCM_ANALOG_Register_Masks */ + + +/* CCM_ANALOG - Peripheral instance base addresses */ +/** Peripheral CCM_ANALOG base address */ +#define CCM_ANALOG_BASE (0x20C8000u) +/** Peripheral CCM_ANALOG base pointer */ +#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE) +/** Array initializer of CCM_ANALOG peripheral base addresses */ +#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE } +/** Array initializer of CCM_ANALOG peripheral base pointers */ +#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG } + +/*! + * @} + */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CSI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer + * @{ + */ + +/** CSI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSICR1; /**< CSI Control Register 1, offset: 0x0 */ + __IO uint32_t CSICR2; /**< CSI Control Register 2, offset: 0x4 */ + __IO uint32_t CSICR3; /**< CSI Control Register 3, offset: 0x8 */ + __I uint32_t CSISTATFIFO; /**< CSI Statistic FIFO Register, offset: 0xC */ + __I uint32_t CSIRFIFO; /**< CSI RX FIFO Register, offset: 0x10 */ + __IO uint32_t CSIRXCNT; /**< CSI RX Count Register, offset: 0x14 */ + __IO uint32_t CSISR; /**< CSI Status Register, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CSIDMASA_STATFIFO; /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */ + __IO uint32_t CSIDMATS_STATFIFO; /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */ + __IO uint32_t CSIDMASA_FB1; /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */ + __IO uint32_t CSIDMASA_FB2; /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */ + __IO uint32_t CSIFBUF_PARA; /**< CSI Frame Buffer Parameter Register, offset: 0x30 */ + __IO uint32_t CSIIMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */ + uint8_t RESERVED_1[16]; + __IO uint32_t CSICR18; /**< CSI Control Register 18, offset: 0x48 */ + __IO uint32_t CSICR19; /**< CSI Control Register 19, offset: 0x4C */ +} CSI_Type; + +/* ---------------------------------------------------------------------------- + -- CSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Register_Masks CSI Register Masks + * @{ + */ + +/*! @name CSICR1 - CSI Control Register 1 */ +#define CSI_CSICR1_PIXEL_BIT_MASK (0x1U) +#define CSI_CSICR1_PIXEL_BIT_SHIFT (0U) +#define CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK) +#define CSI_CSICR1_REDGE_MASK (0x2U) +#define CSI_CSICR1_REDGE_SHIFT (1U) +#define CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK) +#define CSI_CSICR1_INV_PCLK_MASK (0x4U) +#define CSI_CSICR1_INV_PCLK_SHIFT (2U) +#define CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK) +#define CSI_CSICR1_INV_DATA_MASK (0x8U) +#define CSI_CSICR1_INV_DATA_SHIFT (3U) +#define CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK) +#define CSI_CSICR1_GCLK_MODE_MASK (0x10U) +#define CSI_CSICR1_GCLK_MODE_SHIFT (4U) +#define CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK) +#define CSI_CSICR1_CLR_RXFIFO_MASK (0x20U) +#define CSI_CSICR1_CLR_RXFIFO_SHIFT (5U) +#define CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK) +#define CSI_CSICR1_CLR_STATFIFO_MASK (0x40U) +#define CSI_CSICR1_CLR_STATFIFO_SHIFT (6U) +#define CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK) +#define CSI_CSICR1_PACK_DIR_MASK (0x80U) +#define CSI_CSICR1_PACK_DIR_SHIFT (7U) +#define CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK) +#define CSI_CSICR1_FCC_MASK (0x100U) +#define CSI_CSICR1_FCC_SHIFT (8U) +#define CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK) +#define CSI_CSICR1_CCIR_EN_MASK (0x400U) +#define CSI_CSICR1_CCIR_EN_SHIFT (10U) +#define CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK) +#define CSI_CSICR1_HSYNC_POL_MASK (0x800U) +#define CSI_CSICR1_HSYNC_POL_SHIFT (11U) +#define CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK) +#define CSI_CSICR1_SOF_INTEN_MASK (0x10000U) +#define CSI_CSICR1_SOF_INTEN_SHIFT (16U) +#define CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK) +#define CSI_CSICR1_SOF_POL_MASK (0x20000U) +#define CSI_CSICR1_SOF_POL_SHIFT (17U) +#define CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK) +#define CSI_CSICR1_RXFF_INTEN_MASK (0x40000U) +#define CSI_CSICR1_RXFF_INTEN_SHIFT (18U) +#define CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_STATFF_INTEN_MASK (0x200000U) +#define CSI_CSICR1_STATFF_INTEN_SHIFT (21U) +#define CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U) +#define CSI_CSICR1_RF_OR_INTEN_SHIFT (24U) +#define CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK) +#define CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U) +#define CSI_CSICR1_SF_OR_INTEN_SHIFT (25U) +#define CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK) +#define CSI_CSICR1_COF_INT_EN_MASK (0x4000000U) +#define CSI_CSICR1_COF_INT_EN_SHIFT (26U) +#define CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK) +#define CSI_CSICR1_VIDEO_MODE_MASK (0x8000000U) +#define CSI_CSICR1_VIDEO_MODE_SHIFT (27U) +#define CSI_CSICR1_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_VIDEO_MODE_SHIFT)) & CSI_CSICR1_VIDEO_MODE_MASK) +#define CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U) +#define CSI_CSICR1_PrP_IF_EN_SHIFT (28U) +#define CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK) +#define CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U) +#define CSI_CSICR1_EOF_INT_EN_SHIFT (29U) +#define CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK) +#define CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U) +#define CSI_CSICR1_EXT_VSYNC_SHIFT (30U) +#define CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK) +#define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U) +#define CSI_CSICR1_SWAP16_EN_SHIFT (31U) +#define CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK) + +/*! @name CSICR2 - CSI Control Register 2 */ +#define CSI_CSICR2_HSC_MASK (0xFFU) +#define CSI_CSICR2_HSC_SHIFT (0U) +#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK) +#define CSI_CSICR2_VSC_MASK (0xFF00U) +#define CSI_CSICR2_VSC_SHIFT (8U) +#define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK) +#define CSI_CSICR2_LVRM_MASK (0x70000U) +#define CSI_CSICR2_LVRM_SHIFT (16U) +#define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK) +#define CSI_CSICR2_BTS_MASK (0x180000U) +#define CSI_CSICR2_BTS_SHIFT (19U) +#define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK) +#define CSI_CSICR2_SCE_MASK (0x800000U) +#define CSI_CSICR2_SCE_SHIFT (23U) +#define CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK) +#define CSI_CSICR2_AFS_MASK (0x3000000U) +#define CSI_CSICR2_AFS_SHIFT (24U) +#define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK) +#define CSI_CSICR2_DRM_MASK (0x4000000U) +#define CSI_CSICR2_DRM_SHIFT (26U) +#define CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK) + +/*! @name CSICR3 - CSI Control Register 3 */ +#define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U) +#define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U) +#define CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK) +#define CSI_CSICR3_ECC_INT_EN_MASK (0x2U) +#define CSI_CSICR3_ECC_INT_EN_SHIFT (1U) +#define CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK) +#define CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U) +#define CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U) +#define CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK) +#define CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U) +#define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U) +#define CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK) +#define CSI_CSICR3_RxFF_LEVEL_MASK (0x70U) +#define CSI_CSICR3_RxFF_LEVEL_SHIFT (4U) +#define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK) +#define CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U) +#define CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U) +#define CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK) +#define CSI_CSICR3_STATFF_LEVEL_MASK (0x700U) +#define CSI_CSICR3_STATFF_LEVEL_SHIFT (8U) +#define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK) +#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U) +#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U) +#define CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK) +#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U) +#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U) +#define CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK) +#define CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U) +#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U) +#define CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK) +#define CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U) +#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U) +#define CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK) +#define CSI_CSICR3_FRMCNT_RST_MASK (0x8000U) +#define CSI_CSICR3_FRMCNT_RST_SHIFT (15U) +#define CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK) +#define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U) +#define CSI_CSICR3_FRMCNT_SHIFT (16U) +#define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK) + +/*! @name CSISTATFIFO - CSI Statistic FIFO Register */ +#define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU) +#define CSI_CSISTATFIFO_STAT_SHIFT (0U) +#define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK) + +/*! @name CSIRFIFO - CSI RX FIFO Register */ +#define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU) +#define CSI_CSIRFIFO_IMAGE_SHIFT (0U) +#define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK) + +/*! @name CSIRXCNT - CSI RX Count Register */ +#define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU) +#define CSI_CSIRXCNT_RXCNT_SHIFT (0U) +#define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK) + +/*! @name CSISR - CSI Status Register */ +#define CSI_CSISR_DRDY_MASK (0x1U) +#define CSI_CSISR_DRDY_SHIFT (0U) +#define CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK) +#define CSI_CSISR_ECC_INT_MASK (0x2U) +#define CSI_CSISR_ECC_INT_SHIFT (1U) +#define CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK) +#define CSI_CSISR_HRESP_ERR_INT_MASK (0x80U) +#define CSI_CSISR_HRESP_ERR_INT_SHIFT (7U) +#define CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK) +#define CSI_CSISR_COF_INT_MASK (0x2000U) +#define CSI_CSISR_COF_INT_SHIFT (13U) +#define CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK) +#define CSI_CSISR_F1_INT_MASK (0x4000U) +#define CSI_CSISR_F1_INT_SHIFT (14U) +#define CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK) +#define CSI_CSISR_F2_INT_MASK (0x8000U) +#define CSI_CSISR_F2_INT_SHIFT (15U) +#define CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK) +#define CSI_CSISR_SOF_INT_MASK (0x10000U) +#define CSI_CSISR_SOF_INT_SHIFT (16U) +#define CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK) +#define CSI_CSISR_EOF_INT_MASK (0x20000U) +#define CSI_CSISR_EOF_INT_SHIFT (17U) +#define CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK) +#define CSI_CSISR_RxFF_INT_MASK (0x40000U) +#define CSI_CSISR_RxFF_INT_SHIFT (18U) +#define CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK) +#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U) +#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U) +#define CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK) +#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U) +#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U) +#define CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK) +#define CSI_CSISR_STATFF_INT_MASK (0x200000U) +#define CSI_CSISR_STATFF_INT_SHIFT (21U) +#define CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK) +#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U) +#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U) +#define CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK) +#define CSI_CSISR_RF_OR_INT_MASK (0x1000000U) +#define CSI_CSISR_RF_OR_INT_SHIFT (24U) +#define CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK) +#define CSI_CSISR_SF_OR_INT_MASK (0x2000000U) +#define CSI_CSISR_SF_OR_INT_SHIFT (25U) +#define CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK) +#define CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U) +#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U) +#define CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK) +#define CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U) +#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U) +#define CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK) + +/*! @name CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */ +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U) +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK) + +/*! @name CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */ +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU) +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U) +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK) + +/*! @name CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */ +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U) +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK) + +/*! @name CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */ +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U) +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK) + +/*! @name CSIFBUF_PARA - CSI Frame Buffer Parameter Register */ +#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU) +#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U) +#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK) + +/*! @name CSIIMAG_PARA - CSI Image Parameter Register */ +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU) +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U) +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK) + +/*! @name CSICR18 - CSI Control Register 18 */ +#define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U) +#define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U) +#define CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK) +#define CSI_CSICR18_PARALLEL24_EN_MASK (0x8U) +#define CSI_CSICR18_PARALLEL24_EN_SHIFT (3U) +#define CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK) +#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U) +#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U) +#define CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK) +#define CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U) +#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U) +#define CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK) +#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U) +#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U) +#define CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK) +#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U) +#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U) +#define CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK) +#define CSI_CSICR18_AHB_HPROT_MASK (0xF000U) +#define CSI_CSICR18_AHB_HPROT_SHIFT (12U) +#define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK) +#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK (0x30000U) +#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT (16U) +#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT)) & CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK) +#define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U) +#define CSI_CSICR18_MASK_OPTION_SHIFT (18U) +#define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK) +#define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U) +#define CSI_CSICR18_CSI_ENABLE_SHIFT (31U) +#define CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK) + +/*! @name CSICR19 - CSI Control Register 19 */ +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU) +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U) +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK) + + +/*! + * @} + */ /* end of group CSI_Register_Masks */ + + +/* CSI - Peripheral instance base addresses */ +/** Peripheral CSI base address */ +#define CSI_BASE (0x21C4000u) +/** Peripheral CSI base pointer */ +#define CSI ((CSI_Type *)CSI_BASE) +/** Array initializer of CSI peripheral base addresses */ +#define CSI_BASE_ADDRS { CSI_BASE } +/** Array initializer of CSI peripheral base pointers */ +#define CSI_BASE_PTRS { CSI } +/** Interrupt vectors for the CSI peripheral type */ +#define CSI_IRQS { CSI_IRQn } + +/*! + * @} + */ /* end of group CSI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DCP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCP_Peripheral_Access_Layer DCP Peripheral Access Layer + * @{ + */ + +/** DCP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DCP control register 0, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t STAT; /**< DCP status register, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CHANNELCTRL; /**< DCP channel control register, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CAPABILITY0; /**< DCP capability 0 register, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __I uint32_t CAPABILITY1; /**< DCP capability 1 register, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t CONTEXT; /**< DCP context buffer pointer, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t KEY; /**< DCP key index, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t KEYDATA; /**< DCP key data, offset: 0x70 */ + uint8_t RESERVED_7[12]; + __I uint32_t PACKET0; /**< DCP work packet 0 status register, offset: 0x80 */ + uint8_t RESERVED_8[12]; + __I uint32_t PACKET1; /**< DCP work packet 1 status register, offset: 0x90 */ + uint8_t RESERVED_9[12]; + __I uint32_t PACKET2; /**< DCP work packet 2 status register, offset: 0xA0 */ + uint8_t RESERVED_10[12]; + __I uint32_t PACKET3; /**< DCP work packet 3 status register, offset: 0xB0 */ + uint8_t RESERVED_11[12]; + __I uint32_t PACKET4; /**< DCP work packet 4 status register, offset: 0xC0 */ + uint8_t RESERVED_12[12]; + __I uint32_t PACKET5; /**< DCP work packet 5 status register, offset: 0xD0 */ + uint8_t RESERVED_13[12]; + __I uint32_t PACKET6; /**< DCP work packet 6 status register, offset: 0xE0 */ + uint8_t RESERVED_14[28]; + __IO uint32_t CH0CMDPTR; /**< DCP channel 0 command pointer address register, offset: 0x100 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CH0SEMA; /**< DCP channel 0 semaphore register, offset: 0x110 */ + uint8_t RESERVED_16[12]; + __IO uint32_t CH0STAT; /**< DCP channel 0 status register, offset: 0x120 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CH0OPTS; /**< DCP channel 0 options register, offset: 0x130 */ + uint8_t RESERVED_18[12]; + __IO uint32_t CH1CMDPTR; /**< DCP channel 1 command pointer address register, offset: 0x140 */ + uint8_t RESERVED_19[12]; + __IO uint32_t CH1SEMA; /**< DCP channel 1 semaphore register, offset: 0x150 */ + uint8_t RESERVED_20[12]; + __IO uint32_t CH1STAT; /**< DCP channel 1 status register, offset: 0x160 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CH1OPTS; /**< DCP channel 1 options register, offset: 0x170 */ + uint8_t RESERVED_22[12]; + __IO uint32_t CH2CMDPTR; /**< DCP channel 2 command pointer address register, offset: 0x180 */ + uint8_t RESERVED_23[12]; + __IO uint32_t CH2SEMA; /**< DCP channel 2 semaphore register, offset: 0x190 */ + uint8_t RESERVED_24[12]; + __IO uint32_t CH2STAT; /**< DCP channel 2 status register, offset: 0x1A0 */ + uint8_t RESERVED_25[12]; + __IO uint32_t CH2OPTS; /**< DCP channel 2 options register, offset: 0x1B0 */ + uint8_t RESERVED_26[12]; + __IO uint32_t CH3CMDPTR; /**< DCP channel 3 command pointer address register, offset: 0x1C0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t CH3SEMA; /**< DCP channel 3 semaphore register, offset: 0x1D0 */ + uint8_t RESERVED_28[12]; + __IO uint32_t CH3STAT; /**< DCP channel 3 status register, offset: 0x1E0 */ + uint8_t RESERVED_29[12]; + __IO uint32_t CH3OPTS; /**< DCP channel 3 options register, offset: 0x1F0 */ + uint8_t RESERVED_30[524]; + __IO uint32_t DBGSELECT; /**< DCP debug select register, offset: 0x400 */ + uint8_t RESERVED_31[12]; + __I uint32_t DBGDATA; /**< DCP debug data register, offset: 0x410 */ + uint8_t RESERVED_32[12]; + __IO uint32_t PAGETABLE; /**< DCP page table register, offset: 0x420 */ + uint8_t RESERVED_33[12]; + __I uint32_t VERSION; /**< DCP version register, offset: 0x430 */ +} DCP_Type; + +/* ---------------------------------------------------------------------------- + -- DCP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCP_Register_Masks DCP Register Masks + * @{ + */ + +/*! @name CTRL - DCP control register 0 */ +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK) +#define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U) +#define DCP_CTRL_PRESENT_SHA_SHIFT (28U) +#define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK) +#define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U) +#define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U) +#define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK) +#define DCP_CTRL_CLKGATE_MASK (0x40000000U) +#define DCP_CTRL_CLKGATE_SHIFT (30U) +#define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK) +#define DCP_CTRL_SFTRST_MASK (0x80000000U) +#define DCP_CTRL_SFTRST_SHIFT (31U) +#define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK) + +/*! @name STAT - DCP status register */ +#define DCP_STAT_IRQ_MASK (0xFU) +#define DCP_STAT_IRQ_SHIFT (0U) +#define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK) +#define DCP_STAT_RSVD_IRQ_MASK (0x100U) +#define DCP_STAT_RSVD_IRQ_SHIFT (8U) +#define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK) +#define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U) +#define DCP_STAT_READY_CHANNELS_SHIFT (16U) +#define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK) +#define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U) +#define DCP_STAT_CUR_CHANNEL_SHIFT (24U) +#define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK) +#define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U) +#define DCP_STAT_OTP_KEY_READY_SHIFT (28U) +#define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK) + +/*! @name CHANNELCTRL - DCP channel control register */ +#define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU) +#define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U) +#define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK) +#define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U) +#define DCP_CHANNELCTRL_RSVD_SHIFT (17U) +#define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK) + +/*! @name CAPABILITY0 - DCP capability 0 register */ +#define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU) +#define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U) +#define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK) +#define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U) +#define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U) +#define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK) +#define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U) +#define DCP_CAPABILITY0_RSVD_SHIFT (12U) +#define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK) +#define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U) +#define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U) +#define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK) + +/*! @name CAPABILITY1 - DCP capability 1 register */ +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU) +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U) +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK) +#define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U) +#define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U) +#define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK) + +/*! @name CONTEXT - DCP context buffer pointer */ +#define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CONTEXT_ADDR_SHIFT (0U) +#define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK) + +/*! @name KEY - DCP key index */ +#define DCP_KEY_SUBWORD_MASK (0x3U) +#define DCP_KEY_SUBWORD_SHIFT (0U) +#define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK) +#define DCP_KEY_RSVD_SUBWORD_MASK (0xCU) +#define DCP_KEY_RSVD_SUBWORD_SHIFT (2U) +#define DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK) +#define DCP_KEY_INDEX_MASK (0x30U) +#define DCP_KEY_INDEX_SHIFT (4U) +#define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK) +#define DCP_KEY_RSVD_INDEX_MASK (0xC0U) +#define DCP_KEY_RSVD_INDEX_SHIFT (6U) +#define DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK) +#define DCP_KEY_RSVD_MASK (0xFFFFFF00U) +#define DCP_KEY_RSVD_SHIFT (8U) +#define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK) + +/*! @name KEYDATA - DCP key data */ +#define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU) +#define DCP_KEYDATA_DATA_SHIFT (0U) +#define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK) + +/*! @name PACKET0 - DCP work packet 0 status register */ +#define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET0_ADDR_SHIFT (0U) +#define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK) + +/*! @name PACKET1 - DCP work packet 1 status register */ +#define DCP_PACKET1_INTERRUPT_MASK (0x1U) +#define DCP_PACKET1_INTERRUPT_SHIFT (0U) +#define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK) +#define DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U) +#define DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U) +#define DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK) +#define DCP_PACKET1_CHAIN_MASK (0x4U) +#define DCP_PACKET1_CHAIN_SHIFT (2U) +#define DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK) +#define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U) +#define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U) +#define DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK) +#define DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U) +#define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U) +#define DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK) +#define DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U) +#define DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U) +#define DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK) +#define DCP_PACKET1_ENABLE_HASH_MASK (0x40U) +#define DCP_PACKET1_ENABLE_HASH_SHIFT (6U) +#define DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK) +#define DCP_PACKET1_ENABLE_BLIT_MASK (0x80U) +#define DCP_PACKET1_ENABLE_BLIT_SHIFT (7U) +#define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK) +#define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U) +#define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U) +#define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK) +#define DCP_PACKET1_CIPHER_INIT_MASK (0x200U) +#define DCP_PACKET1_CIPHER_INIT_SHIFT (9U) +#define DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK) +#define DCP_PACKET1_OTP_KEY_MASK (0x400U) +#define DCP_PACKET1_OTP_KEY_SHIFT (10U) +#define DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK) +#define DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U) +#define DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U) +#define DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK) +#define DCP_PACKET1_HASH_INIT_MASK (0x1000U) +#define DCP_PACKET1_HASH_INIT_SHIFT (12U) +#define DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK) +#define DCP_PACKET1_HASH_TERM_MASK (0x2000U) +#define DCP_PACKET1_HASH_TERM_SHIFT (13U) +#define DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK) +#define DCP_PACKET1_CHECK_HASH_MASK (0x4000U) +#define DCP_PACKET1_CHECK_HASH_SHIFT (14U) +#define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK) +#define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U) +#define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U) +#define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK) +#define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U) +#define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U) +#define DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK) +#define DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U) +#define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U) +#define DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK) +#define DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U) +#define DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U) +#define DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK) +#define DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U) +#define DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U) +#define DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK) +#define DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U) +#define DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U) +#define DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK) +#define DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U) +#define DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U) +#define DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK) +#define DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U) +#define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U) +#define DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK) +#define DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U) +#define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U) +#define DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK) +#define DCP_PACKET1_TAG_MASK (0xFF000000U) +#define DCP_PACKET1_TAG_SHIFT (24U) +#define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK) + +/*! @name PACKET2 - DCP work packet 2 status register */ +#define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU) +#define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U) +#define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK) +#define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U) +#define DCP_PACKET2_CIPHER_MODE_SHIFT (4U) +#define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK) +#define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U) +#define DCP_PACKET2_KEY_SELECT_SHIFT (8U) +#define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK) +#define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U) +#define DCP_PACKET2_HASH_SELECT_SHIFT (16U) +#define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK) +#define DCP_PACKET2_RSVD_MASK (0xF00000U) +#define DCP_PACKET2_RSVD_SHIFT (20U) +#define DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK) +#define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U) +#define DCP_PACKET2_CIPHER_CFG_SHIFT (24U) +#define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK) + +/*! @name PACKET3 - DCP work packet 3 status register */ +#define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET3_ADDR_SHIFT (0U) +#define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK) + +/*! @name PACKET4 - DCP work packet 4 status register */ +#define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET4_ADDR_SHIFT (0U) +#define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK) + +/*! @name PACKET5 - DCP work packet 5 status register */ +#define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU) +#define DCP_PACKET5_COUNT_SHIFT (0U) +#define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK) + +/*! @name PACKET6 - DCP work packet 6 status register */ +#define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET6_ADDR_SHIFT (0U) +#define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK) + +/*! @name CH0CMDPTR - DCP channel 0 command pointer address register */ +#define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH0CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK) + +/*! @name CH0SEMA - DCP channel 0 semaphore register */ +#define DCP_CH0SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH0SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK) +#define DCP_CH0SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH0SEMA_VALUE_SHIFT (16U) +#define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK) + +/*! @name CH0STAT - DCP channel 0 status register */ +#define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK) +#define DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK) +#define DCP_CH0STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH0STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK) +#define DCP_CH0STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH0STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK) +#define DCP_CH0STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH0STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK) +#define DCP_CH0STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH0STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK) +#define DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH0STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK) +#define DCP_CH0STAT_TAG_MASK (0xFF000000U) +#define DCP_CH0STAT_TAG_SHIFT (24U) +#define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK) + +/*! @name CH0OPTS - DCP channel 0 options register */ +#define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH0OPTS_RSVD_SHIFT (16U) +#define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK) + +/*! @name CH1CMDPTR - DCP channel 1 command pointer address register */ +#define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH1CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK) + +/*! @name CH1SEMA - DCP channel 1 semaphore register */ +#define DCP_CH1SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH1SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK) +#define DCP_CH1SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH1SEMA_VALUE_SHIFT (16U) +#define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK) + +/*! @name CH1STAT - DCP channel 1 status register */ +#define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK) +#define DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK) +#define DCP_CH1STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH1STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK) +#define DCP_CH1STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH1STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK) +#define DCP_CH1STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH1STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK) +#define DCP_CH1STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH1STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK) +#define DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH1STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK) +#define DCP_CH1STAT_TAG_MASK (0xFF000000U) +#define DCP_CH1STAT_TAG_SHIFT (24U) +#define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK) + +/*! @name CH1OPTS - DCP channel 1 options register */ +#define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH1OPTS_RSVD_SHIFT (16U) +#define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK) + +/*! @name CH2CMDPTR - DCP channel 2 command pointer address register */ +#define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH2CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK) + +/*! @name CH2SEMA - DCP channel 2 semaphore register */ +#define DCP_CH2SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH2SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK) +#define DCP_CH2SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH2SEMA_VALUE_SHIFT (16U) +#define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK) + +/*! @name CH2STAT - DCP channel 2 status register */ +#define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK) +#define DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK) +#define DCP_CH2STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH2STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK) +#define DCP_CH2STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH2STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK) +#define DCP_CH2STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH2STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK) +#define DCP_CH2STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH2STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK) +#define DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH2STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK) +#define DCP_CH2STAT_TAG_MASK (0xFF000000U) +#define DCP_CH2STAT_TAG_SHIFT (24U) +#define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK) + +/*! @name CH2OPTS - DCP channel 2 options register */ +#define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH2OPTS_RSVD_SHIFT (16U) +#define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK) + +/*! @name CH3CMDPTR - DCP channel 3 command pointer address register */ +#define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH3CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK) + +/*! @name CH3SEMA - DCP channel 3 semaphore register */ +#define DCP_CH3SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH3SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK) +#define DCP_CH3SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH3SEMA_VALUE_SHIFT (16U) +#define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK) + +/*! @name CH3STAT - DCP channel 3 status register */ +#define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK) +#define DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK) +#define DCP_CH3STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH3STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK) +#define DCP_CH3STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH3STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK) +#define DCP_CH3STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH3STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK) +#define DCP_CH3STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH3STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK) +#define DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH3STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK) +#define DCP_CH3STAT_TAG_MASK (0xFF000000U) +#define DCP_CH3STAT_TAG_SHIFT (24U) +#define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK) + +/*! @name CH3OPTS - DCP channel 3 options register */ +#define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH3OPTS_RSVD_SHIFT (16U) +#define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK) + +/*! @name DBGSELECT - DCP debug select register */ +#define DCP_DBGSELECT_INDEX_MASK (0xFFU) +#define DCP_DBGSELECT_INDEX_SHIFT (0U) +#define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK) +#define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U) +#define DCP_DBGSELECT_RSVD_SHIFT (8U) +#define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK) + +/*! @name DBGDATA - DCP debug data register */ +#define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU) +#define DCP_DBGDATA_DATA_SHIFT (0U) +#define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK) + +/*! @name PAGETABLE - DCP page table register */ +#define DCP_PAGETABLE_ENABLE_MASK (0x1U) +#define DCP_PAGETABLE_ENABLE_SHIFT (0U) +#define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK) +#define DCP_PAGETABLE_FLUSH_MASK (0x2U) +#define DCP_PAGETABLE_FLUSH_SHIFT (1U) +#define DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK) +#define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU) +#define DCP_PAGETABLE_BASE_SHIFT (2U) +#define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK) + +/*! @name VERSION - DCP version register */ +#define DCP_VERSION_STEP_MASK (0xFFFFU) +#define DCP_VERSION_STEP_SHIFT (0U) +#define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK) +#define DCP_VERSION_MINOR_MASK (0xFF0000U) +#define DCP_VERSION_MINOR_SHIFT (16U) +#define DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK) +#define DCP_VERSION_MAJOR_MASK (0xFF000000U) +#define DCP_VERSION_MAJOR_SHIFT (24U) +#define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK) + + +/*! + * @} + */ /* end of group DCP_Register_Masks */ + + +/* DCP - Peripheral instance base addresses */ +/** Peripheral DCP base address */ +#define DCP_BASE (0x2280000u) +/** Peripheral DCP base pointer */ +#define DCP ((DCP_Type *)DCP_BASE) +/** Array initializer of DCP peripheral base addresses */ +#define DCP_BASE_ADDRS { DCP_BASE } +/** Array initializer of DCP peripheral base pointers */ +#define DCP_BASE_PTRS { DCP } +/** Interrupt vectors for the DCP peripheral type */ +#define DCP_IRQS { DCP_IRQ_IRQn } +#define DCP_VMI_IRQS { DCP_VMI_IRQ_IRQn } +#define DCP_SEC_IRQS { DCP_SEC_IRQ_IRQn } + +/*! + * @} + */ /* end of group DCP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ECSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSPI_Peripheral_Access_Layer ECSPI Peripheral Access Layer + * @{ + */ + +/** ECSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t RXDATA; /**< Receive Data Register, offset: 0x0 */ + __O uint32_t TXDATA; /**< Transmit Data Register, offset: 0x4 */ + __IO uint32_t CONREG; /**< Control Register, offset: 0x8 */ + __IO uint32_t CONFIGREG; /**< Config Register, offset: 0xC */ + __IO uint32_t INTREG; /**< Interrupt Control Register, offset: 0x10 */ + __IO uint32_t DMAREG; /**< DMA Control Register, offset: 0x14 */ + __IO uint32_t STATREG; /**< Status Register, offset: 0x18 */ + __IO uint32_t PERIODREG; /**< Sample Period Control Register, offset: 0x1C */ + __IO uint32_t TESTREG; /**< Test Control Register, offset: 0x20 */ + uint8_t RESERVED_0[28]; + __O uint32_t MSGDATA; /**< Message Data Register, offset: 0x40 */ +} ECSPI_Type; + +/* ---------------------------------------------------------------------------- + -- ECSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSPI_Register_Masks ECSPI Register Masks + * @{ + */ + +/*! @name RXDATA - Receive Data Register */ +#define ECSPI_RXDATA_ECSPI_RXDATA_MASK (0xFFFFFFFFU) +#define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT (0U) +#define ECSPI_RXDATA_ECSPI_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_RXDATA_ECSPI_RXDATA_SHIFT)) & ECSPI_RXDATA_ECSPI_RXDATA_MASK) + +/*! @name TXDATA - Transmit Data Register */ +#define ECSPI_TXDATA_ECSPI_TXDATA_MASK (0xFFFFFFFFU) +#define ECSPI_TXDATA_ECSPI_TXDATA_SHIFT (0U) +#define ECSPI_TXDATA_ECSPI_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TXDATA_ECSPI_TXDATA_SHIFT)) & ECSPI_TXDATA_ECSPI_TXDATA_MASK) + +/*! @name CONREG - Control Register */ +#define ECSPI_CONREG_EN_MASK (0x1U) +#define ECSPI_CONREG_EN_SHIFT (0U) +#define ECSPI_CONREG_EN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_EN_SHIFT)) & ECSPI_CONREG_EN_MASK) +#define ECSPI_CONREG_HT_MASK (0x2U) +#define ECSPI_CONREG_HT_SHIFT (1U) +#define ECSPI_CONREG_HT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_HT_SHIFT)) & ECSPI_CONREG_HT_MASK) +#define ECSPI_CONREG_XCH_MASK (0x4U) +#define ECSPI_CONREG_XCH_SHIFT (2U) +#define ECSPI_CONREG_XCH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_XCH_SHIFT)) & ECSPI_CONREG_XCH_MASK) +#define ECSPI_CONREG_SMC_MASK (0x8U) +#define ECSPI_CONREG_SMC_SHIFT (3U) +#define ECSPI_CONREG_SMC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_SMC_SHIFT)) & ECSPI_CONREG_SMC_MASK) +#define ECSPI_CONREG_CHANNEL_MODE_MASK (0xF0U) +#define ECSPI_CONREG_CHANNEL_MODE_SHIFT (4U) +#define ECSPI_CONREG_CHANNEL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_MODE_SHIFT)) & ECSPI_CONREG_CHANNEL_MODE_MASK) +#define ECSPI_CONREG_POST_DIVIDER_MASK (0xF00U) +#define ECSPI_CONREG_POST_DIVIDER_SHIFT (8U) +#define ECSPI_CONREG_POST_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_POST_DIVIDER_SHIFT)) & ECSPI_CONREG_POST_DIVIDER_MASK) +#define ECSPI_CONREG_PRE_DIVIDER_MASK (0xF000U) +#define ECSPI_CONREG_PRE_DIVIDER_SHIFT (12U) +#define ECSPI_CONREG_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_PRE_DIVIDER_SHIFT)) & ECSPI_CONREG_PRE_DIVIDER_MASK) +#define ECSPI_CONREG_DRCTL_MASK (0x30000U) +#define ECSPI_CONREG_DRCTL_SHIFT (16U) +#define ECSPI_CONREG_DRCTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_DRCTL_SHIFT)) & ECSPI_CONREG_DRCTL_MASK) +#define ECSPI_CONREG_CHANNEL_SELECT_MASK (0xC0000U) +#define ECSPI_CONREG_CHANNEL_SELECT_SHIFT (18U) +#define ECSPI_CONREG_CHANNEL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_SELECT_SHIFT)) & ECSPI_CONREG_CHANNEL_SELECT_MASK) +#define ECSPI_CONREG_BURST_LENGTH_MASK (0xFFF00000U) +#define ECSPI_CONREG_BURST_LENGTH_SHIFT (20U) +#define ECSPI_CONREG_BURST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_BURST_LENGTH_SHIFT)) & ECSPI_CONREG_BURST_LENGTH_MASK) + +/*! @name CONFIGREG - Config Register */ +#define ECSPI_CONFIGREG_SCLK_PHA_MASK (0xFU) +#define ECSPI_CONFIGREG_SCLK_PHA_SHIFT (0U) +#define ECSPI_CONFIGREG_SCLK_PHA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_PHA_SHIFT)) & ECSPI_CONFIGREG_SCLK_PHA_MASK) +#define ECSPI_CONFIGREG_SCLK_POL_MASK (0xF0U) +#define ECSPI_CONFIGREG_SCLK_POL_SHIFT (4U) +#define ECSPI_CONFIGREG_SCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_POL_SHIFT)) & ECSPI_CONFIGREG_SCLK_POL_MASK) +#define ECSPI_CONFIGREG_SS_CTL_MASK (0xF00U) +#define ECSPI_CONFIGREG_SS_CTL_SHIFT (8U) +#define ECSPI_CONFIGREG_SS_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_CTL_SHIFT)) & ECSPI_CONFIGREG_SS_CTL_MASK) +#define ECSPI_CONFIGREG_SS_POL_MASK (0xF000U) +#define ECSPI_CONFIGREG_SS_POL_SHIFT (12U) +#define ECSPI_CONFIGREG_SS_POL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_POL_SHIFT)) & ECSPI_CONFIGREG_SS_POL_MASK) +#define ECSPI_CONFIGREG_DATA_CTL_MASK (0xF0000U) +#define ECSPI_CONFIGREG_DATA_CTL_SHIFT (16U) +#define ECSPI_CONFIGREG_DATA_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_DATA_CTL_SHIFT)) & ECSPI_CONFIGREG_DATA_CTL_MASK) +#define ECSPI_CONFIGREG_SCLK_CTL_MASK (0xF00000U) +#define ECSPI_CONFIGREG_SCLK_CTL_SHIFT (20U) +#define ECSPI_CONFIGREG_SCLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_CTL_SHIFT)) & ECSPI_CONFIGREG_SCLK_CTL_MASK) +#define ECSPI_CONFIGREG_HT_LENGTH_MASK (0x1F000000U) +#define ECSPI_CONFIGREG_HT_LENGTH_SHIFT (24U) +#define ECSPI_CONFIGREG_HT_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_HT_LENGTH_SHIFT)) & ECSPI_CONFIGREG_HT_LENGTH_MASK) + +/*! @name INTREG - Interrupt Control Register */ +#define ECSPI_INTREG_TEEN_MASK (0x1U) +#define ECSPI_INTREG_TEEN_SHIFT (0U) +#define ECSPI_INTREG_TEEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TEEN_SHIFT)) & ECSPI_INTREG_TEEN_MASK) +#define ECSPI_INTREG_TDREN_MASK (0x2U) +#define ECSPI_INTREG_TDREN_SHIFT (1U) +#define ECSPI_INTREG_TDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TDREN_SHIFT)) & ECSPI_INTREG_TDREN_MASK) +#define ECSPI_INTREG_TFEN_MASK (0x4U) +#define ECSPI_INTREG_TFEN_SHIFT (2U) +#define ECSPI_INTREG_TFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TFEN_SHIFT)) & ECSPI_INTREG_TFEN_MASK) +#define ECSPI_INTREG_RREN_MASK (0x8U) +#define ECSPI_INTREG_RREN_SHIFT (3U) +#define ECSPI_INTREG_RREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RREN_SHIFT)) & ECSPI_INTREG_RREN_MASK) +#define ECSPI_INTREG_RDREN_MASK (0x10U) +#define ECSPI_INTREG_RDREN_SHIFT (4U) +#define ECSPI_INTREG_RDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RDREN_SHIFT)) & ECSPI_INTREG_RDREN_MASK) +#define ECSPI_INTREG_RFEN_MASK (0x20U) +#define ECSPI_INTREG_RFEN_SHIFT (5U) +#define ECSPI_INTREG_RFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RFEN_SHIFT)) & ECSPI_INTREG_RFEN_MASK) +#define ECSPI_INTREG_ROEN_MASK (0x40U) +#define ECSPI_INTREG_ROEN_SHIFT (6U) +#define ECSPI_INTREG_ROEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_ROEN_SHIFT)) & ECSPI_INTREG_ROEN_MASK) +#define ECSPI_INTREG_TCEN_MASK (0x80U) +#define ECSPI_INTREG_TCEN_SHIFT (7U) +#define ECSPI_INTREG_TCEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TCEN_SHIFT)) & ECSPI_INTREG_TCEN_MASK) + +/*! @name DMAREG - DMA Control Register */ +#define ECSPI_DMAREG_TX_THRESHOLD_MASK (0x3FU) +#define ECSPI_DMAREG_TX_THRESHOLD_SHIFT (0U) +#define ECSPI_DMAREG_TX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_TX_THRESHOLD_MASK) +#define ECSPI_DMAREG_TEDEN_MASK (0x80U) +#define ECSPI_DMAREG_TEDEN_SHIFT (7U) +#define ECSPI_DMAREG_TEDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TEDEN_SHIFT)) & ECSPI_DMAREG_TEDEN_MASK) +#define ECSPI_DMAREG_RX_THRESHOLD_MASK (0x3F0000U) +#define ECSPI_DMAREG_RX_THRESHOLD_SHIFT (16U) +#define ECSPI_DMAREG_RX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_RX_THRESHOLD_MASK) +#define ECSPI_DMAREG_RXDEN_MASK (0x800000U) +#define ECSPI_DMAREG_RXDEN_SHIFT (23U) +#define ECSPI_DMAREG_RXDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXDEN_SHIFT)) & ECSPI_DMAREG_RXDEN_MASK) +#define ECSPI_DMAREG_RX_DMA_LENGTH_MASK (0x3F000000U) +#define ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT (24U) +#define ECSPI_DMAREG_RX_DMA_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT)) & ECSPI_DMAREG_RX_DMA_LENGTH_MASK) +#define ECSPI_DMAREG_RXTDEN_MASK (0x80000000U) +#define ECSPI_DMAREG_RXTDEN_SHIFT (31U) +#define ECSPI_DMAREG_RXTDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXTDEN_SHIFT)) & ECSPI_DMAREG_RXTDEN_MASK) + +/*! @name STATREG - Status Register */ +#define ECSPI_STATREG_TE_MASK (0x1U) +#define ECSPI_STATREG_TE_SHIFT (0U) +#define ECSPI_STATREG_TE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TE_SHIFT)) & ECSPI_STATREG_TE_MASK) +#define ECSPI_STATREG_TDR_MASK (0x2U) +#define ECSPI_STATREG_TDR_SHIFT (1U) +#define ECSPI_STATREG_TDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TDR_SHIFT)) & ECSPI_STATREG_TDR_MASK) +#define ECSPI_STATREG_TF_MASK (0x4U) +#define ECSPI_STATREG_TF_SHIFT (2U) +#define ECSPI_STATREG_TF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TF_SHIFT)) & ECSPI_STATREG_TF_MASK) +#define ECSPI_STATREG_RR_MASK (0x8U) +#define ECSPI_STATREG_RR_SHIFT (3U) +#define ECSPI_STATREG_RR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RR_SHIFT)) & ECSPI_STATREG_RR_MASK) +#define ECSPI_STATREG_RDR_MASK (0x10U) +#define ECSPI_STATREG_RDR_SHIFT (4U) +#define ECSPI_STATREG_RDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RDR_SHIFT)) & ECSPI_STATREG_RDR_MASK) +#define ECSPI_STATREG_RF_MASK (0x20U) +#define ECSPI_STATREG_RF_SHIFT (5U) +#define ECSPI_STATREG_RF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RF_SHIFT)) & ECSPI_STATREG_RF_MASK) +#define ECSPI_STATREG_RO_MASK (0x40U) +#define ECSPI_STATREG_RO_SHIFT (6U) +#define ECSPI_STATREG_RO(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RO_SHIFT)) & ECSPI_STATREG_RO_MASK) +#define ECSPI_STATREG_TC_MASK (0x80U) +#define ECSPI_STATREG_TC_SHIFT (7U) +#define ECSPI_STATREG_TC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TC_SHIFT)) & ECSPI_STATREG_TC_MASK) + +/*! @name PERIODREG - Sample Period Control Register */ +#define ECSPI_PERIODREG_SAMPLE_PERIOD_MASK (0x7FFFU) +#define ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT (0U) +#define ECSPI_PERIODREG_SAMPLE_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT)) & ECSPI_PERIODREG_SAMPLE_PERIOD_MASK) +#define ECSPI_PERIODREG_CSRC_MASK (0x8000U) +#define ECSPI_PERIODREG_CSRC_SHIFT (15U) +#define ECSPI_PERIODREG_CSRC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSRC_SHIFT)) & ECSPI_PERIODREG_CSRC_MASK) +#define ECSPI_PERIODREG_CSD_CTL_MASK (0x3F0000U) +#define ECSPI_PERIODREG_CSD_CTL_SHIFT (16U) +#define ECSPI_PERIODREG_CSD_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSD_CTL_SHIFT)) & ECSPI_PERIODREG_CSD_CTL_MASK) + +/*! @name TESTREG - Test Control Register */ +#define ECSPI_TESTREG_TXCNT_MASK (0x7FU) +#define ECSPI_TESTREG_TXCNT_SHIFT (0U) +#define ECSPI_TESTREG_TXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_TXCNT_SHIFT)) & ECSPI_TESTREG_TXCNT_MASK) +#define ECSPI_TESTREG_RXCNT_MASK (0x7F00U) +#define ECSPI_TESTREG_RXCNT_SHIFT (8U) +#define ECSPI_TESTREG_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_RXCNT_SHIFT)) & ECSPI_TESTREG_RXCNT_MASK) +#define ECSPI_TESTREG_LBC_MASK (0x80000000U) +#define ECSPI_TESTREG_LBC_SHIFT (31U) +#define ECSPI_TESTREG_LBC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_LBC_SHIFT)) & ECSPI_TESTREG_LBC_MASK) + +/*! @name MSGDATA - Message Data Register */ +#define ECSPI_MSGDATA_ECSPI_MSGDATA_MASK (0xFFFFFFFFU) +#define ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT (0U) +#define ECSPI_MSGDATA_ECSPI_MSGDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT)) & ECSPI_MSGDATA_ECSPI_MSGDATA_MASK) + + +/*! + * @} + */ /* end of group ECSPI_Register_Masks */ + + +/* ECSPI - Peripheral instance base addresses */ +/** Peripheral ECSPI1 base address */ +#define ECSPI1_BASE (0x2008000u) +/** Peripheral ECSPI1 base pointer */ +#define ECSPI1 ((ECSPI_Type *)ECSPI1_BASE) +/** Peripheral ECSPI2 base address */ +#define ECSPI2_BASE (0x200C000u) +/** Peripheral ECSPI2 base pointer */ +#define ECSPI2 ((ECSPI_Type *)ECSPI2_BASE) +/** Peripheral ECSPI3 base address */ +#define ECSPI3_BASE (0x2010000u) +/** Peripheral ECSPI3 base pointer */ +#define ECSPI3 ((ECSPI_Type *)ECSPI3_BASE) +/** Peripheral ECSPI4 base address */ +#define ECSPI4_BASE (0x2014000u) +/** Peripheral ECSPI4 base pointer */ +#define ECSPI4 ((ECSPI_Type *)ECSPI4_BASE) +/** Array initializer of ECSPI peripheral base addresses */ +#define ECSPI_BASE_ADDRS { 0u, ECSPI1_BASE, ECSPI2_BASE, ECSPI3_BASE, ECSPI4_BASE } +/** Array initializer of ECSPI peripheral base pointers */ +#define ECSPI_BASE_PTRS { (ECSPI_Type *)0u, ECSPI1, ECSPI2, ECSPI3, ECSPI4 } +/** Interrupt vectors for the ECSPI peripheral type */ +#define ECSPI_IRQS { NotAvail_IRQn, eCSPI1_IRQn, eCSPI2_IRQn, eCSPI3_IRQn, eCSPI4_IRQn } + +/*! + * @} + */ /* end of group ECSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer + * @{ + */ + +/** EIM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CS0GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x0 */ + __IO uint32_t CS0GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x4 */ + __IO uint32_t CS0RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x8 */ + __IO uint32_t CS0RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0xC */ + __IO uint32_t CS0WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x10 */ + __IO uint32_t CS0WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x14 */ + __IO uint32_t CS1GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x18 */ + __IO uint32_t CS1GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x1C */ + __IO uint32_t CS1RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x20 */ + __IO uint32_t CS1RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x24 */ + __IO uint32_t CS1WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x28 */ + __IO uint32_t CS1WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x2C */ + __IO uint32_t CS2GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x30 */ + __IO uint32_t CS2GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x34 */ + __IO uint32_t CS2RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x38 */ + __IO uint32_t CS2RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x3C */ + __IO uint32_t CS2WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x40 */ + __IO uint32_t CS2WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x44 */ + __IO uint32_t CS3GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x48 */ + __IO uint32_t CS3GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x4C */ + __IO uint32_t CS3RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x50 */ + __IO uint32_t CS3RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x54 */ + __IO uint32_t CS3WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x58 */ + __IO uint32_t CS3WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x5C */ + __IO uint32_t CS4GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x60 */ + __IO uint32_t CS4GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x64 */ + __IO uint32_t CS4RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x68 */ + __IO uint32_t CS4RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x6C */ + __IO uint32_t CS4WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x70 */ + __IO uint32_t CS4WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x74 */ + __IO uint32_t CS5GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x78 */ + __IO uint32_t CS5GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x7C */ + __IO uint32_t CS5RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x80 */ + __IO uint32_t CS5RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x84 */ + __IO uint32_t CS5WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x88 */ + __IO uint32_t CS5WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x8C */ + __IO uint32_t WCR; /**< EIM Configuration Register, offset: 0x90 */ +} EIM_Type; + +/* ---------------------------------------------------------------------------- + -- EIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Register_Masks EIM Register Masks + * @{ + */ + +/*! @name CS0GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS0GCR1_CSEN_MASK (0x1U) +#define EIM_CS0GCR1_CSEN_SHIFT (0U) +#define EIM_CS0GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_CSEN_SHIFT)) & EIM_CS0GCR1_CSEN_MASK) +#define EIM_CS0GCR1_SWR_MASK (0x2U) +#define EIM_CS0GCR1_SWR_SHIFT (1U) +#define EIM_CS0GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_SWR_SHIFT)) & EIM_CS0GCR1_SWR_MASK) +#define EIM_CS0GCR1_SRD_MASK (0x4U) +#define EIM_CS0GCR1_SRD_SHIFT (2U) +#define EIM_CS0GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_SRD_SHIFT)) & EIM_CS0GCR1_SRD_MASK) +#define EIM_CS0GCR1_MUM_MASK (0x8U) +#define EIM_CS0GCR1_MUM_SHIFT (3U) +#define EIM_CS0GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_MUM_SHIFT)) & EIM_CS0GCR1_MUM_MASK) +#define EIM_CS0GCR1_WFL_MASK (0x10U) +#define EIM_CS0GCR1_WFL_SHIFT (4U) +#define EIM_CS0GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_WFL_SHIFT)) & EIM_CS0GCR1_WFL_MASK) +#define EIM_CS0GCR1_RFL_MASK (0x20U) +#define EIM_CS0GCR1_RFL_SHIFT (5U) +#define EIM_CS0GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_RFL_SHIFT)) & EIM_CS0GCR1_RFL_MASK) +#define EIM_CS0GCR1_CRE_MASK (0x40U) +#define EIM_CS0GCR1_CRE_SHIFT (6U) +#define EIM_CS0GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_CRE_SHIFT)) & EIM_CS0GCR1_CRE_MASK) +#define EIM_CS0GCR1_CREP_MASK (0x80U) +#define EIM_CS0GCR1_CREP_SHIFT (7U) +#define EIM_CS0GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_CREP_SHIFT)) & EIM_CS0GCR1_CREP_MASK) +#define EIM_CS0GCR1_BL_MASK (0x700U) +#define EIM_CS0GCR1_BL_SHIFT (8U) +#define EIM_CS0GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_BL_SHIFT)) & EIM_CS0GCR1_BL_MASK) +#define EIM_CS0GCR1_WC_MASK (0x800U) +#define EIM_CS0GCR1_WC_SHIFT (11U) +#define EIM_CS0GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_WC_SHIFT)) & EIM_CS0GCR1_WC_MASK) +#define EIM_CS0GCR1_BCD_MASK (0x3000U) +#define EIM_CS0GCR1_BCD_SHIFT (12U) +#define EIM_CS0GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_BCD_SHIFT)) & EIM_CS0GCR1_BCD_MASK) +#define EIM_CS0GCR1_BCS_MASK (0xC000U) +#define EIM_CS0GCR1_BCS_SHIFT (14U) +#define EIM_CS0GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_BCS_SHIFT)) & EIM_CS0GCR1_BCS_MASK) +#define EIM_CS0GCR1_DSZ_MASK (0x70000U) +#define EIM_CS0GCR1_DSZ_SHIFT (16U) +#define EIM_CS0GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_DSZ_SHIFT)) & EIM_CS0GCR1_DSZ_MASK) +#define EIM_CS0GCR1_SP_MASK (0x80000U) +#define EIM_CS0GCR1_SP_SHIFT (19U) +#define EIM_CS0GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_SP_SHIFT)) & EIM_CS0GCR1_SP_MASK) +#define EIM_CS0GCR1_CSREC_MASK (0x700000U) +#define EIM_CS0GCR1_CSREC_SHIFT (20U) +#define EIM_CS0GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_CSREC_SHIFT)) & EIM_CS0GCR1_CSREC_MASK) +#define EIM_CS0GCR1_AUS_MASK (0x800000U) +#define EIM_CS0GCR1_AUS_SHIFT (23U) +#define EIM_CS0GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_AUS_SHIFT)) & EIM_CS0GCR1_AUS_MASK) +#define EIM_CS0GCR1_GBC_MASK (0x7000000U) +#define EIM_CS0GCR1_GBC_SHIFT (24U) +#define EIM_CS0GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_GBC_SHIFT)) & EIM_CS0GCR1_GBC_MASK) +#define EIM_CS0GCR1_WP_MASK (0x8000000U) +#define EIM_CS0GCR1_WP_SHIFT (27U) +#define EIM_CS0GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_WP_SHIFT)) & EIM_CS0GCR1_WP_MASK) +#define EIM_CS0GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS0GCR1_PSZ_SHIFT (28U) +#define EIM_CS0GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_PSZ_SHIFT)) & EIM_CS0GCR1_PSZ_MASK) + +/*! @name CS0GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS0GCR2_ADH_MASK (0x3U) +#define EIM_CS0GCR2_ADH_SHIFT (0U) +#define EIM_CS0GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_ADH_SHIFT)) & EIM_CS0GCR2_ADH_MASK) +#define EIM_CS0GCR2_DAPS_MASK (0xF0U) +#define EIM_CS0GCR2_DAPS_SHIFT (4U) +#define EIM_CS0GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_DAPS_SHIFT)) & EIM_CS0GCR2_DAPS_MASK) +#define EIM_CS0GCR2_DAE_MASK (0x100U) +#define EIM_CS0GCR2_DAE_SHIFT (8U) +#define EIM_CS0GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_DAE_SHIFT)) & EIM_CS0GCR2_DAE_MASK) +#define EIM_CS0GCR2_DAP_MASK (0x200U) +#define EIM_CS0GCR2_DAP_SHIFT (9U) +#define EIM_CS0GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_DAP_SHIFT)) & EIM_CS0GCR2_DAP_MASK) +#define EIM_CS0GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS0GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS0GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS0GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS0RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS0RCR1_RCSN_MASK (0x7U) +#define EIM_CS0RCR1_RCSN_SHIFT (0U) +#define EIM_CS0RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RCSN_SHIFT)) & EIM_CS0RCR1_RCSN_MASK) +#define EIM_CS0RCR1_RCSA_MASK (0x70U) +#define EIM_CS0RCR1_RCSA_SHIFT (4U) +#define EIM_CS0RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RCSA_SHIFT)) & EIM_CS0RCR1_RCSA_MASK) +#define EIM_CS0RCR1_OEN_MASK (0x700U) +#define EIM_CS0RCR1_OEN_SHIFT (8U) +#define EIM_CS0RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_OEN_SHIFT)) & EIM_CS0RCR1_OEN_MASK) +#define EIM_CS0RCR1_OEA_MASK (0x7000U) +#define EIM_CS0RCR1_OEA_SHIFT (12U) +#define EIM_CS0RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_OEA_SHIFT)) & EIM_CS0RCR1_OEA_MASK) +#define EIM_CS0RCR1_RADVN_MASK (0x70000U) +#define EIM_CS0RCR1_RADVN_SHIFT (16U) +#define EIM_CS0RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RADVN_SHIFT)) & EIM_CS0RCR1_RADVN_MASK) +#define EIM_CS0RCR1_RAL_MASK (0x80000U) +#define EIM_CS0RCR1_RAL_SHIFT (19U) +#define EIM_CS0RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RAL_SHIFT)) & EIM_CS0RCR1_RAL_MASK) +#define EIM_CS0RCR1_RADVA_MASK (0x700000U) +#define EIM_CS0RCR1_RADVA_SHIFT (20U) +#define EIM_CS0RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RADVA_SHIFT)) & EIM_CS0RCR1_RADVA_MASK) +#define EIM_CS0RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS0RCR1_RWSC_SHIFT (24U) +#define EIM_CS0RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RWSC_SHIFT)) & EIM_CS0RCR1_RWSC_MASK) + +/*! @name CS0RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS0RCR2_RBEN_MASK (0x7U) +#define EIM_CS0RCR2_RBEN_SHIFT (0U) +#define EIM_CS0RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_RBEN_SHIFT)) & EIM_CS0RCR2_RBEN_MASK) +#define EIM_CS0RCR2_RBE_MASK (0x8U) +#define EIM_CS0RCR2_RBE_SHIFT (3U) +#define EIM_CS0RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_RBE_SHIFT)) & EIM_CS0RCR2_RBE_MASK) +#define EIM_CS0RCR2_RBEA_MASK (0x70U) +#define EIM_CS0RCR2_RBEA_SHIFT (4U) +#define EIM_CS0RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_RBEA_SHIFT)) & EIM_CS0RCR2_RBEA_MASK) +#define EIM_CS0RCR2_RL_MASK (0x300U) +#define EIM_CS0RCR2_RL_SHIFT (8U) +#define EIM_CS0RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_RL_SHIFT)) & EIM_CS0RCR2_RL_MASK) +#define EIM_CS0RCR2_PAT_MASK (0x7000U) +#define EIM_CS0RCR2_PAT_SHIFT (12U) +#define EIM_CS0RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_PAT_SHIFT)) & EIM_CS0RCR2_PAT_MASK) +#define EIM_CS0RCR2_APR_MASK (0x8000U) +#define EIM_CS0RCR2_APR_SHIFT (15U) +#define EIM_CS0RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_APR_SHIFT)) & EIM_CS0RCR2_APR_MASK) + +/*! @name CS0WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS0WCR1_WCSN_MASK (0x7U) +#define EIM_CS0WCR1_WCSN_SHIFT (0U) +#define EIM_CS0WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WCSN_SHIFT)) & EIM_CS0WCR1_WCSN_MASK) +#define EIM_CS0WCR1_WCSA_MASK (0x38U) +#define EIM_CS0WCR1_WCSA_SHIFT (3U) +#define EIM_CS0WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WCSA_SHIFT)) & EIM_CS0WCR1_WCSA_MASK) +#define EIM_CS0WCR1_WEN_MASK (0x1C0U) +#define EIM_CS0WCR1_WEN_SHIFT (6U) +#define EIM_CS0WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WEN_SHIFT)) & EIM_CS0WCR1_WEN_MASK) +#define EIM_CS0WCR1_WEA_MASK (0xE00U) +#define EIM_CS0WCR1_WEA_SHIFT (9U) +#define EIM_CS0WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WEA_SHIFT)) & EIM_CS0WCR1_WEA_MASK) +#define EIM_CS0WCR1_WBEN_MASK (0x7000U) +#define EIM_CS0WCR1_WBEN_SHIFT (12U) +#define EIM_CS0WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WBEN_SHIFT)) & EIM_CS0WCR1_WBEN_MASK) +#define EIM_CS0WCR1_WBEA_MASK (0x38000U) +#define EIM_CS0WCR1_WBEA_SHIFT (15U) +#define EIM_CS0WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WBEA_SHIFT)) & EIM_CS0WCR1_WBEA_MASK) +#define EIM_CS0WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS0WCR1_WADVN_SHIFT (18U) +#define EIM_CS0WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WADVN_SHIFT)) & EIM_CS0WCR1_WADVN_MASK) +#define EIM_CS0WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS0WCR1_WADVA_SHIFT (21U) +#define EIM_CS0WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WADVA_SHIFT)) & EIM_CS0WCR1_WADVA_MASK) +#define EIM_CS0WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS0WCR1_WWSC_SHIFT (24U) +#define EIM_CS0WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WWSC_SHIFT)) & EIM_CS0WCR1_WWSC_MASK) +#define EIM_CS0WCR1_WBED_MASK (0x40000000U) +#define EIM_CS0WCR1_WBED_SHIFT (30U) +#define EIM_CS0WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WBED_SHIFT)) & EIM_CS0WCR1_WBED_MASK) +#define EIM_CS0WCR1_WAL_MASK (0x80000000U) +#define EIM_CS0WCR1_WAL_SHIFT (31U) +#define EIM_CS0WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WAL_SHIFT)) & EIM_CS0WCR1_WAL_MASK) + +/*! @name CS0WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS0WCR2_WBCDD_MASK (0x1U) +#define EIM_CS0WCR2_WBCDD_SHIFT (0U) +#define EIM_CS0WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR2_WBCDD_SHIFT)) & EIM_CS0WCR2_WBCDD_MASK) + +/*! @name CS1GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS1GCR1_CSEN_MASK (0x1U) +#define EIM_CS1GCR1_CSEN_SHIFT (0U) +#define EIM_CS1GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_CSEN_SHIFT)) & EIM_CS1GCR1_CSEN_MASK) +#define EIM_CS1GCR1_SWR_MASK (0x2U) +#define EIM_CS1GCR1_SWR_SHIFT (1U) +#define EIM_CS1GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_SWR_SHIFT)) & EIM_CS1GCR1_SWR_MASK) +#define EIM_CS1GCR1_SRD_MASK (0x4U) +#define EIM_CS1GCR1_SRD_SHIFT (2U) +#define EIM_CS1GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_SRD_SHIFT)) & EIM_CS1GCR1_SRD_MASK) +#define EIM_CS1GCR1_MUM_MASK (0x8U) +#define EIM_CS1GCR1_MUM_SHIFT (3U) +#define EIM_CS1GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_MUM_SHIFT)) & EIM_CS1GCR1_MUM_MASK) +#define EIM_CS1GCR1_WFL_MASK (0x10U) +#define EIM_CS1GCR1_WFL_SHIFT (4U) +#define EIM_CS1GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_WFL_SHIFT)) & EIM_CS1GCR1_WFL_MASK) +#define EIM_CS1GCR1_RFL_MASK (0x20U) +#define EIM_CS1GCR1_RFL_SHIFT (5U) +#define EIM_CS1GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_RFL_SHIFT)) & EIM_CS1GCR1_RFL_MASK) +#define EIM_CS1GCR1_CRE_MASK (0x40U) +#define EIM_CS1GCR1_CRE_SHIFT (6U) +#define EIM_CS1GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_CRE_SHIFT)) & EIM_CS1GCR1_CRE_MASK) +#define EIM_CS1GCR1_CREP_MASK (0x80U) +#define EIM_CS1GCR1_CREP_SHIFT (7U) +#define EIM_CS1GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_CREP_SHIFT)) & EIM_CS1GCR1_CREP_MASK) +#define EIM_CS1GCR1_BL_MASK (0x700U) +#define EIM_CS1GCR1_BL_SHIFT (8U) +#define EIM_CS1GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_BL_SHIFT)) & EIM_CS1GCR1_BL_MASK) +#define EIM_CS1GCR1_WC_MASK (0x800U) +#define EIM_CS1GCR1_WC_SHIFT (11U) +#define EIM_CS1GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_WC_SHIFT)) & EIM_CS1GCR1_WC_MASK) +#define EIM_CS1GCR1_BCD_MASK (0x3000U) +#define EIM_CS1GCR1_BCD_SHIFT (12U) +#define EIM_CS1GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_BCD_SHIFT)) & EIM_CS1GCR1_BCD_MASK) +#define EIM_CS1GCR1_BCS_MASK (0xC000U) +#define EIM_CS1GCR1_BCS_SHIFT (14U) +#define EIM_CS1GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_BCS_SHIFT)) & EIM_CS1GCR1_BCS_MASK) +#define EIM_CS1GCR1_DSZ_MASK (0x70000U) +#define EIM_CS1GCR1_DSZ_SHIFT (16U) +#define EIM_CS1GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_DSZ_SHIFT)) & EIM_CS1GCR1_DSZ_MASK) +#define EIM_CS1GCR1_SP_MASK (0x80000U) +#define EIM_CS1GCR1_SP_SHIFT (19U) +#define EIM_CS1GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_SP_SHIFT)) & EIM_CS1GCR1_SP_MASK) +#define EIM_CS1GCR1_CSREC_MASK (0x700000U) +#define EIM_CS1GCR1_CSREC_SHIFT (20U) +#define EIM_CS1GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_CSREC_SHIFT)) & EIM_CS1GCR1_CSREC_MASK) +#define EIM_CS1GCR1_AUS_MASK (0x800000U) +#define EIM_CS1GCR1_AUS_SHIFT (23U) +#define EIM_CS1GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_AUS_SHIFT)) & EIM_CS1GCR1_AUS_MASK) +#define EIM_CS1GCR1_GBC_MASK (0x7000000U) +#define EIM_CS1GCR1_GBC_SHIFT (24U) +#define EIM_CS1GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_GBC_SHIFT)) & EIM_CS1GCR1_GBC_MASK) +#define EIM_CS1GCR1_WP_MASK (0x8000000U) +#define EIM_CS1GCR1_WP_SHIFT (27U) +#define EIM_CS1GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_WP_SHIFT)) & EIM_CS1GCR1_WP_MASK) +#define EIM_CS1GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS1GCR1_PSZ_SHIFT (28U) +#define EIM_CS1GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_PSZ_SHIFT)) & EIM_CS1GCR1_PSZ_MASK) + +/*! @name CS1GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS1GCR2_ADH_MASK (0x3U) +#define EIM_CS1GCR2_ADH_SHIFT (0U) +#define EIM_CS1GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_ADH_SHIFT)) & EIM_CS1GCR2_ADH_MASK) +#define EIM_CS1GCR2_DAPS_MASK (0xF0U) +#define EIM_CS1GCR2_DAPS_SHIFT (4U) +#define EIM_CS1GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_DAPS_SHIFT)) & EIM_CS1GCR2_DAPS_MASK) +#define EIM_CS1GCR2_DAE_MASK (0x100U) +#define EIM_CS1GCR2_DAE_SHIFT (8U) +#define EIM_CS1GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_DAE_SHIFT)) & EIM_CS1GCR2_DAE_MASK) +#define EIM_CS1GCR2_DAP_MASK (0x200U) +#define EIM_CS1GCR2_DAP_SHIFT (9U) +#define EIM_CS1GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_DAP_SHIFT)) & EIM_CS1GCR2_DAP_MASK) +#define EIM_CS1GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS1GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS1GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS1GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS1RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS1RCR1_RCSN_MASK (0x7U) +#define EIM_CS1RCR1_RCSN_SHIFT (0U) +#define EIM_CS1RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RCSN_SHIFT)) & EIM_CS1RCR1_RCSN_MASK) +#define EIM_CS1RCR1_RCSA_MASK (0x70U) +#define EIM_CS1RCR1_RCSA_SHIFT (4U) +#define EIM_CS1RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RCSA_SHIFT)) & EIM_CS1RCR1_RCSA_MASK) +#define EIM_CS1RCR1_OEN_MASK (0x700U) +#define EIM_CS1RCR1_OEN_SHIFT (8U) +#define EIM_CS1RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_OEN_SHIFT)) & EIM_CS1RCR1_OEN_MASK) +#define EIM_CS1RCR1_OEA_MASK (0x7000U) +#define EIM_CS1RCR1_OEA_SHIFT (12U) +#define EIM_CS1RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_OEA_SHIFT)) & EIM_CS1RCR1_OEA_MASK) +#define EIM_CS1RCR1_RADVN_MASK (0x70000U) +#define EIM_CS1RCR1_RADVN_SHIFT (16U) +#define EIM_CS1RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RADVN_SHIFT)) & EIM_CS1RCR1_RADVN_MASK) +#define EIM_CS1RCR1_RAL_MASK (0x80000U) +#define EIM_CS1RCR1_RAL_SHIFT (19U) +#define EIM_CS1RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RAL_SHIFT)) & EIM_CS1RCR1_RAL_MASK) +#define EIM_CS1RCR1_RADVA_MASK (0x700000U) +#define EIM_CS1RCR1_RADVA_SHIFT (20U) +#define EIM_CS1RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RADVA_SHIFT)) & EIM_CS1RCR1_RADVA_MASK) +#define EIM_CS1RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS1RCR1_RWSC_SHIFT (24U) +#define EIM_CS1RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RWSC_SHIFT)) & EIM_CS1RCR1_RWSC_MASK) + +/*! @name CS1RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS1RCR2_RBEN_MASK (0x7U) +#define EIM_CS1RCR2_RBEN_SHIFT (0U) +#define EIM_CS1RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_RBEN_SHIFT)) & EIM_CS1RCR2_RBEN_MASK) +#define EIM_CS1RCR2_RBE_MASK (0x8U) +#define EIM_CS1RCR2_RBE_SHIFT (3U) +#define EIM_CS1RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_RBE_SHIFT)) & EIM_CS1RCR2_RBE_MASK) +#define EIM_CS1RCR2_RBEA_MASK (0x70U) +#define EIM_CS1RCR2_RBEA_SHIFT (4U) +#define EIM_CS1RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_RBEA_SHIFT)) & EIM_CS1RCR2_RBEA_MASK) +#define EIM_CS1RCR2_RL_MASK (0x300U) +#define EIM_CS1RCR2_RL_SHIFT (8U) +#define EIM_CS1RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_RL_SHIFT)) & EIM_CS1RCR2_RL_MASK) +#define EIM_CS1RCR2_PAT_MASK (0x7000U) +#define EIM_CS1RCR2_PAT_SHIFT (12U) +#define EIM_CS1RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_PAT_SHIFT)) & EIM_CS1RCR2_PAT_MASK) +#define EIM_CS1RCR2_APR_MASK (0x8000U) +#define EIM_CS1RCR2_APR_SHIFT (15U) +#define EIM_CS1RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_APR_SHIFT)) & EIM_CS1RCR2_APR_MASK) + +/*! @name CS1WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS1WCR1_WCSN_MASK (0x7U) +#define EIM_CS1WCR1_WCSN_SHIFT (0U) +#define EIM_CS1WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WCSN_SHIFT)) & EIM_CS1WCR1_WCSN_MASK) +#define EIM_CS1WCR1_WCSA_MASK (0x38U) +#define EIM_CS1WCR1_WCSA_SHIFT (3U) +#define EIM_CS1WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WCSA_SHIFT)) & EIM_CS1WCR1_WCSA_MASK) +#define EIM_CS1WCR1_WEN_MASK (0x1C0U) +#define EIM_CS1WCR1_WEN_SHIFT (6U) +#define EIM_CS1WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WEN_SHIFT)) & EIM_CS1WCR1_WEN_MASK) +#define EIM_CS1WCR1_WEA_MASK (0xE00U) +#define EIM_CS1WCR1_WEA_SHIFT (9U) +#define EIM_CS1WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WEA_SHIFT)) & EIM_CS1WCR1_WEA_MASK) +#define EIM_CS1WCR1_WBEN_MASK (0x7000U) +#define EIM_CS1WCR1_WBEN_SHIFT (12U) +#define EIM_CS1WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WBEN_SHIFT)) & EIM_CS1WCR1_WBEN_MASK) +#define EIM_CS1WCR1_WBEA_MASK (0x38000U) +#define EIM_CS1WCR1_WBEA_SHIFT (15U) +#define EIM_CS1WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WBEA_SHIFT)) & EIM_CS1WCR1_WBEA_MASK) +#define EIM_CS1WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS1WCR1_WADVN_SHIFT (18U) +#define EIM_CS1WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WADVN_SHIFT)) & EIM_CS1WCR1_WADVN_MASK) +#define EIM_CS1WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS1WCR1_WADVA_SHIFT (21U) +#define EIM_CS1WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WADVA_SHIFT)) & EIM_CS1WCR1_WADVA_MASK) +#define EIM_CS1WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS1WCR1_WWSC_SHIFT (24U) +#define EIM_CS1WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WWSC_SHIFT)) & EIM_CS1WCR1_WWSC_MASK) +#define EIM_CS1WCR1_WBED_MASK (0x40000000U) +#define EIM_CS1WCR1_WBED_SHIFT (30U) +#define EIM_CS1WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WBED_SHIFT)) & EIM_CS1WCR1_WBED_MASK) +#define EIM_CS1WCR1_WAL_MASK (0x80000000U) +#define EIM_CS1WCR1_WAL_SHIFT (31U) +#define EIM_CS1WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WAL_SHIFT)) & EIM_CS1WCR1_WAL_MASK) + +/*! @name CS1WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS1WCR2_WBCDD_MASK (0x1U) +#define EIM_CS1WCR2_WBCDD_SHIFT (0U) +#define EIM_CS1WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR2_WBCDD_SHIFT)) & EIM_CS1WCR2_WBCDD_MASK) + +/*! @name CS2GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS2GCR1_CSEN_MASK (0x1U) +#define EIM_CS2GCR1_CSEN_SHIFT (0U) +#define EIM_CS2GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_CSEN_SHIFT)) & EIM_CS2GCR1_CSEN_MASK) +#define EIM_CS2GCR1_SWR_MASK (0x2U) +#define EIM_CS2GCR1_SWR_SHIFT (1U) +#define EIM_CS2GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_SWR_SHIFT)) & EIM_CS2GCR1_SWR_MASK) +#define EIM_CS2GCR1_SRD_MASK (0x4U) +#define EIM_CS2GCR1_SRD_SHIFT (2U) +#define EIM_CS2GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_SRD_SHIFT)) & EIM_CS2GCR1_SRD_MASK) +#define EIM_CS2GCR1_MUM_MASK (0x8U) +#define EIM_CS2GCR1_MUM_SHIFT (3U) +#define EIM_CS2GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_MUM_SHIFT)) & EIM_CS2GCR1_MUM_MASK) +#define EIM_CS2GCR1_WFL_MASK (0x10U) +#define EIM_CS2GCR1_WFL_SHIFT (4U) +#define EIM_CS2GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_WFL_SHIFT)) & EIM_CS2GCR1_WFL_MASK) +#define EIM_CS2GCR1_RFL_MASK (0x20U) +#define EIM_CS2GCR1_RFL_SHIFT (5U) +#define EIM_CS2GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_RFL_SHIFT)) & EIM_CS2GCR1_RFL_MASK) +#define EIM_CS2GCR1_CRE_MASK (0x40U) +#define EIM_CS2GCR1_CRE_SHIFT (6U) +#define EIM_CS2GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_CRE_SHIFT)) & EIM_CS2GCR1_CRE_MASK) +#define EIM_CS2GCR1_CREP_MASK (0x80U) +#define EIM_CS2GCR1_CREP_SHIFT (7U) +#define EIM_CS2GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_CREP_SHIFT)) & EIM_CS2GCR1_CREP_MASK) +#define EIM_CS2GCR1_BL_MASK (0x700U) +#define EIM_CS2GCR1_BL_SHIFT (8U) +#define EIM_CS2GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_BL_SHIFT)) & EIM_CS2GCR1_BL_MASK) +#define EIM_CS2GCR1_WC_MASK (0x800U) +#define EIM_CS2GCR1_WC_SHIFT (11U) +#define EIM_CS2GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_WC_SHIFT)) & EIM_CS2GCR1_WC_MASK) +#define EIM_CS2GCR1_BCD_MASK (0x3000U) +#define EIM_CS2GCR1_BCD_SHIFT (12U) +#define EIM_CS2GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_BCD_SHIFT)) & EIM_CS2GCR1_BCD_MASK) +#define EIM_CS2GCR1_BCS_MASK (0xC000U) +#define EIM_CS2GCR1_BCS_SHIFT (14U) +#define EIM_CS2GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_BCS_SHIFT)) & EIM_CS2GCR1_BCS_MASK) +#define EIM_CS2GCR1_DSZ_MASK (0x70000U) +#define EIM_CS2GCR1_DSZ_SHIFT (16U) +#define EIM_CS2GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_DSZ_SHIFT)) & EIM_CS2GCR1_DSZ_MASK) +#define EIM_CS2GCR1_SP_MASK (0x80000U) +#define EIM_CS2GCR1_SP_SHIFT (19U) +#define EIM_CS2GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_SP_SHIFT)) & EIM_CS2GCR1_SP_MASK) +#define EIM_CS2GCR1_CSREC_MASK (0x700000U) +#define EIM_CS2GCR1_CSREC_SHIFT (20U) +#define EIM_CS2GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_CSREC_SHIFT)) & EIM_CS2GCR1_CSREC_MASK) +#define EIM_CS2GCR1_AUS_MASK (0x800000U) +#define EIM_CS2GCR1_AUS_SHIFT (23U) +#define EIM_CS2GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_AUS_SHIFT)) & EIM_CS2GCR1_AUS_MASK) +#define EIM_CS2GCR1_GBC_MASK (0x7000000U) +#define EIM_CS2GCR1_GBC_SHIFT (24U) +#define EIM_CS2GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_GBC_SHIFT)) & EIM_CS2GCR1_GBC_MASK) +#define EIM_CS2GCR1_WP_MASK (0x8000000U) +#define EIM_CS2GCR1_WP_SHIFT (27U) +#define EIM_CS2GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_WP_SHIFT)) & EIM_CS2GCR1_WP_MASK) +#define EIM_CS2GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS2GCR1_PSZ_SHIFT (28U) +#define EIM_CS2GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_PSZ_SHIFT)) & EIM_CS2GCR1_PSZ_MASK) + +/*! @name CS2GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS2GCR2_ADH_MASK (0x3U) +#define EIM_CS2GCR2_ADH_SHIFT (0U) +#define EIM_CS2GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_ADH_SHIFT)) & EIM_CS2GCR2_ADH_MASK) +#define EIM_CS2GCR2_DAPS_MASK (0xF0U) +#define EIM_CS2GCR2_DAPS_SHIFT (4U) +#define EIM_CS2GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_DAPS_SHIFT)) & EIM_CS2GCR2_DAPS_MASK) +#define EIM_CS2GCR2_DAE_MASK (0x100U) +#define EIM_CS2GCR2_DAE_SHIFT (8U) +#define EIM_CS2GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_DAE_SHIFT)) & EIM_CS2GCR2_DAE_MASK) +#define EIM_CS2GCR2_DAP_MASK (0x200U) +#define EIM_CS2GCR2_DAP_SHIFT (9U) +#define EIM_CS2GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_DAP_SHIFT)) & EIM_CS2GCR2_DAP_MASK) +#define EIM_CS2GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS2GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS2GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS2GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS2RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS2RCR1_RCSN_MASK (0x7U) +#define EIM_CS2RCR1_RCSN_SHIFT (0U) +#define EIM_CS2RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RCSN_SHIFT)) & EIM_CS2RCR1_RCSN_MASK) +#define EIM_CS2RCR1_RCSA_MASK (0x70U) +#define EIM_CS2RCR1_RCSA_SHIFT (4U) +#define EIM_CS2RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RCSA_SHIFT)) & EIM_CS2RCR1_RCSA_MASK) +#define EIM_CS2RCR1_OEN_MASK (0x700U) +#define EIM_CS2RCR1_OEN_SHIFT (8U) +#define EIM_CS2RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_OEN_SHIFT)) & EIM_CS2RCR1_OEN_MASK) +#define EIM_CS2RCR1_OEA_MASK (0x7000U) +#define EIM_CS2RCR1_OEA_SHIFT (12U) +#define EIM_CS2RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_OEA_SHIFT)) & EIM_CS2RCR1_OEA_MASK) +#define EIM_CS2RCR1_RADVN_MASK (0x70000U) +#define EIM_CS2RCR1_RADVN_SHIFT (16U) +#define EIM_CS2RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RADVN_SHIFT)) & EIM_CS2RCR1_RADVN_MASK) +#define EIM_CS2RCR1_RAL_MASK (0x80000U) +#define EIM_CS2RCR1_RAL_SHIFT (19U) +#define EIM_CS2RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RAL_SHIFT)) & EIM_CS2RCR1_RAL_MASK) +#define EIM_CS2RCR1_RADVA_MASK (0x700000U) +#define EIM_CS2RCR1_RADVA_SHIFT (20U) +#define EIM_CS2RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RADVA_SHIFT)) & EIM_CS2RCR1_RADVA_MASK) +#define EIM_CS2RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS2RCR1_RWSC_SHIFT (24U) +#define EIM_CS2RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RWSC_SHIFT)) & EIM_CS2RCR1_RWSC_MASK) + +/*! @name CS2RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS2RCR2_RBEN_MASK (0x7U) +#define EIM_CS2RCR2_RBEN_SHIFT (0U) +#define EIM_CS2RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_RBEN_SHIFT)) & EIM_CS2RCR2_RBEN_MASK) +#define EIM_CS2RCR2_RBE_MASK (0x8U) +#define EIM_CS2RCR2_RBE_SHIFT (3U) +#define EIM_CS2RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_RBE_SHIFT)) & EIM_CS2RCR2_RBE_MASK) +#define EIM_CS2RCR2_RBEA_MASK (0x70U) +#define EIM_CS2RCR2_RBEA_SHIFT (4U) +#define EIM_CS2RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_RBEA_SHIFT)) & EIM_CS2RCR2_RBEA_MASK) +#define EIM_CS2RCR2_RL_MASK (0x300U) +#define EIM_CS2RCR2_RL_SHIFT (8U) +#define EIM_CS2RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_RL_SHIFT)) & EIM_CS2RCR2_RL_MASK) +#define EIM_CS2RCR2_PAT_MASK (0x7000U) +#define EIM_CS2RCR2_PAT_SHIFT (12U) +#define EIM_CS2RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_PAT_SHIFT)) & EIM_CS2RCR2_PAT_MASK) +#define EIM_CS2RCR2_APR_MASK (0x8000U) +#define EIM_CS2RCR2_APR_SHIFT (15U) +#define EIM_CS2RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_APR_SHIFT)) & EIM_CS2RCR2_APR_MASK) + +/*! @name CS2WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS2WCR1_WCSN_MASK (0x7U) +#define EIM_CS2WCR1_WCSN_SHIFT (0U) +#define EIM_CS2WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WCSN_SHIFT)) & EIM_CS2WCR1_WCSN_MASK) +#define EIM_CS2WCR1_WCSA_MASK (0x38U) +#define EIM_CS2WCR1_WCSA_SHIFT (3U) +#define EIM_CS2WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WCSA_SHIFT)) & EIM_CS2WCR1_WCSA_MASK) +#define EIM_CS2WCR1_WEN_MASK (0x1C0U) +#define EIM_CS2WCR1_WEN_SHIFT (6U) +#define EIM_CS2WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WEN_SHIFT)) & EIM_CS2WCR1_WEN_MASK) +#define EIM_CS2WCR1_WEA_MASK (0xE00U) +#define EIM_CS2WCR1_WEA_SHIFT (9U) +#define EIM_CS2WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WEA_SHIFT)) & EIM_CS2WCR1_WEA_MASK) +#define EIM_CS2WCR1_WBEN_MASK (0x7000U) +#define EIM_CS2WCR1_WBEN_SHIFT (12U) +#define EIM_CS2WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WBEN_SHIFT)) & EIM_CS2WCR1_WBEN_MASK) +#define EIM_CS2WCR1_WBEA_MASK (0x38000U) +#define EIM_CS2WCR1_WBEA_SHIFT (15U) +#define EIM_CS2WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WBEA_SHIFT)) & EIM_CS2WCR1_WBEA_MASK) +#define EIM_CS2WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS2WCR1_WADVN_SHIFT (18U) +#define EIM_CS2WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WADVN_SHIFT)) & EIM_CS2WCR1_WADVN_MASK) +#define EIM_CS2WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS2WCR1_WADVA_SHIFT (21U) +#define EIM_CS2WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WADVA_SHIFT)) & EIM_CS2WCR1_WADVA_MASK) +#define EIM_CS2WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS2WCR1_WWSC_SHIFT (24U) +#define EIM_CS2WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WWSC_SHIFT)) & EIM_CS2WCR1_WWSC_MASK) +#define EIM_CS2WCR1_WBED_MASK (0x40000000U) +#define EIM_CS2WCR1_WBED_SHIFT (30U) +#define EIM_CS2WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WBED_SHIFT)) & EIM_CS2WCR1_WBED_MASK) +#define EIM_CS2WCR1_WAL_MASK (0x80000000U) +#define EIM_CS2WCR1_WAL_SHIFT (31U) +#define EIM_CS2WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WAL_SHIFT)) & EIM_CS2WCR1_WAL_MASK) + +/*! @name CS2WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS2WCR2_WBCDD_MASK (0x1U) +#define EIM_CS2WCR2_WBCDD_SHIFT (0U) +#define EIM_CS2WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR2_WBCDD_SHIFT)) & EIM_CS2WCR2_WBCDD_MASK) + +/*! @name CS3GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS3GCR1_CSEN_MASK (0x1U) +#define EIM_CS3GCR1_CSEN_SHIFT (0U) +#define EIM_CS3GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_CSEN_SHIFT)) & EIM_CS3GCR1_CSEN_MASK) +#define EIM_CS3GCR1_SWR_MASK (0x2U) +#define EIM_CS3GCR1_SWR_SHIFT (1U) +#define EIM_CS3GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_SWR_SHIFT)) & EIM_CS3GCR1_SWR_MASK) +#define EIM_CS3GCR1_SRD_MASK (0x4U) +#define EIM_CS3GCR1_SRD_SHIFT (2U) +#define EIM_CS3GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_SRD_SHIFT)) & EIM_CS3GCR1_SRD_MASK) +#define EIM_CS3GCR1_MUM_MASK (0x8U) +#define EIM_CS3GCR1_MUM_SHIFT (3U) +#define EIM_CS3GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_MUM_SHIFT)) & EIM_CS3GCR1_MUM_MASK) +#define EIM_CS3GCR1_WFL_MASK (0x10U) +#define EIM_CS3GCR1_WFL_SHIFT (4U) +#define EIM_CS3GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_WFL_SHIFT)) & EIM_CS3GCR1_WFL_MASK) +#define EIM_CS3GCR1_RFL_MASK (0x20U) +#define EIM_CS3GCR1_RFL_SHIFT (5U) +#define EIM_CS3GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_RFL_SHIFT)) & EIM_CS3GCR1_RFL_MASK) +#define EIM_CS3GCR1_CRE_MASK (0x40U) +#define EIM_CS3GCR1_CRE_SHIFT (6U) +#define EIM_CS3GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_CRE_SHIFT)) & EIM_CS3GCR1_CRE_MASK) +#define EIM_CS3GCR1_CREP_MASK (0x80U) +#define EIM_CS3GCR1_CREP_SHIFT (7U) +#define EIM_CS3GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_CREP_SHIFT)) & EIM_CS3GCR1_CREP_MASK) +#define EIM_CS3GCR1_BL_MASK (0x700U) +#define EIM_CS3GCR1_BL_SHIFT (8U) +#define EIM_CS3GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_BL_SHIFT)) & EIM_CS3GCR1_BL_MASK) +#define EIM_CS3GCR1_WC_MASK (0x800U) +#define EIM_CS3GCR1_WC_SHIFT (11U) +#define EIM_CS3GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_WC_SHIFT)) & EIM_CS3GCR1_WC_MASK) +#define EIM_CS3GCR1_BCD_MASK (0x3000U) +#define EIM_CS3GCR1_BCD_SHIFT (12U) +#define EIM_CS3GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_BCD_SHIFT)) & EIM_CS3GCR1_BCD_MASK) +#define EIM_CS3GCR1_BCS_MASK (0xC000U) +#define EIM_CS3GCR1_BCS_SHIFT (14U) +#define EIM_CS3GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_BCS_SHIFT)) & EIM_CS3GCR1_BCS_MASK) +#define EIM_CS3GCR1_DSZ_MASK (0x70000U) +#define EIM_CS3GCR1_DSZ_SHIFT (16U) +#define EIM_CS3GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_DSZ_SHIFT)) & EIM_CS3GCR1_DSZ_MASK) +#define EIM_CS3GCR1_SP_MASK (0x80000U) +#define EIM_CS3GCR1_SP_SHIFT (19U) +#define EIM_CS3GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_SP_SHIFT)) & EIM_CS3GCR1_SP_MASK) +#define EIM_CS3GCR1_CSREC_MASK (0x700000U) +#define EIM_CS3GCR1_CSREC_SHIFT (20U) +#define EIM_CS3GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_CSREC_SHIFT)) & EIM_CS3GCR1_CSREC_MASK) +#define EIM_CS3GCR1_AUS_MASK (0x800000U) +#define EIM_CS3GCR1_AUS_SHIFT (23U) +#define EIM_CS3GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_AUS_SHIFT)) & EIM_CS3GCR1_AUS_MASK) +#define EIM_CS3GCR1_GBC_MASK (0x7000000U) +#define EIM_CS3GCR1_GBC_SHIFT (24U) +#define EIM_CS3GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_GBC_SHIFT)) & EIM_CS3GCR1_GBC_MASK) +#define EIM_CS3GCR1_WP_MASK (0x8000000U) +#define EIM_CS3GCR1_WP_SHIFT (27U) +#define EIM_CS3GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_WP_SHIFT)) & EIM_CS3GCR1_WP_MASK) +#define EIM_CS3GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS3GCR1_PSZ_SHIFT (28U) +#define EIM_CS3GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_PSZ_SHIFT)) & EIM_CS3GCR1_PSZ_MASK) + +/*! @name CS3GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS3GCR2_ADH_MASK (0x3U) +#define EIM_CS3GCR2_ADH_SHIFT (0U) +#define EIM_CS3GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_ADH_SHIFT)) & EIM_CS3GCR2_ADH_MASK) +#define EIM_CS3GCR2_DAPS_MASK (0xF0U) +#define EIM_CS3GCR2_DAPS_SHIFT (4U) +#define EIM_CS3GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_DAPS_SHIFT)) & EIM_CS3GCR2_DAPS_MASK) +#define EIM_CS3GCR2_DAE_MASK (0x100U) +#define EIM_CS3GCR2_DAE_SHIFT (8U) +#define EIM_CS3GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_DAE_SHIFT)) & EIM_CS3GCR2_DAE_MASK) +#define EIM_CS3GCR2_DAP_MASK (0x200U) +#define EIM_CS3GCR2_DAP_SHIFT (9U) +#define EIM_CS3GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_DAP_SHIFT)) & EIM_CS3GCR2_DAP_MASK) +#define EIM_CS3GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS3GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS3GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS3GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS3RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS3RCR1_RCSN_MASK (0x7U) +#define EIM_CS3RCR1_RCSN_SHIFT (0U) +#define EIM_CS3RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RCSN_SHIFT)) & EIM_CS3RCR1_RCSN_MASK) +#define EIM_CS3RCR1_RCSA_MASK (0x70U) +#define EIM_CS3RCR1_RCSA_SHIFT (4U) +#define EIM_CS3RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RCSA_SHIFT)) & EIM_CS3RCR1_RCSA_MASK) +#define EIM_CS3RCR1_OEN_MASK (0x700U) +#define EIM_CS3RCR1_OEN_SHIFT (8U) +#define EIM_CS3RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_OEN_SHIFT)) & EIM_CS3RCR1_OEN_MASK) +#define EIM_CS3RCR1_OEA_MASK (0x7000U) +#define EIM_CS3RCR1_OEA_SHIFT (12U) +#define EIM_CS3RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_OEA_SHIFT)) & EIM_CS3RCR1_OEA_MASK) +#define EIM_CS3RCR1_RADVN_MASK (0x70000U) +#define EIM_CS3RCR1_RADVN_SHIFT (16U) +#define EIM_CS3RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RADVN_SHIFT)) & EIM_CS3RCR1_RADVN_MASK) +#define EIM_CS3RCR1_RAL_MASK (0x80000U) +#define EIM_CS3RCR1_RAL_SHIFT (19U) +#define EIM_CS3RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RAL_SHIFT)) & EIM_CS3RCR1_RAL_MASK) +#define EIM_CS3RCR1_RADVA_MASK (0x700000U) +#define EIM_CS3RCR1_RADVA_SHIFT (20U) +#define EIM_CS3RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RADVA_SHIFT)) & EIM_CS3RCR1_RADVA_MASK) +#define EIM_CS3RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS3RCR1_RWSC_SHIFT (24U) +#define EIM_CS3RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RWSC_SHIFT)) & EIM_CS3RCR1_RWSC_MASK) + +/*! @name CS3RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS3RCR2_RBEN_MASK (0x7U) +#define EIM_CS3RCR2_RBEN_SHIFT (0U) +#define EIM_CS3RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_RBEN_SHIFT)) & EIM_CS3RCR2_RBEN_MASK) +#define EIM_CS3RCR2_RBE_MASK (0x8U) +#define EIM_CS3RCR2_RBE_SHIFT (3U) +#define EIM_CS3RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_RBE_SHIFT)) & EIM_CS3RCR2_RBE_MASK) +#define EIM_CS3RCR2_RBEA_MASK (0x70U) +#define EIM_CS3RCR2_RBEA_SHIFT (4U) +#define EIM_CS3RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_RBEA_SHIFT)) & EIM_CS3RCR2_RBEA_MASK) +#define EIM_CS3RCR2_RL_MASK (0x300U) +#define EIM_CS3RCR2_RL_SHIFT (8U) +#define EIM_CS3RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_RL_SHIFT)) & EIM_CS3RCR2_RL_MASK) +#define EIM_CS3RCR2_PAT_MASK (0x7000U) +#define EIM_CS3RCR2_PAT_SHIFT (12U) +#define EIM_CS3RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_PAT_SHIFT)) & EIM_CS3RCR2_PAT_MASK) +#define EIM_CS3RCR2_APR_MASK (0x8000U) +#define EIM_CS3RCR2_APR_SHIFT (15U) +#define EIM_CS3RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_APR_SHIFT)) & EIM_CS3RCR2_APR_MASK) + +/*! @name CS3WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS3WCR1_WCSN_MASK (0x7U) +#define EIM_CS3WCR1_WCSN_SHIFT (0U) +#define EIM_CS3WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WCSN_SHIFT)) & EIM_CS3WCR1_WCSN_MASK) +#define EIM_CS3WCR1_WCSA_MASK (0x38U) +#define EIM_CS3WCR1_WCSA_SHIFT (3U) +#define EIM_CS3WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WCSA_SHIFT)) & EIM_CS3WCR1_WCSA_MASK) +#define EIM_CS3WCR1_WEN_MASK (0x1C0U) +#define EIM_CS3WCR1_WEN_SHIFT (6U) +#define EIM_CS3WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WEN_SHIFT)) & EIM_CS3WCR1_WEN_MASK) +#define EIM_CS3WCR1_WEA_MASK (0xE00U) +#define EIM_CS3WCR1_WEA_SHIFT (9U) +#define EIM_CS3WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WEA_SHIFT)) & EIM_CS3WCR1_WEA_MASK) +#define EIM_CS3WCR1_WBEN_MASK (0x7000U) +#define EIM_CS3WCR1_WBEN_SHIFT (12U) +#define EIM_CS3WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WBEN_SHIFT)) & EIM_CS3WCR1_WBEN_MASK) +#define EIM_CS3WCR1_WBEA_MASK (0x38000U) +#define EIM_CS3WCR1_WBEA_SHIFT (15U) +#define EIM_CS3WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WBEA_SHIFT)) & EIM_CS3WCR1_WBEA_MASK) +#define EIM_CS3WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS3WCR1_WADVN_SHIFT (18U) +#define EIM_CS3WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WADVN_SHIFT)) & EIM_CS3WCR1_WADVN_MASK) +#define EIM_CS3WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS3WCR1_WADVA_SHIFT (21U) +#define EIM_CS3WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WADVA_SHIFT)) & EIM_CS3WCR1_WADVA_MASK) +#define EIM_CS3WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS3WCR1_WWSC_SHIFT (24U) +#define EIM_CS3WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WWSC_SHIFT)) & EIM_CS3WCR1_WWSC_MASK) +#define EIM_CS3WCR1_WBED_MASK (0x40000000U) +#define EIM_CS3WCR1_WBED_SHIFT (30U) +#define EIM_CS3WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WBED_SHIFT)) & EIM_CS3WCR1_WBED_MASK) +#define EIM_CS3WCR1_WAL_MASK (0x80000000U) +#define EIM_CS3WCR1_WAL_SHIFT (31U) +#define EIM_CS3WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WAL_SHIFT)) & EIM_CS3WCR1_WAL_MASK) + +/*! @name CS3WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS3WCR2_WBCDD_MASK (0x1U) +#define EIM_CS3WCR2_WBCDD_SHIFT (0U) +#define EIM_CS3WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR2_WBCDD_SHIFT)) & EIM_CS3WCR2_WBCDD_MASK) + +/*! @name CS4GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS4GCR1_CSEN_MASK (0x1U) +#define EIM_CS4GCR1_CSEN_SHIFT (0U) +#define EIM_CS4GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_CSEN_SHIFT)) & EIM_CS4GCR1_CSEN_MASK) +#define EIM_CS4GCR1_SWR_MASK (0x2U) +#define EIM_CS4GCR1_SWR_SHIFT (1U) +#define EIM_CS4GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_SWR_SHIFT)) & EIM_CS4GCR1_SWR_MASK) +#define EIM_CS4GCR1_SRD_MASK (0x4U) +#define EIM_CS4GCR1_SRD_SHIFT (2U) +#define EIM_CS4GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_SRD_SHIFT)) & EIM_CS4GCR1_SRD_MASK) +#define EIM_CS4GCR1_MUM_MASK (0x8U) +#define EIM_CS4GCR1_MUM_SHIFT (3U) +#define EIM_CS4GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_MUM_SHIFT)) & EIM_CS4GCR1_MUM_MASK) +#define EIM_CS4GCR1_WFL_MASK (0x10U) +#define EIM_CS4GCR1_WFL_SHIFT (4U) +#define EIM_CS4GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_WFL_SHIFT)) & EIM_CS4GCR1_WFL_MASK) +#define EIM_CS4GCR1_RFL_MASK (0x20U) +#define EIM_CS4GCR1_RFL_SHIFT (5U) +#define EIM_CS4GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_RFL_SHIFT)) & EIM_CS4GCR1_RFL_MASK) +#define EIM_CS4GCR1_CRE_MASK (0x40U) +#define EIM_CS4GCR1_CRE_SHIFT (6U) +#define EIM_CS4GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_CRE_SHIFT)) & EIM_CS4GCR1_CRE_MASK) +#define EIM_CS4GCR1_CREP_MASK (0x80U) +#define EIM_CS4GCR1_CREP_SHIFT (7U) +#define EIM_CS4GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_CREP_SHIFT)) & EIM_CS4GCR1_CREP_MASK) +#define EIM_CS4GCR1_BL_MASK (0x700U) +#define EIM_CS4GCR1_BL_SHIFT (8U) +#define EIM_CS4GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_BL_SHIFT)) & EIM_CS4GCR1_BL_MASK) +#define EIM_CS4GCR1_WC_MASK (0x800U) +#define EIM_CS4GCR1_WC_SHIFT (11U) +#define EIM_CS4GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_WC_SHIFT)) & EIM_CS4GCR1_WC_MASK) +#define EIM_CS4GCR1_BCD_MASK (0x3000U) +#define EIM_CS4GCR1_BCD_SHIFT (12U) +#define EIM_CS4GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_BCD_SHIFT)) & EIM_CS4GCR1_BCD_MASK) +#define EIM_CS4GCR1_BCS_MASK (0xC000U) +#define EIM_CS4GCR1_BCS_SHIFT (14U) +#define EIM_CS4GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_BCS_SHIFT)) & EIM_CS4GCR1_BCS_MASK) +#define EIM_CS4GCR1_DSZ_MASK (0x70000U) +#define EIM_CS4GCR1_DSZ_SHIFT (16U) +#define EIM_CS4GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_DSZ_SHIFT)) & EIM_CS4GCR1_DSZ_MASK) +#define EIM_CS4GCR1_SP_MASK (0x80000U) +#define EIM_CS4GCR1_SP_SHIFT (19U) +#define EIM_CS4GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_SP_SHIFT)) & EIM_CS4GCR1_SP_MASK) +#define EIM_CS4GCR1_CSREC_MASK (0x700000U) +#define EIM_CS4GCR1_CSREC_SHIFT (20U) +#define EIM_CS4GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_CSREC_SHIFT)) & EIM_CS4GCR1_CSREC_MASK) +#define EIM_CS4GCR1_AUS_MASK (0x800000U) +#define EIM_CS4GCR1_AUS_SHIFT (23U) +#define EIM_CS4GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_AUS_SHIFT)) & EIM_CS4GCR1_AUS_MASK) +#define EIM_CS4GCR1_GBC_MASK (0x7000000U) +#define EIM_CS4GCR1_GBC_SHIFT (24U) +#define EIM_CS4GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_GBC_SHIFT)) & EIM_CS4GCR1_GBC_MASK) +#define EIM_CS4GCR1_WP_MASK (0x8000000U) +#define EIM_CS4GCR1_WP_SHIFT (27U) +#define EIM_CS4GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_WP_SHIFT)) & EIM_CS4GCR1_WP_MASK) +#define EIM_CS4GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS4GCR1_PSZ_SHIFT (28U) +#define EIM_CS4GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_PSZ_SHIFT)) & EIM_CS4GCR1_PSZ_MASK) + +/*! @name CS4GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS4GCR2_ADH_MASK (0x3U) +#define EIM_CS4GCR2_ADH_SHIFT (0U) +#define EIM_CS4GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_ADH_SHIFT)) & EIM_CS4GCR2_ADH_MASK) +#define EIM_CS4GCR2_DAPS_MASK (0xF0U) +#define EIM_CS4GCR2_DAPS_SHIFT (4U) +#define EIM_CS4GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_DAPS_SHIFT)) & EIM_CS4GCR2_DAPS_MASK) +#define EIM_CS4GCR2_DAE_MASK (0x100U) +#define EIM_CS4GCR2_DAE_SHIFT (8U) +#define EIM_CS4GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_DAE_SHIFT)) & EIM_CS4GCR2_DAE_MASK) +#define EIM_CS4GCR2_DAP_MASK (0x200U) +#define EIM_CS4GCR2_DAP_SHIFT (9U) +#define EIM_CS4GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_DAP_SHIFT)) & EIM_CS4GCR2_DAP_MASK) +#define EIM_CS4GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS4GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS4GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS4GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS4RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS4RCR1_RCSN_MASK (0x7U) +#define EIM_CS4RCR1_RCSN_SHIFT (0U) +#define EIM_CS4RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RCSN_SHIFT)) & EIM_CS4RCR1_RCSN_MASK) +#define EIM_CS4RCR1_RCSA_MASK (0x70U) +#define EIM_CS4RCR1_RCSA_SHIFT (4U) +#define EIM_CS4RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RCSA_SHIFT)) & EIM_CS4RCR1_RCSA_MASK) +#define EIM_CS4RCR1_OEN_MASK (0x700U) +#define EIM_CS4RCR1_OEN_SHIFT (8U) +#define EIM_CS4RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_OEN_SHIFT)) & EIM_CS4RCR1_OEN_MASK) +#define EIM_CS4RCR1_OEA_MASK (0x7000U) +#define EIM_CS4RCR1_OEA_SHIFT (12U) +#define EIM_CS4RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_OEA_SHIFT)) & EIM_CS4RCR1_OEA_MASK) +#define EIM_CS4RCR1_RADVN_MASK (0x70000U) +#define EIM_CS4RCR1_RADVN_SHIFT (16U) +#define EIM_CS4RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RADVN_SHIFT)) & EIM_CS4RCR1_RADVN_MASK) +#define EIM_CS4RCR1_RAL_MASK (0x80000U) +#define EIM_CS4RCR1_RAL_SHIFT (19U) +#define EIM_CS4RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RAL_SHIFT)) & EIM_CS4RCR1_RAL_MASK) +#define EIM_CS4RCR1_RADVA_MASK (0x700000U) +#define EIM_CS4RCR1_RADVA_SHIFT (20U) +#define EIM_CS4RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RADVA_SHIFT)) & EIM_CS4RCR1_RADVA_MASK) +#define EIM_CS4RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS4RCR1_RWSC_SHIFT (24U) +#define EIM_CS4RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RWSC_SHIFT)) & EIM_CS4RCR1_RWSC_MASK) + +/*! @name CS4RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS4RCR2_RBEN_MASK (0x7U) +#define EIM_CS4RCR2_RBEN_SHIFT (0U) +#define EIM_CS4RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_RBEN_SHIFT)) & EIM_CS4RCR2_RBEN_MASK) +#define EIM_CS4RCR2_RBE_MASK (0x8U) +#define EIM_CS4RCR2_RBE_SHIFT (3U) +#define EIM_CS4RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_RBE_SHIFT)) & EIM_CS4RCR2_RBE_MASK) +#define EIM_CS4RCR2_RBEA_MASK (0x70U) +#define EIM_CS4RCR2_RBEA_SHIFT (4U) +#define EIM_CS4RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_RBEA_SHIFT)) & EIM_CS4RCR2_RBEA_MASK) +#define EIM_CS4RCR2_RL_MASK (0x300U) +#define EIM_CS4RCR2_RL_SHIFT (8U) +#define EIM_CS4RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_RL_SHIFT)) & EIM_CS4RCR2_RL_MASK) +#define EIM_CS4RCR2_PAT_MASK (0x7000U) +#define EIM_CS4RCR2_PAT_SHIFT (12U) +#define EIM_CS4RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_PAT_SHIFT)) & EIM_CS4RCR2_PAT_MASK) +#define EIM_CS4RCR2_APR_MASK (0x8000U) +#define EIM_CS4RCR2_APR_SHIFT (15U) +#define EIM_CS4RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_APR_SHIFT)) & EIM_CS4RCR2_APR_MASK) + +/*! @name CS4WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS4WCR1_WCSN_MASK (0x7U) +#define EIM_CS4WCR1_WCSN_SHIFT (0U) +#define EIM_CS4WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WCSN_SHIFT)) & EIM_CS4WCR1_WCSN_MASK) +#define EIM_CS4WCR1_WCSA_MASK (0x38U) +#define EIM_CS4WCR1_WCSA_SHIFT (3U) +#define EIM_CS4WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WCSA_SHIFT)) & EIM_CS4WCR1_WCSA_MASK) +#define EIM_CS4WCR1_WEN_MASK (0x1C0U) +#define EIM_CS4WCR1_WEN_SHIFT (6U) +#define EIM_CS4WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WEN_SHIFT)) & EIM_CS4WCR1_WEN_MASK) +#define EIM_CS4WCR1_WEA_MASK (0xE00U) +#define EIM_CS4WCR1_WEA_SHIFT (9U) +#define EIM_CS4WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WEA_SHIFT)) & EIM_CS4WCR1_WEA_MASK) +#define EIM_CS4WCR1_WBEN_MASK (0x7000U) +#define EIM_CS4WCR1_WBEN_SHIFT (12U) +#define EIM_CS4WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WBEN_SHIFT)) & EIM_CS4WCR1_WBEN_MASK) +#define EIM_CS4WCR1_WBEA_MASK (0x38000U) +#define EIM_CS4WCR1_WBEA_SHIFT (15U) +#define EIM_CS4WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WBEA_SHIFT)) & EIM_CS4WCR1_WBEA_MASK) +#define EIM_CS4WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS4WCR1_WADVN_SHIFT (18U) +#define EIM_CS4WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WADVN_SHIFT)) & EIM_CS4WCR1_WADVN_MASK) +#define EIM_CS4WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS4WCR1_WADVA_SHIFT (21U) +#define EIM_CS4WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WADVA_SHIFT)) & EIM_CS4WCR1_WADVA_MASK) +#define EIM_CS4WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS4WCR1_WWSC_SHIFT (24U) +#define EIM_CS4WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WWSC_SHIFT)) & EIM_CS4WCR1_WWSC_MASK) +#define EIM_CS4WCR1_WBED_MASK (0x40000000U) +#define EIM_CS4WCR1_WBED_SHIFT (30U) +#define EIM_CS4WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WBED_SHIFT)) & EIM_CS4WCR1_WBED_MASK) +#define EIM_CS4WCR1_WAL_MASK (0x80000000U) +#define EIM_CS4WCR1_WAL_SHIFT (31U) +#define EIM_CS4WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WAL_SHIFT)) & EIM_CS4WCR1_WAL_MASK) + +/*! @name CS4WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS4WCR2_WBCDD_MASK (0x1U) +#define EIM_CS4WCR2_WBCDD_SHIFT (0U) +#define EIM_CS4WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR2_WBCDD_SHIFT)) & EIM_CS4WCR2_WBCDD_MASK) + +/*! @name CS5GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS5GCR1_CSEN_MASK (0x1U) +#define EIM_CS5GCR1_CSEN_SHIFT (0U) +#define EIM_CS5GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_CSEN_SHIFT)) & EIM_CS5GCR1_CSEN_MASK) +#define EIM_CS5GCR1_SWR_MASK (0x2U) +#define EIM_CS5GCR1_SWR_SHIFT (1U) +#define EIM_CS5GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_SWR_SHIFT)) & EIM_CS5GCR1_SWR_MASK) +#define EIM_CS5GCR1_SRD_MASK (0x4U) +#define EIM_CS5GCR1_SRD_SHIFT (2U) +#define EIM_CS5GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_SRD_SHIFT)) & EIM_CS5GCR1_SRD_MASK) +#define EIM_CS5GCR1_MUM_MASK (0x8U) +#define EIM_CS5GCR1_MUM_SHIFT (3U) +#define EIM_CS5GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_MUM_SHIFT)) & EIM_CS5GCR1_MUM_MASK) +#define EIM_CS5GCR1_WFL_MASK (0x10U) +#define EIM_CS5GCR1_WFL_SHIFT (4U) +#define EIM_CS5GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_WFL_SHIFT)) & EIM_CS5GCR1_WFL_MASK) +#define EIM_CS5GCR1_RFL_MASK (0x20U) +#define EIM_CS5GCR1_RFL_SHIFT (5U) +#define EIM_CS5GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_RFL_SHIFT)) & EIM_CS5GCR1_RFL_MASK) +#define EIM_CS5GCR1_CRE_MASK (0x40U) +#define EIM_CS5GCR1_CRE_SHIFT (6U) +#define EIM_CS5GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_CRE_SHIFT)) & EIM_CS5GCR1_CRE_MASK) +#define EIM_CS5GCR1_CREP_MASK (0x80U) +#define EIM_CS5GCR1_CREP_SHIFT (7U) +#define EIM_CS5GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_CREP_SHIFT)) & EIM_CS5GCR1_CREP_MASK) +#define EIM_CS5GCR1_BL_MASK (0x700U) +#define EIM_CS5GCR1_BL_SHIFT (8U) +#define EIM_CS5GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_BL_SHIFT)) & EIM_CS5GCR1_BL_MASK) +#define EIM_CS5GCR1_WC_MASK (0x800U) +#define EIM_CS5GCR1_WC_SHIFT (11U) +#define EIM_CS5GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_WC_SHIFT)) & EIM_CS5GCR1_WC_MASK) +#define EIM_CS5GCR1_BCD_MASK (0x3000U) +#define EIM_CS5GCR1_BCD_SHIFT (12U) +#define EIM_CS5GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_BCD_SHIFT)) & EIM_CS5GCR1_BCD_MASK) +#define EIM_CS5GCR1_BCS_MASK (0xC000U) +#define EIM_CS5GCR1_BCS_SHIFT (14U) +#define EIM_CS5GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_BCS_SHIFT)) & EIM_CS5GCR1_BCS_MASK) +#define EIM_CS5GCR1_DSZ_MASK (0x70000U) +#define EIM_CS5GCR1_DSZ_SHIFT (16U) +#define EIM_CS5GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_DSZ_SHIFT)) & EIM_CS5GCR1_DSZ_MASK) +#define EIM_CS5GCR1_SP_MASK (0x80000U) +#define EIM_CS5GCR1_SP_SHIFT (19U) +#define EIM_CS5GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_SP_SHIFT)) & EIM_CS5GCR1_SP_MASK) +#define EIM_CS5GCR1_CSREC_MASK (0x700000U) +#define EIM_CS5GCR1_CSREC_SHIFT (20U) +#define EIM_CS5GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_CSREC_SHIFT)) & EIM_CS5GCR1_CSREC_MASK) +#define EIM_CS5GCR1_AUS_MASK (0x800000U) +#define EIM_CS5GCR1_AUS_SHIFT (23U) +#define EIM_CS5GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_AUS_SHIFT)) & EIM_CS5GCR1_AUS_MASK) +#define EIM_CS5GCR1_GBC_MASK (0x7000000U) +#define EIM_CS5GCR1_GBC_SHIFT (24U) +#define EIM_CS5GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_GBC_SHIFT)) & EIM_CS5GCR1_GBC_MASK) +#define EIM_CS5GCR1_WP_MASK (0x8000000U) +#define EIM_CS5GCR1_WP_SHIFT (27U) +#define EIM_CS5GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_WP_SHIFT)) & EIM_CS5GCR1_WP_MASK) +#define EIM_CS5GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS5GCR1_PSZ_SHIFT (28U) +#define EIM_CS5GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_PSZ_SHIFT)) & EIM_CS5GCR1_PSZ_MASK) + +/*! @name CS5GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS5GCR2_ADH_MASK (0x3U) +#define EIM_CS5GCR2_ADH_SHIFT (0U) +#define EIM_CS5GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_ADH_SHIFT)) & EIM_CS5GCR2_ADH_MASK) +#define EIM_CS5GCR2_DAPS_MASK (0xF0U) +#define EIM_CS5GCR2_DAPS_SHIFT (4U) +#define EIM_CS5GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_DAPS_SHIFT)) & EIM_CS5GCR2_DAPS_MASK) +#define EIM_CS5GCR2_DAE_MASK (0x100U) +#define EIM_CS5GCR2_DAE_SHIFT (8U) +#define EIM_CS5GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_DAE_SHIFT)) & EIM_CS5GCR2_DAE_MASK) +#define EIM_CS5GCR2_DAP_MASK (0x200U) +#define EIM_CS5GCR2_DAP_SHIFT (9U) +#define EIM_CS5GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_DAP_SHIFT)) & EIM_CS5GCR2_DAP_MASK) +#define EIM_CS5GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS5GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS5GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS5GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS5RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS5RCR1_RCSN_MASK (0x7U) +#define EIM_CS5RCR1_RCSN_SHIFT (0U) +#define EIM_CS5RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RCSN_SHIFT)) & EIM_CS5RCR1_RCSN_MASK) +#define EIM_CS5RCR1_RCSA_MASK (0x70U) +#define EIM_CS5RCR1_RCSA_SHIFT (4U) +#define EIM_CS5RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RCSA_SHIFT)) & EIM_CS5RCR1_RCSA_MASK) +#define EIM_CS5RCR1_OEN_MASK (0x700U) +#define EIM_CS5RCR1_OEN_SHIFT (8U) +#define EIM_CS5RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_OEN_SHIFT)) & EIM_CS5RCR1_OEN_MASK) +#define EIM_CS5RCR1_OEA_MASK (0x7000U) +#define EIM_CS5RCR1_OEA_SHIFT (12U) +#define EIM_CS5RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_OEA_SHIFT)) & EIM_CS5RCR1_OEA_MASK) +#define EIM_CS5RCR1_RADVN_MASK (0x70000U) +#define EIM_CS5RCR1_RADVN_SHIFT (16U) +#define EIM_CS5RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RADVN_SHIFT)) & EIM_CS5RCR1_RADVN_MASK) +#define EIM_CS5RCR1_RAL_MASK (0x80000U) +#define EIM_CS5RCR1_RAL_SHIFT (19U) +#define EIM_CS5RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RAL_SHIFT)) & EIM_CS5RCR1_RAL_MASK) +#define EIM_CS5RCR1_RADVA_MASK (0x700000U) +#define EIM_CS5RCR1_RADVA_SHIFT (20U) +#define EIM_CS5RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RADVA_SHIFT)) & EIM_CS5RCR1_RADVA_MASK) +#define EIM_CS5RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS5RCR1_RWSC_SHIFT (24U) +#define EIM_CS5RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RWSC_SHIFT)) & EIM_CS5RCR1_RWSC_MASK) + +/*! @name CS5RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS5RCR2_RBEN_MASK (0x7U) +#define EIM_CS5RCR2_RBEN_SHIFT (0U) +#define EIM_CS5RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_RBEN_SHIFT)) & EIM_CS5RCR2_RBEN_MASK) +#define EIM_CS5RCR2_RBE_MASK (0x8U) +#define EIM_CS5RCR2_RBE_SHIFT (3U) +#define EIM_CS5RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_RBE_SHIFT)) & EIM_CS5RCR2_RBE_MASK) +#define EIM_CS5RCR2_RBEA_MASK (0x70U) +#define EIM_CS5RCR2_RBEA_SHIFT (4U) +#define EIM_CS5RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_RBEA_SHIFT)) & EIM_CS5RCR2_RBEA_MASK) +#define EIM_CS5RCR2_RL_MASK (0x300U) +#define EIM_CS5RCR2_RL_SHIFT (8U) +#define EIM_CS5RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_RL_SHIFT)) & EIM_CS5RCR2_RL_MASK) +#define EIM_CS5RCR2_PAT_MASK (0x7000U) +#define EIM_CS5RCR2_PAT_SHIFT (12U) +#define EIM_CS5RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_PAT_SHIFT)) & EIM_CS5RCR2_PAT_MASK) +#define EIM_CS5RCR2_APR_MASK (0x8000U) +#define EIM_CS5RCR2_APR_SHIFT (15U) +#define EIM_CS5RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_APR_SHIFT)) & EIM_CS5RCR2_APR_MASK) + +/*! @name CS5WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS5WCR1_WCSN_MASK (0x7U) +#define EIM_CS5WCR1_WCSN_SHIFT (0U) +#define EIM_CS5WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WCSN_SHIFT)) & EIM_CS5WCR1_WCSN_MASK) +#define EIM_CS5WCR1_WCSA_MASK (0x38U) +#define EIM_CS5WCR1_WCSA_SHIFT (3U) +#define EIM_CS5WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WCSA_SHIFT)) & EIM_CS5WCR1_WCSA_MASK) +#define EIM_CS5WCR1_WEN_MASK (0x1C0U) +#define EIM_CS5WCR1_WEN_SHIFT (6U) +#define EIM_CS5WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WEN_SHIFT)) & EIM_CS5WCR1_WEN_MASK) +#define EIM_CS5WCR1_WEA_MASK (0xE00U) +#define EIM_CS5WCR1_WEA_SHIFT (9U) +#define EIM_CS5WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WEA_SHIFT)) & EIM_CS5WCR1_WEA_MASK) +#define EIM_CS5WCR1_WBEN_MASK (0x7000U) +#define EIM_CS5WCR1_WBEN_SHIFT (12U) +#define EIM_CS5WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WBEN_SHIFT)) & EIM_CS5WCR1_WBEN_MASK) +#define EIM_CS5WCR1_WBEA_MASK (0x38000U) +#define EIM_CS5WCR1_WBEA_SHIFT (15U) +#define EIM_CS5WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WBEA_SHIFT)) & EIM_CS5WCR1_WBEA_MASK) +#define EIM_CS5WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS5WCR1_WADVN_SHIFT (18U) +#define EIM_CS5WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WADVN_SHIFT)) & EIM_CS5WCR1_WADVN_MASK) +#define EIM_CS5WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS5WCR1_WADVA_SHIFT (21U) +#define EIM_CS5WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WADVA_SHIFT)) & EIM_CS5WCR1_WADVA_MASK) +#define EIM_CS5WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS5WCR1_WWSC_SHIFT (24U) +#define EIM_CS5WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WWSC_SHIFT)) & EIM_CS5WCR1_WWSC_MASK) +#define EIM_CS5WCR1_WBED_MASK (0x40000000U) +#define EIM_CS5WCR1_WBED_SHIFT (30U) +#define EIM_CS5WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WBED_SHIFT)) & EIM_CS5WCR1_WBED_MASK) +#define EIM_CS5WCR1_WAL_MASK (0x80000000U) +#define EIM_CS5WCR1_WAL_SHIFT (31U) +#define EIM_CS5WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WAL_SHIFT)) & EIM_CS5WCR1_WAL_MASK) + +/*! @name CS5WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS5WCR2_WBCDD_MASK (0x1U) +#define EIM_CS5WCR2_WBCDD_SHIFT (0U) +#define EIM_CS5WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR2_WBCDD_SHIFT)) & EIM_CS5WCR2_WBCDD_MASK) + +/*! @name WCR - EIM Configuration Register */ +#define EIM_WCR_BCM_MASK (0x1U) +#define EIM_WCR_BCM_SHIFT (0U) +#define EIM_WCR_BCM(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_BCM_SHIFT)) & EIM_WCR_BCM_MASK) +#define EIM_WCR_GBCD_MASK (0x6U) +#define EIM_WCR_GBCD_SHIFT (1U) +#define EIM_WCR_GBCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_GBCD_SHIFT)) & EIM_WCR_GBCD_MASK) +#define EIM_WCR_CONT_BCLK_SEL_MASK (0x8U) +#define EIM_WCR_CONT_BCLK_SEL_SHIFT (3U) +#define EIM_WCR_CONT_BCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_CONT_BCLK_SEL_SHIFT)) & EIM_WCR_CONT_BCLK_SEL_MASK) +#define EIM_WCR_INTEN_MASK (0x10U) +#define EIM_WCR_INTEN_SHIFT (4U) +#define EIM_WCR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_INTEN_SHIFT)) & EIM_WCR_INTEN_MASK) +#define EIM_WCR_INTPOL_MASK (0x20U) +#define EIM_WCR_INTPOL_SHIFT (5U) +#define EIM_WCR_INTPOL(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_INTPOL_SHIFT)) & EIM_WCR_INTPOL_MASK) +#define EIM_WCR_WDOG_EN_MASK (0x100U) +#define EIM_WCR_WDOG_EN_SHIFT (8U) +#define EIM_WCR_WDOG_EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_WDOG_EN_SHIFT)) & EIM_WCR_WDOG_EN_MASK) +#define EIM_WCR_WDOG_LIMIT_MASK (0x600U) +#define EIM_WCR_WDOG_LIMIT_SHIFT (9U) +#define EIM_WCR_WDOG_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_WDOG_LIMIT_SHIFT)) & EIM_WCR_WDOG_LIMIT_MASK) +#define EIM_WCR_FRUN_ACLK_EN_MASK (0x800U) +#define EIM_WCR_FRUN_ACLK_EN_SHIFT (11U) +#define EIM_WCR_FRUN_ACLK_EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_FRUN_ACLK_EN_SHIFT)) & EIM_WCR_FRUN_ACLK_EN_MASK) + + +/*! + * @} + */ /* end of group EIM_Register_Masks */ + + +/* EIM - Peripheral instance base addresses */ +/** Peripheral EIM base address */ +#define EIM_BASE (0x21B8000u) +/** Peripheral EIM base pointer */ +#define EIM ((EIM_Type *)EIM_BASE) +/** Array initializer of EIM peripheral base addresses */ +#define EIM_BASE_ADDRS { EIM_BASE } +/** Array initializer of EIM peripheral base pointers */ +#define EIM_BASE_PTRS { EIM } +/** Interrupt vectors for the EIM peripheral type */ +#define EIM_IRQS { WEIM_IRQn } + +/*! + * @} + */ /* end of group EIM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENET Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer + * @{ + */ + +/** ENET - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ + __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */ + __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */ + uint8_t RESERVED_2[12]; + __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ + uint8_t RESERVED_3[24]; + __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ + __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ + uint8_t RESERVED_4[28]; + __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ + uint8_t RESERVED_5[28]; + __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ + uint8_t RESERVED_6[60]; + __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ + uint8_t RESERVED_7[28]; + __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ + __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ + __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ + __IO uint32_t TXIC; /**< Transmit Interrupt Coalescing Register, offset: 0xF0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t RXIC; /**< Receive Interrupt Coalescing Register, offset: 0x100 */ + uint8_t RESERVED_9[20]; + __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ + __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ + __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ + __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ + uint8_t RESERVED_10[28]; + __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ + uint8_t RESERVED_11[56]; + __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */ + __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */ + __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */ + uint8_t RESERVED_12[4]; + __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ + __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ + __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ + __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ + __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ + __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ + __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ + __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ + __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ + __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ + uint8_t RESERVED_14[56]; + __I uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */ + __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ + __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ + __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ + __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ + __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ + __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ + __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ + __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ + __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ + __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ + __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ + __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ + __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ + __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ + __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ + __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ + __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ + __I uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */ + __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ + __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ + __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ + __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ + __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ + __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ + __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ + __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ + __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */ + __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ + __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ + uint8_t RESERVED_15[12]; + __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ + __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ + __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ + __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ + __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ + __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ + __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ + __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ + __I uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */ + __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ + __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ + __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ + __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ + __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ + __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ + __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ + __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ + __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ + __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ + __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ + __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ + __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ + __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ + __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ + uint8_t RESERVED_16[284]; + __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ + __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ + __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ + __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ + __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ + __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ + __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ + uint8_t RESERVED_17[488]; + __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ + struct { /* offset: 0x608, array step: 0x8 */ + __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ + __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ + } CHANNEL[4]; +} ENET_Type; + +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/*! @name EIR - Interrupt Event Register */ +#define ENET_EIR_TS_TIMER_MASK (0x8000U) +#define ENET_EIR_TS_TIMER_SHIFT (15U) +#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) +#define ENET_EIR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIR_TS_AVAIL_SHIFT (16U) +#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) +#define ENET_EIR_WAKEUP_MASK (0x20000U) +#define ENET_EIR_WAKEUP_SHIFT (17U) +#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) +#define ENET_EIR_PLR_MASK (0x40000U) +#define ENET_EIR_PLR_SHIFT (18U) +#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) +#define ENET_EIR_UN_MASK (0x80000U) +#define ENET_EIR_UN_SHIFT (19U) +#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) +#define ENET_EIR_RL_MASK (0x100000U) +#define ENET_EIR_RL_SHIFT (20U) +#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) +#define ENET_EIR_LC_MASK (0x200000U) +#define ENET_EIR_LC_SHIFT (21U) +#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) +#define ENET_EIR_EBERR_MASK (0x400000U) +#define ENET_EIR_EBERR_SHIFT (22U) +#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) +#define ENET_EIR_MII_MASK (0x800000U) +#define ENET_EIR_MII_SHIFT (23U) +#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) +#define ENET_EIR_RXB_MASK (0x1000000U) +#define ENET_EIR_RXB_SHIFT (24U) +#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) +#define ENET_EIR_RXF_MASK (0x2000000U) +#define ENET_EIR_RXF_SHIFT (25U) +#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) +#define ENET_EIR_TXB_MASK (0x4000000U) +#define ENET_EIR_TXB_SHIFT (26U) +#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) +#define ENET_EIR_TXF_MASK (0x8000000U) +#define ENET_EIR_TXF_SHIFT (27U) +#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) +#define ENET_EIR_GRA_MASK (0x10000000U) +#define ENET_EIR_GRA_SHIFT (28U) +#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) +#define ENET_EIR_BABT_MASK (0x20000000U) +#define ENET_EIR_BABT_SHIFT (29U) +#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) +#define ENET_EIR_BABR_MASK (0x40000000U) +#define ENET_EIR_BABR_SHIFT (30U) +#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) + +/*! @name EIMR - Interrupt Mask Register */ +#define ENET_EIMR_TS_TIMER_MASK (0x8000U) +#define ENET_EIMR_TS_TIMER_SHIFT (15U) +#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) +#define ENET_EIMR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIMR_TS_AVAIL_SHIFT (16U) +#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) +#define ENET_EIMR_WAKEUP_MASK (0x20000U) +#define ENET_EIMR_WAKEUP_SHIFT (17U) +#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) +#define ENET_EIMR_PLR_MASK (0x40000U) +#define ENET_EIMR_PLR_SHIFT (18U) +#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) +#define ENET_EIMR_UN_MASK (0x80000U) +#define ENET_EIMR_UN_SHIFT (19U) +#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) +#define ENET_EIMR_RL_MASK (0x100000U) +#define ENET_EIMR_RL_SHIFT (20U) +#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) +#define ENET_EIMR_LC_MASK (0x200000U) +#define ENET_EIMR_LC_SHIFT (21U) +#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) +#define ENET_EIMR_EBERR_MASK (0x400000U) +#define ENET_EIMR_EBERR_SHIFT (22U) +#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) +#define ENET_EIMR_MII_MASK (0x800000U) +#define ENET_EIMR_MII_SHIFT (23U) +#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) +#define ENET_EIMR_RXB_MASK (0x1000000U) +#define ENET_EIMR_RXB_SHIFT (24U) +#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) +#define ENET_EIMR_RXF_MASK (0x2000000U) +#define ENET_EIMR_RXF_SHIFT (25U) +#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) +#define ENET_EIMR_TXB_MASK (0x4000000U) +#define ENET_EIMR_TXB_SHIFT (26U) +#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) +#define ENET_EIMR_TXF_MASK (0x8000000U) +#define ENET_EIMR_TXF_SHIFT (27U) +#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) +#define ENET_EIMR_GRA_MASK (0x10000000U) +#define ENET_EIMR_GRA_SHIFT (28U) +#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) +#define ENET_EIMR_BABT_MASK (0x20000000U) +#define ENET_EIMR_BABT_SHIFT (29U) +#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) +#define ENET_EIMR_BABR_MASK (0x40000000U) +#define ENET_EIMR_BABR_SHIFT (30U) +#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) + +/*! @name RDAR - Receive Descriptor Active Register */ +#define ENET_RDAR_RDAR_MASK (0x1000000U) +#define ENET_RDAR_RDAR_SHIFT (24U) +#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) + +/*! @name TDAR - Transmit Descriptor Active Register */ +#define ENET_TDAR_TDAR_MASK (0x1000000U) +#define ENET_TDAR_TDAR_SHIFT (24U) +#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) + +/*! @name ECR - Ethernet Control Register */ +#define ENET_ECR_RESET_MASK (0x1U) +#define ENET_ECR_RESET_SHIFT (0U) +#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) +#define ENET_ECR_ETHEREN_MASK (0x2U) +#define ENET_ECR_ETHEREN_SHIFT (1U) +#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) +#define ENET_ECR_MAGICEN_MASK (0x4U) +#define ENET_ECR_MAGICEN_SHIFT (2U) +#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) +#define ENET_ECR_SLEEP_MASK (0x8U) +#define ENET_ECR_SLEEP_SHIFT (3U) +#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) +#define ENET_ECR_EN1588_MASK (0x10U) +#define ENET_ECR_EN1588_SHIFT (4U) +#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) +#define ENET_ECR_DBGEN_MASK (0x40U) +#define ENET_ECR_DBGEN_SHIFT (6U) +#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) +#define ENET_ECR_DBSWP_MASK (0x100U) +#define ENET_ECR_DBSWP_SHIFT (8U) +#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) + +/*! @name MMFR - MII Management Frame Register */ +#define ENET_MMFR_DATA_MASK (0xFFFFU) +#define ENET_MMFR_DATA_SHIFT (0U) +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) +#define ENET_MMFR_TA_MASK (0x30000U) +#define ENET_MMFR_TA_SHIFT (16U) +#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) +#define ENET_MMFR_RA_MASK (0x7C0000U) +#define ENET_MMFR_RA_SHIFT (18U) +#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) +#define ENET_MMFR_PA_MASK (0xF800000U) +#define ENET_MMFR_PA_SHIFT (23U) +#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) +#define ENET_MMFR_OP_MASK (0x30000000U) +#define ENET_MMFR_OP_SHIFT (28U) +#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) +#define ENET_MMFR_ST_MASK (0xC0000000U) +#define ENET_MMFR_ST_SHIFT (30U) +#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) + +/*! @name MSCR - MII Speed Control Register */ +#define ENET_MSCR_MII_SPEED_MASK (0x7EU) +#define ENET_MSCR_MII_SPEED_SHIFT (1U) +#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) +#define ENET_MSCR_DIS_PRE_MASK (0x80U) +#define ENET_MSCR_DIS_PRE_SHIFT (7U) +#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) +#define ENET_MSCR_HOLDTIME_MASK (0x700U) +#define ENET_MSCR_HOLDTIME_SHIFT (8U) +#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) + +/*! @name MIBC - MIB Control Register */ +#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) +#define ENET_MIBC_MIB_CLEAR_SHIFT (29U) +#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) +#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) +#define ENET_MIBC_MIB_IDLE_SHIFT (30U) +#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) +#define ENET_MIBC_MIB_DIS_MASK (0x80000000U) +#define ENET_MIBC_MIB_DIS_SHIFT (31U) +#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) + +/*! @name RCR - Receive Control Register */ +#define ENET_RCR_LOOP_MASK (0x1U) +#define ENET_RCR_LOOP_SHIFT (0U) +#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) +#define ENET_RCR_DRT_MASK (0x2U) +#define ENET_RCR_DRT_SHIFT (1U) +#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) +#define ENET_RCR_MII_MODE_MASK (0x4U) +#define ENET_RCR_MII_MODE_SHIFT (2U) +#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) +#define ENET_RCR_PROM_MASK (0x8U) +#define ENET_RCR_PROM_SHIFT (3U) +#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) +#define ENET_RCR_BC_REJ_MASK (0x10U) +#define ENET_RCR_BC_REJ_SHIFT (4U) +#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) +#define ENET_RCR_FCE_MASK (0x20U) +#define ENET_RCR_FCE_SHIFT (5U) +#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) +#define ENET_RCR_RMII_MODE_MASK (0x100U) +#define ENET_RCR_RMII_MODE_SHIFT (8U) +#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) +#define ENET_RCR_RMII_10T_MASK (0x200U) +#define ENET_RCR_RMII_10T_SHIFT (9U) +#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) +#define ENET_RCR_PADEN_MASK (0x1000U) +#define ENET_RCR_PADEN_SHIFT (12U) +#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) +#define ENET_RCR_PAUFWD_MASK (0x2000U) +#define ENET_RCR_PAUFWD_SHIFT (13U) +#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) +#define ENET_RCR_CRCFWD_MASK (0x4000U) +#define ENET_RCR_CRCFWD_SHIFT (14U) +#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) +#define ENET_RCR_CFEN_MASK (0x8000U) +#define ENET_RCR_CFEN_SHIFT (15U) +#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) +#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) +#define ENET_RCR_MAX_FL_SHIFT (16U) +#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) +#define ENET_RCR_NLC_MASK (0x40000000U) +#define ENET_RCR_NLC_SHIFT (30U) +#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) +#define ENET_RCR_GRS_MASK (0x80000000U) +#define ENET_RCR_GRS_SHIFT (31U) +#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) + +/*! @name TCR - Transmit Control Register */ +#define ENET_TCR_GTS_MASK (0x1U) +#define ENET_TCR_GTS_SHIFT (0U) +#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) +#define ENET_TCR_FDEN_MASK (0x4U) +#define ENET_TCR_FDEN_SHIFT (2U) +#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) +#define ENET_TCR_TFC_PAUSE_MASK (0x8U) +#define ENET_TCR_TFC_PAUSE_SHIFT (3U) +#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) +#define ENET_TCR_RFC_PAUSE_MASK (0x10U) +#define ENET_TCR_RFC_PAUSE_SHIFT (4U) +#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) +#define ENET_TCR_ADDSEL_MASK (0xE0U) +#define ENET_TCR_ADDSEL_SHIFT (5U) +#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) +#define ENET_TCR_ADDINS_MASK (0x100U) +#define ENET_TCR_ADDINS_SHIFT (8U) +#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) +#define ENET_TCR_CRCFWD_MASK (0x200U) +#define ENET_TCR_CRCFWD_SHIFT (9U) +#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) + +/*! @name PALR - Physical Address Lower Register */ +#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) +#define ENET_PALR_PADDR1_SHIFT (0U) +#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) + +/*! @name PAUR - Physical Address Upper Register */ +#define ENET_PAUR_TYPE_MASK (0xFFFFU) +#define ENET_PAUR_TYPE_SHIFT (0U) +#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) +#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) +#define ENET_PAUR_PADDR2_SHIFT (16U) +#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) + +/*! @name OPD - Opcode/Pause Duration Register */ +#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) +#define ENET_OPD_PAUSE_DUR_SHIFT (0U) +#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) +#define ENET_OPD_OPCODE_MASK (0xFFFF0000U) +#define ENET_OPD_OPCODE_SHIFT (16U) +#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) + +/*! @name TXIC - Transmit Interrupt Coalescing Register */ +#define ENET_TXIC_ICTT_MASK (0xFFFFU) +#define ENET_TXIC_ICTT_SHIFT (0U) +#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) +#define ENET_TXIC_ICFT_MASK (0xFF00000U) +#define ENET_TXIC_ICFT_SHIFT (20U) +#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) +#define ENET_TXIC_ICCS_MASK (0x40000000U) +#define ENET_TXIC_ICCS_SHIFT (30U) +#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) +#define ENET_TXIC_ICEN_MASK (0x80000000U) +#define ENET_TXIC_ICEN_SHIFT (31U) +#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) + +/*! @name RXIC - Receive Interrupt Coalescing Register */ +#define ENET_RXIC_ICTT_MASK (0xFFFFU) +#define ENET_RXIC_ICTT_SHIFT (0U) +#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) +#define ENET_RXIC_ICFT_MASK (0xFF00000U) +#define ENET_RXIC_ICFT_SHIFT (20U) +#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) +#define ENET_RXIC_ICCS_MASK (0x40000000U) +#define ENET_RXIC_ICCS_SHIFT (30U) +#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) +#define ENET_RXIC_ICEN_MASK (0x80000000U) +#define ENET_RXIC_ICEN_SHIFT (31U) +#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) + +/*! @name IAUR - Descriptor Individual Upper Address Register */ +#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) +#define ENET_IAUR_IADDR1_SHIFT (0U) +#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) + +/*! @name IALR - Descriptor Individual Lower Address Register */ +#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) +#define ENET_IALR_IADDR2_SHIFT (0U) +#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) + +/*! @name GAUR - Descriptor Group Upper Address Register */ +#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) +#define ENET_GAUR_GADDR1_SHIFT (0U) +#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) + +/*! @name GALR - Descriptor Group Lower Address Register */ +#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) +#define ENET_GALR_GADDR2_SHIFT (0U) +#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) + +/*! @name TFWR - Transmit FIFO Watermark Register */ +#define ENET_TFWR_TFWR_MASK (0x3FU) +#define ENET_TFWR_TFWR_SHIFT (0U) +#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) +#define ENET_TFWR_STRFWD_MASK (0x100U) +#define ENET_TFWR_STRFWD_SHIFT (8U) +#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) + +/*! @name RDSR - Receive Descriptor Ring Start Register */ +#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) +#define ENET_RDSR_R_DES_START_SHIFT (3U) +#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) + +/*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */ +#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) +#define ENET_TDSR_X_DES_START_SHIFT (3U) +#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) + +/*! @name MRBR - Maximum Receive Buffer Size Register */ +#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) +#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) +#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) + +/*! @name RSFL - Receive FIFO Section Full Threshold */ +#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU) +#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) +#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) + +/*! @name RSEM - Receive FIFO Section Empty Threshold */ +#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU) +#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) +#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) +#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) +#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) +#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) + +/*! @name RAEM - Receive FIFO Almost Empty Threshold */ +#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU) +#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) +#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) + +/*! @name RAFL - Receive FIFO Almost Full Threshold */ +#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU) +#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) +#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) + +/*! @name TSEM - Transmit FIFO Section Empty Threshold */ +#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU) +#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) +#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) + +/*! @name TAEM - Transmit FIFO Almost Empty Threshold */ +#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU) +#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) +#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) + +/*! @name TAFL - Transmit FIFO Almost Full Threshold */ +#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU) +#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) +#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) + +/*! @name TIPG - Transmit Inter-Packet Gap */ +#define ENET_TIPG_IPG_MASK (0x1FU) +#define ENET_TIPG_IPG_SHIFT (0U) +#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) + +/*! @name FTRL - Frame Truncation Length */ +#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) +#define ENET_FTRL_TRUNC_FL_SHIFT (0U) +#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) + +/*! @name TACC - Transmit Accelerator Function Configuration */ +#define ENET_TACC_SHIFT16_MASK (0x1U) +#define ENET_TACC_SHIFT16_SHIFT (0U) +#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) +#define ENET_TACC_IPCHK_MASK (0x8U) +#define ENET_TACC_IPCHK_SHIFT (3U) +#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) +#define ENET_TACC_PROCHK_MASK (0x10U) +#define ENET_TACC_PROCHK_SHIFT (4U) +#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) + +/*! @name RACC - Receive Accelerator Function Configuration */ +#define ENET_RACC_PADREM_MASK (0x1U) +#define ENET_RACC_PADREM_SHIFT (0U) +#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) +#define ENET_RACC_IPDIS_MASK (0x2U) +#define ENET_RACC_IPDIS_SHIFT (1U) +#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) +#define ENET_RACC_PRODIS_MASK (0x4U) +#define ENET_RACC_PRODIS_SHIFT (2U) +#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) +#define ENET_RACC_LINEDIS_MASK (0x40U) +#define ENET_RACC_LINEDIS_SHIFT (6U) +#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) +#define ENET_RACC_SHIFT16_MASK (0x80U) +#define ENET_RACC_SHIFT16_SHIFT (7U) +#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) + +/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ +#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) + +/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ +#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) + +/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ +#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) + +/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) + +/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ +#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) + +/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ +#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) + +/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) + +/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ +#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) + +/*! @name RMON_T_COL - Tx Collision Count Statistic Register */ +#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) + +/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ +#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) + +/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ +#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) + +/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ +#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) + +/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ +#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) + +/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ +#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) + +/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ +#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) + +/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ +#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) + +/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ +#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) +#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) +#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) + +/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ +#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) + +/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ +#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) + +/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ +#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) + +/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ +#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) +#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) + +/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ +#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) + +/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ +#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) + +/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ +#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) + +/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ +#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) + +/*! @name IEEE_T_SQE - Reserved Statistic Register */ +#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) +#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) + +/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ +#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) + +/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ +#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) + +/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ +#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) + +/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ +#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) + +/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ +#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) + +/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ +#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) +#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) + +/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ +#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) + +/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ +#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) + +/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) +#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) + +/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ +#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_JAB_COUNT_SHIFT (0U) +#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) + +/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ +#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P64_COUNT_SHIFT (0U) +#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) + +/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ +#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) +#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) + +/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ +#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) +#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) + +/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ +#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) +#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) + +/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ +#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) +#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) + +/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ +#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) +#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) + +/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ +#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) +#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) + +/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ +#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) +#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) + +/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ +#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) +#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) + +/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ +#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) + +/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ +#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) + +/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ +#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) +#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) + +/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ +#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) + +/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ +#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) + +/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ +#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) + +/*! @name ATCR - Adjustable Timer Control Register */ +#define ENET_ATCR_EN_MASK (0x1U) +#define ENET_ATCR_EN_SHIFT (0U) +#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) +#define ENET_ATCR_OFFEN_MASK (0x4U) +#define ENET_ATCR_OFFEN_SHIFT (2U) +#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) +#define ENET_ATCR_OFFRST_MASK (0x8U) +#define ENET_ATCR_OFFRST_SHIFT (3U) +#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) +#define ENET_ATCR_PEREN_MASK (0x10U) +#define ENET_ATCR_PEREN_SHIFT (4U) +#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) +#define ENET_ATCR_PINPER_MASK (0x80U) +#define ENET_ATCR_PINPER_SHIFT (7U) +#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) +#define ENET_ATCR_RESTART_MASK (0x200U) +#define ENET_ATCR_RESTART_SHIFT (9U) +#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) +#define ENET_ATCR_CAPTURE_MASK (0x800U) +#define ENET_ATCR_CAPTURE_SHIFT (11U) +#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) +#define ENET_ATCR_SLAVE_MASK (0x2000U) +#define ENET_ATCR_SLAVE_SHIFT (13U) +#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) + +/*! @name ATVR - Timer Value Register */ +#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) +#define ENET_ATVR_ATIME_SHIFT (0U) +#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) + +/*! @name ATOFF - Timer Offset Register */ +#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) +#define ENET_ATOFF_OFFSET_SHIFT (0U) +#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) + +/*! @name ATPER - Timer Period Register */ +#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) +#define ENET_ATPER_PERIOD_SHIFT (0U) +#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) + +/*! @name ATCOR - Timer Correction Register */ +#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) +#define ENET_ATCOR_COR_SHIFT (0U) +#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) + +/*! @name ATINC - Time-Stamping Clock Period Register */ +#define ENET_ATINC_INC_MASK (0x7FU) +#define ENET_ATINC_INC_SHIFT (0U) +#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) +#define ENET_ATINC_INC_CORR_MASK (0x7F00U) +#define ENET_ATINC_INC_CORR_SHIFT (8U) +#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) + +/*! @name ATSTMP - Timestamp of Last Transmitted Frame */ +#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) +#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) +#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) + +/*! @name TGSR - Timer Global Status Register */ +#define ENET_TGSR_TF0_MASK (0x1U) +#define ENET_TGSR_TF0_SHIFT (0U) +#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) +#define ENET_TGSR_TF1_MASK (0x2U) +#define ENET_TGSR_TF1_SHIFT (1U) +#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) +#define ENET_TGSR_TF2_MASK (0x4U) +#define ENET_TGSR_TF2_SHIFT (2U) +#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) +#define ENET_TGSR_TF3_MASK (0x8U) +#define ENET_TGSR_TF3_SHIFT (3U) +#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) + +/*! @name TCSR - Timer Control Status Register */ +#define ENET_TCSR_TDRE_MASK (0x1U) +#define ENET_TCSR_TDRE_SHIFT (0U) +#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) +#define ENET_TCSR_TMODE_MASK (0x3CU) +#define ENET_TCSR_TMODE_SHIFT (2U) +#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) +#define ENET_TCSR_TIE_MASK (0x40U) +#define ENET_TCSR_TIE_SHIFT (6U) +#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) +#define ENET_TCSR_TF_MASK (0x80U) +#define ENET_TCSR_TF_SHIFT (7U) +#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) +#define ENET_TCSR_TPWC_MASK (0xF800U) +#define ENET_TCSR_TPWC_SHIFT (11U) +#define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK) + +/* The count of ENET_TCSR */ +#define ENET_TCSR_COUNT (4U) + +/*! @name TCCR - Timer Compare Capture Register */ +#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) +#define ENET_TCCR_TCC_SHIFT (0U) +#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) + +/* The count of ENET_TCCR */ +#define ENET_TCCR_COUNT (4U) + + +/*! + * @} + */ /* end of group ENET_Register_Masks */ + + +/* ENET - Peripheral instance base addresses */ +/** Peripheral ENET1 base address */ +#define ENET1_BASE (0x2188000u) +/** Peripheral ENET1 base pointer */ +#define ENET1 ((ENET_Type *)ENET1_BASE) +/** Peripheral ENET2 base address */ +#define ENET2_BASE (0x20B4000u) +/** Peripheral ENET2 base pointer */ +#define ENET2 ((ENET_Type *)ENET2_BASE) +/** Array initializer of ENET peripheral base addresses */ +#define ENET_BASE_ADDRS { 0u, ENET1_BASE, ENET2_BASE } +/** Array initializer of ENET peripheral base pointers */ +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1, ENET2 } +/** Interrupt vectors for the ENET peripheral type */ +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn, ENET2_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn, ENET2_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn, ENET2_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_IRQn, ENET2_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + + +/*! + * @} + */ /* end of group ENET_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EPIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EPIT_Peripheral_Access_Layer EPIT Peripheral Access Layer + * @{ + */ + +/** EPIT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control register, offset: 0x0 */ + __IO uint32_t SR; /**< Status register, offset: 0x4 */ + __IO uint32_t LR; /**< Load register, offset: 0x8 */ + __IO uint32_t CMPR; /**< Compare register, offset: 0xC */ + __I uint32_t CNR; /**< Counter register, offset: 0x10 */ +} EPIT_Type; + +/* ---------------------------------------------------------------------------- + -- EPIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EPIT_Register_Masks EPIT Register Masks + * @{ + */ + +/*! @name CR - Control register */ +#define EPIT_CR_EN_MASK (0x1U) +#define EPIT_CR_EN_SHIFT (0U) +#define EPIT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_EN_SHIFT)) & EPIT_CR_EN_MASK) +#define EPIT_CR_ENMOD_MASK (0x2U) +#define EPIT_CR_ENMOD_SHIFT (1U) +#define EPIT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_ENMOD_SHIFT)) & EPIT_CR_ENMOD_MASK) +#define EPIT_CR_OCIEN_MASK (0x4U) +#define EPIT_CR_OCIEN_SHIFT (2U) +#define EPIT_CR_OCIEN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_OCIEN_SHIFT)) & EPIT_CR_OCIEN_MASK) +#define EPIT_CR_RLD_MASK (0x8U) +#define EPIT_CR_RLD_SHIFT (3U) +#define EPIT_CR_RLD(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_RLD_SHIFT)) & EPIT_CR_RLD_MASK) +#define EPIT_CR_PRESCALAR_MASK (0xFFF0U) +#define EPIT_CR_PRESCALAR_SHIFT (4U) +#define EPIT_CR_PRESCALAR(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_PRESCALAR_SHIFT)) & EPIT_CR_PRESCALAR_MASK) +#define EPIT_CR_SWR_MASK (0x10000U) +#define EPIT_CR_SWR_SHIFT (16U) +#define EPIT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_SWR_SHIFT)) & EPIT_CR_SWR_MASK) +#define EPIT_CR_IOVW_MASK (0x20000U) +#define EPIT_CR_IOVW_SHIFT (17U) +#define EPIT_CR_IOVW(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_IOVW_SHIFT)) & EPIT_CR_IOVW_MASK) +#define EPIT_CR_DBGEN_MASK (0x40000U) +#define EPIT_CR_DBGEN_SHIFT (18U) +#define EPIT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_DBGEN_SHIFT)) & EPIT_CR_DBGEN_MASK) +#define EPIT_CR_WAITEN_MASK (0x80000U) +#define EPIT_CR_WAITEN_SHIFT (19U) +#define EPIT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_WAITEN_SHIFT)) & EPIT_CR_WAITEN_MASK) +#define EPIT_CR_STOPEN_MASK (0x200000U) +#define EPIT_CR_STOPEN_SHIFT (21U) +#define EPIT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_STOPEN_SHIFT)) & EPIT_CR_STOPEN_MASK) +#define EPIT_CR_OM_MASK (0xC00000U) +#define EPIT_CR_OM_SHIFT (22U) +#define EPIT_CR_OM(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_OM_SHIFT)) & EPIT_CR_OM_MASK) +#define EPIT_CR_CLKSRC_MASK (0x3000000U) +#define EPIT_CR_CLKSRC_SHIFT (24U) +#define EPIT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_CLKSRC_SHIFT)) & EPIT_CR_CLKSRC_MASK) + +/*! @name SR - Status register */ +#define EPIT_SR_OCIF_MASK (0x1U) +#define EPIT_SR_OCIF_SHIFT (0U) +#define EPIT_SR_OCIF(x) (((uint32_t)(((uint32_t)(x)) << EPIT_SR_OCIF_SHIFT)) & EPIT_SR_OCIF_MASK) + +/*! @name LR - Load register */ +#define EPIT_LR_LOAD_MASK (0xFFFFFFFFU) +#define EPIT_LR_LOAD_SHIFT (0U) +#define EPIT_LR_LOAD(x) (((uint32_t)(((uint32_t)(x)) << EPIT_LR_LOAD_SHIFT)) & EPIT_LR_LOAD_MASK) + +/*! @name CMPR - Compare register */ +#define EPIT_CMPR_COMPARE_MASK (0xFFFFFFFFU) +#define EPIT_CMPR_COMPARE_SHIFT (0U) +#define EPIT_CMPR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CMPR_COMPARE_SHIFT)) & EPIT_CMPR_COMPARE_MASK) + +/*! @name CNR - Counter register */ +#define EPIT_CNR_COUNT_MASK (0xFFFFFFFFU) +#define EPIT_CNR_COUNT_SHIFT (0U) +#define EPIT_CNR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CNR_COUNT_SHIFT)) & EPIT_CNR_COUNT_MASK) + + +/*! + * @} + */ /* end of group EPIT_Register_Masks */ + + +/* EPIT - Peripheral instance base addresses */ +/** Peripheral EPIT1 base address */ +#define EPIT1_BASE (0x20D0000u) +/** Peripheral EPIT1 base pointer */ +#define EPIT1 ((EPIT_Type *)EPIT1_BASE) +/** Peripheral EPIT2 base address */ +#define EPIT2_BASE (0x20D4000u) +/** Peripheral EPIT2 base pointer */ +#define EPIT2 ((EPIT_Type *)EPIT2_BASE) +/** Array initializer of EPIT peripheral base addresses */ +#define EPIT_BASE_ADDRS { 0u, EPIT1_BASE, EPIT2_BASE } +/** Array initializer of EPIT peripheral base pointers */ +#define EPIT_BASE_PTRS { (EPIT_Type *)0u, EPIT1, EPIT2 } +/** Interrupt vectors for the EPIT peripheral type */ +#define EPIT_IRQS { NotAvail_IRQn, EPIT1_IRQn, EPIT2_IRQn } + +/*! + * @} + */ /* end of group EPIT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ESAI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ESAI_Peripheral_Access_Layer ESAI Peripheral Access Layer + * @{ + */ + +/** ESAI - Register Layout Typedef */ +typedef struct { + __O uint32_t ETDR; /**< ESAI Transmit Data Register, offset: 0x0 */ + __I uint32_t ERDR; /**< ESAI Receive Data Register, offset: 0x4 */ + __IO uint32_t ECR; /**< ESAI Control Register, offset: 0x8 */ + __I uint32_t ESR; /**< ESAI Status Register, offset: 0xC */ + __IO uint32_t TFCR; /**< Transmit FIFO Configuration Register, offset: 0x10 */ + __I uint32_t TFSR; /**< Transmit FIFO Status Register, offset: 0x14 */ + __IO uint32_t RFCR; /**< Receive FIFO Configuration Register, offset: 0x18 */ + __I uint32_t RFSR; /**< Receive FIFO Status Register, offset: 0x1C */ + uint8_t RESERVED_0[96]; + __IO uint32_t TX[6]; /**< Transmit Data Register n, array offset: 0x80, array step: 0x4 */ + __IO uint32_t TSR; /**< ESAI Transmit Slot Register, offset: 0x98 */ + uint8_t RESERVED_1[4]; + __I uint32_t RX[4]; /**< Receive Data Register n, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_2[28]; + __I uint32_t SAISR; /**< Serial Audio Interface Status Register, offset: 0xCC */ + __IO uint32_t SAICR; /**< Serial Audio Interface Control Register, offset: 0xD0 */ + __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xD4 */ + __IO uint32_t TCCR; /**< Transmit Clock Control Register, offset: 0xD8 */ + __IO uint32_t RCR; /**< Receive Control Register, offset: 0xDC */ + __IO uint32_t RCCR; /**< Receive Clock Control Register, offset: 0xE0 */ + __IO uint32_t TSMA; /**< Transmit Slot Mask Register A, offset: 0xE4 */ + __IO uint32_t TSMB; /**< Transmit Slot Mask Register B, offset: 0xE8 */ + __IO uint32_t RSMA; /**< Receive Slot Mask Register A, offset: 0xEC */ + __IO uint32_t RSMB; /**< Receive Slot Mask Register B, offset: 0xF0 */ + uint8_t RESERVED_3[4]; + __IO uint32_t PRRC; /**< Port C Direction Register, offset: 0xF8 */ + __IO uint32_t PCRC; /**< Port C Control Register, offset: 0xFC */ +} ESAI_Type; + +/* ---------------------------------------------------------------------------- + -- ESAI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ESAI_Register_Masks ESAI Register Masks + * @{ + */ + +/*! @name ETDR - ESAI Transmit Data Register */ +#define ESAI_ETDR_ETDR_MASK (0xFFFFFFFFU) +#define ESAI_ETDR_ETDR_SHIFT (0U) +#define ESAI_ETDR_ETDR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ETDR_ETDR_SHIFT)) & ESAI_ETDR_ETDR_MASK) + +/*! @name ERDR - ESAI Receive Data Register */ +#define ESAI_ERDR_ERDR_MASK (0xFFFFFFFFU) +#define ESAI_ERDR_ERDR_SHIFT (0U) +#define ESAI_ERDR_ERDR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ERDR_ERDR_SHIFT)) & ESAI_ERDR_ERDR_MASK) + +/*! @name ECR - ESAI Control Register */ +#define ESAI_ECR_ESAIEN_MASK (0x1U) +#define ESAI_ECR_ESAIEN_SHIFT (0U) +#define ESAI_ECR_ESAIEN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ESAIEN_SHIFT)) & ESAI_ECR_ESAIEN_MASK) +#define ESAI_ECR_ERST_MASK (0x2U) +#define ESAI_ECR_ERST_SHIFT (1U) +#define ESAI_ECR_ERST(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERST_SHIFT)) & ESAI_ECR_ERST_MASK) +#define ESAI_ECR_ERO_MASK (0x10000U) +#define ESAI_ECR_ERO_SHIFT (16U) +#define ESAI_ECR_ERO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERO_SHIFT)) & ESAI_ECR_ERO_MASK) +#define ESAI_ECR_ERI_MASK (0x20000U) +#define ESAI_ECR_ERI_SHIFT (17U) +#define ESAI_ECR_ERI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERI_SHIFT)) & ESAI_ECR_ERI_MASK) +#define ESAI_ECR_ETO_MASK (0x40000U) +#define ESAI_ECR_ETO_SHIFT (18U) +#define ESAI_ECR_ETO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ETO_SHIFT)) & ESAI_ECR_ETO_MASK) +#define ESAI_ECR_ETI_MASK (0x80000U) +#define ESAI_ECR_ETI_SHIFT (19U) +#define ESAI_ECR_ETI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ETI_SHIFT)) & ESAI_ECR_ETI_MASK) + +/*! @name ESR - ESAI Status Register */ +#define ESAI_ESR_RD_MASK (0x1U) +#define ESAI_ESR_RD_SHIFT (0U) +#define ESAI_ESR_RD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RD_SHIFT)) & ESAI_ESR_RD_MASK) +#define ESAI_ESR_RED_MASK (0x2U) +#define ESAI_ESR_RED_SHIFT (1U) +#define ESAI_ESR_RED(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RED_SHIFT)) & ESAI_ESR_RED_MASK) +#define ESAI_ESR_RDE_MASK (0x4U) +#define ESAI_ESR_RDE_SHIFT (2U) +#define ESAI_ESR_RDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RDE_SHIFT)) & ESAI_ESR_RDE_MASK) +#define ESAI_ESR_RLS_MASK (0x8U) +#define ESAI_ESR_RLS_SHIFT (3U) +#define ESAI_ESR_RLS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RLS_SHIFT)) & ESAI_ESR_RLS_MASK) +#define ESAI_ESR_TD_MASK (0x10U) +#define ESAI_ESR_TD_SHIFT (4U) +#define ESAI_ESR_TD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TD_SHIFT)) & ESAI_ESR_TD_MASK) +#define ESAI_ESR_TED_MASK (0x20U) +#define ESAI_ESR_TED_SHIFT (5U) +#define ESAI_ESR_TED(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TED_SHIFT)) & ESAI_ESR_TED_MASK) +#define ESAI_ESR_TDE_MASK (0x40U) +#define ESAI_ESR_TDE_SHIFT (6U) +#define ESAI_ESR_TDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TDE_SHIFT)) & ESAI_ESR_TDE_MASK) +#define ESAI_ESR_TLS_MASK (0x80U) +#define ESAI_ESR_TLS_SHIFT (7U) +#define ESAI_ESR_TLS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TLS_SHIFT)) & ESAI_ESR_TLS_MASK) +#define ESAI_ESR_TFE_MASK (0x100U) +#define ESAI_ESR_TFE_SHIFT (8U) +#define ESAI_ESR_TFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TFE_SHIFT)) & ESAI_ESR_TFE_MASK) +#define ESAI_ESR_RFF_MASK (0x200U) +#define ESAI_ESR_RFF_SHIFT (9U) +#define ESAI_ESR_RFF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RFF_SHIFT)) & ESAI_ESR_RFF_MASK) +#define ESAI_ESR_TINIT_MASK (0x400U) +#define ESAI_ESR_TINIT_SHIFT (10U) +#define ESAI_ESR_TINIT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TINIT_SHIFT)) & ESAI_ESR_TINIT_MASK) + +/*! @name TFCR - Transmit FIFO Configuration Register */ +#define ESAI_TFCR_TFE_MASK (0x1U) +#define ESAI_TFCR_TFE_SHIFT (0U) +#define ESAI_TFCR_TFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFE_SHIFT)) & ESAI_TFCR_TFE_MASK) +#define ESAI_TFCR_TFR_MASK (0x2U) +#define ESAI_TFCR_TFR_SHIFT (1U) +#define ESAI_TFCR_TFR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFR_SHIFT)) & ESAI_TFCR_TFR_MASK) +#define ESAI_TFCR_TE0_MASK (0x4U) +#define ESAI_TFCR_TE0_SHIFT (2U) +#define ESAI_TFCR_TE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE0_SHIFT)) & ESAI_TFCR_TE0_MASK) +#define ESAI_TFCR_TE1_MASK (0x8U) +#define ESAI_TFCR_TE1_SHIFT (3U) +#define ESAI_TFCR_TE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE1_SHIFT)) & ESAI_TFCR_TE1_MASK) +#define ESAI_TFCR_TE2_MASK (0x10U) +#define ESAI_TFCR_TE2_SHIFT (4U) +#define ESAI_TFCR_TE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE2_SHIFT)) & ESAI_TFCR_TE2_MASK) +#define ESAI_TFCR_TE3_MASK (0x20U) +#define ESAI_TFCR_TE3_SHIFT (5U) +#define ESAI_TFCR_TE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE3_SHIFT)) & ESAI_TFCR_TE3_MASK) +#define ESAI_TFCR_TE4_MASK (0x40U) +#define ESAI_TFCR_TE4_SHIFT (6U) +#define ESAI_TFCR_TE4(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE4_SHIFT)) & ESAI_TFCR_TE4_MASK) +#define ESAI_TFCR_TE5_MASK (0x80U) +#define ESAI_TFCR_TE5_SHIFT (7U) +#define ESAI_TFCR_TE5(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE5_SHIFT)) & ESAI_TFCR_TE5_MASK) +#define ESAI_TFCR_TFWM_MASK (0xFF00U) +#define ESAI_TFCR_TFWM_SHIFT (8U) +#define ESAI_TFCR_TFWM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFWM_SHIFT)) & ESAI_TFCR_TFWM_MASK) +#define ESAI_TFCR_TWA_MASK (0x70000U) +#define ESAI_TFCR_TWA_SHIFT (16U) +#define ESAI_TFCR_TWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TWA_SHIFT)) & ESAI_TFCR_TWA_MASK) +#define ESAI_TFCR_TIEN_MASK (0x80000U) +#define ESAI_TFCR_TIEN_SHIFT (19U) +#define ESAI_TFCR_TIEN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TIEN_SHIFT)) & ESAI_TFCR_TIEN_MASK) +#define ESAI_TFCR_TAENB_MASK (0x100000U) +#define ESAI_TFCR_TAENB_SHIFT (20U) +#define ESAI_TFCR_TAENB(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TAENB_SHIFT)) & ESAI_TFCR_TAENB_MASK) +#define ESAI_TFCR_TFIN_MASK (0x200000U) +#define ESAI_TFCR_TFIN_SHIFT (21U) +#define ESAI_TFCR_TFIN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFIN_SHIFT)) & ESAI_TFCR_TFIN_MASK) + +/*! @name TFSR - Transmit FIFO Status Register */ +#define ESAI_TFSR_TFCNT_MASK (0xFFU) +#define ESAI_TFSR_TFCNT_SHIFT (0U) +#define ESAI_TFSR_TFCNT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_TFCNT_SHIFT)) & ESAI_TFSR_TFCNT_MASK) +#define ESAI_TFSR_NTFI_MASK (0x700U) +#define ESAI_TFSR_NTFI_SHIFT (8U) +#define ESAI_TFSR_NTFI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_NTFI_SHIFT)) & ESAI_TFSR_NTFI_MASK) +#define ESAI_TFSR_NTFO_MASK (0x7000U) +#define ESAI_TFSR_NTFO_SHIFT (12U) +#define ESAI_TFSR_NTFO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_NTFO_SHIFT)) & ESAI_TFSR_NTFO_MASK) + +/*! @name RFCR - Receive FIFO Configuration Register */ +#define ESAI_RFCR_RFE_MASK (0x1U) +#define ESAI_RFCR_RFE_SHIFT (0U) +#define ESAI_RFCR_RFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFE_SHIFT)) & ESAI_RFCR_RFE_MASK) +#define ESAI_RFCR_RFR_MASK (0x2U) +#define ESAI_RFCR_RFR_SHIFT (1U) +#define ESAI_RFCR_RFR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFR_SHIFT)) & ESAI_RFCR_RFR_MASK) +#define ESAI_RFCR_RE0_MASK (0x4U) +#define ESAI_RFCR_RE0_SHIFT (2U) +#define ESAI_RFCR_RE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE0_SHIFT)) & ESAI_RFCR_RE0_MASK) +#define ESAI_RFCR_RE1_MASK (0x8U) +#define ESAI_RFCR_RE1_SHIFT (3U) +#define ESAI_RFCR_RE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE1_SHIFT)) & ESAI_RFCR_RE1_MASK) +#define ESAI_RFCR_RE2_MASK (0x10U) +#define ESAI_RFCR_RE2_SHIFT (4U) +#define ESAI_RFCR_RE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE2_SHIFT)) & ESAI_RFCR_RE2_MASK) +#define ESAI_RFCR_RE3_MASK (0x20U) +#define ESAI_RFCR_RE3_SHIFT (5U) +#define ESAI_RFCR_RE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE3_SHIFT)) & ESAI_RFCR_RE3_MASK) +#define ESAI_RFCR_RFWM_MASK (0xFF00U) +#define ESAI_RFCR_RFWM_SHIFT (8U) +#define ESAI_RFCR_RFWM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFWM_SHIFT)) & ESAI_RFCR_RFWM_MASK) +#define ESAI_RFCR_RWA_MASK (0x70000U) +#define ESAI_RFCR_RWA_SHIFT (16U) +#define ESAI_RFCR_RWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RWA_SHIFT)) & ESAI_RFCR_RWA_MASK) +#define ESAI_RFCR_REXT_MASK (0x80000U) +#define ESAI_RFCR_REXT_SHIFT (19U) +#define ESAI_RFCR_REXT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_REXT_SHIFT)) & ESAI_RFCR_REXT_MASK) +#define ESAI_RFCR_RAENB_MASK (0x100000U) +#define ESAI_RFCR_RAENB_SHIFT (20U) +#define ESAI_RFCR_RAENB(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RAENB_SHIFT)) & ESAI_RFCR_RAENB_MASK) +#define ESAI_RFCR_RFIN_MASK (0x200000U) +#define ESAI_RFCR_RFIN_SHIFT (21U) +#define ESAI_RFCR_RFIN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFIN_SHIFT)) & ESAI_RFCR_RFIN_MASK) + +/*! @name RFSR - Receive FIFO Status Register */ +#define ESAI_RFSR_RFCNT_MASK (0xFFU) +#define ESAI_RFSR_RFCNT_SHIFT (0U) +#define ESAI_RFSR_RFCNT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_RFCNT_SHIFT)) & ESAI_RFSR_RFCNT_MASK) +#define ESAI_RFSR_NRFO_MASK (0x300U) +#define ESAI_RFSR_NRFO_SHIFT (8U) +#define ESAI_RFSR_NRFO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_NRFO_SHIFT)) & ESAI_RFSR_NRFO_MASK) +#define ESAI_RFSR_NRFI_MASK (0x3000U) +#define ESAI_RFSR_NRFI_SHIFT (12U) +#define ESAI_RFSR_NRFI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_NRFI_SHIFT)) & ESAI_RFSR_NRFI_MASK) + +/*! @name TX - Transmit Data Register n */ +#define ESAI_TX_TXn_MASK (0xFFFFFFU) +#define ESAI_TX_TXn_SHIFT (0U) +#define ESAI_TX_TXn(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TX_TXn_SHIFT)) & ESAI_TX_TXn_MASK) + +/* The count of ESAI_TX */ +#define ESAI_TX_COUNT (6U) + +/*! @name TSR - ESAI Transmit Slot Register */ +#define ESAI_TSR_TSR_MASK (0xFFFFFFU) +#define ESAI_TSR_TSR_SHIFT (0U) +#define ESAI_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TSR_TSR_SHIFT)) & ESAI_TSR_TSR_MASK) + +/*! @name RX - Receive Data Register n */ +#define ESAI_RX_RXn_MASK (0xFFFFFFU) +#define ESAI_RX_RXn_SHIFT (0U) +#define ESAI_RX_RXn(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RX_RXn_SHIFT)) & ESAI_RX_RXn_MASK) + +/* The count of ESAI_RX */ +#define ESAI_RX_COUNT (4U) + +/*! @name SAISR - Serial Audio Interface Status Register */ +#define ESAI_SAISR_IF0_MASK (0x1U) +#define ESAI_SAISR_IF0_SHIFT (0U) +#define ESAI_SAISR_IF0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF0_SHIFT)) & ESAI_SAISR_IF0_MASK) +#define ESAI_SAISR_IF1_MASK (0x2U) +#define ESAI_SAISR_IF1_SHIFT (1U) +#define ESAI_SAISR_IF1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF1_SHIFT)) & ESAI_SAISR_IF1_MASK) +#define ESAI_SAISR_IF2_MASK (0x4U) +#define ESAI_SAISR_IF2_SHIFT (2U) +#define ESAI_SAISR_IF2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF2_SHIFT)) & ESAI_SAISR_IF2_MASK) +#define ESAI_SAISR_RFS_MASK (0x40U) +#define ESAI_SAISR_RFS_SHIFT (6U) +#define ESAI_SAISR_RFS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RFS_SHIFT)) & ESAI_SAISR_RFS_MASK) +#define ESAI_SAISR_ROE_MASK (0x80U) +#define ESAI_SAISR_ROE_SHIFT (7U) +#define ESAI_SAISR_ROE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_ROE_SHIFT)) & ESAI_SAISR_ROE_MASK) +#define ESAI_SAISR_RDF_MASK (0x100U) +#define ESAI_SAISR_RDF_SHIFT (8U) +#define ESAI_SAISR_RDF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RDF_SHIFT)) & ESAI_SAISR_RDF_MASK) +#define ESAI_SAISR_REDF_MASK (0x200U) +#define ESAI_SAISR_REDF_SHIFT (9U) +#define ESAI_SAISR_REDF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_REDF_SHIFT)) & ESAI_SAISR_REDF_MASK) +#define ESAI_SAISR_RODF_MASK (0x400U) +#define ESAI_SAISR_RODF_SHIFT (10U) +#define ESAI_SAISR_RODF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RODF_SHIFT)) & ESAI_SAISR_RODF_MASK) +#define ESAI_SAISR_TFS_MASK (0x2000U) +#define ESAI_SAISR_TFS_SHIFT (13U) +#define ESAI_SAISR_TFS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TFS_SHIFT)) & ESAI_SAISR_TFS_MASK) +#define ESAI_SAISR_TUE_MASK (0x4000U) +#define ESAI_SAISR_TUE_SHIFT (14U) +#define ESAI_SAISR_TUE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TUE_SHIFT)) & ESAI_SAISR_TUE_MASK) +#define ESAI_SAISR_TDE_MASK (0x8000U) +#define ESAI_SAISR_TDE_SHIFT (15U) +#define ESAI_SAISR_TDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TDE_SHIFT)) & ESAI_SAISR_TDE_MASK) +#define ESAI_SAISR_TEDE_MASK (0x10000U) +#define ESAI_SAISR_TEDE_SHIFT (16U) +#define ESAI_SAISR_TEDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TEDE_SHIFT)) & ESAI_SAISR_TEDE_MASK) +#define ESAI_SAISR_TODFE_MASK (0x20000U) +#define ESAI_SAISR_TODFE_SHIFT (17U) +#define ESAI_SAISR_TODFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TODFE_SHIFT)) & ESAI_SAISR_TODFE_MASK) + +/*! @name SAICR - Serial Audio Interface Control Register */ +#define ESAI_SAICR_OF0_MASK (0x1U) +#define ESAI_SAICR_OF0_SHIFT (0U) +#define ESAI_SAICR_OF0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF0_SHIFT)) & ESAI_SAICR_OF0_MASK) +#define ESAI_SAICR_OF1_MASK (0x2U) +#define ESAI_SAICR_OF1_SHIFT (1U) +#define ESAI_SAICR_OF1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF1_SHIFT)) & ESAI_SAICR_OF1_MASK) +#define ESAI_SAICR_OF2_MASK (0x4U) +#define ESAI_SAICR_OF2_SHIFT (2U) +#define ESAI_SAICR_OF2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF2_SHIFT)) & ESAI_SAICR_OF2_MASK) +#define ESAI_SAICR_SYN_MASK (0x40U) +#define ESAI_SAICR_SYN_SHIFT (6U) +#define ESAI_SAICR_SYN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_SYN_SHIFT)) & ESAI_SAICR_SYN_MASK) +#define ESAI_SAICR_TEBE_MASK (0x80U) +#define ESAI_SAICR_TEBE_SHIFT (7U) +#define ESAI_SAICR_TEBE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_TEBE_SHIFT)) & ESAI_SAICR_TEBE_MASK) +#define ESAI_SAICR_ALC_MASK (0x100U) +#define ESAI_SAICR_ALC_SHIFT (8U) +#define ESAI_SAICR_ALC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_ALC_SHIFT)) & ESAI_SAICR_ALC_MASK) + +/*! @name TCR - Transmit Control Register */ +#define ESAI_TCR_TE0_MASK (0x1U) +#define ESAI_TCR_TE0_SHIFT (0U) +#define ESAI_TCR_TE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE0_SHIFT)) & ESAI_TCR_TE0_MASK) +#define ESAI_TCR_TE1_MASK (0x2U) +#define ESAI_TCR_TE1_SHIFT (1U) +#define ESAI_TCR_TE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE1_SHIFT)) & ESAI_TCR_TE1_MASK) +#define ESAI_TCR_TE2_MASK (0x4U) +#define ESAI_TCR_TE2_SHIFT (2U) +#define ESAI_TCR_TE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE2_SHIFT)) & ESAI_TCR_TE2_MASK) +#define ESAI_TCR_TE3_MASK (0x8U) +#define ESAI_TCR_TE3_SHIFT (3U) +#define ESAI_TCR_TE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE3_SHIFT)) & ESAI_TCR_TE3_MASK) +#define ESAI_TCR_TE4_MASK (0x10U) +#define ESAI_TCR_TE4_SHIFT (4U) +#define ESAI_TCR_TE4(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE4_SHIFT)) & ESAI_TCR_TE4_MASK) +#define ESAI_TCR_TE5_MASK (0x20U) +#define ESAI_TCR_TE5_SHIFT (5U) +#define ESAI_TCR_TE5(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE5_SHIFT)) & ESAI_TCR_TE5_MASK) +#define ESAI_TCR_TSHFD_MASK (0x40U) +#define ESAI_TCR_TSHFD_SHIFT (6U) +#define ESAI_TCR_TSHFD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TSHFD_SHIFT)) & ESAI_TCR_TSHFD_MASK) +#define ESAI_TCR_TWA_MASK (0x80U) +#define ESAI_TCR_TWA_SHIFT (7U) +#define ESAI_TCR_TWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TWA_SHIFT)) & ESAI_TCR_TWA_MASK) +#define ESAI_TCR_TMOD_MASK (0x300U) +#define ESAI_TCR_TMOD_SHIFT (8U) +#define ESAI_TCR_TMOD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TMOD_SHIFT)) & ESAI_TCR_TMOD_MASK) +#define ESAI_TCR_TSWS_MASK (0x7C00U) +#define ESAI_TCR_TSWS_SHIFT (10U) +#define ESAI_TCR_TSWS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TSWS_SHIFT)) & ESAI_TCR_TSWS_MASK) +#define ESAI_TCR_TFSL_MASK (0x8000U) +#define ESAI_TCR_TFSL_SHIFT (15U) +#define ESAI_TCR_TFSL(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TFSL_SHIFT)) & ESAI_TCR_TFSL_MASK) +#define ESAI_TCR_TFSR_MASK (0x10000U) +#define ESAI_TCR_TFSR_SHIFT (16U) +#define ESAI_TCR_TFSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TFSR_SHIFT)) & ESAI_TCR_TFSR_MASK) +#define ESAI_TCR_PADC_MASK (0x20000U) +#define ESAI_TCR_PADC_SHIFT (17U) +#define ESAI_TCR_PADC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_PADC_SHIFT)) & ESAI_TCR_PADC_MASK) +#define ESAI_TCR_TPR_MASK (0x80000U) +#define ESAI_TCR_TPR_SHIFT (19U) +#define ESAI_TCR_TPR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TPR_SHIFT)) & ESAI_TCR_TPR_MASK) +#define ESAI_TCR_TEIE_MASK (0x100000U) +#define ESAI_TCR_TEIE_SHIFT (20U) +#define ESAI_TCR_TEIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TEIE_SHIFT)) & ESAI_TCR_TEIE_MASK) +#define ESAI_TCR_TEDIE_MASK (0x200000U) +#define ESAI_TCR_TEDIE_SHIFT (21U) +#define ESAI_TCR_TEDIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TEDIE_SHIFT)) & ESAI_TCR_TEDIE_MASK) +#define ESAI_TCR_TIE_MASK (0x400000U) +#define ESAI_TCR_TIE_SHIFT (22U) +#define ESAI_TCR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TIE_SHIFT)) & ESAI_TCR_TIE_MASK) +#define ESAI_TCR_TLIE_MASK (0x800000U) +#define ESAI_TCR_TLIE_SHIFT (23U) +#define ESAI_TCR_TLIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TLIE_SHIFT)) & ESAI_TCR_TLIE_MASK) + +/*! @name TCCR - Transmit Clock Control Register */ +#define ESAI_TCCR_TPM_MASK (0xFFU) +#define ESAI_TCCR_TPM_SHIFT (0U) +#define ESAI_TCCR_TPM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TPM_SHIFT)) & ESAI_TCCR_TPM_MASK) +#define ESAI_TCCR_TPSR_MASK (0x100U) +#define ESAI_TCCR_TPSR_SHIFT (8U) +#define ESAI_TCCR_TPSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TPSR_SHIFT)) & ESAI_TCCR_TPSR_MASK) +#define ESAI_TCCR_TDC_MASK (0x3E00U) +#define ESAI_TCCR_TDC_SHIFT (9U) +#define ESAI_TCCR_TDC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TDC_SHIFT)) & ESAI_TCCR_TDC_MASK) +#define ESAI_TCCR_TFP_MASK (0x3C000U) +#define ESAI_TCCR_TFP_SHIFT (14U) +#define ESAI_TCCR_TFP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFP_SHIFT)) & ESAI_TCCR_TFP_MASK) +#define ESAI_TCCR_TCKP_MASK (0x40000U) +#define ESAI_TCCR_TCKP_SHIFT (18U) +#define ESAI_TCCR_TCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TCKP_SHIFT)) & ESAI_TCCR_TCKP_MASK) +#define ESAI_TCCR_TFSP_MASK (0x80000U) +#define ESAI_TCCR_TFSP_SHIFT (19U) +#define ESAI_TCCR_TFSP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFSP_SHIFT)) & ESAI_TCCR_TFSP_MASK) +#define ESAI_TCCR_THCKP_MASK (0x100000U) +#define ESAI_TCCR_THCKP_SHIFT (20U) +#define ESAI_TCCR_THCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_THCKP_SHIFT)) & ESAI_TCCR_THCKP_MASK) +#define ESAI_TCCR_TCKD_MASK (0x200000U) +#define ESAI_TCCR_TCKD_SHIFT (21U) +#define ESAI_TCCR_TCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TCKD_SHIFT)) & ESAI_TCCR_TCKD_MASK) +#define ESAI_TCCR_TFSD_MASK (0x400000U) +#define ESAI_TCCR_TFSD_SHIFT (22U) +#define ESAI_TCCR_TFSD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFSD_SHIFT)) & ESAI_TCCR_TFSD_MASK) +#define ESAI_TCCR_THCKD_MASK (0x800000U) +#define ESAI_TCCR_THCKD_SHIFT (23U) +#define ESAI_TCCR_THCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_THCKD_SHIFT)) & ESAI_TCCR_THCKD_MASK) + +/*! @name RCR - Receive Control Register */ +#define ESAI_RCR_RE0_MASK (0x1U) +#define ESAI_RCR_RE0_SHIFT (0U) +#define ESAI_RCR_RE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE0_SHIFT)) & ESAI_RCR_RE0_MASK) +#define ESAI_RCR_RE1_MASK (0x2U) +#define ESAI_RCR_RE1_SHIFT (1U) +#define ESAI_RCR_RE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE1_SHIFT)) & ESAI_RCR_RE1_MASK) +#define ESAI_RCR_RE2_MASK (0x4U) +#define ESAI_RCR_RE2_SHIFT (2U) +#define ESAI_RCR_RE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE2_SHIFT)) & ESAI_RCR_RE2_MASK) +#define ESAI_RCR_RE3_MASK (0x8U) +#define ESAI_RCR_RE3_SHIFT (3U) +#define ESAI_RCR_RE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE3_SHIFT)) & ESAI_RCR_RE3_MASK) +#define ESAI_RCR_RSHFD_MASK (0x40U) +#define ESAI_RCR_RSHFD_SHIFT (6U) +#define ESAI_RCR_RSHFD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RSHFD_SHIFT)) & ESAI_RCR_RSHFD_MASK) +#define ESAI_RCR_RWA_MASK (0x80U) +#define ESAI_RCR_RWA_SHIFT (7U) +#define ESAI_RCR_RWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RWA_SHIFT)) & ESAI_RCR_RWA_MASK) +#define ESAI_RCR_RMOD_MASK (0x300U) +#define ESAI_RCR_RMOD_SHIFT (8U) +#define ESAI_RCR_RMOD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RMOD_SHIFT)) & ESAI_RCR_RMOD_MASK) +#define ESAI_RCR_RSWS_MASK (0x7C00U) +#define ESAI_RCR_RSWS_SHIFT (10U) +#define ESAI_RCR_RSWS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RSWS_SHIFT)) & ESAI_RCR_RSWS_MASK) +#define ESAI_RCR_RFSL_MASK (0x8000U) +#define ESAI_RCR_RFSL_SHIFT (15U) +#define ESAI_RCR_RFSL(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RFSL_SHIFT)) & ESAI_RCR_RFSL_MASK) +#define ESAI_RCR_RFSR_MASK (0x10000U) +#define ESAI_RCR_RFSR_SHIFT (16U) +#define ESAI_RCR_RFSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RFSR_SHIFT)) & ESAI_RCR_RFSR_MASK) +#define ESAI_RCR_RPR_MASK (0x80000U) +#define ESAI_RCR_RPR_SHIFT (19U) +#define ESAI_RCR_RPR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RPR_SHIFT)) & ESAI_RCR_RPR_MASK) +#define ESAI_RCR_REIE_MASK (0x100000U) +#define ESAI_RCR_REIE_SHIFT (20U) +#define ESAI_RCR_REIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_REIE_SHIFT)) & ESAI_RCR_REIE_MASK) +#define ESAI_RCR_REDIE_MASK (0x200000U) +#define ESAI_RCR_REDIE_SHIFT (21U) +#define ESAI_RCR_REDIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_REDIE_SHIFT)) & ESAI_RCR_REDIE_MASK) +#define ESAI_RCR_RIE_MASK (0x400000U) +#define ESAI_RCR_RIE_SHIFT (22U) +#define ESAI_RCR_RIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RIE_SHIFT)) & ESAI_RCR_RIE_MASK) +#define ESAI_RCR_RLIE_MASK (0x800000U) +#define ESAI_RCR_RLIE_SHIFT (23U) +#define ESAI_RCR_RLIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RLIE_SHIFT)) & ESAI_RCR_RLIE_MASK) + +/*! @name RCCR - Receive Clock Control Register */ +#define ESAI_RCCR_RPM_MASK (0xFFU) +#define ESAI_RCCR_RPM_SHIFT (0U) +#define ESAI_RCCR_RPM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RPM_SHIFT)) & ESAI_RCCR_RPM_MASK) +#define ESAI_RCCR_RPSR_MASK (0x100U) +#define ESAI_RCCR_RPSR_SHIFT (8U) +#define ESAI_RCCR_RPSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RPSR_SHIFT)) & ESAI_RCCR_RPSR_MASK) +#define ESAI_RCCR_RDC_MASK (0x3E00U) +#define ESAI_RCCR_RDC_SHIFT (9U) +#define ESAI_RCCR_RDC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RDC_SHIFT)) & ESAI_RCCR_RDC_MASK) +#define ESAI_RCCR_RFP_MASK (0x3C000U) +#define ESAI_RCCR_RFP_SHIFT (14U) +#define ESAI_RCCR_RFP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFP_SHIFT)) & ESAI_RCCR_RFP_MASK) +#define ESAI_RCCR_RCKP_MASK (0x40000U) +#define ESAI_RCCR_RCKP_SHIFT (18U) +#define ESAI_RCCR_RCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RCKP_SHIFT)) & ESAI_RCCR_RCKP_MASK) +#define ESAI_RCCR_RFSP_MASK (0x80000U) +#define ESAI_RCCR_RFSP_SHIFT (19U) +#define ESAI_RCCR_RFSP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFSP_SHIFT)) & ESAI_RCCR_RFSP_MASK) +#define ESAI_RCCR_RHCKP_MASK (0x100000U) +#define ESAI_RCCR_RHCKP_SHIFT (20U) +#define ESAI_RCCR_RHCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RHCKP_SHIFT)) & ESAI_RCCR_RHCKP_MASK) +#define ESAI_RCCR_RCKD_MASK (0x200000U) +#define ESAI_RCCR_RCKD_SHIFT (21U) +#define ESAI_RCCR_RCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RCKD_SHIFT)) & ESAI_RCCR_RCKD_MASK) +#define ESAI_RCCR_RFSD_MASK (0x400000U) +#define ESAI_RCCR_RFSD_SHIFT (22U) +#define ESAI_RCCR_RFSD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFSD_SHIFT)) & ESAI_RCCR_RFSD_MASK) +#define ESAI_RCCR_RHCKD_MASK (0x800000U) +#define ESAI_RCCR_RHCKD_SHIFT (23U) +#define ESAI_RCCR_RHCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RHCKD_SHIFT)) & ESAI_RCCR_RHCKD_MASK) + +/*! @name TSMA - Transmit Slot Mask Register A */ +#define ESAI_TSMA_TS_MASK (0xFFFFU) +#define ESAI_TSMA_TS_SHIFT (0U) +#define ESAI_TSMA_TS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TSMA_TS_SHIFT)) & ESAI_TSMA_TS_MASK) + +/*! @name TSMB - Transmit Slot Mask Register B */ +#define ESAI_TSMB_TS_MASK (0xFFFFU) +#define ESAI_TSMB_TS_SHIFT (0U) +#define ESAI_TSMB_TS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TSMB_TS_SHIFT)) & ESAI_TSMB_TS_MASK) + +/*! @name RSMA - Receive Slot Mask Register A */ +#define ESAI_RSMA_RS_MASK (0xFFFFU) +#define ESAI_RSMA_RS_SHIFT (0U) +#define ESAI_RSMA_RS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RSMA_RS_SHIFT)) & ESAI_RSMA_RS_MASK) + +/*! @name RSMB - Receive Slot Mask Register B */ +#define ESAI_RSMB_RS_MASK (0xFFFFU) +#define ESAI_RSMB_RS_SHIFT (0U) +#define ESAI_RSMB_RS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RSMB_RS_SHIFT)) & ESAI_RSMB_RS_MASK) + +/*! @name PRRC - Port C Direction Register */ +#define ESAI_PRRC_PDC_MASK (0xFFFU) +#define ESAI_PRRC_PDC_SHIFT (0U) +#define ESAI_PRRC_PDC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_PRRC_PDC_SHIFT)) & ESAI_PRRC_PDC_MASK) + +/*! @name PCRC - Port C Control Register */ +#define ESAI_PCRC_PC_MASK (0xFFFU) +#define ESAI_PCRC_PC_SHIFT (0U) +#define ESAI_PCRC_PC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_PCRC_PC_SHIFT)) & ESAI_PCRC_PC_MASK) + + +/*! + * @} + */ /* end of group ESAI_Register_Masks */ + + +/* ESAI - Peripheral instance base addresses */ +/** Peripheral ESAI base address */ +#define ESAI_BASE (0x2024000u) +/** Peripheral ESAI base pointer */ +#define ESAI ((ESAI_Type *)ESAI_BASE) +/** Array initializer of ESAI peripheral base addresses */ +#define ESAI_BASE_ADDRS { ESAI_BASE } +/** Array initializer of ESAI peripheral base pointers */ +#define ESAI_BASE_PTRS { ESAI } +/** Interrupt vectors for the ESAI peripheral type */ +#define ESAI_IRQS { ESAI_IRQn } + +/*! + * @} + */ /* end of group ESAI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer + * @{ + */ + +/** GPC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CNTR; /**< GPC Interface control register, offset: 0x0 */ + __IO uint32_t PGR; /**< GPC Power Gating Register, offset: 0x4 */ + __IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register 4, array offset: 0x8, array step: 0x4 */ + __I uint32_t ISR[4]; /**< IRQ status resister 1..IRQ status resister 4, array offset: 0x18, array step: 0x4 */ +} GPC_Type; + +/* ---------------------------------------------------------------------------- + -- GPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Register_Masks GPC Register Masks + * @{ + */ + +/*! @name CNTR - GPC Interface control register */ +#define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U) +#define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U) +#define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK) +#define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U) +#define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U) +#define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK) +#define GPC_CNTR_DISPLAY_PDN_REQ_MASK (0x10U) +#define GPC_CNTR_DISPLAY_PDN_REQ_SHIFT (4U) +#define GPC_CNTR_DISPLAY_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_DISPLAY_PDN_REQ_SHIFT)) & GPC_CNTR_DISPLAY_PDN_REQ_MASK) +#define GPC_CNTR_DISPLAY_PUP_REQ_MASK (0x20U) +#define GPC_CNTR_DISPLAY_PUP_REQ_SHIFT (5U) +#define GPC_CNTR_DISPLAY_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_DISPLAY_PUP_REQ_SHIFT)) & GPC_CNTR_DISPLAY_PUP_REQ_MASK) +#define GPC_CNTR_VADC_ANALOG_OFF_MASK (0x20000U) +#define GPC_CNTR_VADC_ANALOG_OFF_SHIFT (17U) +#define GPC_CNTR_VADC_ANALOG_OFF(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_VADC_ANALOG_OFF_SHIFT)) & GPC_CNTR_VADC_ANALOG_OFF_MASK) +#define GPC_CNTR_VADC_EXT_PWD_N_MASK (0x40000U) +#define GPC_CNTR_VADC_EXT_PWD_N_SHIFT (18U) +#define GPC_CNTR_VADC_EXT_PWD_N(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_VADC_EXT_PWD_N_SHIFT)) & GPC_CNTR_VADC_EXT_PWD_N_MASK) +#define GPC_CNTR_GPCIRQM_MASK (0x200000U) +#define GPC_CNTR_GPCIRQM_SHIFT (21U) +#define GPC_CNTR_GPCIRQM(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_GPCIRQM_SHIFT)) & GPC_CNTR_GPCIRQM_MASK) +#define GPC_CNTR_L2_PGE_MASK (0x400000U) +#define GPC_CNTR_L2_PGE_SHIFT (22U) +#define GPC_CNTR_L2_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_L2_PGE_SHIFT)) & GPC_CNTR_L2_PGE_MASK) + +/*! @name PGR - GPC Power Gating Register */ +#define GPC_PGR_DRCIC_MASK (0x60000000U) +#define GPC_PGR_DRCIC_SHIFT (29U) +#define GPC_PGR_DRCIC(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGR_DRCIC_SHIFT)) & GPC_PGR_DRCIC_MASK) + +/*! @name IMR - IRQ masking register 1..IRQ masking register 4 */ +#define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR1_SHIFT (0U) +#define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK) +#define GPC_IMR_IMR2_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR2_SHIFT (0U) +#define GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK) +#define GPC_IMR_IMR3_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR3_SHIFT (0U) +#define GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK) +#define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR4_SHIFT (0U) +#define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK) + +/* The count of GPC_IMR */ +#define GPC_IMR_COUNT (4U) + +/*! @name ISR - IRQ status resister 1..IRQ status resister 4 */ +#define GPC_ISR_ISR1_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR1_SHIFT (0U) +#define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK) +#define GPC_ISR_ISR2_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR2_SHIFT (0U) +#define GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK) +#define GPC_ISR_ISR3_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR3_SHIFT (0U) +#define GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK) +#define GPC_ISR_ISR4_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR4_SHIFT (0U) +#define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK) + +/* The count of GPC_ISR */ +#define GPC_ISR_COUNT (4U) + + +/*! + * @} + */ /* end of group GPC_Register_Masks */ + + +/* GPC - Peripheral instance base addresses */ +/** Peripheral GPC base address */ +#define GPC_BASE (0x20DC000u) +/** Peripheral GPC base pointer */ +#define GPC ((GPC_Type *)GPC_BASE) +/** Array initializer of GPC peripheral base addresses */ +#define GPC_BASE_ADDRS { GPC_BASE } +/** Array initializer of GPC peripheral base pointers */ +#define GPC_BASE_PTRS { GPC } +/** Interrupt vectors for the GPC peripheral type */ +#define GPC_IRQS { GPC_IRQn } + +/*! + * @} + */ /* end of group GPC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ + __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */ + __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */ + __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */ + __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */ + __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ + __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ + __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name DR - GPIO data register */ +#define GPIO_DR_DR_MASK (0xFFFFFFFFU) +#define GPIO_DR_DR_SHIFT (0U) +#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) + +/*! @name GDIR - GPIO direction register */ +#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) +#define GPIO_GDIR_GDIR_SHIFT (0U) +#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) + +/*! @name PSR - GPIO pad status register */ +#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) +#define GPIO_PSR_PSR_SHIFT (0U) +#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) + +/*! @name ICR1 - GPIO interrupt configuration register1 */ +#define GPIO_ICR1_ICR0_MASK (0x3U) +#define GPIO_ICR1_ICR0_SHIFT (0U) +#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) +#define GPIO_ICR1_ICR1_MASK (0xCU) +#define GPIO_ICR1_ICR1_SHIFT (2U) +#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) +#define GPIO_ICR1_ICR2_MASK (0x30U) +#define GPIO_ICR1_ICR2_SHIFT (4U) +#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) +#define GPIO_ICR1_ICR3_MASK (0xC0U) +#define GPIO_ICR1_ICR3_SHIFT (6U) +#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) +#define GPIO_ICR1_ICR4_MASK (0x300U) +#define GPIO_ICR1_ICR4_SHIFT (8U) +#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) +#define GPIO_ICR1_ICR5_MASK (0xC00U) +#define GPIO_ICR1_ICR5_SHIFT (10U) +#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) +#define GPIO_ICR1_ICR6_MASK (0x3000U) +#define GPIO_ICR1_ICR6_SHIFT (12U) +#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) +#define GPIO_ICR1_ICR7_MASK (0xC000U) +#define GPIO_ICR1_ICR7_SHIFT (14U) +#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) +#define GPIO_ICR1_ICR8_MASK (0x30000U) +#define GPIO_ICR1_ICR8_SHIFT (16U) +#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) +#define GPIO_ICR1_ICR9_MASK (0xC0000U) +#define GPIO_ICR1_ICR9_SHIFT (18U) +#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) +#define GPIO_ICR1_ICR10_MASK (0x300000U) +#define GPIO_ICR1_ICR10_SHIFT (20U) +#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) +#define GPIO_ICR1_ICR11_MASK (0xC00000U) +#define GPIO_ICR1_ICR11_SHIFT (22U) +#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) +#define GPIO_ICR1_ICR12_MASK (0x3000000U) +#define GPIO_ICR1_ICR12_SHIFT (24U) +#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) +#define GPIO_ICR1_ICR13_MASK (0xC000000U) +#define GPIO_ICR1_ICR13_SHIFT (26U) +#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) +#define GPIO_ICR1_ICR14_MASK (0x30000000U) +#define GPIO_ICR1_ICR14_SHIFT (28U) +#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) +#define GPIO_ICR1_ICR15_MASK (0xC0000000U) +#define GPIO_ICR1_ICR15_SHIFT (30U) +#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) + +/*! @name ICR2 - GPIO interrupt configuration register2 */ +#define GPIO_ICR2_ICR16_MASK (0x3U) +#define GPIO_ICR2_ICR16_SHIFT (0U) +#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) +#define GPIO_ICR2_ICR17_MASK (0xCU) +#define GPIO_ICR2_ICR17_SHIFT (2U) +#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) +#define GPIO_ICR2_ICR18_MASK (0x30U) +#define GPIO_ICR2_ICR18_SHIFT (4U) +#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) +#define GPIO_ICR2_ICR19_MASK (0xC0U) +#define GPIO_ICR2_ICR19_SHIFT (6U) +#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) +#define GPIO_ICR2_ICR20_MASK (0x300U) +#define GPIO_ICR2_ICR20_SHIFT (8U) +#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) +#define GPIO_ICR2_ICR21_MASK (0xC00U) +#define GPIO_ICR2_ICR21_SHIFT (10U) +#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) +#define GPIO_ICR2_ICR22_MASK (0x3000U) +#define GPIO_ICR2_ICR22_SHIFT (12U) +#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) +#define GPIO_ICR2_ICR23_MASK (0xC000U) +#define GPIO_ICR2_ICR23_SHIFT (14U) +#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) +#define GPIO_ICR2_ICR24_MASK (0x30000U) +#define GPIO_ICR2_ICR24_SHIFT (16U) +#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) +#define GPIO_ICR2_ICR25_MASK (0xC0000U) +#define GPIO_ICR2_ICR25_SHIFT (18U) +#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) +#define GPIO_ICR2_ICR26_MASK (0x300000U) +#define GPIO_ICR2_ICR26_SHIFT (20U) +#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) +#define GPIO_ICR2_ICR27_MASK (0xC00000U) +#define GPIO_ICR2_ICR27_SHIFT (22U) +#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) +#define GPIO_ICR2_ICR28_MASK (0x3000000U) +#define GPIO_ICR2_ICR28_SHIFT (24U) +#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) +#define GPIO_ICR2_ICR29_MASK (0xC000000U) +#define GPIO_ICR2_ICR29_SHIFT (26U) +#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) +#define GPIO_ICR2_ICR30_MASK (0x30000000U) +#define GPIO_ICR2_ICR30_SHIFT (28U) +#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) +#define GPIO_ICR2_ICR31_MASK (0xC0000000U) +#define GPIO_ICR2_ICR31_SHIFT (30U) +#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) + +/*! @name IMR - GPIO interrupt mask register */ +#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) +#define GPIO_IMR_IMR_SHIFT (0U) +#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) + +/*! @name ISR - GPIO interrupt status register */ +#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) +#define GPIO_ISR_ISR_SHIFT (0U) +#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) + +/*! @name EDGE_SEL - GPIO edge select register */ +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x209C000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x20A0000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x20A4000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x20A8000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Peripheral GPIO5 base address */ +#define GPIO5_BASE (0x20AC000u) +/** Peripheral GPIO5 base pointer */ +#define GPIO5 ((GPIO_Type *)GPIO5_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } +#define GPIO_COMBINED_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_0_15_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_0_15_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_0_15_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_0_15_IRQn, GPIO5_Combined_16_31_IRQn } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPMI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer + * @{ + */ + +/** GPMI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< GPMI Control Register 0 Description, offset: 0x0 */ + __IO uint32_t CTRL0_SET; /**< GPMI Control Register 0 Description, offset: 0x4 */ + __IO uint32_t CTRL0_CLR; /**< GPMI Control Register 0 Description, offset: 0x8 */ + __IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset: 0xC */ + __IO uint32_t COMPARE; /**< GPMI Compare Register Description, offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t ECCCTRL; /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */ + __IO uint32_t ECCCTRL_SET; /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */ + __IO uint32_t ECCCTRL_CLR; /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */ + __IO uint32_t ECCCTRL_TOG; /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */ + __IO uint32_t ECCCOUNT; /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PAYLOAD; /**< GPMI Payload Address Register Description, offset: 0x40 */ + uint8_t RESERVED_2[12]; + __IO uint32_t AUXILIARY; /**< GPMI Auxiliary Address Register Description, offset: 0x50 */ + uint8_t RESERVED_3[12]; + __IO uint32_t CTRL1; /**< GPMI Control Register 1 Description, offset: 0x60 */ + __IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset: 0x64 */ + __IO uint32_t CTRL1_CLR; /**< GPMI Control Register 1 Description, offset: 0x68 */ + __IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset: 0x6C */ + __IO uint32_t TIMING0; /**< GPMI Timing Register 0 Description, offset: 0x70 */ + uint8_t RESERVED_4[12]; + __IO uint32_t TIMING1; /**< GPMI Timing Register 1 Description, offset: 0x80 */ + uint8_t RESERVED_5[12]; + __IO uint32_t TIMING2; /**< GPMI Timing Register 2 Description, offset: 0x90 */ + uint8_t RESERVED_6[12]; + __IO uint32_t DATA; /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */ + uint8_t RESERVED_7[12]; + __I uint32_t STAT; /**< GPMI Status Register Description, offset: 0xB0 */ + uint8_t RESERVED_8[12]; + __I uint32_t DEBUGr; /**< GPMI Debug Information Register Description, offset: 0xC0 */ + uint8_t RESERVED_9[12]; + __I uint32_t VERSION; /**< GPMI Version Register Description, offset: 0xD0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t DEBUG2; /**< GPMI Debug2 Information Register Description, offset: 0xE0 */ + uint8_t RESERVED_11[12]; + __I uint32_t DEBUG3; /**< GPMI Debug3 Information Register Description, offset: 0xF0 */ + uint8_t RESERVED_12[12]; + __IO uint32_t READ_DDR_DLL_CTRL; /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */ + uint8_t RESERVED_13[12]; + __IO uint32_t WRITE_DDR_DLL_CTRL; /**< GPMI Double Rate Write DLL Control Register Description, offset: 0x110 */ + uint8_t RESERVED_14[12]; + __I uint32_t READ_DDR_DLL_STS; /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */ + uint8_t RESERVED_15[12]; + __I uint32_t WRITE_DDR_DLL_STS; /**< GPMI Double Rate Write DLL Status Register Description, offset: 0x130 */ +} GPMI_Type; + +/* ---------------------------------------------------------------------------- + -- GPMI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPMI_Register_Masks GPMI Register Masks + * @{ + */ + +/*! @name CTRL0 - GPMI Control Register 0 Description */ +#define GPMI_CTRL0_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_XFER_COUNT_SHIFT)) & GPMI_CTRL0_XFER_COUNT_MASK) +#define GPMI_CTRL0_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT (16U) +#define GPMI_CTRL0_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_ADDRESS_INCREMENT_MASK) +#define GPMI_CTRL0_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_SHIFT)) & GPMI_CTRL0_ADDRESS_MASK) +#define GPMI_CTRL0_CS_MASK (0x700000U) +#define GPMI_CTRL0_CS_SHIFT (20U) +#define GPMI_CTRL0_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CS_SHIFT)) & GPMI_CTRL0_CS_MASK) +#define GPMI_CTRL0_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_WORD_LENGTH_SHIFT (23U) +#define GPMI_CTRL0_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_WORD_LENGTH_MASK) +#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_COMMAND_MODE_SHIFT (24U) +#define GPMI_CTRL0_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_COMMAND_MODE_MASK) +#define GPMI_CTRL0_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_UDMA_SHIFT (26U) +#define GPMI_CTRL0_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_UDMA_SHIFT)) & GPMI_CTRL0_UDMA_MASK) +#define GPMI_CTRL0_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_LOCK_CS_SHIFT)) & GPMI_CTRL0_LOCK_CS_MASK) +#define GPMI_CTRL0_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_DEV_IRQ_EN_MASK) +#define GPMI_CTRL0_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_RUN_SHIFT (29U) +#define GPMI_CTRL0_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_RUN_SHIFT)) & GPMI_CTRL0_RUN_MASK) +#define GPMI_CTRL0_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLKGATE_SHIFT)) & GPMI_CTRL0_CLKGATE_MASK) +#define GPMI_CTRL0_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SFTRST_SHIFT)) & GPMI_CTRL0_SFTRST_MASK) + +/*! @name CTRL0_SET - GPMI Control Register 0 Description */ +#define GPMI_CTRL0_SET_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_SET_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_SET_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_XFER_COUNT_SHIFT)) & GPMI_CTRL0_SET_XFER_COUNT_MASK) +#define GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT (16U) +#define GPMI_CTRL0_SET_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK) +#define GPMI_CTRL0_SET_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_SET_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_SET_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_MASK) +#define GPMI_CTRL0_SET_CS_MASK (0x700000U) +#define GPMI_CTRL0_SET_CS_SHIFT (20U) +#define GPMI_CTRL0_SET_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CS_SHIFT)) & GPMI_CTRL0_SET_CS_MASK) +#define GPMI_CTRL0_SET_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_SET_WORD_LENGTH_SHIFT (23U) +#define GPMI_CTRL0_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_SET_WORD_LENGTH_MASK) +#define GPMI_CTRL0_SET_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_SET_COMMAND_MODE_SHIFT (24U) +#define GPMI_CTRL0_SET_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_SET_COMMAND_MODE_MASK) +#define GPMI_CTRL0_SET_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_SET_UDMA_SHIFT (26U) +#define GPMI_CTRL0_SET_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_UDMA_SHIFT)) & GPMI_CTRL0_SET_UDMA_MASK) +#define GPMI_CTRL0_SET_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_SET_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_SET_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_LOCK_CS_SHIFT)) & GPMI_CTRL0_SET_LOCK_CS_MASK) +#define GPMI_CTRL0_SET_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_SET_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_SET_DEV_IRQ_EN_MASK) +#define GPMI_CTRL0_SET_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_SET_RUN_SHIFT (29U) +#define GPMI_CTRL0_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_RUN_SHIFT)) & GPMI_CTRL0_SET_RUN_MASK) +#define GPMI_CTRL0_SET_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_SET_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CLKGATE_SHIFT)) & GPMI_CTRL0_SET_CLKGATE_MASK) +#define GPMI_CTRL0_SET_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_SET_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_SFTRST_SHIFT)) & GPMI_CTRL0_SET_SFTRST_MASK) + +/*! @name CTRL0_CLR - GPMI Control Register 0 Description */ +#define GPMI_CTRL0_CLR_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_CLR_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_CLR_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_XFER_COUNT_SHIFT)) & GPMI_CTRL0_CLR_XFER_COUNT_MASK) +#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT (16U) +#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK) +#define GPMI_CTRL0_CLR_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_CLR_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_CLR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_MASK) +#define GPMI_CTRL0_CLR_CS_MASK (0x700000U) +#define GPMI_CTRL0_CLR_CS_SHIFT (20U) +#define GPMI_CTRL0_CLR_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CS_SHIFT)) & GPMI_CTRL0_CLR_CS_MASK) +#define GPMI_CTRL0_CLR_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT (23U) +#define GPMI_CTRL0_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_CLR_WORD_LENGTH_MASK) +#define GPMI_CTRL0_CLR_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT (24U) +#define GPMI_CTRL0_CLR_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_CLR_COMMAND_MODE_MASK) +#define GPMI_CTRL0_CLR_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_CLR_UDMA_SHIFT (26U) +#define GPMI_CTRL0_CLR_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_UDMA_SHIFT)) & GPMI_CTRL0_CLR_UDMA_MASK) +#define GPMI_CTRL0_CLR_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_CLR_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_CLR_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_LOCK_CS_SHIFT)) & GPMI_CTRL0_CLR_LOCK_CS_MASK) +#define GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_CLR_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK) +#define GPMI_CTRL0_CLR_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_CLR_RUN_SHIFT (29U) +#define GPMI_CTRL0_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_RUN_SHIFT)) & GPMI_CTRL0_CLR_RUN_MASK) +#define GPMI_CTRL0_CLR_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_CLR_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CLKGATE_SHIFT)) & GPMI_CTRL0_CLR_CLKGATE_MASK) +#define GPMI_CTRL0_CLR_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_CLR_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_SFTRST_SHIFT)) & GPMI_CTRL0_CLR_SFTRST_MASK) + +/*! @name CTRL0_TOG - GPMI Control Register 0 Description */ +#define GPMI_CTRL0_TOG_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_TOG_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_TOG_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_XFER_COUNT_SHIFT)) & GPMI_CTRL0_TOG_XFER_COUNT_MASK) +#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT (16U) +#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK) +#define GPMI_CTRL0_TOG_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_TOG_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_TOG_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_MASK) +#define GPMI_CTRL0_TOG_CS_MASK (0x700000U) +#define GPMI_CTRL0_TOG_CS_SHIFT (20U) +#define GPMI_CTRL0_TOG_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CS_SHIFT)) & GPMI_CTRL0_TOG_CS_MASK) +#define GPMI_CTRL0_TOG_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT (23U) +#define GPMI_CTRL0_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_TOG_WORD_LENGTH_MASK) +#define GPMI_CTRL0_TOG_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT (24U) +#define GPMI_CTRL0_TOG_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_TOG_COMMAND_MODE_MASK) +#define GPMI_CTRL0_TOG_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_TOG_UDMA_SHIFT (26U) +#define GPMI_CTRL0_TOG_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_UDMA_SHIFT)) & GPMI_CTRL0_TOG_UDMA_MASK) +#define GPMI_CTRL0_TOG_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_TOG_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_TOG_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_LOCK_CS_SHIFT)) & GPMI_CTRL0_TOG_LOCK_CS_MASK) +#define GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_TOG_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK) +#define GPMI_CTRL0_TOG_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_TOG_RUN_SHIFT (29U) +#define GPMI_CTRL0_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_RUN_SHIFT)) & GPMI_CTRL0_TOG_RUN_MASK) +#define GPMI_CTRL0_TOG_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_TOG_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CLKGATE_SHIFT)) & GPMI_CTRL0_TOG_CLKGATE_MASK) +#define GPMI_CTRL0_TOG_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_TOG_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_SFTRST_SHIFT)) & GPMI_CTRL0_TOG_SFTRST_MASK) + +/*! @name COMPARE - GPMI Compare Register Description */ +#define GPMI_COMPARE_REFERENCE_MASK (0xFFFFU) +#define GPMI_COMPARE_REFERENCE_SHIFT (0U) +#define GPMI_COMPARE_REFERENCE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_REFERENCE_SHIFT)) & GPMI_COMPARE_REFERENCE_MASK) +#define GPMI_COMPARE_MASK_MASK (0xFFFF0000U) +#define GPMI_COMPARE_MASK_SHIFT (16U) +#define GPMI_COMPARE_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_MASK_SHIFT)) & GPMI_COMPARE_MASK_MASK) + +/*! @name ECCCTRL - GPMI Integrated ECC Control Register Description */ +#define GPMI_ECCCTRL_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_RSVD1_MASK (0xE00U) +#define GPMI_ECCCTRL_RSVD1_SHIFT (9U) +#define GPMI_ECCCTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD1_SHIFT)) & GPMI_ECCCTRL_RSVD1_MASK) +#define GPMI_ECCCTRL_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_ENABLE_ECC_MASK) +#define GPMI_ECCCTRL_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_ECC_CMD_MASK) +#define GPMI_ECCCTRL_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD2_SHIFT)) & GPMI_ECCCTRL_RSVD2_MASK) +#define GPMI_ECCCTRL_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_HANDLE_SHIFT)) & GPMI_ECCCTRL_HANDLE_MASK) + +/*! @name ECCCTRL_SET - GPMI Integrated ECC Control Register Description */ +#define GPMI_ECCCTRL_SET_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_SET_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_SET_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_SET_RSVD1_MASK (0xE00U) +#define GPMI_ECCCTRL_SET_RSVD1_SHIFT (9U) +#define GPMI_ECCCTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RSVD1_SHIFT)) & GPMI_ECCCTRL_SET_RSVD1_MASK) +#define GPMI_ECCCTRL_SET_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_SET_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_SET_ENABLE_ECC_MASK) +#define GPMI_ECCCTRL_SET_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_SET_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_SET_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_SET_ECC_CMD_MASK) +#define GPMI_ECCCTRL_SET_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_SET_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RSVD2_SHIFT)) & GPMI_ECCCTRL_SET_RSVD2_MASK) +#define GPMI_ECCCTRL_SET_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_SET_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_HANDLE_SHIFT)) & GPMI_ECCCTRL_SET_HANDLE_MASK) + +/*! @name ECCCTRL_CLR - GPMI Integrated ECC Control Register Description */ +#define GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_CLR_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_CLR_RSVD1_MASK (0xE00U) +#define GPMI_ECCCTRL_CLR_RSVD1_SHIFT (9U) +#define GPMI_ECCCTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RSVD1_SHIFT)) & GPMI_ECCCTRL_CLR_RSVD1_MASK) +#define GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_CLR_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK) +#define GPMI_ECCCTRL_CLR_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_CLR_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_CLR_ECC_CMD_MASK) +#define GPMI_ECCCTRL_CLR_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_CLR_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RSVD2_SHIFT)) & GPMI_ECCCTRL_CLR_RSVD2_MASK) +#define GPMI_ECCCTRL_CLR_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_CLR_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_HANDLE_SHIFT)) & GPMI_ECCCTRL_CLR_HANDLE_MASK) + +/*! @name ECCCTRL_TOG - GPMI Integrated ECC Control Register Description */ +#define GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_TOG_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_TOG_RSVD1_MASK (0xE00U) +#define GPMI_ECCCTRL_TOG_RSVD1_SHIFT (9U) +#define GPMI_ECCCTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RSVD1_SHIFT)) & GPMI_ECCCTRL_TOG_RSVD1_MASK) +#define GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_TOG_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK) +#define GPMI_ECCCTRL_TOG_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_TOG_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_TOG_ECC_CMD_MASK) +#define GPMI_ECCCTRL_TOG_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_TOG_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RSVD2_SHIFT)) & GPMI_ECCCTRL_TOG_RSVD2_MASK) +#define GPMI_ECCCTRL_TOG_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_TOG_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_HANDLE_SHIFT)) & GPMI_ECCCTRL_TOG_HANDLE_MASK) + +/*! @name ECCCOUNT - GPMI Integrated ECC Transfer Count Register Description */ +#define GPMI_ECCCOUNT_COUNT_MASK (0xFFFFU) +#define GPMI_ECCCOUNT_COUNT_SHIFT (0U) +#define GPMI_ECCCOUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_COUNT_SHIFT)) & GPMI_ECCCOUNT_COUNT_MASK) +#define GPMI_ECCCOUNT_RSVD2_MASK (0xFFFF0000U) +#define GPMI_ECCCOUNT_RSVD2_SHIFT (16U) +#define GPMI_ECCCOUNT_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_RSVD2_SHIFT)) & GPMI_ECCCOUNT_RSVD2_MASK) + +/*! @name PAYLOAD - GPMI Payload Address Register Description */ +#define GPMI_PAYLOAD_RSVD0_MASK (0x3U) +#define GPMI_PAYLOAD_RSVD0_SHIFT (0U) +#define GPMI_PAYLOAD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_RSVD0_SHIFT)) & GPMI_PAYLOAD_RSVD0_MASK) +#define GPMI_PAYLOAD_ADDRESS_MASK (0xFFFFFFFCU) +#define GPMI_PAYLOAD_ADDRESS_SHIFT (2U) +#define GPMI_PAYLOAD_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_ADDRESS_SHIFT)) & GPMI_PAYLOAD_ADDRESS_MASK) + +/*! @name AUXILIARY - GPMI Auxiliary Address Register Description */ +#define GPMI_AUXILIARY_RSVD0_MASK (0x3U) +#define GPMI_AUXILIARY_RSVD0_SHIFT (0U) +#define GPMI_AUXILIARY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_RSVD0_SHIFT)) & GPMI_AUXILIARY_RSVD0_MASK) +#define GPMI_AUXILIARY_ADDRESS_MASK (0xFFFFFFFCU) +#define GPMI_AUXILIARY_ADDRESS_SHIFT (2U) +#define GPMI_AUXILIARY_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_ADDRESS_SHIFT)) & GPMI_AUXILIARY_ADDRESS_MASK) + +/*! @name CTRL1 - GPMI Control Register 1 Description */ +#define GPMI_CTRL1_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_GPMI_MODE_SHIFT (0U) +#define GPMI_CTRL1_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_MODE_SHIFT)) & GPMI_CTRL1_GPMI_MODE_MASK) +#define GPMI_CTRL1_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CAMERA_MODE_MASK) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT (2U) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK) +#define GPMI_CTRL1_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_DEV_RESET_SHIFT (3U) +#define GPMI_CTRL1_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_RESET_SHIFT)) & GPMI_CTRL1_DEV_RESET_MASK) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK) +#define GPMI_CTRL1_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BURST_EN_SHIFT)) & GPMI_CTRL1_BURST_EN_MASK) +#define GPMI_CTRL1_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_MASK) +#define GPMI_CTRL1_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_IRQ_SHIFT)) & GPMI_CTRL1_DEV_IRQ_MASK) +#define GPMI_CTRL1_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_DMA2ECC_MODE_MASK) +#define GPMI_CTRL1_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RDN_DELAY_SHIFT)) & GPMI_CTRL1_RDN_DELAY_MASK) +#define GPMI_CTRL1_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_HALF_PERIOD_MASK) +#define GPMI_CTRL1_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_DLL_ENABLE_MASK) +#define GPMI_CTRL1_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BCH_MODE_SHIFT)) & GPMI_CTRL1_BCH_MODE_MASK) +#define GPMI_CTRL1_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_GANGED_RDYBUSY_MASK) +#define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK) +#define GPMI_CTRL1_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_TEST_TRIGGER_SHIFT (21U) +#define GPMI_CTRL1_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TEST_TRIGGER_MASK) +#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_DECOUPLE_CS_MASK) +#define GPMI_CTRL1_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SSYNCMODE_MASK) +#define GPMI_CTRL1_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_UPDATE_CS_SHIFT)) & GPMI_CTRL1_UPDATE_CS_MASK) +#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT (27U) +#define GPMI_CTRL1_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK) +#define GPMI_CTRL1_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOGGLE_MODE_MASK) +#define GPMI_CTRL1_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_WRITE_CLK_STOP_MASK) +#define GPMI_CTRL1_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SSYNC_CLK_STOP_MASK) +#define GPMI_CTRL1_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_DEV_CLK_STOP_MASK) + +/*! @name CTRL1_SET - GPMI Control Register 1 Description */ +#define GPMI_CTRL1_SET_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_SET_GPMI_MODE_SHIFT (0U) +#define GPMI_CTRL1_SET_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_MODE_SHIFT)) & GPMI_CTRL1_SET_GPMI_MODE_MASK) +#define GPMI_CTRL1_SET_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_SET_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_SET_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_SET_CAMERA_MODE_MASK) +#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT (2U) +#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK) +#define GPMI_CTRL1_SET_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_SET_DEV_RESET_SHIFT (3U) +#define GPMI_CTRL1_SET_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_RESET_SHIFT)) & GPMI_CTRL1_SET_DEV_RESET_MASK) +#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK) +#define GPMI_CTRL1_SET_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_SET_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_SET_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BURST_EN_SHIFT)) & GPMI_CTRL1_SET_BURST_EN_MASK) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK) +#define GPMI_CTRL1_SET_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_SET_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_SET_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_IRQ_SHIFT)) & GPMI_CTRL1_SET_DEV_IRQ_MASK) +#define GPMI_CTRL1_SET_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_SET_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_SET_DMA2ECC_MODE_MASK) +#define GPMI_CTRL1_SET_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_SET_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_SET_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_RDN_DELAY_SHIFT)) & GPMI_CTRL1_SET_RDN_DELAY_MASK) +#define GPMI_CTRL1_SET_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_SET_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_SET_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_SET_HALF_PERIOD_MASK) +#define GPMI_CTRL1_SET_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_SET_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_SET_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_SET_DLL_ENABLE_MASK) +#define GPMI_CTRL1_SET_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_SET_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_SET_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BCH_MODE_SHIFT)) & GPMI_CTRL1_SET_BCH_MODE_MASK) +#define GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_SET_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK) +#define GPMI_CTRL1_SET_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT (21U) +#define GPMI_CTRL1_SET_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_SET_TEST_TRIGGER_MASK) +#define GPMI_CTRL1_SET_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_SET_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_SET_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_SET_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_SET_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_SET_DECOUPLE_CS_MASK) +#define GPMI_CTRL1_SET_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_SET_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_SET_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SET_SSYNCMODE_MASK) +#define GPMI_CTRL1_SET_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_SET_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_SET_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_UPDATE_CS_SHIFT)) & GPMI_CTRL1_SET_UPDATE_CS_MASK) +#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT (27U) +#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK) +#define GPMI_CTRL1_SET_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_SET_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_SET_TOGGLE_MODE_MASK) +#define GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_SET_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK) +#define GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_SET_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK) +#define GPMI_CTRL1_SET_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_SET_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_DEV_CLK_STOP_MASK) + +/*! @name CTRL1_CLR - GPMI Control Register 1 Description */ +#define GPMI_CTRL1_CLR_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_CLR_GPMI_MODE_SHIFT (0U) +#define GPMI_CTRL1_CLR_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_MODE_SHIFT)) & GPMI_CTRL1_CLR_GPMI_MODE_MASK) +#define GPMI_CTRL1_CLR_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_CLR_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CLR_CAMERA_MODE_MASK) +#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT (2U) +#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK) +#define GPMI_CTRL1_CLR_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_CLR_DEV_RESET_SHIFT (3U) +#define GPMI_CTRL1_CLR_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_RESET_SHIFT)) & GPMI_CTRL1_CLR_DEV_RESET_MASK) +#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK) +#define GPMI_CTRL1_CLR_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_CLR_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_CLR_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BURST_EN_SHIFT)) & GPMI_CTRL1_CLR_BURST_EN_MASK) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK) +#define GPMI_CTRL1_CLR_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_CLR_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_CLR_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_IRQ_SHIFT)) & GPMI_CTRL1_CLR_DEV_IRQ_MASK) +#define GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_CLR_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK) +#define GPMI_CTRL1_CLR_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_CLR_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_CLR_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_RDN_DELAY_SHIFT)) & GPMI_CTRL1_CLR_RDN_DELAY_MASK) +#define GPMI_CTRL1_CLR_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_CLR_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_CLR_HALF_PERIOD_MASK) +#define GPMI_CTRL1_CLR_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_CLR_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_CLR_DLL_ENABLE_MASK) +#define GPMI_CTRL1_CLR_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_CLR_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_CLR_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BCH_MODE_SHIFT)) & GPMI_CTRL1_CLR_BCH_MODE_MASK) +#define GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_CLR_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK) +#define GPMI_CTRL1_CLR_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT (21U) +#define GPMI_CTRL1_CLR_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_CLR_TEST_TRIGGER_MASK) +#define GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_CLR_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_CLR_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_CLR_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_CLR_DECOUPLE_CS_MASK) +#define GPMI_CTRL1_CLR_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_CLR_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_CLR_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNCMODE_SHIFT)) & GPMI_CTRL1_CLR_SSYNCMODE_MASK) +#define GPMI_CTRL1_CLR_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_CLR_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_CLR_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_UPDATE_CS_SHIFT)) & GPMI_CTRL1_CLR_UPDATE_CS_MASK) +#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT (27U) +#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK) +#define GPMI_CTRL1_CLR_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_CLR_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_CLR_TOGGLE_MODE_MASK) +#define GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_CLR_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK) +#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK) +#define GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_CLR_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK) + +/*! @name CTRL1_TOG - GPMI Control Register 1 Description */ +#define GPMI_CTRL1_TOG_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_TOG_GPMI_MODE_SHIFT (0U) +#define GPMI_CTRL1_TOG_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_MODE_SHIFT)) & GPMI_CTRL1_TOG_GPMI_MODE_MASK) +#define GPMI_CTRL1_TOG_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_TOG_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_TOG_CAMERA_MODE_MASK) +#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT (2U) +#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK) +#define GPMI_CTRL1_TOG_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_TOG_DEV_RESET_SHIFT (3U) +#define GPMI_CTRL1_TOG_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_RESET_SHIFT)) & GPMI_CTRL1_TOG_DEV_RESET_MASK) +#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK) +#define GPMI_CTRL1_TOG_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_TOG_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_TOG_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BURST_EN_SHIFT)) & GPMI_CTRL1_TOG_BURST_EN_MASK) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK) +#define GPMI_CTRL1_TOG_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_TOG_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_TOG_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_IRQ_SHIFT)) & GPMI_CTRL1_TOG_DEV_IRQ_MASK) +#define GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_TOG_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK) +#define GPMI_CTRL1_TOG_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_TOG_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_TOG_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_RDN_DELAY_SHIFT)) & GPMI_CTRL1_TOG_RDN_DELAY_MASK) +#define GPMI_CTRL1_TOG_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_TOG_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_TOG_HALF_PERIOD_MASK) +#define GPMI_CTRL1_TOG_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_TOG_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_TOG_DLL_ENABLE_MASK) +#define GPMI_CTRL1_TOG_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_TOG_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_TOG_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BCH_MODE_SHIFT)) & GPMI_CTRL1_TOG_BCH_MODE_MASK) +#define GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_TOG_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK) +#define GPMI_CTRL1_TOG_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT (21U) +#define GPMI_CTRL1_TOG_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TOG_TEST_TRIGGER_MASK) +#define GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_TOG_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_TOG_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_TOG_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_TOG_DECOUPLE_CS_MASK) +#define GPMI_CTRL1_TOG_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_TOG_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_TOG_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNCMODE_SHIFT)) & GPMI_CTRL1_TOG_SSYNCMODE_MASK) +#define GPMI_CTRL1_TOG_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_TOG_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_TOG_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_UPDATE_CS_SHIFT)) & GPMI_CTRL1_TOG_UPDATE_CS_MASK) +#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT (27U) +#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK) +#define GPMI_CTRL1_TOG_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_TOG_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOG_TOGGLE_MODE_MASK) +#define GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_TOG_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK) +#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK) +#define GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_TOG_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK) + +/*! @name TIMING0 - GPMI Timing Register 0 Description */ +#define GPMI_TIMING0_DATA_SETUP_MASK (0xFFU) +#define GPMI_TIMING0_DATA_SETUP_SHIFT (0U) +#define GPMI_TIMING0_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_SETUP_SHIFT)) & GPMI_TIMING0_DATA_SETUP_MASK) +#define GPMI_TIMING0_DATA_HOLD_MASK (0xFF00U) +#define GPMI_TIMING0_DATA_HOLD_SHIFT (8U) +#define GPMI_TIMING0_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_HOLD_SHIFT)) & GPMI_TIMING0_DATA_HOLD_MASK) +#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xFF0000U) +#define GPMI_TIMING0_ADDRESS_SETUP_SHIFT (16U) +#define GPMI_TIMING0_ADDRESS_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_ADDRESS_SETUP_SHIFT)) & GPMI_TIMING0_ADDRESS_SETUP_MASK) +#define GPMI_TIMING0_RSVD1_MASK (0xFF000000U) +#define GPMI_TIMING0_RSVD1_SHIFT (24U) +#define GPMI_TIMING0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_RSVD1_SHIFT)) & GPMI_TIMING0_RSVD1_MASK) + +/*! @name TIMING1 - GPMI Timing Register 1 Description */ +#define GPMI_TIMING1_RSVD1_MASK (0xFFFFU) +#define GPMI_TIMING1_RSVD1_SHIFT (0U) +#define GPMI_TIMING1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_RSVD1_SHIFT)) & GPMI_TIMING1_RSVD1_MASK) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xFFFF0000U) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT (16U) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT)) & GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK) + +/*! @name TIMING2 - GPMI Timing Register 2 Description */ +#define GPMI_TIMING2_DATA_PAUSE_MASK (0xFU) +#define GPMI_TIMING2_DATA_PAUSE_SHIFT (0U) +#define GPMI_TIMING2_DATA_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_DATA_PAUSE_SHIFT)) & GPMI_TIMING2_DATA_PAUSE_MASK) +#define GPMI_TIMING2_CMDADD_PAUSE_MASK (0xF0U) +#define GPMI_TIMING2_CMDADD_PAUSE_SHIFT (4U) +#define GPMI_TIMING2_CMDADD_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CMDADD_PAUSE_SHIFT)) & GPMI_TIMING2_CMDADD_PAUSE_MASK) +#define GPMI_TIMING2_POSTAMBLE_DELAY_MASK (0xF00U) +#define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT (8U) +#define GPMI_TIMING2_POSTAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_POSTAMBLE_DELAY_MASK) +#define GPMI_TIMING2_PREAMBLE_DELAY_MASK (0xF000U) +#define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT (12U) +#define GPMI_TIMING2_PREAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_PREAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_PREAMBLE_DELAY_MASK) +#define GPMI_TIMING2_CE_DELAY_MASK (0x1F0000U) +#define GPMI_TIMING2_CE_DELAY_SHIFT (16U) +#define GPMI_TIMING2_CE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CE_DELAY_SHIFT)) & GPMI_TIMING2_CE_DELAY_MASK) +#define GPMI_TIMING2_RSVD0_MASK (0xE00000U) +#define GPMI_TIMING2_RSVD0_SHIFT (21U) +#define GPMI_TIMING2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_RSVD0_SHIFT)) & GPMI_TIMING2_RSVD0_MASK) +#define GPMI_TIMING2_READ_LATENCY_MASK (0x7000000U) +#define GPMI_TIMING2_READ_LATENCY_SHIFT (24U) +#define GPMI_TIMING2_READ_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_READ_LATENCY_SHIFT)) & GPMI_TIMING2_READ_LATENCY_MASK) +#define GPMI_TIMING2_TCR_MASK (0x18000000U) +#define GPMI_TIMING2_TCR_SHIFT (27U) +#define GPMI_TIMING2_TCR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TCR_SHIFT)) & GPMI_TIMING2_TCR_MASK) +#define GPMI_TIMING2_TRPSTH_MASK (0xE0000000U) +#define GPMI_TIMING2_TRPSTH_SHIFT (29U) +#define GPMI_TIMING2_TRPSTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TRPSTH_SHIFT)) & GPMI_TIMING2_TRPSTH_MASK) + +/*! @name DATA - GPMI DMA Data Transfer Register Description */ +#define GPMI_DATA_DATA_MASK (0xFFFFFFFFU) +#define GPMI_DATA_DATA_SHIFT (0U) +#define GPMI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DATA_DATA_SHIFT)) & GPMI_DATA_DATA_MASK) + +/*! @name STAT - GPMI Status Register Description */ +#define GPMI_STAT_PRESENT_MASK (0x1U) +#define GPMI_STAT_PRESENT_SHIFT (0U) +#define GPMI_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_PRESENT_SHIFT)) & GPMI_STAT_PRESENT_MASK) +#define GPMI_STAT_FIFO_FULL_MASK (0x2U) +#define GPMI_STAT_FIFO_FULL_SHIFT (1U) +#define GPMI_STAT_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_FULL_SHIFT)) & GPMI_STAT_FIFO_FULL_MASK) +#define GPMI_STAT_FIFO_EMPTY_MASK (0x4U) +#define GPMI_STAT_FIFO_EMPTY_SHIFT (2U) +#define GPMI_STAT_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_EMPTY_SHIFT)) & GPMI_STAT_FIFO_EMPTY_MASK) +#define GPMI_STAT_INVALID_BUFFER_MASK_MASK (0x8U) +#define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT (3U) +#define GPMI_STAT_INVALID_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_INVALID_BUFFER_MASK_SHIFT)) & GPMI_STAT_INVALID_BUFFER_MASK_MASK) +#define GPMI_STAT_ATA_IRQ_MASK (0x10U) +#define GPMI_STAT_ATA_IRQ_SHIFT (4U) +#define GPMI_STAT_ATA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_ATA_IRQ_SHIFT)) & GPMI_STAT_ATA_IRQ_MASK) +#define GPMI_STAT_RSVD1_MASK (0xE0U) +#define GPMI_STAT_RSVD1_SHIFT (5U) +#define GPMI_STAT_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RSVD1_SHIFT)) & GPMI_STAT_RSVD1_MASK) +#define GPMI_STAT_DEV0_ERROR_MASK (0x100U) +#define GPMI_STAT_DEV0_ERROR_SHIFT (8U) +#define GPMI_STAT_DEV0_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV0_ERROR_SHIFT)) & GPMI_STAT_DEV0_ERROR_MASK) +#define GPMI_STAT_DEV1_ERROR_MASK (0x200U) +#define GPMI_STAT_DEV1_ERROR_SHIFT (9U) +#define GPMI_STAT_DEV1_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV1_ERROR_SHIFT)) & GPMI_STAT_DEV1_ERROR_MASK) +#define GPMI_STAT_DEV2_ERROR_MASK (0x400U) +#define GPMI_STAT_DEV2_ERROR_SHIFT (10U) +#define GPMI_STAT_DEV2_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV2_ERROR_SHIFT)) & GPMI_STAT_DEV2_ERROR_MASK) +#define GPMI_STAT_DEV3_ERROR_MASK (0x800U) +#define GPMI_STAT_DEV3_ERROR_SHIFT (11U) +#define GPMI_STAT_DEV3_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV3_ERROR_SHIFT)) & GPMI_STAT_DEV3_ERROR_MASK) +#define GPMI_STAT_DEV4_ERROR_MASK (0x1000U) +#define GPMI_STAT_DEV4_ERROR_SHIFT (12U) +#define GPMI_STAT_DEV4_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV4_ERROR_SHIFT)) & GPMI_STAT_DEV4_ERROR_MASK) +#define GPMI_STAT_DEV5_ERROR_MASK (0x2000U) +#define GPMI_STAT_DEV5_ERROR_SHIFT (13U) +#define GPMI_STAT_DEV5_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV5_ERROR_SHIFT)) & GPMI_STAT_DEV5_ERROR_MASK) +#define GPMI_STAT_DEV6_ERROR_MASK (0x4000U) +#define GPMI_STAT_DEV6_ERROR_SHIFT (14U) +#define GPMI_STAT_DEV6_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV6_ERROR_SHIFT)) & GPMI_STAT_DEV6_ERROR_MASK) +#define GPMI_STAT_DEV7_ERROR_MASK (0x8000U) +#define GPMI_STAT_DEV7_ERROR_SHIFT (15U) +#define GPMI_STAT_DEV7_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV7_ERROR_SHIFT)) & GPMI_STAT_DEV7_ERROR_MASK) +#define GPMI_STAT_RDY_TIMEOUT_MASK (0xFF0000U) +#define GPMI_STAT_RDY_TIMEOUT_SHIFT (16U) +#define GPMI_STAT_RDY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RDY_TIMEOUT_SHIFT)) & GPMI_STAT_RDY_TIMEOUT_MASK) +#define GPMI_STAT_READY_BUSY_MASK (0xFF000000U) +#define GPMI_STAT_READY_BUSY_SHIFT (24U) +#define GPMI_STAT_READY_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_READY_BUSY_SHIFT)) & GPMI_STAT_READY_BUSY_MASK) + +/*! @name DEBUG - GPMI Debug Information Register Description */ +#define GPMI_DEBUG_CMD_END_MASK (0xFFU) +#define GPMI_DEBUG_CMD_END_SHIFT (0U) +#define GPMI_DEBUG_CMD_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_CMD_END_SHIFT)) & GPMI_DEBUG_CMD_END_MASK) +#define GPMI_DEBUG_DMAREQ_MASK (0xFF00U) +#define GPMI_DEBUG_DMAREQ_SHIFT (8U) +#define GPMI_DEBUG_DMAREQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMAREQ_SHIFT)) & GPMI_DEBUG_DMAREQ_MASK) +#define GPMI_DEBUG_DMA_SENSE_MASK (0xFF0000U) +#define GPMI_DEBUG_DMA_SENSE_SHIFT (16U) +#define GPMI_DEBUG_DMA_SENSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMA_SENSE_SHIFT)) & GPMI_DEBUG_DMA_SENSE_MASK) +#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xFF000000U) +#define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT (24U) +#define GPMI_DEBUG_WAIT_FOR_READY_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT)) & GPMI_DEBUG_WAIT_FOR_READY_END_MASK) + +/*! @name VERSION - GPMI Version Register Description */ +#define GPMI_VERSION_STEP_MASK (0xFFFFU) +#define GPMI_VERSION_STEP_SHIFT (0U) +#define GPMI_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_STEP_SHIFT)) & GPMI_VERSION_STEP_MASK) +#define GPMI_VERSION_MINOR_MASK (0xFF0000U) +#define GPMI_VERSION_MINOR_SHIFT (16U) +#define GPMI_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MINOR_SHIFT)) & GPMI_VERSION_MINOR_MASK) +#define GPMI_VERSION_MAJOR_MASK (0xFF000000U) +#define GPMI_VERSION_MAJOR_SHIFT (24U) +#define GPMI_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MAJOR_SHIFT)) & GPMI_VERSION_MAJOR_MASK) + +/*! @name DEBUG2 - GPMI Debug2 Information Register Description */ +#define GPMI_DEBUG2_RDN_TAP_MASK (0x3FU) +#define GPMI_DEBUG2_RDN_TAP_SHIFT (0U) +#define GPMI_DEBUG2_RDN_TAP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RDN_TAP_SHIFT)) & GPMI_DEBUG2_RDN_TAP_MASK) +#define GPMI_DEBUG2_UPDATE_WINDOW_MASK (0x40U) +#define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT (6U) +#define GPMI_DEBUG2_UPDATE_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UPDATE_WINDOW_SHIFT)) & GPMI_DEBUG2_UPDATE_WINDOW_MASK) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK (0x80U) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT (7U) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT)) & GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK) +#define GPMI_DEBUG2_SYND2GPMI_READY_MASK (0x100U) +#define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT (8U) +#define GPMI_DEBUG2_SYND2GPMI_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_READY_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_READY_MASK) +#define GPMI_DEBUG2_SYND2GPMI_VALID_MASK (0x200U) +#define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT (9U) +#define GPMI_DEBUG2_SYND2GPMI_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_VALID_MASK) +#define GPMI_DEBUG2_GPMI2SYND_READY_MASK (0x400U) +#define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT (10U) +#define GPMI_DEBUG2_GPMI2SYND_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_READY_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_READY_MASK) +#define GPMI_DEBUG2_GPMI2SYND_VALID_MASK (0x800U) +#define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT (11U) +#define GPMI_DEBUG2_GPMI2SYND_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_VALID_MASK) +#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xF000U) +#define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT (12U) +#define GPMI_DEBUG2_SYND2GPMI_BE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_BE_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_BE_MASK) +#define GPMI_DEBUG2_MAIN_STATE_MASK (0xF0000U) +#define GPMI_DEBUG2_MAIN_STATE_SHIFT (16U) +#define GPMI_DEBUG2_MAIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_MAIN_STATE_SHIFT)) & GPMI_DEBUG2_MAIN_STATE_MASK) +#define GPMI_DEBUG2_PIN_STATE_MASK (0x700000U) +#define GPMI_DEBUG2_PIN_STATE_SHIFT (20U) +#define GPMI_DEBUG2_PIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_PIN_STATE_SHIFT)) & GPMI_DEBUG2_PIN_STATE_MASK) +#define GPMI_DEBUG2_BUSY_MASK (0x800000U) +#define GPMI_DEBUG2_BUSY_SHIFT (23U) +#define GPMI_DEBUG2_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_BUSY_SHIFT)) & GPMI_DEBUG2_BUSY_MASK) +#define GPMI_DEBUG2_UDMA_STATE_MASK (0xF000000U) +#define GPMI_DEBUG2_UDMA_STATE_SHIFT (24U) +#define GPMI_DEBUG2_UDMA_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UDMA_STATE_SHIFT)) & GPMI_DEBUG2_UDMA_STATE_MASK) +#define GPMI_DEBUG2_RSVD1_MASK (0xF0000000U) +#define GPMI_DEBUG2_RSVD1_SHIFT (28U) +#define GPMI_DEBUG2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RSVD1_SHIFT)) & GPMI_DEBUG2_RSVD1_MASK) + +/*! @name DEBUG3 - GPMI Debug3 Information Register Description */ +#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK (0xFFFFU) +#define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT (0U) +#define GPMI_DEBUG3_DEV_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_DEV_WORD_CNTR_MASK) +#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xFFFF0000U) +#define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT (16U) +#define GPMI_DEBUG3_APB_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_APB_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_APB_WORD_CNTR_MASK) + +/*! @name READ_DDR_DLL_CTRL - GPMI Double Rate Read DLL Control Register Description */ +#define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK (0x1U) +#define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT (0U) +#define GPMI_READ_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK) +#define GPMI_READ_DDR_DLL_CTRL_RESET_MASK (0x2U) +#define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT (1U) +#define GPMI_READ_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RESET_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) +#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK) +#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U) +#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U) +#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U) +#define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT (18U) +#define GPMI_READ_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) + +/*! @name WRITE_DDR_DLL_CTRL - GPMI Double Rate Write DLL Control Register Description */ +#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK (0x1U) +#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT (0U) +#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK (0x2U) +#define GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT (1U) +#define GPMI_WRITE_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U) +#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U) +#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U) +#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT (18U) +#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) + +/*! @name READ_DDR_DLL_STS - GPMI Double Rate Read DLL Status Register Description */ +#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK (0x1U) +#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT (0U) +#define GPMI_READ_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK) +#define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU) +#define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT (1U) +#define GPMI_READ_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK) +#define GPMI_READ_DDR_DLL_STS_RSVD0_MASK (0xFE00U) +#define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT (9U) +#define GPMI_READ_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD0_MASK) +#define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK (0x10000U) +#define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT (16U) +#define GPMI_READ_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK) +#define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U) +#define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT (17U) +#define GPMI_READ_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_SEL_MASK) +#define GPMI_READ_DDR_DLL_STS_RSVD1_MASK (0xFE000000U) +#define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT (25U) +#define GPMI_READ_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD1_MASK) + +/*! @name WRITE_DDR_DLL_STS - GPMI Double Rate Write DLL Status Register Description */ +#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK (0x1U) +#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT (0U) +#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK) +#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU) +#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT (1U) +#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK) +#define GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK (0xFE00U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT (9U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK) +#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK (0x10000U) +#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT (16U) +#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK) +#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U) +#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT (17U) +#define GPMI_WRITE_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK) +#define GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK (0xFE000000U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT (25U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK) + + +/*! + * @} + */ /* end of group GPMI_Register_Masks */ + + +/* GPMI - Peripheral instance base addresses */ +/** Peripheral GPMI base address */ +#define GPMI_BASE (0x1806000u) +/** Peripheral GPMI base pointer */ +#define GPMI ((GPMI_Type *)GPMI_BASE) +/** Array initializer of GPMI peripheral base addresses */ +#define GPMI_BASE_ADDRS { GPMI_BASE } +/** Array initializer of GPMI peripheral base pointers */ +#define GPMI_BASE_PTRS { GPMI } +/** Interrupt vectors for the GPMI peripheral type */ +#define GPMI_IRQS { RAWNAND_GPMI_IRQn } + +/*! + * @} + */ /* end of group GPMI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer + * @{ + */ + +/** GPT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */ + __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */ + __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */ + __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */ + __IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */ + __I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */ + __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */ +} GPT_Type; + +/* ---------------------------------------------------------------------------- + -- GPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Register_Masks GPT Register Masks + * @{ + */ + +/*! @name CR - GPT Control Register */ +#define GPT_CR_EN_MASK (0x1U) +#define GPT_CR_EN_SHIFT (0U) +#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) +#define GPT_CR_ENMOD_MASK (0x2U) +#define GPT_CR_ENMOD_SHIFT (1U) +#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) +#define GPT_CR_DBGEN_MASK (0x4U) +#define GPT_CR_DBGEN_SHIFT (2U) +#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) +#define GPT_CR_WAITEN_MASK (0x8U) +#define GPT_CR_WAITEN_SHIFT (3U) +#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) +#define GPT_CR_DOZEEN_MASK (0x10U) +#define GPT_CR_DOZEEN_SHIFT (4U) +#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) +#define GPT_CR_STOPEN_MASK (0x20U) +#define GPT_CR_STOPEN_SHIFT (5U) +#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) +#define GPT_CR_CLKSRC_MASK (0x1C0U) +#define GPT_CR_CLKSRC_SHIFT (6U) +#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) +#define GPT_CR_FRR_MASK (0x200U) +#define GPT_CR_FRR_SHIFT (9U) +#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) +#define GPT_CR_EN_24M_MASK (0x400U) +#define GPT_CR_EN_24M_SHIFT (10U) +#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) +#define GPT_CR_SWR_MASK (0x8000U) +#define GPT_CR_SWR_SHIFT (15U) +#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) +#define GPT_CR_IM1_MASK (0x30000U) +#define GPT_CR_IM1_SHIFT (16U) +#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) +#define GPT_CR_IM2_MASK (0xC0000U) +#define GPT_CR_IM2_SHIFT (18U) +#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) +#define GPT_CR_OM1_MASK (0x700000U) +#define GPT_CR_OM1_SHIFT (20U) +#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) +#define GPT_CR_OM2_MASK (0x3800000U) +#define GPT_CR_OM2_SHIFT (23U) +#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) +#define GPT_CR_OM3_MASK (0x1C000000U) +#define GPT_CR_OM3_SHIFT (26U) +#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) +#define GPT_CR_FO1_MASK (0x20000000U) +#define GPT_CR_FO1_SHIFT (29U) +#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) +#define GPT_CR_FO2_MASK (0x40000000U) +#define GPT_CR_FO2_SHIFT (30U) +#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) +#define GPT_CR_FO3_MASK (0x80000000U) +#define GPT_CR_FO3_SHIFT (31U) +#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) + +/*! @name PR - GPT Prescaler Register */ +#define GPT_PR_PRESCALER_MASK (0xFFFU) +#define GPT_PR_PRESCALER_SHIFT (0U) +#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) +#define GPT_PR_PRESCALER24M_MASK (0xF000U) +#define GPT_PR_PRESCALER24M_SHIFT (12U) +#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) + +/*! @name SR - GPT Status Register */ +#define GPT_SR_OF1_MASK (0x1U) +#define GPT_SR_OF1_SHIFT (0U) +#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) +#define GPT_SR_OF2_MASK (0x2U) +#define GPT_SR_OF2_SHIFT (1U) +#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) +#define GPT_SR_OF3_MASK (0x4U) +#define GPT_SR_OF3_SHIFT (2U) +#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) +#define GPT_SR_IF1_MASK (0x8U) +#define GPT_SR_IF1_SHIFT (3U) +#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) +#define GPT_SR_IF2_MASK (0x10U) +#define GPT_SR_IF2_SHIFT (4U) +#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) +#define GPT_SR_ROV_MASK (0x20U) +#define GPT_SR_ROV_SHIFT (5U) +#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) + +/*! @name IR - GPT Interrupt Register */ +#define GPT_IR_OF1IE_MASK (0x1U) +#define GPT_IR_OF1IE_SHIFT (0U) +#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) +#define GPT_IR_OF2IE_MASK (0x2U) +#define GPT_IR_OF2IE_SHIFT (1U) +#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) +#define GPT_IR_OF3IE_MASK (0x4U) +#define GPT_IR_OF3IE_SHIFT (2U) +#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) +#define GPT_IR_IF1IE_MASK (0x8U) +#define GPT_IR_IF1IE_SHIFT (3U) +#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) +#define GPT_IR_IF2IE_MASK (0x10U) +#define GPT_IR_IF2IE_SHIFT (4U) +#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) +#define GPT_IR_ROVIE_MASK (0x20U) +#define GPT_IR_ROVIE_SHIFT (5U) +#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) + +/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */ +#define GPT_OCR_COMP_MASK (0xFFFFFFFFU) +#define GPT_OCR_COMP_SHIFT (0U) +#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) + +/* The count of GPT_OCR */ +#define GPT_OCR_COUNT (3U) + +/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */ +#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) +#define GPT_ICR_CAPT_SHIFT (0U) +#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) + +/* The count of GPT_ICR */ +#define GPT_ICR_COUNT (2U) + +/*! @name CNT - GPT Counter Register */ +#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) +#define GPT_CNT_COUNT_SHIFT (0U) +#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) + + +/*! + * @} + */ /* end of group GPT_Register_Masks */ + + +/* GPT - Peripheral instance base addresses */ +/** Peripheral GPT1 base address */ +#define GPT1_BASE (0x2098000u) +/** Peripheral GPT1 base pointer */ +#define GPT1 ((GPT_Type *)GPT1_BASE) +/** Peripheral GPT2 base address */ +#define GPT2_BASE (0x20E8000u) +/** Peripheral GPT2 base pointer */ +#define GPT2 ((GPT_Type *)GPT2_BASE) +/** Array initializer of GPT peripheral base addresses */ +#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE } +/** Array initializer of GPT peripheral base pointers */ +#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 } +/** Interrupt vectors for the GPT peripheral type */ +#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn } + +/*! + * @} + */ /* end of group GPT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + __IO uint16_t IADR; /**< I2C Address Register, offset: 0x0 */ + uint8_t RESERVED_0[2]; + __IO uint16_t IFDR; /**< I2C Frequency Divider Register, offset: 0x4 */ + uint8_t RESERVED_1[2]; + __IO uint16_t I2CR; /**< I2C Control Register, offset: 0x8 */ + uint8_t RESERVED_2[2]; + __IO uint16_t I2SR; /**< I2C Status Register, offset: 0xC */ + uint8_t RESERVED_3[2]; + __IO uint16_t I2DR; /**< I2C Data I/O Register, offset: 0x10 */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name IADR - I2C Address Register */ +#define I2C_IADR_ADR_MASK (0xFEU) +#define I2C_IADR_ADR_SHIFT (1U) +#define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x)) << I2C_IADR_ADR_SHIFT)) & I2C_IADR_ADR_MASK) + +/*! @name IFDR - I2C Frequency Divider Register */ +#define I2C_IFDR_IC_MASK (0x3FU) +#define I2C_IFDR_IC_SHIFT (0U) +#define I2C_IFDR_IC(x) (((uint16_t)(((uint16_t)(x)) << I2C_IFDR_IC_SHIFT)) & I2C_IFDR_IC_MASK) + +/*! @name I2CR - I2C Control Register */ +#define I2C_I2CR_RSTA_MASK (0x4U) +#define I2C_I2CR_RSTA_SHIFT (2U) +#define I2C_I2CR_RSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_RSTA_SHIFT)) & I2C_I2CR_RSTA_MASK) +#define I2C_I2CR_TXAK_MASK (0x8U) +#define I2C_I2CR_TXAK_SHIFT (3U) +#define I2C_I2CR_TXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_TXAK_SHIFT)) & I2C_I2CR_TXAK_MASK) +#define I2C_I2CR_MTX_MASK (0x10U) +#define I2C_I2CR_MTX_SHIFT (4U) +#define I2C_I2CR_MTX(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MTX_SHIFT)) & I2C_I2CR_MTX_MASK) +#define I2C_I2CR_MSTA_MASK (0x20U) +#define I2C_I2CR_MSTA_SHIFT (5U) +#define I2C_I2CR_MSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MSTA_SHIFT)) & I2C_I2CR_MSTA_MASK) +#define I2C_I2CR_IIEN_MASK (0x40U) +#define I2C_I2CR_IIEN_SHIFT (6U) +#define I2C_I2CR_IIEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IIEN_SHIFT)) & I2C_I2CR_IIEN_MASK) +#define I2C_I2CR_IEN_MASK (0x80U) +#define I2C_I2CR_IEN_SHIFT (7U) +#define I2C_I2CR_IEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IEN_SHIFT)) & I2C_I2CR_IEN_MASK) + +/*! @name I2SR - I2C Status Register */ +#define I2C_I2SR_RXAK_MASK (0x1U) +#define I2C_I2SR_RXAK_SHIFT (0U) +#define I2C_I2SR_RXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_RXAK_SHIFT)) & I2C_I2SR_RXAK_MASK) +#define I2C_I2SR_IIF_MASK (0x2U) +#define I2C_I2SR_IIF_SHIFT (1U) +#define I2C_I2SR_IIF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IIF_SHIFT)) & I2C_I2SR_IIF_MASK) +#define I2C_I2SR_SRW_MASK (0x4U) +#define I2C_I2SR_SRW_SHIFT (2U) +#define I2C_I2SR_SRW(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_SRW_SHIFT)) & I2C_I2SR_SRW_MASK) +#define I2C_I2SR_IAL_MASK (0x10U) +#define I2C_I2SR_IAL_SHIFT (4U) +#define I2C_I2SR_IAL(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAL_SHIFT)) & I2C_I2SR_IAL_MASK) +#define I2C_I2SR_IBB_MASK (0x20U) +#define I2C_I2SR_IBB_SHIFT (5U) +#define I2C_I2SR_IBB(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IBB_SHIFT)) & I2C_I2SR_IBB_MASK) +#define I2C_I2SR_IAAS_MASK (0x40U) +#define I2C_I2SR_IAAS_SHIFT (6U) +#define I2C_I2SR_IAAS(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAAS_SHIFT)) & I2C_I2SR_IAAS_MASK) +#define I2C_I2SR_ICF_MASK (0x80U) +#define I2C_I2SR_ICF_SHIFT (7U) +#define I2C_I2SR_ICF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_ICF_SHIFT)) & I2C_I2SR_ICF_MASK) + +/*! @name I2DR - I2C Data I/O Register */ +#define I2C_I2DR_DATA_MASK (0xFFU) +#define I2C_I2DR_DATA_SHIFT (0U) +#define I2C_I2DR_DATA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2DR_DATA_SHIFT)) & I2C_I2DR_DATA_MASK) + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +/** Peripheral I2C1 base address */ +#define I2C1_BASE (0x21A0000u) +/** Peripheral I2C1 base pointer */ +#define I2C1 ((I2C_Type *)I2C1_BASE) +/** Peripheral I2C2 base address */ +#define I2C2_BASE (0x21A4000u) +/** Peripheral I2C2 base pointer */ +#define I2C2 ((I2C_Type *)I2C2_BASE) +/** Peripheral I2C3 base address */ +#define I2C3_BASE (0x21A8000u) +/** Peripheral I2C3 base pointer */ +#define I2C3 ((I2C_Type *)I2C3_BASE) +/** Peripheral I2C4 base address */ +#define I2C4_BASE (0x21F8000u) +/** Peripheral I2C4 base pointer */ +#define I2C4 ((I2C_Type *)I2C4_BASE) +/** Array initializer of I2C peripheral base addresses */ +#define I2C_BASE_ADDRS { 0u, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE } +/** Array initializer of I2C peripheral base pointers */ +#define I2C_BASE_PTRS { (I2C_Type *)0u, I2C1, I2C2, I2C3, I2C4 } +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { NotAvail_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn, I2C4_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ + __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ + __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ + __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ + __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ + __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ + uint8_t RESERVED_0[8]; + __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[28]; + __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_2[28]; + __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ + uint8_t RESERVED_3[28]; + __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ + __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ + __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ + __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ + __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ + __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ + uint8_t RESERVED_4[8]; + __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_5[28]; + __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_6[28]; + __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name TCSR - SAI Transmit Control Register */ +#define I2S_TCSR_FRDE_MASK (0x1U) +#define I2S_TCSR_FRDE_SHIFT (0U) +#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) +#define I2S_TCSR_FWDE_MASK (0x2U) +#define I2S_TCSR_FWDE_SHIFT (1U) +#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) +#define I2S_TCSR_FRIE_MASK (0x100U) +#define I2S_TCSR_FRIE_SHIFT (8U) +#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) +#define I2S_TCSR_FWIE_MASK (0x200U) +#define I2S_TCSR_FWIE_SHIFT (9U) +#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) +#define I2S_TCSR_FEIE_MASK (0x400U) +#define I2S_TCSR_FEIE_SHIFT (10U) +#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) +#define I2S_TCSR_SEIE_MASK (0x800U) +#define I2S_TCSR_SEIE_SHIFT (11U) +#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) +#define I2S_TCSR_WSIE_MASK (0x1000U) +#define I2S_TCSR_WSIE_SHIFT (12U) +#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) +#define I2S_TCSR_FRF_MASK (0x10000U) +#define I2S_TCSR_FRF_SHIFT (16U) +#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) +#define I2S_TCSR_FWF_MASK (0x20000U) +#define I2S_TCSR_FWF_SHIFT (17U) +#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) +#define I2S_TCSR_FEF_MASK (0x40000U) +#define I2S_TCSR_FEF_SHIFT (18U) +#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) +#define I2S_TCSR_SEF_MASK (0x80000U) +#define I2S_TCSR_SEF_SHIFT (19U) +#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) +#define I2S_TCSR_WSF_MASK (0x100000U) +#define I2S_TCSR_WSF_SHIFT (20U) +#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) +#define I2S_TCSR_SR_MASK (0x1000000U) +#define I2S_TCSR_SR_SHIFT (24U) +#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) +#define I2S_TCSR_FR_MASK (0x2000000U) +#define I2S_TCSR_FR_SHIFT (25U) +#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) +#define I2S_TCSR_BCE_MASK (0x10000000U) +#define I2S_TCSR_BCE_SHIFT (28U) +#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) +#define I2S_TCSR_STOPE_MASK (0x40000000U) +#define I2S_TCSR_STOPE_SHIFT (30U) +#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) +#define I2S_TCSR_TE_MASK (0x80000000U) +#define I2S_TCSR_TE_SHIFT (31U) +#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) + +/*! @name TCR1 - SAI Transmit Configuration 1 Register */ +#define I2S_TCR1_TFW_MASK (0x1FU) +#define I2S_TCR1_TFW_SHIFT (0U) +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) + +/*! @name TCR2 - SAI Transmit Configuration 2 Register */ +#define I2S_TCR2_DIV_MASK (0xFFU) +#define I2S_TCR2_DIV_SHIFT (0U) +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) +#define I2S_TCR2_BCD_MASK (0x1000000U) +#define I2S_TCR2_BCD_SHIFT (24U) +#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) +#define I2S_TCR2_BCP_MASK (0x2000000U) +#define I2S_TCR2_BCP_SHIFT (25U) +#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) +#define I2S_TCR2_MSEL_MASK (0xC000000U) +#define I2S_TCR2_MSEL_SHIFT (26U) +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) +#define I2S_TCR2_BCI_MASK (0x10000000U) +#define I2S_TCR2_BCI_SHIFT (28U) +#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) +#define I2S_TCR2_BCS_MASK (0x20000000U) +#define I2S_TCR2_BCS_SHIFT (29U) +#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) +#define I2S_TCR2_SYNC_MASK (0xC0000000U) +#define I2S_TCR2_SYNC_SHIFT (30U) +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) + +/*! @name TCR3 - SAI Transmit Configuration 3 Register */ +#define I2S_TCR3_WDFL_MASK (0x1FU) +#define I2S_TCR3_WDFL_SHIFT (0U) +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) +#define I2S_TCR3_TCE_MASK (0x10000U) +#define I2S_TCR3_TCE_SHIFT (16U) +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) + +/*! @name TCR4 - SAI Transmit Configuration 4 Register */ +#define I2S_TCR4_FSD_MASK (0x1U) +#define I2S_TCR4_FSD_SHIFT (0U) +#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) +#define I2S_TCR4_FSP_MASK (0x2U) +#define I2S_TCR4_FSP_SHIFT (1U) +#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) +#define I2S_TCR4_FSE_MASK (0x8U) +#define I2S_TCR4_FSE_SHIFT (3U) +#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) +#define I2S_TCR4_MF_MASK (0x10U) +#define I2S_TCR4_MF_SHIFT (4U) +#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) +#define I2S_TCR4_SYWD_MASK (0x1F00U) +#define I2S_TCR4_SYWD_SHIFT (8U) +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) +#define I2S_TCR4_FRSZ_MASK (0x1F0000U) +#define I2S_TCR4_FRSZ_SHIFT (16U) +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) + +/*! @name TCR5 - SAI Transmit Configuration 5 Register */ +#define I2S_TCR5_FBT_MASK (0x1F00U) +#define I2S_TCR5_FBT_SHIFT (8U) +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) +#define I2S_TCR5_W0W_MASK (0x1F0000U) +#define I2S_TCR5_W0W_SHIFT (16U) +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) +#define I2S_TCR5_WNW_MASK (0x1F000000U) +#define I2S_TCR5_WNW_SHIFT (24U) +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) + +/*! @name TDR - SAI Transmit Data Register */ +#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) +#define I2S_TDR_TDR_SHIFT (0U) +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) + +/* The count of I2S_TDR */ +#define I2S_TDR_COUNT (1U) + +/*! @name TFR - SAI Transmit FIFO Register */ +#define I2S_TFR_RFP_MASK (0x3FU) +#define I2S_TFR_RFP_SHIFT (0U) +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) +#define I2S_TFR_WFP_MASK (0x3F0000U) +#define I2S_TFR_WFP_SHIFT (16U) +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) + +/* The count of I2S_TFR */ +#define I2S_TFR_COUNT (1U) + +/*! @name TMR - SAI Transmit Mask Register */ +#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) +#define I2S_TMR_TWM_SHIFT (0U) +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) + +/*! @name RCSR - SAI Receive Control Register */ +#define I2S_RCSR_FRDE_MASK (0x1U) +#define I2S_RCSR_FRDE_SHIFT (0U) +#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) +#define I2S_RCSR_FWDE_MASK (0x2U) +#define I2S_RCSR_FWDE_SHIFT (1U) +#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) +#define I2S_RCSR_FRIE_MASK (0x100U) +#define I2S_RCSR_FRIE_SHIFT (8U) +#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) +#define I2S_RCSR_FWIE_MASK (0x200U) +#define I2S_RCSR_FWIE_SHIFT (9U) +#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) +#define I2S_RCSR_FEIE_MASK (0x400U) +#define I2S_RCSR_FEIE_SHIFT (10U) +#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) +#define I2S_RCSR_SEIE_MASK (0x800U) +#define I2S_RCSR_SEIE_SHIFT (11U) +#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) +#define I2S_RCSR_WSIE_MASK (0x1000U) +#define I2S_RCSR_WSIE_SHIFT (12U) +#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) +#define I2S_RCSR_FRF_MASK (0x10000U) +#define I2S_RCSR_FRF_SHIFT (16U) +#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) +#define I2S_RCSR_FWF_MASK (0x20000U) +#define I2S_RCSR_FWF_SHIFT (17U) +#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) +#define I2S_RCSR_FEF_MASK (0x40000U) +#define I2S_RCSR_FEF_SHIFT (18U) +#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) +#define I2S_RCSR_SEF_MASK (0x80000U) +#define I2S_RCSR_SEF_SHIFT (19U) +#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) +#define I2S_RCSR_WSF_MASK (0x100000U) +#define I2S_RCSR_WSF_SHIFT (20U) +#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) +#define I2S_RCSR_SR_MASK (0x1000000U) +#define I2S_RCSR_SR_SHIFT (24U) +#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) +#define I2S_RCSR_FR_MASK (0x2000000U) +#define I2S_RCSR_FR_SHIFT (25U) +#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) +#define I2S_RCSR_BCE_MASK (0x10000000U) +#define I2S_RCSR_BCE_SHIFT (28U) +#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) +#define I2S_RCSR_STOPE_MASK (0x40000000U) +#define I2S_RCSR_STOPE_SHIFT (30U) +#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) +#define I2S_RCSR_RE_MASK (0x80000000U) +#define I2S_RCSR_RE_SHIFT (31U) +#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) + +/*! @name RCR1 - SAI Receive Configuration 1 Register */ +#define I2S_RCR1_RFW_MASK (0x1FU) +#define I2S_RCR1_RFW_SHIFT (0U) +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) + +/*! @name RCR2 - SAI Receive Configuration 2 Register */ +#define I2S_RCR2_DIV_MASK (0xFFU) +#define I2S_RCR2_DIV_SHIFT (0U) +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) +#define I2S_RCR2_BCD_MASK (0x1000000U) +#define I2S_RCR2_BCD_SHIFT (24U) +#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) +#define I2S_RCR2_BCP_MASK (0x2000000U) +#define I2S_RCR2_BCP_SHIFT (25U) +#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) +#define I2S_RCR2_MSEL_MASK (0xC000000U) +#define I2S_RCR2_MSEL_SHIFT (26U) +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) +#define I2S_RCR2_BCI_MASK (0x10000000U) +#define I2S_RCR2_BCI_SHIFT (28U) +#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) +#define I2S_RCR2_BCS_MASK (0x20000000U) +#define I2S_RCR2_BCS_SHIFT (29U) +#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) +#define I2S_RCR2_SYNC_MASK (0xC0000000U) +#define I2S_RCR2_SYNC_SHIFT (30U) +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) + +/*! @name RCR3 - SAI Receive Configuration 3 Register */ +#define I2S_RCR3_WDFL_MASK (0x1FU) +#define I2S_RCR3_WDFL_SHIFT (0U) +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) +#define I2S_RCR3_RCE_MASK (0x10000U) +#define I2S_RCR3_RCE_SHIFT (16U) +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) + +/*! @name RCR4 - SAI Receive Configuration 4 Register */ +#define I2S_RCR4_FSD_MASK (0x1U) +#define I2S_RCR4_FSD_SHIFT (0U) +#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) +#define I2S_RCR4_FSP_MASK (0x2U) +#define I2S_RCR4_FSP_SHIFT (1U) +#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) +#define I2S_RCR4_FSE_MASK (0x8U) +#define I2S_RCR4_FSE_SHIFT (3U) +#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) +#define I2S_RCR4_MF_MASK (0x10U) +#define I2S_RCR4_MF_SHIFT (4U) +#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) +#define I2S_RCR4_SYWD_MASK (0x1F00U) +#define I2S_RCR4_SYWD_SHIFT (8U) +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) +#define I2S_RCR4_FRSZ_MASK (0x1F0000U) +#define I2S_RCR4_FRSZ_SHIFT (16U) +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) + +/*! @name RCR5 - SAI Receive Configuration 5 Register */ +#define I2S_RCR5_FBT_MASK (0x1F00U) +#define I2S_RCR5_FBT_SHIFT (8U) +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) +#define I2S_RCR5_W0W_MASK (0x1F0000U) +#define I2S_RCR5_W0W_SHIFT (16U) +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) +#define I2S_RCR5_WNW_MASK (0x1F000000U) +#define I2S_RCR5_WNW_SHIFT (24U) +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) + +/*! @name RDR - SAI Receive Data Register */ +#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) +#define I2S_RDR_RDR_SHIFT (0U) +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) + +/* The count of I2S_RDR */ +#define I2S_RDR_COUNT (1U) + +/*! @name RFR - SAI Receive FIFO Register */ +#define I2S_RFR_RFP_MASK (0x3FU) +#define I2S_RFR_RFP_SHIFT (0U) +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) +#define I2S_RFR_WFP_MASK (0x3F0000U) +#define I2S_RFR_WFP_SHIFT (16U) +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) + +/* The count of I2S_RFR */ +#define I2S_RFR_COUNT (1U) + +/*! @name RMR - SAI Receive Mask Register */ +#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) +#define I2S_RMR_RWM_SHIFT (0U) +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral I2S1 base address */ +#define I2S1_BASE (0x2028000u) +/** Peripheral I2S1 base pointer */ +#define I2S1 ((I2S_Type *)I2S1_BASE) +/** Peripheral I2S2 base address */ +#define I2S2_BASE (0x202C000u) +/** Peripheral I2S2 base pointer */ +#define I2S2 ((I2S_Type *)I2S2_BASE) +/** Peripheral I2S3 base address */ +#define I2S3_BASE (0x2030000u) +/** Peripheral I2S3 base pointer */ +#define I2S3 ((I2S_Type *)I2S3_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { 0u, I2S1_BASE, I2S2_BASE, I2S3_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { (I2S_Type *)0u, I2S1, I2S2, I2S3 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn } +#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer + * @{ + */ + +/** IOMUXC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[68]; + __IO uint32_t SW_MUX_CTL_PAD[112]; /**< SW_MUX_CTL_PAD_JTAG_MOD SW MUX Control Register..SW_MUX_CTL_PAD_CSI_DATA07 SW MUX Control Register, array offset: 0x44, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_PAD_DDR[34]; /**< SW_PAD_CTL_PAD_DRAM_ADDR00 SW PAD Control Register..SW_PAD_CTL_PAD_DRAM_RESET SW PAD Control Register, array offset: 0x204, array step: 0x4 */ + uint8_t RESERVED_1[68]; + __IO uint32_t SW_PAD_CTL_PAD[112]; /**< SW_PAD_CTL_PAD_JTAG_MOD SW PAD Control Register..SW_PAD_CTL_PAD_CSI_DATA07 SW PAD Control Register, array offset: 0x2D0, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_GRP[10]; /**< SW_PAD_CTL_GRP_ADDDS SW GRP Register..SW_PAD_CTL_GRP_DDR_TYPE SW GRP Register, array offset: 0x490, array step: 0x4 */ + __IO uint32_t SELECT_INPUT[122]; /**< USB_OTG1_ID_SELECT_INPUT DAISY Register..USDHC2_WP_SELECT_INPUT DAISY Register, array offset: 0x4B8, array step: 0x4 */ +} IOMUXC_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_JTAG_MOD SW MUX Control Register..SW_MUX_CTL_PAD_CSI_DATA07 SW MUX Control Register */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) +#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) +#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) + +/* The count of IOMUXC_SW_MUX_CTL_PAD */ +#define IOMUXC_SW_MUX_CTL_PAD_COUNT (112U) + +/*! @name SW_PAD_CTL_PAD_DDR - SW_PAD_CTL_PAD_DRAM_ADDR00 SW PAD Control Register..SW_PAD_CTL_PAD_DRAM_RESET SW PAD Control Register */ +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DSE_SHIFT (3U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_ODT_MASK (0x700U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_ODT_SHIFT (8U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_ODT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_ODT_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_ODT_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PKE_SHIFT (12U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_PKE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUE_SHIFT (13U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_PUE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUS_MASK (0xC000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUS_SHIFT (14U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_PUS_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_HYS_SHIFT (16U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_HYS_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT_MASK (0x20000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT_SHIFT (17U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL_MASK (0xC0000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL_SHIFT (18U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_MASK (0x300000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_SHIFT (20U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN_MASK (0x3000000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN_SHIFT (24U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN_MASK) + +/* The count of IOMUXC_SW_PAD_CTL_PAD_DDR */ +#define IOMUXC_SW_PAD_CTL_PAD_DDR_COUNT (34U) + +/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_JTAG_MOD SW PAD Control Register..SW_PAD_CTL_PAD_CSI_DATA07 SW PAD Control Register */ +#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U) +#define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U) +#define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U) +#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U) +#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U) +#define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U) +#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U) +#define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U) +#define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U) +#define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK) + +/* The count of IOMUXC_SW_PAD_CTL_PAD */ +#define IOMUXC_SW_PAD_CTL_PAD_COUNT (112U) + +/*! @name SW_PAD_CTL_GRP - SW_PAD_CTL_GRP_ADDDS SW GRP Register..SW_PAD_CTL_GRP_DDR_TYPE SW GRP Register */ +#define IOMUXC_SW_PAD_CTL_GRP_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_GRP_DSE_SHIFT (3U) +#define IOMUXC_SW_PAD_CTL_GRP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_GRP_PKE_SHIFT (12U) +#define IOMUXC_SW_PAD_CTL_GRP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_PKE_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_GRP_PUE_SHIFT (13U) +#define IOMUXC_SW_PAD_CTL_GRP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_PUE_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_GRP_HYS_SHIFT (16U) +#define IOMUXC_SW_PAD_CTL_GRP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_HYS_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT_MASK (0x20000U) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT_SHIFT (17U) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_SEL_MASK (0xC0000U) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_SEL_SHIFT (18U) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_DDR_SEL_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_DDR_SEL_MASK) + +/* The count of IOMUXC_SW_PAD_CTL_GRP */ +#define IOMUXC_SW_PAD_CTL_GRP_COUNT (10U) + +/*! @name SELECT_INPUT - USB_OTG1_ID_SELECT_INPUT DAISY Register..USDHC2_WP_SELECT_INPUT DAISY Register */ +#define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ +#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) +#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ + +/* The count of IOMUXC_SELECT_INPUT */ +#define IOMUXC_SELECT_INPUT_COUNT (122U) + + +/*! + * @} + */ /* end of group IOMUXC_Register_Masks */ + + +/* IOMUXC - Peripheral instance base addresses */ +/** Peripheral IOMUXC base address */ +#define IOMUXC_BASE (0x20E0000u) +/** Peripheral IOMUXC base pointer */ +#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) +/** Array initializer of IOMUXC peripheral base addresses */ +#define IOMUXC_BASE_ADDRS { IOMUXC_BASE } +/** Array initializer of IOMUXC peripheral base pointers */ +#define IOMUXC_BASE_PTRS { IOMUXC } + +/*! + * @} + */ /* end of group IOMUXC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_GPR - Register Layout Typedef */ +typedef struct { + __IO uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ + __IO uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ + __IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ + __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ + __IO uint32_t GPR4; /**< GPR4 General Purpose Register, offset: 0x10 */ + __IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 */ + uint8_t RESERVED_0[12]; + __I uint32_t GPR9; /**< GPR9 General Purpose Register, offset: 0x24 */ + __IO uint32_t GPR10; /**< GPR10 General Purpose Register, offset: 0x28 */ + uint8_t RESERVED_1[12]; + __IO uint32_t GPR14; /**< GPR14 General Purpose Register, offset: 0x38 */ +} IOMUXC_GPR_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks + * @{ + */ + +/*! @name GPR0 - GPR0 General Purpose Register */ +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK (0x1U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT (0U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK (0x2U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT (1U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK (0x4U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT (2U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK (0x8U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT (3U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK (0x10U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT (4U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK (0x20U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT (5U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK (0x40U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT (6U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_MASK (0x80U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_SHIFT (7U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_MASK (0x100U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_SHIFT (8U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_MASK (0x200U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_SHIFT (9U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_MASK (0x400U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_SHIFT (10U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_MASK (0x800U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_SHIFT (11U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_MASK (0x1000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_SHIFT (12U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_MASK (0x2000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_SHIFT (13U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_MASK (0x4000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_SHIFT (14U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_MASK (0x8000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_SHIFT (15U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_MASK (0x10000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_SHIFT (16U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_MASK (0x20000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_SHIFT (17U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_MASK (0x40000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_SHIFT (18U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_MASK (0x80000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_SHIFT (19U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_MASK (0x100000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_SHIFT (20U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_MASK (0x200000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_SHIFT (21U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_MASK (0x400000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_SHIFT (22U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_MASK) + +/*! @name GPR1 - GPR1 General Purpose Register */ +#define IOMUXC_GPR_GPR1_ACT_CS0_MASK (0x1U) +#define IOMUXC_GPR_GPR1_ACT_CS0_SHIFT (0U) +#define IOMUXC_GPR_GPR1_ACT_CS0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ACT_CS0_SHIFT)) & IOMUXC_GPR_GPR1_ACT_CS0_MASK) +#define IOMUXC_GPR_GPR1_ADDRS0_MASK (0x6U) +#define IOMUXC_GPR_GPR1_ADDRS0_SHIFT (1U) +#define IOMUXC_GPR_GPR1_ADDRS0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADDRS0_SHIFT)) & IOMUXC_GPR_GPR1_ADDRS0_MASK) +#define IOMUXC_GPR_GPR1_ACT_CS1_MASK (0x8U) +#define IOMUXC_GPR_GPR1_ACT_CS1_SHIFT (3U) +#define IOMUXC_GPR_GPR1_ACT_CS1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ACT_CS1_SHIFT)) & IOMUXC_GPR_GPR1_ACT_CS1_MASK) +#define IOMUXC_GPR_GPR1_ADDRS1_MASK (0x30U) +#define IOMUXC_GPR_GPR1_ADDRS1_SHIFT (4U) +#define IOMUXC_GPR_GPR1_ADDRS1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADDRS1_SHIFT)) & IOMUXC_GPR_GPR1_ADDRS1_MASK) +#define IOMUXC_GPR_GPR1_ACT_CS2_MASK (0x40U) +#define IOMUXC_GPR_GPR1_ACT_CS2_SHIFT (6U) +#define IOMUXC_GPR_GPR1_ACT_CS2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ACT_CS2_SHIFT)) & IOMUXC_GPR_GPR1_ACT_CS2_MASK) +#define IOMUXC_GPR_GPR1_ADDRS2_MASK (0x180U) +#define IOMUXC_GPR_GPR1_ADDRS2_SHIFT (7U) +#define IOMUXC_GPR_GPR1_ADDRS2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADDRS2_SHIFT)) & IOMUXC_GPR_GPR1_ADDRS2_MASK) +#define IOMUXC_GPR_GPR1_ACT_CS3_MASK (0x200U) +#define IOMUXC_GPR_GPR1_ACT_CS3_SHIFT (9U) +#define IOMUXC_GPR_GPR1_ACT_CS3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ACT_CS3_SHIFT)) & IOMUXC_GPR_GPR1_ACT_CS3_MASK) +#define IOMUXC_GPR_GPR1_ADDRS3_MASK (0xC00U) +#define IOMUXC_GPR_GPR1_ADDRS3_SHIFT (10U) +#define IOMUXC_GPR_GPR1_ADDRS3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADDRS3_SHIFT)) & IOMUXC_GPR_GPR1_ADDRS3_MASK) +#define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U) +#define IOMUXC_GPR_GPR1_GINT_SHIFT (12U) +#define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK) +#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK (0x4000U) +#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT (14U) +#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK) +#define IOMUXC_GPR_GPR1_ADD_DS_MASK (0x10000U) +#define IOMUXC_GPR_GPR1_ADD_DS_SHIFT (16U) +#define IOMUXC_GPR_GPR1_ADD_DS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADD_DS_SHIFT)) & IOMUXC_GPR_GPR1_ADD_DS_MASK) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK (0x40000U) +#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT (18U) +#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U) +#define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U) +#define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK) +#define IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_MASK (0x800000U) +#define IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_SHIFT (23U) +#define IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_SHIFT)) & IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_MASK) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN_MASK (0x1000000U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN_SHIFT (24U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN_MASK) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN_MASK (0x2000000U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN_SHIFT (25U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN_SHIFT)) & IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN_MASK) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN_MASK (0x4000000U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN_SHIFT (26U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN_SHIFT)) & IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN_MASK) + +/*! @name GPR2 - GPR2 General Purpose Register */ +#define IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_MASK (0x1U) +#define IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_SHIFT (0U) +#define IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_MASK (0x2U) +#define IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_SHIFT (1U) +#define IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_SHIFT)) & IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_MASK) +#define IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_MASK (0x4U) +#define IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_SHIFT (2U) +#define IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_MASK (0x8U) +#define IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_SHIFT (3U) +#define IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_MASK) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_MASK (0x10U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_SHIFT (4U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_MASK (0x20U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_SHIFT (5U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_MASK) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_MASK (0x40U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_SHIFT (6U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_MASK (0x80U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_SHIFT (7U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_MASK) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_MASK (0x100U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_SHIFT (8U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_MASK (0x200U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_SHIFT (9U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_MASK) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_MASK (0x400U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_SHIFT (10U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_MASK (0x800U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_SHIFT (11U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_MASK (0x2000U) +#define IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_SHIFT (13U) +#define IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_MASK (0x8000U) +#define IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_SHIFT (15U) +#define IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_MASK) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U) +#define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK) +#define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U) +#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U) +#define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK) +#define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_MASK (0x8000000U) +#define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_SHIFT (27U) +#define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_MASK) +#define IOMUXC_GPR_GPR2_DRAM_RESET_MASK (0x10000000U) +#define IOMUXC_GPR_GPR2_DRAM_RESET_SHIFT (28U) +#define IOMUXC_GPR_GPR2_DRAM_RESET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_RESET_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_RESET_MASK) +#define IOMUXC_GPR_GPR2_DRAM_CKE0_MASK (0x20000000U) +#define IOMUXC_GPR_GPR2_DRAM_CKE0_SHIFT (29U) +#define IOMUXC_GPR_GPR2_DRAM_CKE0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_CKE0_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_CKE0_MASK) +#define IOMUXC_GPR_GPR2_DRAM_CKE1_MASK (0x40000000U) +#define IOMUXC_GPR_GPR2_DRAM_CKE1_SHIFT (30U) +#define IOMUXC_GPR_GPR2_DRAM_CKE1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_CKE1_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_CKE1_MASK) +#define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_MASK (0x80000000U) +#define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_SHIFT (31U) +#define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_MASK) + +/*! @name GPR3 - GPR3 General Purpose Register */ +#define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU) +#define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U) +#define IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK) +#define IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_MASK (0x2000U) +#define IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_SHIFT (13U) +#define IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_SHIFT)) & IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_MASK) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK) + +/*! @name GPR4 - GPR4 General Purpose Register */ +#define IOMUXC_GPR_GPR4_SDMA_STOP_REQ_MASK (0x1U) +#define IOMUXC_GPR_GPR4_SDMA_STOP_REQ_SHIFT (0U) +#define IOMUXC_GPR_GPR4_SDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SDMA_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_ENET1_STOP_REQ_MASK (0x8U) +#define IOMUXC_GPR_GPR4_ENET1_STOP_REQ_SHIFT (3U) +#define IOMUXC_GPR_GPR4_ENET1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK (0x10U) +#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT (4U) +#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN_MASK (0x100U) +#define IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN_SHIFT (8U) +#define IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN_MASK) +#define IOMUXC_GPR_GPR4_SDMA_STOP_ACK_MASK (0x10000U) +#define IOMUXC_GPR_GPR4_SDMA_STOP_ACK_SHIFT (16U) +#define IOMUXC_GPR_GPR4_SDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SDMA_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_ENET1_STOP_ACK_MASK (0x80000U) +#define IOMUXC_GPR_GPR4_ENET1_STOP_ACK_SHIFT (19U) +#define IOMUXC_GPR_GPR4_ENET1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK (0x100000U) +#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT (20U) +#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_ARM_WFI_MASK (0x40000000U) +#define IOMUXC_GPR_GPR4_ARM_WFI_SHIFT (30U) +#define IOMUXC_GPR_GPR4_ARM_WFI(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ARM_WFI_SHIFT)) & IOMUXC_GPR_GPR4_ARM_WFI_MASK) +#define IOMUXC_GPR_GPR4_ARM_WFE_MASK (0x80000000U) +#define IOMUXC_GPR_GPR4_ARM_WFE_SHIFT (31U) +#define IOMUXC_GPR_GPR4_ARM_WFE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ARM_WFE_SHIFT)) & IOMUXC_GPR_GPR4_ARM_WFE_MASK) + +/*! @name GPR5 - GPR5 General Purpose Register */ +#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U) +#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U) +#define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK) +#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U) +#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U) +#define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI_MASK (0x300U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI_SHIFT (8U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI_SHIFT)) & IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI_MASK) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF_MASK (0x3000U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF_SHIFT (12U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF_SHIFT)) & IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF_MASK) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_MASK (0x30000U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_SHIFT (16U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_SHIFT)) & IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_MASK) +#define IOMUXC_GPR_GPR5_WDOG3_MASK_MASK (0x100000U) +#define IOMUXC_GPR_GPR5_WDOG3_MASK_SHIFT (20U) +#define IOMUXC_GPR_GPR5_WDOG3_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG3_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG3_MASK_MASK) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK (0x1000000U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT (24U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK) +#define IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_MASK (0x2000000U) +#define IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_SHIFT (25U) +#define IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_MASK) +#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK (0x4000000U) +#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT (26U) +#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_MASK (0x40000000U) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_SHIFT (30U) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_SHIFT)) & IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_MASK) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_MASK (0x80000000U) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_SHIFT (31U) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_SHIFT)) & IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_MASK) + +/*! @name GPR9 - GPR9 General Purpose Register */ +#define IOMUXC_GPR_GPR9_TZASC1_BYP_MASK (0x1U) +#define IOMUXC_GPR_GPR9_TZASC1_BYP_SHIFT (0U) +#define IOMUXC_GPR_GPR9_TZASC1_BYP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_TZASC1_BYP_SHIFT)) & IOMUXC_GPR_GPR9_TZASC1_BYP_MASK) + +/*! @name GPR10 - GPR10 General Purpose Register */ +#define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x1U) +#define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (0U) +#define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK) +#define IOMUXC_GPR_GPR10_DBG_CLK_EN_MASK (0x2U) +#define IOMUXC_GPR_GPR10_DBG_CLK_EN_SHIFT (1U) +#define IOMUXC_GPR_GPR10_DBG_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_CLK_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_CLK_EN_MASK) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x400U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (10U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xF800U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (11U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK) + +/*! @name GPR14 - GPR14 General Purpose Register */ +#define IOMUXC_GPR_GPR14_GPR_MASK (0xFFFFFFFCU) +#define IOMUXC_GPR_GPR14_GPR_SHIFT (2U) +#define IOMUXC_GPR_GPR14_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_GPR_SHIFT)) & IOMUXC_GPR_GPR14_GPR_MASK) + + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Masks */ + + +/* IOMUXC_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_GPR base address */ +#define IOMUXC_GPR_BASE (0x20E4000u) +/** Peripheral IOMUXC_GPR base pointer */ +#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) +/** Array initializer of IOMUXC_GPR peripheral base addresses */ +#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE } +/** Array initializer of IOMUXC_GPR peripheral base pointers */ +#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR } + +/*! + * @} + */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_Peripheral_Access_Layer IOMUXC_SNVS Peripheral Access Layer + * @{ + */ + +/** IOMUXC_SNVS - Register Layout Typedef */ +typedef struct { + __IO uint32_t SW_MUX_CTL_PAD[12]; /**< SW_MUX_CTL_PAD_BOOT_MODE0 SW MUX Control Register..SW_MUX_CTL_PAD_SNVS_TAMPER9 SW MUX Control Register, array offset: 0x0, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_PAD[17]; /**< SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register..SW_PAD_CTL_PAD_SNVS_TAMPER9 SW PAD Control Register, array offset: 0x30, array step: 0x4 */ +} IOMUXC_SNVS_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_Register_Masks IOMUXC_SNVS Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_BOOT_MODE0 SW MUX Control Register..SW_MUX_CTL_PAD_SNVS_TAMPER9 SW MUX Control Register */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE_MASK) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_SION_MASK (0x10U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_SION_SHIFT (4U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_SION_MASK) + +/* The count of IOMUXC_SNVS_SW_MUX_CTL_PAD */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_COUNT (12U) + +/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register..SW_PAD_CTL_PAD_SNVS_TAMPER9 SW PAD Control Register */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE_SHIFT (0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE_SHIFT (3U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED_SHIFT (6U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE_SHIFT (11U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE_SHIFT (12U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE_SHIFT (13U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS_SHIFT (14U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS_SHIFT (16U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS_MASK) + +/* The count of IOMUXC_SNVS_SW_PAD_CTL_PAD */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_COUNT (17U) + + +/*! + * @} + */ /* end of group IOMUXC_SNVS_Register_Masks */ + + +/* IOMUXC_SNVS - Peripheral instance base addresses */ +/** Peripheral IOMUXC_SNVS base address */ +#define IOMUXC_SNVS_BASE (0x2290000u) +/** Peripheral IOMUXC_SNVS base pointer */ +#define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE) +/** Array initializer of IOMUXC_SNVS peripheral base addresses */ +#define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE } +/** Array initializer of IOMUXC_SNVS peripheral base pointers */ +#define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS } + +/*! + * @} + */ /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- KPP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer + * @{ + */ + +/** KPP - Register Layout Typedef */ +typedef struct { + __IO uint16_t KPCR; /**< Keypad Control Register, offset: 0x0 */ + __IO uint16_t KPSR; /**< Keypad Status Register, offset: 0x2 */ + __IO uint16_t KDDR; /**< Keypad Data Direction Register, offset: 0x4 */ + __IO uint16_t KPDR; /**< Keypad Data Register, offset: 0x6 */ +} KPP_Type; + +/* ---------------------------------------------------------------------------- + -- KPP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Register_Masks KPP Register Masks + * @{ + */ + +/*! @name KPCR - Keypad Control Register */ +#define KPP_KPCR_KRE_MASK (0xFFU) +#define KPP_KPCR_KRE_SHIFT (0U) +#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK) +#define KPP_KPCR_KCO_MASK (0xFF00U) +#define KPP_KPCR_KCO_SHIFT (8U) +#define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK) + +/*! @name KPSR - Keypad Status Register */ +#define KPP_KPSR_KPKD_MASK (0x1U) +#define KPP_KPSR_KPKD_SHIFT (0U) +#define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK) +#define KPP_KPSR_KPKR_MASK (0x2U) +#define KPP_KPSR_KPKR_SHIFT (1U) +#define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK) +#define KPP_KPSR_KDSC_MASK (0x4U) +#define KPP_KPSR_KDSC_SHIFT (2U) +#define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK) +#define KPP_KPSR_KRSS_MASK (0x8U) +#define KPP_KPSR_KRSS_SHIFT (3U) +#define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK) +#define KPP_KPSR_KDIE_MASK (0x100U) +#define KPP_KPSR_KDIE_SHIFT (8U) +#define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK) +#define KPP_KPSR_KRIE_MASK (0x200U) +#define KPP_KPSR_KRIE_SHIFT (9U) +#define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK) + +/*! @name KDDR - Keypad Data Direction Register */ +#define KPP_KDDR_KRDD_MASK (0xFFU) +#define KPP_KDDR_KRDD_SHIFT (0U) +#define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK) +#define KPP_KDDR_KCDD_MASK (0xFF00U) +#define KPP_KDDR_KCDD_SHIFT (8U) +#define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK) + +/*! @name KPDR - Keypad Data Register */ +#define KPP_KPDR_KRD_MASK (0xFFU) +#define KPP_KPDR_KRD_SHIFT (0U) +#define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK) +#define KPP_KPDR_KCD_MASK (0xFF00U) +#define KPP_KPDR_KCD_SHIFT (8U) +#define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) + + +/*! + * @} + */ /* end of group KPP_Register_Masks */ + + +/* KPP - Peripheral instance base addresses */ +/** Peripheral KPP base address */ +#define KPP_BASE (0x20B8000u) +/** Peripheral KPP base pointer */ +#define KPP ((KPP_Type *)KPP_BASE) +/** Array initializer of KPP peripheral base addresses */ +#define KPP_BASE_ADDRS { KPP_BASE } +/** Array initializer of KPP peripheral base pointers */ +#define KPP_BASE_PTRS { KPP } +/** Interrupt vectors for the KPP peripheral type */ +#define KPP_IRQS { KPP_IRQn } + +/*! + * @} + */ /* end of group KPP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LCDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer + * @{ + */ + +/** LCDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< eLCDIF General Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< eLCDIF General Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< eLCDIF General Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< eLCDIF General Control Register, offset: 0xC */ + __IO uint32_t CTRL1; /**< eLCDIF General Control1 Register, offset: 0x10 */ + __IO uint32_t CTRL1_SET; /**< eLCDIF General Control1 Register, offset: 0x14 */ + __IO uint32_t CTRL1_CLR; /**< eLCDIF General Control1 Register, offset: 0x18 */ + __IO uint32_t CTRL1_TOG; /**< eLCDIF General Control1 Register, offset: 0x1C */ + __IO uint32_t CTRL2; /**< eLCDIF General Control2 Register, offset: 0x20 */ + __IO uint32_t CTRL2_SET; /**< eLCDIF General Control2 Register, offset: 0x24 */ + __IO uint32_t CTRL2_CLR; /**< eLCDIF General Control2 Register, offset: 0x28 */ + __IO uint32_t CTRL2_TOG; /**< eLCDIF General Control2 Register, offset: 0x2C */ + __IO uint32_t TRANSFER_COUNT; /**< eLCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t TIMING; /**< LCD Interface Timing Register, offset: 0x60 */ + uint8_t RESERVED_3[12]; + __IO uint32_t VDCTRL0; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ + __IO uint32_t VDCTRL0_SET; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ + __IO uint32_t VDCTRL0_CLR; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ + __IO uint32_t VDCTRL0_TOG; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ + __IO uint32_t VDCTRL1; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ + uint8_t RESERVED_4[12]; + __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */ + uint8_t RESERVED_5[12]; + __IO uint32_t VDCTRL3; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ + uint8_t RESERVED_6[12]; + __IO uint32_t VDCTRL4; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ + uint8_t RESERVED_7[12]; + __IO uint32_t DVICTRL0; /**< Digital Video Interface Control0 Register, offset: 0xC0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t DVICTRL1; /**< Digital Video Interface Control1 Register, offset: 0xD0 */ + uint8_t RESERVED_9[12]; + __IO uint32_t DVICTRL2; /**< Digital Video Interface Control2 Register, offset: 0xE0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t DVICTRL3; /**< Digital Video Interface Control3 Register, offset: 0xF0 */ + uint8_t RESERVED_11[12]; + __IO uint32_t DVICTRL4; /**< Digital Video Interface Control4 Register, offset: 0x100 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CSC_COEFF0; /**< RGB to YCbCr 4:2:2 CSC Coefficient0 Register, offset: 0x110 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CSC_COEFF1; /**< RGB to YCbCr 4:2:2 CSC Coefficient1 Register, offset: 0x120 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CSC_COEFF2; /**< RGB to YCbCr 4:2:2 CSC Coefficent2 Register, offset: 0x130 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CSC_COEFF3; /**< RGB to YCbCr 4:2:2 CSC Coefficient3 Register, offset: 0x140 */ + uint8_t RESERVED_16[12]; + __IO uint32_t CSC_COEFF4; /**< RGB to YCbCr 4:2:2 CSC Coefficient4 Register, offset: 0x150 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CSC_OFFSET; /**< RGB to YCbCr 4:2:2 CSC Offset Register, offset: 0x160 */ + uint8_t RESERVED_18[12]; + __IO uint32_t CSC_LIMIT; /**< RGB to YCbCr 4:2:2 CSC Limit Register, offset: 0x170 */ + uint8_t RESERVED_19[12]; + __IO uint32_t DATA; /**< LCD Interface Data Register, offset: 0x180 */ + uint8_t RESERVED_20[12]; + __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */ + uint8_t RESERVED_22[12]; + __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ + uint8_t RESERVED_23[76]; + __IO uint32_t THRES; /**< eLCDIF Threshold Register, offset: 0x200 */ + uint8_t RESERVED_24[12]; + __IO uint32_t AS_CTRL; /**< eLCDIF AS Buffer Control Register, offset: 0x210 */ + uint8_t RESERVED_25[12]; + __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x220 */ + uint8_t RESERVED_26[12]; + __IO uint32_t AS_NEXT_BUF; /**< , offset: 0x230 */ + uint8_t RESERVED_27[12]; + __IO uint32_t AS_CLRKEYLOW; /**< eLCDIF Overlay Color Key Low, offset: 0x240 */ + uint8_t RESERVED_28[12]; + __IO uint32_t AS_CLRKEYHIGH; /**< eLCDIF Overlay Color Key High, offset: 0x250 */ + uint8_t RESERVED_29[12]; + __IO uint32_t SYNC_DELAY; /**< LCD working insync mode with CSI for VSYNC delay, offset: 0x260 */ +} LCDIF_Type; + +/* ---------------------------------------------------------------------------- + -- LCDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Register_Masks LCDIF Register Masks + * @{ + */ + +/*! @name CTRL - eLCDIF General Control Register */ +#define LCDIF_CTRL_RUN_MASK (0x1U) +#define LCDIF_CTRL_RUN_SHIFT (0U) +#define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK) +#define LCDIF_CTRL_MASTER_MASK (0x20U) +#define LCDIF_CTRL_MASTER_SHIFT (5U) +#define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK) +#define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_DATA_SELECT_SHIFT (16U) +#define LCDIF_CTRL_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SELECT_SHIFT)) & LCDIF_CTRL_DATA_SELECT_MASK) +#define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_VSYNC_MODE_MASK) +#define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DVI_MODE_SHIFT)) & LCDIF_CTRL_DVI_MODE_MASK) +#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK) +#define LCDIF_CTRL_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_READ_WRITEB_SHIFT)) & LCDIF_CTRL_READ_WRITEB_MASK) +#define LCDIF_CTRL_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_YCBCR422_INPUT_MASK) +#define LCDIF_CTRL_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK) +#define LCDIF_CTRL_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) + +/*! @name CTRL_SET - eLCDIF General Control Register */ +#define LCDIF_CTRL_SET_RUN_MASK (0x1U) +#define LCDIF_CTRL_SET_RUN_SHIFT (0U) +#define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK) +#define LCDIF_CTRL_SET_MASTER_MASK (0x20U) +#define LCDIF_CTRL_SET_MASTER_SHIFT (5U) +#define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK) +#define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_SET_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_SET_DATA_SELECT_SHIFT (16U) +#define LCDIF_CTRL_SET_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SELECT_SHIFT)) & LCDIF_CTRL_SET_DATA_SELECT_MASK) +#define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_SET_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_SET_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_SET_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_SET_VSYNC_MODE_MASK) +#define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_SET_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_SET_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_SET_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DVI_MODE_SHIFT)) & LCDIF_CTRL_SET_DVI_MODE_MASK) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK) +#define LCDIF_CTRL_SET_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_SET_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_SET_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_READ_WRITEB_SHIFT)) & LCDIF_CTRL_SET_READ_WRITEB_MASK) +#define LCDIF_CTRL_SET_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_SET_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_SET_YCBCR422_INPUT_MASK) +#define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK) +#define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_SET_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) + +/*! @name CTRL_CLR - eLCDIF General Control Register */ +#define LCDIF_CTRL_CLR_RUN_MASK (0x1U) +#define LCDIF_CTRL_CLR_RUN_SHIFT (0U) +#define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK) +#define LCDIF_CTRL_CLR_MASTER_MASK (0x20U) +#define LCDIF_CTRL_CLR_MASTER_SHIFT (5U) +#define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK) +#define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_CLR_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_CLR_DATA_SELECT_SHIFT (16U) +#define LCDIF_CTRL_CLR_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SELECT_SHIFT)) & LCDIF_CTRL_CLR_DATA_SELECT_MASK) +#define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_CLR_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_CLR_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_CLR_VSYNC_MODE_MASK) +#define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_CLR_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_CLR_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_CLR_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DVI_MODE_SHIFT)) & LCDIF_CTRL_CLR_DVI_MODE_MASK) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK) +#define LCDIF_CTRL_CLR_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_CLR_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_CLR_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_READ_WRITEB_SHIFT)) & LCDIF_CTRL_CLR_READ_WRITEB_MASK) +#define LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_CLR_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK) +#define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK) +#define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) + +/*! @name CTRL_TOG - eLCDIF General Control Register */ +#define LCDIF_CTRL_TOG_RUN_MASK (0x1U) +#define LCDIF_CTRL_TOG_RUN_SHIFT (0U) +#define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK) +#define LCDIF_CTRL_TOG_MASTER_MASK (0x20U) +#define LCDIF_CTRL_TOG_MASTER_SHIFT (5U) +#define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK) +#define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_TOG_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_TOG_DATA_SELECT_SHIFT (16U) +#define LCDIF_CTRL_TOG_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SELECT_SHIFT)) & LCDIF_CTRL_TOG_DATA_SELECT_MASK) +#define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_TOG_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_TOG_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_TOG_VSYNC_MODE_MASK) +#define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_TOG_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_TOG_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_TOG_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DVI_MODE_SHIFT)) & LCDIF_CTRL_TOG_DVI_MODE_MASK) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK) +#define LCDIF_CTRL_TOG_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_TOG_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_TOG_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_READ_WRITEB_SHIFT)) & LCDIF_CTRL_TOG_READ_WRITEB_MASK) +#define LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_TOG_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK) +#define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK) +#define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) + +/*! @name CTRL1 - eLCDIF General Control1 Register */ +#define LCDIF_CTRL1_RESET_MASK (0x1U) +#define LCDIF_CTRL1_RESET_SHIFT (0U) +#define LCDIF_CTRL1_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RESET_SHIFT)) & LCDIF_CTRL1_RESET_MASK) +#define LCDIF_CTRL1_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_MODE86_SHIFT (1U) +#define LCDIF_CTRL1_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_MODE86_SHIFT)) & LCDIF_CTRL1_MODE86_MASK) +#define LCDIF_CTRL1_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_BUSY_ENABLE_SHIFT (2U) +#define LCDIF_CTRL1_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_BUSY_ENABLE_MASK) +#define LCDIF_CTRL1_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK) +#define LCDIF_CTRL1_RSRVD1_MASK (0xF0000000U) +#define LCDIF_CTRL1_RSRVD1_SHIFT (28U) +#define LCDIF_CTRL1_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD1_SHIFT)) & LCDIF_CTRL1_RSRVD1_MASK) + +/*! @name CTRL1_SET - eLCDIF General Control1 Register */ +#define LCDIF_CTRL1_SET_RESET_MASK (0x1U) +#define LCDIF_CTRL1_SET_RESET_SHIFT (0U) +#define LCDIF_CTRL1_SET_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RESET_SHIFT)) & LCDIF_CTRL1_SET_RESET_MASK) +#define LCDIF_CTRL1_SET_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_SET_MODE86_SHIFT (1U) +#define LCDIF_CTRL1_SET_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_MODE86_SHIFT)) & LCDIF_CTRL1_SET_MODE86_MASK) +#define LCDIF_CTRL1_SET_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT (2U) +#define LCDIF_CTRL1_SET_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_SET_BUSY_ENABLE_MASK) +#define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK) +#define LCDIF_CTRL1_SET_RSRVD1_MASK (0xF0000000U) +#define LCDIF_CTRL1_SET_RSRVD1_SHIFT (28U) +#define LCDIF_CTRL1_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD1_SHIFT)) & LCDIF_CTRL1_SET_RSRVD1_MASK) + +/*! @name CTRL1_CLR - eLCDIF General Control1 Register */ +#define LCDIF_CTRL1_CLR_RESET_MASK (0x1U) +#define LCDIF_CTRL1_CLR_RESET_SHIFT (0U) +#define LCDIF_CTRL1_CLR_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RESET_SHIFT)) & LCDIF_CTRL1_CLR_RESET_MASK) +#define LCDIF_CTRL1_CLR_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_CLR_MODE86_SHIFT (1U) +#define LCDIF_CTRL1_CLR_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_MODE86_SHIFT)) & LCDIF_CTRL1_CLR_MODE86_MASK) +#define LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT (2U) +#define LCDIF_CTRL1_CLR_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK) +#define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK) +#define LCDIF_CTRL1_CLR_RSRVD1_MASK (0xF0000000U) +#define LCDIF_CTRL1_CLR_RSRVD1_SHIFT (28U) +#define LCDIF_CTRL1_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD1_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD1_MASK) + +/*! @name CTRL1_TOG - eLCDIF General Control1 Register */ +#define LCDIF_CTRL1_TOG_RESET_MASK (0x1U) +#define LCDIF_CTRL1_TOG_RESET_SHIFT (0U) +#define LCDIF_CTRL1_TOG_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RESET_SHIFT)) & LCDIF_CTRL1_TOG_RESET_MASK) +#define LCDIF_CTRL1_TOG_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_TOG_MODE86_SHIFT (1U) +#define LCDIF_CTRL1_TOG_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_MODE86_SHIFT)) & LCDIF_CTRL1_TOG_MODE86_MASK) +#define LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT (2U) +#define LCDIF_CTRL1_TOG_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK) +#define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK) +#define LCDIF_CTRL1_TOG_RSRVD1_MASK (0xF0000000U) +#define LCDIF_CTRL1_TOG_RSRVD1_SHIFT (28U) +#define LCDIF_CTRL1_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD1_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD1_MASK) + +/*! @name CTRL2 - eLCDIF General Control2 Register */ +#define LCDIF_CTRL2_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD1_SHIFT)) & LCDIF_CTRL2_RSRVD1_MASK) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) +#define LCDIF_CTRL2_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_READ_PACK_DIR_MASK) +#define LCDIF_CTRL2_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD2_SHIFT)) & LCDIF_CTRL2_RSRVD2_MASK) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK) +#define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) + +/*! @name CTRL2_SET - eLCDIF General Control2 Register */ +#define LCDIF_CTRL2_SET_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) +#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_SET_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_SET_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD1_SHIFT)) & LCDIF_CTRL2_SET_RSRVD1_MASK) +#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK) +#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) +#define LCDIF_CTRL2_SET_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_SET_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_SET_READ_PACK_DIR_MASK) +#define LCDIF_CTRL2_SET_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_SET_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD2_SHIFT)) & LCDIF_CTRL2_SET_RSRVD2_MASK) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK) +#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) + +/*! @name CTRL2_CLR - eLCDIF General Control2 Register */ +#define LCDIF_CTRL2_CLR_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) +#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_CLR_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_CLR_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD1_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD1_MASK) +#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK) +#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) +#define LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_CLR_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK) +#define LCDIF_CTRL2_CLR_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_CLR_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD2_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD2_MASK) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK) +#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) + +/*! @name CTRL2_TOG - eLCDIF General Control2 Register */ +#define LCDIF_CTRL2_TOG_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) +#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_TOG_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_TOG_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD1_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD1_MASK) +#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK) +#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) +#define LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_TOG_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK) +#define LCDIF_CTRL2_TOG_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_TOG_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD2_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD2_MASK) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK) +#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) + +/*! @name TRANSFER_COUNT - eLCDIF Horizontal and Vertical Valid Data Count Register */ +#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU) +#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) +#define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) +#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U) +#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) +#define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) + +/*! @name CUR_BUF - LCD Interface Current Buffer Address Register */ +#define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_CUR_BUF_ADDR_SHIFT (0U) +#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) + +/*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */ +#define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_NEXT_BUF_ADDR_SHIFT (0U) +#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) + +/*! @name TIMING - LCD Interface Timing Register */ +#define LCDIF_TIMING_DATA_SETUP_MASK (0xFFU) +#define LCDIF_TIMING_DATA_SETUP_SHIFT (0U) +#define LCDIF_TIMING_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_SETUP_SHIFT)) & LCDIF_TIMING_DATA_SETUP_MASK) +#define LCDIF_TIMING_DATA_HOLD_MASK (0xFF00U) +#define LCDIF_TIMING_DATA_HOLD_SHIFT (8U) +#define LCDIF_TIMING_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_HOLD_SHIFT)) & LCDIF_TIMING_DATA_HOLD_MASK) +#define LCDIF_TIMING_CMD_SETUP_MASK (0xFF0000U) +#define LCDIF_TIMING_CMD_SETUP_SHIFT (16U) +#define LCDIF_TIMING_CMD_SETUP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_SETUP_SHIFT)) & LCDIF_TIMING_CMD_SETUP_MASK) +#define LCDIF_TIMING_CMD_HOLD_MASK (0xFF000000U) +#define LCDIF_TIMING_CMD_HOLD_SHIFT (24U) +#define LCDIF_TIMING_CMD_HOLD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_HOLD_SHIFT)) & LCDIF_TIMING_CMD_HOLD_MASK) + +/*! @name VDCTRL0 - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK) +#define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT (29U) +#define LCDIF_VDCTRL0_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK) +#define LCDIF_VDCTRL0_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) + +/*! @name VDCTRL0_SET - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK) +#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT (29U) +#define LCDIF_VDCTRL0_SET_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK) +#define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) + +/*! @name VDCTRL0_CLR - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT (29U) +#define LCDIF_VDCTRL0_CLR_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK) +#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) + +/*! @name VDCTRL0_TOG - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT (29U) +#define LCDIF_VDCTRL0_TOG_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK) +#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) + +/*! @name VDCTRL1 - eLCDIF VSYNC Mode and Dotclk Mode Control Register1 */ +#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU) +#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) +#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) + +/*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */ +#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU) +#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) +#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) + +/*! @name VDCTRL3 - eLCDIF VSYNC Mode and Dotclk Mode Control Register3 */ +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) +#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U) +#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U) +#define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK) +#define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) +#define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) +#define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) + +/*! @name VDCTRL4 - eLCDIF VSYNC Mode and Dotclk Mode Control Register4 */ +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK) +#define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U) +#define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U) +#define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) + +/*! @name DVICTRL0 - Digital Video Interface Control0 Register */ +#define LCDIF_DVICTRL0_H_BLANKING_CNT_MASK (0xFFFU) +#define LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT (0U) +#define LCDIF_DVICTRL0_H_BLANKING_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT)) & LCDIF_DVICTRL0_H_BLANKING_CNT_MASK) +#define LCDIF_DVICTRL0_RSRVD0_MASK (0xF000U) +#define LCDIF_DVICTRL0_RSRVD0_SHIFT (12U) +#define LCDIF_DVICTRL0_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD0_SHIFT)) & LCDIF_DVICTRL0_RSRVD0_MASK) +#define LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK (0xFFF0000U) +#define LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT (16U) +#define LCDIF_DVICTRL0_H_ACTIVE_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT)) & LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK) +#define LCDIF_DVICTRL0_RSRVD1_MASK (0xF0000000U) +#define LCDIF_DVICTRL0_RSRVD1_SHIFT (28U) +#define LCDIF_DVICTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD1_SHIFT)) & LCDIF_DVICTRL0_RSRVD1_MASK) + +/*! @name DVICTRL1 - Digital Video Interface Control1 Register */ +#define LCDIF_DVICTRL1_F2_START_LINE_MASK (0x3FFU) +#define LCDIF_DVICTRL1_F2_START_LINE_SHIFT (0U) +#define LCDIF_DVICTRL1_F2_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F2_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F2_START_LINE_MASK) +#define LCDIF_DVICTRL1_F1_END_LINE_MASK (0xFFC00U) +#define LCDIF_DVICTRL1_F1_END_LINE_SHIFT (10U) +#define LCDIF_DVICTRL1_F1_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_END_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_END_LINE_MASK) +#define LCDIF_DVICTRL1_F1_START_LINE_MASK (0x3FF00000U) +#define LCDIF_DVICTRL1_F1_START_LINE_SHIFT (20U) +#define LCDIF_DVICTRL1_F1_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_START_LINE_MASK) +#define LCDIF_DVICTRL1_RSRVD0_MASK (0xC0000000U) +#define LCDIF_DVICTRL1_RSRVD0_SHIFT (30U) +#define LCDIF_DVICTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_RSRVD0_SHIFT)) & LCDIF_DVICTRL1_RSRVD0_MASK) + +/*! @name DVICTRL2 - Digital Video Interface Control2 Register */ +#define LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK (0x3FFU) +#define LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT (0U) +#define LCDIF_DVICTRL2_V1_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK) +#define LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK (0xFFC00U) +#define LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT (10U) +#define LCDIF_DVICTRL2_V1_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK) +#define LCDIF_DVICTRL2_F2_END_LINE_MASK (0x3FF00000U) +#define LCDIF_DVICTRL2_F2_END_LINE_SHIFT (20U) +#define LCDIF_DVICTRL2_F2_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_F2_END_LINE_SHIFT)) & LCDIF_DVICTRL2_F2_END_LINE_MASK) +#define LCDIF_DVICTRL2_RSRVD0_MASK (0xC0000000U) +#define LCDIF_DVICTRL2_RSRVD0_SHIFT (30U) +#define LCDIF_DVICTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_RSRVD0_SHIFT)) & LCDIF_DVICTRL2_RSRVD0_MASK) + +/*! @name DVICTRL3 - Digital Video Interface Control3 Register */ +#define LCDIF_DVICTRL3_V_LINES_CNT_MASK (0x3FFU) +#define LCDIF_DVICTRL3_V_LINES_CNT_SHIFT (0U) +#define LCDIF_DVICTRL3_V_LINES_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V_LINES_CNT_SHIFT)) & LCDIF_DVICTRL3_V_LINES_CNT_MASK) +#define LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK (0xFFC00U) +#define LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT (10U) +#define LCDIF_DVICTRL3_V2_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK) +#define LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK (0x3FF00000U) +#define LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT (20U) +#define LCDIF_DVICTRL3_V2_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK) +#define LCDIF_DVICTRL3_RSRVD0_MASK (0xC0000000U) +#define LCDIF_DVICTRL3_RSRVD0_SHIFT (30U) +#define LCDIF_DVICTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_RSRVD0_SHIFT)) & LCDIF_DVICTRL3_RSRVD0_MASK) + +/*! @name DVICTRL4 - Digital Video Interface Control4 Register */ +#define LCDIF_DVICTRL4_H_FILL_CNT_MASK (0xFFU) +#define LCDIF_DVICTRL4_H_FILL_CNT_SHIFT (0U) +#define LCDIF_DVICTRL4_H_FILL_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_H_FILL_CNT_SHIFT)) & LCDIF_DVICTRL4_H_FILL_CNT_MASK) +#define LCDIF_DVICTRL4_CR_FILL_VALUE_MASK (0xFF00U) +#define LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT (8U) +#define LCDIF_DVICTRL4_CR_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CR_FILL_VALUE_MASK) +#define LCDIF_DVICTRL4_CB_FILL_VALUE_MASK (0xFF0000U) +#define LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT (16U) +#define LCDIF_DVICTRL4_CB_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CB_FILL_VALUE_MASK) +#define LCDIF_DVICTRL4_Y_FILL_VALUE_MASK (0xFF000000U) +#define LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT (24U) +#define LCDIF_DVICTRL4_Y_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_Y_FILL_VALUE_MASK) + +/*! @name CSC_COEFF0 - RGB to YCbCr 4:2:2 CSC Coefficient0 Register */ +#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK (0x3U) +#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT (0U) +#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT)) & LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK) +#define LCDIF_CSC_COEFF0_RSRVD0_MASK (0xFFFCU) +#define LCDIF_CSC_COEFF0_RSRVD0_SHIFT (2U) +#define LCDIF_CSC_COEFF0_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD0_MASK) +#define LCDIF_CSC_COEFF0_C0_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF0_C0_SHIFT (16U) +#define LCDIF_CSC_COEFF0_C0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_C0_SHIFT)) & LCDIF_CSC_COEFF0_C0_MASK) +#define LCDIF_CSC_COEFF0_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF0_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD1_MASK) + +/*! @name CSC_COEFF1 - RGB to YCbCr 4:2:2 CSC Coefficient1 Register */ +#define LCDIF_CSC_COEFF1_C1_MASK (0x3FFU) +#define LCDIF_CSC_COEFF1_C1_SHIFT (0U) +#define LCDIF_CSC_COEFF1_C1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C1_SHIFT)) & LCDIF_CSC_COEFF1_C1_MASK) +#define LCDIF_CSC_COEFF1_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF1_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD0_MASK) +#define LCDIF_CSC_COEFF1_C2_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF1_C2_SHIFT (16U) +#define LCDIF_CSC_COEFF1_C2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C2_SHIFT)) & LCDIF_CSC_COEFF1_C2_MASK) +#define LCDIF_CSC_COEFF1_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF1_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF1_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD1_MASK) + +/*! @name CSC_COEFF2 - RGB to YCbCr 4:2:2 CSC Coefficent2 Register */ +#define LCDIF_CSC_COEFF2_C3_MASK (0x3FFU) +#define LCDIF_CSC_COEFF2_C3_SHIFT (0U) +#define LCDIF_CSC_COEFF2_C3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C3_SHIFT)) & LCDIF_CSC_COEFF2_C3_MASK) +#define LCDIF_CSC_COEFF2_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF2_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD0_MASK) +#define LCDIF_CSC_COEFF2_C4_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF2_C4_SHIFT (16U) +#define LCDIF_CSC_COEFF2_C4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C4_SHIFT)) & LCDIF_CSC_COEFF2_C4_MASK) +#define LCDIF_CSC_COEFF2_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF2_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD1_MASK) + +/*! @name CSC_COEFF3 - RGB to YCbCr 4:2:2 CSC Coefficient3 Register */ +#define LCDIF_CSC_COEFF3_C5_MASK (0x3FFU) +#define LCDIF_CSC_COEFF3_C5_SHIFT (0U) +#define LCDIF_CSC_COEFF3_C5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C5_SHIFT)) & LCDIF_CSC_COEFF3_C5_MASK) +#define LCDIF_CSC_COEFF3_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF3_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD0_MASK) +#define LCDIF_CSC_COEFF3_C6_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF3_C6_SHIFT (16U) +#define LCDIF_CSC_COEFF3_C6(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C6_SHIFT)) & LCDIF_CSC_COEFF3_C6_MASK) +#define LCDIF_CSC_COEFF3_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF3_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF3_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD1_MASK) + +/*! @name CSC_COEFF4 - RGB to YCbCr 4:2:2 CSC Coefficient4 Register */ +#define LCDIF_CSC_COEFF4_C7_MASK (0x3FFU) +#define LCDIF_CSC_COEFF4_C7_SHIFT (0U) +#define LCDIF_CSC_COEFF4_C7(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C7_SHIFT)) & LCDIF_CSC_COEFF4_C7_MASK) +#define LCDIF_CSC_COEFF4_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF4_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD0_MASK) +#define LCDIF_CSC_COEFF4_C8_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF4_C8_SHIFT (16U) +#define LCDIF_CSC_COEFF4_C8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C8_SHIFT)) & LCDIF_CSC_COEFF4_C8_MASK) +#define LCDIF_CSC_COEFF4_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF4_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF4_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD1_MASK) + +/*! @name CSC_OFFSET - RGB to YCbCr 4:2:2 CSC Offset Register */ +#define LCDIF_CSC_OFFSET_Y_OFFSET_MASK (0x1FFU) +#define LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT (0U) +#define LCDIF_CSC_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_Y_OFFSET_MASK) +#define LCDIF_CSC_OFFSET_RSRVD0_MASK (0xFE00U) +#define LCDIF_CSC_OFFSET_RSRVD0_SHIFT (9U) +#define LCDIF_CSC_OFFSET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD0_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD0_MASK) +#define LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK (0x1FF0000U) +#define LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT (16U) +#define LCDIF_CSC_OFFSET_CBCR_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK) +#define LCDIF_CSC_OFFSET_RSRVD1_MASK (0xFE000000U) +#define LCDIF_CSC_OFFSET_RSRVD1_SHIFT (25U) +#define LCDIF_CSC_OFFSET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD1_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD1_MASK) + +/*! @name CSC_LIMIT - RGB to YCbCr 4:2:2 CSC Limit Register */ +#define LCDIF_CSC_LIMIT_Y_MAX_MASK (0xFFU) +#define LCDIF_CSC_LIMIT_Y_MAX_SHIFT (0U) +#define LCDIF_CSC_LIMIT_Y_MAX(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MAX_SHIFT)) & LCDIF_CSC_LIMIT_Y_MAX_MASK) +#define LCDIF_CSC_LIMIT_Y_MIN_MASK (0xFF00U) +#define LCDIF_CSC_LIMIT_Y_MIN_SHIFT (8U) +#define LCDIF_CSC_LIMIT_Y_MIN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MIN_SHIFT)) & LCDIF_CSC_LIMIT_Y_MIN_MASK) +#define LCDIF_CSC_LIMIT_CBCR_MAX_MASK (0xFF0000U) +#define LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT (16U) +#define LCDIF_CSC_LIMIT_CBCR_MAX(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MAX_MASK) +#define LCDIF_CSC_LIMIT_CBCR_MIN_MASK (0xFF000000U) +#define LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT (24U) +#define LCDIF_CSC_LIMIT_CBCR_MIN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MIN_MASK) + +/*! @name DATA - LCD Interface Data Register */ +#define LCDIF_DATA_DATA_ZERO_MASK (0xFFU) +#define LCDIF_DATA_DATA_ZERO_SHIFT (0U) +#define LCDIF_DATA_DATA_ZERO(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ZERO_SHIFT)) & LCDIF_DATA_DATA_ZERO_MASK) +#define LCDIF_DATA_DATA_ONE_MASK (0xFF00U) +#define LCDIF_DATA_DATA_ONE_SHIFT (8U) +#define LCDIF_DATA_DATA_ONE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ONE_SHIFT)) & LCDIF_DATA_DATA_ONE_MASK) +#define LCDIF_DATA_DATA_TWO_MASK (0xFF0000U) +#define LCDIF_DATA_DATA_TWO_SHIFT (16U) +#define LCDIF_DATA_DATA_TWO(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_TWO_SHIFT)) & LCDIF_DATA_DATA_TWO_MASK) +#define LCDIF_DATA_DATA_THREE_MASK (0xFF000000U) +#define LCDIF_DATA_DATA_THREE_SHIFT (24U) +#define LCDIF_DATA_DATA_THREE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_THREE_SHIFT)) & LCDIF_DATA_DATA_THREE_MASK) + +/*! @name BM_ERROR_STAT - Bus Master Error Status Register */ +#define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) +#define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) + +/*! @name CRC_STAT - CRC Status Register */ +#define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU) +#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) +#define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) + +/*! @name STAT - LCD Interface Status Register */ +#define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU) +#define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) +#define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) +#define LCDIF_STAT_RSRVD0_MASK (0xFFFE00U) +#define LCDIF_STAT_RSRVD0_SHIFT (9U) +#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK) +#define LCDIF_STAT_DVI_CURRENT_FIELD_MASK (0x1000000U) +#define LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT (24U) +#define LCDIF_STAT_DVI_CURRENT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT)) & LCDIF_STAT_DVI_CURRENT_FIELD_MASK) +#define LCDIF_STAT_BUSY_MASK (0x2000000U) +#define LCDIF_STAT_BUSY_SHIFT (25U) +#define LCDIF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_BUSY_SHIFT)) & LCDIF_STAT_BUSY_MASK) +#define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U) +#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U) +#define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK) +#define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U) +#define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U) +#define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK) +#define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U) +#define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U) +#define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK) +#define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U) +#define LCDIF_STAT_LFIFO_FULL_SHIFT (29U) +#define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK) +#define LCDIF_STAT_PRESENT_MASK (0x80000000U) +#define LCDIF_STAT_PRESENT_SHIFT (31U) +#define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) + +/*! @name THRES - eLCDIF Threshold Register */ +#define LCDIF_THRES_PANIC_MASK (0x1FFU) +#define LCDIF_THRES_PANIC_SHIFT (0U) +#define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK) +#define LCDIF_THRES_RSRVD1_MASK (0xFE00U) +#define LCDIF_THRES_RSRVD1_SHIFT (9U) +#define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK) +#define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U) +#define LCDIF_THRES_FASTCLOCK_SHIFT (16U) +#define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK) +#define LCDIF_THRES_RSRVD2_MASK (0xFE000000U) +#define LCDIF_THRES_RSRVD2_SHIFT (25U) +#define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK) + +/*! @name AS_CTRL - eLCDIF AS Buffer Control Register */ +#define LCDIF_AS_CTRL_AS_ENABLE_MASK (0x1U) +#define LCDIF_AS_CTRL_AS_ENABLE_SHIFT (0U) +#define LCDIF_AS_CTRL_AS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_AS_ENABLE_SHIFT)) & LCDIF_AS_CTRL_AS_ENABLE_MASK) +#define LCDIF_AS_CTRL_ALPHA_CTRL_MASK (0x6U) +#define LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT (1U) +#define LCDIF_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT)) & LCDIF_AS_CTRL_ALPHA_CTRL_MASK) +#define LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) +#define LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) +#define LCDIF_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK) +#define LCDIF_AS_CTRL_FORMAT_MASK (0xF0U) +#define LCDIF_AS_CTRL_FORMAT_SHIFT (4U) +#define LCDIF_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_FORMAT_SHIFT)) & LCDIF_AS_CTRL_FORMAT_MASK) +#define LCDIF_AS_CTRL_ALPHA_MASK (0xFF00U) +#define LCDIF_AS_CTRL_ALPHA_SHIFT (8U) +#define LCDIF_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_SHIFT)) & LCDIF_AS_CTRL_ALPHA_MASK) +#define LCDIF_AS_CTRL_ROP_MASK (0xF0000U) +#define LCDIF_AS_CTRL_ROP_SHIFT (16U) +#define LCDIF_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ROP_SHIFT)) & LCDIF_AS_CTRL_ROP_MASK) +#define LCDIF_AS_CTRL_ALPHA_INVERT_MASK (0x100000U) +#define LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT (20U) +#define LCDIF_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT)) & LCDIF_AS_CTRL_ALPHA_INVERT_MASK) +#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK (0x600000U) +#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT (21U) +#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_AS_CTRL_PS_DISABLE_MASK (0x800000U) +#define LCDIF_AS_CTRL_PS_DISABLE_SHIFT (23U) +#define LCDIF_AS_CTRL_PS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_PS_DISABLE_SHIFT)) & LCDIF_AS_CTRL_PS_DISABLE_MASK) +#define LCDIF_AS_CTRL_RVDS1_MASK (0x7000000U) +#define LCDIF_AS_CTRL_RVDS1_SHIFT (24U) +#define LCDIF_AS_CTRL_RVDS1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_RVDS1_SHIFT)) & LCDIF_AS_CTRL_RVDS1_MASK) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK (0x8000000U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT (27U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK (0x10000000U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT (28U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK) +#define LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK (0x20000000U) +#define LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT (29U) +#define LCDIF_AS_CTRL_CSI_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK) +#define LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK (0x40000000U) +#define LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT (30U) +#define LCDIF_AS_CTRL_CSI_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK) +#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK (0x80000000U) +#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT (31U) +#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK) + +/*! @name AS_BUF - Alpha Surface Buffer Pointer */ +#define LCDIF_AS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_AS_BUF_ADDR_SHIFT (0U) +#define LCDIF_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_BUF_ADDR_SHIFT)) & LCDIF_AS_BUF_ADDR_MASK) + +/*! @name AS_NEXT_BUF - */ +#define LCDIF_AS_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_AS_NEXT_BUF_ADDR_SHIFT (0U) +#define LCDIF_AS_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_NEXT_BUF_ADDR_SHIFT)) & LCDIF_AS_NEXT_BUF_ADDR_MASK) + +/*! @name AS_CLRKEYLOW - eLCDIF Overlay Color Key Low */ +#define LCDIF_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) +#define LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT (0U) +#define LCDIF_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYLOW_PIXEL_MASK) +#define LCDIF_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) +#define LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT (24U) +#define LCDIF_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYLOW_RSVD1_MASK) + +/*! @name AS_CLRKEYHIGH - eLCDIF Overlay Color Key High */ +#define LCDIF_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) +#define LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT (0U) +#define LCDIF_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYHIGH_PIXEL_MASK) +#define LCDIF_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) +#define LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT (24U) +#define LCDIF_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYHIGH_RSVD1_MASK) + +/*! @name SYNC_DELAY - LCD working insync mode with CSI for VSYNC delay */ +#define LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK (0xFFFFU) +#define LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT (0U) +#define LCDIF_SYNC_DELAY_H_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK) +#define LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK (0xFFFF0000U) +#define LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT (16U) +#define LCDIF_SYNC_DELAY_V_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK) + + +/*! + * @} + */ /* end of group LCDIF_Register_Masks */ + + +/* LCDIF - Peripheral instance base addresses */ +/** Peripheral LCDIF base address */ +#define LCDIF_BASE (0x21C8000u) +/** Peripheral LCDIF base pointer */ +#define LCDIF ((LCDIF_Type *)LCDIF_BASE) +/** Array initializer of LCDIF peripheral base addresses */ +#define LCDIF_BASE_ADDRS { LCDIF_BASE } +/** Array initializer of LCDIF peripheral base pointers */ +#define LCDIF_BASE_PTRS { LCDIF } + +/*! + * @} + */ /* end of group LCDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MMDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MMDC_Peripheral_Access_Layer MMDC Peripheral Access Layer + * @{ + */ + +/** MMDC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MDCTL; /**< MMDC Core Control Register, offset: 0x0 */ + __IO uint32_t MDPDC; /**< MMDC Core Power Down Control Register, offset: 0x4 */ + __IO uint32_t MDOTC; /**< MMDC Core ODT Timing Control Register, offset: 0x8 */ + __IO uint32_t MDCFG0; /**< MMDC Core Timing Configuration Register 0, offset: 0xC */ + __IO uint32_t MDCFG1; /**< MMDC Core Timing Configuration Register 1, offset: 0x10 */ + __IO uint32_t MDCFG2; /**< MMDC Core Timing Configuration Register 2, offset: 0x14 */ + __IO uint32_t MDMISC; /**< MMDC Core Miscellaneous Register, offset: 0x18 */ + __IO uint32_t MDSCR; /**< MMDC Core Special Command Register, offset: 0x1C */ + __IO uint32_t MDREF; /**< MMDC Core Refresh Control Register, offset: 0x20 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MDRWD; /**< MMDC Core Read/Write Command Delay Register, offset: 0x2C */ + __IO uint32_t MDOR; /**< MMDC Core Out of Reset Delays Register, offset: 0x30 */ + __I uint32_t MDMRR; /**< MMDC Core MRR Data Register, offset: 0x34 */ + __IO uint32_t MDCFG3LP; /**< MMDC Core Timing Configuration Register 3, offset: 0x38 */ + __IO uint32_t MDMR4; /**< MMDC Core MR4 Derating Register, offset: 0x3C */ + __IO uint32_t MDASP; /**< MMDC Core Address Space Partition Register, offset: 0x40 */ + uint8_t RESERVED_1[956]; + __IO uint32_t MAARCR; /**< MMDC Core AXI Reordering Control Register, offset: 0x400 */ + __IO uint32_t MAPSR; /**< MMDC Core Power Saving Control and Status Register, offset: 0x404 */ + __IO uint32_t MAEXIDR0; /**< MMDC Core Exclusive ID Monitor Register0, offset: 0x408 */ + __IO uint32_t MAEXIDR1; /**< MMDC Core Exclusive ID Monitor Register1, offset: 0x40C */ + __IO uint32_t MADPCR0; /**< MMDC Core Debug and Profiling Control Register 0, offset: 0x410 */ + __IO uint32_t MADPCR1; /**< MMDC Core Debug and Profiling Control Register 1, offset: 0x414 */ + __I uint32_t MADPSR0; /**< MMDC Core Debug and Profiling Status Register 0, offset: 0x418 */ + __I uint32_t MADPSR1; /**< MMDC Core Debug and Profiling Status Register 1, offset: 0x41C */ + __I uint32_t MADPSR2; /**< MMDC Core Debug and Profiling Status Register 2, offset: 0x420 */ + __I uint32_t MADPSR3; /**< MMDC Core Debug and Profiling Status Register 3, offset: 0x424 */ + __I uint32_t MADPSR4; /**< MMDC Core Debug and Profiling Status Register 4, offset: 0x428 */ + __I uint32_t MADPSR5; /**< MMDC Core Debug and Profiling Status Register 5, offset: 0x42C */ + __I uint32_t MASBS0; /**< MMDC Core Step By Step Address Register, offset: 0x430 */ + __I uint32_t MASBS1; /**< MMDC Core Step By Step Address Attributes Register, offset: 0x434 */ + uint8_t RESERVED_2[8]; + __IO uint32_t MAGENP; /**< MMDC Core General Purpose Register, offset: 0x440 */ + uint8_t RESERVED_3[956]; + __IO uint32_t MPZQHWCTRL; /**< MMDC PHY ZQ HW control register, offset: 0x800 */ + __IO uint32_t MPZQSWCTRL; /**< MMDC PHY ZQ SW control register, offset: 0x804 */ + __IO uint32_t MPWLGCR; /**< MMDC PHY Write Leveling Configuration and Error Status Register, offset: 0x808 */ + __IO uint32_t MPWLDECTRL0; /**< MMDC PHY Write Leveling Delay Control Register 0, offset: 0x80C */ + __IO uint32_t MPWLDECTRL1; /**< MMDC PHY Write Leveling Delay Control Register 1, offset: 0x810 */ + __I uint32_t MPWLDLST; /**< MMDC PHY Write Leveling delay-line Status Register, offset: 0x814 */ + __IO uint32_t MPODTCTRL; /**< MMDC PHY ODT control register, offset: 0x818 */ + __IO uint32_t MPRDDQBY0DL; /**< MMDC PHY Read DQ Byte0 Delay Register, offset: 0x81C */ + __IO uint32_t MPRDDQBY1DL; /**< MMDC PHY Read DQ Byte1 Delay Register, offset: 0x820 */ + uint8_t RESERVED_4[8]; + __IO uint32_t MPWRDQBY0DL; /**< MMDC PHY Write DQ Byte0 Delay Register, offset: 0x82C */ + __IO uint32_t MPWRDQBY1DL; /**< MMDC PHY Write DQ Byte1 Delay Register, offset: 0x830 */ + __IO uint32_t MPWRDQBY2DL; /**< MMDC PHY Write DQ Byte2 Delay Register, offset: 0x834 */ + __IO uint32_t MPWRDQBY3DL; /**< MMDC PHY Write DQ Byte3 Delay Register, offset: 0x838 */ + __IO uint32_t MPDGCTRL0; /**< MMDC PHY Read DQS Gating Control Register 0, offset: 0x83C */ + uint8_t RESERVED_5[4]; + __I uint32_t MPDGDLST0; /**< MMDC PHY Read DQS Gating delay-line Status Register, offset: 0x844 */ + __IO uint32_t MPRDDLCTL; /**< MMDC PHY Read delay-lines Configuration Register, offset: 0x848 */ + __I uint32_t MPRDDLST; /**< MMDC PHY Read delay-lines Status Register, offset: 0x84C */ + __IO uint32_t MPWRDLCTL; /**< MMDC PHY Write delay-lines Configuration Register, offset: 0x850 */ + __I uint32_t MPWRDLST; /**< MMDC PHY Write delay-lines Status Register, offset: 0x854 */ + __IO uint32_t MPSDCTRL; /**< MMDC PHY CK Control Register, offset: 0x858 */ + __IO uint32_t MPZQLP2CTL; /**< MMDC ZQ LPDDR2 HW Control Register, offset: 0x85C */ + __IO uint32_t MPRDDLHWCTL; /**< MMDC PHY Read Delay HW Calibration Control Register, offset: 0x860 */ + __IO uint32_t MPWRDLHWCTL; /**< MMDC PHY Write Delay HW Calibration Control Register, offset: 0x864 */ + __I uint32_t MPRDDLHWST0; /**< MMDC PHY Read Delay HW Calibration Status Register 0, offset: 0x868 */ + uint8_t RESERVED_6[4]; + __I uint32_t MPWRDLHWST0; /**< MMDC PHY Write Delay HW Calibration Status Register 0, offset: 0x870 */ + uint8_t RESERVED_7[4]; + __I uint32_t MPWLHWERR; /**< MMDC PHY Write Leveling HW Error Register, offset: 0x878 */ + __I uint32_t MPDGHWST0; /**< MMDC PHY Read DQS Gating HW Status Register 0, offset: 0x87C */ + __I uint32_t MPDGHWST1; /**< MMDC PHY Read DQS Gating HW Status Register 1, offset: 0x880 */ + uint8_t RESERVED_8[8]; + __IO uint32_t MPPDCMPR1; /**< MMDC PHY Pre-defined Compare Register 1, offset: 0x88C */ + __IO uint32_t MPPDCMPR2; /**< MMDC PHY Pre-defined Compare and CA delay-line Configuration Register, offset: 0x890 */ + __IO uint32_t MPSWDAR0; /**< MMDC PHY SW Dummy Access Register, offset: 0x894 */ + __I uint32_t MPSWDRDR0; /**< MMDC PHY SW Dummy Read Data Register 0, offset: 0x898 */ + __I uint32_t MPSWDRDR1; /**< MMDC PHY SW Dummy Read Data Register 1, offset: 0x89C */ + __I uint32_t MPSWDRDR2; /**< MMDC PHY SW Dummy Read Data Register 2, offset: 0x8A0 */ + __I uint32_t MPSWDRDR3; /**< MMDC PHY SW Dummy Read Data Register 3, offset: 0x8A4 */ + __I uint32_t MPSWDRDR4; /**< MMDC PHY SW Dummy Read Data Register 4, offset: 0x8A8 */ + __I uint32_t MPSWDRDR5; /**< MMDC PHY SW Dummy Read Data Register 5, offset: 0x8AC */ + __I uint32_t MPSWDRDR6; /**< MMDC PHY SW Dummy Read Data Register 6, offset: 0x8B0 */ + __I uint32_t MPSWDRDR7; /**< MMDC PHY SW Dummy Read Data Register 7, offset: 0x8B4 */ + __IO uint32_t MPMUR0; /**< MMDC PHY Measure Unit Register, offset: 0x8B8 */ + __IO uint32_t MPWRCADL; /**< MMDC Write CA delay-line controller, offset: 0x8BC */ + __IO uint32_t MPDCCR; /**< MMDC Duty Cycle Control Register, offset: 0x8C0 */ +} MMDC_Type; + +/* ---------------------------------------------------------------------------- + -- MMDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MMDC_Register_Masks MMDC Register Masks + * @{ + */ + +/*! @name MDCTL - MMDC Core Control Register */ +#define MMDC_MDCTL_DSIZ_MASK (0x30000U) +#define MMDC_MDCTL_DSIZ_SHIFT (16U) +#define MMDC_MDCTL_DSIZ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_DSIZ_SHIFT)) & MMDC_MDCTL_DSIZ_MASK) +#define MMDC_MDCTL_BL_MASK (0x80000U) +#define MMDC_MDCTL_BL_SHIFT (19U) +#define MMDC_MDCTL_BL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_BL_SHIFT)) & MMDC_MDCTL_BL_MASK) +#define MMDC_MDCTL_COL_MASK (0x700000U) +#define MMDC_MDCTL_COL_SHIFT (20U) +#define MMDC_MDCTL_COL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_COL_SHIFT)) & MMDC_MDCTL_COL_MASK) +#define MMDC_MDCTL_ROW_MASK (0x7000000U) +#define MMDC_MDCTL_ROW_SHIFT (24U) +#define MMDC_MDCTL_ROW(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_ROW_SHIFT)) & MMDC_MDCTL_ROW_MASK) +#define MMDC_MDCTL_SDE_1_MASK (0x40000000U) +#define MMDC_MDCTL_SDE_1_SHIFT (30U) +#define MMDC_MDCTL_SDE_1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_SDE_1_SHIFT)) & MMDC_MDCTL_SDE_1_MASK) +#define MMDC_MDCTL_SDE_0_MASK (0x80000000U) +#define MMDC_MDCTL_SDE_0_SHIFT (31U) +#define MMDC_MDCTL_SDE_0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_SDE_0_SHIFT)) & MMDC_MDCTL_SDE_0_MASK) + +/*! @name MDPDC - MMDC Core Power Down Control Register */ +#define MMDC_MDPDC_TCKSRE_MASK (0x7U) +#define MMDC_MDPDC_TCKSRE_SHIFT (0U) +#define MMDC_MDPDC_TCKSRE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_TCKSRE_SHIFT)) & MMDC_MDPDC_TCKSRE_MASK) +#define MMDC_MDPDC_TCKSRX_MASK (0x38U) +#define MMDC_MDPDC_TCKSRX_SHIFT (3U) +#define MMDC_MDPDC_TCKSRX(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_TCKSRX_SHIFT)) & MMDC_MDPDC_TCKSRX_MASK) +#define MMDC_MDPDC_BOTH_CS_PD_MASK (0x40U) +#define MMDC_MDPDC_BOTH_CS_PD_SHIFT (6U) +#define MMDC_MDPDC_BOTH_CS_PD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_BOTH_CS_PD_SHIFT)) & MMDC_MDPDC_BOTH_CS_PD_MASK) +#define MMDC_MDPDC_SLOW_PD_MASK (0x80U) +#define MMDC_MDPDC_SLOW_PD_SHIFT (7U) +#define MMDC_MDPDC_SLOW_PD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_SLOW_PD_SHIFT)) & MMDC_MDPDC_SLOW_PD_MASK) +#define MMDC_MDPDC_PWDT_0_MASK (0xF00U) +#define MMDC_MDPDC_PWDT_0_SHIFT (8U) +#define MMDC_MDPDC_PWDT_0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PWDT_0_SHIFT)) & MMDC_MDPDC_PWDT_0_MASK) +#define MMDC_MDPDC_PWDT_1_MASK (0xF000U) +#define MMDC_MDPDC_PWDT_1_SHIFT (12U) +#define MMDC_MDPDC_PWDT_1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PWDT_1_SHIFT)) & MMDC_MDPDC_PWDT_1_MASK) +#define MMDC_MDPDC_TCKE_MASK (0x70000U) +#define MMDC_MDPDC_TCKE_SHIFT (16U) +#define MMDC_MDPDC_TCKE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_TCKE_SHIFT)) & MMDC_MDPDC_TCKE_MASK) +#define MMDC_MDPDC_PRCT_0_MASK (0x7000000U) +#define MMDC_MDPDC_PRCT_0_SHIFT (24U) +#define MMDC_MDPDC_PRCT_0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PRCT_0_SHIFT)) & MMDC_MDPDC_PRCT_0_MASK) +#define MMDC_MDPDC_PRCT_1_MASK (0x70000000U) +#define MMDC_MDPDC_PRCT_1_SHIFT (28U) +#define MMDC_MDPDC_PRCT_1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PRCT_1_SHIFT)) & MMDC_MDPDC_PRCT_1_MASK) + +/*! @name MDOTC - MMDC Core ODT Timing Control Register */ +#define MMDC_MDOTC_TODT_IDLE_OFF_MASK (0x1F0U) +#define MMDC_MDOTC_TODT_IDLE_OFF_SHIFT (4U) +#define MMDC_MDOTC_TODT_IDLE_OFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TODT_IDLE_OFF_SHIFT)) & MMDC_MDOTC_TODT_IDLE_OFF_MASK) +#define MMDC_MDOTC_TODTLON_MASK (0x7000U) +#define MMDC_MDOTC_TODTLON_SHIFT (12U) +#define MMDC_MDOTC_TODTLON(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TODTLON_SHIFT)) & MMDC_MDOTC_TODTLON_MASK) +#define MMDC_MDOTC_TAXPD_MASK (0xF0000U) +#define MMDC_MDOTC_TAXPD_SHIFT (16U) +#define MMDC_MDOTC_TAXPD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TAXPD_SHIFT)) & MMDC_MDOTC_TAXPD_MASK) +#define MMDC_MDOTC_TANPD_MASK (0xF00000U) +#define MMDC_MDOTC_TANPD_SHIFT (20U) +#define MMDC_MDOTC_TANPD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TANPD_SHIFT)) & MMDC_MDOTC_TANPD_MASK) +#define MMDC_MDOTC_TAONPD_MASK (0x7000000U) +#define MMDC_MDOTC_TAONPD_SHIFT (24U) +#define MMDC_MDOTC_TAONPD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TAONPD_SHIFT)) & MMDC_MDOTC_TAONPD_MASK) +#define MMDC_MDOTC_TAOFPD_MASK (0x38000000U) +#define MMDC_MDOTC_TAOFPD_SHIFT (27U) +#define MMDC_MDOTC_TAOFPD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TAOFPD_SHIFT)) & MMDC_MDOTC_TAOFPD_MASK) + +/*! @name MDCFG0 - MMDC Core Timing Configuration Register 0 */ +#define MMDC_MDCFG0_TCL_MASK (0xFU) +#define MMDC_MDCFG0_TCL_SHIFT (0U) +#define MMDC_MDCFG0_TCL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TCL_SHIFT)) & MMDC_MDCFG0_TCL_MASK) +#define MMDC_MDCFG0_TFAW_MASK (0x1F0U) +#define MMDC_MDCFG0_TFAW_SHIFT (4U) +#define MMDC_MDCFG0_TFAW(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TFAW_SHIFT)) & MMDC_MDCFG0_TFAW_MASK) +#define MMDC_MDCFG0_TXPDLL_MASK (0x1E00U) +#define MMDC_MDCFG0_TXPDLL_SHIFT (9U) +#define MMDC_MDCFG0_TXPDLL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TXPDLL_SHIFT)) & MMDC_MDCFG0_TXPDLL_MASK) +#define MMDC_MDCFG0_TXP_MASK (0xE000U) +#define MMDC_MDCFG0_TXP_SHIFT (13U) +#define MMDC_MDCFG0_TXP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TXP_SHIFT)) & MMDC_MDCFG0_TXP_MASK) +#define MMDC_MDCFG0_TXS_MASK (0xFF0000U) +#define MMDC_MDCFG0_TXS_SHIFT (16U) +#define MMDC_MDCFG0_TXS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TXS_SHIFT)) & MMDC_MDCFG0_TXS_MASK) +#define MMDC_MDCFG0_TRFC_MASK (0xFF000000U) +#define MMDC_MDCFG0_TRFC_SHIFT (24U) +#define MMDC_MDCFG0_TRFC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TRFC_SHIFT)) & MMDC_MDCFG0_TRFC_MASK) + +/*! @name MDCFG1 - MMDC Core Timing Configuration Register 1 */ +#define MMDC_MDCFG1_TCWL_MASK (0x7U) +#define MMDC_MDCFG1_TCWL_SHIFT (0U) +#define MMDC_MDCFG1_TCWL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TCWL_SHIFT)) & MMDC_MDCFG1_TCWL_MASK) +#define MMDC_MDCFG1_TMRD_MASK (0x1E0U) +#define MMDC_MDCFG1_TMRD_SHIFT (5U) +#define MMDC_MDCFG1_TMRD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TMRD_SHIFT)) & MMDC_MDCFG1_TMRD_MASK) +#define MMDC_MDCFG1_TWR_MASK (0xE00U) +#define MMDC_MDCFG1_TWR_SHIFT (9U) +#define MMDC_MDCFG1_TWR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TWR_SHIFT)) & MMDC_MDCFG1_TWR_MASK) +#define MMDC_MDCFG1_TRPA_MASK (0x8000U) +#define MMDC_MDCFG1_TRPA_SHIFT (15U) +#define MMDC_MDCFG1_TRPA(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRPA_SHIFT)) & MMDC_MDCFG1_TRPA_MASK) +#define MMDC_MDCFG1_TRAS_MASK (0x1F0000U) +#define MMDC_MDCFG1_TRAS_SHIFT (16U) +#define MMDC_MDCFG1_TRAS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRAS_SHIFT)) & MMDC_MDCFG1_TRAS_MASK) +#define MMDC_MDCFG1_TRC_MASK (0x3E00000U) +#define MMDC_MDCFG1_TRC_SHIFT (21U) +#define MMDC_MDCFG1_TRC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRC_SHIFT)) & MMDC_MDCFG1_TRC_MASK) +#define MMDC_MDCFG1_TRP_MASK (0x1C000000U) +#define MMDC_MDCFG1_TRP_SHIFT (26U) +#define MMDC_MDCFG1_TRP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRP_SHIFT)) & MMDC_MDCFG1_TRP_MASK) +#define MMDC_MDCFG1_TRCD_MASK (0xE0000000U) +#define MMDC_MDCFG1_TRCD_SHIFT (29U) +#define MMDC_MDCFG1_TRCD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRCD_SHIFT)) & MMDC_MDCFG1_TRCD_MASK) + +/*! @name MDCFG2 - MMDC Core Timing Configuration Register 2 */ +#define MMDC_MDCFG2_TRRD_MASK (0x7U) +#define MMDC_MDCFG2_TRRD_SHIFT (0U) +#define MMDC_MDCFG2_TRRD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_TRRD_SHIFT)) & MMDC_MDCFG2_TRRD_MASK) +#define MMDC_MDCFG2_TWTR_MASK (0x38U) +#define MMDC_MDCFG2_TWTR_SHIFT (3U) +#define MMDC_MDCFG2_TWTR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_TWTR_SHIFT)) & MMDC_MDCFG2_TWTR_MASK) +#define MMDC_MDCFG2_TRTP_MASK (0x1C0U) +#define MMDC_MDCFG2_TRTP_SHIFT (6U) +#define MMDC_MDCFG2_TRTP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_TRTP_SHIFT)) & MMDC_MDCFG2_TRTP_MASK) +#define MMDC_MDCFG2_TDLLK_MASK (0x1FF0000U) +#define MMDC_MDCFG2_TDLLK_SHIFT (16U) +#define MMDC_MDCFG2_TDLLK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_TDLLK_SHIFT)) & MMDC_MDCFG2_TDLLK_MASK) + +/*! @name MDMISC - MMDC Core Miscellaneous Register */ +#define MMDC_MDMISC_RST_MASK (0x2U) +#define MMDC_MDMISC_RST_SHIFT (1U) +#define MMDC_MDMISC_RST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_RST_SHIFT)) & MMDC_MDMISC_RST_MASK) +#define MMDC_MDMISC_DDR_TYPE_MASK (0x18U) +#define MMDC_MDMISC_DDR_TYPE_SHIFT (3U) +#define MMDC_MDMISC_DDR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_DDR_TYPE_SHIFT)) & MMDC_MDMISC_DDR_TYPE_MASK) +#define MMDC_MDMISC_DDR_4_BANK_MASK (0x20U) +#define MMDC_MDMISC_DDR_4_BANK_SHIFT (5U) +#define MMDC_MDMISC_DDR_4_BANK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_DDR_4_BANK_SHIFT)) & MMDC_MDMISC_DDR_4_BANK_MASK) +#define MMDC_MDMISC_RALAT_MASK (0x1C0U) +#define MMDC_MDMISC_RALAT_SHIFT (6U) +#define MMDC_MDMISC_RALAT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_RALAT_SHIFT)) & MMDC_MDMISC_RALAT_MASK) +#define MMDC_MDMISC_MIF3_MODE_MASK (0x600U) +#define MMDC_MDMISC_MIF3_MODE_SHIFT (9U) +#define MMDC_MDMISC_MIF3_MODE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_MIF3_MODE_SHIFT)) & MMDC_MDMISC_MIF3_MODE_MASK) +#define MMDC_MDMISC_LPDDR2_S2_MASK (0x800U) +#define MMDC_MDMISC_LPDDR2_S2_SHIFT (11U) +#define MMDC_MDMISC_LPDDR2_S2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_LPDDR2_S2_SHIFT)) & MMDC_MDMISC_LPDDR2_S2_MASK) +#define MMDC_MDMISC_BI_ON_MASK (0x1000U) +#define MMDC_MDMISC_BI_ON_SHIFT (12U) +#define MMDC_MDMISC_BI_ON(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_BI_ON_SHIFT)) & MMDC_MDMISC_BI_ON_MASK) +#define MMDC_MDMISC_WALAT_MASK (0x30000U) +#define MMDC_MDMISC_WALAT_SHIFT (16U) +#define MMDC_MDMISC_WALAT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_WALAT_SHIFT)) & MMDC_MDMISC_WALAT_MASK) +#define MMDC_MDMISC_LHD_MASK (0x40000U) +#define MMDC_MDMISC_LHD_SHIFT (18U) +#define MMDC_MDMISC_LHD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_LHD_SHIFT)) & MMDC_MDMISC_LHD_MASK) +#define MMDC_MDMISC_ADDR_MIRROR_MASK (0x80000U) +#define MMDC_MDMISC_ADDR_MIRROR_SHIFT (19U) +#define MMDC_MDMISC_ADDR_MIRROR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_ADDR_MIRROR_SHIFT)) & MMDC_MDMISC_ADDR_MIRROR_MASK) +#define MMDC_MDMISC_CALIB_PER_CS_MASK (0x100000U) +#define MMDC_MDMISC_CALIB_PER_CS_SHIFT (20U) +#define MMDC_MDMISC_CALIB_PER_CS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CALIB_PER_CS_SHIFT)) & MMDC_MDMISC_CALIB_PER_CS_MASK) +#define MMDC_MDMISC_CK1_GATING_MASK (0x200000U) +#define MMDC_MDMISC_CK1_GATING_SHIFT (21U) +#define MMDC_MDMISC_CK1_GATING(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CK1_GATING_SHIFT)) & MMDC_MDMISC_CK1_GATING_MASK) +#define MMDC_MDMISC_CS1_RDY_MASK (0x40000000U) +#define MMDC_MDMISC_CS1_RDY_SHIFT (30U) +#define MMDC_MDMISC_CS1_RDY(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CS1_RDY_SHIFT)) & MMDC_MDMISC_CS1_RDY_MASK) +#define MMDC_MDMISC_CS0_RDY_MASK (0x80000000U) +#define MMDC_MDMISC_CS0_RDY_SHIFT (31U) +#define MMDC_MDMISC_CS0_RDY(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CS0_RDY_SHIFT)) & MMDC_MDMISC_CS0_RDY_MASK) + +/*! @name MDSCR - MMDC Core Special Command Register */ +#define MMDC_MDSCR_CMD_BA_MASK (0x7U) +#define MMDC_MDSCR_CMD_BA_SHIFT (0U) +#define MMDC_MDSCR_CMD_BA(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_BA_SHIFT)) & MMDC_MDSCR_CMD_BA_MASK) +#define MMDC_MDSCR_CMD_CS_MASK (0x8U) +#define MMDC_MDSCR_CMD_CS_SHIFT (3U) +#define MMDC_MDSCR_CMD_CS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_CS_SHIFT)) & MMDC_MDSCR_CMD_CS_MASK) +#define MMDC_MDSCR_CMD_MASK (0x70U) +#define MMDC_MDSCR_CMD_SHIFT (4U) +#define MMDC_MDSCR_CMD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_SHIFT)) & MMDC_MDSCR_CMD_MASK) +#define MMDC_MDSCR_WL_EN_MASK (0x200U) +#define MMDC_MDSCR_WL_EN_SHIFT (9U) +#define MMDC_MDSCR_WL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_WL_EN_SHIFT)) & MMDC_MDSCR_WL_EN_MASK) +#define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK (0x400U) +#define MMDC_MDSCR_MRR_READ_DATA_VALID_SHIFT (10U) +#define MMDC_MDSCR_MRR_READ_DATA_VALID(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_MRR_READ_DATA_VALID_SHIFT)) & MMDC_MDSCR_MRR_READ_DATA_VALID_MASK) +#define MMDC_MDSCR_CON_ACK_MASK (0x4000U) +#define MMDC_MDSCR_CON_ACK_SHIFT (14U) +#define MMDC_MDSCR_CON_ACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CON_ACK_SHIFT)) & MMDC_MDSCR_CON_ACK_MASK) +#define MMDC_MDSCR_CON_REQ_MASK (0x8000U) +#define MMDC_MDSCR_CON_REQ_SHIFT (15U) +#define MMDC_MDSCR_CON_REQ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CON_REQ_SHIFT)) & MMDC_MDSCR_CON_REQ_MASK) +#define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_MASK (0xFF0000U) +#define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_SHIFT (16U) +#define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_SHIFT)) & MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_MASK) +#define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_MASK (0xFF000000U) +#define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_SHIFT (24U) +#define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_SHIFT)) & MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_MASK) + +/*! @name MDREF - MMDC Core Refresh Control Register */ +#define MMDC_MDREF_START_REF_MASK (0x1U) +#define MMDC_MDREF_START_REF_SHIFT (0U) +#define MMDC_MDREF_START_REF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_START_REF_SHIFT)) & MMDC_MDREF_START_REF_MASK) +#define MMDC_MDREF_REFR_MASK (0x3800U) +#define MMDC_MDREF_REFR_SHIFT (11U) +#define MMDC_MDREF_REFR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_REFR_SHIFT)) & MMDC_MDREF_REFR_MASK) +#define MMDC_MDREF_REF_SEL_MASK (0xC000U) +#define MMDC_MDREF_REF_SEL_SHIFT (14U) +#define MMDC_MDREF_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_REF_SEL_SHIFT)) & MMDC_MDREF_REF_SEL_MASK) +#define MMDC_MDREF_REF_CNT_MASK (0xFFFF0000U) +#define MMDC_MDREF_REF_CNT_SHIFT (16U) +#define MMDC_MDREF_REF_CNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_REF_CNT_SHIFT)) & MMDC_MDREF_REF_CNT_MASK) + +/*! @name MDRWD - MMDC Core Read/Write Command Delay Register */ +#define MMDC_MDRWD_RTR_DIFF_MASK (0x7U) +#define MMDC_MDRWD_RTR_DIFF_SHIFT (0U) +#define MMDC_MDRWD_RTR_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_RTR_DIFF_SHIFT)) & MMDC_MDRWD_RTR_DIFF_MASK) +#define MMDC_MDRWD_RTW_DIFF_MASK (0x38U) +#define MMDC_MDRWD_RTW_DIFF_SHIFT (3U) +#define MMDC_MDRWD_RTW_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_RTW_DIFF_SHIFT)) & MMDC_MDRWD_RTW_DIFF_MASK) +#define MMDC_MDRWD_WTW_DIFF_MASK (0x1C0U) +#define MMDC_MDRWD_WTW_DIFF_SHIFT (6U) +#define MMDC_MDRWD_WTW_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_WTW_DIFF_SHIFT)) & MMDC_MDRWD_WTW_DIFF_MASK) +#define MMDC_MDRWD_WTR_DIFF_MASK (0xE00U) +#define MMDC_MDRWD_WTR_DIFF_SHIFT (9U) +#define MMDC_MDRWD_WTR_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_WTR_DIFF_SHIFT)) & MMDC_MDRWD_WTR_DIFF_MASK) +#define MMDC_MDRWD_RTW_SAME_MASK (0x7000U) +#define MMDC_MDRWD_RTW_SAME_SHIFT (12U) +#define MMDC_MDRWD_RTW_SAME(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_RTW_SAME_SHIFT)) & MMDC_MDRWD_RTW_SAME_MASK) +#define MMDC_MDRWD_TDAI_MASK (0x1FFF0000U) +#define MMDC_MDRWD_TDAI_SHIFT (16U) +#define MMDC_MDRWD_TDAI(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_TDAI_SHIFT)) & MMDC_MDRWD_TDAI_MASK) + +/*! @name MDOR - MMDC Core Out of Reset Delays Register */ +#define MMDC_MDOR_RST_TO_CKE_MASK (0x3FU) +#define MMDC_MDOR_RST_TO_CKE_SHIFT (0U) +#define MMDC_MDOR_RST_TO_CKE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOR_RST_TO_CKE_SHIFT)) & MMDC_MDOR_RST_TO_CKE_MASK) +#define MMDC_MDOR_SDE_TO_RST_MASK (0x3F00U) +#define MMDC_MDOR_SDE_TO_RST_SHIFT (8U) +#define MMDC_MDOR_SDE_TO_RST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOR_SDE_TO_RST_SHIFT)) & MMDC_MDOR_SDE_TO_RST_MASK) +#define MMDC_MDOR_TXPR_MASK (0xFF0000U) +#define MMDC_MDOR_TXPR_SHIFT (16U) +#define MMDC_MDOR_TXPR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOR_TXPR_SHIFT)) & MMDC_MDOR_TXPR_MASK) + +/*! @name MDMRR - MMDC Core MRR Data Register */ +#define MMDC_MDMRR_MRR_READ_DATA0_MASK (0xFFU) +#define MMDC_MDMRR_MRR_READ_DATA0_SHIFT (0U) +#define MMDC_MDMRR_MRR_READ_DATA0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMRR_MRR_READ_DATA0_SHIFT)) & MMDC_MDMRR_MRR_READ_DATA0_MASK) +#define MMDC_MDMRR_MRR_READ_DATA1_MASK (0xFF00U) +#define MMDC_MDMRR_MRR_READ_DATA1_SHIFT (8U) +#define MMDC_MDMRR_MRR_READ_DATA1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMRR_MRR_READ_DATA1_SHIFT)) & MMDC_MDMRR_MRR_READ_DATA1_MASK) + +/*! @name MDCFG3LP - MMDC Core Timing Configuration Register 3 */ +#define MMDC_MDCFG3LP_TRPAB_LP_MASK (0xFU) +#define MMDC_MDCFG3LP_TRPAB_LP_SHIFT (0U) +#define MMDC_MDCFG3LP_TRPAB_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_TRPAB_LP_SHIFT)) & MMDC_MDCFG3LP_TRPAB_LP_MASK) +#define MMDC_MDCFG3LP_TRPPB_LP_MASK (0xF0U) +#define MMDC_MDCFG3LP_TRPPB_LP_SHIFT (4U) +#define MMDC_MDCFG3LP_TRPPB_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_TRPPB_LP_SHIFT)) & MMDC_MDCFG3LP_TRPPB_LP_MASK) +#define MMDC_MDCFG3LP_TRCD_LP_MASK (0xF00U) +#define MMDC_MDCFG3LP_TRCD_LP_SHIFT (8U) +#define MMDC_MDCFG3LP_TRCD_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_TRCD_LP_SHIFT)) & MMDC_MDCFG3LP_TRCD_LP_MASK) +#define MMDC_MDCFG3LP_RC_LP_MASK (0x3F0000U) +#define MMDC_MDCFG3LP_RC_LP_SHIFT (16U) +#define MMDC_MDCFG3LP_RC_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_RC_LP_SHIFT)) & MMDC_MDCFG3LP_RC_LP_MASK) + +/*! @name MDMR4 - MMDC Core MR4 Derating Register */ +#define MMDC_MDMR4_UPDATE_DE_REQ_MASK (0x1U) +#define MMDC_MDMR4_UPDATE_DE_REQ_SHIFT (0U) +#define MMDC_MDMR4_UPDATE_DE_REQ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_UPDATE_DE_REQ_SHIFT)) & MMDC_MDMR4_UPDATE_DE_REQ_MASK) +#define MMDC_MDMR4_UPDATE_DE_ACK_MASK (0x2U) +#define MMDC_MDMR4_UPDATE_DE_ACK_SHIFT (1U) +#define MMDC_MDMR4_UPDATE_DE_ACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_UPDATE_DE_ACK_SHIFT)) & MMDC_MDMR4_UPDATE_DE_ACK_MASK) +#define MMDC_MDMR4_TRCD_DE_MASK (0x10U) +#define MMDC_MDMR4_TRCD_DE_SHIFT (4U) +#define MMDC_MDMR4_TRCD_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRCD_DE_SHIFT)) & MMDC_MDMR4_TRCD_DE_MASK) +#define MMDC_MDMR4_TRC_DE_MASK (0x20U) +#define MMDC_MDMR4_TRC_DE_SHIFT (5U) +#define MMDC_MDMR4_TRC_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRC_DE_SHIFT)) & MMDC_MDMR4_TRC_DE_MASK) +#define MMDC_MDMR4_TRAS_DE_MASK (0x40U) +#define MMDC_MDMR4_TRAS_DE_SHIFT (6U) +#define MMDC_MDMR4_TRAS_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRAS_DE_SHIFT)) & MMDC_MDMR4_TRAS_DE_MASK) +#define MMDC_MDMR4_TRP_DE_MASK (0x80U) +#define MMDC_MDMR4_TRP_DE_SHIFT (7U) +#define MMDC_MDMR4_TRP_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRP_DE_SHIFT)) & MMDC_MDMR4_TRP_DE_MASK) +#define MMDC_MDMR4_TRRD_DE_MASK (0x100U) +#define MMDC_MDMR4_TRRD_DE_SHIFT (8U) +#define MMDC_MDMR4_TRRD_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRRD_DE_SHIFT)) & MMDC_MDMR4_TRRD_DE_MASK) + +/*! @name MDASP - MMDC Core Address Space Partition Register */ +#define MMDC_MDASP_CS0_END_MASK (0x7FU) +#define MMDC_MDASP_CS0_END_SHIFT (0U) +#define MMDC_MDASP_CS0_END(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDASP_CS0_END_SHIFT)) & MMDC_MDASP_CS0_END_MASK) + +/*! @name MAARCR - MMDC Core AXI Reordering Control Register */ +#define MMDC_MAARCR_ARCR_GUARD_MASK (0xFU) +#define MMDC_MAARCR_ARCR_GUARD_SHIFT (0U) +#define MMDC_MAARCR_ARCR_GUARD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_GUARD_SHIFT)) & MMDC_MAARCR_ARCR_GUARD_MASK) +#define MMDC_MAARCR_ARCR_DYN_MAX_MASK (0xF0U) +#define MMDC_MAARCR_ARCR_DYN_MAX_SHIFT (4U) +#define MMDC_MAARCR_ARCR_DYN_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_DYN_MAX_SHIFT)) & MMDC_MAARCR_ARCR_DYN_MAX_MASK) +#define MMDC_MAARCR_ARCR_DYN_JMP_MASK (0xF00U) +#define MMDC_MAARCR_ARCR_DYN_JMP_SHIFT (8U) +#define MMDC_MAARCR_ARCR_DYN_JMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_DYN_JMP_SHIFT)) & MMDC_MAARCR_ARCR_DYN_JMP_MASK) +#define MMDC_MAARCR_ARCR_ACC_HIT_MASK (0x70000U) +#define MMDC_MAARCR_ARCR_ACC_HIT_SHIFT (16U) +#define MMDC_MAARCR_ARCR_ACC_HIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_ACC_HIT_SHIFT)) & MMDC_MAARCR_ARCR_ACC_HIT_MASK) +#define MMDC_MAARCR_ARCR_PAG_HIT_MASK (0x700000U) +#define MMDC_MAARCR_ARCR_PAG_HIT_SHIFT (20U) +#define MMDC_MAARCR_ARCR_PAG_HIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_PAG_HIT_SHIFT)) & MMDC_MAARCR_ARCR_PAG_HIT_MASK) +#define MMDC_MAARCR_ARCR_RCH_EN_MASK (0x1000000U) +#define MMDC_MAARCR_ARCR_RCH_EN_SHIFT (24U) +#define MMDC_MAARCR_ARCR_RCH_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_RCH_EN_SHIFT)) & MMDC_MAARCR_ARCR_RCH_EN_MASK) +#define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK (0x10000000U) +#define MMDC_MAARCR_ARCR_EXC_ERR_EN_SHIFT (28U) +#define MMDC_MAARCR_ARCR_EXC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_EXC_ERR_EN_SHIFT)) & MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK) +#define MMDC_MAARCR_ARCR_SEC_ERR_EN_MASK (0x40000000U) +#define MMDC_MAARCR_ARCR_SEC_ERR_EN_SHIFT (30U) +#define MMDC_MAARCR_ARCR_SEC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_SEC_ERR_EN_SHIFT)) & MMDC_MAARCR_ARCR_SEC_ERR_EN_MASK) +#define MMDC_MAARCR_ARCR_SEC_ERR_LOCK_MASK (0x80000000U) +#define MMDC_MAARCR_ARCR_SEC_ERR_LOCK_SHIFT (31U) +#define MMDC_MAARCR_ARCR_SEC_ERR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_SEC_ERR_LOCK_SHIFT)) & MMDC_MAARCR_ARCR_SEC_ERR_LOCK_MASK) + +/*! @name MAPSR - MMDC Core Power Saving Control and Status Register */ +#define MMDC_MAPSR_PSD_MASK (0x1U) +#define MMDC_MAPSR_PSD_SHIFT (0U) +#define MMDC_MAPSR_PSD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_PSD_SHIFT)) & MMDC_MAPSR_PSD_MASK) +#define MMDC_MAPSR_PSS_MASK (0x10U) +#define MMDC_MAPSR_PSS_SHIFT (4U) +#define MMDC_MAPSR_PSS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_PSS_SHIFT)) & MMDC_MAPSR_PSS_MASK) +#define MMDC_MAPSR_RIS_MASK (0x20U) +#define MMDC_MAPSR_RIS_SHIFT (5U) +#define MMDC_MAPSR_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_RIS_SHIFT)) & MMDC_MAPSR_RIS_MASK) +#define MMDC_MAPSR_WIS_MASK (0x40U) +#define MMDC_MAPSR_WIS_SHIFT (6U) +#define MMDC_MAPSR_WIS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_WIS_SHIFT)) & MMDC_MAPSR_WIS_MASK) +#define MMDC_MAPSR_PST_MASK (0xFF00U) +#define MMDC_MAPSR_PST_SHIFT (8U) +#define MMDC_MAPSR_PST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_PST_SHIFT)) & MMDC_MAPSR_PST_MASK) +#define MMDC_MAPSR_LPMD_MASK (0x100000U) +#define MMDC_MAPSR_LPMD_SHIFT (20U) +#define MMDC_MAPSR_LPMD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_LPMD_SHIFT)) & MMDC_MAPSR_LPMD_MASK) +#define MMDC_MAPSR_DVFS_MASK (0x200000U) +#define MMDC_MAPSR_DVFS_SHIFT (21U) +#define MMDC_MAPSR_DVFS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_DVFS_SHIFT)) & MMDC_MAPSR_DVFS_MASK) +#define MMDC_MAPSR_LPACK_MASK (0x1000000U) +#define MMDC_MAPSR_LPACK_SHIFT (24U) +#define MMDC_MAPSR_LPACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_LPACK_SHIFT)) & MMDC_MAPSR_LPACK_MASK) +#define MMDC_MAPSR_DVACK_MASK (0x2000000U) +#define MMDC_MAPSR_DVACK_SHIFT (25U) +#define MMDC_MAPSR_DVACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_DVACK_SHIFT)) & MMDC_MAPSR_DVACK_MASK) + +/*! @name MAEXIDR0 - MMDC Core Exclusive ID Monitor Register0 */ +#define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK (0xFFFFU) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR0_SHIFT (0U) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR0_EXC_ID_MONITOR0_SHIFT)) & MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK (0xFFFF0000U) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR1_SHIFT (16U) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR0_EXC_ID_MONITOR1_SHIFT)) & MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK) + +/*! @name MAEXIDR1 - MMDC Core Exclusive ID Monitor Register1 */ +#define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK (0xFFFFU) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR2_SHIFT (0U) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR1_EXC_ID_MONITOR2_SHIFT)) & MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK (0xFFFF0000U) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR3_SHIFT (16U) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR1_EXC_ID_MONITOR3_SHIFT)) & MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK) + +/*! @name MADPCR0 - MMDC Core Debug and Profiling Control Register 0 */ +#define MMDC_MADPCR0_DBG_EN_MASK (0x1U) +#define MMDC_MADPCR0_DBG_EN_SHIFT (0U) +#define MMDC_MADPCR0_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_DBG_EN_SHIFT)) & MMDC_MADPCR0_DBG_EN_MASK) +#define MMDC_MADPCR0_DBG_RST_MASK (0x2U) +#define MMDC_MADPCR0_DBG_RST_SHIFT (1U) +#define MMDC_MADPCR0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_DBG_RST_SHIFT)) & MMDC_MADPCR0_DBG_RST_MASK) +#define MMDC_MADPCR0_PRF_FRZ_MASK (0x4U) +#define MMDC_MADPCR0_PRF_FRZ_SHIFT (2U) +#define MMDC_MADPCR0_PRF_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_PRF_FRZ_SHIFT)) & MMDC_MADPCR0_PRF_FRZ_MASK) +#define MMDC_MADPCR0_CYC_OVF_MASK (0x8U) +#define MMDC_MADPCR0_CYC_OVF_SHIFT (3U) +#define MMDC_MADPCR0_CYC_OVF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_CYC_OVF_SHIFT)) & MMDC_MADPCR0_CYC_OVF_MASK) +#define MMDC_MADPCR0_SBS_EN_MASK (0x100U) +#define MMDC_MADPCR0_SBS_EN_SHIFT (8U) +#define MMDC_MADPCR0_SBS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_SBS_EN_SHIFT)) & MMDC_MADPCR0_SBS_EN_MASK) +#define MMDC_MADPCR0_SBS_MASK (0x200U) +#define MMDC_MADPCR0_SBS_SHIFT (9U) +#define MMDC_MADPCR0_SBS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_SBS_SHIFT)) & MMDC_MADPCR0_SBS_MASK) + +/*! @name MADPCR1 - MMDC Core Debug and Profiling Control Register 1 */ +#define MMDC_MADPCR1_PRF_AXI_ID_MASK (0xFFFFU) +#define MMDC_MADPCR1_PRF_AXI_ID_SHIFT (0U) +#define MMDC_MADPCR1_PRF_AXI_ID(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR1_PRF_AXI_ID_SHIFT)) & MMDC_MADPCR1_PRF_AXI_ID_MASK) +#define MMDC_MADPCR1_PRF_AXI_IDMASK_MASK (0xFFFF0000U) +#define MMDC_MADPCR1_PRF_AXI_IDMASK_SHIFT (16U) +#define MMDC_MADPCR1_PRF_AXI_IDMASK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR1_PRF_AXI_IDMASK_SHIFT)) & MMDC_MADPCR1_PRF_AXI_IDMASK_MASK) + +/*! @name MADPSR0 - MMDC Core Debug and Profiling Status Register 0 */ +#define MMDC_MADPSR0_CYC_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR0_CYC_COUNT_SHIFT (0U) +#define MMDC_MADPSR0_CYC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR0_CYC_COUNT_SHIFT)) & MMDC_MADPSR0_CYC_COUNT_MASK) + +/*! @name MADPSR1 - MMDC Core Debug and Profiling Status Register 1 */ +#define MMDC_MADPSR1_BUSY_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR1_BUSY_COUNT_SHIFT (0U) +#define MMDC_MADPSR1_BUSY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR1_BUSY_COUNT_SHIFT)) & MMDC_MADPSR1_BUSY_COUNT_MASK) + +/*! @name MADPSR2 - MMDC Core Debug and Profiling Status Register 2 */ +#define MMDC_MADPSR2_RD_ACC_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR2_RD_ACC_COUNT_SHIFT (0U) +#define MMDC_MADPSR2_RD_ACC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR2_RD_ACC_COUNT_SHIFT)) & MMDC_MADPSR2_RD_ACC_COUNT_MASK) + +/*! @name MADPSR3 - MMDC Core Debug and Profiling Status Register 3 */ +#define MMDC_MADPSR3_WR_ACC_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR3_WR_ACC_COUNT_SHIFT (0U) +#define MMDC_MADPSR3_WR_ACC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR3_WR_ACC_COUNT_SHIFT)) & MMDC_MADPSR3_WR_ACC_COUNT_MASK) + +/*! @name MADPSR4 - MMDC Core Debug and Profiling Status Register 4 */ +#define MMDC_MADPSR4_RD_BYTES_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR4_RD_BYTES_COUNT_SHIFT (0U) +#define MMDC_MADPSR4_RD_BYTES_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR4_RD_BYTES_COUNT_SHIFT)) & MMDC_MADPSR4_RD_BYTES_COUNT_MASK) + +/*! @name MADPSR5 - MMDC Core Debug and Profiling Status Register 5 */ +#define MMDC_MADPSR5_WR_BYTES_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR5_WR_BYTES_COUNT_SHIFT (0U) +#define MMDC_MADPSR5_WR_BYTES_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR5_WR_BYTES_COUNT_SHIFT)) & MMDC_MADPSR5_WR_BYTES_COUNT_MASK) + +/*! @name MASBS0 - MMDC Core Step By Step Address Register */ +#define MMDC_MASBS0_SBS_ADDR_MASK (0xFFFFFFFFU) +#define MMDC_MASBS0_SBS_ADDR_SHIFT (0U) +#define MMDC_MASBS0_SBS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS0_SBS_ADDR_SHIFT)) & MMDC_MASBS0_SBS_ADDR_MASK) + +/*! @name MASBS1 - MMDC Core Step By Step Address Attributes Register */ +#define MMDC_MASBS1_SBS_VLD_MASK (0x1U) +#define MMDC_MASBS1_SBS_VLD_SHIFT (0U) +#define MMDC_MASBS1_SBS_VLD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_VLD_SHIFT)) & MMDC_MASBS1_SBS_VLD_MASK) +#define MMDC_MASBS1_SBS_TYPE_MASK (0x2U) +#define MMDC_MASBS1_SBS_TYPE_SHIFT (1U) +#define MMDC_MASBS1_SBS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_TYPE_SHIFT)) & MMDC_MASBS1_SBS_TYPE_MASK) +#define MMDC_MASBS1_SBS_LOCK_MASK (0xCU) +#define MMDC_MASBS1_SBS_LOCK_SHIFT (2U) +#define MMDC_MASBS1_SBS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_LOCK_SHIFT)) & MMDC_MASBS1_SBS_LOCK_MASK) +#define MMDC_MASBS1_SBS_PROT_MASK (0x70U) +#define MMDC_MASBS1_SBS_PROT_SHIFT (4U) +#define MMDC_MASBS1_SBS_PROT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_PROT_SHIFT)) & MMDC_MASBS1_SBS_PROT_MASK) +#define MMDC_MASBS1_SBS_SIZE_MASK (0x380U) +#define MMDC_MASBS1_SBS_SIZE_SHIFT (7U) +#define MMDC_MASBS1_SBS_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_SIZE_SHIFT)) & MMDC_MASBS1_SBS_SIZE_MASK) +#define MMDC_MASBS1_SBS_BURST_MASK (0xC00U) +#define MMDC_MASBS1_SBS_BURST_SHIFT (10U) +#define MMDC_MASBS1_SBS_BURST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_BURST_SHIFT)) & MMDC_MASBS1_SBS_BURST_MASK) +#define MMDC_MASBS1_SBS_BUFF_MASK (0x1000U) +#define MMDC_MASBS1_SBS_BUFF_SHIFT (12U) +#define MMDC_MASBS1_SBS_BUFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_BUFF_SHIFT)) & MMDC_MASBS1_SBS_BUFF_MASK) +#define MMDC_MASBS1_SBS_LEN_MASK (0xE000U) +#define MMDC_MASBS1_SBS_LEN_SHIFT (13U) +#define MMDC_MASBS1_SBS_LEN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_LEN_SHIFT)) & MMDC_MASBS1_SBS_LEN_MASK) +#define MMDC_MASBS1_SBS_AXI_ID_MASK (0xFFFF0000U) +#define MMDC_MASBS1_SBS_AXI_ID_SHIFT (16U) +#define MMDC_MASBS1_SBS_AXI_ID(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_AXI_ID_SHIFT)) & MMDC_MASBS1_SBS_AXI_ID_MASK) + +/*! @name MAGENP - MMDC Core General Purpose Register */ +#define MMDC_MAGENP_GP31_GP0_MASK (0xFFFFFFFFU) +#define MMDC_MAGENP_GP31_GP0_SHIFT (0U) +#define MMDC_MAGENP_GP31_GP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAGENP_GP31_GP0_SHIFT)) & MMDC_MAGENP_GP31_GP0_MASK) + +/*! @name MPZQHWCTRL - MMDC PHY ZQ HW control register */ +#define MMDC_MPZQHWCTRL_ZQ_MODE_MASK (0x3U) +#define MMDC_MPZQHWCTRL_ZQ_MODE_SHIFT (0U) +#define MMDC_MPZQHWCTRL_ZQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_MODE_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_MODE_MASK) +#define MMDC_MPZQHWCTRL_ZQ_HW_PER_MASK (0x3CU) +#define MMDC_MPZQHWCTRL_ZQ_HW_PER_SHIFT (2U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PER(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_PER_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_PER_MASK) +#define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_MASK (0x7C0U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_SHIFT (6U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_MASK) +#define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_MASK (0xF800U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_SHIFT (11U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_MASK) +#define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK (0x10000U) +#define MMDC_MPZQHWCTRL_ZQ_HW_FOR_SHIFT (16U) +#define MMDC_MPZQHWCTRL_ZQ_HW_FOR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_FOR_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK) +#define MMDC_MPZQHWCTRL_TZQ_INIT_MASK (0xE0000U) +#define MMDC_MPZQHWCTRL_TZQ_INIT_SHIFT (17U) +#define MMDC_MPZQHWCTRL_TZQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_TZQ_INIT_SHIFT)) & MMDC_MPZQHWCTRL_TZQ_INIT_MASK) +#define MMDC_MPZQHWCTRL_TZQ_OPER_MASK (0x700000U) +#define MMDC_MPZQHWCTRL_TZQ_OPER_SHIFT (20U) +#define MMDC_MPZQHWCTRL_TZQ_OPER(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_TZQ_OPER_SHIFT)) & MMDC_MPZQHWCTRL_TZQ_OPER_MASK) +#define MMDC_MPZQHWCTRL_TZQ_CS_MASK (0x3800000U) +#define MMDC_MPZQHWCTRL_TZQ_CS_SHIFT (23U) +#define MMDC_MPZQHWCTRL_TZQ_CS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_TZQ_CS_SHIFT)) & MMDC_MPZQHWCTRL_TZQ_CS_MASK) +#define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_MASK (0xF8000000U) +#define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_SHIFT (27U) +#define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_MASK) + +/*! @name MPZQSWCTRL - MMDC PHY ZQ SW control register */ +#define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK (0x1U) +#define MMDC_MPZQSWCTRL_ZQ_SW_FOR_SHIFT (0U) +#define MMDC_MPZQSWCTRL_ZQ_SW_FOR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_FOR_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK) +#define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK (0x2U) +#define MMDC_MPZQSWCTRL_ZQ_SW_RES_SHIFT (1U) +#define MMDC_MPZQSWCTRL_ZQ_SW_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_RES_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK) +#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK (0x7CU) +#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_SHIFT (2U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK (0xF80U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_SHIFT (7U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK (0x1000U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_SHIFT (12U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_PD_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK) +#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK (0x2000U) +#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_SHIFT (13U) +#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_SHIFT)) & MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK) +#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK (0x30000U) +#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_SHIFT (16U) +#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK) + +/*! @name MPWLGCR - MMDC PHY Write Leveling Configuration and Error Status Register */ +#define MMDC_MPWLGCR_HW_WL_EN_MASK (0x1U) +#define MMDC_MPWLGCR_HW_WL_EN_SHIFT (0U) +#define MMDC_MPWLGCR_HW_WL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_HW_WL_EN_SHIFT)) & MMDC_MPWLGCR_HW_WL_EN_MASK) +#define MMDC_MPWLGCR_SW_WL_EN_MASK (0x2U) +#define MMDC_MPWLGCR_SW_WL_EN_SHIFT (1U) +#define MMDC_MPWLGCR_SW_WL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_SW_WL_EN_SHIFT)) & MMDC_MPWLGCR_SW_WL_EN_MASK) +#define MMDC_MPWLGCR_SW_WL_CNT_EN_MASK (0x4U) +#define MMDC_MPWLGCR_SW_WL_CNT_EN_SHIFT (2U) +#define MMDC_MPWLGCR_SW_WL_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_SW_WL_CNT_EN_SHIFT)) & MMDC_MPWLGCR_SW_WL_CNT_EN_MASK) +#define MMDC_MPWLGCR_WL_SW_RES0_MASK (0x10U) +#define MMDC_MPWLGCR_WL_SW_RES0_SHIFT (4U) +#define MMDC_MPWLGCR_WL_SW_RES0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_WL_SW_RES0_SHIFT)) & MMDC_MPWLGCR_WL_SW_RES0_MASK) +#define MMDC_MPWLGCR_WL_SW_RES1_MASK (0x20U) +#define MMDC_MPWLGCR_WL_SW_RES1_SHIFT (5U) +#define MMDC_MPWLGCR_WL_SW_RES1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_WL_SW_RES1_SHIFT)) & MMDC_MPWLGCR_WL_SW_RES1_MASK) +#define MMDC_MPWLGCR_WL_HW_ERR0_MASK (0x100U) +#define MMDC_MPWLGCR_WL_HW_ERR0_SHIFT (8U) +#define MMDC_MPWLGCR_WL_HW_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_WL_HW_ERR0_SHIFT)) & MMDC_MPWLGCR_WL_HW_ERR0_MASK) +#define MMDC_MPWLGCR_WL_HW_ERR1_MASK (0x200U) +#define MMDC_MPWLGCR_WL_HW_ERR1_SHIFT (9U) +#define MMDC_MPWLGCR_WL_HW_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_WL_HW_ERR1_SHIFT)) & MMDC_MPWLGCR_WL_HW_ERR1_MASK) + +/*! @name MPWLDECTRL0 - MMDC PHY Write Leveling Delay Control Register 0 */ +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_MASK (0x7FU) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_SHIFT (0U) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_SHIFT)) & MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_MASK) +#define MMDC_MPWLDECTRL0_WL_HC_DEL0_MASK (0x100U) +#define MMDC_MPWLDECTRL0_WL_HC_DEL0_SHIFT (8U) +#define MMDC_MPWLDECTRL0_WL_HC_DEL0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_HC_DEL0_SHIFT)) & MMDC_MPWLDECTRL0_WL_HC_DEL0_MASK) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL0_MASK (0x600U) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL0_SHIFT (9U) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_CYC_DEL0_SHIFT)) & MMDC_MPWLDECTRL0_WL_CYC_DEL0_MASK) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_MASK (0x7F0000U) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_SHIFT (16U) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_SHIFT)) & MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_MASK) +#define MMDC_MPWLDECTRL0_WL_HC_DEL1_MASK (0x1000000U) +#define MMDC_MPWLDECTRL0_WL_HC_DEL1_SHIFT (24U) +#define MMDC_MPWLDECTRL0_WL_HC_DEL1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_HC_DEL1_SHIFT)) & MMDC_MPWLDECTRL0_WL_HC_DEL1_MASK) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL1_MASK (0x6000000U) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL1_SHIFT (25U) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_CYC_DEL1_SHIFT)) & MMDC_MPWLDECTRL0_WL_CYC_DEL1_MASK) + +/*! @name MPWLDECTRL1 - MMDC PHY Write Leveling Delay Control Register 1 */ +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_MASK (0x7FU) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_SHIFT (0U) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_SHIFT)) & MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_MASK) +#define MMDC_MPWLDECTRL1_WL_HC_DEL2_MASK (0x100U) +#define MMDC_MPWLDECTRL1_WL_HC_DEL2_SHIFT (8U) +#define MMDC_MPWLDECTRL1_WL_HC_DEL2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_HC_DEL2_SHIFT)) & MMDC_MPWLDECTRL1_WL_HC_DEL2_MASK) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL2_MASK (0x600U) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL2_SHIFT (9U) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_CYC_DEL2_SHIFT)) & MMDC_MPWLDECTRL1_WL_CYC_DEL2_MASK) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_MASK (0x7F0000U) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_SHIFT (16U) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_SHIFT)) & MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_MASK) +#define MMDC_MPWLDECTRL1_WL_HC_DEL3_MASK (0x1000000U) +#define MMDC_MPWLDECTRL1_WL_HC_DEL3_SHIFT (24U) +#define MMDC_MPWLDECTRL1_WL_HC_DEL3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_HC_DEL3_SHIFT)) & MMDC_MPWLDECTRL1_WL_HC_DEL3_MASK) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL3_MASK (0x6000000U) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL3_SHIFT (25U) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_CYC_DEL3_SHIFT)) & MMDC_MPWLDECTRL1_WL_CYC_DEL3_MASK) + +/*! @name MPWLDLST - MMDC PHY Write Leveling delay-line Status Register */ +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM0_MASK (0x7FU) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM0_SHIFT (0U) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDLST_WL_DL_UNIT_NUM0_SHIFT)) & MMDC_MPWLDLST_WL_DL_UNIT_NUM0_MASK) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM1_MASK (0x7F00U) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM1_SHIFT (8U) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDLST_WL_DL_UNIT_NUM1_SHIFT)) & MMDC_MPWLDLST_WL_DL_UNIT_NUM1_MASK) + +/*! @name MPODTCTRL - MMDC PHY ODT control register */ +#define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK (0x1U) +#define MMDC_MPODTCTRL_ODT_WR_PAS_EN_SHIFT (0U) +#define MMDC_MPODTCTRL_ODT_WR_PAS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT_WR_PAS_EN_SHIFT)) & MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK) +#define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK (0x2U) +#define MMDC_MPODTCTRL_ODT_WR_ACT_EN_SHIFT (1U) +#define MMDC_MPODTCTRL_ODT_WR_ACT_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT_WR_ACT_EN_SHIFT)) & MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK) +#define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK (0x4U) +#define MMDC_MPODTCTRL_ODT_RD_PAS_EN_SHIFT (2U) +#define MMDC_MPODTCTRL_ODT_RD_PAS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT_RD_PAS_EN_SHIFT)) & MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK) +#define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK (0x8U) +#define MMDC_MPODTCTRL_ODT_RD_ACT_EN_SHIFT (3U) +#define MMDC_MPODTCTRL_ODT_RD_ACT_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT_RD_ACT_EN_SHIFT)) & MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK) +#define MMDC_MPODTCTRL_ODT0_INT_RES_MASK (0x70U) +#define MMDC_MPODTCTRL_ODT0_INT_RES_SHIFT (4U) +#define MMDC_MPODTCTRL_ODT0_INT_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT0_INT_RES_SHIFT)) & MMDC_MPODTCTRL_ODT0_INT_RES_MASK) +#define MMDC_MPODTCTRL_ODT1_INT_RES_MASK (0x700U) +#define MMDC_MPODTCTRL_ODT1_INT_RES_SHIFT (8U) +#define MMDC_MPODTCTRL_ODT1_INT_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT1_INT_RES_SHIFT)) & MMDC_MPODTCTRL_ODT1_INT_RES_MASK) + +/*! @name MPRDDQBY0DL - MMDC PHY Read DQ Byte0 Delay Register */ +#define MMDC_MPRDDQBY0DL_RD_DQ0_DEL_MASK (0x7U) +#define MMDC_MPRDDQBY0DL_RD_DQ0_DEL_SHIFT (0U) +#define MMDC_MPRDDQBY0DL_RD_DQ0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ0_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ0_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ1_DEL_MASK (0x70U) +#define MMDC_MPRDDQBY0DL_RD_DQ1_DEL_SHIFT (4U) +#define MMDC_MPRDDQBY0DL_RD_DQ1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ1_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ1_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ2_DEL_MASK (0x700U) +#define MMDC_MPRDDQBY0DL_RD_DQ2_DEL_SHIFT (8U) +#define MMDC_MPRDDQBY0DL_RD_DQ2_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ2_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ2_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ3_DEL_MASK (0x7000U) +#define MMDC_MPRDDQBY0DL_RD_DQ3_DEL_SHIFT (12U) +#define MMDC_MPRDDQBY0DL_RD_DQ3_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ3_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ3_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ4_DEL_MASK (0x70000U) +#define MMDC_MPRDDQBY0DL_RD_DQ4_DEL_SHIFT (16U) +#define MMDC_MPRDDQBY0DL_RD_DQ4_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ4_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ4_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ5_DEL_MASK (0x700000U) +#define MMDC_MPRDDQBY0DL_RD_DQ5_DEL_SHIFT (20U) +#define MMDC_MPRDDQBY0DL_RD_DQ5_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ5_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ5_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ6_DEL_MASK (0x7000000U) +#define MMDC_MPRDDQBY0DL_RD_DQ6_DEL_SHIFT (24U) +#define MMDC_MPRDDQBY0DL_RD_DQ6_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ6_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ6_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ7_DEL_MASK (0x70000000U) +#define MMDC_MPRDDQBY0DL_RD_DQ7_DEL_SHIFT (28U) +#define MMDC_MPRDDQBY0DL_RD_DQ7_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ7_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ7_DEL_MASK) + +/*! @name MPRDDQBY1DL - MMDC PHY Read DQ Byte1 Delay Register */ +#define MMDC_MPRDDQBY1DL_RD_DQ8_DEL_MASK (0x7U) +#define MMDC_MPRDDQBY1DL_RD_DQ8_DEL_SHIFT (0U) +#define MMDC_MPRDDQBY1DL_RD_DQ8_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ8_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ8_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ9_DEL_MASK (0x70U) +#define MMDC_MPRDDQBY1DL_RD_DQ9_DEL_SHIFT (4U) +#define MMDC_MPRDDQBY1DL_RD_DQ9_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ9_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ9_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ10_DEL_MASK (0x700U) +#define MMDC_MPRDDQBY1DL_RD_DQ10_DEL_SHIFT (8U) +#define MMDC_MPRDDQBY1DL_RD_DQ10_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ10_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ10_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ11_DEL_MASK (0x7000U) +#define MMDC_MPRDDQBY1DL_RD_DQ11_DEL_SHIFT (12U) +#define MMDC_MPRDDQBY1DL_RD_DQ11_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ11_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ11_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ12_DEL_MASK (0x70000U) +#define MMDC_MPRDDQBY1DL_RD_DQ12_DEL_SHIFT (16U) +#define MMDC_MPRDDQBY1DL_RD_DQ12_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ12_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ12_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ13_DEL_MASK (0x700000U) +#define MMDC_MPRDDQBY1DL_RD_DQ13_DEL_SHIFT (20U) +#define MMDC_MPRDDQBY1DL_RD_DQ13_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ13_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ13_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ14_DEL_MASK (0x7000000U) +#define MMDC_MPRDDQBY1DL_RD_DQ14_DEL_SHIFT (24U) +#define MMDC_MPRDDQBY1DL_RD_DQ14_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ14_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ14_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ15_DEL_MASK (0x70000000U) +#define MMDC_MPRDDQBY1DL_RD_DQ15_DEL_SHIFT (28U) +#define MMDC_MPRDDQBY1DL_RD_DQ15_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ15_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ15_DEL_MASK) + +/*! @name MPWRDQBY0DL - MMDC PHY Write DQ Byte0 Delay Register */ +#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK (0x3U) +#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_SHIFT (0U) +#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ0_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK (0x30U) +#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_SHIFT (4U) +#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ1_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK (0x300U) +#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_SHIFT (8U) +#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ2_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK (0x3000U) +#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_SHIFT (12U) +#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ3_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK (0x30000U) +#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_SHIFT (16U) +#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ4_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK (0x300000U) +#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_SHIFT (20U) +#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ5_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK (0x3000000U) +#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_SHIFT (24U) +#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ6_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK (0x30000000U) +#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_SHIFT (28U) +#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ7_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK (0xC0000000U) +#define MMDC_MPWRDQBY0DL_WR_DM0_DEL_SHIFT (30U) +#define MMDC_MPWRDQBY0DL_WR_DM0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DM0_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK) + +/*! @name MPWRDQBY1DL - MMDC PHY Write DQ Byte1 Delay Register */ +#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK (0x3U) +#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_SHIFT (0U) +#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ8_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK (0x30U) +#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_SHIFT (4U) +#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ9_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK (0x300U) +#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_SHIFT (8U) +#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ10_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK (0x3000U) +#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_SHIFT (12U) +#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ11_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK (0x30000U) +#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_SHIFT (16U) +#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ12_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK (0x300000U) +#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_SHIFT (20U) +#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ13_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK (0x3000000U) +#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_SHIFT (24U) +#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ14_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK (0x30000000U) +#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_SHIFT (28U) +#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ15_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK (0xC0000000U) +#define MMDC_MPWRDQBY1DL_WR_DM1_DEL_SHIFT (30U) +#define MMDC_MPWRDQBY1DL_WR_DM1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DM1_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK) + +/*! @name MPWRDQBY2DL - MMDC PHY Write DQ Byte2 Delay Register */ +#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK (0x3U) +#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_SHIFT (0U) +#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ16_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK (0x30U) +#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_SHIFT (4U) +#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ17_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK (0x300U) +#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_SHIFT (8U) +#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ18_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK (0x3000U) +#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_SHIFT (12U) +#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ19_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK (0x30000U) +#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_SHIFT (16U) +#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ20_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK (0x300000U) +#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_SHIFT (20U) +#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ21_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK (0x3000000U) +#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_SHIFT (24U) +#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ22_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK (0x30000000U) +#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_SHIFT (28U) +#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ23_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK (0xC0000000U) +#define MMDC_MPWRDQBY2DL_WR_DM2_DEL_SHIFT (30U) +#define MMDC_MPWRDQBY2DL_WR_DM2_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DM2_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK) + +/*! @name MPWRDQBY3DL - MMDC PHY Write DQ Byte3 Delay Register */ +#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK (0x3U) +#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_SHIFT (0U) +#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ24_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK (0x30U) +#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_SHIFT (4U) +#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ25_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK (0x300U) +#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_SHIFT (8U) +#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ26_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK (0x3000U) +#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_SHIFT (12U) +#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ27_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK (0x30000U) +#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_SHIFT (16U) +#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ28_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK (0x300000U) +#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_SHIFT (20U) +#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ29_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK (0x3000000U) +#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_SHIFT (24U) +#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ30_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK (0x30000000U) +#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_SHIFT (28U) +#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ31_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK (0xC0000000U) +#define MMDC_MPWRDQBY3DL_WR_DM3_DEL_SHIFT (30U) +#define MMDC_MPWRDQBY3DL_WR_DM3_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DM3_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK) + +/*! @name MPDGCTRL0 - MMDC PHY Read DQS Gating Control Register 0 */ +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_MASK (0x7FU) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_SHIFT (0U) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_SHIFT)) & MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_MASK) +#define MMDC_MPDGCTRL0_DG_HC_DEL0_MASK (0xF00U) +#define MMDC_MPDGCTRL0_DG_HC_DEL0_SHIFT (8U) +#define MMDC_MPDGCTRL0_DG_HC_DEL0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_HC_DEL0_SHIFT)) & MMDC_MPDGCTRL0_DG_HC_DEL0_MASK) +#define MMDC_MPDGCTRL0_HW_DG_ERR_MASK (0x1000U) +#define MMDC_MPDGCTRL0_HW_DG_ERR_SHIFT (12U) +#define MMDC_MPDGCTRL0_HW_DG_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_HW_DG_ERR_SHIFT)) & MMDC_MPDGCTRL0_HW_DG_ERR_MASK) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_MASK (0x7F0000U) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_SHIFT (16U) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_SHIFT)) & MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_MASK) +#define MMDC_MPDGCTRL0_DG_EXT_UP_MASK (0x800000U) +#define MMDC_MPDGCTRL0_DG_EXT_UP_SHIFT (23U) +#define MMDC_MPDGCTRL0_DG_EXT_UP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_EXT_UP_SHIFT)) & MMDC_MPDGCTRL0_DG_EXT_UP_MASK) +#define MMDC_MPDGCTRL0_DG_HC_DEL1_MASK (0xF000000U) +#define MMDC_MPDGCTRL0_DG_HC_DEL1_SHIFT (24U) +#define MMDC_MPDGCTRL0_DG_HC_DEL1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_HC_DEL1_SHIFT)) & MMDC_MPDGCTRL0_DG_HC_DEL1_MASK) +#define MMDC_MPDGCTRL0_HW_DG_EN_MASK (0x10000000U) +#define MMDC_MPDGCTRL0_HW_DG_EN_SHIFT (28U) +#define MMDC_MPDGCTRL0_HW_DG_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_HW_DG_EN_SHIFT)) & MMDC_MPDGCTRL0_HW_DG_EN_MASK) +#define MMDC_MPDGCTRL0_DG_DIS_MASK (0x20000000U) +#define MMDC_MPDGCTRL0_DG_DIS_SHIFT (29U) +#define MMDC_MPDGCTRL0_DG_DIS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_DIS_SHIFT)) & MMDC_MPDGCTRL0_DG_DIS_MASK) +#define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK (0x40000000U) +#define MMDC_MPDGCTRL0_DG_CMP_CYC_SHIFT (30U) +#define MMDC_MPDGCTRL0_DG_CMP_CYC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_CMP_CYC_SHIFT)) & MMDC_MPDGCTRL0_DG_CMP_CYC_MASK) +#define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK (0x80000000U) +#define MMDC_MPDGCTRL0_RST_RD_FIFO_SHIFT (31U) +#define MMDC_MPDGCTRL0_RST_RD_FIFO(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_RST_RD_FIFO_SHIFT)) & MMDC_MPDGCTRL0_RST_RD_FIFO_MASK) + +/*! @name MPDGDLST0 - MMDC PHY Read DQS Gating delay-line Status Register */ +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_MASK (0x7FU) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_SHIFT (0U) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_SHIFT)) & MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_MASK) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_MASK (0x7F00U) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_SHIFT (8U) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_SHIFT)) & MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_MASK) + +/*! @name MPRDDLCTL - MMDC PHY Read delay-lines Configuration Register */ +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK (0x7FU) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_SHIFT (0U) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_SHIFT)) & MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK (0x7F00U) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_SHIFT (8U) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_SHIFT)) & MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK) + +/*! @name MPRDDLST - MMDC PHY Read delay-lines Status Register */ +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM0_MASK (0x7FU) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM0_SHIFT (0U) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLST_RD_DL_UNIT_NUM0_SHIFT)) & MMDC_MPRDDLST_RD_DL_UNIT_NUM0_MASK) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM1_MASK (0x7F00U) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM1_SHIFT (8U) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLST_RD_DL_UNIT_NUM1_SHIFT)) & MMDC_MPRDDLST_RD_DL_UNIT_NUM1_MASK) + +/*! @name MPWRDLCTL - MMDC PHY Write delay-lines Configuration Register */ +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK (0x7FU) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_SHIFT (0U) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_SHIFT)) & MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK (0x7F00U) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_SHIFT (8U) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_SHIFT)) & MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK) + +/*! @name MPWRDLST - MMDC PHY Write delay-lines Status Register */ +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM0_MASK (0x7FU) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM0_SHIFT (0U) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLST_WR_DL_UNIT_NUM0_SHIFT)) & MMDC_MPWRDLST_WR_DL_UNIT_NUM0_MASK) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM1_MASK (0x7F00U) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM1_SHIFT (8U) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLST_WR_DL_UNIT_NUM1_SHIFT)) & MMDC_MPWRDLST_WR_DL_UNIT_NUM1_MASK) + +/*! @name MPSDCTRL - MMDC PHY CK Control Register */ +#define MMDC_MPSDCTRL_SDCLK0_DEL_MASK (0x300U) +#define MMDC_MPSDCTRL_SDCLK0_DEL_SHIFT (8U) +#define MMDC_MPSDCTRL_SDCLK0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSDCTRL_SDCLK0_DEL_SHIFT)) & MMDC_MPSDCTRL_SDCLK0_DEL_MASK) +#define MMDC_MPSDCTRL_SDCLK1_DEL_MASK (0xC00U) +#define MMDC_MPSDCTRL_SDCLK1_DEL_SHIFT (10U) +#define MMDC_MPSDCTRL_SDCLK1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSDCTRL_SDCLK1_DEL_SHIFT)) & MMDC_MPSDCTRL_SDCLK1_DEL_MASK) + +/*! @name MPZQLP2CTL - MMDC ZQ LPDDR2 HW Control Register */ +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK (0x1FFU) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_SHIFT (0U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_SHIFT)) & MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK (0xFF0000U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_SHIFT (16U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_SHIFT)) & MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK (0x7F000000U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_SHIFT (24U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_SHIFT)) & MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK) + +/*! @name MPRDDLHWCTL - MMDC PHY Read Delay HW Calibration Control Register */ +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_MASK (0x1U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_SHIFT (0U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_MASK) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_MASK (0x2U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_SHIFT (1U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_MASK) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK (0x10U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_SHIFT (4U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_EN_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK (0x20U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_SHIFT (5U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK) + +/*! @name MPWRDLHWCTL - MMDC PHY Write Delay HW Calibration Control Register */ +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_MASK (0x1U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_SHIFT (0U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_MASK) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_MASK (0x2U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_SHIFT (1U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_MASK) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK (0x10U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_SHIFT (4U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_EN_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK (0x20U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_SHIFT (5U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK) + +/*! @name MPRDDLHWST0 - MMDC PHY Read Delay HW Calibration Status Register 0 */ +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_MASK (0x7FU) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_SHIFT (0U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_MASK) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP0_MASK (0x7F00U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP0_SHIFT (8U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_UP0_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_UP0_MASK) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_MASK (0x7F0000U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_SHIFT (16U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_MASK) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP1_MASK (0x7F000000U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP1_SHIFT (24U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_UP1_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_UP1_MASK) + +/*! @name MPWRDLHWST0 - MMDC PHY Write Delay HW Calibration Status Register 0 */ +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_MASK (0x7FU) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_SHIFT (0U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_MASK) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP0_MASK (0x7F00U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP0_SHIFT (8U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_UP0_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_UP0_MASK) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_MASK (0x7F0000U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_SHIFT (16U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_MASK) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP1_MASK (0x7F000000U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP1_SHIFT (24U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_UP1_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_UP1_MASK) + +/*! @name MPWLHWERR - MMDC PHY Write Leveling HW Error Register */ +#define MMDC_MPWLHWERR_HW_WL0_DQ_MASK (0xFFU) +#define MMDC_MPWLHWERR_HW_WL0_DQ_SHIFT (0U) +#define MMDC_MPWLHWERR_HW_WL0_DQ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLHWERR_HW_WL0_DQ_SHIFT)) & MMDC_MPWLHWERR_HW_WL0_DQ_MASK) +#define MMDC_MPWLHWERR_HW_WL1_DQ_MASK (0xFF00U) +#define MMDC_MPWLHWERR_HW_WL1_DQ_SHIFT (8U) +#define MMDC_MPWLHWERR_HW_WL1_DQ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLHWERR_HW_WL1_DQ_SHIFT)) & MMDC_MPWLHWERR_HW_WL1_DQ_MASK) + +/*! @name MPDGHWST0 - MMDC PHY Read DQS Gating HW Status Register 0 */ +#define MMDC_MPDGHWST0_HW_DG_LOW0_MASK (0x7FFU) +#define MMDC_MPDGHWST0_HW_DG_LOW0_SHIFT (0U) +#define MMDC_MPDGHWST0_HW_DG_LOW0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGHWST0_HW_DG_LOW0_SHIFT)) & MMDC_MPDGHWST0_HW_DG_LOW0_MASK) +#define MMDC_MPDGHWST0_HW_DG_UP0_MASK (0x7FF0000U) +#define MMDC_MPDGHWST0_HW_DG_UP0_SHIFT (16U) +#define MMDC_MPDGHWST0_HW_DG_UP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGHWST0_HW_DG_UP0_SHIFT)) & MMDC_MPDGHWST0_HW_DG_UP0_MASK) + +/*! @name MPDGHWST1 - MMDC PHY Read DQS Gating HW Status Register 1 */ +#define MMDC_MPDGHWST1_HW_DG_LOW1_MASK (0x7FFU) +#define MMDC_MPDGHWST1_HW_DG_LOW1_SHIFT (0U) +#define MMDC_MPDGHWST1_HW_DG_LOW1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGHWST1_HW_DG_LOW1_SHIFT)) & MMDC_MPDGHWST1_HW_DG_LOW1_MASK) +#define MMDC_MPDGHWST1_HW_DG_UP1_MASK (0x7FF0000U) +#define MMDC_MPDGHWST1_HW_DG_UP1_SHIFT (16U) +#define MMDC_MPDGHWST1_HW_DG_UP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGHWST1_HW_DG_UP1_SHIFT)) & MMDC_MPDGHWST1_HW_DG_UP1_MASK) + +/*! @name MPPDCMPR1 - MMDC PHY Pre-defined Compare Register 1 */ +#define MMDC_MPPDCMPR1_PDV1_MASK (0xFFFFU) +#define MMDC_MPPDCMPR1_PDV1_SHIFT (0U) +#define MMDC_MPPDCMPR1_PDV1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR1_PDV1_SHIFT)) & MMDC_MPPDCMPR1_PDV1_MASK) +#define MMDC_MPPDCMPR1_PDV2_MASK (0xFFFF0000U) +#define MMDC_MPPDCMPR1_PDV2_SHIFT (16U) +#define MMDC_MPPDCMPR1_PDV2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR1_PDV2_SHIFT)) & MMDC_MPPDCMPR1_PDV2_MASK) + +/*! @name MPPDCMPR2 - MMDC PHY Pre-defined Compare and CA delay-line Configuration Register */ +#define MMDC_MPPDCMPR2_MPR_CMP_MASK (0x1U) +#define MMDC_MPPDCMPR2_MPR_CMP_SHIFT (0U) +#define MMDC_MPPDCMPR2_MPR_CMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_MPR_CMP_SHIFT)) & MMDC_MPPDCMPR2_MPR_CMP_MASK) +#define MMDC_MPPDCMPR2_MPR_FULL_CMP_MASK (0x2U) +#define MMDC_MPPDCMPR2_MPR_FULL_CMP_SHIFT (1U) +#define MMDC_MPPDCMPR2_MPR_FULL_CMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_MPR_FULL_CMP_SHIFT)) & MMDC_MPPDCMPR2_MPR_FULL_CMP_MASK) +#define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_MASK (0x4U) +#define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_SHIFT (2U) +#define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_SHIFT)) & MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_MASK) +#define MMDC_MPPDCMPR2_ZQ_OFFSET_EN_MASK (0x8U) +#define MMDC_MPPDCMPR2_ZQ_OFFSET_EN_SHIFT (3U) +#define MMDC_MPPDCMPR2_ZQ_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_ZQ_OFFSET_EN_SHIFT)) & MMDC_MPPDCMPR2_ZQ_OFFSET_EN_MASK) +#define MMDC_MPPDCMPR2_ZQ_PD_OFFSET_MASK (0xF0U) +#define MMDC_MPPDCMPR2_ZQ_PD_OFFSET_SHIFT (4U) +#define MMDC_MPPDCMPR2_ZQ_PD_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_ZQ_PD_OFFSET_SHIFT)) & MMDC_MPPDCMPR2_ZQ_PD_OFFSET_MASK) +#define MMDC_MPPDCMPR2_ZQ_PU_OFFSET_MASK (0xF00U) +#define MMDC_MPPDCMPR2_ZQ_PU_OFFSET_SHIFT (8U) +#define MMDC_MPPDCMPR2_ZQ_PU_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_ZQ_PU_OFFSET_SHIFT)) & MMDC_MPPDCMPR2_ZQ_PU_OFFSET_MASK) +#define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_MASK (0x7F0000U) +#define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_SHIFT (16U) +#define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_SHIFT)) & MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_MASK) +#define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_MASK (0x7F000000U) +#define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_SHIFT (24U) +#define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_SHIFT)) & MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_MASK) + +/*! @name MPSWDAR0 - MMDC PHY SW Dummy Access Register */ +#define MMDC_MPSWDAR0_SW_DUMMY_WR_MASK (0x1U) +#define MMDC_MPSWDAR0_SW_DUMMY_WR_SHIFT (0U) +#define MMDC_MPSWDAR0_SW_DUMMY_WR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUMMY_WR_SHIFT)) & MMDC_MPSWDAR0_SW_DUMMY_WR_MASK) +#define MMDC_MPSWDAR0_SW_DUMMY_RD_MASK (0x2U) +#define MMDC_MPSWDAR0_SW_DUMMY_RD_SHIFT (1U) +#define MMDC_MPSWDAR0_SW_DUMMY_RD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUMMY_RD_SHIFT)) & MMDC_MPSWDAR0_SW_DUMMY_RD_MASK) +#define MMDC_MPSWDAR0_SW_DUM_CMP0_MASK (0x4U) +#define MMDC_MPSWDAR0_SW_DUM_CMP0_SHIFT (2U) +#define MMDC_MPSWDAR0_SW_DUM_CMP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUM_CMP0_SHIFT)) & MMDC_MPSWDAR0_SW_DUM_CMP0_MASK) +#define MMDC_MPSWDAR0_SW_DUM_CMP1_MASK (0x8U) +#define MMDC_MPSWDAR0_SW_DUM_CMP1_SHIFT (3U) +#define MMDC_MPSWDAR0_SW_DUM_CMP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUM_CMP1_SHIFT)) & MMDC_MPSWDAR0_SW_DUM_CMP1_MASK) + +/*! @name MPSWDRDR0 - MMDC PHY SW Dummy Read Data Register 0 */ +#define MMDC_MPSWDRDR0_DUM_RD0_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR0_DUM_RD0_SHIFT (0U) +#define MMDC_MPSWDRDR0_DUM_RD0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR0_DUM_RD0_SHIFT)) & MMDC_MPSWDRDR0_DUM_RD0_MASK) + +/*! @name MPSWDRDR1 - MMDC PHY SW Dummy Read Data Register 1 */ +#define MMDC_MPSWDRDR1_DUM_RD1_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR1_DUM_RD1_SHIFT (0U) +#define MMDC_MPSWDRDR1_DUM_RD1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR1_DUM_RD1_SHIFT)) & MMDC_MPSWDRDR1_DUM_RD1_MASK) + +/*! @name MPSWDRDR2 - MMDC PHY SW Dummy Read Data Register 2 */ +#define MMDC_MPSWDRDR2_DUM_RD2_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR2_DUM_RD2_SHIFT (0U) +#define MMDC_MPSWDRDR2_DUM_RD2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR2_DUM_RD2_SHIFT)) & MMDC_MPSWDRDR2_DUM_RD2_MASK) + +/*! @name MPSWDRDR3 - MMDC PHY SW Dummy Read Data Register 3 */ +#define MMDC_MPSWDRDR3_DUM_RD3_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR3_DUM_RD3_SHIFT (0U) +#define MMDC_MPSWDRDR3_DUM_RD3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR3_DUM_RD3_SHIFT)) & MMDC_MPSWDRDR3_DUM_RD3_MASK) + +/*! @name MPSWDRDR4 - MMDC PHY SW Dummy Read Data Register 4 */ +#define MMDC_MPSWDRDR4_DUM_RD4_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR4_DUM_RD4_SHIFT (0U) +#define MMDC_MPSWDRDR4_DUM_RD4(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR4_DUM_RD4_SHIFT)) & MMDC_MPSWDRDR4_DUM_RD4_MASK) + +/*! @name MPSWDRDR5 - MMDC PHY SW Dummy Read Data Register 5 */ +#define MMDC_MPSWDRDR5_DUM_RD5_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR5_DUM_RD5_SHIFT (0U) +#define MMDC_MPSWDRDR5_DUM_RD5(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR5_DUM_RD5_SHIFT)) & MMDC_MPSWDRDR5_DUM_RD5_MASK) + +/*! @name MPSWDRDR6 - MMDC PHY SW Dummy Read Data Register 6 */ +#define MMDC_MPSWDRDR6_DUM_RD6_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR6_DUM_RD6_SHIFT (0U) +#define MMDC_MPSWDRDR6_DUM_RD6(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR6_DUM_RD6_SHIFT)) & MMDC_MPSWDRDR6_DUM_RD6_MASK) + +/*! @name MPSWDRDR7 - MMDC PHY SW Dummy Read Data Register 7 */ +#define MMDC_MPSWDRDR7_DUM_RD7_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR7_DUM_RD7_SHIFT (0U) +#define MMDC_MPSWDRDR7_DUM_RD7(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR7_DUM_RD7_SHIFT)) & MMDC_MPSWDRDR7_DUM_RD7_MASK) + +/*! @name MPMUR0 - MMDC PHY Measure Unit Register */ +#define MMDC_MPMUR0_MU_BYP_VAL_MASK (0x3FFU) +#define MMDC_MPMUR0_MU_BYP_VAL_SHIFT (0U) +#define MMDC_MPMUR0_MU_BYP_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_MU_BYP_VAL_SHIFT)) & MMDC_MPMUR0_MU_BYP_VAL_MASK) +#define MMDC_MPMUR0_MU_BYP_EN_MASK (0x400U) +#define MMDC_MPMUR0_MU_BYP_EN_SHIFT (10U) +#define MMDC_MPMUR0_MU_BYP_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_MU_BYP_EN_SHIFT)) & MMDC_MPMUR0_MU_BYP_EN_MASK) +#define MMDC_MPMUR0_FRC_MSR_MASK (0x800U) +#define MMDC_MPMUR0_FRC_MSR_SHIFT (11U) +#define MMDC_MPMUR0_FRC_MSR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_FRC_MSR_SHIFT)) & MMDC_MPMUR0_FRC_MSR_MASK) +#define MMDC_MPMUR0_MU_UNIT_DEL_NUM_MASK (0x3FF0000U) +#define MMDC_MPMUR0_MU_UNIT_DEL_NUM_SHIFT (16U) +#define MMDC_MPMUR0_MU_UNIT_DEL_NUM(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_MU_UNIT_DEL_NUM_SHIFT)) & MMDC_MPMUR0_MU_UNIT_DEL_NUM_MASK) + +/*! @name MPWRCADL - MMDC Write CA delay-line controller */ +#define MMDC_MPWRCADL_WR_CA0_DEL_MASK (0x3U) +#define MMDC_MPWRCADL_WR_CA0_DEL_SHIFT (0U) +#define MMDC_MPWRCADL_WR_CA0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA0_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA0_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA1_DEL_MASK (0xCU) +#define MMDC_MPWRCADL_WR_CA1_DEL_SHIFT (2U) +#define MMDC_MPWRCADL_WR_CA1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA1_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA1_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA2_DEL_MASK (0x30U) +#define MMDC_MPWRCADL_WR_CA2_DEL_SHIFT (4U) +#define MMDC_MPWRCADL_WR_CA2_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA2_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA2_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA3_DEL_MASK (0xC0U) +#define MMDC_MPWRCADL_WR_CA3_DEL_SHIFT (6U) +#define MMDC_MPWRCADL_WR_CA3_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA3_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA3_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA4_DEL_MASK (0x300U) +#define MMDC_MPWRCADL_WR_CA4_DEL_SHIFT (8U) +#define MMDC_MPWRCADL_WR_CA4_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA4_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA4_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA5_DEL_MASK (0xC00U) +#define MMDC_MPWRCADL_WR_CA5_DEL_SHIFT (10U) +#define MMDC_MPWRCADL_WR_CA5_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA5_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA5_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA6_DEL_MASK (0x3000U) +#define MMDC_MPWRCADL_WR_CA6_DEL_SHIFT (12U) +#define MMDC_MPWRCADL_WR_CA6_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA6_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA6_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA7_DEL_MASK (0xC000U) +#define MMDC_MPWRCADL_WR_CA7_DEL_SHIFT (14U) +#define MMDC_MPWRCADL_WR_CA7_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA7_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA7_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA8_DEL_MASK (0x30000U) +#define MMDC_MPWRCADL_WR_CA8_DEL_SHIFT (16U) +#define MMDC_MPWRCADL_WR_CA8_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA8_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA8_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA9_DEL_MASK (0xC0000U) +#define MMDC_MPWRCADL_WR_CA9_DEL_SHIFT (18U) +#define MMDC_MPWRCADL_WR_CA9_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA9_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA9_DEL_MASK) + +/*! @name MPDCCR - MMDC Duty Cycle Control Register */ +#define MMDC_MPDCCR_WR_DQS0_FT_DCC_MASK (0x7U) +#define MMDC_MPDCCR_WR_DQS0_FT_DCC_SHIFT (0U) +#define MMDC_MPDCCR_WR_DQS0_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_WR_DQS0_FT_DCC_SHIFT)) & MMDC_MPDCCR_WR_DQS0_FT_DCC_MASK) +#define MMDC_MPDCCR_WR_DQS1_FT_DCC_MASK (0x38U) +#define MMDC_MPDCCR_WR_DQS1_FT_DCC_SHIFT (3U) +#define MMDC_MPDCCR_WR_DQS1_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_WR_DQS1_FT_DCC_SHIFT)) & MMDC_MPDCCR_WR_DQS1_FT_DCC_MASK) +#define MMDC_MPDCCR_CK_FT0_DCC_MASK (0x7000U) +#define MMDC_MPDCCR_CK_FT0_DCC_SHIFT (12U) +#define MMDC_MPDCCR_CK_FT0_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_CK_FT0_DCC_SHIFT)) & MMDC_MPDCCR_CK_FT0_DCC_MASK) +#define MMDC_MPDCCR_CK_FT1_DCC_MASK (0x70000U) +#define MMDC_MPDCCR_CK_FT1_DCC_SHIFT (16U) +#define MMDC_MPDCCR_CK_FT1_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_CK_FT1_DCC_SHIFT)) & MMDC_MPDCCR_CK_FT1_DCC_MASK) +#define MMDC_MPDCCR_RD_DQS0_FT_DCC_MASK (0x380000U) +#define MMDC_MPDCCR_RD_DQS0_FT_DCC_SHIFT (19U) +#define MMDC_MPDCCR_RD_DQS0_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_RD_DQS0_FT_DCC_SHIFT)) & MMDC_MPDCCR_RD_DQS0_FT_DCC_MASK) +#define MMDC_MPDCCR_RD_DQS1_FT_DCC_MASK (0x1C00000U) +#define MMDC_MPDCCR_RD_DQS1_FT_DCC_SHIFT (22U) +#define MMDC_MPDCCR_RD_DQS1_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_RD_DQS1_FT_DCC_SHIFT)) & MMDC_MPDCCR_RD_DQS1_FT_DCC_MASK) + + +/*! + * @} + */ /* end of group MMDC_Register_Masks */ + + +/* MMDC - Peripheral instance base addresses */ +/** Peripheral MMDC base address */ +#define MMDC_BASE (0x21B0000u) +/** Peripheral MMDC base pointer */ +#define MMDC ((MMDC_Type *)MMDC_BASE) +/** Array initializer of MMDC peripheral base addresses */ +#define MMDC_BASE_ADDRS { MMDC_BASE } +/** Array initializer of MMDC peripheral base pointers */ +#define MMDC_BASE_PTRS { MMDC } +/* MMDC max frequency (MHz). */ +#define MMDC_MAX_FREQUENCY (400) +/* MMDC device start address. */ +#define MMDC_DEVICE_START_ADDRESS (0x80000000U) + + +/*! + * @} + */ /* end of group MMDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OCOTP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer + * @{ + */ + +/** OCOTP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< OTP Controller Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */ + __IO uint32_t TIMING; /**< OTP Controller Timing Register, offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DATA; /**< OTP Controller Write Data Register, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t READ_CTRL; /**< OTP Controller Read Control Register, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t READ_FUSE_DATA; /**< OTP Controller Read Fuse Data Register, offset: 0x40 */ + uint8_t RESERVED_3[12]; + __IO uint32_t SW_STICKY; /**< Sticky bit Register, offset: 0x50 */ + uint8_t RESERVED_4[12]; + __IO uint32_t SCS; /**< Software Controllable Signals Register, offset: 0x60 */ + __IO uint32_t SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */ + __IO uint32_t SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */ + __IO uint32_t SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */ + __IO uint32_t CRC_ADDR; /**< OTP Controller CRC Test Address, offset: 0x70 */ + uint8_t RESERVED_5[12]; + __IO uint32_t CRC_VALUE; /**< OTP Controller CRC Value Register, offset: 0x80 */ + uint8_t RESERVED_6[12]; + __I uint32_t VERSION; /**< OTP Controller Version Register, offset: 0x90 */ + uint8_t RESERVED_7[108]; + __IO uint32_t TIMING2; /**< OTP Controller Timing Register 2, offset: 0x100 */ + uint8_t RESERVED_8[764]; + __IO uint32_t LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */ + uint8_t RESERVED_9[12]; + __IO uint32_t CFG0; /**< Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CFG1; /**< Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420 */ + uint8_t RESERVED_11[12]; + __IO uint32_t CFG2; /**< Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.), offset: 0x430 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CFG3; /**< Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.), offset: 0x440 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CFG4; /**< Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CFG5; /**< Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CFG6; /**< Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.), offset: 0x470 */ + uint8_t RESERVED_16[12]; + __IO uint32_t MEM0; /**< Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480 */ + uint8_t RESERVED_17[12]; + __IO uint32_t MEM1; /**< Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490 */ + uint8_t RESERVED_18[12]; + __IO uint32_t MEM2; /**< Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0 */ + uint8_t RESERVED_19[12]; + __IO uint32_t MEM3; /**< Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0 */ + uint8_t RESERVED_20[12]; + __IO uint32_t MEM4; /**< Value of OTP Bank1 Word4 (Memory Related Info.), offset: 0x4C0 */ + uint8_t RESERVED_21[12]; + __IO uint32_t ANA0; /**< Value of OTP Bank1 Word5 (Memory Related Info.), offset: 0x4D0 */ + uint8_t RESERVED_22[12]; + __IO uint32_t ANA1; /**< Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.), offset: 0x4E0 */ + uint8_t RESERVED_23[12]; + __IO uint32_t ANA2; /**< Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.), offset: 0x4F0 */ + uint8_t RESERVED_24[12]; + __IO uint32_t OTPMK0; /**< Value of OTP Bank2 Word0 (OTPMK Key), offset: 0x500 */ + uint8_t RESERVED_25[12]; + __IO uint32_t OTPMK1; /**< Value of OTP Bank2 Word1 (OTPMK Key), offset: 0x510 */ + uint8_t RESERVED_26[12]; + __IO uint32_t OTPMK2; /**< Value of OTP Bank2 Word2 (OTPMK Key), offset: 0x520 */ + uint8_t RESERVED_27[12]; + __IO uint32_t OTPMK3; /**< Value of OTP Bank2 Word3 (OTPMK Key), offset: 0x530 */ + uint8_t RESERVED_28[12]; + __IO uint32_t OTPMK4; /**< Value of OTP Bank2 Word4 (OTPMK Key), offset: 0x540 */ + uint8_t RESERVED_29[12]; + __IO uint32_t OTPMK5; /**< Value of OTP Bank2 Word5 (OTPMK Key), offset: 0x550 */ + uint8_t RESERVED_30[12]; + __IO uint32_t OTPMK6; /**< Value of OTP Bank2 Word6 (OTPMK Key), offset: 0x560 */ + uint8_t RESERVED_31[12]; + __IO uint32_t OTPMK7; /**< Value of OTP Bank2 Word7 (OTPMK Key), offset: 0x570 */ + uint8_t RESERVED_32[12]; + __IO uint32_t SRK0; /**< Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580 */ + uint8_t RESERVED_33[12]; + __IO uint32_t SRK1; /**< Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590 */ + uint8_t RESERVED_34[12]; + __IO uint32_t SRK2; /**< Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0 */ + uint8_t RESERVED_35[12]; + __IO uint32_t SRK3; /**< Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0 */ + uint8_t RESERVED_36[12]; + __IO uint32_t SRK4; /**< Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0 */ + uint8_t RESERVED_37[12]; + __IO uint32_t SRK5; /**< Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0 */ + uint8_t RESERVED_38[12]; + __IO uint32_t SRK6; /**< Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0 */ + uint8_t RESERVED_39[12]; + __IO uint32_t SRK7; /**< Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0 */ + uint8_t RESERVED_40[12]; + __IO uint32_t SJC_RESP0; /**< Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600 */ + uint8_t RESERVED_41[12]; + __IO uint32_t SJC_RESP1; /**< Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610 */ + uint8_t RESERVED_42[12]; + __IO uint32_t MAC0; /**< Value of OTP Bank4 Word2 (MAC Address), offset: 0x620 */ + uint8_t RESERVED_43[12]; + __IO uint32_t MAC1; /**< Value of OTP Bank4 Word3 (MAC Address), offset: 0x630 */ + uint8_t RESERVED_44[12]; + __IO uint32_t MAC; /**< Value of OTP Bank4 Word4 (MAC Address) (OCOTP_RESERVED), offset: 0x640 */ + uint8_t RESERVED_45[12]; + __IO uint32_t CRC; /**< Value of OTP Bank4 Word5 (CRC Key), offset: 0x650 */ + uint8_t RESERVED_46[12]; + __IO uint32_t GP1; /**< Value of OTP Bank4 Word6 (General Purpose Customer Defined Info), offset: 0x660 */ + uint8_t RESERVED_47[12]; + __IO uint32_t GP2; /**< Value of OTP Bank4 Word7 (General Purpose Customer Defined Info), offset: 0x670 */ + uint8_t RESERVED_48[12]; + __IO uint32_t SW_GP0; /**< Value of OTP Bank5 Word0 (SW GP), offset: 0x680 */ + uint8_t RESERVED_49[12]; + __IO uint32_t SW_GP1; /**< Value of OTP Bank5 Word1 (SW GP), offset: 0x690 */ + uint8_t RESERVED_50[12]; + __IO uint32_t SW_GP2; /**< Value of OTP Bank5 Word2 (SW GP), offset: 0x6A0 */ + uint8_t RESERVED_51[12]; + __IO uint32_t SW_GP3; /**< Value of OTP Bank5 Word3 (SW GP), offset: 0x6B0 */ + uint8_t RESERVED_52[12]; + __IO uint32_t SW_GP4; /**< Value of OTP Bank5 Word4 (SW GP), offset: 0x6C0 */ + uint8_t RESERVED_53[12]; + __IO uint32_t MISC_CONF; /**< Value of OTP Bank5 Word5 (Misc Conf), offset: 0x6D0 */ + uint8_t RESERVED_54[12]; + __IO uint32_t FIELD_RETURN; /**< Value of OTP Bank5 Word6 (Field Return), offset: 0x6E0 */ + uint8_t RESERVED_55[12]; + __IO uint32_t SRK_REVOKE; /**< Value of OTP Bank5 Word7 (SRK Revoke), offset: 0x6F0 */ + uint8_t RESERVED_56[268]; + __IO uint32_t ROM_PATCH0; /**< Value of OTP Bank6 Word0 (ROM Patch), offset: 0x800 */ + uint8_t RESERVED_57[12]; + __IO uint32_t ROM_PATCH1; /**< Value of OTP Bank6 Word1 (ROM Patch), offset: 0x810 */ + uint8_t RESERVED_58[12]; + __IO uint32_t ROM_PATCH2; /**< Value of OTP Bank6 Word2 (ROM Patch), offset: 0x820 */ + uint8_t RESERVED_59[12]; + __IO uint32_t ROM_PATCH3; /**< Value of OTP Bank6 Word3 (ROM Patch), offset: 0x830 */ + uint8_t RESERVED_60[12]; + __IO uint32_t ROM_PATCH4; /**< Value of OTP Bank6 Word4 (ROM Patch), offset: 0x840 */ + uint8_t RESERVED_61[12]; + __IO uint32_t ROM_PATCH5; /**< Value of OTP Bank6 Word5 (ROM Patch), offset: 0x850 */ + uint8_t RESERVED_62[12]; + __IO uint32_t ROM_PATCH6; /**< Value of OTP Bank6 Word6 (ROM Patch), offset: 0x860 */ + uint8_t RESERVED_63[12]; + __IO uint32_t ROM_PATCH7; /**< Value of OTP Bank6 Word7 (ROM Patch), offset: 0x870 */ + uint8_t RESERVED_64[12]; + __IO uint32_t GP3_0; /**< Value of OTP Bank7 Word0 (General Purpose Customer Defined Info), offset: 0x880 */ + uint8_t RESERVED_65[12]; + __IO uint32_t GP3_1; /**< Value of OTP Bank7 Word1 (General Purpose Customer Defined Info), offset: 0x890 */ + uint8_t RESERVED_66[12]; + __IO uint32_t GP3_2; /**< Value of OTP Bank7 Word2 (General Purpose Customer Defined Info), offset: 0x8A0 */ + uint8_t RESERVED_67[12]; + __IO uint32_t GP3_3; /**< Value of OTP Bank7 Word3 (General Purpose Customer Defined Info), offset: 0x8B0 */ + uint8_t RESERVED_68[12]; + __IO uint32_t GP3_4; /**< Value of OTP Bank8 Word4 (General Purpose Customer Defined Info), offset: 0x8C0 */ + uint8_t RESERVED_69[12]; + __IO uint32_t GP4_0; /**< Value of OTP Bank7 Word5 (General Purpose Customer Defined Info), offset: 0x8D0 */ + uint8_t RESERVED_70[12]; + __IO uint32_t GP4_1; /**< Value of OTP Bank7 Word6 (General Purpose Customer Defined Info), offset: 0x8E0 */ + uint8_t RESERVED_71[12]; + __IO uint32_t GP4_2; /**< Value of OTP Bank7 Word7 (General Purpose Customer Defined Info), offset: 0x8F0 */ +} OCOTP_Type; + +/* ---------------------------------------------------------------------------- + -- OCOTP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Register_Masks OCOTP Register Masks + * @{ + */ + +/*! @name CTRL - OTP Controller Control Register */ +#define OCOTP_CTRL_ADDR_MASK (0x7FU) +#define OCOTP_CTRL_ADDR_SHIFT (0U) +#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK) +#define OCOTP_CTRL_RSVD0_MASK (0x80U) +#define OCOTP_CTRL_RSVD0_SHIFT (7U) +#define OCOTP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RSVD0_SHIFT)) & OCOTP_CTRL_RSVD0_MASK) +#define OCOTP_CTRL_BUSY_MASK (0x100U) +#define OCOTP_CTRL_BUSY_SHIFT (8U) +#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK) +#define OCOTP_CTRL_ERROR_MASK (0x200U) +#define OCOTP_CTRL_ERROR_SHIFT (9U) +#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK) +#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CRC_TEST_SHIFT)) & OCOTP_CTRL_CRC_TEST_MASK) +#define OCOTP_CTRL_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CRC_FAIL_SHIFT)) & OCOTP_CTRL_CRC_FAIL_MASK) +#define OCOTP_CTRL_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RSVD1_SHIFT)) & OCOTP_CTRL_RSVD1_MASK) +#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK) + +/*! @name CTRL_SET - OTP Controller Control Register */ +#define OCOTP_CTRL_SET_ADDR_MASK (0x7FU) +#define OCOTP_CTRL_SET_ADDR_SHIFT (0U) +#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK) +#define OCOTP_CTRL_SET_RSVD0_MASK (0x80U) +#define OCOTP_CTRL_SET_RSVD0_SHIFT (7U) +#define OCOTP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RSVD0_SHIFT)) & OCOTP_CTRL_SET_RSVD0_MASK) +#define OCOTP_CTRL_SET_BUSY_MASK (0x100U) +#define OCOTP_CTRL_SET_BUSY_SHIFT (8U) +#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK) +#define OCOTP_CTRL_SET_ERROR_MASK (0x200U) +#define OCOTP_CTRL_SET_ERROR_SHIFT (9U) +#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_SET_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_SET_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_SET_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_CRC_TEST_SHIFT)) & OCOTP_CTRL_SET_CRC_TEST_MASK) +#define OCOTP_CTRL_SET_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_SET_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_SET_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_CRC_FAIL_SHIFT)) & OCOTP_CTRL_SET_CRC_FAIL_MASK) +#define OCOTP_CTRL_SET_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_SET_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RSVD1_SHIFT)) & OCOTP_CTRL_SET_RSVD1_MASK) +#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK) + +/*! @name CTRL_CLR - OTP Controller Control Register */ +#define OCOTP_CTRL_CLR_ADDR_MASK (0x7FU) +#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U) +#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK) +#define OCOTP_CTRL_CLR_RSVD0_MASK (0x80U) +#define OCOTP_CTRL_CLR_RSVD0_SHIFT (7U) +#define OCOTP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RSVD0_SHIFT)) & OCOTP_CTRL_CLR_RSVD0_MASK) +#define OCOTP_CTRL_CLR_BUSY_MASK (0x100U) +#define OCOTP_CTRL_CLR_BUSY_SHIFT (8U) +#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK) +#define OCOTP_CTRL_CLR_ERROR_MASK (0x200U) +#define OCOTP_CTRL_CLR_ERROR_SHIFT (9U) +#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_CLR_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_CLR_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_CLR_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_CRC_TEST_SHIFT)) & OCOTP_CTRL_CLR_CRC_TEST_MASK) +#define OCOTP_CTRL_CLR_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_CLR_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_CLR_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_CRC_FAIL_SHIFT)) & OCOTP_CTRL_CLR_CRC_FAIL_MASK) +#define OCOTP_CTRL_CLR_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_CLR_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RSVD1_SHIFT)) & OCOTP_CTRL_CLR_RSVD1_MASK) +#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK) + +/*! @name CTRL_TOG - OTP Controller Control Register */ +#define OCOTP_CTRL_TOG_ADDR_MASK (0x7FU) +#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U) +#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK) +#define OCOTP_CTRL_TOG_RSVD0_MASK (0x80U) +#define OCOTP_CTRL_TOG_RSVD0_SHIFT (7U) +#define OCOTP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RSVD0_SHIFT)) & OCOTP_CTRL_TOG_RSVD0_MASK) +#define OCOTP_CTRL_TOG_BUSY_MASK (0x100U) +#define OCOTP_CTRL_TOG_BUSY_SHIFT (8U) +#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK) +#define OCOTP_CTRL_TOG_ERROR_MASK (0x200U) +#define OCOTP_CTRL_TOG_ERROR_SHIFT (9U) +#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_TOG_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_TOG_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_TOG_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_CRC_TEST_SHIFT)) & OCOTP_CTRL_TOG_CRC_TEST_MASK) +#define OCOTP_CTRL_TOG_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_TOG_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_TOG_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_CRC_FAIL_SHIFT)) & OCOTP_CTRL_TOG_CRC_FAIL_MASK) +#define OCOTP_CTRL_TOG_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_TOG_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RSVD1_SHIFT)) & OCOTP_CTRL_TOG_RSVD1_MASK) +#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK) + +/*! @name TIMING - OTP Controller Timing Register */ +#define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU) +#define OCOTP_TIMING_STROBE_PROG_SHIFT (0U) +#define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK) +#define OCOTP_TIMING_RELAX_MASK (0xF000U) +#define OCOTP_TIMING_RELAX_SHIFT (12U) +#define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK) +#define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U) +#define OCOTP_TIMING_STROBE_READ_SHIFT (16U) +#define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK) +#define OCOTP_TIMING_WAIT_MASK (0xFC00000U) +#define OCOTP_TIMING_WAIT_SHIFT (22U) +#define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK) +#define OCOTP_TIMING_RSRVD0_MASK (0xF0000000U) +#define OCOTP_TIMING_RSRVD0_SHIFT (28U) +#define OCOTP_TIMING_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RSRVD0_SHIFT)) & OCOTP_TIMING_RSRVD0_MASK) + +/*! @name DATA - OTP Controller Write Data Register */ +#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_DATA_DATA_SHIFT (0U) +#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK) + +/*! @name READ_CTRL - OTP Controller Read Control Register */ +#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) +#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) +#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK) +#define OCOTP_READ_CTRL_RSVD0_MASK (0xFFFFFFFEU) +#define OCOTP_READ_CTRL_RSVD0_SHIFT (1U) +#define OCOTP_READ_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_RSVD0_SHIFT)) & OCOTP_READ_CTRL_RSVD0_MASK) + +/*! @name READ_FUSE_DATA - OTP Controller Read Fuse Data Register */ +#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) +#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK) + +/*! @name SW_STICKY - Sticky bit Register */ +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK) +#define OCOTP_SW_STICKY_RSVD0_MASK (0xFFFFFFE0U) +#define OCOTP_SW_STICKY_RSVD0_SHIFT (5U) +#define OCOTP_SW_STICKY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_RSVD0_SHIFT)) & OCOTP_SW_STICKY_RSVD0_MASK) + +/*! @name SCS - Software Controllable Signals Register */ +#define OCOTP_SCS_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK) +#define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SPARE_SHIFT (1U) +#define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK) +#define OCOTP_SCS_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_LOCK_SHIFT (31U) +#define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK) + +/*! @name SCS_SET - Software Controllable Signals Register */ +#define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK) +#define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SET_SPARE_SHIFT (1U) +#define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK) +#define OCOTP_SCS_SET_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_SET_LOCK_SHIFT (31U) +#define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK) + +/*! @name SCS_CLR - Software Controllable Signals Register */ +#define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK) +#define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_CLR_SPARE_SHIFT (1U) +#define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK) +#define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_CLR_LOCK_SHIFT (31U) +#define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK) + +/*! @name SCS_TOG - Software Controllable Signals Register */ +#define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK) +#define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_TOG_SPARE_SHIFT (1U) +#define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK) +#define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_TOG_LOCK_SHIFT (31U) +#define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK) + +/*! @name CRC_ADDR - OTP Controller CRC Test Address */ +#define OCOTP_CRC_ADDR_DATA_START_ADDR_MASK (0xFFU) +#define OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT (0U) +#define OCOTP_CRC_ADDR_DATA_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT)) & OCOTP_CRC_ADDR_DATA_START_ADDR_MASK) +#define OCOTP_CRC_ADDR_DATA_END_ADDR_MASK (0xFF00U) +#define OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT (8U) +#define OCOTP_CRC_ADDR_DATA_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT)) & OCOTP_CRC_ADDR_DATA_END_ADDR_MASK) +#define OCOTP_CRC_ADDR_CRC_ADDR_MASK (0x70000U) +#define OCOTP_CRC_ADDR_CRC_ADDR_SHIFT (16U) +#define OCOTP_CRC_ADDR_CRC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_CRC_ADDR_SHIFT)) & OCOTP_CRC_ADDR_CRC_ADDR_MASK) +#define OCOTP_CRC_ADDR_OTPMK_CRC_MASK (0x80000U) +#define OCOTP_CRC_ADDR_OTPMK_CRC_SHIFT (19U) +#define OCOTP_CRC_ADDR_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_OTPMK_CRC_SHIFT)) & OCOTP_CRC_ADDR_OTPMK_CRC_MASK) +#define OCOTP_CRC_ADDR_RSVD0_MASK (0xFFF00000U) +#define OCOTP_CRC_ADDR_RSVD0_SHIFT (20U) +#define OCOTP_CRC_ADDR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_RSVD0_SHIFT)) & OCOTP_CRC_ADDR_RSVD0_MASK) + +/*! @name CRC_VALUE - OTP Controller CRC Value Register */ +#define OCOTP_CRC_VALUE_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_CRC_VALUE_DATA_SHIFT (0U) +#define OCOTP_CRC_VALUE_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_VALUE_DATA_SHIFT)) & OCOTP_CRC_VALUE_DATA_MASK) + +/*! @name VERSION - OTP Controller Version Register */ +#define OCOTP_VERSION_STEP_MASK (0xFFFFU) +#define OCOTP_VERSION_STEP_SHIFT (0U) +#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK) +#define OCOTP_VERSION_MINOR_MASK (0xFF0000U) +#define OCOTP_VERSION_MINOR_SHIFT (16U) +#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK) +#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U) +#define OCOTP_VERSION_MAJOR_SHIFT (24U) +#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK) + +/*! @name TIMING2 - OTP Controller Timing Register 2 */ +#define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU) +#define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U) +#define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK) +#define OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U) +#define OCOTP_TIMING2_RELAX_READ_SHIFT (16U) +#define OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK) +#define OCOTP_TIMING2_RELAX1_MASK (0x1FC00000U) +#define OCOTP_TIMING2_RELAX1_SHIFT (22U) +#define OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK) + +/*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */ +#define OCOTP_LOCK_TESTER_MASK (0x3U) +#define OCOTP_LOCK_TESTER_SHIFT (0U) +#define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK) +#define OCOTP_LOCK_BOOT_CFG_MASK (0xCU) +#define OCOTP_LOCK_BOOT_CFG_SHIFT (2U) +#define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK) +#define OCOTP_LOCK_MEM_TRIM_MASK (0x30U) +#define OCOTP_LOCK_MEM_TRIM_SHIFT (4U) +#define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK) +#define OCOTP_LOCK_SJC_RESP_MASK (0x40U) +#define OCOTP_LOCK_SJC_RESP_SHIFT (6U) +#define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK) +#define OCOTP_LOCK_RSVD0_MASK (0x80U) +#define OCOTP_LOCK_RSVD0_SHIFT (7U) +#define OCOTP_LOCK_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_RSVD0_SHIFT)) & OCOTP_LOCK_RSVD0_MASK) +#define OCOTP_LOCK_MAC_ADDR_MASK (0x300U) +#define OCOTP_LOCK_MAC_ADDR_SHIFT (8U) +#define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK) +#define OCOTP_LOCK_GP1_MASK (0xC00U) +#define OCOTP_LOCK_GP1_SHIFT (10U) +#define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK) +#define OCOTP_LOCK_GP2_MASK (0x3000U) +#define OCOTP_LOCK_GP2_SHIFT (12U) +#define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK) +#define OCOTP_LOCK_SRK_MASK (0x4000U) +#define OCOTP_LOCK_SRK_SHIFT (14U) +#define OCOTP_LOCK_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK) +#define OCOTP_LOCK_GP3_MASK (0x8000U) +#define OCOTP_LOCK_GP3_SHIFT (15U) +#define OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK) +#define OCOTP_LOCK_SW_GP_MASK (0x10000U) +#define OCOTP_LOCK_SW_GP_SHIFT (16U) +#define OCOTP_LOCK_SW_GP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP_SHIFT)) & OCOTP_LOCK_SW_GP_MASK) +#define OCOTP_LOCK_OTPMK_MASK (0x20000U) +#define OCOTP_LOCK_OTPMK_SHIFT (17U) +#define OCOTP_LOCK_OTPMK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_SHIFT)) & OCOTP_LOCK_OTPMK_MASK) +#define OCOTP_LOCK_ANALOG_MASK (0xC0000U) +#define OCOTP_LOCK_ANALOG_SHIFT (18U) +#define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK) +#define OCOTP_LOCK_OTPMK_CRC_MASK (0x100000U) +#define OCOTP_LOCK_OTPMK_CRC_SHIFT (20U) +#define OCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK) +#define OCOTP_LOCK_ROM_PATCH_MASK (0x200000U) +#define OCOTP_LOCK_ROM_PATCH_SHIFT (21U) +#define OCOTP_LOCK_ROM_PATCH(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ROM_PATCH_SHIFT)) & OCOTP_LOCK_ROM_PATCH_MASK) +#define OCOTP_LOCK_MISC_CONF_MASK (0x400000U) +#define OCOTP_LOCK_MISC_CONF_SHIFT (22U) +#define OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK) +#define OCOTP_LOCK_GP4_MASK (0x800000U) +#define OCOTP_LOCK_GP4_SHIFT (23U) +#define OCOTP_LOCK_GP4(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP4_SHIFT)) & OCOTP_LOCK_GP4_MASK) +#define OCOTP_LOCK_PIN_MASK (0x2000000U) +#define OCOTP_LOCK_PIN_SHIFT (25U) +#define OCOTP_LOCK_PIN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_PIN_SHIFT)) & OCOTP_LOCK_PIN_MASK) +#define OCOTP_LOCK_GP4_RLOCK_MASK (0x40000000U) +#define OCOTP_LOCK_GP4_RLOCK_SHIFT (30U) +#define OCOTP_LOCK_GP4_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP4_RLOCK_SHIFT)) & OCOTP_LOCK_GP4_RLOCK_MASK) +#define OCOTP_LOCK_GP3_RLOCK_MASK (0x80000000U) +#define OCOTP_LOCK_GP3_RLOCK_SHIFT (31U) +#define OCOTP_LOCK_GP3_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_RLOCK_SHIFT)) & OCOTP_LOCK_GP3_RLOCK_MASK) + +/*! @name CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG0_BITS_SHIFT (0U) +#define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK) + +/*! @name CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG1_BITS_SHIFT (0U) +#define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK) + +/*! @name CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG2_BITS_SHIFT (0U) +#define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK) + +/*! @name CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG3_BITS_SHIFT (0U) +#define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK) + +/*! @name CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG4_BITS_SHIFT (0U) +#define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK) + +/*! @name CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG5_BITS_SHIFT (0U) +#define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK) + +/*! @name CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG6_BITS_SHIFT (0U) +#define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK) + +/*! @name MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) */ +#define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM0_BITS_SHIFT (0U) +#define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK) + +/*! @name MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) */ +#define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM1_BITS_SHIFT (0U) +#define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK) + +/*! @name MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) */ +#define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM2_BITS_SHIFT (0U) +#define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK) + +/*! @name MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) */ +#define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM3_BITS_SHIFT (0U) +#define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK) + +/*! @name MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) */ +#define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM4_BITS_SHIFT (0U) +#define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK) + +/*! @name ANA0 - Value of OTP Bank1 Word5 (Memory Related Info.) */ +#define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA0_BITS_SHIFT (0U) +#define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK) + +/*! @name ANA1 - Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.) */ +#define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA1_BITS_SHIFT (0U) +#define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK) + +/*! @name ANA2 - Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) */ +#define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA2_BITS_SHIFT (0U) +#define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK) + +/*! @name OTPMK0 - Value of OTP Bank2 Word0 (OTPMK Key) */ +#define OCOTP_OTPMK0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK0_BITS_SHIFT (0U) +#define OCOTP_OTPMK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK0_BITS_SHIFT)) & OCOTP_OTPMK0_BITS_MASK) + +/*! @name OTPMK1 - Value of OTP Bank2 Word1 (OTPMK Key) */ +#define OCOTP_OTPMK1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK1_BITS_SHIFT (0U) +#define OCOTP_OTPMK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK1_BITS_SHIFT)) & OCOTP_OTPMK1_BITS_MASK) + +/*! @name OTPMK2 - Value of OTP Bank2 Word2 (OTPMK Key) */ +#define OCOTP_OTPMK2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK2_BITS_SHIFT (0U) +#define OCOTP_OTPMK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK2_BITS_SHIFT)) & OCOTP_OTPMK2_BITS_MASK) + +/*! @name OTPMK3 - Value of OTP Bank2 Word3 (OTPMK Key) */ +#define OCOTP_OTPMK3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK3_BITS_SHIFT (0U) +#define OCOTP_OTPMK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK3_BITS_SHIFT)) & OCOTP_OTPMK3_BITS_MASK) + +/*! @name OTPMK4 - Value of OTP Bank2 Word4 (OTPMK Key) */ +#define OCOTP_OTPMK4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK4_BITS_SHIFT (0U) +#define OCOTP_OTPMK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK4_BITS_SHIFT)) & OCOTP_OTPMK4_BITS_MASK) + +/*! @name OTPMK5 - Value of OTP Bank2 Word5 (OTPMK Key) */ +#define OCOTP_OTPMK5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK5_BITS_SHIFT (0U) +#define OCOTP_OTPMK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK5_BITS_SHIFT)) & OCOTP_OTPMK5_BITS_MASK) + +/*! @name OTPMK6 - Value of OTP Bank2 Word6 (OTPMK Key) */ +#define OCOTP_OTPMK6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK6_BITS_SHIFT (0U) +#define OCOTP_OTPMK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK6_BITS_SHIFT)) & OCOTP_OTPMK6_BITS_MASK) + +/*! @name OTPMK7 - Value of OTP Bank2 Word7 (OTPMK Key) */ +#define OCOTP_OTPMK7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK7_BITS_SHIFT (0U) +#define OCOTP_OTPMK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK7_BITS_SHIFT)) & OCOTP_OTPMK7_BITS_MASK) + +/*! @name SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) */ +#define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK0_BITS_SHIFT (0U) +#define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK) + +/*! @name SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) */ +#define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK1_BITS_SHIFT (0U) +#define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK) + +/*! @name SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) */ +#define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK2_BITS_SHIFT (0U) +#define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK) + +/*! @name SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) */ +#define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK3_BITS_SHIFT (0U) +#define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK) + +/*! @name SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) */ +#define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK4_BITS_SHIFT (0U) +#define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK) + +/*! @name SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) */ +#define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK5_BITS_SHIFT (0U) +#define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK) + +/*! @name SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) */ +#define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK6_BITS_SHIFT (0U) +#define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK) + +/*! @name SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) */ +#define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK7_BITS_SHIFT (0U) +#define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK) + +/*! @name SJC_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) */ +#define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP0_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK) + +/*! @name SJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) */ +#define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP1_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK) + +/*! @name MAC0 - Value of OTP Bank4 Word2 (MAC Address) */ +#define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC0_BITS_SHIFT (0U) +#define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK) + +/*! @name MAC1 - Value of OTP Bank4 Word3 (MAC Address) */ +#define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC1_BITS_SHIFT (0U) +#define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK) + +/*! @name MAC - Value of OTP Bank4 Word4 (MAC Address) (OCOTP_RESERVED) */ +#define OCOTP_MAC_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC_BITS_SHIFT (0U) +#define OCOTP_MAC_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC_BITS_SHIFT)) & OCOTP_MAC_BITS_MASK) + +/*! @name CRC - Value of OTP Bank4 Word5 (CRC Key) */ +#define OCOTP_CRC_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CRC_BITS_SHIFT (0U) +#define OCOTP_CRC_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_BITS_SHIFT)) & OCOTP_CRC_BITS_MASK) + +/*! @name GP1 - Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) */ +#define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP1_BITS_SHIFT (0U) +#define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK) + +/*! @name GP2 - Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) */ +#define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP2_BITS_SHIFT (0U) +#define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK) + +/*! @name SW_GP0 - Value of OTP Bank5 Word0 (SW GP) */ +#define OCOTP_SW_GP0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP0_BITS_SHIFT (0U) +#define OCOTP_SW_GP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP0_BITS_SHIFT)) & OCOTP_SW_GP0_BITS_MASK) + +/*! @name SW_GP1 - Value of OTP Bank5 Word1 (SW GP) */ +#define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP1_BITS_SHIFT (0U) +#define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK) + +/*! @name SW_GP2 - Value of OTP Bank5 Word2 (SW GP) */ +#define OCOTP_SW_GP2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP2_BITS_SHIFT (0U) +#define OCOTP_SW_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP2_BITS_SHIFT)) & OCOTP_SW_GP2_BITS_MASK) + +/*! @name SW_GP3 - Value of OTP Bank5 Word3 (SW GP) */ +#define OCOTP_SW_GP3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP3_BITS_SHIFT (0U) +#define OCOTP_SW_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP3_BITS_SHIFT)) & OCOTP_SW_GP3_BITS_MASK) + +/*! @name SW_GP4 - Value of OTP Bank5 Word4 (SW GP) */ +#define OCOTP_SW_GP4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP4_BITS_SHIFT (0U) +#define OCOTP_SW_GP4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP4_BITS_SHIFT)) & OCOTP_SW_GP4_BITS_MASK) + +/*! @name MISC_CONF - Value of OTP Bank5 Word5 (Misc Conf) */ +#define OCOTP_MISC_CONF_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MISC_CONF_BITS_SHIFT (0U) +#define OCOTP_MISC_CONF_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF_BITS_SHIFT)) & OCOTP_MISC_CONF_BITS_MASK) + +/*! @name FIELD_RETURN - Value of OTP Bank5 Word6 (Field Return) */ +#define OCOTP_FIELD_RETURN_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_FIELD_RETURN_BITS_SHIFT (0U) +#define OCOTP_FIELD_RETURN_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FIELD_RETURN_BITS_SHIFT)) & OCOTP_FIELD_RETURN_BITS_MASK) + +/*! @name SRK_REVOKE - Value of OTP Bank5 Word7 (SRK Revoke) */ +#define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK_REVOKE_BITS_SHIFT (0U) +#define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK) + +/*! @name ROM_PATCH0 - Value of OTP Bank6 Word0 (ROM Patch) */ +#define OCOTP_ROM_PATCH0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH0_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH0_BITS_SHIFT)) & OCOTP_ROM_PATCH0_BITS_MASK) + +/*! @name ROM_PATCH1 - Value of OTP Bank6 Word1 (ROM Patch) */ +#define OCOTP_ROM_PATCH1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH1_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH1_BITS_SHIFT)) & OCOTP_ROM_PATCH1_BITS_MASK) + +/*! @name ROM_PATCH2 - Value of OTP Bank6 Word2 (ROM Patch) */ +#define OCOTP_ROM_PATCH2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH2_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH2_BITS_SHIFT)) & OCOTP_ROM_PATCH2_BITS_MASK) + +/*! @name ROM_PATCH3 - Value of OTP Bank6 Word3 (ROM Patch) */ +#define OCOTP_ROM_PATCH3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH3_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH3_BITS_SHIFT)) & OCOTP_ROM_PATCH3_BITS_MASK) + +/*! @name ROM_PATCH4 - Value of OTP Bank6 Word4 (ROM Patch) */ +#define OCOTP_ROM_PATCH4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH4_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH4_BITS_SHIFT)) & OCOTP_ROM_PATCH4_BITS_MASK) + +/*! @name ROM_PATCH5 - Value of OTP Bank6 Word5 (ROM Patch) */ +#define OCOTP_ROM_PATCH5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH5_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH5_BITS_SHIFT)) & OCOTP_ROM_PATCH5_BITS_MASK) + +/*! @name ROM_PATCH6 - Value of OTP Bank6 Word6 (ROM Patch) */ +#define OCOTP_ROM_PATCH6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH6_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH6_BITS_SHIFT)) & OCOTP_ROM_PATCH6_BITS_MASK) + +/*! @name ROM_PATCH7 - Value of OTP Bank6 Word7 (ROM Patch) */ +#define OCOTP_ROM_PATCH7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH7_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH7_BITS_SHIFT)) & OCOTP_ROM_PATCH7_BITS_MASK) + +/*! @name GP3_0 - Value of OTP Bank7 Word0 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_0_BITS_SHIFT (0U) +#define OCOTP_GP3_0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_0_BITS_SHIFT)) & OCOTP_GP3_0_BITS_MASK) + +/*! @name GP3_1 - Value of OTP Bank7 Word1 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_1_BITS_SHIFT (0U) +#define OCOTP_GP3_1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_1_BITS_SHIFT)) & OCOTP_GP3_1_BITS_MASK) + +/*! @name GP3_2 - Value of OTP Bank7 Word2 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_2_BITS_SHIFT (0U) +#define OCOTP_GP3_2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_2_BITS_SHIFT)) & OCOTP_GP3_2_BITS_MASK) + +/*! @name GP3_3 - Value of OTP Bank7 Word3 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_3_BITS_SHIFT (0U) +#define OCOTP_GP3_3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_3_BITS_SHIFT)) & OCOTP_GP3_3_BITS_MASK) + +/*! @name GP3_4 - Value of OTP Bank8 Word4 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_4_BITS_SHIFT (0U) +#define OCOTP_GP3_4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_4_BITS_SHIFT)) & OCOTP_GP3_4_BITS_MASK) + +/*! @name GP4_0 - Value of OTP Bank7 Word5 (General Purpose Customer Defined Info) */ +#define OCOTP_GP4_0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP4_0_BITS_SHIFT (0U) +#define OCOTP_GP4_0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP4_0_BITS_SHIFT)) & OCOTP_GP4_0_BITS_MASK) + +/*! @name GP4_1 - Value of OTP Bank7 Word6 (General Purpose Customer Defined Info) */ +#define OCOTP_GP4_1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP4_1_BITS_SHIFT (0U) +#define OCOTP_GP4_1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP4_1_BITS_SHIFT)) & OCOTP_GP4_1_BITS_MASK) + +/*! @name GP4_2 - Value of OTP Bank7 Word7 (General Purpose Customer Defined Info) */ +#define OCOTP_GP4_2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP4_2_BITS_SHIFT (0U) +#define OCOTP_GP4_2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP4_2_BITS_SHIFT)) & OCOTP_GP4_2_BITS_MASK) + + +/*! + * @} + */ /* end of group OCOTP_Register_Masks */ + + +/* OCOTP - Peripheral instance base addresses */ +/** Peripheral OCOTP base address */ +#define OCOTP_BASE (0x21BC000u) +/** Peripheral OCOTP base pointer */ +#define OCOTP ((OCOTP_Type *)OCOTP_BASE) +/** Array initializer of OCOTP peripheral base addresses */ +#define OCOTP_BASE_ADDRS { OCOTP_BASE } +/** Array initializer of OCOTP peripheral base pointers */ +#define OCOTP_BASE_PTRS { OCOTP } + +/*! + * @} + */ /* end of group OCOTP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PGC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Peripheral_Access_Layer PGC Peripheral Access Layer + * @{ + */ + +/** PGC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MEGA_CTRL; /**< PGC Mega Control Register, offset: 0x0 */ + __IO uint32_t MEGA_PUPSCR; /**< PGC Mega Power Up Sequence Control Register, offset: 0x4 */ + __IO uint32_t MEGA_PDNSCR; /**< PGC Mega Pull Down Sequence Control Register, offset: 0x8 */ + __IO uint32_t MEGA_SR; /**< PGC Mega Power Gating Controller Status Register, offset: 0xC */ + uint8_t RESERVED_0[112]; + __IO uint32_t CPU_CTRL; /**< PGC CPU Control Register, offset: 0x80 */ + __IO uint32_t CPU_PUPSCR; /**< PGC CPU Power Up Sequence Control Register, offset: 0x84 */ + __IO uint32_t CPU_PDNSCR; /**< PGC CPU Pull Down Sequence Control Register, offset: 0x88 */ + __IO uint32_t CPU_SR; /**< PGC CPU Power Gating Controller Status Register, offset: 0x8C */ +} PGC_Type; + +/* ---------------------------------------------------------------------------- + -- PGC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Register_Masks PGC Register Masks + * @{ + */ + +/*! @name MEGA_CTRL - PGC Mega Control Register */ +#define PGC_MEGA_CTRL_PCR_MASK (0x1U) +#define PGC_MEGA_CTRL_PCR_SHIFT (0U) +#define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK) + +/*! @name MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register */ +#define PGC_MEGA_PUPSCR_SW_MASK (0x3FU) +#define PGC_MEGA_PUPSCR_SW_SHIFT (0U) +#define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK) +#define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U) +#define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U) +#define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK) + +/*! @name MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register */ +#define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU) +#define PGC_MEGA_PDNSCR_ISO_SHIFT (0U) +#define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK) +#define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U) +#define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U) +#define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK) + +/*! @name MEGA_SR - PGC Mega Power Gating Controller Status Register */ +#define PGC_MEGA_SR_PSR_MASK (0x1U) +#define PGC_MEGA_SR_PSR_SHIFT (0U) +#define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK) + +/*! @name CPU_CTRL - PGC CPU Control Register */ +#define PGC_CPU_CTRL_PCR_MASK (0x1U) +#define PGC_CPU_CTRL_PCR_SHIFT (0U) +#define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK) + +/*! @name CPU_PUPSCR - PGC CPU Power Up Sequence Control Register */ +#define PGC_CPU_PUPSCR_SW_MASK (0x3FU) +#define PGC_CPU_PUPSCR_SW_SHIFT (0U) +#define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK) +#define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) +#define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U) +#define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK) + +/*! @name CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register */ +#define PGC_CPU_PDNSCR_ISO_MASK (0x3FU) +#define PGC_CPU_PDNSCR_ISO_SHIFT (0U) +#define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK) +#define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) +#define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U) +#define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK) + +/*! @name CPU_SR - PGC CPU Power Gating Controller Status Register */ +#define PGC_CPU_SR_PSR_MASK (0x1U) +#define PGC_CPU_SR_PSR_SHIFT (0U) +#define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK) + + +/*! + * @} + */ /* end of group PGC_Register_Masks */ + + +/* PGC - Peripheral instance base addresses */ +/** Peripheral PGC base address */ +#define PGC_BASE (0x20DC220u) +/** Peripheral PGC base pointer */ +#define PGC ((PGC_Type *)PGC_BASE) +/** Array initializer of PGC peripheral base addresses */ +#define PGC_BASE_ADDRS { PGC_BASE } +/** Array initializer of PGC peripheral base pointers */ +#define PGC_BASE_PTRS { PGC } + +/*! + * @} + */ /* end of group PGC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer + * @{ + */ + +/** PMU - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG_1P1; /**< Regulator 1P1 Register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __IO uint32_t REG_CORE; /**< Digital Regulator Core Register, offset: 0x30 */ + uint8_t RESERVED_3[300]; + __IO uint32_t LOWPWR_CTRL; /**< Low Power Control Register, offset: 0x160 */ + __IO uint32_t LOWPWR_CTRL_SET; /**< Low Power Control Register, offset: 0x164 */ + __IO uint32_t LOWPWR_CTRL_CLR; /**< Low Power Control Register, offset: 0x168 */ + __IO uint32_t LOWPWR_CTRL_TOG; /**< Low Power Control Register, offset: 0x16C */ +} PMU_Type; + +/* ---------------------------------------------------------------------------- + -- PMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Register_Masks PMU Register Masks + * @{ + */ + +/*! @name REG_1P1 - Regulator 1P1 Register */ +#define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK) +#define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK) +#define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK) +#define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U) +#define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) + +/*! @name REG_3P0 - Regulator 3P0 Register */ +#define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK) +#define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK) +#define PMU_REG_3P0_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_VBUS_SEL_SHIFT (7U) +#define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK) +#define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK) +#define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK) + +/*! @name REG_2P5 - Regulator 2P5 Register */ +#define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK) +#define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK) +#define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK) +#define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK) + +/*! @name REG_CORE - Digital Regulator Core Register */ +#define PMU_REG_CORE_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_REG0_TARG_SHIFT (0U) +#define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK) +#define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_REG2_TARG_SHIFT (18U) +#define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK) +#define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_RAMP_RATE_SHIFT (27U) +#define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK) +#define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK) + +/*! @name LOWPWR_CTRL - Low Power Control Register */ +#define PMU_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U) +#define PMU_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U) +#define PMU_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & PMU_LOWPWR_CTRL_RC_OSC_EN_MASK) +#define PMU_LOWPWR_CTRL_RC_OSC_PROG_MASK (0xEU) +#define PMU_LOWPWR_CTRL_RC_OSC_PROG_SHIFT (1U) +#define PMU_LOWPWR_CTRL_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_RC_OSC_PROG_SHIFT)) & PMU_LOWPWR_CTRL_RC_OSC_PROG_MASK) +#define PMU_LOWPWR_CTRL_OSC_SEL_MASK (0x10U) +#define PMU_LOWPWR_CTRL_OSC_SEL_SHIFT (4U) +#define PMU_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_OSC_SEL_SHIFT)) & PMU_LOWPWR_CTRL_OSC_SEL_MASK) +#define PMU_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) +#define PMU_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U) +#define PMU_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & PMU_LOWPWR_CTRL_LPBG_SEL_MASK) +#define PMU_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U) +#define PMU_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U) +#define PMU_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & PMU_LOWPWR_CTRL_LPBG_TEST_MASK) +#define PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U) +#define PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U) +#define PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK) +#define PMU_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U) +#define PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U) +#define PMU_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_L1_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U) +#define PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U) +#define PMU_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_L2_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U) +#define PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U) +#define PMU_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U) +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U) +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) +#define PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U) +#define PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U) +#define PMU_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK) + +/*! @name LOWPWR_CTRL_SET - Low Power Control Register */ +#define PMU_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & PMU_LOWPWR_CTRL_SET_RC_OSC_EN_MASK) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK (0xEU) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT (1U) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT)) & PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK) +#define PMU_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U) +#define PMU_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U) +#define PMU_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & PMU_LOWPWR_CTRL_SET_OSC_SEL_MASK) +#define PMU_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U) +#define PMU_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U) +#define PMU_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & PMU_LOWPWR_CTRL_SET_LPBG_SEL_MASK) +#define PMU_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U) +#define PMU_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U) +#define PMU_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & PMU_LOWPWR_CTRL_SET_LPBG_TEST_MASK) +#define PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U) +#define PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U) +#define PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK) +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U) +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U) +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U) +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U) +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U) +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U) +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U) +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK) +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U) +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U) +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK) + +/*! @name LOWPWR_CTRL_CLR - Low Power Control Register */ +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK (0xEU) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT (1U) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT)) & PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK) +#define PMU_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U) +#define PMU_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U) +#define PMU_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & PMU_LOWPWR_CTRL_CLR_OSC_SEL_MASK) +#define PMU_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U) +#define PMU_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U) +#define PMU_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & PMU_LOWPWR_CTRL_CLR_LPBG_SEL_MASK) +#define PMU_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U) +#define PMU_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U) +#define PMU_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & PMU_LOWPWR_CTRL_CLR_LPBG_TEST_MASK) +#define PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U) +#define PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U) +#define PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK) +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U) +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U) +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U) +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U) +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U) +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U) +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U) +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK) +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U) +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U) +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK) + +/*! @name LOWPWR_CTRL_TOG - Low Power Control Register */ +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK (0xEU) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT (1U) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT)) & PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK) +#define PMU_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U) +#define PMU_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U) +#define PMU_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & PMU_LOWPWR_CTRL_TOG_OSC_SEL_MASK) +#define PMU_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U) +#define PMU_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U) +#define PMU_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & PMU_LOWPWR_CTRL_TOG_LPBG_SEL_MASK) +#define PMU_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U) +#define PMU_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U) +#define PMU_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & PMU_LOWPWR_CTRL_TOG_LPBG_TEST_MASK) +#define PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U) +#define PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U) +#define PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK) +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U) +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U) +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U) +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U) +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U) +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U) +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U) +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U) +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK) +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U) +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U) +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK) + + +/*! + * @} + */ /* end of group PMU_Register_Masks */ + + +/* PMU - Peripheral instance base addresses */ +/** Peripheral PMU base address */ +#define PMU_BASE (0x20C8110u) +/** Peripheral PMU base pointer */ +#define PMU ((PMU_Type *)PMU_BASE) +/** Array initializer of PMU peripheral base addresses */ +#define PMU_BASE_ADDRS { PMU_BASE } +/** Array initializer of PMU peripheral base pointers */ +#define PMU_BASE_PTRS { PMU } +/** Interrupt vectors for the PMU peripheral type */ +#define PMU_IRQS { PMU_IRQ1_IRQn, PMU_IRQ2_IRQn } + +/*! + * @} + */ /* end of group PMU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer + * @{ + */ + +/** PWM - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWMCR; /**< PWM Control Register, offset: 0x0 */ + __IO uint32_t PWMSR; /**< PWM Status Register, offset: 0x4 */ + __IO uint32_t PWMIR; /**< PWM Interrupt Register, offset: 0x8 */ + __IO uint32_t PWMSAR; /**< PWM Sample Register, offset: 0xC */ + __IO uint32_t PWMPR; /**< PWM Period Register, offset: 0x10 */ + __I uint32_t PWMCNR; /**< PWM Counter Register, offset: 0x14 */ +} PWM_Type; + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/*! @name PWMCR - PWM Control Register */ +#define PWM_PWMCR_EN_MASK (0x1U) +#define PWM_PWMCR_EN_SHIFT (0U) +#define PWM_PWMCR_EN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_EN_SHIFT)) & PWM_PWMCR_EN_MASK) +#define PWM_PWMCR_REPEAT_MASK (0x6U) +#define PWM_PWMCR_REPEAT_SHIFT (1U) +#define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_REPEAT_SHIFT)) & PWM_PWMCR_REPEAT_MASK) +#define PWM_PWMCR_SWR_MASK (0x8U) +#define PWM_PWMCR_SWR_SHIFT (3U) +#define PWM_PWMCR_SWR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_SWR_SHIFT)) & PWM_PWMCR_SWR_MASK) +#define PWM_PWMCR_PRESCALER_MASK (0xFFF0U) +#define PWM_PWMCR_PRESCALER_SHIFT (4U) +#define PWM_PWMCR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_PRESCALER_SHIFT)) & PWM_PWMCR_PRESCALER_MASK) +#define PWM_PWMCR_CLKSRC_MASK (0x30000U) +#define PWM_PWMCR_CLKSRC_SHIFT (16U) +#define PWM_PWMCR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_CLKSRC_SHIFT)) & PWM_PWMCR_CLKSRC_MASK) +#define PWM_PWMCR_POUTC_MASK (0xC0000U) +#define PWM_PWMCR_POUTC_SHIFT (18U) +#define PWM_PWMCR_POUTC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_POUTC_SHIFT)) & PWM_PWMCR_POUTC_MASK) +#define PWM_PWMCR_HCTR_MASK (0x100000U) +#define PWM_PWMCR_HCTR_SHIFT (20U) +#define PWM_PWMCR_HCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_HCTR_SHIFT)) & PWM_PWMCR_HCTR_MASK) +#define PWM_PWMCR_BCTR_MASK (0x200000U) +#define PWM_PWMCR_BCTR_SHIFT (21U) +#define PWM_PWMCR_BCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_BCTR_SHIFT)) & PWM_PWMCR_BCTR_MASK) +#define PWM_PWMCR_DBGEN_MASK (0x400000U) +#define PWM_PWMCR_DBGEN_SHIFT (22U) +#define PWM_PWMCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DBGEN_SHIFT)) & PWM_PWMCR_DBGEN_MASK) +#define PWM_PWMCR_WAITEN_MASK (0x800000U) +#define PWM_PWMCR_WAITEN_SHIFT (23U) +#define PWM_PWMCR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_WAITEN_SHIFT)) & PWM_PWMCR_WAITEN_MASK) +#define PWM_PWMCR_DOZEN_MASK (0x1000000U) +#define PWM_PWMCR_DOZEN_SHIFT (24U) +#define PWM_PWMCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DOZEN_SHIFT)) & PWM_PWMCR_DOZEN_MASK) +#define PWM_PWMCR_STOPEN_MASK (0x2000000U) +#define PWM_PWMCR_STOPEN_SHIFT (25U) +#define PWM_PWMCR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_STOPEN_SHIFT)) & PWM_PWMCR_STOPEN_MASK) +#define PWM_PWMCR_FWM_MASK (0xC000000U) +#define PWM_PWMCR_FWM_SHIFT (26U) +#define PWM_PWMCR_FWM(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_FWM_SHIFT)) & PWM_PWMCR_FWM_MASK) + +/*! @name PWMSR - PWM Status Register */ +#define PWM_PWMSR_FIFOAV_MASK (0x7U) +#define PWM_PWMSR_FIFOAV_SHIFT (0U) +#define PWM_PWMSR_FIFOAV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FIFOAV_SHIFT)) & PWM_PWMSR_FIFOAV_MASK) +#define PWM_PWMSR_FE_MASK (0x8U) +#define PWM_PWMSR_FE_SHIFT (3U) +#define PWM_PWMSR_FE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FE_SHIFT)) & PWM_PWMSR_FE_MASK) +#define PWM_PWMSR_ROV_MASK (0x10U) +#define PWM_PWMSR_ROV_SHIFT (4U) +#define PWM_PWMSR_ROV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_ROV_SHIFT)) & PWM_PWMSR_ROV_MASK) +#define PWM_PWMSR_CMP_MASK (0x20U) +#define PWM_PWMSR_CMP_SHIFT (5U) +#define PWM_PWMSR_CMP(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_CMP_SHIFT)) & PWM_PWMSR_CMP_MASK) +#define PWM_PWMSR_FWE_MASK (0x40U) +#define PWM_PWMSR_FWE_SHIFT (6U) +#define PWM_PWMSR_FWE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FWE_SHIFT)) & PWM_PWMSR_FWE_MASK) + +/*! @name PWMIR - PWM Interrupt Register */ +#define PWM_PWMIR_FIE_MASK (0x1U) +#define PWM_PWMIR_FIE_SHIFT (0U) +#define PWM_PWMIR_FIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_FIE_SHIFT)) & PWM_PWMIR_FIE_MASK) +#define PWM_PWMIR_RIE_MASK (0x2U) +#define PWM_PWMIR_RIE_SHIFT (1U) +#define PWM_PWMIR_RIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_RIE_SHIFT)) & PWM_PWMIR_RIE_MASK) +#define PWM_PWMIR_CIE_MASK (0x4U) +#define PWM_PWMIR_CIE_SHIFT (2U) +#define PWM_PWMIR_CIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_CIE_SHIFT)) & PWM_PWMIR_CIE_MASK) + +/*! @name PWMSAR - PWM Sample Register */ +#define PWM_PWMSAR_SAMPLE_MASK (0xFFFFU) +#define PWM_PWMSAR_SAMPLE_SHIFT (0U) +#define PWM_PWMSAR_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSAR_SAMPLE_SHIFT)) & PWM_PWMSAR_SAMPLE_MASK) + +/*! @name PWMPR - PWM Period Register */ +#define PWM_PWMPR_PERIOD_MASK (0xFFFFU) +#define PWM_PWMPR_PERIOD_SHIFT (0U) +#define PWM_PWMPR_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMPR_PERIOD_SHIFT)) & PWM_PWMPR_PERIOD_MASK) + +/*! @name PWMCNR - PWM Counter Register */ +#define PWM_PWMCNR_COUNT_MASK (0xFFFFU) +#define PWM_PWMCNR_COUNT_SHIFT (0U) +#define PWM_PWMCNR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCNR_COUNT_SHIFT)) & PWM_PWMCNR_COUNT_MASK) + + +/*! + * @} + */ /* end of group PWM_Register_Masks */ + + +/* PWM - Peripheral instance base addresses */ +/** Peripheral PWM1 base address */ +#define PWM1_BASE (0x2080000u) +/** Peripheral PWM1 base pointer */ +#define PWM1 ((PWM_Type *)PWM1_BASE) +/** Peripheral PWM2 base address */ +#define PWM2_BASE (0x2084000u) +/** Peripheral PWM2 base pointer */ +#define PWM2 ((PWM_Type *)PWM2_BASE) +/** Peripheral PWM3 base address */ +#define PWM3_BASE (0x2088000u) +/** Peripheral PWM3 base pointer */ +#define PWM3 ((PWM_Type *)PWM3_BASE) +/** Peripheral PWM4 base address */ +#define PWM4_BASE (0x208C000u) +/** Peripheral PWM4 base pointer */ +#define PWM4 ((PWM_Type *)PWM4_BASE) +/** Peripheral PWM5 base address */ +#define PWM5_BASE (0x20F0000u) +/** Peripheral PWM5 base pointer */ +#define PWM5 ((PWM_Type *)PWM5_BASE) +/** Peripheral PWM6 base address */ +#define PWM6_BASE (0x20F4000u) +/** Peripheral PWM6 base pointer */ +#define PWM6 ((PWM_Type *)PWM6_BASE) +/** Peripheral PWM7 base address */ +#define PWM7_BASE (0x20F8000u) +/** Peripheral PWM7 base pointer */ +#define PWM7 ((PWM_Type *)PWM7_BASE) +/** Peripheral PWM8 base address */ +#define PWM8_BASE (0x20FC000u) +/** Peripheral PWM8 base pointer */ +#define PWM8 ((PWM_Type *)PWM8_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE, PWM5_BASE, PWM6_BASE, PWM7_BASE, PWM8_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_IRQS { NotAvail_IRQn, PWM1_IRQn, PWM2_IRQn, PWM3_IRQn, PWM4_IRQn, PWM5_IRQn, PWM6_IRQn, PWM7_IRQn, PWM8_IRQn } + +/*! + * @} + */ /* end of group PWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PXP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer + * @{ + */ + +/** PXP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control Register 0, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< Control Register 0, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< Control Register 0, offset: 0xC */ + __IO uint32_t STAT; /**< Status Register, offset: 0x10 */ + __IO uint32_t STAT_SET; /**< Status Register, offset: 0x14 */ + __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ + __IO uint32_t STAT_TOG; /**< Status Register, offset: 0x1C */ + __IO uint32_t OUT_CTRL; /**< Output Buffer Control Register, offset: 0x20 */ + __IO uint32_t OUT_CTRL_SET; /**< Output Buffer Control Register, offset: 0x24 */ + __IO uint32_t OUT_CTRL_CLR; /**< Output Buffer Control Register, offset: 0x28 */ + __IO uint32_t OUT_CTRL_TOG; /**< Output Buffer Control Register, offset: 0x2C */ + __IO uint32_t OUT_BUF; /**< Output Frame Buffer Pointer, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t OUT_BUF2; /**< Output Frame Buffer Pointer #2, offset: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t OUT_PITCH; /**< Output Buffer Pitch, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t OUT_LRC; /**< Output Surface Lower Right Coordinate, offset: 0x60 */ + uint8_t RESERVED_3[12]; + __IO uint32_t OUT_PS_ULC; /**< Processed Surface Upper Left Coordinate, offset: 0x70 */ + uint8_t RESERVED_4[12]; + __IO uint32_t OUT_PS_LRC; /**< Processed Surface Lower Right Coordinate, offset: 0x80 */ + uint8_t RESERVED_5[12]; + __IO uint32_t OUT_AS_ULC; /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */ + uint8_t RESERVED_6[12]; + __IO uint32_t OUT_AS_LRC; /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */ + uint8_t RESERVED_7[12]; + __IO uint32_t PS_CTRL; /**< Processed Surface (PS) Control Register, offset: 0xB0 */ + __IO uint32_t PS_CTRL_SET; /**< Processed Surface (PS) Control Register, offset: 0xB4 */ + __IO uint32_t PS_CTRL_CLR; /**< Processed Surface (PS) Control Register, offset: 0xB8 */ + __IO uint32_t PS_CTRL_TOG; /**< Processed Surface (PS) Control Register, offset: 0xBC */ + __IO uint32_t PS_BUF; /**< PS Input Buffer Address, offset: 0xC0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t PS_UBUF; /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */ + uint8_t RESERVED_9[12]; + __IO uint32_t PS_VBUF; /**< PS V/Cr Input Buffer Address, offset: 0xE0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t PS_PITCH; /**< Processed Surface Pitch, offset: 0xF0 */ + uint8_t RESERVED_11[12]; + __IO uint32_t PS_BACKGROUND_0; /**< PS Background Color, offset: 0x100 */ + uint8_t RESERVED_12[12]; + __IO uint32_t PS_SCALE; /**< PS Scale Factor Register, offset: 0x110 */ + uint8_t RESERVED_13[12]; + __IO uint32_t PS_OFFSET; /**< PS Scale Offset Register, offset: 0x120 */ + uint8_t RESERVED_14[12]; + __IO uint32_t PS_CLRKEYLOW_0; /**< PS Color Key Low, offset: 0x130 */ + uint8_t RESERVED_15[12]; + __IO uint32_t PS_CLRKEYHIGH_0; /**< PS Color Key High, offset: 0x140 */ + uint8_t RESERVED_16[12]; + __IO uint32_t AS_CTRL; /**< Alpha Surface Control, offset: 0x150 */ + uint8_t RESERVED_17[12]; + __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x160 */ + uint8_t RESERVED_18[12]; + __IO uint32_t AS_PITCH; /**< Alpha Surface Pitch, offset: 0x170 */ + uint8_t RESERVED_19[12]; + __IO uint32_t AS_CLRKEYLOW_0; /**< Overlay Color Key Low, offset: 0x180 */ + uint8_t RESERVED_20[12]; + __IO uint32_t AS_CLRKEYHIGH_0; /**< Overlay Color Key High, offset: 0x190 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CSC1_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */ + uint8_t RESERVED_22[12]; + __IO uint32_t CSC1_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */ + uint8_t RESERVED_23[12]; + __IO uint32_t CSC1_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */ + uint8_t RESERVED_24[12]; + __IO uint32_t CSC2_CTRL; /**< Color Space Conversion Control Register., offset: 0x1D0 */ + uint8_t RESERVED_25[12]; + __IO uint32_t CSC2_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1E0 */ + uint8_t RESERVED_26[12]; + __IO uint32_t CSC2_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1F0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t CSC2_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x200 */ + uint8_t RESERVED_28[12]; + __IO uint32_t CSC2_COEF3; /**< Color Space Conversion Coefficient Register 3, offset: 0x210 */ + uint8_t RESERVED_29[12]; + __IO uint32_t CSC2_COEF4; /**< Color Space Conversion Coefficient Register 4, offset: 0x220 */ + uint8_t RESERVED_30[12]; + __IO uint32_t CSC2_COEF5; /**< Color Space Conversion Coefficient Register 5, offset: 0x230 */ + uint8_t RESERVED_31[12]; + __IO uint32_t LUT_CTRL; /**< Lookup Table Control Register., offset: 0x240 */ + uint8_t RESERVED_32[12]; + __IO uint32_t LUT_ADDR; /**< Lookup Table Control Register., offset: 0x250 */ + uint8_t RESERVED_33[12]; + __IO uint32_t LUT_DATA; /**< Lookup Table Data Register., offset: 0x260 */ + uint8_t RESERVED_34[12]; + __IO uint32_t LUT_EXTMEM; /**< Lookup Table External Memory Address Register., offset: 0x270 */ + uint8_t RESERVED_35[12]; + __IO uint32_t CFA; /**< Color Filter Array Register., offset: 0x280 */ + uint8_t RESERVED_36[12]; + __IO uint32_t ALPHA_A_CTRL; /**< PXP Alpha Engine A Control Register., offset: 0x290 */ + uint8_t RESERVED_37[44]; + __IO uint32_t PS_BACKGROUND_1; /**< PS Background Color 1, offset: 0x2C0 */ + uint8_t RESERVED_38[12]; + __IO uint32_t PS_CLRKEYLOW_1; /**< PS Color Key Low 1, offset: 0x2D0 */ + uint8_t RESERVED_39[12]; + __IO uint32_t PS_CLRKEYHIGH_1; /**< PS Color Key High 1, offset: 0x2E0 */ + uint8_t RESERVED_40[12]; + __IO uint32_t AS_CLRKEYLOW_1; /**< Overlay Color Key Low, offset: 0x2F0 */ + uint8_t RESERVED_41[12]; + __IO uint32_t AS_CLRKEYHIGH_1; /**< Overlay Color Key High, offset: 0x300 */ + uint8_t RESERVED_42[12]; + __IO uint32_t CTRL2; /**< Control Register 2, offset: 0x310 */ + __IO uint32_t CTRL2_SET; /**< Control Register 2, offset: 0x314 */ + __IO uint32_t CTRL2_CLR; /**< Control Register 2, offset: 0x318 */ + __IO uint32_t CTRL2_TOG; /**< Control Register 2, offset: 0x31C */ + __IO uint32_t POWER_REG0; /**< PXP Power Control Register., offset: 0x320 */ + uint8_t RESERVED_43[12]; + __IO uint32_t POWER_REG1; /**< PXP Power Control Register 1., offset: 0x330 */ + uint8_t RESERVED_44[12]; + __IO uint32_t DATA_PATH_CTRL0; /**< This register helps decide the data path gthrough the PXP., offset: 0x340 */ + __IO uint32_t DATA_PATH_CTRL0_SET; /**< This register helps decide the data path gthrough the PXP., offset: 0x344 */ + __IO uint32_t DATA_PATH_CTRL0_CLR; /**< This register helps decide the data path gthrough the PXP., offset: 0x348 */ + __IO uint32_t DATA_PATH_CTRL0_TOG; /**< This register helps decide the data path gthrough the PXP., offset: 0x34C */ + __IO uint32_t DATA_PATH_CTRL1; /**< This register helps decide the data path gthrough the PXP., offset: 0x350 */ + __IO uint32_t DATA_PATH_CTRL1_SET; /**< This register helps decide the data path gthrough the PXP., offset: 0x354 */ + __IO uint32_t DATA_PATH_CTRL1_CLR; /**< This register helps decide the data path gthrough the PXP., offset: 0x358 */ + __IO uint32_t DATA_PATH_CTRL1_TOG; /**< This register helps decide the data path gthrough the PXP., offset: 0x35C */ + __IO uint32_t INIT_MEM_CTRL; /**< Initialize memory buffer control Register, offset: 0x360 */ + __IO uint32_t INIT_MEM_CTRL_SET; /**< Initialize memory buffer control Register, offset: 0x364 */ + __IO uint32_t INIT_MEM_CTRL_CLR; /**< Initialize memory buffer control Register, offset: 0x368 */ + __IO uint32_t INIT_MEM_CTRL_TOG; /**< Initialize memory buffer control Register, offset: 0x36C */ + __IO uint32_t INIT_MEM_DATA; /**< Write data Register, offset: 0x370 */ + uint8_t RESERVED_45[12]; + __IO uint32_t INIT_MEM_DATA_HIGH; /**< Write data Register, offset: 0x380 */ + uint8_t RESERVED_46[12]; + __IO uint32_t IRQ_MASK; /**< PXP IRQ Mask Register, offset: 0x390 */ + __IO uint32_t IRQ_MASK_SET; /**< PXP IRQ Mask Register, offset: 0x394 */ + __IO uint32_t IRQ_MASK_CLR; /**< PXP IRQ Mask Register, offset: 0x398 */ + __IO uint32_t IRQ_MASK_TOG; /**< PXP IRQ Mask Register, offset: 0x39C */ + __IO uint32_t IRQ; /**< PXP Interrupt Register, offset: 0x3A0 */ + __IO uint32_t IRQ_SET; /**< PXP Interrupt Register, offset: 0x3A4 */ + __IO uint32_t IRQ_CLR; /**< PXP Interrupt Register, offset: 0x3A8 */ + __IO uint32_t IRQ_TOG; /**< PXP Interrupt Register, offset: 0x3AC */ + __IO uint32_t NEXT_EN; /**< PXP NEXT Buffer Enable select Register, offset: 0x3B0 */ + __IO uint32_t NEXT_EN_SET; /**< PXP NEXT Buffer Enable select Register, offset: 0x3B4 */ + __IO uint32_t NEXT_EN_CLR; /**< PXP NEXT Buffer Enable select Register, offset: 0x3B8 */ + __IO uint32_t NEXT_EN_TOG; /**< PXP NEXT Buffer Enable select Register, offset: 0x3BC */ + uint8_t RESERVED_47[64]; + __IO uint32_t NEXT; /**< Next Frame Pointer, offset: 0x400 */ + uint8_t RESERVED_48[12]; + __IO uint32_t DEBUGCTRL; /**< Debug Control Register, offset: 0x410 */ + uint8_t RESERVED_49[12]; + __I uint32_t DEBUGr; /**< Debug Register, offset: 0x420 */ + uint8_t RESERVED_50[12]; + __I uint32_t VERSION; /**< Version Register, offset: 0x430 */ + uint8_t RESERVED_51[1484]; + __IO uint32_t DITHER_STORE_SIZE_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0xA00 */ + uint8_t RESERVED_52[1788]; + __IO uint32_t WFB_FETCH_CTRL; /**< Fetch engine Control for WFE B Register, offset: 0x1100 */ + __IO uint32_t WFB_FETCH_CTRL_SET; /**< Fetch engine Control for WFE B Register, offset: 0x1104 */ + __IO uint32_t WFB_FETCH_CTRL_CLR; /**< Fetch engine Control for WFE B Register, offset: 0x1108 */ + __IO uint32_t WFB_FETCH_CTRL_TOG; /**< Fetch engine Control for WFE B Register, offset: 0x110C */ + __IO uint32_t WFB_FETCH_BUF1_ADDR; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1110 */ + uint8_t RESERVED_53[12]; + __IO uint32_t WFB_FETCH_BUF1_PITCH; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1120 */ + uint8_t RESERVED_54[12]; + __IO uint32_t WFB_FETCH_BUF1_SIZE; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1130 */ + uint8_t RESERVED_55[12]; + __IO uint32_t WFB_FETCH_BUF2_ADDR; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1140 */ + uint8_t RESERVED_56[12]; + __IO uint32_t WFB_FETCH_BUF2_PITCH; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1150 */ + uint8_t RESERVED_57[12]; + __IO uint32_t WFB_FETCH_BUF2_SIZE; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1160 */ + uint8_t RESERVED_58[12]; + __IO uint32_t WFB_ARRAY_PIXEL0_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1170 */ + uint8_t RESERVED_59[12]; + __IO uint32_t WFB_ARRAY_PIXEL1_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1180 */ + uint8_t RESERVED_60[12]; + __IO uint32_t WFB_ARRAY_PIXEL2_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1190 */ + uint8_t RESERVED_61[12]; + __IO uint32_t WFB_ARRAY_PIXEL3_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11A0 */ + uint8_t RESERVED_62[12]; + __IO uint32_t WFB_ARRAY_PIXEL4_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11B0 */ + uint8_t RESERVED_63[12]; + __IO uint32_t WFB_ARRAY_PIXEL5_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11C0 */ + uint8_t RESERVED_64[12]; + __IO uint32_t WFB_ARRAY_PIXEL6_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11D0 */ + uint8_t RESERVED_65[12]; + __IO uint32_t WFB_ARRAY_PIXEL7_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11E0 */ + uint8_t RESERVED_66[12]; + __IO uint32_t WFB_ARRAY_FLAG0_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11F0 */ + uint8_t RESERVED_67[12]; + __IO uint32_t WFB_ARRAY_FLAG1_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1200 */ + uint8_t RESERVED_68[12]; + __IO uint32_t WFB_ARRAY_FLAG2_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1210 */ + uint8_t RESERVED_69[12]; + __IO uint32_t WFB_ARRAY_FLAG3_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1220 */ + uint8_t RESERVED_70[12]; + __IO uint32_t WFB_ARRAY_FLAG4_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1230 */ + uint8_t RESERVED_71[12]; + __IO uint32_t WFB_ARRAY_FLAG5_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1240 */ + uint8_t RESERVED_72[12]; + __IO uint32_t WFB_ARRAY_FLAG6_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1250 */ + uint8_t RESERVED_73[12]; + __IO uint32_t WFB_ARRAY_FLAG7_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1260 */ + uint8_t RESERVED_74[12]; + __IO uint32_t WFB_FETCH_BUF1_CORD; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x1270 */ + uint8_t RESERVED_75[12]; + __IO uint32_t WFB_FETCH_BUF2_CORD; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x1280 */ + uint8_t RESERVED_76[12]; + __IO uint32_t WFB_ARRAY_FLAG8_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x1290 */ + uint8_t RESERVED_77[12]; + __IO uint32_t WFB_ARRAY_FLAG9_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12A0 */ + uint8_t RESERVED_78[12]; + __IO uint32_t WFB_ARRAY_FLAG10_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12B0 */ + uint8_t RESERVED_79[12]; + __IO uint32_t WFB_ARRAY_FLAG11_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12C0 */ + uint8_t RESERVED_80[12]; + __IO uint32_t WFB_ARRAY_FLAG12_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12D0 */ + uint8_t RESERVED_81[12]; + __IO uint32_t WFB_ARRAY_FLAG13_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12E0 */ + uint8_t RESERVED_82[12]; + __IO uint32_t WFB_ARRAY_FLAG14_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12F0 */ + uint8_t RESERVED_83[12]; + __IO uint32_t WFB_ARRAY_FLAG15_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x1300 */ + uint8_t RESERVED_84[12]; + __IO uint32_t WFB_ARRAY_REG0; /**< This register defines software define pixels for wfb fetch sub-block., offset: 0x1310 */ + uint8_t RESERVED_85[12]; + __IO uint32_t WFB_ARRAY_REG1; /**< This register defines software define pixels for wfb fetch sub-block., offset: 0x1320 */ + uint8_t RESERVED_86[12]; + __IO uint32_t WFB_ARRAY_REG2; /**< This register defines software define pixels for wfb fetch sub-block., offset: 0x1330 */ + uint8_t RESERVED_87[12]; + __IO uint32_t WFE_B_STORE_CTRL_CH0; /**< Store engine Control Channel 0 Register, offset: 0x1340 */ + __IO uint32_t WFE_B_STORE_CTRL_CH0_SET; /**< Store engine Control Channel 0 Register, offset: 0x1344 */ + __IO uint32_t WFE_B_STORE_CTRL_CH0_CLR; /**< Store engine Control Channel 0 Register, offset: 0x1348 */ + __IO uint32_t WFE_B_STORE_CTRL_CH0_TOG; /**< Store engine Control Channel 0 Register, offset: 0x134C */ + __IO uint32_t WFE_B_STORE_CTRL_CH1; /**< Store engine Control Channel 1 Register, offset: 0x1350 */ + __IO uint32_t WFE_B_STORE_CTRL_CH1_SET; /**< Store engine Control Channel 1 Register, offset: 0x1354 */ + __IO uint32_t WFE_B_STORE_CTRL_CH1_CLR; /**< Store engine Control Channel 1 Register, offset: 0x1358 */ + __IO uint32_t WFE_B_STORE_CTRL_CH1_TOG; /**< Store engine Control Channel 1 Register, offset: 0x135C */ + __I uint32_t WFE_B_STORE_STATUS_CH0; /**< Store engine status Channel 0 Register, offset: 0x1360 */ + uint8_t RESERVED_88[12]; + __I uint32_t WFE_B_STORE_STATUS_CH1; /**< Store engine status Channel 1 Register, offset: 0x1370 */ + uint8_t RESERVED_89[12]; + __IO uint32_t WFE_B_STORE_SIZE_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1380 */ + uint8_t RESERVED_90[12]; + __IO uint32_t WFE_B_STORE_SIZE_CH1; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1390 */ + uint8_t RESERVED_91[12]; + __IO uint32_t WFE_B_STORE_PITCH; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13A0 */ + uint8_t RESERVED_92[12]; + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13B0 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0_SET; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13B4 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0_CLR; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13B8 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0_TOG; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13BC */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13C0 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1_SET; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13C4 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1_CLR; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13C8 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1_TOG; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13CC */ + uint8_t RESERVED_93[64]; + __IO uint32_t WFE_B_STORE_ADDR_0_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1410 */ + uint8_t RESERVED_94[12]; + __IO uint32_t WFE_B_STORE_ADDR_1_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1420 */ + uint8_t RESERVED_95[12]; + __IO uint32_t WFE_B_STORE_FILL_DATA_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1430 */ + uint8_t RESERVED_96[12]; + __IO uint32_t WFE_B_STORE_ADDR_0_CH1; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1440 */ + uint8_t RESERVED_97[12]; + __IO uint32_t WFE_B_STORE_ADDR_1_CH1; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1450 */ + uint8_t RESERVED_98[12]; + __IO uint32_t WFE_B_STORE_D_MASK0_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1460 */ + uint8_t RESERVED_99[12]; + __IO uint32_t WFE_B_STORE_D_MASK0_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1470 */ + uint8_t RESERVED_100[12]; + __IO uint32_t WFE_B_STORE_D_MASK1_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1480 */ + uint8_t RESERVED_101[12]; + __IO uint32_t WFE_B_STORE_D_MASK1_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1490 */ + uint8_t RESERVED_102[12]; + __IO uint32_t WFE_B_STORE_D_MASK2_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14A0 */ + uint8_t RESERVED_103[12]; + __IO uint32_t WFE_B_STORE_D_MASK2_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14B0 */ + uint8_t RESERVED_104[12]; + __IO uint32_t WFE_B_STORE_D_MASK3_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14C0 */ + uint8_t RESERVED_105[12]; + __IO uint32_t WFE_B_STORE_D_MASK3_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14D0 */ + uint8_t RESERVED_106[12]; + __IO uint32_t WFE_B_STORE_D_MASK4_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14E0 */ + uint8_t RESERVED_107[12]; + __IO uint32_t WFE_B_STORE_D_MASK4_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14F0 */ + uint8_t RESERVED_108[12]; + __IO uint32_t WFE_B_STORE_D_MASK5_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1500 */ + uint8_t RESERVED_109[12]; + __IO uint32_t WFE_B_STORE_D_MASK5_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1510 */ + uint8_t RESERVED_110[12]; + __IO uint32_t WFE_B_STORE_D_MASK6_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1520 */ + uint8_t RESERVED_111[12]; + __IO uint32_t WFE_B_STORE_D_MASK6_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1530 */ + uint8_t RESERVED_112[12]; + __IO uint32_t WFE_B_STORE_D_MASK7_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1540 */ + uint8_t RESERVED_113[12]; + __IO uint32_t WFE_B_STORE_D_MASK7_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1550 */ + uint8_t RESERVED_114[12]; + __IO uint32_t WFE_B_STORE_D_SHIFT_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1560 */ + uint8_t RESERVED_115[12]; + __IO uint32_t WFE_B_STORE_D_SHIFT_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1570 */ + uint8_t RESERVED_116[12]; + __IO uint32_t WFE_B_STORE_F_SHIFT_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1580 */ + uint8_t RESERVED_117[12]; + __IO uint32_t WFE_B_STORE_F_SHIFT_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1590 */ + uint8_t RESERVED_118[12]; + __IO uint32_t WFE_B_STORE_F_MASK_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x15A0 */ + uint8_t RESERVED_119[12]; + __IO uint32_t WFE_B_STORE_F_MASK_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x15B0 */ + uint8_t RESERVED_120[28]; + __IO uint32_t FETCH_WFE_B_DEBUG; /**< This register holds the debug bits for the prefetch engine for WFE B., offset: 0x15D0 */ + uint8_t RESERVED_121[156]; + __IO uint32_t DITHER_CTRL; /**< Dither Control Register 0, offset: 0x1670 */ + __IO uint32_t DITHER_CTRL_SET; /**< Dither Control Register 0, offset: 0x1674 */ + __IO uint32_t DITHER_CTRL_CLR; /**< Dither Control Register 0, offset: 0x1678 */ + __IO uint32_t DITHER_CTRL_TOG; /**< Dither Control Register 0, offset: 0x167C */ + __IO uint32_t DITHER_FINAL_LUT_DATA0; /**< Final stage lookup value Register, offset: 0x1680 */ + __IO uint32_t DITHER_FINAL_LUT_DATA0_SET; /**< Final stage lookup value Register, offset: 0x1684 */ + __IO uint32_t DITHER_FINAL_LUT_DATA0_CLR; /**< Final stage lookup value Register, offset: 0x1688 */ + __IO uint32_t DITHER_FINAL_LUT_DATA0_TOG; /**< Final stage lookup value Register, offset: 0x168C */ + __IO uint32_t DITHER_FINAL_LUT_DATA1; /**< Final stage lookup value Register, offset: 0x1690 */ + __IO uint32_t DITHER_FINAL_LUT_DATA1_SET; /**< Final stage lookup value Register, offset: 0x1694 */ + __IO uint32_t DITHER_FINAL_LUT_DATA1_CLR; /**< Final stage lookup value Register, offset: 0x1698 */ + __IO uint32_t DITHER_FINAL_LUT_DATA1_TOG; /**< Final stage lookup value Register, offset: 0x169C */ + __IO uint32_t DITHER_FINAL_LUT_DATA2; /**< Final stage lookup value Register, offset: 0x16A0 */ + __IO uint32_t DITHER_FINAL_LUT_DATA2_SET; /**< Final stage lookup value Register, offset: 0x16A4 */ + __IO uint32_t DITHER_FINAL_LUT_DATA2_CLR; /**< Final stage lookup value Register, offset: 0x16A8 */ + __IO uint32_t DITHER_FINAL_LUT_DATA2_TOG; /**< Final stage lookup value Register, offset: 0x16AC */ + __IO uint32_t DITHER_FINAL_LUT_DATA3; /**< Final stage lookup value Register, offset: 0x16B0 */ + __IO uint32_t DITHER_FINAL_LUT_DATA3_SET; /**< Final stage lookup value Register, offset: 0x16B4 */ + __IO uint32_t DITHER_FINAL_LUT_DATA3_CLR; /**< Final stage lookup value Register, offset: 0x16B8 */ + __IO uint32_t DITHER_FINAL_LUT_DATA3_TOG; /**< Final stage lookup value Register, offset: 0x16BC */ + uint8_t RESERVED_122[1600]; + __IO uint32_t WFE_B_CTRL; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D00 */ + __IO uint32_t WFE_B_CTRL_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D04 */ + __IO uint32_t WFE_B_CTRL_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D08 */ + __IO uint32_t WFE_B_CTRL_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D0C */ + __IO uint32_t WFE_B_DIMENSIONS; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D10 */ + uint8_t RESERVED_123[12]; + __IO uint32_t WFE_B_OFFSET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D20 */ + uint8_t RESERVED_124[12]; + __IO uint32_t WFE_B_SW_DATA_REGS; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D30 */ + uint8_t RESERVED_125[12]; + __IO uint32_t WFE_B_SW_FLAG_REGS; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D40 */ + uint8_t RESERVED_126[12]; + __IO uint32_t WFE_B_STAGE1_MUX0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D50 */ + __IO uint32_t WFE_B_STAGE1_MUX0_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D54 */ + __IO uint32_t WFE_B_STAGE1_MUX0_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D58 */ + __IO uint32_t WFE_B_STAGE1_MUX0_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D5C */ + __IO uint32_t WFE_B_STAGE1_MUX1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D60 */ + __IO uint32_t WFE_B_STAGE1_MUX1_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D64 */ + __IO uint32_t WFE_B_STAGE1_MUX1_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D68 */ + __IO uint32_t WFE_B_STAGE1_MUX1_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D6C */ + __IO uint32_t WFE_B_STAGE1_MUX2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D70 */ + __IO uint32_t WFE_B_STAGE1_MUX2_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D74 */ + __IO uint32_t WFE_B_STAGE1_MUX2_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D78 */ + __IO uint32_t WFE_B_STAGE1_MUX2_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D7C */ + __IO uint32_t WFE_B_STAGE1_MUX3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D80 */ + __IO uint32_t WFE_B_STAGE1_MUX3_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D84 */ + __IO uint32_t WFE_B_STAGE1_MUX3_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D88 */ + __IO uint32_t WFE_B_STAGE1_MUX3_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D8C */ + __IO uint32_t WFE_B_STAGE1_MUX4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D90 */ + __IO uint32_t WFE_B_STAGE1_MUX4_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D94 */ + __IO uint32_t WFE_B_STAGE1_MUX4_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D98 */ + __IO uint32_t WFE_B_STAGE1_MUX4_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D9C */ + __IO uint32_t WFE_B_STAGE1_MUX5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DA0 */ + __IO uint32_t WFE_B_STAGE1_MUX5_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DA4 */ + __IO uint32_t WFE_B_STAGE1_MUX5_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DA8 */ + __IO uint32_t WFE_B_STAGE1_MUX5_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DAC */ + __IO uint32_t WFE_B_STAGE1_MUX6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DB0 */ + __IO uint32_t WFE_B_STAGE1_MUX6_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DB4 */ + __IO uint32_t WFE_B_STAGE1_MUX6_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DB8 */ + __IO uint32_t WFE_B_STAGE1_MUX6_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DBC */ + __IO uint32_t WFE_B_STAGE1_MUX7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DC0 */ + __IO uint32_t WFE_B_STAGE1_MUX7_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DC4 */ + __IO uint32_t WFE_B_STAGE1_MUX7_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DC8 */ + __IO uint32_t WFE_B_STAGE1_MUX7_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DCC */ + __IO uint32_t WFE_B_STAGE1_MUX8; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DD0 */ + __IO uint32_t WFE_B_STAGE1_MUX8_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DD4 */ + __IO uint32_t WFE_B_STAGE1_MUX8_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DD8 */ + __IO uint32_t WFE_B_STAGE1_MUX8_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DDC */ + __IO uint32_t WFE_B_STAGE2_MUX0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DE0 */ + __IO uint32_t WFE_B_STAGE2_MUX0_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DE4 */ + __IO uint32_t WFE_B_STAGE2_MUX0_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DE8 */ + __IO uint32_t WFE_B_STAGE2_MUX0_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DEC */ + __IO uint32_t WFE_B_STAGE2_MUX1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DF0 */ + __IO uint32_t WFE_B_STAGE2_MUX1_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DF4 */ + __IO uint32_t WFE_B_STAGE2_MUX1_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DF8 */ + __IO uint32_t WFE_B_STAGE2_MUX1_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DFC */ + __IO uint32_t WFE_B_STAGE2_MUX2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E00 */ + __IO uint32_t WFE_B_STAGE2_MUX2_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E04 */ + __IO uint32_t WFE_B_STAGE2_MUX2_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E08 */ + __IO uint32_t WFE_B_STAGE2_MUX2_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E0C */ + __IO uint32_t WFE_B_STAGE2_MUX3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E10 */ + __IO uint32_t WFE_B_STAGE2_MUX3_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E14 */ + __IO uint32_t WFE_B_STAGE2_MUX3_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E18 */ + __IO uint32_t WFE_B_STAGE2_MUX3_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E1C */ + __IO uint32_t WFE_B_STAGE2_MUX4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E20 */ + __IO uint32_t WFE_B_STAGE2_MUX4_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E24 */ + __IO uint32_t WFE_B_STAGE2_MUX4_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E28 */ + __IO uint32_t WFE_B_STAGE2_MUX4_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E2C */ + __IO uint32_t WFE_B_STAGE2_MUX5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E30 */ + __IO uint32_t WFE_B_STAGE2_MUX5_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E34 */ + __IO uint32_t WFE_B_STAGE2_MUX5_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E38 */ + __IO uint32_t WFE_B_STAGE2_MUX5_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E3C */ + __IO uint32_t WFE_B_STAGE2_MUX6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E40 */ + __IO uint32_t WFE_B_STAGE2_MUX6_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E44 */ + __IO uint32_t WFE_B_STAGE2_MUX6_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E48 */ + __IO uint32_t WFE_B_STAGE2_MUX6_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E4C */ + __IO uint32_t WFE_B_STAGE2_MUX7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E50 */ + __IO uint32_t WFE_B_STAGE2_MUX7_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E54 */ + __IO uint32_t WFE_B_STAGE2_MUX7_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E58 */ + __IO uint32_t WFE_B_STAGE2_MUX7_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E5C */ + __IO uint32_t WFE_B_STAGE2_MUX8; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E60 */ + __IO uint32_t WFE_B_STAGE2_MUX8_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E64 */ + __IO uint32_t WFE_B_STAGE2_MUX8_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E68 */ + __IO uint32_t WFE_B_STAGE2_MUX8_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E6C */ + __IO uint32_t WFE_B_STAGE2_MUX9; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E70 */ + __IO uint32_t WFE_B_STAGE2_MUX9_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E74 */ + __IO uint32_t WFE_B_STAGE2_MUX9_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E78 */ + __IO uint32_t WFE_B_STAGE2_MUX9_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E7C */ + __IO uint32_t WFE_B_STAGE2_MUX10; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E80 */ + __IO uint32_t WFE_B_STAGE2_MUX10_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E84 */ + __IO uint32_t WFE_B_STAGE2_MUX10_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E88 */ + __IO uint32_t WFE_B_STAGE2_MUX10_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E8C */ + __IO uint32_t WFE_B_STAGE2_MUX11; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E90 */ + __IO uint32_t WFE_B_STAGE2_MUX11_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E94 */ + __IO uint32_t WFE_B_STAGE2_MUX11_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E98 */ + __IO uint32_t WFE_B_STAGE2_MUX11_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E9C */ + __IO uint32_t WFE_B_STAGE2_MUX12; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EA0 */ + __IO uint32_t WFE_B_STAGE2_MUX12_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EA4 */ + __IO uint32_t WFE_B_STAGE2_MUX12_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EA8 */ + __IO uint32_t WFE_B_STAGE2_MUX12_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EAC */ + __IO uint32_t WFE_B_STAGE3_MUX0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EB0 */ + __IO uint32_t WFE_B_STAGE3_MUX0_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EB4 */ + __IO uint32_t WFE_B_STAGE3_MUX0_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EB8 */ + __IO uint32_t WFE_B_STAGE3_MUX0_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EBC */ + __IO uint32_t WFE_B_STAGE3_MUX1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EC0 */ + __IO uint32_t WFE_B_STAGE3_MUX1_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EC4 */ + __IO uint32_t WFE_B_STAGE3_MUX1_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EC8 */ + __IO uint32_t WFE_B_STAGE3_MUX1_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1ECC */ + __IO uint32_t WFE_B_STAGE3_MUX2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1ED0 */ + __IO uint32_t WFE_B_STAGE3_MUX2_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1ED4 */ + __IO uint32_t WFE_B_STAGE3_MUX2_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1ED8 */ + __IO uint32_t WFE_B_STAGE3_MUX2_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EDC */ + __IO uint32_t WFE_B_STAGE3_MUX3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EE0 */ + __IO uint32_t WFE_B_STAGE3_MUX3_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EE4 */ + __IO uint32_t WFE_B_STAGE3_MUX3_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EE8 */ + __IO uint32_t WFE_B_STAGE3_MUX3_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EEC */ + __IO uint32_t WFE_B_STAGE3_MUX4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EF0 */ + __IO uint32_t WFE_B_STAGE3_MUX4_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EF4 */ + __IO uint32_t WFE_B_STAGE3_MUX4_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EF8 */ + __IO uint32_t WFE_B_STAGE3_MUX4_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EFC */ + __IO uint32_t WFE_B_STAGE3_MUX5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F00 */ + __IO uint32_t WFE_B_STAGE3_MUX5_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F04 */ + __IO uint32_t WFE_B_STAGE3_MUX5_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F08 */ + __IO uint32_t WFE_B_STAGE3_MUX5_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F0C */ + __IO uint32_t WFE_B_STAGE3_MUX6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F10 */ + __IO uint32_t WFE_B_STAGE3_MUX6_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F14 */ + __IO uint32_t WFE_B_STAGE3_MUX6_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F18 */ + __IO uint32_t WFE_B_STAGE3_MUX6_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F1C */ + __IO uint32_t WFE_B_STAGE3_MUX7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F20 */ + __IO uint32_t WFE_B_STAGE3_MUX7_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F24 */ + __IO uint32_t WFE_B_STAGE3_MUX7_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F28 */ + __IO uint32_t WFE_B_STAGE3_MUX7_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F2C */ + __IO uint32_t WFE_B_STAGE3_MUX8; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F30 */ + __IO uint32_t WFE_B_STAGE3_MUX8_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F34 */ + __IO uint32_t WFE_B_STAGE3_MUX8_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F38 */ + __IO uint32_t WFE_B_STAGE3_MUX8_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F3C */ + __IO uint32_t WFE_B_STAGE3_MUX9; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F40 */ + __IO uint32_t WFE_B_STAGE3_MUX9_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F44 */ + __IO uint32_t WFE_B_STAGE3_MUX9_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F48 */ + __IO uint32_t WFE_B_STAGE3_MUX9_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F4C */ + __IO uint32_t WFE_B_STAGE3_MUX10; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F50 */ + __IO uint32_t WFE_B_STAGE3_MUX10_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F54 */ + __IO uint32_t WFE_B_STAGE3_MUX10_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F58 */ + __IO uint32_t WFE_B_STAGE3_MUX10_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F5C */ + __IO uint32_t WFE_B_STG1_5X8_OUT0_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F60 */ + uint8_t RESERVED_127[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F70 */ + uint8_t RESERVED_128[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F80 */ + uint8_t RESERVED_129[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F90 */ + uint8_t RESERVED_130[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FA0 */ + uint8_t RESERVED_131[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FB0 */ + uint8_t RESERVED_132[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FC0 */ + uint8_t RESERVED_133[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FD0 */ + uint8_t RESERVED_134[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FE0 */ + uint8_t RESERVED_135[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FF0 */ + uint8_t RESERVED_136[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2000 */ + uint8_t RESERVED_137[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2010 */ + uint8_t RESERVED_138[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2020 */ + uint8_t RESERVED_139[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2030 */ + uint8_t RESERVED_140[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2040 */ + uint8_t RESERVED_141[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2050 */ + uint8_t RESERVED_142[12]; + __IO uint32_t WFE_B_STAGE1_5X8_MASKS_0; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x8 LUT., offset: 0x2060 */ + uint8_t RESERVED_143[12]; + __IO uint32_t WFE_B_STG1_5X1_OUT0; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 1., offset: 0x2070 */ + uint8_t RESERVED_144[12]; + __IO uint32_t WFE_B_STG1_5X1_MASKS; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x1 LUT., offset: 0x2080 */ + uint8_t RESERVED_145[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2090 */ + uint8_t RESERVED_146[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20A0 */ + uint8_t RESERVED_147[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20B0 */ + uint8_t RESERVED_148[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20C0 */ + uint8_t RESERVED_149[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20D0 */ + uint8_t RESERVED_150[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20E0 */ + uint8_t RESERVED_151[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20F0 */ + uint8_t RESERVED_152[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2100 */ + uint8_t RESERVED_153[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2110 */ + uint8_t RESERVED_154[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2120 */ + uint8_t RESERVED_155[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2130 */ + uint8_t RESERVED_156[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2140 */ + uint8_t RESERVED_157[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2150 */ + uint8_t RESERVED_158[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2160 */ + uint8_t RESERVED_159[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2170 */ + uint8_t RESERVED_160[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2180 */ + uint8_t RESERVED_161[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2190 */ + uint8_t RESERVED_162[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21A0 */ + uint8_t RESERVED_163[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21B0 */ + uint8_t RESERVED_164[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21C0 */ + uint8_t RESERVED_165[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21D0 */ + uint8_t RESERVED_166[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21E0 */ + uint8_t RESERVED_167[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21F0 */ + uint8_t RESERVED_168[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2200 */ + uint8_t RESERVED_169[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2210 */ + uint8_t RESERVED_170[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2220 */ + uint8_t RESERVED_171[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2230 */ + uint8_t RESERVED_172[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2240 */ + uint8_t RESERVED_173[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2250 */ + uint8_t RESERVED_174[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2260 */ + uint8_t RESERVED_175[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2270 */ + uint8_t RESERVED_176[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2280 */ + uint8_t RESERVED_177[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2290 */ + uint8_t RESERVED_178[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22A0 */ + uint8_t RESERVED_179[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22B0 */ + uint8_t RESERVED_180[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22C0 */ + uint8_t RESERVED_181[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22D0 */ + uint8_t RESERVED_182[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22E0 */ + uint8_t RESERVED_183[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22F0 */ + uint8_t RESERVED_184[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2300 */ + uint8_t RESERVED_185[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2310 */ + uint8_t RESERVED_186[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2320 */ + uint8_t RESERVED_187[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2330 */ + uint8_t RESERVED_188[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2340 */ + uint8_t RESERVED_189[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2350 */ + uint8_t RESERVED_190[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2360 */ + uint8_t RESERVED_191[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2370 */ + uint8_t RESERVED_192[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2380 */ + uint8_t RESERVED_193[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2390 */ + uint8_t RESERVED_194[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23A0 */ + uint8_t RESERVED_195[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23B0 */ + uint8_t RESERVED_196[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23C0 */ + uint8_t RESERVED_197[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23D0 */ + uint8_t RESERVED_198[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23E0 */ + uint8_t RESERVED_199[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23F0 */ + uint8_t RESERVED_200[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2400 */ + uint8_t RESERVED_201[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2410 */ + uint8_t RESERVED_202[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2420 */ + uint8_t RESERVED_203[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2430 */ + uint8_t RESERVED_204[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2440 */ + uint8_t RESERVED_205[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2450 */ + uint8_t RESERVED_206[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2460 */ + uint8_t RESERVED_207[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2470 */ + uint8_t RESERVED_208[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2480 */ + uint8_t RESERVED_209[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2490 */ + uint8_t RESERVED_210[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24A0 */ + uint8_t RESERVED_211[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24B0 */ + uint8_t RESERVED_212[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24C0 */ + uint8_t RESERVED_213[28]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24E0 */ + uint8_t RESERVED_214[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24F0 */ + uint8_t RESERVED_215[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2500 */ + uint8_t RESERVED_216[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2510 */ + uint8_t RESERVED_217[12]; + __IO uint32_t WFE_B_STAGE2_5X6_MASKS_0; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x6 LUT., offset: 0x2520 */ + uint8_t RESERVED_218[12]; + __IO uint32_t WFE_B_STAGE2_5X6_ADDR_0; /**< Each Address specifies the MUX position in the MUX array. There is one MUXADDR per 5x6 LUT., offset: 0x2530 */ + uint8_t RESERVED_219[12]; + __IO uint32_t WFE_B_STG2_5X1_OUT0; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 2., offset: 0x2540 */ + uint8_t RESERVED_220[12]; + __IO uint32_t WFE_B_STG2_5X1_OUT1; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 2., offset: 0x2550 */ + uint8_t RESERVED_221[12]; + __IO uint32_t WFE_B_STG2_5X1_OUT2; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 2., offset: 0x2560 */ + uint8_t RESERVED_222[12]; + __IO uint32_t WFE_B_STG2_5X1_OUT3; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 2., offset: 0x2570 */ + uint8_t RESERVED_223[12]; + __IO uint32_t WFE_B_STG2_5X1_MASKS; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x1 LUT., offset: 0x2580 */ + uint8_t RESERVED_224[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2590 */ + uint8_t RESERVED_225[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25A0 */ + uint8_t RESERVED_226[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25B0 */ + uint8_t RESERVED_227[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25C0 */ + uint8_t RESERVED_228[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25D0 */ + uint8_t RESERVED_229[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25E0 */ + uint8_t RESERVED_230[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25F0 */ + uint8_t RESERVED_231[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2600 */ + uint8_t RESERVED_232[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2610 */ + uint8_t RESERVED_233[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2620 */ + uint8_t RESERVED_234[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2630 */ + uint8_t RESERVED_235[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2640 */ + uint8_t RESERVED_236[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2650 */ + uint8_t RESERVED_237[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2660 */ + uint8_t RESERVED_238[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2670 */ + uint8_t RESERVED_239[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2680 */ + uint8_t RESERVED_240[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2690 */ + uint8_t RESERVED_241[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26A0 */ + uint8_t RESERVED_242[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26B0 */ + uint8_t RESERVED_243[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26C0 */ + uint8_t RESERVED_244[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26D0 */ + uint8_t RESERVED_245[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26E0 */ + uint8_t RESERVED_246[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26F0 */ + uint8_t RESERVED_247[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2700 */ + uint8_t RESERVED_248[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2710 */ + uint8_t RESERVED_249[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2720 */ + uint8_t RESERVED_250[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2730 */ + uint8_t RESERVED_251[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2740 */ + uint8_t RESERVED_252[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2750 */ + uint8_t RESERVED_253[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2760 */ + uint8_t RESERVED_254[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2770 */ + uint8_t RESERVED_255[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2780 */ + uint8_t RESERVED_256[12]; + __IO uint32_t WFE_B_STG3_F8X1_MASKS; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 8x1 LUT., offset: 0x2790 */ + uint8_t RESERVED_257[268]; + __IO uint32_t ALU_B_CTRL; /**< This register defines the control bits for the pxp alu sub-block., offset: 0x28A0 */ + __IO uint32_t ALU_B_CTRL_SET; /**< This register defines the control bits for the pxp alu sub-block., offset: 0x28A4 */ + __IO uint32_t ALU_B_CTRL_CLR; /**< This register defines the control bits for the pxp alu sub-block., offset: 0x28A8 */ + __IO uint32_t ALU_B_CTRL_TOG; /**< This register defines the control bits for the pxp alu sub-block., offset: 0x28AC */ + __IO uint32_t ALU_B_BUF_SIZE; /**< This register defines the size of the buffer to be processed by the alu engine., offset: 0x28B0 */ + uint8_t RESERVED_258[12]; + __IO uint32_t ALU_B_INST_ENTRY; /**< This register defines the Entry Address for the Instruction Memory of the ALU., offset: 0x28C0 */ + uint8_t RESERVED_259[12]; + __IO uint32_t ALU_B_PARAM; /**< This register defines the parameter used by SW running on ALU., offset: 0x28D0 */ + uint8_t RESERVED_260[12]; + __IO uint32_t ALU_B_CONFIG; /**< This register defines the hw configuration options for the alu core., offset: 0x28E0 */ + uint8_t RESERVED_261[12]; + __IO uint32_t ALU_B_LUT_CONFIG; /**< This register defines the hw configuration options for the LUT, offset: 0x28F0 */ + __IO uint32_t ALU_B_LUT_CONFIG_SET; /**< This register defines the hw configuration options for the LUT, offset: 0x28F4 */ + __IO uint32_t ALU_B_LUT_CONFIG_CLR; /**< This register defines the hw configuration options for the LUT, offset: 0x28F8 */ + __IO uint32_t ALU_B_LUT_CONFIG_TOG; /**< This register defines the hw configuration options for the LUT, offset: 0x28FC */ + __IO uint32_t ALU_B_LUT_DATA0; /**< This register defines the lower 32-bit data for the LUT, offset: 0x2900 */ + uint8_t RESERVED_262[12]; + __IO uint32_t ALU_B_LUT_DATA1; /**< This register defines the higher 32-bit data for the LUT, offset: 0x2910 */ + uint8_t RESERVED_263[12]; + __IO uint32_t ALU_B_DBG; /**< This register is used for debugging alu block, offset: 0x2920 */ + uint8_t RESERVED_264[220]; + __IO uint32_t HIST_A_CTRL; /**< Histogram Control Register., offset: 0x2A00 */ + uint8_t RESERVED_265[12]; + __IO uint32_t HIST_A_MASK; /**< Histogram Pixel Mask Register., offset: 0x2A10 */ + uint8_t RESERVED_266[12]; + __IO uint32_t HIST_A_BUF_SIZE; /**< Histogram Pixel Buffer Size Register., offset: 0x2A20 */ + uint8_t RESERVED_267[12]; + __I uint32_t HIST_A_TOTAL_PIXEL; /**< Total Number of Pixels Used by Histogram Engine., offset: 0x2A30 */ + uint8_t RESERVED_268[12]; + __I uint32_t HIST_A_ACTIVE_AREA_X; /**< The X Coordinate Offset for Active Area., offset: 0x2A40 */ + uint8_t RESERVED_269[12]; + __I uint32_t HIST_A_ACTIVE_AREA_Y; /**< The Y Coordinate Offset for Active Area., offset: 0x2A50 */ + uint8_t RESERVED_270[12]; + __I uint32_t HIST_A_RAW_STAT0; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2A60 */ + uint8_t RESERVED_271[12]; + __I uint32_t HIST_A_RAW_STAT1; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2A70 */ + uint8_t RESERVED_272[12]; + __IO uint32_t HIST_B_CTRL; /**< Histogram Control Register., offset: 0x2A80 */ + uint8_t RESERVED_273[12]; + __IO uint32_t HIST_B_MASK; /**< Histogram Pixel Mask Register., offset: 0x2A90 */ + uint8_t RESERVED_274[12]; + __IO uint32_t HIST_B_BUF_SIZE; /**< Histogram Pixel Buffer Size Register., offset: 0x2AA0 */ + uint8_t RESERVED_275[12]; + __I uint32_t HIST_B_TOTAL_PIXEL; /**< Total Number of Pixels Used by Histogram Engine., offset: 0x2AB0 */ + uint8_t RESERVED_276[12]; + __I uint32_t HIST_B_ACTIVE_AREA_X; /**< The X Coordinate Offset for Active Area., offset: 0x2AC0 */ + uint8_t RESERVED_277[12]; + __I uint32_t HIST_B_ACTIVE_AREA_Y; /**< The Y Coordinate Offset for Active Area., offset: 0x2AD0 */ + uint8_t RESERVED_278[12]; + __I uint32_t HIST_B_RAW_STAT0; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2AE0 */ + uint8_t RESERVED_279[12]; + __I uint32_t HIST_B_RAW_STAT1; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2AF0 */ + uint8_t RESERVED_280[12]; + __IO uint32_t HIST2_PARAM; /**< 2-level Histogram Parameter Register., offset: 0x2B00 */ + uint8_t RESERVED_281[12]; + __IO uint32_t HIST4_PARAM; /**< 4-level Histogram Parameter Register., offset: 0x2B10 */ + uint8_t RESERVED_282[12]; + __IO uint32_t HIST8_PARAM0; /**< 8-level Histogram Parameter 0 Register., offset: 0x2B20 */ + uint8_t RESERVED_283[12]; + __IO uint32_t HIST8_PARAM1; /**< 8-level Histogram Parameter 1 Register., offset: 0x2B30 */ + uint8_t RESERVED_284[12]; + __IO uint32_t HIST16_PARAM0; /**< 16-level Histogram Parameter 0 Register., offset: 0x2B40 */ + uint8_t RESERVED_285[12]; + __IO uint32_t HIST16_PARAM1; /**< 16-level Histogram Parameter 1 Register., offset: 0x2B50 */ + uint8_t RESERVED_286[12]; + __IO uint32_t HIST16_PARAM2; /**< 16-level Histogram Parameter 2 Register., offset: 0x2B60 */ + uint8_t RESERVED_287[12]; + __IO uint32_t HIST16_PARAM3; /**< 16-level Histogram Parameter 3 Register., offset: 0x2B70 */ + uint8_t RESERVED_288[12]; + __IO uint32_t HIST32_PARAM0; /**< 32-level Histogram Parameter 0 Register., offset: 0x2B80 */ + uint8_t RESERVED_289[12]; + __IO uint32_t HIST32_PARAM1; /**< 32-level Histogram Parameter 1 Register., offset: 0x2B90 */ + uint8_t RESERVED_290[12]; + __IO uint32_t HIST32_PARAM2; /**< 32-level Histogram Parameter 2 Register., offset: 0x2BA0 */ + uint8_t RESERVED_291[12]; + __IO uint32_t HIST32_PARAM3; /**< 32-level Histogram Parameter 3 Register., offset: 0x2BB0 */ + uint8_t RESERVED_292[12]; + __IO uint32_t HIST32_PARAM4; /**< 32-level Histogram Parameter 0 Register., offset: 0x2BC0 */ + uint8_t RESERVED_293[12]; + __IO uint32_t HIST32_PARAM5; /**< 32-level Histogram Parameter 1 Register., offset: 0x2BD0 */ + uint8_t RESERVED_294[12]; + __IO uint32_t HIST32_PARAM6; /**< 32-level Histogram Parameter 2 Register., offset: 0x2BE0 */ + uint8_t RESERVED_295[12]; + __IO uint32_t HIST32_PARAM7; /**< 32-level Histogram Parameter 3 Register., offset: 0x2BF0 */ + uint8_t RESERVED_296[252]; + __IO uint32_t HANDSHAKE_READY_MUX0; /**< This register defines the pxp subblock handshake signals ready mux on top level., offset: 0x2CF0 */ + uint8_t RESERVED_297[12]; + __IO uint32_t HANDSHAKE_READY_MUX1; /**< This register defines the pxp subblock handshake signals ready mux on top level., offset: 0x2D00 */ + uint8_t RESERVED_298[12]; + __IO uint32_t HANDSHAKE_DONE_MUX0; /**< This register defines the pxp subblock handshake signals done mux on top level., offset: 0x2D10 */ + uint8_t RESERVED_299[12]; + __IO uint32_t HANDSHAKE_DONE_MUX1; /**< This register defines the pxp subblock handshake signals done mux on top level., offset: 0x2D20 */ +} PXP_Type; + +/* ---------------------------------------------------------------------------- + -- PXP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Register_Masks PXP Register Masks + * @{ + */ + +/*! @name CTRL - Control Register 0 */ +#define PXP_CTRL_ENABLE_MASK (0x1U) +#define PXP_CTRL_ENABLE_SHIFT (0U) +#define PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK) +#define PXP_CTRL_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK) +#define PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK (0x8U) +#define PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT (3U) +#define PXP_CTRL_LUT_DMA_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK) +#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK) +#define PXP_CTRL_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +#define PXP_CTRL_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_HANDSHAKE_ABORT_SKIP_MASK) +#define PXP_CTRL_ROTATE0_MASK (0x300U) +#define PXP_CTRL_ROTATE0_SHIFT (8U) +#define PXP_CTRL_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE0_SHIFT)) & PXP_CTRL_ROTATE0_MASK) +#define PXP_CTRL_HFLIP0_MASK (0x400U) +#define PXP_CTRL_HFLIP0_SHIFT (10U) +#define PXP_CTRL_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP0_SHIFT)) & PXP_CTRL_HFLIP0_MASK) +#define PXP_CTRL_VFLIP0_MASK (0x800U) +#define PXP_CTRL_VFLIP0_SHIFT (11U) +#define PXP_CTRL_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP0_SHIFT)) & PXP_CTRL_VFLIP0_MASK) +#define PXP_CTRL_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_ROTATE1_SHIFT (12U) +#define PXP_CTRL_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE1_SHIFT)) & PXP_CTRL_ROTATE1_MASK) +#define PXP_CTRL_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_HFLIP1_SHIFT (14U) +#define PXP_CTRL_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP1_SHIFT)) & PXP_CTRL_HFLIP1_MASK) +#define PXP_CTRL_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_VFLIP1_SHIFT (15U) +#define PXP_CTRL_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP1_SHIFT)) & PXP_CTRL_VFLIP1_MASK) +#define PXP_CTRL_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_ENABLE_PS_AS_OUT_SHIFT (16U) +#define PXP_CTRL_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_ENABLE_PS_AS_OUT_MASK) +#define PXP_CTRL_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_DITHER_SHIFT)) & PXP_CTRL_ENABLE_DITHER_MASK) +#define PXP_CTRL_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_ENABLE_WFE_B_MASK) +#define PXP_CTRL_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK) +#define PXP_CTRL_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_CSC2_SHIFT)) & PXP_CTRL_ENABLE_CSC2_MASK) +#define PXP_CTRL_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LUT_SHIFT)) & PXP_CTRL_ENABLE_LUT_MASK) +#define PXP_CTRL_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_ENABLE_ROTATE0_MASK) +#define PXP_CTRL_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_ENABLE_ROTATE1_MASK) +#define PXP_CTRL_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK) +#define PXP_CTRL_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_CLKGATE_SHIFT (30U) +#define PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK) +#define PXP_CTRL_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_SFTRST_SHIFT (31U) +#define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK) + +/*! @name CTRL_SET - Control Register 0 */ +#define PXP_CTRL_SET_ENABLE_MASK (0x1U) +#define PXP_CTRL_SET_ENABLE_SHIFT (0U) +#define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK) +#define PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_MASK (0x8U) +#define PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_SHIFT (3U) +#define PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_MASK) +#define PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_MASK) +#define PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +#define PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_MASK) +#define PXP_CTRL_SET_ROTATE0_MASK (0x300U) +#define PXP_CTRL_SET_ROTATE0_SHIFT (8U) +#define PXP_CTRL_SET_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE0_SHIFT)) & PXP_CTRL_SET_ROTATE0_MASK) +#define PXP_CTRL_SET_HFLIP0_MASK (0x400U) +#define PXP_CTRL_SET_HFLIP0_SHIFT (10U) +#define PXP_CTRL_SET_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP0_SHIFT)) & PXP_CTRL_SET_HFLIP0_MASK) +#define PXP_CTRL_SET_VFLIP0_MASK (0x800U) +#define PXP_CTRL_SET_VFLIP0_SHIFT (11U) +#define PXP_CTRL_SET_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP0_SHIFT)) & PXP_CTRL_SET_VFLIP0_MASK) +#define PXP_CTRL_SET_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_SET_ROTATE1_SHIFT (12U) +#define PXP_CTRL_SET_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE1_SHIFT)) & PXP_CTRL_SET_ROTATE1_MASK) +#define PXP_CTRL_SET_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_SET_HFLIP1_SHIFT (14U) +#define PXP_CTRL_SET_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP1_SHIFT)) & PXP_CTRL_SET_HFLIP1_MASK) +#define PXP_CTRL_SET_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_SET_VFLIP1_SHIFT (15U) +#define PXP_CTRL_SET_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP1_SHIFT)) & PXP_CTRL_SET_VFLIP1_MASK) +#define PXP_CTRL_SET_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_SET_ENABLE_PS_AS_OUT_SHIFT (16U) +#define PXP_CTRL_SET_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_SET_ENABLE_PS_AS_OUT_MASK) +#define PXP_CTRL_SET_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL_SET_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL_SET_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_DITHER_SHIFT)) & PXP_CTRL_SET_ENABLE_DITHER_MASK) +#define PXP_CTRL_SET_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL_SET_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL_SET_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_SET_ENABLE_WFE_B_MASK) +#define PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK) +#define PXP_CTRL_SET_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_SET_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL_SET_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_CSC2_SHIFT)) & PXP_CTRL_SET_ENABLE_CSC2_MASK) +#define PXP_CTRL_SET_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL_SET_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL_SET_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LUT_SHIFT)) & PXP_CTRL_SET_ENABLE_LUT_MASK) +#define PXP_CTRL_SET_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_SET_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL_SET_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_SET_ENABLE_ROTATE0_MASK) +#define PXP_CTRL_SET_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_SET_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL_SET_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_SET_ENABLE_ROTATE1_MASK) +#define PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_SET_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK) +#define PXP_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_SET_CLKGATE_SHIFT (30U) +#define PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK) +#define PXP_CTRL_SET_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_SET_SFTRST_SHIFT (31U) +#define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK) + +/*! @name CTRL_CLR - Control Register 0 */ +#define PXP_CTRL_CLR_ENABLE_MASK (0x1U) +#define PXP_CTRL_CLR_ENABLE_SHIFT (0U) +#define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK) +#define PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_MASK (0x8U) +#define PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_SHIFT (3U) +#define PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_MASK) +#define PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_MASK) +#define PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +#define PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_MASK) +#define PXP_CTRL_CLR_ROTATE0_MASK (0x300U) +#define PXP_CTRL_CLR_ROTATE0_SHIFT (8U) +#define PXP_CTRL_CLR_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE0_SHIFT)) & PXP_CTRL_CLR_ROTATE0_MASK) +#define PXP_CTRL_CLR_HFLIP0_MASK (0x400U) +#define PXP_CTRL_CLR_HFLIP0_SHIFT (10U) +#define PXP_CTRL_CLR_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP0_SHIFT)) & PXP_CTRL_CLR_HFLIP0_MASK) +#define PXP_CTRL_CLR_VFLIP0_MASK (0x800U) +#define PXP_CTRL_CLR_VFLIP0_SHIFT (11U) +#define PXP_CTRL_CLR_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP0_SHIFT)) & PXP_CTRL_CLR_VFLIP0_MASK) +#define PXP_CTRL_CLR_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_CLR_ROTATE1_SHIFT (12U) +#define PXP_CTRL_CLR_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE1_SHIFT)) & PXP_CTRL_CLR_ROTATE1_MASK) +#define PXP_CTRL_CLR_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_CLR_HFLIP1_SHIFT (14U) +#define PXP_CTRL_CLR_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP1_SHIFT)) & PXP_CTRL_CLR_HFLIP1_MASK) +#define PXP_CTRL_CLR_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_CLR_VFLIP1_SHIFT (15U) +#define PXP_CTRL_CLR_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP1_SHIFT)) & PXP_CTRL_CLR_VFLIP1_MASK) +#define PXP_CTRL_CLR_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_CLR_ENABLE_PS_AS_OUT_SHIFT (16U) +#define PXP_CTRL_CLR_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_CLR_ENABLE_PS_AS_OUT_MASK) +#define PXP_CTRL_CLR_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL_CLR_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL_CLR_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_DITHER_SHIFT)) & PXP_CTRL_CLR_ENABLE_DITHER_MASK) +#define PXP_CTRL_CLR_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL_CLR_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL_CLR_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_CLR_ENABLE_WFE_B_MASK) +#define PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK) +#define PXP_CTRL_CLR_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_CLR_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL_CLR_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_CSC2_SHIFT)) & PXP_CTRL_CLR_ENABLE_CSC2_MASK) +#define PXP_CTRL_CLR_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL_CLR_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL_CLR_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LUT_SHIFT)) & PXP_CTRL_CLR_ENABLE_LUT_MASK) +#define PXP_CTRL_CLR_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_CLR_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL_CLR_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_CLR_ENABLE_ROTATE0_MASK) +#define PXP_CTRL_CLR_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_CLR_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL_CLR_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_CLR_ENABLE_ROTATE1_MASK) +#define PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK) +#define PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_CLR_CLKGATE_SHIFT (30U) +#define PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK) +#define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_CLR_SFTRST_SHIFT (31U) +#define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK) + +/*! @name CTRL_TOG - Control Register 0 */ +#define PXP_CTRL_TOG_ENABLE_MASK (0x1U) +#define PXP_CTRL_TOG_ENABLE_SHIFT (0U) +#define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK) +#define PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_MASK (0x8U) +#define PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_SHIFT (3U) +#define PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_MASK) +#define PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_MASK) +#define PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +#define PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_MASK) +#define PXP_CTRL_TOG_ROTATE0_MASK (0x300U) +#define PXP_CTRL_TOG_ROTATE0_SHIFT (8U) +#define PXP_CTRL_TOG_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE0_SHIFT)) & PXP_CTRL_TOG_ROTATE0_MASK) +#define PXP_CTRL_TOG_HFLIP0_MASK (0x400U) +#define PXP_CTRL_TOG_HFLIP0_SHIFT (10U) +#define PXP_CTRL_TOG_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP0_SHIFT)) & PXP_CTRL_TOG_HFLIP0_MASK) +#define PXP_CTRL_TOG_VFLIP0_MASK (0x800U) +#define PXP_CTRL_TOG_VFLIP0_SHIFT (11U) +#define PXP_CTRL_TOG_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP0_SHIFT)) & PXP_CTRL_TOG_VFLIP0_MASK) +#define PXP_CTRL_TOG_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_TOG_ROTATE1_SHIFT (12U) +#define PXP_CTRL_TOG_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE1_SHIFT)) & PXP_CTRL_TOG_ROTATE1_MASK) +#define PXP_CTRL_TOG_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_TOG_HFLIP1_SHIFT (14U) +#define PXP_CTRL_TOG_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP1_SHIFT)) & PXP_CTRL_TOG_HFLIP1_MASK) +#define PXP_CTRL_TOG_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_TOG_VFLIP1_SHIFT (15U) +#define PXP_CTRL_TOG_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP1_SHIFT)) & PXP_CTRL_TOG_VFLIP1_MASK) +#define PXP_CTRL_TOG_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_TOG_ENABLE_PS_AS_OUT_SHIFT (16U) +#define PXP_CTRL_TOG_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_TOG_ENABLE_PS_AS_OUT_MASK) +#define PXP_CTRL_TOG_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL_TOG_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL_TOG_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_DITHER_SHIFT)) & PXP_CTRL_TOG_ENABLE_DITHER_MASK) +#define PXP_CTRL_TOG_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL_TOG_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL_TOG_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_TOG_ENABLE_WFE_B_MASK) +#define PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK) +#define PXP_CTRL_TOG_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_TOG_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL_TOG_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_CSC2_SHIFT)) & PXP_CTRL_TOG_ENABLE_CSC2_MASK) +#define PXP_CTRL_TOG_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL_TOG_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL_TOG_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LUT_SHIFT)) & PXP_CTRL_TOG_ENABLE_LUT_MASK) +#define PXP_CTRL_TOG_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_TOG_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL_TOG_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_TOG_ENABLE_ROTATE0_MASK) +#define PXP_CTRL_TOG_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_TOG_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL_TOG_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_TOG_ENABLE_ROTATE1_MASK) +#define PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK) +#define PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_TOG_CLKGATE_SHIFT (30U) +#define PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK) +#define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_TOG_SFTRST_SHIFT (31U) +#define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK) + +/*! @name STAT - Status Register */ +#define PXP_STAT_IRQ0_MASK (0x1U) +#define PXP_STAT_IRQ0_SHIFT (0U) +#define PXP_STAT_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ0_SHIFT)) & PXP_STAT_IRQ0_MASK) +#define PXP_STAT_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_AXI_WRITE_ERROR_0_SHIFT (1U) +#define PXP_STAT_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_0_MASK) +#define PXP_STAT_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_AXI_READ_ERROR_0_SHIFT (2U) +#define PXP_STAT_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_AXI_READ_ERROR_0_MASK) +#define PXP_STAT_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK) +#define PXP_STAT_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_AXI_ERROR_ID_0_SHIFT (4U) +#define PXP_STAT_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_AXI_ERROR_ID_0_MASK) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_AXI_WRITE_ERROR_1_SHIFT (9U) +#define PXP_STAT_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_1_MASK) +#define PXP_STAT_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_AXI_READ_ERROR_1_SHIFT (10U) +#define PXP_STAT_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_AXI_READ_ERROR_1_MASK) +#define PXP_STAT_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_AXI_ERROR_ID_1_SHIFT (12U) +#define PXP_STAT_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_AXI_ERROR_ID_1_MASK) +#define PXP_STAT_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_BLOCKY_SHIFT (16U) +#define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK) +#define PXP_STAT_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_BLOCKX_SHIFT (24U) +#define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK) + +/*! @name STAT_SET - Status Register */ +#define PXP_STAT_SET_IRQ0_MASK (0x1U) +#define PXP_STAT_SET_IRQ0_SHIFT (0U) +#define PXP_STAT_SET_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ0_SHIFT)) & PXP_STAT_SET_IRQ0_MASK) +#define PXP_STAT_SET_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_0_SHIFT (1U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_0_MASK) +#define PXP_STAT_SET_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_SET_AXI_READ_ERROR_0_SHIFT (2U) +#define PXP_STAT_SET_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_0_MASK) +#define PXP_STAT_SET_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_SET_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK) +#define PXP_STAT_SET_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_SET_AXI_ERROR_ID_0_SHIFT (4U) +#define PXP_STAT_SET_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_0_MASK) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_SET_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_1_SHIFT (9U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_1_MASK) +#define PXP_STAT_SET_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_SET_AXI_READ_ERROR_1_SHIFT (10U) +#define PXP_STAT_SET_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_1_MASK) +#define PXP_STAT_SET_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_SET_AXI_ERROR_ID_1_SHIFT (12U) +#define PXP_STAT_SET_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_1_MASK) +#define PXP_STAT_SET_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_SET_BLOCKY_SHIFT (16U) +#define PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK) +#define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_SET_BLOCKX_SHIFT (24U) +#define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK) + +/*! @name STAT_CLR - Status Register */ +#define PXP_STAT_CLR_IRQ0_MASK (0x1U) +#define PXP_STAT_CLR_IRQ0_SHIFT (0U) +#define PXP_STAT_CLR_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ0_SHIFT)) & PXP_STAT_CLR_IRQ0_MASK) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_0_SHIFT (1U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_0_MASK) +#define PXP_STAT_CLR_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_CLR_AXI_READ_ERROR_0_SHIFT (2U) +#define PXP_STAT_CLR_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_0_MASK) +#define PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK) +#define PXP_STAT_CLR_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_CLR_AXI_ERROR_ID_0_SHIFT (4U) +#define PXP_STAT_CLR_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_0_MASK) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_1_SHIFT (9U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_1_MASK) +#define PXP_STAT_CLR_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_CLR_AXI_READ_ERROR_1_SHIFT (10U) +#define PXP_STAT_CLR_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_1_MASK) +#define PXP_STAT_CLR_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_CLR_AXI_ERROR_ID_1_SHIFT (12U) +#define PXP_STAT_CLR_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_1_MASK) +#define PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_CLR_BLOCKY_SHIFT (16U) +#define PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK) +#define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_CLR_BLOCKX_SHIFT (24U) +#define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK) + +/*! @name STAT_TOG - Status Register */ +#define PXP_STAT_TOG_IRQ0_MASK (0x1U) +#define PXP_STAT_TOG_IRQ0_SHIFT (0U) +#define PXP_STAT_TOG_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ0_SHIFT)) & PXP_STAT_TOG_IRQ0_MASK) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_0_SHIFT (1U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_0_MASK) +#define PXP_STAT_TOG_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_TOG_AXI_READ_ERROR_0_SHIFT (2U) +#define PXP_STAT_TOG_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_0_MASK) +#define PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK) +#define PXP_STAT_TOG_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_TOG_AXI_ERROR_ID_0_SHIFT (4U) +#define PXP_STAT_TOG_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_0_MASK) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_1_SHIFT (9U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_1_MASK) +#define PXP_STAT_TOG_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_TOG_AXI_READ_ERROR_1_SHIFT (10U) +#define PXP_STAT_TOG_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_1_MASK) +#define PXP_STAT_TOG_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_TOG_AXI_ERROR_ID_1_SHIFT (12U) +#define PXP_STAT_TOG_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_1_MASK) +#define PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_TOG_BLOCKY_SHIFT (16U) +#define PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK) +#define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_TOG_BLOCKX_SHIFT (24U) +#define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK) + +/*! @name OUT_CTRL - Output Buffer Control Register */ +#define PXP_OUT_CTRL_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK) + +/*! @name OUT_CTRL_SET - Output Buffer Control Register */ +#define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK) + +/*! @name OUT_CTRL_CLR - Output Buffer Control Register */ +#define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK) + +/*! @name OUT_CTRL_TOG - Output Buffer Control Register */ +#define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK) + +/*! @name OUT_BUF - Output Frame Buffer Pointer */ +#define PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_OUT_BUF_ADDR_SHIFT (0U) +#define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK) + +/*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */ +#define PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU) +#define PXP_OUT_BUF2_ADDR_SHIFT (0U) +#define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK) + +/*! @name OUT_PITCH - Output Buffer Pitch */ +#define PXP_OUT_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_OUT_PITCH_PITCH_SHIFT (0U) +#define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK) + +/*! @name OUT_LRC - Output Surface Lower Right Coordinate */ +#define PXP_OUT_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_LRC_Y_SHIFT (0U) +#define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK) +#define PXP_OUT_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_LRC_X_SHIFT (16U) +#define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK) + +/*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */ +#define PXP_OUT_PS_ULC_Y_MASK (0x3FFFU) +#define PXP_OUT_PS_ULC_Y_SHIFT (0U) +#define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK) +#define PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U) +#define PXP_OUT_PS_ULC_X_SHIFT (16U) +#define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK) + +/*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */ +#define PXP_OUT_PS_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_PS_LRC_Y_SHIFT (0U) +#define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK) +#define PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_PS_LRC_X_SHIFT (16U) +#define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK) + +/*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */ +#define PXP_OUT_AS_ULC_Y_MASK (0x3FFFU) +#define PXP_OUT_AS_ULC_Y_SHIFT (0U) +#define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK) +#define PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U) +#define PXP_OUT_AS_ULC_X_SHIFT (16U) +#define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK) + +/*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */ +#define PXP_OUT_AS_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_AS_LRC_Y_SHIFT (0U) +#define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK) +#define PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_AS_LRC_X_SHIFT (16U) +#define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK) + +/*! @name PS_CTRL - Processed Surface (PS) Control Register */ +#define PXP_PS_CTRL_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK) +#define PXP_PS_CTRL_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_WB_SWAP_SHIFT (6U) +#define PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK) +#define PXP_PS_CTRL_DECY_MASK (0x300U) +#define PXP_PS_CTRL_DECY_SHIFT (8U) +#define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK) +#define PXP_PS_CTRL_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_DECX_SHIFT (10U) +#define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK) + +/*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */ +#define PXP_PS_CTRL_SET_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK) +#define PXP_PS_CTRL_SET_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_SET_WB_SWAP_SHIFT (6U) +#define PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK) +#define PXP_PS_CTRL_SET_DECY_MASK (0x300U) +#define PXP_PS_CTRL_SET_DECY_SHIFT (8U) +#define PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK) +#define PXP_PS_CTRL_SET_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_SET_DECX_SHIFT (10U) +#define PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK) + +/*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */ +#define PXP_PS_CTRL_CLR_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK) +#define PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (6U) +#define PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK) +#define PXP_PS_CTRL_CLR_DECY_MASK (0x300U) +#define PXP_PS_CTRL_CLR_DECY_SHIFT (8U) +#define PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK) +#define PXP_PS_CTRL_CLR_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_CLR_DECX_SHIFT (10U) +#define PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK) + +/*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */ +#define PXP_PS_CTRL_TOG_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK) +#define PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (6U) +#define PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK) +#define PXP_PS_CTRL_TOG_DECY_MASK (0x300U) +#define PXP_PS_CTRL_TOG_DECY_SHIFT (8U) +#define PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK) +#define PXP_PS_CTRL_TOG_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_TOG_DECX_SHIFT (10U) +#define PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK) + +/*! @name PS_BUF - PS Input Buffer Address */ +#define PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_BUF_ADDR_SHIFT (0U) +#define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK) + +/*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */ +#define PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_UBUF_ADDR_SHIFT (0U) +#define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK) + +/*! @name PS_VBUF - PS V/Cr Input Buffer Address */ +#define PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_VBUF_ADDR_SHIFT (0U) +#define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK) + +/*! @name PS_PITCH - Processed Surface Pitch */ +#define PXP_PS_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_PS_PITCH_PITCH_SHIFT (0U) +#define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK) + +/*! @name PS_BACKGROUND_0 - PS Background Color */ +#define PXP_PS_BACKGROUND_0_COLOR_MASK (0xFFFFFFU) +#define PXP_PS_BACKGROUND_0_COLOR_SHIFT (0U) +#define PXP_PS_BACKGROUND_0_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_0_COLOR_SHIFT)) & PXP_PS_BACKGROUND_0_COLOR_MASK) + +/*! @name PS_SCALE - PS Scale Factor Register */ +#define PXP_PS_SCALE_XSCALE_MASK (0x7FFFU) +#define PXP_PS_SCALE_XSCALE_SHIFT (0U) +#define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK) +#define PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U) +#define PXP_PS_SCALE_YSCALE_SHIFT (16U) +#define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK) + +/*! @name PS_OFFSET - PS Scale Offset Register */ +#define PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU) +#define PXP_PS_OFFSET_XOFFSET_SHIFT (0U) +#define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK) +#define PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U) +#define PXP_PS_OFFSET_YOFFSET_SHIFT (16U) +#define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK) + +/*! @name PS_CLRKEYLOW_0 - PS Color Key Low */ +#define PXP_PS_CLRKEYLOW_0_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYLOW_0_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYLOW_0_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_0_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_0_PIXEL_MASK) + +/*! @name PS_CLRKEYHIGH_0 - PS Color Key High */ +#define PXP_PS_CLRKEYHIGH_0_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYHIGH_0_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYHIGH_0_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_0_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_0_PIXEL_MASK) + +/*! @name AS_CTRL - Alpha Surface Control */ +#define PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U) +#define PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U) +#define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK) +#define PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) +#define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) +#define PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK) +#define PXP_AS_CTRL_FORMAT_MASK (0xF0U) +#define PXP_AS_CTRL_FORMAT_SHIFT (4U) +#define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK) +#define PXP_AS_CTRL_ALPHA_MASK (0xFF00U) +#define PXP_AS_CTRL_ALPHA_SHIFT (8U) +#define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK) +#define PXP_AS_CTRL_ROP_MASK (0xF0000U) +#define PXP_AS_CTRL_ROP_SHIFT (16U) +#define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK) +#define PXP_AS_CTRL_ALPHA0_INVERT_MASK (0x100000U) +#define PXP_AS_CTRL_ALPHA0_INVERT_SHIFT (20U) +#define PXP_AS_CTRL_ALPHA0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA0_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA0_INVERT_MASK) +#define PXP_AS_CTRL_ALPHA1_INVERT_MASK (0x200000U) +#define PXP_AS_CTRL_ALPHA1_INVERT_SHIFT (21U) +#define PXP_AS_CTRL_ALPHA1_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA1_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA1_INVERT_MASK) + +/*! @name AS_BUF - Alpha Surface Buffer Pointer */ +#define PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_AS_BUF_ADDR_SHIFT (0U) +#define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK) + +/*! @name AS_PITCH - Alpha Surface Pitch */ +#define PXP_AS_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_AS_PITCH_PITCH_SHIFT (0U) +#define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK) + +/*! @name AS_CLRKEYLOW_0 - Overlay Color Key Low */ +#define PXP_AS_CLRKEYLOW_0_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYLOW_0_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYLOW_0_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_0_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_0_PIXEL_MASK) + +/*! @name AS_CLRKEYHIGH_0 - Overlay Color Key High */ +#define PXP_AS_CLRKEYHIGH_0_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYHIGH_0_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYHIGH_0_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_0_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_0_PIXEL_MASK) + +/*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */ +#define PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU) +#define PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U) +#define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK) +#define PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U) +#define PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U) +#define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK) +#define PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U) +#define PXP_CSC1_COEF0_C0_SHIFT (18U) +#define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK) +#define PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U) +#define PXP_CSC1_COEF0_BYPASS_SHIFT (30U) +#define PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK) +#define PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U) +#define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U) +#define PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK) + +/*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */ +#define PXP_CSC1_COEF1_C4_MASK (0x7FFU) +#define PXP_CSC1_COEF1_C4_SHIFT (0U) +#define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK) +#define PXP_CSC1_COEF1_C1_MASK (0x7FF0000U) +#define PXP_CSC1_COEF1_C1_SHIFT (16U) +#define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK) + +/*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */ +#define PXP_CSC1_COEF2_C3_MASK (0x7FFU) +#define PXP_CSC1_COEF2_C3_SHIFT (0U) +#define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK) +#define PXP_CSC1_COEF2_C2_MASK (0x7FF0000U) +#define PXP_CSC1_COEF2_C2_SHIFT (16U) +#define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK) + +/*! @name CSC2_CTRL - Color Space Conversion Control Register. */ +#define PXP_CSC2_CTRL_BYPASS_MASK (0x1U) +#define PXP_CSC2_CTRL_BYPASS_SHIFT (0U) +#define PXP_CSC2_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_CTRL_BYPASS_SHIFT)) & PXP_CSC2_CTRL_BYPASS_MASK) +#define PXP_CSC2_CTRL_CSC_MODE_MASK (0x6U) +#define PXP_CSC2_CTRL_CSC_MODE_SHIFT (1U) +#define PXP_CSC2_CTRL_CSC_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_CTRL_CSC_MODE_SHIFT)) & PXP_CSC2_CTRL_CSC_MODE_MASK) + +/*! @name CSC2_COEF0 - Color Space Conversion Coefficient Register 0 */ +#define PXP_CSC2_COEF0_A1_MASK (0x7FFU) +#define PXP_CSC2_COEF0_A1_SHIFT (0U) +#define PXP_CSC2_COEF0_A1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF0_A1_SHIFT)) & PXP_CSC2_COEF0_A1_MASK) +#define PXP_CSC2_COEF0_A2_MASK (0x7FF0000U) +#define PXP_CSC2_COEF0_A2_SHIFT (16U) +#define PXP_CSC2_COEF0_A2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF0_A2_SHIFT)) & PXP_CSC2_COEF0_A2_MASK) + +/*! @name CSC2_COEF1 - Color Space Conversion Coefficient Register 1 */ +#define PXP_CSC2_COEF1_A3_MASK (0x7FFU) +#define PXP_CSC2_COEF1_A3_SHIFT (0U) +#define PXP_CSC2_COEF1_A3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF1_A3_SHIFT)) & PXP_CSC2_COEF1_A3_MASK) +#define PXP_CSC2_COEF1_B1_MASK (0x7FF0000U) +#define PXP_CSC2_COEF1_B1_SHIFT (16U) +#define PXP_CSC2_COEF1_B1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF1_B1_SHIFT)) & PXP_CSC2_COEF1_B1_MASK) + +/*! @name CSC2_COEF2 - Color Space Conversion Coefficient Register 2 */ +#define PXP_CSC2_COEF2_B2_MASK (0x7FFU) +#define PXP_CSC2_COEF2_B2_SHIFT (0U) +#define PXP_CSC2_COEF2_B2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF2_B2_SHIFT)) & PXP_CSC2_COEF2_B2_MASK) +#define PXP_CSC2_COEF2_B3_MASK (0x7FF0000U) +#define PXP_CSC2_COEF2_B3_SHIFT (16U) +#define PXP_CSC2_COEF2_B3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF2_B3_SHIFT)) & PXP_CSC2_COEF2_B3_MASK) + +/*! @name CSC2_COEF3 - Color Space Conversion Coefficient Register 3 */ +#define PXP_CSC2_COEF3_C1_MASK (0x7FFU) +#define PXP_CSC2_COEF3_C1_SHIFT (0U) +#define PXP_CSC2_COEF3_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF3_C1_SHIFT)) & PXP_CSC2_COEF3_C1_MASK) +#define PXP_CSC2_COEF3_C2_MASK (0x7FF0000U) +#define PXP_CSC2_COEF3_C2_SHIFT (16U) +#define PXP_CSC2_COEF3_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF3_C2_SHIFT)) & PXP_CSC2_COEF3_C2_MASK) + +/*! @name CSC2_COEF4 - Color Space Conversion Coefficient Register 4 */ +#define PXP_CSC2_COEF4_C3_MASK (0x7FFU) +#define PXP_CSC2_COEF4_C3_SHIFT (0U) +#define PXP_CSC2_COEF4_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF4_C3_SHIFT)) & PXP_CSC2_COEF4_C3_MASK) +#define PXP_CSC2_COEF4_D1_MASK (0x1FF0000U) +#define PXP_CSC2_COEF4_D1_SHIFT (16U) +#define PXP_CSC2_COEF4_D1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF4_D1_SHIFT)) & PXP_CSC2_COEF4_D1_MASK) + +/*! @name CSC2_COEF5 - Color Space Conversion Coefficient Register 5 */ +#define PXP_CSC2_COEF5_D2_MASK (0x1FFU) +#define PXP_CSC2_COEF5_D2_SHIFT (0U) +#define PXP_CSC2_COEF5_D2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF5_D2_SHIFT)) & PXP_CSC2_COEF5_D2_MASK) +#define PXP_CSC2_COEF5_D3_MASK (0x1FF0000U) +#define PXP_CSC2_COEF5_D3_SHIFT (16U) +#define PXP_CSC2_COEF5_D3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF5_D3_SHIFT)) & PXP_CSC2_COEF5_D3_MASK) + +/*! @name LUT_CTRL - Lookup Table Control Register. */ +#define PXP_LUT_CTRL_DMA_START_MASK (0x1U) +#define PXP_LUT_CTRL_DMA_START_SHIFT (0U) +#define PXP_LUT_CTRL_DMA_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_DMA_START_SHIFT)) & PXP_LUT_CTRL_DMA_START_MASK) +#define PXP_LUT_CTRL_INVALID_MASK (0x100U) +#define PXP_LUT_CTRL_INVALID_SHIFT (8U) +#define PXP_LUT_CTRL_INVALID(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_INVALID_SHIFT)) & PXP_LUT_CTRL_INVALID_MASK) +#define PXP_LUT_CTRL_LRU_UPD_MASK (0x200U) +#define PXP_LUT_CTRL_LRU_UPD_SHIFT (9U) +#define PXP_LUT_CTRL_LRU_UPD(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_LRU_UPD_SHIFT)) & PXP_LUT_CTRL_LRU_UPD_MASK) +#define PXP_LUT_CTRL_SEL_8KB_MASK (0x400U) +#define PXP_LUT_CTRL_SEL_8KB_SHIFT (10U) +#define PXP_LUT_CTRL_SEL_8KB(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_SEL_8KB_SHIFT)) & PXP_LUT_CTRL_SEL_8KB_MASK) +#define PXP_LUT_CTRL_OUT_MODE_MASK (0x30000U) +#define PXP_LUT_CTRL_OUT_MODE_SHIFT (16U) +#define PXP_LUT_CTRL_OUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_OUT_MODE_SHIFT)) & PXP_LUT_CTRL_OUT_MODE_MASK) +#define PXP_LUT_CTRL_LOOKUP_MODE_MASK (0x3000000U) +#define PXP_LUT_CTRL_LOOKUP_MODE_SHIFT (24U) +#define PXP_LUT_CTRL_LOOKUP_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_LOOKUP_MODE_SHIFT)) & PXP_LUT_CTRL_LOOKUP_MODE_MASK) +#define PXP_LUT_CTRL_BYPASS_MASK (0x80000000U) +#define PXP_LUT_CTRL_BYPASS_SHIFT (31U) +#define PXP_LUT_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_BYPASS_SHIFT)) & PXP_LUT_CTRL_BYPASS_MASK) + +/*! @name LUT_ADDR - Lookup Table Control Register. */ +#define PXP_LUT_ADDR_ADDR_MASK (0x3FFFU) +#define PXP_LUT_ADDR_ADDR_SHIFT (0U) +#define PXP_LUT_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_ADDR_ADDR_SHIFT)) & PXP_LUT_ADDR_ADDR_MASK) +#define PXP_LUT_ADDR_NUM_BYTES_MASK (0x7FFF0000U) +#define PXP_LUT_ADDR_NUM_BYTES_SHIFT (16U) +#define PXP_LUT_ADDR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_ADDR_NUM_BYTES_SHIFT)) & PXP_LUT_ADDR_NUM_BYTES_MASK) + +/*! @name LUT_DATA - Lookup Table Data Register. */ +#define PXP_LUT_DATA_DATA_MASK (0xFFFFFFFFU) +#define PXP_LUT_DATA_DATA_SHIFT (0U) +#define PXP_LUT_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_DATA_DATA_SHIFT)) & PXP_LUT_DATA_DATA_MASK) + +/*! @name LUT_EXTMEM - Lookup Table External Memory Address Register. */ +#define PXP_LUT_EXTMEM_ADDR_MASK (0xFFFFFFFFU) +#define PXP_LUT_EXTMEM_ADDR_SHIFT (0U) +#define PXP_LUT_EXTMEM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_EXTMEM_ADDR_SHIFT)) & PXP_LUT_EXTMEM_ADDR_MASK) + +/*! @name CFA - Color Filter Array Register. */ +#define PXP_CFA_DATA_MASK (0xFFFFFFFFU) +#define PXP_CFA_DATA_SHIFT (0U) +#define PXP_CFA_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_CFA_DATA_SHIFT)) & PXP_CFA_DATA_MASK) + +/*! @name ALPHA_A_CTRL - PXP Alpha Engine A Control Register. */ +#define PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_MASK (0x1U) +#define PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_SHIFT (0U) +#define PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_SHIFT)) & PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_MASK) +#define PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U) +#define PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U) +#define PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_MASK (0x20U) +#define PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_SHIFT (5U) +#define PXP_ALPHA_A_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S0_COLOR_MODE_MASK (0x40U) +#define PXP_ALPHA_A_CTRL_S0_COLOR_MODE_SHIFT (6U) +#define PXP_ALPHA_A_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_COLOR_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U) +#define PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U) +#define PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_MASK (0x1000U) +#define PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_SHIFT (12U) +#define PXP_ALPHA_A_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S1_COLOR_MODE_MASK (0x2000U) +#define PXP_ALPHA_A_CTRL_S1_COLOR_MODE_SHIFT (13U) +#define PXP_ALPHA_A_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_COLOR_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MASK) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MASK) + +/*! @name PS_BACKGROUND_1 - PS Background Color 1 */ +#define PXP_PS_BACKGROUND_1_COLOR_MASK (0xFFFFFFU) +#define PXP_PS_BACKGROUND_1_COLOR_SHIFT (0U) +#define PXP_PS_BACKGROUND_1_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_1_COLOR_SHIFT)) & PXP_PS_BACKGROUND_1_COLOR_MASK) + +/*! @name PS_CLRKEYLOW_1 - PS Color Key Low 1 */ +#define PXP_PS_CLRKEYLOW_1_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYLOW_1_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYLOW_1_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_1_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_1_PIXEL_MASK) + +/*! @name PS_CLRKEYHIGH_1 - PS Color Key High 1 */ +#define PXP_PS_CLRKEYHIGH_1_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYHIGH_1_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYHIGH_1_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_1_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_1_PIXEL_MASK) + +/*! @name AS_CLRKEYLOW_1 - Overlay Color Key Low */ +#define PXP_AS_CLRKEYLOW_1_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYLOW_1_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYLOW_1_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_1_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_1_PIXEL_MASK) + +/*! @name AS_CLRKEYHIGH_1 - Overlay Color Key High */ +#define PXP_AS_CLRKEYHIGH_1_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYHIGH_1_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYHIGH_1_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_1_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_1_PIXEL_MASK) + +/*! @name CTRL2 - Control Register 2 */ +#define PXP_CTRL2_ENABLE_MASK (0x1U) +#define PXP_CTRL2_ENABLE_SHIFT (0U) +#define PXP_CTRL2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_SHIFT)) & PXP_CTRL2_ENABLE_MASK) +#define PXP_CTRL2_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_ROTATE0_SHIFT (8U) +#define PXP_CTRL2_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ROTATE0_SHIFT)) & PXP_CTRL2_ROTATE0_MASK) +#define PXP_CTRL2_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_HFLIP0_SHIFT (10U) +#define PXP_CTRL2_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_HFLIP0_SHIFT)) & PXP_CTRL2_HFLIP0_MASK) +#define PXP_CTRL2_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_VFLIP0_SHIFT (11U) +#define PXP_CTRL2_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_VFLIP0_SHIFT)) & PXP_CTRL2_VFLIP0_MASK) +#define PXP_CTRL2_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_ROTATE1_SHIFT (12U) +#define PXP_CTRL2_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ROTATE1_SHIFT)) & PXP_CTRL2_ROTATE1_MASK) +#define PXP_CTRL2_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_HFLIP1_SHIFT (14U) +#define PXP_CTRL2_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_HFLIP1_SHIFT)) & PXP_CTRL2_HFLIP1_MASK) +#define PXP_CTRL2_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_VFLIP1_SHIFT (15U) +#define PXP_CTRL2_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_VFLIP1_SHIFT)) & PXP_CTRL2_VFLIP1_MASK) +#define PXP_CTRL2_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL2_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL2_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_ENABLE_DITHER_MASK) +#define PXP_CTRL2_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL2_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL2_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_ENABLE_WFE_B_MASK) +#define PXP_CTRL2_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL2_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_BLOCK_SIZE_MASK) +#define PXP_CTRL2_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL2_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_ENABLE_CSC2_MASK) +#define PXP_CTRL2_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL2_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL2_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_LUT_SHIFT)) & PXP_CTRL2_ENABLE_LUT_MASK) +#define PXP_CTRL2_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL2_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_ENABLE_ROTATE0_MASK) +#define PXP_CTRL2_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL2_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_ENABLE_ROTATE1_MASK) + +/*! @name CTRL2_SET - Control Register 2 */ +#define PXP_CTRL2_SET_ENABLE_MASK (0x1U) +#define PXP_CTRL2_SET_ENABLE_SHIFT (0U) +#define PXP_CTRL2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_SHIFT)) & PXP_CTRL2_SET_ENABLE_MASK) +#define PXP_CTRL2_SET_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_SET_ROTATE0_SHIFT (8U) +#define PXP_CTRL2_SET_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ROTATE0_SHIFT)) & PXP_CTRL2_SET_ROTATE0_MASK) +#define PXP_CTRL2_SET_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_SET_HFLIP0_SHIFT (10U) +#define PXP_CTRL2_SET_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_HFLIP0_SHIFT)) & PXP_CTRL2_SET_HFLIP0_MASK) +#define PXP_CTRL2_SET_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_SET_VFLIP0_SHIFT (11U) +#define PXP_CTRL2_SET_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_VFLIP0_SHIFT)) & PXP_CTRL2_SET_VFLIP0_MASK) +#define PXP_CTRL2_SET_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_SET_ROTATE1_SHIFT (12U) +#define PXP_CTRL2_SET_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ROTATE1_SHIFT)) & PXP_CTRL2_SET_ROTATE1_MASK) +#define PXP_CTRL2_SET_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_SET_HFLIP1_SHIFT (14U) +#define PXP_CTRL2_SET_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_HFLIP1_SHIFT)) & PXP_CTRL2_SET_HFLIP1_MASK) +#define PXP_CTRL2_SET_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_SET_VFLIP1_SHIFT (15U) +#define PXP_CTRL2_SET_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_VFLIP1_SHIFT)) & PXP_CTRL2_SET_VFLIP1_MASK) +#define PXP_CTRL2_SET_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL2_SET_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL2_SET_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_SET_ENABLE_DITHER_MASK) +#define PXP_CTRL2_SET_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL2_SET_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL2_SET_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_SET_ENABLE_WFE_B_MASK) +#define PXP_CTRL2_SET_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_SET_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL2_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_SET_BLOCK_SIZE_MASK) +#define PXP_CTRL2_SET_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_SET_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL2_SET_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_SET_ENABLE_CSC2_MASK) +#define PXP_CTRL2_SET_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL2_SET_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL2_SET_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_LUT_SHIFT)) & PXP_CTRL2_SET_ENABLE_LUT_MASK) +#define PXP_CTRL2_SET_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_SET_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL2_SET_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_SET_ENABLE_ROTATE0_MASK) +#define PXP_CTRL2_SET_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_SET_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL2_SET_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_SET_ENABLE_ROTATE1_MASK) + +/*! @name CTRL2_CLR - Control Register 2 */ +#define PXP_CTRL2_CLR_ENABLE_MASK (0x1U) +#define PXP_CTRL2_CLR_ENABLE_SHIFT (0U) +#define PXP_CTRL2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_SHIFT)) & PXP_CTRL2_CLR_ENABLE_MASK) +#define PXP_CTRL2_CLR_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_CLR_ROTATE0_SHIFT (8U) +#define PXP_CTRL2_CLR_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ROTATE0_SHIFT)) & PXP_CTRL2_CLR_ROTATE0_MASK) +#define PXP_CTRL2_CLR_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_CLR_HFLIP0_SHIFT (10U) +#define PXP_CTRL2_CLR_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_HFLIP0_SHIFT)) & PXP_CTRL2_CLR_HFLIP0_MASK) +#define PXP_CTRL2_CLR_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_CLR_VFLIP0_SHIFT (11U) +#define PXP_CTRL2_CLR_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_VFLIP0_SHIFT)) & PXP_CTRL2_CLR_VFLIP0_MASK) +#define PXP_CTRL2_CLR_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_CLR_ROTATE1_SHIFT (12U) +#define PXP_CTRL2_CLR_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ROTATE1_SHIFT)) & PXP_CTRL2_CLR_ROTATE1_MASK) +#define PXP_CTRL2_CLR_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_CLR_HFLIP1_SHIFT (14U) +#define PXP_CTRL2_CLR_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_HFLIP1_SHIFT)) & PXP_CTRL2_CLR_HFLIP1_MASK) +#define PXP_CTRL2_CLR_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_CLR_VFLIP1_SHIFT (15U) +#define PXP_CTRL2_CLR_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_VFLIP1_SHIFT)) & PXP_CTRL2_CLR_VFLIP1_MASK) +#define PXP_CTRL2_CLR_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL2_CLR_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL2_CLR_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_CLR_ENABLE_DITHER_MASK) +#define PXP_CTRL2_CLR_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL2_CLR_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL2_CLR_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_CLR_ENABLE_WFE_B_MASK) +#define PXP_CTRL2_CLR_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_CLR_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL2_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_CLR_BLOCK_SIZE_MASK) +#define PXP_CTRL2_CLR_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_CLR_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL2_CLR_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_CLR_ENABLE_CSC2_MASK) +#define PXP_CTRL2_CLR_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL2_CLR_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL2_CLR_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_LUT_SHIFT)) & PXP_CTRL2_CLR_ENABLE_LUT_MASK) +#define PXP_CTRL2_CLR_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_CLR_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL2_CLR_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_CLR_ENABLE_ROTATE0_MASK) +#define PXP_CTRL2_CLR_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_CLR_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL2_CLR_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_CLR_ENABLE_ROTATE1_MASK) + +/*! @name CTRL2_TOG - Control Register 2 */ +#define PXP_CTRL2_TOG_ENABLE_MASK (0x1U) +#define PXP_CTRL2_TOG_ENABLE_SHIFT (0U) +#define PXP_CTRL2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_SHIFT)) & PXP_CTRL2_TOG_ENABLE_MASK) +#define PXP_CTRL2_TOG_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_TOG_ROTATE0_SHIFT (8U) +#define PXP_CTRL2_TOG_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ROTATE0_SHIFT)) & PXP_CTRL2_TOG_ROTATE0_MASK) +#define PXP_CTRL2_TOG_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_TOG_HFLIP0_SHIFT (10U) +#define PXP_CTRL2_TOG_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_HFLIP0_SHIFT)) & PXP_CTRL2_TOG_HFLIP0_MASK) +#define PXP_CTRL2_TOG_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_TOG_VFLIP0_SHIFT (11U) +#define PXP_CTRL2_TOG_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_VFLIP0_SHIFT)) & PXP_CTRL2_TOG_VFLIP0_MASK) +#define PXP_CTRL2_TOG_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_TOG_ROTATE1_SHIFT (12U) +#define PXP_CTRL2_TOG_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ROTATE1_SHIFT)) & PXP_CTRL2_TOG_ROTATE1_MASK) +#define PXP_CTRL2_TOG_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_TOG_HFLIP1_SHIFT (14U) +#define PXP_CTRL2_TOG_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_HFLIP1_SHIFT)) & PXP_CTRL2_TOG_HFLIP1_MASK) +#define PXP_CTRL2_TOG_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_TOG_VFLIP1_SHIFT (15U) +#define PXP_CTRL2_TOG_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_VFLIP1_SHIFT)) & PXP_CTRL2_TOG_VFLIP1_MASK) +#define PXP_CTRL2_TOG_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL2_TOG_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL2_TOG_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_TOG_ENABLE_DITHER_MASK) +#define PXP_CTRL2_TOG_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL2_TOG_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL2_TOG_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_TOG_ENABLE_WFE_B_MASK) +#define PXP_CTRL2_TOG_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_TOG_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL2_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_TOG_BLOCK_SIZE_MASK) +#define PXP_CTRL2_TOG_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_TOG_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL2_TOG_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_TOG_ENABLE_CSC2_MASK) +#define PXP_CTRL2_TOG_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL2_TOG_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL2_TOG_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_LUT_SHIFT)) & PXP_CTRL2_TOG_ENABLE_LUT_MASK) +#define PXP_CTRL2_TOG_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_TOG_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL2_TOG_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_TOG_ENABLE_ROTATE0_MASK) +#define PXP_CTRL2_TOG_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_TOG_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL2_TOG_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_TOG_ENABLE_ROTATE1_MASK) + +/*! @name POWER_REG0 - PXP Power Control Register. */ +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_MASK (0x7U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_SHIFT (0U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_SHIFT)) & PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_MASK) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_MASK (0x38U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_SHIFT (3U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_SHIFT)) & PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_MASK) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_MASK (0x1C0U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_SHIFT (6U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_SHIFT)) & PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_MASK) +#define PXP_POWER_REG0_ROT0_MEM_LP_STATE_MASK (0xE00U) +#define PXP_POWER_REG0_ROT0_MEM_LP_STATE_SHIFT (9U) +#define PXP_POWER_REG0_ROT0_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_ROT0_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG0_ROT0_MEM_LP_STATE_MASK) +#define PXP_POWER_REG0_CTRL_MASK (0xFFFFF000U) +#define PXP_POWER_REG0_CTRL_SHIFT (12U) +#define PXP_POWER_REG0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_CTRL_SHIFT)) & PXP_POWER_REG0_CTRL_MASK) + +/*! @name POWER_REG1 - PXP Power Control Register 1. */ +#define PXP_POWER_REG1_ROT1_MEM_LP_STATE_MASK (0x7U) +#define PXP_POWER_REG1_ROT1_MEM_LP_STATE_SHIFT (0U) +#define PXP_POWER_REG1_ROT1_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_ROT1_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_ROT1_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_MASK (0x38U) +#define PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_SHIFT (3U) +#define PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_MASK (0x1C0U) +#define PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_SHIFT (6U) +#define PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_MASK (0xE00U) +#define PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_SHIFT (9U) +#define PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_MASK (0x7000U) +#define PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_SHIFT (12U) +#define PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_MASK (0x38000U) +#define PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_SHIFT (15U) +#define PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_ALU_A_MEM_LP_STATE_MASK (0x1C0000U) +#define PXP_POWER_REG1_ALU_A_MEM_LP_STATE_SHIFT (18U) +#define PXP_POWER_REG1_ALU_A_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_ALU_A_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_ALU_A_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_ALU_B_MEM_LP_STATE_MASK (0xE00000U) +#define PXP_POWER_REG1_ALU_B_MEM_LP_STATE_SHIFT (21U) +#define PXP_POWER_REG1_ALU_B_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_ALU_B_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_ALU_B_MEM_LP_STATE_MASK) + +/*! @name DATA_PATH_CTRL0 - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_MUX0_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL0_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_MUX1_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL0_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX1_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_MUX3_SEL_SHIFT (6U) +#define PXP_DATA_PATH_CTRL0_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_MUX8_SEL_SHIFT (16U) +#define PXP_DATA_PATH_CTRL0_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX8_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_MUX9_SEL_SHIFT (18U) +#define PXP_DATA_PATH_CTRL0_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX9_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_MUX11_SEL_SHIFT (22U) +#define PXP_DATA_PATH_CTRL0_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX11_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_MUX12_SEL_SHIFT (24U) +#define PXP_DATA_PATH_CTRL0_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_MUX14_SEL_SHIFT (28U) +#define PXP_DATA_PATH_CTRL0_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX14_SEL_MASK) + +/*! @name DATA_PATH_CTRL0_SET - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL0_SET_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL0_SET_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_SHIFT (6U) +#define PXP_DATA_PATH_CTRL0_SET_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_SHIFT (16U) +#define PXP_DATA_PATH_CTRL0_SET_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_SHIFT (18U) +#define PXP_DATA_PATH_CTRL0_SET_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_SHIFT (22U) +#define PXP_DATA_PATH_CTRL0_SET_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_SHIFT (24U) +#define PXP_DATA_PATH_CTRL0_SET_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_SHIFT (28U) +#define PXP_DATA_PATH_CTRL0_SET_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_MASK) + +/*! @name DATA_PATH_CTRL0_CLR - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_SHIFT (6U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_SHIFT (16U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_SHIFT (18U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_SHIFT (22U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_SHIFT (24U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_SHIFT (28U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_MASK) + +/*! @name DATA_PATH_CTRL0_TOG - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_SHIFT (6U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_SHIFT (16U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_SHIFT (18U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_SHIFT (22U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_SHIFT (24U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_SHIFT (28U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_MASK) + +/*! @name DATA_PATH_CTRL1 - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL1_MUX16_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL1_MUX16_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL1_MUX16_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_MUX16_SEL_MASK) +#define PXP_DATA_PATH_CTRL1_MUX17_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL1_MUX17_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL1_MUX17_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_MUX17_SEL_MASK) + +/*! @name DATA_PATH_CTRL1_SET - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL1_SET_MUX16_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_MASK) +#define PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL1_SET_MUX17_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_MASK) + +/*! @name DATA_PATH_CTRL1_CLR - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_MASK) +#define PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_MASK) + +/*! @name DATA_PATH_CTRL1_TOG - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_MASK) +#define PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_MASK) + +/*! @name INIT_MEM_CTRL - Initialize memory buffer control Register */ +#define PXP_INIT_MEM_CTRL_ADDR_MASK (0xFFFFU) +#define PXP_INIT_MEM_CTRL_ADDR_SHIFT (0U) +#define PXP_INIT_MEM_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_ADDR_MASK) +#define PXP_INIT_MEM_CTRL_SELECT_MASK (0x78000000U) +#define PXP_INIT_MEM_CTRL_SELECT_SHIFT (27U) +#define PXP_INIT_MEM_CTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_SELECT_MASK) +#define PXP_INIT_MEM_CTRL_START_MASK (0x80000000U) +#define PXP_INIT_MEM_CTRL_START_SHIFT (31U) +#define PXP_INIT_MEM_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_START_SHIFT)) & PXP_INIT_MEM_CTRL_START_MASK) + +/*! @name INIT_MEM_CTRL_SET - Initialize memory buffer control Register */ +#define PXP_INIT_MEM_CTRL_SET_ADDR_MASK (0xFFFFU) +#define PXP_INIT_MEM_CTRL_SET_ADDR_SHIFT (0U) +#define PXP_INIT_MEM_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SET_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_SET_ADDR_MASK) +#define PXP_INIT_MEM_CTRL_SET_SELECT_MASK (0x78000000U) +#define PXP_INIT_MEM_CTRL_SET_SELECT_SHIFT (27U) +#define PXP_INIT_MEM_CTRL_SET_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SET_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_SET_SELECT_MASK) +#define PXP_INIT_MEM_CTRL_SET_START_MASK (0x80000000U) +#define PXP_INIT_MEM_CTRL_SET_START_SHIFT (31U) +#define PXP_INIT_MEM_CTRL_SET_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SET_START_SHIFT)) & PXP_INIT_MEM_CTRL_SET_START_MASK) + +/*! @name INIT_MEM_CTRL_CLR - Initialize memory buffer control Register */ +#define PXP_INIT_MEM_CTRL_CLR_ADDR_MASK (0xFFFFU) +#define PXP_INIT_MEM_CTRL_CLR_ADDR_SHIFT (0U) +#define PXP_INIT_MEM_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_CLR_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_CLR_ADDR_MASK) +#define PXP_INIT_MEM_CTRL_CLR_SELECT_MASK (0x78000000U) +#define PXP_INIT_MEM_CTRL_CLR_SELECT_SHIFT (27U) +#define PXP_INIT_MEM_CTRL_CLR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_CLR_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_CLR_SELECT_MASK) +#define PXP_INIT_MEM_CTRL_CLR_START_MASK (0x80000000U) +#define PXP_INIT_MEM_CTRL_CLR_START_SHIFT (31U) +#define PXP_INIT_MEM_CTRL_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_CLR_START_SHIFT)) & PXP_INIT_MEM_CTRL_CLR_START_MASK) + +/*! @name INIT_MEM_CTRL_TOG - Initialize memory buffer control Register */ +#define PXP_INIT_MEM_CTRL_TOG_ADDR_MASK (0xFFFFU) +#define PXP_INIT_MEM_CTRL_TOG_ADDR_SHIFT (0U) +#define PXP_INIT_MEM_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_TOG_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_TOG_ADDR_MASK) +#define PXP_INIT_MEM_CTRL_TOG_SELECT_MASK (0x78000000U) +#define PXP_INIT_MEM_CTRL_TOG_SELECT_SHIFT (27U) +#define PXP_INIT_MEM_CTRL_TOG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_TOG_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_TOG_SELECT_MASK) +#define PXP_INIT_MEM_CTRL_TOG_START_MASK (0x80000000U) +#define PXP_INIT_MEM_CTRL_TOG_START_SHIFT (31U) +#define PXP_INIT_MEM_CTRL_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_TOG_START_SHIFT)) & PXP_INIT_MEM_CTRL_TOG_START_MASK) + +/*! @name INIT_MEM_DATA - Write data Register */ +#define PXP_INIT_MEM_DATA_DATA_MASK (0xFFFFFFFFU) +#define PXP_INIT_MEM_DATA_DATA_SHIFT (0U) +#define PXP_INIT_MEM_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_DATA_DATA_SHIFT)) & PXP_INIT_MEM_DATA_DATA_MASK) + +/*! @name INIT_MEM_DATA_HIGH - Write data Register */ +#define PXP_INIT_MEM_DATA_HIGH_DATA_MASK (0xFFFFFFFFU) +#define PXP_INIT_MEM_DATA_HIGH_DATA_SHIFT (0U) +#define PXP_INIT_MEM_DATA_HIGH_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_DATA_HIGH_DATA_SHIFT)) & PXP_INIT_MEM_DATA_HIGH_DATA_MASK) + +/*! @name IRQ_MASK - PXP IRQ Mask Register */ +#define PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U) +#define PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U) +#define PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U) +#define PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U) +#define PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_MASK (0x8000U) +#define PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_SHIFT (15U) +#define PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_MASK) + +/*! @name IRQ_MASK_SET - PXP IRQ Mask Register */ +#define PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U) +#define PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U) +#define PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U) +#define PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U) +#define PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_MASK (0x8000U) +#define PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_SHIFT (15U) +#define PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_MASK) + +/*! @name IRQ_MASK_CLR - PXP IRQ Mask Register */ +#define PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U) +#define PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U) +#define PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U) +#define PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U) +#define PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_MASK (0x8000U) +#define PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_SHIFT (15U) +#define PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_MASK) + +/*! @name IRQ_MASK_TOG - PXP IRQ Mask Register */ +#define PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U) +#define PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U) +#define PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U) +#define PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U) +#define PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_MASK (0x8000U) +#define PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_SHIFT (15U) +#define PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_MASK) + +/*! @name IRQ - PXP Interrupt Register */ +#define PXP_IRQ_WFE_B_CH0_STORE_IRQ_MASK (0x400U) +#define PXP_IRQ_WFE_B_CH0_STORE_IRQ_SHIFT (10U) +#define PXP_IRQ_WFE_B_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_WFE_B_CH0_STORE_IRQ_MASK) +#define PXP_IRQ_WFE_B_CH1_STORE_IRQ_MASK (0x800U) +#define PXP_IRQ_WFE_B_CH1_STORE_IRQ_SHIFT (11U) +#define PXP_IRQ_WFE_B_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_WFE_B_CH1_STORE_IRQ_MASK) +#define PXP_IRQ_WFE_B_STORE_IRQ_MASK (0x8000U) +#define PXP_IRQ_WFE_B_STORE_IRQ_SHIFT (15U) +#define PXP_IRQ_WFE_B_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_WFE_B_STORE_IRQ_MASK) + +/*! @name IRQ_SET - PXP Interrupt Register */ +#define PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_MASK (0x400U) +#define PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_SHIFT (10U) +#define PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_MASK) +#define PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_MASK (0x800U) +#define PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_SHIFT (11U) +#define PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_MASK) +#define PXP_IRQ_SET_WFE_B_STORE_IRQ_MASK (0x8000U) +#define PXP_IRQ_SET_WFE_B_STORE_IRQ_SHIFT (15U) +#define PXP_IRQ_SET_WFE_B_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_WFE_B_STORE_IRQ_MASK) + +/*! @name IRQ_CLR - PXP Interrupt Register */ +#define PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_MASK (0x400U) +#define PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_SHIFT (10U) +#define PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_MASK) +#define PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_MASK (0x800U) +#define PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_SHIFT (11U) +#define PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_MASK) +#define PXP_IRQ_CLR_WFE_B_STORE_IRQ_MASK (0x8000U) +#define PXP_IRQ_CLR_WFE_B_STORE_IRQ_SHIFT (15U) +#define PXP_IRQ_CLR_WFE_B_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_WFE_B_STORE_IRQ_MASK) + +/*! @name IRQ_TOG - PXP Interrupt Register */ +#define PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_MASK (0x400U) +#define PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_SHIFT (10U) +#define PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_MASK) +#define PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_MASK (0x800U) +#define PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_SHIFT (11U) +#define PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_MASK) +#define PXP_IRQ_TOG_WFE_B_STORE_IRQ_MASK (0x8000U) +#define PXP_IRQ_TOG_WFE_B_STORE_IRQ_SHIFT (15U) +#define PXP_IRQ_TOG_WFE_B_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_WFE_B_STORE_IRQ_MASK) + +/*! @name NEXT_EN - PXP NEXT Buffer Enable select Register */ +#define PXP_NEXT_EN_LEGACY_MASK (0x1U) +#define PXP_NEXT_EN_LEGACY_SHIFT (0U) +#define PXP_NEXT_EN_LEGACY(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_LEGACY_SHIFT)) & PXP_NEXT_EN_LEGACY_MASK) +#define PXP_NEXT_EN_WFEB_MASK (0x2U) +#define PXP_NEXT_EN_WFEB_SHIFT (1U) +#define PXP_NEXT_EN_WFEB(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_WFEB_SHIFT)) & PXP_NEXT_EN_WFEB_MASK) + +/*! @name NEXT_EN_SET - PXP NEXT Buffer Enable select Register */ +#define PXP_NEXT_EN_SET_LEGACY_MASK (0x1U) +#define PXP_NEXT_EN_SET_LEGACY_SHIFT (0U) +#define PXP_NEXT_EN_SET_LEGACY(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_SET_LEGACY_SHIFT)) & PXP_NEXT_EN_SET_LEGACY_MASK) +#define PXP_NEXT_EN_SET_WFEB_MASK (0x2U) +#define PXP_NEXT_EN_SET_WFEB_SHIFT (1U) +#define PXP_NEXT_EN_SET_WFEB(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_SET_WFEB_SHIFT)) & PXP_NEXT_EN_SET_WFEB_MASK) + +/*! @name NEXT_EN_CLR - PXP NEXT Buffer Enable select Register */ +#define PXP_NEXT_EN_CLR_LEGACY_MASK (0x1U) +#define PXP_NEXT_EN_CLR_LEGACY_SHIFT (0U) +#define PXP_NEXT_EN_CLR_LEGACY(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_CLR_LEGACY_SHIFT)) & PXP_NEXT_EN_CLR_LEGACY_MASK) +#define PXP_NEXT_EN_CLR_WFEB_MASK (0x2U) +#define PXP_NEXT_EN_CLR_WFEB_SHIFT (1U) +#define PXP_NEXT_EN_CLR_WFEB(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_CLR_WFEB_SHIFT)) & PXP_NEXT_EN_CLR_WFEB_MASK) + +/*! @name NEXT_EN_TOG - PXP NEXT Buffer Enable select Register */ +#define PXP_NEXT_EN_TOG_LEGACY_MASK (0x1U) +#define PXP_NEXT_EN_TOG_LEGACY_SHIFT (0U) +#define PXP_NEXT_EN_TOG_LEGACY(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_TOG_LEGACY_SHIFT)) & PXP_NEXT_EN_TOG_LEGACY_MASK) +#define PXP_NEXT_EN_TOG_WFEB_MASK (0x2U) +#define PXP_NEXT_EN_TOG_WFEB_SHIFT (1U) +#define PXP_NEXT_EN_TOG_WFEB(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_TOG_WFEB_SHIFT)) & PXP_NEXT_EN_TOG_WFEB_MASK) + +/*! @name NEXT - Next Frame Pointer */ +#define PXP_NEXT_ENABLED_MASK (0x1U) +#define PXP_NEXT_ENABLED_SHIFT (0U) +#define PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK) +#define PXP_NEXT_POINTER_MASK (0xFFFFFFFCU) +#define PXP_NEXT_POINTER_SHIFT (2U) +#define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK) + +/*! @name DEBUGCTRL - Debug Control Register */ +#define PXP_DEBUGCTRL_SELECT_MASK (0xFFU) +#define PXP_DEBUGCTRL_SELECT_SHIFT (0U) +#define PXP_DEBUGCTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DEBUGCTRL_SELECT_SHIFT)) & PXP_DEBUGCTRL_SELECT_MASK) +#define PXP_DEBUGCTRL_LUT_CLR_STAT_CNT_MASK (0xF00U) +#define PXP_DEBUGCTRL_LUT_CLR_STAT_CNT_SHIFT (8U) +#define PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DEBUGCTRL_LUT_CLR_STAT_CNT_SHIFT)) & PXP_DEBUGCTRL_LUT_CLR_STAT_CNT_MASK) + +/*! @name DEBUG - Debug Register */ +#define PXP_DEBUG_DATA_MASK (0xFFFFFFFFU) +#define PXP_DEBUG_DATA_SHIFT (0U) +#define PXP_DEBUG_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_DEBUG_DATA_SHIFT)) & PXP_DEBUG_DATA_MASK) + +/*! @name VERSION - Version Register */ +#define PXP_VERSION_STEP_MASK (0xFFFFU) +#define PXP_VERSION_STEP_SHIFT (0U) +#define PXP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << PXP_VERSION_STEP_SHIFT)) & PXP_VERSION_STEP_MASK) +#define PXP_VERSION_MINOR_MASK (0xFF0000U) +#define PXP_VERSION_MINOR_SHIFT (16U) +#define PXP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_VERSION_MINOR_SHIFT)) & PXP_VERSION_MINOR_MASK) +#define PXP_VERSION_MAJOR_MASK (0xFF000000U) +#define PXP_VERSION_MAJOR_SHIFT (24U) +#define PXP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_VERSION_MAJOR_SHIFT)) & PXP_VERSION_MAJOR_MASK) + +/*! @name DITHER_STORE_SIZE_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_MASK (0xFFFFU) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_SHIFT (0U) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_SHIFT)) & PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_MASK) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_MASK (0xFFFF0000U) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT (16U) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT)) & PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_MASK) + +/*! @name WFB_FETCH_CTRL - Fetch engine Control for WFE B Register */ +#define PXP_WFB_FETCH_CTRL_BF1_EN_MASK (0x1U) +#define PXP_WFB_FETCH_CTRL_BF1_EN_SHIFT (0U) +#define PXP_WFB_FETCH_CTRL_BF1_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_EN_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_SRAM_IF_MASK (0x2U) +#define PXP_WFB_FETCH_CTRL_BF1_SRAM_IF_SHIFT (1U) +#define PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_HSK_MODE_MASK (0x4U) +#define PXP_WFB_FETCH_CTRL_BF1_HSK_MODE_SHIFT (2U) +#define PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE_MASK (0x8U) +#define PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE_SHIFT (3U) +#define PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_BURST_LEN_MASK (0x10U) +#define PXP_WFB_FETCH_CTRL_BF1_BURST_LEN_SHIFT (4U) +#define PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE_MASK (0x20U) +#define PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE_SHIFT (5U) +#define PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_EN_MASK (0x100U) +#define PXP_WFB_FETCH_CTRL_BF2_EN_SHIFT (8U) +#define PXP_WFB_FETCH_CTRL_BF2_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_EN_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_SRAM_IF_MASK (0x200U) +#define PXP_WFB_FETCH_CTRL_BF2_SRAM_IF_SHIFT (9U) +#define PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_HSK_MODE_MASK (0x400U) +#define PXP_WFB_FETCH_CTRL_BF2_HSK_MODE_SHIFT (10U) +#define PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE_MASK (0x800U) +#define PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE_SHIFT (11U) +#define PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_BURST_LEN_MASK (0x1000U) +#define PXP_WFB_FETCH_CTRL_BF2_BURST_LEN_SHIFT (12U) +#define PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE_MASK (0x2000U) +#define PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE_SHIFT (13U) +#define PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_BYTES_PP_MASK (0x30000U) +#define PXP_WFB_FETCH_CTRL_BF1_BYTES_PP_SHIFT (16U) +#define PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_LINE_MODE_MASK (0xC0000U) +#define PXP_WFB_FETCH_CTRL_BF1_LINE_MODE_SHIFT (18U) +#define PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_BYTES_PP_MASK (0x300000U) +#define PXP_WFB_FETCH_CTRL_BF2_BYTES_PP_SHIFT (20U) +#define PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_LINE_MODE_MASK (0xC00000U) +#define PXP_WFB_FETCH_CTRL_BF2_LINE_MODE_SHIFT (22U) +#define PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_MASK (0x10000000U) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_SHIFT (28U) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_MASK (0x20000000U) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_SHIFT (29U) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN_MASK (0x40000000U) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN_SHIFT (30U) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN_MASK) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN_MASK (0x80000000U) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN_SHIFT (31U) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN_MASK) + +/*! @name WFB_FETCH_CTRL_SET - Fetch engine Control for WFE B Register */ +#define PXP_WFB_FETCH_CTRL_SET_BF1_EN_MASK (0x1U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_EN_SHIFT (0U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_EN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF_MASK (0x2U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF_SHIFT (1U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE_MASK (0x4U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE_SHIFT (2U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE_MASK (0x8U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE_SHIFT (3U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN_MASK (0x10U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN_SHIFT (4U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE_MASK (0x20U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE_SHIFT (5U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_EN_MASK (0x100U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_EN_SHIFT (8U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_EN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF_MASK (0x200U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF_SHIFT (9U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE_MASK (0x400U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE_SHIFT (10U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE_MASK (0x800U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE_SHIFT (11U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN_MASK (0x1000U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN_SHIFT (12U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE_MASK (0x2000U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE_SHIFT (13U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP_MASK (0x30000U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP_SHIFT (16U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE_MASK (0xC0000U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE_SHIFT (18U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP_MASK (0x300000U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP_SHIFT (20U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE_MASK (0xC00000U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE_SHIFT (22U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_MASK (0x10000000U) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_SHIFT (28U) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_MASK (0x20000000U) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_SHIFT (29U) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_MASK (0x40000000U) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_SHIFT (30U) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_MASK (0x80000000U) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_SHIFT (31U) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_MASK) + +/*! @name WFB_FETCH_CTRL_CLR - Fetch engine Control for WFE B Register */ +#define PXP_WFB_FETCH_CTRL_CLR_BF1_EN_MASK (0x1U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_EN_SHIFT (0U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_EN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF_MASK (0x2U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF_SHIFT (1U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE_MASK (0x4U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE_SHIFT (2U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE_MASK (0x8U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE_SHIFT (3U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN_MASK (0x10U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN_SHIFT (4U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE_MASK (0x20U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE_SHIFT (5U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_EN_MASK (0x100U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_EN_SHIFT (8U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_EN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF_MASK (0x200U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF_SHIFT (9U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE_MASK (0x400U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE_SHIFT (10U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE_MASK (0x800U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE_SHIFT (11U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN_MASK (0x1000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN_SHIFT (12U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE_MASK (0x2000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE_SHIFT (13U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP_MASK (0x30000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP_SHIFT (16U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE_MASK (0xC0000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE_SHIFT (18U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP_MASK (0x300000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP_SHIFT (20U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE_MASK (0xC00000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE_SHIFT (22U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_MASK (0x10000000U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_SHIFT (28U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_MASK (0x20000000U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_SHIFT (29U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_MASK (0x40000000U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_SHIFT (30U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_MASK (0x80000000U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_SHIFT (31U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_MASK) + +/*! @name WFB_FETCH_CTRL_TOG - Fetch engine Control for WFE B Register */ +#define PXP_WFB_FETCH_CTRL_TOG_BF1_EN_MASK (0x1U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_EN_SHIFT (0U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_EN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF_MASK (0x2U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF_SHIFT (1U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE_MASK (0x4U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE_SHIFT (2U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE_MASK (0x8U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE_SHIFT (3U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN_MASK (0x10U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN_SHIFT (4U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE_MASK (0x20U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE_SHIFT (5U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_EN_MASK (0x100U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_EN_SHIFT (8U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_EN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF_MASK (0x200U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF_SHIFT (9U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE_MASK (0x400U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE_SHIFT (10U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE_MASK (0x800U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE_SHIFT (11U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN_MASK (0x1000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN_SHIFT (12U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE_MASK (0x2000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE_SHIFT (13U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP_MASK (0x30000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP_SHIFT (16U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE_MASK (0xC0000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE_SHIFT (18U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP_MASK (0x300000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP_SHIFT (20U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE_MASK (0xC00000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE_SHIFT (22U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_MASK (0x10000000U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_SHIFT (28U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_MASK (0x20000000U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_SHIFT (29U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_MASK (0x40000000U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_SHIFT (30U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_MASK (0x80000000U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_SHIFT (31U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_MASK) + +/*! @name WFB_FETCH_BUF1_ADDR - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR_SHIFT (0U) +#define PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR_SHIFT)) & PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR_MASK) + +/*! @name WFB_FETCH_BUF1_PITCH - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF1_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_WFB_FETCH_BUF1_PITCH_PITCH_SHIFT (0U) +#define PXP_WFB_FETCH_BUF1_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_PITCH_PITCH_SHIFT)) & PXP_WFB_FETCH_BUF1_PITCH_PITCH_MASK) + +/*! @name WFB_FETCH_BUF1_SIZE - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH_MASK (0xFFFFU) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH_SHIFT (0U) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH_SHIFT)) & PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH_MASK) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT_MASK (0xFFFF0000U) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT_SHIFT (16U) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT_SHIFT)) & PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT_MASK) + +/*! @name WFB_FETCH_BUF2_ADDR - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR_SHIFT (0U) +#define PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR_SHIFT)) & PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR_MASK) + +/*! @name WFB_FETCH_BUF2_PITCH - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF2_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_WFB_FETCH_BUF2_PITCH_PITCH_SHIFT (0U) +#define PXP_WFB_FETCH_BUF2_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_PITCH_PITCH_SHIFT)) & PXP_WFB_FETCH_BUF2_PITCH_PITCH_MASK) + +/*! @name WFB_FETCH_BUF2_SIZE - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH_MASK (0xFFFFU) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH_SHIFT (0U) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH_SHIFT)) & PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH_MASK) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT_MASK (0xFFFF0000U) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT_SHIFT (16U) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT_SHIFT)) & PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT_MASK) + +/*! @name WFB_ARRAY_PIXEL0_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL1_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL2_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL3_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL4_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL5_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL6_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL7_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG0_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG0_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG0_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG0_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG1_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG1_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG1_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG1_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG1_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG1_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG2_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG2_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG2_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG2_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG2_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG2_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG3_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG3_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG3_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG3_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG3_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG3_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG4_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG4_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG4_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG4_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG4_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG4_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG5_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG5_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG5_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG5_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG5_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG5_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG6_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG6_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG6_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG6_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG6_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG6_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG7_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG7_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG7_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG7_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG7_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG7_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL_MASK) + +/*! @name WFB_FETCH_BUF1_CORD - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_FETCH_BUF1_CORD_XCORD_MASK (0x3FFFU) +#define PXP_WFB_FETCH_BUF1_CORD_XCORD_SHIFT (0U) +#define PXP_WFB_FETCH_BUF1_CORD_XCORD(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_CORD_XCORD_SHIFT)) & PXP_WFB_FETCH_BUF1_CORD_XCORD_MASK) +#define PXP_WFB_FETCH_BUF1_CORD_YCORD_MASK (0x3FFF0000U) +#define PXP_WFB_FETCH_BUF1_CORD_YCORD_SHIFT (16U) +#define PXP_WFB_FETCH_BUF1_CORD_YCORD(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_CORD_YCORD_SHIFT)) & PXP_WFB_FETCH_BUF1_CORD_YCORD_MASK) + +/*! @name WFB_FETCH_BUF2_CORD - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_FETCH_BUF2_CORD_XCORD_MASK (0x3FFFU) +#define PXP_WFB_FETCH_BUF2_CORD_XCORD_SHIFT (0U) +#define PXP_WFB_FETCH_BUF2_CORD_XCORD(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_CORD_XCORD_SHIFT)) & PXP_WFB_FETCH_BUF2_CORD_XCORD_MASK) +#define PXP_WFB_FETCH_BUF2_CORD_YCORD_MASK (0x3FFF0000U) +#define PXP_WFB_FETCH_BUF2_CORD_YCORD_SHIFT (16U) +#define PXP_WFB_FETCH_BUF2_CORD_YCORD(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_CORD_YCORD_SHIFT)) & PXP_WFB_FETCH_BUF2_CORD_YCORD_MASK) + +/*! @name WFB_ARRAY_FLAG8_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG8_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG8_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG8_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG8_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG8_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG9_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG9_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG9_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG9_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG9_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG9_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG10_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG10_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG10_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG10_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG10_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG10_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG11_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG11_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG11_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG11_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG11_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG11_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG12_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG12_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG12_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG12_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG12_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG12_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG13_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG13_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG13_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG13_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG13_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG13_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG14_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG14_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG14_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG14_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG14_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG14_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG15_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG15_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG15_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG15_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG15_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG15_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_REG0 - This register defines software define pixels for wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_REG0_SW_PIXLE0_MASK (0xFFU) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE0_SHIFT (0U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG0_SW_PIXLE0_SHIFT)) & PXP_WFB_ARRAY_REG0_SW_PIXLE0_MASK) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE1_MASK (0xFF00U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE1_SHIFT (8U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG0_SW_PIXLE1_SHIFT)) & PXP_WFB_ARRAY_REG0_SW_PIXLE1_MASK) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE2_MASK (0xFF0000U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE2_SHIFT (16U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG0_SW_PIXLE2_SHIFT)) & PXP_WFB_ARRAY_REG0_SW_PIXLE2_MASK) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE3_MASK (0xFF000000U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE3_SHIFT (24U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG0_SW_PIXLE3_SHIFT)) & PXP_WFB_ARRAY_REG0_SW_PIXLE3_MASK) + +/*! @name WFB_ARRAY_REG1 - This register defines software define pixels for wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_REG1_SW_PIXLE4_MASK (0xFFU) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE4_SHIFT (0U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG1_SW_PIXLE4_SHIFT)) & PXP_WFB_ARRAY_REG1_SW_PIXLE4_MASK) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE5_MASK (0xFF00U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE5_SHIFT (8U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG1_SW_PIXLE5_SHIFT)) & PXP_WFB_ARRAY_REG1_SW_PIXLE5_MASK) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE6_MASK (0xFF0000U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE6_SHIFT (16U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG1_SW_PIXLE6_SHIFT)) & PXP_WFB_ARRAY_REG1_SW_PIXLE6_MASK) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE7_MASK (0xFF000000U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE7_SHIFT (24U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG1_SW_PIXLE7_SHIFT)) & PXP_WFB_ARRAY_REG1_SW_PIXLE7_MASK) + +/*! @name WFB_ARRAY_REG2 - This register defines software define pixels for wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_REG2_SW_FLAG0_MASK (0x1U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG0_SHIFT (0U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG0_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG0_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG1_MASK (0x2U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG1_SHIFT (1U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG1_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG1_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG2_MASK (0x4U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG2_SHIFT (2U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG2_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG2_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG3_MASK (0x8U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG3_SHIFT (3U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG3_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG3_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG4_MASK (0x10U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG4_SHIFT (4U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG4_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG4_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG5_MASK (0x20U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG5_SHIFT (5U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG5_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG5_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG6_MASK (0x40U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG6_SHIFT (6U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG6_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG6_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG7_MASK (0x80U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG7_SHIFT (7U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG7_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG7_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG8_MASK (0x100U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG8_SHIFT (8U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG8_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG8_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG9_MASK (0x200U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG9_SHIFT (9U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG9_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG9_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG10_MASK (0x400U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG10_SHIFT (10U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG10_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG10_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG11_MASK (0x800U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG11_SHIFT (11U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG11_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG11_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG12_MASK (0x1000U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG12_SHIFT (12U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG12_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG12_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG13_MASK (0x2000U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG13_SHIFT (13U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG13_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG13_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG14_MASK (0x4000U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG14_SHIFT (14U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG14_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG14_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG15_MASK (0x8000U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG15_SHIFT (15U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG15_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG15_MASK) + +/*! @name WFE_B_STORE_CTRL_CH0 - Store engine Control Channel 0 Register */ +#define PXP_WFE_B_STORE_CTRL_CH0_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH0_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH0_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_MASK (0x800U) +#define PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT (11U) +#define PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK (0x1000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT (24U) +#define PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_MASK (0x80000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_SHIFT (31U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_MASK) + +/*! @name WFE_B_STORE_CTRL_CH0_SET - Store engine Control Channel 0 Register */ +#define PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_MASK (0x800U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_SHIFT (11U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK (0x1000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_SHIFT (24U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_MASK (0x80000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_SHIFT (31U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_MASK) + +/*! @name WFE_B_STORE_CTRL_CH0_CLR - Store engine Control Channel 0 Register */ +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_MASK (0x800U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_SHIFT (11U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_MASK (0x1000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_SHIFT (24U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_MASK (0x80000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_SHIFT (31U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_MASK) + +/*! @name WFE_B_STORE_CTRL_CH0_TOG - Store engine Control Channel 0 Register */ +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_MASK (0x800U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_SHIFT (11U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_MASK (0x1000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_SHIFT (24U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_MASK (0x80000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_SHIFT (31U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_MASK) + +/*! @name WFE_B_STORE_CTRL_CH1 - Store engine Control Channel 1 Register */ +#define PXP_WFE_B_STORE_CTRL_CH1_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH1_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH1_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_MASK) + +/*! @name WFE_B_STORE_CTRL_CH1_SET - Store engine Control Channel 1 Register */ +#define PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_MASK) + +/*! @name WFE_B_STORE_CTRL_CH1_CLR - Store engine Control Channel 1 Register */ +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_MASK) + +/*! @name WFE_B_STORE_CTRL_CH1_TOG - Store engine Control Channel 1 Register */ +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_MASK) + +/*! @name WFE_B_STORE_STATUS_CH0 - Store engine status Channel 0 Register */ +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT (0U) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_MASK) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT (16U) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK) + +/*! @name WFE_B_STORE_STATUS_CH1 - Store engine status Channel 1 Register */ +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT (0U) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_MASK) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT (16U) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK) + +/*! @name WFE_B_STORE_SIZE_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_SHIFT (0U) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_MASK) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT (16U) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_MASK) + +/*! @name WFE_B_STORE_SIZE_CH1 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_SHIFT (0U) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_MASK) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT (16U) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_MASK) + +/*! @name WFE_B_STORE_PITCH - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_SHIFT (0U) +#define PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_SHIFT)) & PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_MASK) +#define PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_SHIFT (16U) +#define PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_SHIFT)) & PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK (0x80U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT (7U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH0_SET - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK (0x80U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT (7U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH0_CLR - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK (0x80U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT (7U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH0_TOG - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK (0x80U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT (7U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH1 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH1_SET - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH1_CLR - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH1_TOG - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_MASK) + +/*! @name WFE_B_STORE_ADDR_0_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT (0U) +#define PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT)) & PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK) + +/*! @name WFE_B_STORE_ADDR_1_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT (0U) +#define PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT)) & PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK) + +/*! @name WFE_B_STORE_FILL_DATA_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT)) & PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK) + +/*! @name WFE_B_STORE_ADDR_0_CH1 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT (0U) +#define PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT)) & PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK) + +/*! @name WFE_B_STORE_ADDR_1_CH1 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT (0U) +#define PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT)) & PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK) + +/*! @name WFE_B_STORE_D_MASK0_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK0_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK1_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK1_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK2_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK2_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK3_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK3_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK4_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK4_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK5_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK5_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK6_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK6_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK7_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK7_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_SHIFT_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK (0x3FU) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK (0x80U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT (7U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK (0x3F00U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT (8U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK (0x8000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT (15U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK (0x3F0000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT (16U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK (0x800000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT (23U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK (0x3F000000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT (24U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK (0x80000000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT (31U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK) + +/*! @name WFE_B_STORE_D_SHIFT_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK (0x3FU) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT (0U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK (0x80U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT (7U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK (0x3F00U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT (8U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK (0x8000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT (15U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK (0x3F0000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT (16U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK (0x800000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT (23U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK (0x3F000000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT (24U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK (0x80000000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT (31U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK) + +/*! @name WFE_B_STORE_F_SHIFT_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK (0x3FU) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT (0U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK (0x40U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT (6U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK (0x3F00U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT (8U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK (0x4000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT (14U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK (0x3F0000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT (16U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK (0x400000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT (22U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK (0x3F000000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT (24U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK (0x40000000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT (30U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK) + +/*! @name WFE_B_STORE_F_SHIFT_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK (0x3FU) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT (0U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK (0x40U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT (6U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK (0x3F00U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT (8U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK (0x4000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT (14U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK (0x3F0000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT (16U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK (0x400000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT (22U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK (0x3F000000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT (24U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK (0x40000000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT (30U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK) + +/*! @name WFE_B_STORE_F_MASK_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_MASK (0xFFU) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_SHIFT (0U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_MASK) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_MASK (0xFF00U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_SHIFT (8U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_MASK) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_MASK (0xFF0000U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_SHIFT (16U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_MASK) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_MASK (0xFF000000U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_SHIFT (24U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_MASK) + +/*! @name WFE_B_STORE_F_MASK_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_MASK (0xFFU) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_SHIFT (0U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_MASK) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_MASK (0xFF00U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_SHIFT (8U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_MASK) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_MASK (0xFF0000U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_SHIFT (16U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_MASK) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_MASK (0xFF000000U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_SHIFT (24U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_MASK) + +/*! @name FETCH_WFE_B_DEBUG - This register holds the debug bits for the prefetch engine for WFE B. */ +#define PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_MASK (0xFFFFFFU) +#define PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_SHIFT (0U) +#define PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_SHIFT)) & PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_MASK) +#define PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_MASK (0xF000000U) +#define PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_SHIFT (24U) +#define PXP_FETCH_WFE_B_DEBUG_ITEM_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_SHIFT)) & PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_MASK) +#define PXP_FETCH_WFE_B_DEBUG_BUF_SEL_MASK (0x10000000U) +#define PXP_FETCH_WFE_B_DEBUG_BUF_SEL_SHIFT (28U) +#define PXP_FETCH_WFE_B_DEBUG_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_B_DEBUG_BUF_SEL_SHIFT)) & PXP_FETCH_WFE_B_DEBUG_BUF_SEL_MASK) + +/*! @name DITHER_CTRL - Dither Control Register 0 */ +#define PXP_DITHER_CTRL_ENABLE0_MASK (0x1U) +#define PXP_DITHER_CTRL_ENABLE0_SHIFT (0U) +#define PXP_DITHER_CTRL_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_ENABLE0_MASK) +#define PXP_DITHER_CTRL_ENABLE1_MASK (0x2U) +#define PXP_DITHER_CTRL_ENABLE1_SHIFT (1U) +#define PXP_DITHER_CTRL_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_ENABLE1_MASK) +#define PXP_DITHER_CTRL_ENABLE2_MASK (0x4U) +#define PXP_DITHER_CTRL_ENABLE2_SHIFT (2U) +#define PXP_DITHER_CTRL_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_ENABLE2_MASK) +#define PXP_DITHER_CTRL_DITHER_MODE0_MASK (0x38U) +#define PXP_DITHER_CTRL_DITHER_MODE0_SHIFT (3U) +#define PXP_DITHER_CTRL_DITHER_MODE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_DITHER_MODE0_MASK) +#define PXP_DITHER_CTRL_DITHER_MODE1_MASK (0x1C0U) +#define PXP_DITHER_CTRL_DITHER_MODE1_SHIFT (6U) +#define PXP_DITHER_CTRL_DITHER_MODE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_DITHER_MODE1_MASK) +#define PXP_DITHER_CTRL_DITHER_MODE2_MASK (0xE00U) +#define PXP_DITHER_CTRL_DITHER_MODE2_SHIFT (9U) +#define PXP_DITHER_CTRL_DITHER_MODE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_DITHER_MODE2_MASK) +#define PXP_DITHER_CTRL_NUM_QUANT_BIT_MASK (0x7000U) +#define PXP_DITHER_CTRL_NUM_QUANT_BIT_SHIFT (12U) +#define PXP_DITHER_CTRL_NUM_QUANT_BIT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_NUM_QUANT_BIT_MASK) +#define PXP_DITHER_CTRL_LUT_MODE_MASK (0x18000U) +#define PXP_DITHER_CTRL_LUT_MODE_SHIFT (15U) +#define PXP_DITHER_CTRL_LUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_LUT_MODE_MASK) +#define PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_MASK (0x60000U) +#define PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_SHIFT (17U) +#define PXP_DITHER_CTRL_IDX_MATRIX0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_MASK) +#define PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_MASK (0x180000U) +#define PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_SHIFT (19U) +#define PXP_DITHER_CTRL_IDX_MATRIX1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_MASK) +#define PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_MASK (0x600000U) +#define PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_SHIFT (21U) +#define PXP_DITHER_CTRL_IDX_MATRIX2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_MASK) +#define PXP_DITHER_CTRL_FINAL_LUT_ENABLE_MASK (0x800000U) +#define PXP_DITHER_CTRL_FINAL_LUT_ENABLE_SHIFT (23U) +#define PXP_DITHER_CTRL_FINAL_LUT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_FINAL_LUT_ENABLE_MASK) +#define PXP_DITHER_CTRL_ORDERED_ROUND_MODE_MASK (0x1000000U) +#define PXP_DITHER_CTRL_ORDERED_ROUND_MODE_SHIFT (24U) +#define PXP_DITHER_CTRL_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_ORDERED_ROUND_MODE_MASK) +#define PXP_DITHER_CTRL_BUSY2_MASK (0x20000000U) +#define PXP_DITHER_CTRL_BUSY2_SHIFT (29U) +#define PXP_DITHER_CTRL_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_BUSY2_SHIFT)) & PXP_DITHER_CTRL_BUSY2_MASK) +#define PXP_DITHER_CTRL_BUSY1_MASK (0x40000000U) +#define PXP_DITHER_CTRL_BUSY1_SHIFT (30U) +#define PXP_DITHER_CTRL_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_BUSY1_SHIFT)) & PXP_DITHER_CTRL_BUSY1_MASK) +#define PXP_DITHER_CTRL_BUSY0_MASK (0x80000000U) +#define PXP_DITHER_CTRL_BUSY0_SHIFT (31U) +#define PXP_DITHER_CTRL_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_BUSY0_SHIFT)) & PXP_DITHER_CTRL_BUSY0_MASK) + +/*! @name DITHER_CTRL_SET - Dither Control Register 0 */ +#define PXP_DITHER_CTRL_SET_ENABLE0_MASK (0x1U) +#define PXP_DITHER_CTRL_SET_ENABLE0_SHIFT (0U) +#define PXP_DITHER_CTRL_SET_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_SET_ENABLE0_MASK) +#define PXP_DITHER_CTRL_SET_ENABLE1_MASK (0x2U) +#define PXP_DITHER_CTRL_SET_ENABLE1_SHIFT (1U) +#define PXP_DITHER_CTRL_SET_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_SET_ENABLE1_MASK) +#define PXP_DITHER_CTRL_SET_ENABLE2_MASK (0x4U) +#define PXP_DITHER_CTRL_SET_ENABLE2_SHIFT (2U) +#define PXP_DITHER_CTRL_SET_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_SET_ENABLE2_MASK) +#define PXP_DITHER_CTRL_SET_DITHER_MODE0_MASK (0x38U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE0_SHIFT (3U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_SET_DITHER_MODE0_MASK) +#define PXP_DITHER_CTRL_SET_DITHER_MODE1_MASK (0x1C0U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE1_SHIFT (6U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_SET_DITHER_MODE1_MASK) +#define PXP_DITHER_CTRL_SET_DITHER_MODE2_MASK (0xE00U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE2_SHIFT (9U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_SET_DITHER_MODE2_MASK) +#define PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_MASK (0x7000U) +#define PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_SHIFT (12U) +#define PXP_DITHER_CTRL_SET_NUM_QUANT_BIT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_MASK) +#define PXP_DITHER_CTRL_SET_LUT_MODE_MASK (0x18000U) +#define PXP_DITHER_CTRL_SET_LUT_MODE_SHIFT (15U) +#define PXP_DITHER_CTRL_SET_LUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_SET_LUT_MODE_MASK) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_MASK (0x60000U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_SHIFT (17U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_MASK) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_MASK (0x180000U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_SHIFT (19U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_MASK) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_MASK (0x600000U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_SHIFT (21U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_MASK) +#define PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_MASK (0x800000U) +#define PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_SHIFT (23U) +#define PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_MASK) +#define PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_MASK (0x1000000U) +#define PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_SHIFT (24U) +#define PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_MASK) +#define PXP_DITHER_CTRL_SET_BUSY2_MASK (0x20000000U) +#define PXP_DITHER_CTRL_SET_BUSY2_SHIFT (29U) +#define PXP_DITHER_CTRL_SET_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_BUSY2_SHIFT)) & PXP_DITHER_CTRL_SET_BUSY2_MASK) +#define PXP_DITHER_CTRL_SET_BUSY1_MASK (0x40000000U) +#define PXP_DITHER_CTRL_SET_BUSY1_SHIFT (30U) +#define PXP_DITHER_CTRL_SET_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_BUSY1_SHIFT)) & PXP_DITHER_CTRL_SET_BUSY1_MASK) +#define PXP_DITHER_CTRL_SET_BUSY0_MASK (0x80000000U) +#define PXP_DITHER_CTRL_SET_BUSY0_SHIFT (31U) +#define PXP_DITHER_CTRL_SET_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_BUSY0_SHIFT)) & PXP_DITHER_CTRL_SET_BUSY0_MASK) + +/*! @name DITHER_CTRL_CLR - Dither Control Register 0 */ +#define PXP_DITHER_CTRL_CLR_ENABLE0_MASK (0x1U) +#define PXP_DITHER_CTRL_CLR_ENABLE0_SHIFT (0U) +#define PXP_DITHER_CTRL_CLR_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_CLR_ENABLE0_MASK) +#define PXP_DITHER_CTRL_CLR_ENABLE1_MASK (0x2U) +#define PXP_DITHER_CTRL_CLR_ENABLE1_SHIFT (1U) +#define PXP_DITHER_CTRL_CLR_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_CLR_ENABLE1_MASK) +#define PXP_DITHER_CTRL_CLR_ENABLE2_MASK (0x4U) +#define PXP_DITHER_CTRL_CLR_ENABLE2_SHIFT (2U) +#define PXP_DITHER_CTRL_CLR_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_CLR_ENABLE2_MASK) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE0_MASK (0x38U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE0_SHIFT (3U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_CLR_DITHER_MODE0_MASK) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE1_MASK (0x1C0U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE1_SHIFT (6U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_CLR_DITHER_MODE1_MASK) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE2_MASK (0xE00U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE2_SHIFT (9U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_CLR_DITHER_MODE2_MASK) +#define PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_MASK (0x7000U) +#define PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_SHIFT (12U) +#define PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_MASK) +#define PXP_DITHER_CTRL_CLR_LUT_MODE_MASK (0x18000U) +#define PXP_DITHER_CTRL_CLR_LUT_MODE_SHIFT (15U) +#define PXP_DITHER_CTRL_CLR_LUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_CLR_LUT_MODE_MASK) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_MASK (0x60000U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_SHIFT (17U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_MASK) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_MASK (0x180000U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_SHIFT (19U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_MASK) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_MASK (0x600000U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_SHIFT (21U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_MASK) +#define PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_MASK (0x800000U) +#define PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_SHIFT (23U) +#define PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_MASK) +#define PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_MASK (0x1000000U) +#define PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_SHIFT (24U) +#define PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_MASK) +#define PXP_DITHER_CTRL_CLR_BUSY2_MASK (0x20000000U) +#define PXP_DITHER_CTRL_CLR_BUSY2_SHIFT (29U) +#define PXP_DITHER_CTRL_CLR_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_BUSY2_SHIFT)) & PXP_DITHER_CTRL_CLR_BUSY2_MASK) +#define PXP_DITHER_CTRL_CLR_BUSY1_MASK (0x40000000U) +#define PXP_DITHER_CTRL_CLR_BUSY1_SHIFT (30U) +#define PXP_DITHER_CTRL_CLR_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_BUSY1_SHIFT)) & PXP_DITHER_CTRL_CLR_BUSY1_MASK) +#define PXP_DITHER_CTRL_CLR_BUSY0_MASK (0x80000000U) +#define PXP_DITHER_CTRL_CLR_BUSY0_SHIFT (31U) +#define PXP_DITHER_CTRL_CLR_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_BUSY0_SHIFT)) & PXP_DITHER_CTRL_CLR_BUSY0_MASK) + +/*! @name DITHER_CTRL_TOG - Dither Control Register 0 */ +#define PXP_DITHER_CTRL_TOG_ENABLE0_MASK (0x1U) +#define PXP_DITHER_CTRL_TOG_ENABLE0_SHIFT (0U) +#define PXP_DITHER_CTRL_TOG_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_TOG_ENABLE0_MASK) +#define PXP_DITHER_CTRL_TOG_ENABLE1_MASK (0x2U) +#define PXP_DITHER_CTRL_TOG_ENABLE1_SHIFT (1U) +#define PXP_DITHER_CTRL_TOG_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_TOG_ENABLE1_MASK) +#define PXP_DITHER_CTRL_TOG_ENABLE2_MASK (0x4U) +#define PXP_DITHER_CTRL_TOG_ENABLE2_SHIFT (2U) +#define PXP_DITHER_CTRL_TOG_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_TOG_ENABLE2_MASK) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE0_MASK (0x38U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE0_SHIFT (3U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_TOG_DITHER_MODE0_MASK) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE1_MASK (0x1C0U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE1_SHIFT (6U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_TOG_DITHER_MODE1_MASK) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE2_MASK (0xE00U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE2_SHIFT (9U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_TOG_DITHER_MODE2_MASK) +#define PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_MASK (0x7000U) +#define PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_SHIFT (12U) +#define PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_MASK) +#define PXP_DITHER_CTRL_TOG_LUT_MODE_MASK (0x18000U) +#define PXP_DITHER_CTRL_TOG_LUT_MODE_SHIFT (15U) +#define PXP_DITHER_CTRL_TOG_LUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_TOG_LUT_MODE_MASK) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_MASK (0x60000U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_SHIFT (17U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_MASK) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_MASK (0x180000U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_SHIFT (19U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_MASK) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_MASK (0x600000U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_SHIFT (21U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_MASK) +#define PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_MASK (0x800000U) +#define PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_SHIFT (23U) +#define PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_MASK) +#define PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_MASK (0x1000000U) +#define PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_SHIFT (24U) +#define PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_MASK) +#define PXP_DITHER_CTRL_TOG_BUSY2_MASK (0x20000000U) +#define PXP_DITHER_CTRL_TOG_BUSY2_SHIFT (29U) +#define PXP_DITHER_CTRL_TOG_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_BUSY2_SHIFT)) & PXP_DITHER_CTRL_TOG_BUSY2_MASK) +#define PXP_DITHER_CTRL_TOG_BUSY1_MASK (0x40000000U) +#define PXP_DITHER_CTRL_TOG_BUSY1_SHIFT (30U) +#define PXP_DITHER_CTRL_TOG_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_BUSY1_SHIFT)) & PXP_DITHER_CTRL_TOG_BUSY1_MASK) +#define PXP_DITHER_CTRL_TOG_BUSY0_MASK (0x80000000U) +#define PXP_DITHER_CTRL_TOG_BUSY0_SHIFT (31U) +#define PXP_DITHER_CTRL_TOG_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_BUSY0_SHIFT)) & PXP_DITHER_CTRL_TOG_BUSY0_MASK) + +/*! @name DITHER_FINAL_LUT_DATA0 - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA0_DATA0_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA0_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA0_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA1_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA1_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA1_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA2_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA2_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA2_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA3_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA3_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA3_MASK) + +/*! @name DITHER_FINAL_LUT_DATA0_SET - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_MASK) + +/*! @name DITHER_FINAL_LUT_DATA0_CLR - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_MASK) + +/*! @name DITHER_FINAL_LUT_DATA0_TOG - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_MASK) + +/*! @name DITHER_FINAL_LUT_DATA1 - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA1_DATA4_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA4_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA4_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA5_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA5_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA5_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA6_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA6_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA6_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA7_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA7_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA7_MASK) + +/*! @name DITHER_FINAL_LUT_DATA1_SET - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_MASK) + +/*! @name DITHER_FINAL_LUT_DATA1_CLR - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_MASK) + +/*! @name DITHER_FINAL_LUT_DATA1_TOG - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_MASK) + +/*! @name DITHER_FINAL_LUT_DATA2 - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA2_DATA8_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA8_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA8(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA8_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA9_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA9_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA9(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA9_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA10_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA10_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA10_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA11_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA11_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA11_MASK) + +/*! @name DITHER_FINAL_LUT_DATA2_SET - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_MASK) + +/*! @name DITHER_FINAL_LUT_DATA2_CLR - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_MASK) + +/*! @name DITHER_FINAL_LUT_DATA2_TOG - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_MASK) + +/*! @name DITHER_FINAL_LUT_DATA3 - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA3_DATA12_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA12_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA12_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA13_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA13_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA13_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA14_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA14_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA14_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA15_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA15_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA15_MASK) + +/*! @name DITHER_FINAL_LUT_DATA3_SET - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_MASK) + +/*! @name DITHER_FINAL_LUT_DATA3_CLR - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_MASK) + +/*! @name DITHER_FINAL_LUT_DATA3_TOG - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_MASK) + +/*! @name WFE_B_CTRL - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_CTRL_ENABLE_MASK (0x1U) +#define PXP_WFE_B_CTRL_ENABLE_SHIFT (0U) +#define PXP_WFE_B_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_ENABLE_MASK) +#define PXP_WFE_B_CTRL_SW_RESET_MASK (0x4U) +#define PXP_WFE_B_CTRL_SW_RESET_SHIFT (2U) +#define PXP_WFE_B_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_SW_RESET_MASK) +#define PXP_WFE_B_CTRL_DONE_MASK (0x80000000U) +#define PXP_WFE_B_CTRL_DONE_SHIFT (31U) +#define PXP_WFE_B_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_DONE_SHIFT)) & PXP_WFE_B_CTRL_DONE_MASK) + +/*! @name WFE_B_CTRL_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_CTRL_SET_ENABLE_MASK (0x1U) +#define PXP_WFE_B_CTRL_SET_ENABLE_SHIFT (0U) +#define PXP_WFE_B_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SET_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_SET_ENABLE_MASK) +#define PXP_WFE_B_CTRL_SET_SW_RESET_MASK (0x4U) +#define PXP_WFE_B_CTRL_SET_SW_RESET_SHIFT (2U) +#define PXP_WFE_B_CTRL_SET_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SET_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_SET_SW_RESET_MASK) +#define PXP_WFE_B_CTRL_SET_DONE_MASK (0x80000000U) +#define PXP_WFE_B_CTRL_SET_DONE_SHIFT (31U) +#define PXP_WFE_B_CTRL_SET_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SET_DONE_SHIFT)) & PXP_WFE_B_CTRL_SET_DONE_MASK) + +/*! @name WFE_B_CTRL_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_CTRL_CLR_ENABLE_MASK (0x1U) +#define PXP_WFE_B_CTRL_CLR_ENABLE_SHIFT (0U) +#define PXP_WFE_B_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_CLR_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_CLR_ENABLE_MASK) +#define PXP_WFE_B_CTRL_CLR_SW_RESET_MASK (0x4U) +#define PXP_WFE_B_CTRL_CLR_SW_RESET_SHIFT (2U) +#define PXP_WFE_B_CTRL_CLR_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_CLR_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_CLR_SW_RESET_MASK) +#define PXP_WFE_B_CTRL_CLR_DONE_MASK (0x80000000U) +#define PXP_WFE_B_CTRL_CLR_DONE_SHIFT (31U) +#define PXP_WFE_B_CTRL_CLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_CLR_DONE_SHIFT)) & PXP_WFE_B_CTRL_CLR_DONE_MASK) + +/*! @name WFE_B_CTRL_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_CTRL_TOG_ENABLE_MASK (0x1U) +#define PXP_WFE_B_CTRL_TOG_ENABLE_SHIFT (0U) +#define PXP_WFE_B_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_TOG_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_TOG_ENABLE_MASK) +#define PXP_WFE_B_CTRL_TOG_SW_RESET_MASK (0x4U) +#define PXP_WFE_B_CTRL_TOG_SW_RESET_SHIFT (2U) +#define PXP_WFE_B_CTRL_TOG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_TOG_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_TOG_SW_RESET_MASK) +#define PXP_WFE_B_CTRL_TOG_DONE_MASK (0x80000000U) +#define PXP_WFE_B_CTRL_TOG_DONE_SHIFT (31U) +#define PXP_WFE_B_CTRL_TOG_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_TOG_DONE_SHIFT)) & PXP_WFE_B_CTRL_TOG_DONE_MASK) + +/*! @name WFE_B_DIMENSIONS - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_DIMENSIONS_WIDTH_MASK (0xFFFU) +#define PXP_WFE_B_DIMENSIONS_WIDTH_SHIFT (0U) +#define PXP_WFE_B_DIMENSIONS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_DIMENSIONS_WIDTH_SHIFT)) & PXP_WFE_B_DIMENSIONS_WIDTH_MASK) +#define PXP_WFE_B_DIMENSIONS_HEIGHT_MASK (0xFFF0000U) +#define PXP_WFE_B_DIMENSIONS_HEIGHT_SHIFT (16U) +#define PXP_WFE_B_DIMENSIONS_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_DIMENSIONS_HEIGHT_SHIFT)) & PXP_WFE_B_DIMENSIONS_HEIGHT_MASK) + +/*! @name WFE_B_OFFSET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_OFFSET_X_OFFSET_MASK (0xFFFU) +#define PXP_WFE_B_OFFSET_X_OFFSET_SHIFT (0U) +#define PXP_WFE_B_OFFSET_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_OFFSET_X_OFFSET_SHIFT)) & PXP_WFE_B_OFFSET_X_OFFSET_MASK) +#define PXP_WFE_B_OFFSET_Y_OFFSET_MASK (0xFFF0000U) +#define PXP_WFE_B_OFFSET_Y_OFFSET_SHIFT (16U) +#define PXP_WFE_B_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_OFFSET_Y_OFFSET_SHIFT)) & PXP_WFE_B_OFFSET_Y_OFFSET_MASK) + +/*! @name WFE_B_SW_DATA_REGS - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_SW_DATA_REGS_VAL0_MASK (0xFFU) +#define PXP_WFE_B_SW_DATA_REGS_VAL0_SHIFT (0U) +#define PXP_WFE_B_SW_DATA_REGS_VAL0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL0_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL0_MASK) +#define PXP_WFE_B_SW_DATA_REGS_VAL1_MASK (0xFF00U) +#define PXP_WFE_B_SW_DATA_REGS_VAL1_SHIFT (8U) +#define PXP_WFE_B_SW_DATA_REGS_VAL1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL1_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL1_MASK) +#define PXP_WFE_B_SW_DATA_REGS_VAL2_MASK (0xFF0000U) +#define PXP_WFE_B_SW_DATA_REGS_VAL2_SHIFT (16U) +#define PXP_WFE_B_SW_DATA_REGS_VAL2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL2_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL2_MASK) +#define PXP_WFE_B_SW_DATA_REGS_VAL3_MASK (0xFF000000U) +#define PXP_WFE_B_SW_DATA_REGS_VAL3_SHIFT (24U) +#define PXP_WFE_B_SW_DATA_REGS_VAL3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL3_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL3_MASK) + +/*! @name WFE_B_SW_FLAG_REGS - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_SW_FLAG_REGS_VAL0_MASK (0x1U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL0_SHIFT (0U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL0_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL0_MASK) +#define PXP_WFE_B_SW_FLAG_REGS_VAL1_MASK (0x2U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL1_SHIFT (1U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL1_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL1_MASK) +#define PXP_WFE_B_SW_FLAG_REGS_VAL2_MASK (0x4U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL2_SHIFT (2U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL2_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL2_MASK) +#define PXP_WFE_B_SW_FLAG_REGS_VAL3_MASK (0x8U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL3_SHIFT (3U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL3_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL3_MASK) + +/*! @name WFE_B_STAGE1_MUX0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX0_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX0_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX0_MASK) +#define PXP_WFE_B_STAGE1_MUX0_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX0_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX0_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX1_MASK) +#define PXP_WFE_B_STAGE1_MUX0_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX0_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX0_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX2_MASK) +#define PXP_WFE_B_STAGE1_MUX0_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX0_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX0_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX3_MASK) + +/*! @name WFE_B_STAGE1_MUX0_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX0_MASK) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX1_MASK) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX2_MASK) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX3_MASK) + +/*! @name WFE_B_STAGE1_MUX0_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_MASK) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_MASK) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_MASK) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_MASK) + +/*! @name WFE_B_STAGE1_MUX0_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_MASK) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_MASK) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_MASK) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_MASK) + +/*! @name WFE_B_STAGE1_MUX1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX1_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX1_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX1_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX4_MASK) +#define PXP_WFE_B_STAGE1_MUX1_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX1_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX1_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX5_MASK) +#define PXP_WFE_B_STAGE1_MUX1_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX1_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX1_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX6_MASK) +#define PXP_WFE_B_STAGE1_MUX1_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX1_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX1_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX7_MASK) + +/*! @name WFE_B_STAGE1_MUX1_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX4_MASK) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX5_MASK) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX6_MASK) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX7_MASK) + +/*! @name WFE_B_STAGE1_MUX1_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_MASK) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_MASK) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_MASK) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_MASK) + +/*! @name WFE_B_STAGE1_MUX1_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_MASK) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_MASK) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_MASK) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_MASK) + +/*! @name WFE_B_STAGE1_MUX2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX2_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX2_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX2_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX8_MASK) +#define PXP_WFE_B_STAGE1_MUX2_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX2_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX2_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX9_MASK) +#define PXP_WFE_B_STAGE1_MUX2_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX2_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX2_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX10_MASK) +#define PXP_WFE_B_STAGE1_MUX2_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX2_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX2_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX11_MASK) + +/*! @name WFE_B_STAGE1_MUX2_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX8_MASK) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX9_MASK) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX10_MASK) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX11_MASK) + +/*! @name WFE_B_STAGE1_MUX2_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_MASK) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_MASK) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_MASK) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_MASK) + +/*! @name WFE_B_STAGE1_MUX2_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_MASK) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_MASK) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_MASK) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_MASK) + +/*! @name WFE_B_STAGE1_MUX3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX3_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX3_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX3_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX12_MASK) +#define PXP_WFE_B_STAGE1_MUX3_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX3_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX3_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX13_MASK) +#define PXP_WFE_B_STAGE1_MUX3_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX3_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX3_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX14_MASK) +#define PXP_WFE_B_STAGE1_MUX3_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX3_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX3_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX15_MASK) + +/*! @name WFE_B_STAGE1_MUX3_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX12_MASK) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX13_MASK) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX14_MASK) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX15_MASK) + +/*! @name WFE_B_STAGE1_MUX3_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_MASK) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_MASK) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_MASK) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_MASK) + +/*! @name WFE_B_STAGE1_MUX3_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_MASK) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_MASK) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_MASK) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_MASK) + +/*! @name WFE_B_STAGE1_MUX4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX4_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX4_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX4_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX16_MASK) +#define PXP_WFE_B_STAGE1_MUX4_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX4_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX4_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX17_MASK) +#define PXP_WFE_B_STAGE1_MUX4_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX4_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX4_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX18_MASK) +#define PXP_WFE_B_STAGE1_MUX4_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX4_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX4_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX19_MASK) + +/*! @name WFE_B_STAGE1_MUX4_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX16_MASK) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX17_MASK) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX18_MASK) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX19_MASK) + +/*! @name WFE_B_STAGE1_MUX4_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_MASK) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_MASK) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_MASK) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_MASK) + +/*! @name WFE_B_STAGE1_MUX4_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_MASK) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_MASK) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_MASK) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_MASK) + +/*! @name WFE_B_STAGE1_MUX5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX5_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX5_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX5_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX20_MASK) +#define PXP_WFE_B_STAGE1_MUX5_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX5_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX5_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX21_MASK) +#define PXP_WFE_B_STAGE1_MUX5_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX5_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX5_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX22_MASK) +#define PXP_WFE_B_STAGE1_MUX5_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX5_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX5_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX23_MASK) + +/*! @name WFE_B_STAGE1_MUX5_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX20_MASK) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX21_MASK) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX22_MASK) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX23_MASK) + +/*! @name WFE_B_STAGE1_MUX5_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_MASK) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_MASK) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_MASK) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_MASK) + +/*! @name WFE_B_STAGE1_MUX5_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_MASK) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_MASK) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_MASK) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_MASK) + +/*! @name WFE_B_STAGE1_MUX6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX6_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX6_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX6_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX24_MASK) +#define PXP_WFE_B_STAGE1_MUX6_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX6_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX6_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX25_MASK) +#define PXP_WFE_B_STAGE1_MUX6_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX6_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX6_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX26_MASK) +#define PXP_WFE_B_STAGE1_MUX6_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX6_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX6_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX27_MASK) + +/*! @name WFE_B_STAGE1_MUX6_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX24_MASK) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX25_MASK) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX26_MASK) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX27_MASK) + +/*! @name WFE_B_STAGE1_MUX6_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_MASK) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_MASK) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_MASK) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_MASK) + +/*! @name WFE_B_STAGE1_MUX6_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_MASK) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_MASK) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_MASK) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_MASK) + +/*! @name WFE_B_STAGE1_MUX7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX7_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX7_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX7_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX28_MASK) +#define PXP_WFE_B_STAGE1_MUX7_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX7_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX7_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX29_MASK) +#define PXP_WFE_B_STAGE1_MUX7_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX7_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX7_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX30_MASK) +#define PXP_WFE_B_STAGE1_MUX7_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX7_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX7_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX31_MASK) + +/*! @name WFE_B_STAGE1_MUX7_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX28_MASK) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX29_MASK) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX30_MASK) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX31_MASK) + +/*! @name WFE_B_STAGE1_MUX7_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_MASK) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_MASK) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_MASK) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_MASK) + +/*! @name WFE_B_STAGE1_MUX7_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_MASK) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_MASK) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_MASK) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_MASK) + +/*! @name WFE_B_STAGE1_MUX8 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX8_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX8_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX8_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_MUX32_MASK) + +/*! @name WFE_B_STAGE1_MUX8_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX8_SET_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX8_SET_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX8_SET_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_SET_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_SET_MUX32_MASK) + +/*! @name WFE_B_STAGE1_MUX8_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX8_CLR_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_MASK) + +/*! @name WFE_B_STAGE1_MUX8_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX8_TOG_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_MASK) + +/*! @name WFE_B_STAGE2_MUX0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX0_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX0_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX0_MASK) +#define PXP_WFE_B_STAGE2_MUX0_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX0_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX0_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX1_MASK) +#define PXP_WFE_B_STAGE2_MUX0_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX0_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX0_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX2_MASK) +#define PXP_WFE_B_STAGE2_MUX0_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX0_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX0_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX3_MASK) + +/*! @name WFE_B_STAGE2_MUX0_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX0_MASK) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX1_MASK) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX2_MASK) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX3_MASK) + +/*! @name WFE_B_STAGE2_MUX0_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_MASK) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_MASK) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_MASK) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_MASK) + +/*! @name WFE_B_STAGE2_MUX0_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_MASK) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_MASK) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_MASK) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_MASK) + +/*! @name WFE_B_STAGE2_MUX1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX1_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX1_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX1_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX4_MASK) +#define PXP_WFE_B_STAGE2_MUX1_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX1_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX1_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX5_MASK) +#define PXP_WFE_B_STAGE2_MUX1_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX1_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX1_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX6_MASK) +#define PXP_WFE_B_STAGE2_MUX1_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX1_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX1_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX7_MASK) + +/*! @name WFE_B_STAGE2_MUX1_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX4_MASK) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX5_MASK) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX6_MASK) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX7_MASK) + +/*! @name WFE_B_STAGE2_MUX1_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_MASK) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_MASK) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_MASK) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_MASK) + +/*! @name WFE_B_STAGE2_MUX1_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_MASK) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_MASK) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_MASK) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_MASK) + +/*! @name WFE_B_STAGE2_MUX2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX2_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX2_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX2_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX8_MASK) +#define PXP_WFE_B_STAGE2_MUX2_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX2_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX2_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX9_MASK) +#define PXP_WFE_B_STAGE2_MUX2_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX2_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX2_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX10_MASK) +#define PXP_WFE_B_STAGE2_MUX2_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX2_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX2_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX11_MASK) + +/*! @name WFE_B_STAGE2_MUX2_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX8_MASK) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX9_MASK) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX10_MASK) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX11_MASK) + +/*! @name WFE_B_STAGE2_MUX2_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_MASK) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_MASK) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_MASK) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_MASK) + +/*! @name WFE_B_STAGE2_MUX2_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_MASK) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_MASK) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_MASK) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_MASK) + +/*! @name WFE_B_STAGE2_MUX3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX3_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX3_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX3_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX12_MASK) +#define PXP_WFE_B_STAGE2_MUX3_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX3_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX3_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX13_MASK) +#define PXP_WFE_B_STAGE2_MUX3_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX3_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX3_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX14_MASK) +#define PXP_WFE_B_STAGE2_MUX3_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX3_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX3_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX15_MASK) + +/*! @name WFE_B_STAGE2_MUX3_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX12_MASK) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX13_MASK) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX14_MASK) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX15_MASK) + +/*! @name WFE_B_STAGE2_MUX3_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_MASK) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_MASK) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_MASK) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_MASK) + +/*! @name WFE_B_STAGE2_MUX3_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_MASK) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_MASK) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_MASK) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_MASK) + +/*! @name WFE_B_STAGE2_MUX4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX4_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX4_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX4_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX16_MASK) +#define PXP_WFE_B_STAGE2_MUX4_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX4_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX4_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX17_MASK) +#define PXP_WFE_B_STAGE2_MUX4_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX4_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX4_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX18_MASK) +#define PXP_WFE_B_STAGE2_MUX4_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX4_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX4_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX19_MASK) + +/*! @name WFE_B_STAGE2_MUX4_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX16_MASK) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX17_MASK) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX18_MASK) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX19_MASK) + +/*! @name WFE_B_STAGE2_MUX4_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_MASK) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_MASK) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_MASK) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_MASK) + +/*! @name WFE_B_STAGE2_MUX4_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_MASK) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_MASK) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_MASK) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_MASK) + +/*! @name WFE_B_STAGE2_MUX5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX5_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX5_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX5_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX20_MASK) +#define PXP_WFE_B_STAGE2_MUX5_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX5_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX5_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX21_MASK) +#define PXP_WFE_B_STAGE2_MUX5_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX5_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX5_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX22_MASK) +#define PXP_WFE_B_STAGE2_MUX5_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX5_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX5_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX23_MASK) + +/*! @name WFE_B_STAGE2_MUX5_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX20_MASK) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX21_MASK) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX22_MASK) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX23_MASK) + +/*! @name WFE_B_STAGE2_MUX5_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_MASK) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_MASK) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_MASK) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_MASK) + +/*! @name WFE_B_STAGE2_MUX5_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_MASK) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_MASK) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_MASK) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_MASK) + +/*! @name WFE_B_STAGE2_MUX6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX6_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX6_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX6_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX24_MASK) +#define PXP_WFE_B_STAGE2_MUX6_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX6_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX6_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX25_MASK) +#define PXP_WFE_B_STAGE2_MUX6_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX6_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX6_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX26_MASK) +#define PXP_WFE_B_STAGE2_MUX6_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX6_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX6_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX27_MASK) + +/*! @name WFE_B_STAGE2_MUX6_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX24_MASK) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX25_MASK) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX26_MASK) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX27_MASK) + +/*! @name WFE_B_STAGE2_MUX6_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_MASK) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_MASK) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_MASK) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_MASK) + +/*! @name WFE_B_STAGE2_MUX6_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_MASK) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_MASK) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_MASK) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_MASK) + +/*! @name WFE_B_STAGE2_MUX7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX7_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX7_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX7_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX28_MASK) +#define PXP_WFE_B_STAGE2_MUX7_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX7_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX7_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX29_MASK) +#define PXP_WFE_B_STAGE2_MUX7_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX7_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX7_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX30_MASK) +#define PXP_WFE_B_STAGE2_MUX7_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX7_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX7_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX31_MASK) + +/*! @name WFE_B_STAGE2_MUX7_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX28_MASK) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX29_MASK) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX30_MASK) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX31_MASK) + +/*! @name WFE_B_STAGE2_MUX7_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_MASK) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_MASK) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_MASK) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_MASK) + +/*! @name WFE_B_STAGE2_MUX7_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_MASK) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_MASK) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_MASK) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_MASK) + +/*! @name WFE_B_STAGE2_MUX8 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX8_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX8_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX8_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX32_MASK) +#define PXP_WFE_B_STAGE2_MUX8_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX8_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX8_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX33_MASK) +#define PXP_WFE_B_STAGE2_MUX8_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX8_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX8_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX34_MASK) +#define PXP_WFE_B_STAGE2_MUX8_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX8_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX8_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX35_MASK) + +/*! @name WFE_B_STAGE2_MUX8_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX32_MASK) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX33_MASK) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX34_MASK) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX35_MASK) + +/*! @name WFE_B_STAGE2_MUX8_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_MASK) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_MASK) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_MASK) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_MASK) + +/*! @name WFE_B_STAGE2_MUX8_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_MASK) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_MASK) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_MASK) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_MASK) + +/*! @name WFE_B_STAGE2_MUX9 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX9_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX9_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX9_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX36_MASK) +#define PXP_WFE_B_STAGE2_MUX9_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX9_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX9_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX37_MASK) +#define PXP_WFE_B_STAGE2_MUX9_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX9_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX9_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX38_MASK) +#define PXP_WFE_B_STAGE2_MUX9_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX9_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX9_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX39_MASK) + +/*! @name WFE_B_STAGE2_MUX9_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX36_MASK) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX37_MASK) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX38_MASK) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX39_MASK) + +/*! @name WFE_B_STAGE2_MUX9_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_MASK) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_MASK) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_MASK) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_MASK) + +/*! @name WFE_B_STAGE2_MUX9_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_MASK) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_MASK) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_MASK) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_MASK) + +/*! @name WFE_B_STAGE2_MUX10 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX10_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX10_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX10_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX40_MASK) +#define PXP_WFE_B_STAGE2_MUX10_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX10_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX10_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX41_MASK) +#define PXP_WFE_B_STAGE2_MUX10_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX10_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX10_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX42_MASK) +#define PXP_WFE_B_STAGE2_MUX10_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX10_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX10_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX43_MASK) + +/*! @name WFE_B_STAGE2_MUX10_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX40_MASK) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX41_MASK) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX42_MASK) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX43_MASK) + +/*! @name WFE_B_STAGE2_MUX10_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_MASK) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_MASK) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_MASK) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_MASK) + +/*! @name WFE_B_STAGE2_MUX10_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_MASK) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_MASK) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_MASK) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_MASK) + +/*! @name WFE_B_STAGE2_MUX11 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX11_MUX44_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX11_MUX44_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX11_MUX44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX44_MASK) +#define PXP_WFE_B_STAGE2_MUX11_MUX45_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX11_MUX45_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX11_MUX45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX45_MASK) +#define PXP_WFE_B_STAGE2_MUX11_MUX46_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX11_MUX46_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX11_MUX46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX46_MASK) +#define PXP_WFE_B_STAGE2_MUX11_MUX47_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX11_MUX47_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX11_MUX47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX47_MASK) + +/*! @name WFE_B_STAGE2_MUX11_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX44_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX44_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX44_MASK) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX45_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX45_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX45_MASK) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX46_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX46_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX46_MASK) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX47_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX47_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX47_MASK) + +/*! @name WFE_B_STAGE2_MUX11_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_MASK) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_MASK) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_MASK) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_MASK) + +/*! @name WFE_B_STAGE2_MUX11_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_MASK) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_MASK) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_MASK) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_MASK) + +/*! @name WFE_B_STAGE2_MUX12 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX12_MUX48_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX12_MUX48_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX12_MUX48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_MUX48_MASK) + +/*! @name WFE_B_STAGE2_MUX12_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX12_SET_MUX48_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX12_SET_MUX48_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX12_SET_MUX48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_SET_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_SET_MUX48_MASK) + +/*! @name WFE_B_STAGE2_MUX12_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX12_CLR_MUX48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_MASK) + +/*! @name WFE_B_STAGE2_MUX12_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX12_TOG_MUX48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_MASK) + +/*! @name WFE_B_STAGE3_MUX0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX0_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX0_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX0_MASK) +#define PXP_WFE_B_STAGE3_MUX0_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX0_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX0_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX1_MASK) +#define PXP_WFE_B_STAGE3_MUX0_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX0_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX0_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX2_MASK) +#define PXP_WFE_B_STAGE3_MUX0_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX0_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX0_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX3_MASK) + +/*! @name WFE_B_STAGE3_MUX0_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX0_MASK) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX1_MASK) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX2_MASK) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX3_MASK) + +/*! @name WFE_B_STAGE3_MUX0_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_MASK) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_MASK) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_MASK) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_MASK) + +/*! @name WFE_B_STAGE3_MUX0_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_MASK) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_MASK) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_MASK) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_MASK) + +/*! @name WFE_B_STAGE3_MUX1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX1_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX1_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX1_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX4_MASK) +#define PXP_WFE_B_STAGE3_MUX1_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX1_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX1_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX5_MASK) +#define PXP_WFE_B_STAGE3_MUX1_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX1_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX1_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX6_MASK) +#define PXP_WFE_B_STAGE3_MUX1_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX1_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX1_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX7_MASK) + +/*! @name WFE_B_STAGE3_MUX1_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX4_MASK) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX5_MASK) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX6_MASK) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX7_MASK) + +/*! @name WFE_B_STAGE3_MUX1_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_MASK) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_MASK) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_MASK) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_MASK) + +/*! @name WFE_B_STAGE3_MUX1_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_MASK) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_MASK) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_MASK) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_MASK) + +/*! @name WFE_B_STAGE3_MUX2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX2_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX2_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX2_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX8_MASK) +#define PXP_WFE_B_STAGE3_MUX2_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX2_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX2_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX9_MASK) +#define PXP_WFE_B_STAGE3_MUX2_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX2_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX2_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX10_MASK) +#define PXP_WFE_B_STAGE3_MUX2_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX2_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX2_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX11_MASK) + +/*! @name WFE_B_STAGE3_MUX2_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX8_MASK) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX9_MASK) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX10_MASK) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX11_MASK) + +/*! @name WFE_B_STAGE3_MUX2_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_MASK) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_MASK) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_MASK) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_MASK) + +/*! @name WFE_B_STAGE3_MUX2_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_MASK) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_MASK) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_MASK) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_MASK) + +/*! @name WFE_B_STAGE3_MUX3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX3_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX3_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX3_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX12_MASK) +#define PXP_WFE_B_STAGE3_MUX3_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX3_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX3_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX13_MASK) +#define PXP_WFE_B_STAGE3_MUX3_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX3_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX3_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX14_MASK) +#define PXP_WFE_B_STAGE3_MUX3_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX3_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX3_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX15_MASK) + +/*! @name WFE_B_STAGE3_MUX3_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX12_MASK) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX13_MASK) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX14_MASK) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX15_MASK) + +/*! @name WFE_B_STAGE3_MUX3_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_MASK) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_MASK) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_MASK) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_MASK) + +/*! @name WFE_B_STAGE3_MUX3_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_MASK) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_MASK) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_MASK) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_MASK) + +/*! @name WFE_B_STAGE3_MUX4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX4_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX4_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX4_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX16_MASK) +#define PXP_WFE_B_STAGE3_MUX4_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX4_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX4_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX17_MASK) +#define PXP_WFE_B_STAGE3_MUX4_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX4_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX4_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX18_MASK) +#define PXP_WFE_B_STAGE3_MUX4_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX4_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX4_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX19_MASK) + +/*! @name WFE_B_STAGE3_MUX4_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX16_MASK) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX17_MASK) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX18_MASK) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX19_MASK) + +/*! @name WFE_B_STAGE3_MUX4_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_MASK) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_MASK) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_MASK) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_MASK) + +/*! @name WFE_B_STAGE3_MUX4_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_MASK) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_MASK) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_MASK) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_MASK) + +/*! @name WFE_B_STAGE3_MUX5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX5_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX5_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX5_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX20_MASK) +#define PXP_WFE_B_STAGE3_MUX5_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX5_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX5_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX21_MASK) +#define PXP_WFE_B_STAGE3_MUX5_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX5_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX5_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX22_MASK) +#define PXP_WFE_B_STAGE3_MUX5_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX5_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX5_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX23_MASK) + +/*! @name WFE_B_STAGE3_MUX5_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX20_MASK) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX21_MASK) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX22_MASK) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX23_MASK) + +/*! @name WFE_B_STAGE3_MUX5_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_MASK) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_MASK) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_MASK) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_MASK) + +/*! @name WFE_B_STAGE3_MUX5_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_MASK) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_MASK) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_MASK) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_MASK) + +/*! @name WFE_B_STAGE3_MUX6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX6_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX6_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX6_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX24_MASK) +#define PXP_WFE_B_STAGE3_MUX6_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX6_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX6_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX25_MASK) +#define PXP_WFE_B_STAGE3_MUX6_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX6_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX6_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX26_MASK) +#define PXP_WFE_B_STAGE3_MUX6_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX6_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX6_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX27_MASK) + +/*! @name WFE_B_STAGE3_MUX6_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX24_MASK) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX25_MASK) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX26_MASK) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX27_MASK) + +/*! @name WFE_B_STAGE3_MUX6_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_MASK) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_MASK) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_MASK) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_MASK) + +/*! @name WFE_B_STAGE3_MUX6_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_MASK) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_MASK) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_MASK) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_MASK) + +/*! @name WFE_B_STAGE3_MUX7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX7_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX7_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX7_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX28_MASK) +#define PXP_WFE_B_STAGE3_MUX7_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX7_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX7_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX29_MASK) +#define PXP_WFE_B_STAGE3_MUX7_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX7_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX7_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX30_MASK) +#define PXP_WFE_B_STAGE3_MUX7_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX7_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX7_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX31_MASK) + +/*! @name WFE_B_STAGE3_MUX7_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX28_MASK) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX29_MASK) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX30_MASK) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX31_MASK) + +/*! @name WFE_B_STAGE3_MUX7_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_MASK) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_MASK) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_MASK) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_MASK) + +/*! @name WFE_B_STAGE3_MUX7_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_MASK) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_MASK) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_MASK) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_MASK) + +/*! @name WFE_B_STAGE3_MUX8 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX8_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX8_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX8_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX32_MASK) +#define PXP_WFE_B_STAGE3_MUX8_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX8_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX8_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX33_MASK) +#define PXP_WFE_B_STAGE3_MUX8_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX8_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX8_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX34_MASK) +#define PXP_WFE_B_STAGE3_MUX8_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX8_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX8_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX35_MASK) + +/*! @name WFE_B_STAGE3_MUX8_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX32_MASK) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX33_MASK) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX34_MASK) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX35_MASK) + +/*! @name WFE_B_STAGE3_MUX8_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_MASK) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_MASK) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_MASK) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_MASK) + +/*! @name WFE_B_STAGE3_MUX8_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_MASK) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_MASK) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_MASK) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_MASK) + +/*! @name WFE_B_STAGE3_MUX9 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX9_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX9_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX9_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX36_MASK) +#define PXP_WFE_B_STAGE3_MUX9_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX9_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX9_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX37_MASK) +#define PXP_WFE_B_STAGE3_MUX9_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX9_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX9_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX38_MASK) +#define PXP_WFE_B_STAGE3_MUX9_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX9_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX9_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX39_MASK) + +/*! @name WFE_B_STAGE3_MUX9_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX36_MASK) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX37_MASK) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX38_MASK) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX39_MASK) + +/*! @name WFE_B_STAGE3_MUX9_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_MASK) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_MASK) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_MASK) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_MASK) + +/*! @name WFE_B_STAGE3_MUX9_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_MASK) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_MASK) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_MASK) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_MASK) + +/*! @name WFE_B_STAGE3_MUX10 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX10_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX10_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX10_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX40_MASK) +#define PXP_WFE_B_STAGE3_MUX10_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX10_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX10_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX41_MASK) +#define PXP_WFE_B_STAGE3_MUX10_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX10_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX10_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX42_MASK) +#define PXP_WFE_B_STAGE3_MUX10_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX10_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX10_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX43_MASK) + +/*! @name WFE_B_STAGE3_MUX10_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX40_MASK) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX41_MASK) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX42_MASK) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX43_MASK) + +/*! @name WFE_B_STAGE3_MUX10_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_MASK) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_MASK) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_MASK) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_MASK) + +/*! @name WFE_B_STAGE3_MUX10_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_MASK) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_MASK) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_MASK) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_MASK) + +/*! @name WFE_B_STAGE1_5X8_MASKS_0 - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x8 LUT. */ +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_MASK (0x1FU) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_SHIFT)) & PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_MASK) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_MASK (0x1F00U) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_SHIFT)) & PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_MASK) + +/*! @name WFE_B_STG1_5X1_OUT0 - This register defines the output values (new flag) for the 5x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_5X1_MASKS - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x1 LUT. */ +#define PXP_WFE_B_STG1_5X1_MASKS_MASK0_MASK (0x1FU) +#define PXP_WFE_B_STG1_5X1_MASKS_MASK0_SHIFT (0U) +#define PXP_WFE_B_STG1_5X1_MASKS_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_MASKS_MASK0_SHIFT)) & PXP_WFE_B_STG1_5X1_MASKS_MASK0_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_MASK) + +/*! @name WFE_B_STAGE2_5X6_MASKS_0 - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x6 LUT. */ +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_MASK (0x1FU) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_MASK) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_MASK (0x1F00U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_MASK) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_MASK (0x1F0000U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_MASK) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_MASK (0x1F000000U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_MASK) + +/*! @name WFE_B_STAGE2_5X6_ADDR_0 - Each Address specifies the MUX position in the MUX array. There is one MUXADDR per 5x6 LUT. */ +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_MASK) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_MASK) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_MASK) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_MASK) + +/*! @name WFE_B_STG2_5X1_OUT0 - This register defines the output values (new flag) for the 5x1 LUTs in stage 2. */ +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X1_OUT1 - This register defines the output values (new flag) for the 5x1 LUTs in stage 2. */ +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X1_OUT2 - This register defines the output values (new flag) for the 5x1 LUTs in stage 2. */ +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X1_OUT3 - This register defines the output values (new flag) for the 5x1 LUTs in stage 2. */ +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X1_MASKS - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x1 LUT. */ +#define PXP_WFE_B_STG2_5X1_MASKS_MASK0_MASK (0x1FU) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK0_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK0_MASK) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK1_MASK (0x1F00U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK1_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK1_MASK) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK2_MASK (0x1F0000U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK2_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK2_MASK) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK3_MASK (0x1F000000U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK3_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK3_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG3_F8X1_MASKS - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 8x1 LUT. */ +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK0_MASK (0xFFU) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK0_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK0_MASK) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK1_MASK (0xFF00U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK1_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK1_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK1_MASK) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK2_MASK (0xFF0000U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK2_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK2_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK2_MASK) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK3_MASK (0xFF000000U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK3_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK3_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK3_MASK) + +/*! @name ALU_B_CTRL - This register defines the control bits for the pxp alu sub-block. */ +#define PXP_ALU_B_CTRL_ENABLE_MASK (0x1U) +#define PXP_ALU_B_CTRL_ENABLE_SHIFT (0U) +#define PXP_ALU_B_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_ENABLE_MASK) +#define PXP_ALU_B_CTRL_START_MASK (0x10U) +#define PXP_ALU_B_CTRL_START_SHIFT (4U) +#define PXP_ALU_B_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_START_SHIFT)) & PXP_ALU_B_CTRL_START_MASK) +#define PXP_ALU_B_CTRL_SW_RESET_MASK (0x100U) +#define PXP_ALU_B_CTRL_SW_RESET_SHIFT (8U) +#define PXP_ALU_B_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_SW_RESET_MASK) +#define PXP_ALU_B_CTRL_BYPASS_MASK (0x1000U) +#define PXP_ALU_B_CTRL_BYPASS_SHIFT (12U) +#define PXP_ALU_B_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_BYPASS_MASK) +#define PXP_ALU_B_CTRL_DONE_IRQ_FLAG_MASK (0x10000U) +#define PXP_ALU_B_CTRL_DONE_IRQ_FLAG_SHIFT (16U) +#define PXP_ALU_B_CTRL_DONE_IRQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_DONE_IRQ_FLAG_MASK) +#define PXP_ALU_B_CTRL_DONE_IRQ_EN_MASK (0x100000U) +#define PXP_ALU_B_CTRL_DONE_IRQ_EN_SHIFT (20U) +#define PXP_ALU_B_CTRL_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_DONE_IRQ_EN_MASK) +#define PXP_ALU_B_CTRL_DONE_MASK (0x10000000U) +#define PXP_ALU_B_CTRL_DONE_SHIFT (28U) +#define PXP_ALU_B_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_DONE_SHIFT)) & PXP_ALU_B_CTRL_DONE_MASK) + +/*! @name ALU_B_CTRL_SET - This register defines the control bits for the pxp alu sub-block. */ +#define PXP_ALU_B_CTRL_SET_ENABLE_MASK (0x1U) +#define PXP_ALU_B_CTRL_SET_ENABLE_SHIFT (0U) +#define PXP_ALU_B_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_SET_ENABLE_MASK) +#define PXP_ALU_B_CTRL_SET_START_MASK (0x10U) +#define PXP_ALU_B_CTRL_SET_START_SHIFT (4U) +#define PXP_ALU_B_CTRL_SET_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_START_SHIFT)) & PXP_ALU_B_CTRL_SET_START_MASK) +#define PXP_ALU_B_CTRL_SET_SW_RESET_MASK (0x100U) +#define PXP_ALU_B_CTRL_SET_SW_RESET_SHIFT (8U) +#define PXP_ALU_B_CTRL_SET_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_SET_SW_RESET_MASK) +#define PXP_ALU_B_CTRL_SET_BYPASS_MASK (0x1000U) +#define PXP_ALU_B_CTRL_SET_BYPASS_SHIFT (12U) +#define PXP_ALU_B_CTRL_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_SET_BYPASS_MASK) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_MASK (0x10000U) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_SHIFT (16U) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_MASK) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_MASK (0x100000U) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_SHIFT (20U) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_MASK) +#define PXP_ALU_B_CTRL_SET_DONE_MASK (0x10000000U) +#define PXP_ALU_B_CTRL_SET_DONE_SHIFT (28U) +#define PXP_ALU_B_CTRL_SET_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_DONE_SHIFT)) & PXP_ALU_B_CTRL_SET_DONE_MASK) + +/*! @name ALU_B_CTRL_CLR - This register defines the control bits for the pxp alu sub-block. */ +#define PXP_ALU_B_CTRL_CLR_ENABLE_MASK (0x1U) +#define PXP_ALU_B_CTRL_CLR_ENABLE_SHIFT (0U) +#define PXP_ALU_B_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_CLR_ENABLE_MASK) +#define PXP_ALU_B_CTRL_CLR_START_MASK (0x10U) +#define PXP_ALU_B_CTRL_CLR_START_SHIFT (4U) +#define PXP_ALU_B_CTRL_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_START_SHIFT)) & PXP_ALU_B_CTRL_CLR_START_MASK) +#define PXP_ALU_B_CTRL_CLR_SW_RESET_MASK (0x100U) +#define PXP_ALU_B_CTRL_CLR_SW_RESET_SHIFT (8U) +#define PXP_ALU_B_CTRL_CLR_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_CLR_SW_RESET_MASK) +#define PXP_ALU_B_CTRL_CLR_BYPASS_MASK (0x1000U) +#define PXP_ALU_B_CTRL_CLR_BYPASS_SHIFT (12U) +#define PXP_ALU_B_CTRL_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_CLR_BYPASS_MASK) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_MASK (0x10000U) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_SHIFT (16U) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_MASK) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_MASK (0x100000U) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_SHIFT (20U) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_MASK) +#define PXP_ALU_B_CTRL_CLR_DONE_MASK (0x10000000U) +#define PXP_ALU_B_CTRL_CLR_DONE_SHIFT (28U) +#define PXP_ALU_B_CTRL_CLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_DONE_SHIFT)) & PXP_ALU_B_CTRL_CLR_DONE_MASK) + +/*! @name ALU_B_CTRL_TOG - This register defines the control bits for the pxp alu sub-block. */ +#define PXP_ALU_B_CTRL_TOG_ENABLE_MASK (0x1U) +#define PXP_ALU_B_CTRL_TOG_ENABLE_SHIFT (0U) +#define PXP_ALU_B_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_TOG_ENABLE_MASK) +#define PXP_ALU_B_CTRL_TOG_START_MASK (0x10U) +#define PXP_ALU_B_CTRL_TOG_START_SHIFT (4U) +#define PXP_ALU_B_CTRL_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_START_SHIFT)) & PXP_ALU_B_CTRL_TOG_START_MASK) +#define PXP_ALU_B_CTRL_TOG_SW_RESET_MASK (0x100U) +#define PXP_ALU_B_CTRL_TOG_SW_RESET_SHIFT (8U) +#define PXP_ALU_B_CTRL_TOG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_TOG_SW_RESET_MASK) +#define PXP_ALU_B_CTRL_TOG_BYPASS_MASK (0x1000U) +#define PXP_ALU_B_CTRL_TOG_BYPASS_SHIFT (12U) +#define PXP_ALU_B_CTRL_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_TOG_BYPASS_MASK) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_MASK (0x10000U) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_SHIFT (16U) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_MASK) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_MASK (0x100000U) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_SHIFT (20U) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_MASK) +#define PXP_ALU_B_CTRL_TOG_DONE_MASK (0x10000000U) +#define PXP_ALU_B_CTRL_TOG_DONE_SHIFT (28U) +#define PXP_ALU_B_CTRL_TOG_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_DONE_SHIFT)) & PXP_ALU_B_CTRL_TOG_DONE_MASK) + +/*! @name ALU_B_BUF_SIZE - This register defines the size of the buffer to be processed by the alu engine. */ +#define PXP_ALU_B_BUF_SIZE_BUF_WIDTH_MASK (0xFFFU) +#define PXP_ALU_B_BUF_SIZE_BUF_WIDTH_SHIFT (0U) +#define PXP_ALU_B_BUF_SIZE_BUF_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_BUF_SIZE_BUF_WIDTH_SHIFT)) & PXP_ALU_B_BUF_SIZE_BUF_WIDTH_MASK) +#define PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_MASK (0xFFF0000U) +#define PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_SHIFT (16U) +#define PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_SHIFT)) & PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_MASK) + +/*! @name ALU_B_INST_ENTRY - This register defines the Entry Address for the Instruction Memory of the ALU. */ +#define PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_MASK (0xFFFFU) +#define PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_SHIFT (0U) +#define PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_SHIFT)) & PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_MASK) + +/*! @name ALU_B_PARAM - This register defines the parameter used by SW running on ALU. */ +#define PXP_ALU_B_PARAM_PARAM0_MASK (0xFFU) +#define PXP_ALU_B_PARAM_PARAM0_SHIFT (0U) +#define PXP_ALU_B_PARAM_PARAM0(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_PARAM_PARAM0_SHIFT)) & PXP_ALU_B_PARAM_PARAM0_MASK) +#define PXP_ALU_B_PARAM_PARAM1_MASK (0xFF00U) +#define PXP_ALU_B_PARAM_PARAM1_SHIFT (8U) +#define PXP_ALU_B_PARAM_PARAM1(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_PARAM_PARAM1_SHIFT)) & PXP_ALU_B_PARAM_PARAM1_MASK) + +/*! @name ALU_B_CONFIG - This register defines the hw configuration options for the alu core. */ +#define PXP_ALU_B_CONFIG_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_ALU_B_CONFIG_BUF_ADDR_SHIFT (0U) +#define PXP_ALU_B_CONFIG_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CONFIG_BUF_ADDR_SHIFT)) & PXP_ALU_B_CONFIG_BUF_ADDR_MASK) + +/*! @name ALU_B_LUT_CONFIG - This register defines the hw configuration options for the LUT */ +#define PXP_ALU_B_LUT_CONFIG_EN_MASK (0x1U) +#define PXP_ALU_B_LUT_CONFIG_EN_SHIFT (0U) +#define PXP_ALU_B_LUT_CONFIG_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_EN_MASK) +#define PXP_ALU_B_LUT_CONFIG_MODE_MASK (0x30U) +#define PXP_ALU_B_LUT_CONFIG_MODE_SHIFT (4U) +#define PXP_ALU_B_LUT_CONFIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_MODE_MASK) + +/*! @name ALU_B_LUT_CONFIG_SET - This register defines the hw configuration options for the LUT */ +#define PXP_ALU_B_LUT_CONFIG_SET_EN_MASK (0x1U) +#define PXP_ALU_B_LUT_CONFIG_SET_EN_SHIFT (0U) +#define PXP_ALU_B_LUT_CONFIG_SET_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_SET_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_SET_EN_MASK) +#define PXP_ALU_B_LUT_CONFIG_SET_MODE_MASK (0x30U) +#define PXP_ALU_B_LUT_CONFIG_SET_MODE_SHIFT (4U) +#define PXP_ALU_B_LUT_CONFIG_SET_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_SET_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_SET_MODE_MASK) + +/*! @name ALU_B_LUT_CONFIG_CLR - This register defines the hw configuration options for the LUT */ +#define PXP_ALU_B_LUT_CONFIG_CLR_EN_MASK (0x1U) +#define PXP_ALU_B_LUT_CONFIG_CLR_EN_SHIFT (0U) +#define PXP_ALU_B_LUT_CONFIG_CLR_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_CLR_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_CLR_EN_MASK) +#define PXP_ALU_B_LUT_CONFIG_CLR_MODE_MASK (0x30U) +#define PXP_ALU_B_LUT_CONFIG_CLR_MODE_SHIFT (4U) +#define PXP_ALU_B_LUT_CONFIG_CLR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_CLR_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_CLR_MODE_MASK) + +/*! @name ALU_B_LUT_CONFIG_TOG - This register defines the hw configuration options for the LUT */ +#define PXP_ALU_B_LUT_CONFIG_TOG_EN_MASK (0x1U) +#define PXP_ALU_B_LUT_CONFIG_TOG_EN_SHIFT (0U) +#define PXP_ALU_B_LUT_CONFIG_TOG_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_TOG_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_TOG_EN_MASK) +#define PXP_ALU_B_LUT_CONFIG_TOG_MODE_MASK (0x30U) +#define PXP_ALU_B_LUT_CONFIG_TOG_MODE_SHIFT (4U) +#define PXP_ALU_B_LUT_CONFIG_TOG_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_TOG_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_TOG_MODE_MASK) + +/*! @name ALU_B_LUT_DATA0 - This register defines the lower 32-bit data for the LUT */ +#define PXP_ALU_B_LUT_DATA0_LUT_DATA_L_MASK (0xFFFFFFFFU) +#define PXP_ALU_B_LUT_DATA0_LUT_DATA_L_SHIFT (0U) +#define PXP_ALU_B_LUT_DATA0_LUT_DATA_L(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_DATA0_LUT_DATA_L_SHIFT)) & PXP_ALU_B_LUT_DATA0_LUT_DATA_L_MASK) + +/*! @name ALU_B_LUT_DATA1 - This register defines the higher 32-bit data for the LUT */ +#define PXP_ALU_B_LUT_DATA1_LUT_DATA_H_MASK (0xFFFFFFFFU) +#define PXP_ALU_B_LUT_DATA1_LUT_DATA_H_SHIFT (0U) +#define PXP_ALU_B_LUT_DATA1_LUT_DATA_H(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_DATA1_LUT_DATA_H_SHIFT)) & PXP_ALU_B_LUT_DATA1_LUT_DATA_H_MASK) + +/*! @name ALU_B_DBG - This register is used for debugging alu block */ +#define PXP_ALU_B_DBG_DEBUG_VALUE_MASK (0xFFFFFFU) +#define PXP_ALU_B_DBG_DEBUG_VALUE_SHIFT (0U) +#define PXP_ALU_B_DBG_DEBUG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_DBG_DEBUG_VALUE_SHIFT)) & PXP_ALU_B_DBG_DEBUG_VALUE_MASK) +#define PXP_ALU_B_DBG_DEBUG_SEL_MASK (0xFF000000U) +#define PXP_ALU_B_DBG_DEBUG_SEL_SHIFT (24U) +#define PXP_ALU_B_DBG_DEBUG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_DBG_DEBUG_SEL_SHIFT)) & PXP_ALU_B_DBG_DEBUG_SEL_MASK) + +/*! @name HIST_A_CTRL - Histogram Control Register. */ +#define PXP_HIST_A_CTRL_ENABLE_MASK (0x1U) +#define PXP_HIST_A_CTRL_ENABLE_SHIFT (0U) +#define PXP_HIST_A_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_ENABLE_SHIFT)) & PXP_HIST_A_CTRL_ENABLE_MASK) +#define PXP_HIST_A_CTRL_CLEAR_MASK (0x10U) +#define PXP_HIST_A_CTRL_CLEAR_SHIFT (4U) +#define PXP_HIST_A_CTRL_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_CLEAR_SHIFT)) & PXP_HIST_A_CTRL_CLEAR_MASK) +#define PXP_HIST_A_CTRL_STATUS_MASK (0x1F00U) +#define PXP_HIST_A_CTRL_STATUS_SHIFT (8U) +#define PXP_HIST_A_CTRL_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_STATUS_SHIFT)) & PXP_HIST_A_CTRL_STATUS_MASK) +#define PXP_HIST_A_CTRL_PIXEL_OFFSET_MASK (0x7F0000U) +#define PXP_HIST_A_CTRL_PIXEL_OFFSET_SHIFT (16U) +#define PXP_HIST_A_CTRL_PIXEL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_PIXEL_OFFSET_SHIFT)) & PXP_HIST_A_CTRL_PIXEL_OFFSET_MASK) +#define PXP_HIST_A_CTRL_PIXEL_WIDTH_MASK (0x7000000U) +#define PXP_HIST_A_CTRL_PIXEL_WIDTH_SHIFT (24U) +#define PXP_HIST_A_CTRL_PIXEL_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_PIXEL_WIDTH_SHIFT)) & PXP_HIST_A_CTRL_PIXEL_WIDTH_MASK) + +/*! @name HIST_A_MASK - Histogram Pixel Mask Register. */ +#define PXP_HIST_A_MASK_MASK_EN_MASK (0x1U) +#define PXP_HIST_A_MASK_MASK_EN_SHIFT (0U) +#define PXP_HIST_A_MASK_MASK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_EN_SHIFT)) & PXP_HIST_A_MASK_MASK_EN_MASK) +#define PXP_HIST_A_MASK_MASK_MODE_MASK (0x30U) +#define PXP_HIST_A_MASK_MASK_MODE_SHIFT (4U) +#define PXP_HIST_A_MASK_MASK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_MODE_SHIFT)) & PXP_HIST_A_MASK_MASK_MODE_MASK) +#define PXP_HIST_A_MASK_MASK_OFFSET_MASK (0x1FC0U) +#define PXP_HIST_A_MASK_MASK_OFFSET_SHIFT (6U) +#define PXP_HIST_A_MASK_MASK_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_OFFSET_SHIFT)) & PXP_HIST_A_MASK_MASK_OFFSET_MASK) +#define PXP_HIST_A_MASK_MASK_WIDTH_MASK (0xE000U) +#define PXP_HIST_A_MASK_MASK_WIDTH_SHIFT (13U) +#define PXP_HIST_A_MASK_MASK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_WIDTH_SHIFT)) & PXP_HIST_A_MASK_MASK_WIDTH_MASK) +#define PXP_HIST_A_MASK_MASK_VALUE0_MASK (0xFF0000U) +#define PXP_HIST_A_MASK_MASK_VALUE0_SHIFT (16U) +#define PXP_HIST_A_MASK_MASK_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_VALUE0_SHIFT)) & PXP_HIST_A_MASK_MASK_VALUE0_MASK) +#define PXP_HIST_A_MASK_MASK_VALUE1_MASK (0xFF000000U) +#define PXP_HIST_A_MASK_MASK_VALUE1_SHIFT (24U) +#define PXP_HIST_A_MASK_MASK_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_VALUE1_SHIFT)) & PXP_HIST_A_MASK_MASK_VALUE1_MASK) + +/*! @name HIST_A_BUF_SIZE - Histogram Pixel Buffer Size Register. */ +#define PXP_HIST_A_BUF_SIZE_WIDTH_MASK (0xFFFU) +#define PXP_HIST_A_BUF_SIZE_WIDTH_SHIFT (0U) +#define PXP_HIST_A_BUF_SIZE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_BUF_SIZE_WIDTH_SHIFT)) & PXP_HIST_A_BUF_SIZE_WIDTH_MASK) +#define PXP_HIST_A_BUF_SIZE_HEIGHT_MASK (0xFFF0000U) +#define PXP_HIST_A_BUF_SIZE_HEIGHT_SHIFT (16U) +#define PXP_HIST_A_BUF_SIZE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_BUF_SIZE_HEIGHT_SHIFT)) & PXP_HIST_A_BUF_SIZE_HEIGHT_MASK) + +/*! @name HIST_A_TOTAL_PIXEL - Total Number of Pixels Used by Histogram Engine. */ +#define PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_MASK (0xFFFFFFU) +#define PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT (0U) +#define PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT)) & PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_MASK) + +/*! @name HIST_A_ACTIVE_AREA_X - The X Coordinate Offset for Active Area. */ +#define PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_MASK (0xFFFU) +#define PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT (0U) +#define PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_MASK) +#define PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_MASK (0xFFF0000U) +#define PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT (16U) +#define PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_MASK) + +/*! @name HIST_A_ACTIVE_AREA_Y - The Y Coordinate Offset for Active Area. */ +#define PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK (0xFFFU) +#define PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT (0U) +#define PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK) +#define PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK (0xFFF0000U) +#define PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT (16U) +#define PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK) + +/*! @name HIST_A_RAW_STAT0 - Histogram Result Based on RAW Pixel Value. */ +#define PXP_HIST_A_RAW_STAT0_STAT0_MASK (0xFFFFFFFFU) +#define PXP_HIST_A_RAW_STAT0_STAT0_SHIFT (0U) +#define PXP_HIST_A_RAW_STAT0_STAT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_RAW_STAT0_STAT0_SHIFT)) & PXP_HIST_A_RAW_STAT0_STAT0_MASK) + +/*! @name HIST_A_RAW_STAT1 - Histogram Result Based on RAW Pixel Value. */ +#define PXP_HIST_A_RAW_STAT1_STAT1_MASK (0xFFFFFFFFU) +#define PXP_HIST_A_RAW_STAT1_STAT1_SHIFT (0U) +#define PXP_HIST_A_RAW_STAT1_STAT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_RAW_STAT1_STAT1_SHIFT)) & PXP_HIST_A_RAW_STAT1_STAT1_MASK) + +/*! @name HIST_B_CTRL - Histogram Control Register. */ +#define PXP_HIST_B_CTRL_ENABLE_MASK (0x1U) +#define PXP_HIST_B_CTRL_ENABLE_SHIFT (0U) +#define PXP_HIST_B_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_ENABLE_SHIFT)) & PXP_HIST_B_CTRL_ENABLE_MASK) +#define PXP_HIST_B_CTRL_CLEAR_MASK (0x10U) +#define PXP_HIST_B_CTRL_CLEAR_SHIFT (4U) +#define PXP_HIST_B_CTRL_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_CLEAR_SHIFT)) & PXP_HIST_B_CTRL_CLEAR_MASK) +#define PXP_HIST_B_CTRL_STATUS_MASK (0x1F00U) +#define PXP_HIST_B_CTRL_STATUS_SHIFT (8U) +#define PXP_HIST_B_CTRL_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_STATUS_SHIFT)) & PXP_HIST_B_CTRL_STATUS_MASK) +#define PXP_HIST_B_CTRL_PIXEL_OFFSET_MASK (0x7F0000U) +#define PXP_HIST_B_CTRL_PIXEL_OFFSET_SHIFT (16U) +#define PXP_HIST_B_CTRL_PIXEL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_PIXEL_OFFSET_SHIFT)) & PXP_HIST_B_CTRL_PIXEL_OFFSET_MASK) +#define PXP_HIST_B_CTRL_PIXEL_WIDTH_MASK (0x7000000U) +#define PXP_HIST_B_CTRL_PIXEL_WIDTH_SHIFT (24U) +#define PXP_HIST_B_CTRL_PIXEL_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_PIXEL_WIDTH_SHIFT)) & PXP_HIST_B_CTRL_PIXEL_WIDTH_MASK) + +/*! @name HIST_B_MASK - Histogram Pixel Mask Register. */ +#define PXP_HIST_B_MASK_MASK_EN_MASK (0x1U) +#define PXP_HIST_B_MASK_MASK_EN_SHIFT (0U) +#define PXP_HIST_B_MASK_MASK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_EN_SHIFT)) & PXP_HIST_B_MASK_MASK_EN_MASK) +#define PXP_HIST_B_MASK_MASK_MODE_MASK (0x30U) +#define PXP_HIST_B_MASK_MASK_MODE_SHIFT (4U) +#define PXP_HIST_B_MASK_MASK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_MODE_SHIFT)) & PXP_HIST_B_MASK_MASK_MODE_MASK) +#define PXP_HIST_B_MASK_MASK_OFFSET_MASK (0x1FC0U) +#define PXP_HIST_B_MASK_MASK_OFFSET_SHIFT (6U) +#define PXP_HIST_B_MASK_MASK_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_OFFSET_SHIFT)) & PXP_HIST_B_MASK_MASK_OFFSET_MASK) +#define PXP_HIST_B_MASK_MASK_WIDTH_MASK (0xE000U) +#define PXP_HIST_B_MASK_MASK_WIDTH_SHIFT (13U) +#define PXP_HIST_B_MASK_MASK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_WIDTH_SHIFT)) & PXP_HIST_B_MASK_MASK_WIDTH_MASK) +#define PXP_HIST_B_MASK_MASK_VALUE0_MASK (0xFF0000U) +#define PXP_HIST_B_MASK_MASK_VALUE0_SHIFT (16U) +#define PXP_HIST_B_MASK_MASK_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_VALUE0_SHIFT)) & PXP_HIST_B_MASK_MASK_VALUE0_MASK) +#define PXP_HIST_B_MASK_MASK_VALUE1_MASK (0xFF000000U) +#define PXP_HIST_B_MASK_MASK_VALUE1_SHIFT (24U) +#define PXP_HIST_B_MASK_MASK_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_VALUE1_SHIFT)) & PXP_HIST_B_MASK_MASK_VALUE1_MASK) + +/*! @name HIST_B_BUF_SIZE - Histogram Pixel Buffer Size Register. */ +#define PXP_HIST_B_BUF_SIZE_WIDTH_MASK (0xFFFU) +#define PXP_HIST_B_BUF_SIZE_WIDTH_SHIFT (0U) +#define PXP_HIST_B_BUF_SIZE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_BUF_SIZE_WIDTH_SHIFT)) & PXP_HIST_B_BUF_SIZE_WIDTH_MASK) +#define PXP_HIST_B_BUF_SIZE_HEIGHT_MASK (0xFFF0000U) +#define PXP_HIST_B_BUF_SIZE_HEIGHT_SHIFT (16U) +#define PXP_HIST_B_BUF_SIZE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_BUF_SIZE_HEIGHT_SHIFT)) & PXP_HIST_B_BUF_SIZE_HEIGHT_MASK) + +/*! @name HIST_B_TOTAL_PIXEL - Total Number of Pixels Used by Histogram Engine. */ +#define PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_MASK (0xFFFFFFU) +#define PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT (0U) +#define PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT)) & PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_MASK) + +/*! @name HIST_B_ACTIVE_AREA_X - The X Coordinate Offset for Active Area. */ +#define PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_MASK (0xFFFU) +#define PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT (0U) +#define PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_MASK) +#define PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_MASK (0xFFF0000U) +#define PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT (16U) +#define PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_MASK) + +/*! @name HIST_B_ACTIVE_AREA_Y - The Y Coordinate Offset for Active Area. */ +#define PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK (0xFFFU) +#define PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT (0U) +#define PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK) +#define PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK (0xFFF0000U) +#define PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT (16U) +#define PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK) + +/*! @name HIST_B_RAW_STAT0 - Histogram Result Based on RAW Pixel Value. */ +#define PXP_HIST_B_RAW_STAT0_STAT0_MASK (0xFFFFFFFFU) +#define PXP_HIST_B_RAW_STAT0_STAT0_SHIFT (0U) +#define PXP_HIST_B_RAW_STAT0_STAT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_RAW_STAT0_STAT0_SHIFT)) & PXP_HIST_B_RAW_STAT0_STAT0_MASK) + +/*! @name HIST_B_RAW_STAT1 - Histogram Result Based on RAW Pixel Value. */ +#define PXP_HIST_B_RAW_STAT1_STAT1_MASK (0xFFFFFFFFU) +#define PXP_HIST_B_RAW_STAT1_STAT1_SHIFT (0U) +#define PXP_HIST_B_RAW_STAT1_STAT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_RAW_STAT1_STAT1_SHIFT)) & PXP_HIST_B_RAW_STAT1_STAT1_MASK) + +/*! @name HIST2_PARAM - 2-level Histogram Parameter Register. */ +#define PXP_HIST2_PARAM_VALUE0_MASK (0x3FU) +#define PXP_HIST2_PARAM_VALUE0_SHIFT (0U) +#define PXP_HIST2_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST2_PARAM_VALUE0_SHIFT)) & PXP_HIST2_PARAM_VALUE0_MASK) +#define PXP_HIST2_PARAM_VALUE1_MASK (0x3F00U) +#define PXP_HIST2_PARAM_VALUE1_SHIFT (8U) +#define PXP_HIST2_PARAM_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST2_PARAM_VALUE1_SHIFT)) & PXP_HIST2_PARAM_VALUE1_MASK) + +/*! @name HIST4_PARAM - 4-level Histogram Parameter Register. */ +#define PXP_HIST4_PARAM_VALUE0_MASK (0x3FU) +#define PXP_HIST4_PARAM_VALUE0_SHIFT (0U) +#define PXP_HIST4_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE0_SHIFT)) & PXP_HIST4_PARAM_VALUE0_MASK) +#define PXP_HIST4_PARAM_VALUE1_MASK (0x3F00U) +#define PXP_HIST4_PARAM_VALUE1_SHIFT (8U) +#define PXP_HIST4_PARAM_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE1_SHIFT)) & PXP_HIST4_PARAM_VALUE1_MASK) +#define PXP_HIST4_PARAM_VALUE2_MASK (0x3F0000U) +#define PXP_HIST4_PARAM_VALUE2_SHIFT (16U) +#define PXP_HIST4_PARAM_VALUE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE2_SHIFT)) & PXP_HIST4_PARAM_VALUE2_MASK) +#define PXP_HIST4_PARAM_VALUE3_MASK (0x3F000000U) +#define PXP_HIST4_PARAM_VALUE3_SHIFT (24U) +#define PXP_HIST4_PARAM_VALUE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE3_SHIFT)) & PXP_HIST4_PARAM_VALUE3_MASK) + +/*! @name HIST8_PARAM0 - 8-level Histogram Parameter 0 Register. */ +#define PXP_HIST8_PARAM0_VALUE0_MASK (0x3FU) +#define PXP_HIST8_PARAM0_VALUE0_SHIFT (0U) +#define PXP_HIST8_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE0_SHIFT)) & PXP_HIST8_PARAM0_VALUE0_MASK) +#define PXP_HIST8_PARAM0_VALUE1_MASK (0x3F00U) +#define PXP_HIST8_PARAM0_VALUE1_SHIFT (8U) +#define PXP_HIST8_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE1_SHIFT)) & PXP_HIST8_PARAM0_VALUE1_MASK) +#define PXP_HIST8_PARAM0_VALUE2_MASK (0x3F0000U) +#define PXP_HIST8_PARAM0_VALUE2_SHIFT (16U) +#define PXP_HIST8_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE2_SHIFT)) & PXP_HIST8_PARAM0_VALUE2_MASK) +#define PXP_HIST8_PARAM0_VALUE3_MASK (0x3F000000U) +#define PXP_HIST8_PARAM0_VALUE3_SHIFT (24U) +#define PXP_HIST8_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE3_SHIFT)) & PXP_HIST8_PARAM0_VALUE3_MASK) + +/*! @name HIST8_PARAM1 - 8-level Histogram Parameter 1 Register. */ +#define PXP_HIST8_PARAM1_VALUE4_MASK (0x3FU) +#define PXP_HIST8_PARAM1_VALUE4_SHIFT (0U) +#define PXP_HIST8_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE4_SHIFT)) & PXP_HIST8_PARAM1_VALUE4_MASK) +#define PXP_HIST8_PARAM1_VALUE5_MASK (0x3F00U) +#define PXP_HIST8_PARAM1_VALUE5_SHIFT (8U) +#define PXP_HIST8_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE5_SHIFT)) & PXP_HIST8_PARAM1_VALUE5_MASK) +#define PXP_HIST8_PARAM1_VALUE6_MASK (0x3F0000U) +#define PXP_HIST8_PARAM1_VALUE6_SHIFT (16U) +#define PXP_HIST8_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE6_SHIFT)) & PXP_HIST8_PARAM1_VALUE6_MASK) +#define PXP_HIST8_PARAM1_VALUE7_MASK (0x3F000000U) +#define PXP_HIST8_PARAM1_VALUE7_SHIFT (24U) +#define PXP_HIST8_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE7_SHIFT)) & PXP_HIST8_PARAM1_VALUE7_MASK) + +/*! @name HIST16_PARAM0 - 16-level Histogram Parameter 0 Register. */ +#define PXP_HIST16_PARAM0_VALUE0_MASK (0x3FU) +#define PXP_HIST16_PARAM0_VALUE0_SHIFT (0U) +#define PXP_HIST16_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE0_SHIFT)) & PXP_HIST16_PARAM0_VALUE0_MASK) +#define PXP_HIST16_PARAM0_VALUE1_MASK (0x3F00U) +#define PXP_HIST16_PARAM0_VALUE1_SHIFT (8U) +#define PXP_HIST16_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE1_SHIFT)) & PXP_HIST16_PARAM0_VALUE1_MASK) +#define PXP_HIST16_PARAM0_VALUE2_MASK (0x3F0000U) +#define PXP_HIST16_PARAM0_VALUE2_SHIFT (16U) +#define PXP_HIST16_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE2_SHIFT)) & PXP_HIST16_PARAM0_VALUE2_MASK) +#define PXP_HIST16_PARAM0_VALUE3_MASK (0x3F000000U) +#define PXP_HIST16_PARAM0_VALUE3_SHIFT (24U) +#define PXP_HIST16_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE3_SHIFT)) & PXP_HIST16_PARAM0_VALUE3_MASK) + +/*! @name HIST16_PARAM1 - 16-level Histogram Parameter 1 Register. */ +#define PXP_HIST16_PARAM1_VALUE4_MASK (0x3FU) +#define PXP_HIST16_PARAM1_VALUE4_SHIFT (0U) +#define PXP_HIST16_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE4_SHIFT)) & PXP_HIST16_PARAM1_VALUE4_MASK) +#define PXP_HIST16_PARAM1_VALUE5_MASK (0x3F00U) +#define PXP_HIST16_PARAM1_VALUE5_SHIFT (8U) +#define PXP_HIST16_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE5_SHIFT)) & PXP_HIST16_PARAM1_VALUE5_MASK) +#define PXP_HIST16_PARAM1_VALUE6_MASK (0x3F0000U) +#define PXP_HIST16_PARAM1_VALUE6_SHIFT (16U) +#define PXP_HIST16_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE6_SHIFT)) & PXP_HIST16_PARAM1_VALUE6_MASK) +#define PXP_HIST16_PARAM1_VALUE7_MASK (0x3F000000U) +#define PXP_HIST16_PARAM1_VALUE7_SHIFT (24U) +#define PXP_HIST16_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE7_SHIFT)) & PXP_HIST16_PARAM1_VALUE7_MASK) + +/*! @name HIST16_PARAM2 - 16-level Histogram Parameter 2 Register. */ +#define PXP_HIST16_PARAM2_VALUE8_MASK (0x3FU) +#define PXP_HIST16_PARAM2_VALUE8_SHIFT (0U) +#define PXP_HIST16_PARAM2_VALUE8(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE8_SHIFT)) & PXP_HIST16_PARAM2_VALUE8_MASK) +#define PXP_HIST16_PARAM2_VALUE9_MASK (0x3F00U) +#define PXP_HIST16_PARAM2_VALUE9_SHIFT (8U) +#define PXP_HIST16_PARAM2_VALUE9(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE9_SHIFT)) & PXP_HIST16_PARAM2_VALUE9_MASK) +#define PXP_HIST16_PARAM2_VALUE10_MASK (0x3F0000U) +#define PXP_HIST16_PARAM2_VALUE10_SHIFT (16U) +#define PXP_HIST16_PARAM2_VALUE10(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE10_SHIFT)) & PXP_HIST16_PARAM2_VALUE10_MASK) +#define PXP_HIST16_PARAM2_VALUE11_MASK (0x3F000000U) +#define PXP_HIST16_PARAM2_VALUE11_SHIFT (24U) +#define PXP_HIST16_PARAM2_VALUE11(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE11_SHIFT)) & PXP_HIST16_PARAM2_VALUE11_MASK) + +/*! @name HIST16_PARAM3 - 16-level Histogram Parameter 3 Register. */ +#define PXP_HIST16_PARAM3_VALUE12_MASK (0x3FU) +#define PXP_HIST16_PARAM3_VALUE12_SHIFT (0U) +#define PXP_HIST16_PARAM3_VALUE12(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE12_SHIFT)) & PXP_HIST16_PARAM3_VALUE12_MASK) +#define PXP_HIST16_PARAM3_VALUE13_MASK (0x3F00U) +#define PXP_HIST16_PARAM3_VALUE13_SHIFT (8U) +#define PXP_HIST16_PARAM3_VALUE13(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE13_SHIFT)) & PXP_HIST16_PARAM3_VALUE13_MASK) +#define PXP_HIST16_PARAM3_VALUE14_MASK (0x3F0000U) +#define PXP_HIST16_PARAM3_VALUE14_SHIFT (16U) +#define PXP_HIST16_PARAM3_VALUE14(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE14_SHIFT)) & PXP_HIST16_PARAM3_VALUE14_MASK) +#define PXP_HIST16_PARAM3_VALUE15_MASK (0x3F000000U) +#define PXP_HIST16_PARAM3_VALUE15_SHIFT (24U) +#define PXP_HIST16_PARAM3_VALUE15(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE15_SHIFT)) & PXP_HIST16_PARAM3_VALUE15_MASK) + +/*! @name HIST32_PARAM0 - 32-level Histogram Parameter 0 Register. */ +#define PXP_HIST32_PARAM0_VALUE0_MASK (0x3FU) +#define PXP_HIST32_PARAM0_VALUE0_SHIFT (0U) +#define PXP_HIST32_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE0_SHIFT)) & PXP_HIST32_PARAM0_VALUE0_MASK) +#define PXP_HIST32_PARAM0_VALUE1_MASK (0x3F00U) +#define PXP_HIST32_PARAM0_VALUE1_SHIFT (8U) +#define PXP_HIST32_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE1_SHIFT)) & PXP_HIST32_PARAM0_VALUE1_MASK) +#define PXP_HIST32_PARAM0_VALUE2_MASK (0x3F0000U) +#define PXP_HIST32_PARAM0_VALUE2_SHIFT (16U) +#define PXP_HIST32_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE2_SHIFT)) & PXP_HIST32_PARAM0_VALUE2_MASK) +#define PXP_HIST32_PARAM0_VALUE3_MASK (0x3F000000U) +#define PXP_HIST32_PARAM0_VALUE3_SHIFT (24U) +#define PXP_HIST32_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE3_SHIFT)) & PXP_HIST32_PARAM0_VALUE3_MASK) + +/*! @name HIST32_PARAM1 - 32-level Histogram Parameter 1 Register. */ +#define PXP_HIST32_PARAM1_VALUE4_MASK (0x3FU) +#define PXP_HIST32_PARAM1_VALUE4_SHIFT (0U) +#define PXP_HIST32_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE4_SHIFT)) & PXP_HIST32_PARAM1_VALUE4_MASK) +#define PXP_HIST32_PARAM1_VALUE5_MASK (0x3F00U) +#define PXP_HIST32_PARAM1_VALUE5_SHIFT (8U) +#define PXP_HIST32_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE5_SHIFT)) & PXP_HIST32_PARAM1_VALUE5_MASK) +#define PXP_HIST32_PARAM1_VALUE6_MASK (0x3F0000U) +#define PXP_HIST32_PARAM1_VALUE6_SHIFT (16U) +#define PXP_HIST32_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE6_SHIFT)) & PXP_HIST32_PARAM1_VALUE6_MASK) +#define PXP_HIST32_PARAM1_VALUE7_MASK (0x3F000000U) +#define PXP_HIST32_PARAM1_VALUE7_SHIFT (24U) +#define PXP_HIST32_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE7_SHIFT)) & PXP_HIST32_PARAM1_VALUE7_MASK) + +/*! @name HIST32_PARAM2 - 32-level Histogram Parameter 2 Register. */ +#define PXP_HIST32_PARAM2_VALUE8_MASK (0x3FU) +#define PXP_HIST32_PARAM2_VALUE8_SHIFT (0U) +#define PXP_HIST32_PARAM2_VALUE8(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE8_SHIFT)) & PXP_HIST32_PARAM2_VALUE8_MASK) +#define PXP_HIST32_PARAM2_VALUE9_MASK (0x3F00U) +#define PXP_HIST32_PARAM2_VALUE9_SHIFT (8U) +#define PXP_HIST32_PARAM2_VALUE9(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE9_SHIFT)) & PXP_HIST32_PARAM2_VALUE9_MASK) +#define PXP_HIST32_PARAM2_VALUE10_MASK (0x3F0000U) +#define PXP_HIST32_PARAM2_VALUE10_SHIFT (16U) +#define PXP_HIST32_PARAM2_VALUE10(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE10_SHIFT)) & PXP_HIST32_PARAM2_VALUE10_MASK) +#define PXP_HIST32_PARAM2_VALUE11_MASK (0x3F000000U) +#define PXP_HIST32_PARAM2_VALUE11_SHIFT (24U) +#define PXP_HIST32_PARAM2_VALUE11(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE11_SHIFT)) & PXP_HIST32_PARAM2_VALUE11_MASK) + +/*! @name HIST32_PARAM3 - 32-level Histogram Parameter 3 Register. */ +#define PXP_HIST32_PARAM3_VALUE12_MASK (0x3FU) +#define PXP_HIST32_PARAM3_VALUE12_SHIFT (0U) +#define PXP_HIST32_PARAM3_VALUE12(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE12_SHIFT)) & PXP_HIST32_PARAM3_VALUE12_MASK) +#define PXP_HIST32_PARAM3_VALUE13_MASK (0x3F00U) +#define PXP_HIST32_PARAM3_VALUE13_SHIFT (8U) +#define PXP_HIST32_PARAM3_VALUE13(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE13_SHIFT)) & PXP_HIST32_PARAM3_VALUE13_MASK) +#define PXP_HIST32_PARAM3_VALUE14_MASK (0x3F0000U) +#define PXP_HIST32_PARAM3_VALUE14_SHIFT (16U) +#define PXP_HIST32_PARAM3_VALUE14(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE14_SHIFT)) & PXP_HIST32_PARAM3_VALUE14_MASK) +#define PXP_HIST32_PARAM3_VALUE15_MASK (0x3F000000U) +#define PXP_HIST32_PARAM3_VALUE15_SHIFT (24U) +#define PXP_HIST32_PARAM3_VALUE15(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE15_SHIFT)) & PXP_HIST32_PARAM3_VALUE15_MASK) + +/*! @name HIST32_PARAM4 - 32-level Histogram Parameter 0 Register. */ +#define PXP_HIST32_PARAM4_VALUE16_MASK (0x3FU) +#define PXP_HIST32_PARAM4_VALUE16_SHIFT (0U) +#define PXP_HIST32_PARAM4_VALUE16(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE16_SHIFT)) & PXP_HIST32_PARAM4_VALUE16_MASK) +#define PXP_HIST32_PARAM4_VALUE17_MASK (0x3F00U) +#define PXP_HIST32_PARAM4_VALUE17_SHIFT (8U) +#define PXP_HIST32_PARAM4_VALUE17(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE17_SHIFT)) & PXP_HIST32_PARAM4_VALUE17_MASK) +#define PXP_HIST32_PARAM4_VALUE18_MASK (0x3F0000U) +#define PXP_HIST32_PARAM4_VALUE18_SHIFT (16U) +#define PXP_HIST32_PARAM4_VALUE18(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE18_SHIFT)) & PXP_HIST32_PARAM4_VALUE18_MASK) +#define PXP_HIST32_PARAM4_VALUE19_MASK (0x3F000000U) +#define PXP_HIST32_PARAM4_VALUE19_SHIFT (24U) +#define PXP_HIST32_PARAM4_VALUE19(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE19_SHIFT)) & PXP_HIST32_PARAM4_VALUE19_MASK) + +/*! @name HIST32_PARAM5 - 32-level Histogram Parameter 1 Register. */ +#define PXP_HIST32_PARAM5_VALUE20_MASK (0x3FU) +#define PXP_HIST32_PARAM5_VALUE20_SHIFT (0U) +#define PXP_HIST32_PARAM5_VALUE20(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE20_SHIFT)) & PXP_HIST32_PARAM5_VALUE20_MASK) +#define PXP_HIST32_PARAM5_VALUE21_MASK (0x3F00U) +#define PXP_HIST32_PARAM5_VALUE21_SHIFT (8U) +#define PXP_HIST32_PARAM5_VALUE21(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE21_SHIFT)) & PXP_HIST32_PARAM5_VALUE21_MASK) +#define PXP_HIST32_PARAM5_VALUE22_MASK (0x3F0000U) +#define PXP_HIST32_PARAM5_VALUE22_SHIFT (16U) +#define PXP_HIST32_PARAM5_VALUE22(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE22_SHIFT)) & PXP_HIST32_PARAM5_VALUE22_MASK) +#define PXP_HIST32_PARAM5_VALUE23_MASK (0x3F000000U) +#define PXP_HIST32_PARAM5_VALUE23_SHIFT (24U) +#define PXP_HIST32_PARAM5_VALUE23(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE23_SHIFT)) & PXP_HIST32_PARAM5_VALUE23_MASK) + +/*! @name HIST32_PARAM6 - 32-level Histogram Parameter 2 Register. */ +#define PXP_HIST32_PARAM6_VALUE24_MASK (0x3FU) +#define PXP_HIST32_PARAM6_VALUE24_SHIFT (0U) +#define PXP_HIST32_PARAM6_VALUE24(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE24_SHIFT)) & PXP_HIST32_PARAM6_VALUE24_MASK) +#define PXP_HIST32_PARAM6_VALUE25_MASK (0x3F00U) +#define PXP_HIST32_PARAM6_VALUE25_SHIFT (8U) +#define PXP_HIST32_PARAM6_VALUE25(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE25_SHIFT)) & PXP_HIST32_PARAM6_VALUE25_MASK) +#define PXP_HIST32_PARAM6_VALUE26_MASK (0x3F0000U) +#define PXP_HIST32_PARAM6_VALUE26_SHIFT (16U) +#define PXP_HIST32_PARAM6_VALUE26(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE26_SHIFT)) & PXP_HIST32_PARAM6_VALUE26_MASK) +#define PXP_HIST32_PARAM6_VALUE27_MASK (0x3F000000U) +#define PXP_HIST32_PARAM6_VALUE27_SHIFT (24U) +#define PXP_HIST32_PARAM6_VALUE27(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE27_SHIFT)) & PXP_HIST32_PARAM6_VALUE27_MASK) + +/*! @name HIST32_PARAM7 - 32-level Histogram Parameter 3 Register. */ +#define PXP_HIST32_PARAM7_VALUE28_MASK (0x3FU) +#define PXP_HIST32_PARAM7_VALUE28_SHIFT (0U) +#define PXP_HIST32_PARAM7_VALUE28(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE28_SHIFT)) & PXP_HIST32_PARAM7_VALUE28_MASK) +#define PXP_HIST32_PARAM7_VALUE29_MASK (0x3F00U) +#define PXP_HIST32_PARAM7_VALUE29_SHIFT (8U) +#define PXP_HIST32_PARAM7_VALUE29(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE29_SHIFT)) & PXP_HIST32_PARAM7_VALUE29_MASK) +#define PXP_HIST32_PARAM7_VALUE30_MASK (0x3F0000U) +#define PXP_HIST32_PARAM7_VALUE30_SHIFT (16U) +#define PXP_HIST32_PARAM7_VALUE30(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE30_SHIFT)) & PXP_HIST32_PARAM7_VALUE30_MASK) +#define PXP_HIST32_PARAM7_VALUE31_MASK (0x3F000000U) +#define PXP_HIST32_PARAM7_VALUE31_SHIFT (24U) +#define PXP_HIST32_PARAM7_VALUE31(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE31_SHIFT)) & PXP_HIST32_PARAM7_VALUE31_MASK) + +/*! @name HANDSHAKE_READY_MUX0 - This register defines the pxp subblock handshake signals ready mux on top level. */ +#define PXP_HANDSHAKE_READY_MUX0_HSK0_MASK (0xFU) +#define PXP_HANDSHAKE_READY_MUX0_HSK0_SHIFT (0U) +#define PXP_HANDSHAKE_READY_MUX0_HSK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK0_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK0_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK1_MASK (0xF0U) +#define PXP_HANDSHAKE_READY_MUX0_HSK1_SHIFT (4U) +#define PXP_HANDSHAKE_READY_MUX0_HSK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK1_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK1_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK2_MASK (0xF00U) +#define PXP_HANDSHAKE_READY_MUX0_HSK2_SHIFT (8U) +#define PXP_HANDSHAKE_READY_MUX0_HSK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK2_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK2_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK3_MASK (0xF000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK3_SHIFT (12U) +#define PXP_HANDSHAKE_READY_MUX0_HSK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK3_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK3_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK4_MASK (0xF0000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK4_SHIFT (16U) +#define PXP_HANDSHAKE_READY_MUX0_HSK4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK4_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK4_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK5_MASK (0xF00000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK5_SHIFT (20U) +#define PXP_HANDSHAKE_READY_MUX0_HSK5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK5_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK5_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK6_MASK (0xF000000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK6_SHIFT (24U) +#define PXP_HANDSHAKE_READY_MUX0_HSK6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK6_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK6_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK7_MASK (0xF0000000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK7_SHIFT (28U) +#define PXP_HANDSHAKE_READY_MUX0_HSK7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK7_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK7_MASK) + +/*! @name HANDSHAKE_READY_MUX1 - This register defines the pxp subblock handshake signals ready mux on top level. */ +#define PXP_HANDSHAKE_READY_MUX1_HSK8_MASK (0xFU) +#define PXP_HANDSHAKE_READY_MUX1_HSK8_SHIFT (0U) +#define PXP_HANDSHAKE_READY_MUX1_HSK8(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK8_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK8_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK9_MASK (0xF0U) +#define PXP_HANDSHAKE_READY_MUX1_HSK9_SHIFT (4U) +#define PXP_HANDSHAKE_READY_MUX1_HSK9(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK9_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK9_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK10_MASK (0xF00U) +#define PXP_HANDSHAKE_READY_MUX1_HSK10_SHIFT (8U) +#define PXP_HANDSHAKE_READY_MUX1_HSK10(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK10_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK10_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK11_MASK (0xF000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK11_SHIFT (12U) +#define PXP_HANDSHAKE_READY_MUX1_HSK11(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK11_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK11_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK12_MASK (0xF0000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK12_SHIFT (16U) +#define PXP_HANDSHAKE_READY_MUX1_HSK12(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK12_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK12_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK13_MASK (0xF00000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK13_SHIFT (20U) +#define PXP_HANDSHAKE_READY_MUX1_HSK13(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK13_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK13_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK14_MASK (0xF000000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK14_SHIFT (24U) +#define PXP_HANDSHAKE_READY_MUX1_HSK14(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK14_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK14_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK15_MASK (0xF0000000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK15_SHIFT (28U) +#define PXP_HANDSHAKE_READY_MUX1_HSK15(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK15_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK15_MASK) + +/*! @name HANDSHAKE_DONE_MUX0 - This register defines the pxp subblock handshake signals done mux on top level. */ +#define PXP_HANDSHAKE_DONE_MUX0_HSK0_MASK (0xFU) +#define PXP_HANDSHAKE_DONE_MUX0_HSK0_SHIFT (0U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK0_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK0_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK1_MASK (0xF0U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK1_SHIFT (4U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK1_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK1_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK2_MASK (0xF00U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK2_SHIFT (8U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK2_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK2_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK3_MASK (0xF000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK3_SHIFT (12U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK3_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK3_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK4_MASK (0xF0000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK4_SHIFT (16U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK4_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK4_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK5_MASK (0xF00000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK5_SHIFT (20U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK5_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK5_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK6_MASK (0xF000000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK6_SHIFT (24U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK6_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK6_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK7_MASK (0xF0000000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK7_SHIFT (28U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK7_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK7_MASK) + +/*! @name HANDSHAKE_DONE_MUX1 - This register defines the pxp subblock handshake signals done mux on top level. */ +#define PXP_HANDSHAKE_DONE_MUX1_HSK8_MASK (0xFU) +#define PXP_HANDSHAKE_DONE_MUX1_HSK8_SHIFT (0U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK8(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK8_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK8_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK9_MASK (0xF0U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK9_SHIFT (4U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK9(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK9_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK9_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK10_MASK (0xF00U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK10_SHIFT (8U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK10(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK10_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK10_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK11_MASK (0xF000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK11_SHIFT (12U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK11(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK11_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK11_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK12_MASK (0xF0000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK12_SHIFT (16U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK12(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK12_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK12_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK13_MASK (0xF00000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK13_SHIFT (20U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK13(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK13_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK13_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK14_MASK (0xF000000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK14_SHIFT (24U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK14(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK14_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK14_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK15_MASK (0xF0000000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK15_SHIFT (28U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK15(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK15_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK15_MASK) + + +/*! + * @} + */ /* end of group PXP_Register_Masks */ + + +/* PXP - Peripheral instance base addresses */ +/** Peripheral PXP base address */ +#define PXP_BASE (0x21CC000u) +/** Peripheral PXP base pointer */ +#define PXP ((PXP_Type *)PXP_BASE) +/** Array initializer of PXP peripheral base addresses */ +#define PXP_BASE_ADDRS { PXP_BASE } +/** Array initializer of PXP peripheral base pointers */ +#define PXP_BASE_PTRS { PXP } +/** Interrupt vectors for the PXP peripheral type */ +#define PXP_IRQ0_IRQS { PXP_IRQ0_IRQn } +#define PXP_IRQ1_IRQS { PXP_IRQ1_IRQn } + +/*! + * @} + */ /* end of group PXP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- QuadSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer + * @{ + */ + +/** QuadSPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ + __IO uint32_t FLSHCR; /**< Flash Configuration Register, offset: 0xC */ + __IO uint32_t BUF0CR; /**< Buffer0 Configuration Register, offset: 0x10 */ + __IO uint32_t BUF1CR; /**< Buffer1 Configuration Register, offset: 0x14 */ + __IO uint32_t BUF2CR; /**< Buffer2 Configuration Register, offset: 0x18 */ + __IO uint32_t BUF3CR; /**< Buffer3 Configuration Register, offset: 0x1C */ + __IO uint32_t BFGENCR; /**< Buffer Generic Configuration Register, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ + __IO uint32_t BUF1IND; /**< Buffer1 Top Index Register, offset: 0x34 */ + __IO uint32_t BUF2IND; /**< Buffer2 Top Index Register, offset: 0x38 */ + uint8_t RESERVED_2[196]; + __IO uint32_t SFAR; /**< Serial Flash Address Register, offset: 0x100 */ + uint8_t RESERVED_3[4]; + __IO uint32_t SMPR; /**< Sampling Register, offset: 0x108 */ + __I uint32_t RBSR; /**< RX Buffer Status Register, offset: 0x10C */ + __IO uint32_t RBCT; /**< RX Buffer Control Register, offset: 0x110 */ + uint8_t RESERVED_4[60]; + __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ + __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ + uint8_t RESERVED_5[4]; + __I uint32_t SR; /**< Status Register, offset: 0x15C */ + __IO uint32_t FR; /**< Flag Register, offset: 0x160 */ + __IO uint32_t RSER; /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */ + __I uint32_t SPNDST; /**< Sequence Suspend Status Register, offset: 0x168 */ + __IO uint32_t SPTRCLR; /**< Sequence Pointer Clear Register, offset: 0x16C */ + uint8_t RESERVED_6[16]; + __IO uint32_t SFA1AD; /**< Serial Flash A1 Top Address, offset: 0x180 */ + __IO uint32_t SFA2AD; /**< Serial Flash A2 Top Address, offset: 0x184 */ + __IO uint32_t SFB1AD; /**< Serial Flash B1Top Address, offset: 0x188 */ + __IO uint32_t SFB2AD; /**< Serial Flash B2Top Address, offset: 0x18C */ + uint8_t RESERVED_7[112]; + __IO uint32_t RBDR[32]; /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_8[128]; + __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x300 */ + __IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x304 */ + uint8_t RESERVED_9[8]; + __IO uint32_t LUT[64]; /**< Look-up Table register, array offset: 0x310, array step: 0x4 */ +} QuadSPI_Type; + +/* ---------------------------------------------------------------------------- + -- QuadSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +#define QuadSPI_MCR_SWRSTSD_MASK (0x1U) +#define QuadSPI_MCR_SWRSTSD_SHIFT (0U) +#define QuadSPI_MCR_SWRSTSD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTSD_SHIFT)) & QuadSPI_MCR_SWRSTSD_MASK) +#define QuadSPI_MCR_SWRSTHD_MASK (0x2U) +#define QuadSPI_MCR_SWRSTHD_SHIFT (1U) +#define QuadSPI_MCR_SWRSTHD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK) +#define QuadSPI_MCR_END_CFG_MASK (0xCU) +#define QuadSPI_MCR_END_CFG_SHIFT (2U) +#define QuadSPI_MCR_END_CFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_END_CFG_SHIFT)) & QuadSPI_MCR_END_CFG_MASK) +#define QuadSPI_MCR_DQS_EN_MASK (0x40U) +#define QuadSPI_MCR_DQS_EN_SHIFT (6U) +#define QuadSPI_MCR_DQS_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_EN_SHIFT)) & QuadSPI_MCR_DQS_EN_MASK) +#define QuadSPI_MCR_DDR_EN_MASK (0x80U) +#define QuadSPI_MCR_DDR_EN_SHIFT (7U) +#define QuadSPI_MCR_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DDR_EN_SHIFT)) & QuadSPI_MCR_DDR_EN_MASK) +#define QuadSPI_MCR_CLR_RXF_MASK (0x400U) +#define QuadSPI_MCR_CLR_RXF_SHIFT (10U) +#define QuadSPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_RXF_SHIFT)) & QuadSPI_MCR_CLR_RXF_MASK) +#define QuadSPI_MCR_CLR_TXF_MASK (0x800U) +#define QuadSPI_MCR_CLR_TXF_SHIFT (11U) +#define QuadSPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_TXF_SHIFT)) & QuadSPI_MCR_CLR_TXF_MASK) +#define QuadSPI_MCR_MDIS_MASK (0x4000U) +#define QuadSPI_MCR_MDIS_SHIFT (14U) +#define QuadSPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_MDIS_SHIFT)) & QuadSPI_MCR_MDIS_MASK) +#define QuadSPI_MCR_DQS_LOOPBACK_EN_MASK (0x1000000U) +#define QuadSPI_MCR_DQS_LOOPBACK_EN_SHIFT (24U) +#define QuadSPI_MCR_DQS_LOOPBACK_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_LOOPBACK_EN_SHIFT)) & QuadSPI_MCR_DQS_LOOPBACK_EN_MASK) +#define QuadSPI_MCR_DQS_PHASE_EN_MASK (0x40000000U) +#define QuadSPI_MCR_DQS_PHASE_EN_SHIFT (30U) +#define QuadSPI_MCR_DQS_PHASE_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_PHASE_EN_SHIFT)) & QuadSPI_MCR_DQS_PHASE_EN_MASK) + +/*! @name IPCR - IP Configuration Register */ +#define QuadSPI_IPCR_IDATSZ_MASK (0xFFFFU) +#define QuadSPI_IPCR_IDATSZ_SHIFT (0U) +#define QuadSPI_IPCR_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_IDATSZ_SHIFT)) & QuadSPI_IPCR_IDATSZ_MASK) +#define QuadSPI_IPCR_PAR_EN_MASK (0x10000U) +#define QuadSPI_IPCR_PAR_EN_SHIFT (16U) +#define QuadSPI_IPCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_PAR_EN_SHIFT)) & QuadSPI_IPCR_PAR_EN_MASK) +#define QuadSPI_IPCR_SEQID_MASK (0xF000000U) +#define QuadSPI_IPCR_SEQID_SHIFT (24U) +#define QuadSPI_IPCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK) + +/*! @name FLSHCR - Flash Configuration Register */ +#define QuadSPI_FLSHCR_TCSS_MASK (0xFU) +#define QuadSPI_FLSHCR_TCSS_SHIFT (0U) +#define QuadSPI_FLSHCR_TCSS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSS_SHIFT)) & QuadSPI_FLSHCR_TCSS_MASK) +#define QuadSPI_FLSHCR_TCSH_MASK (0xF00U) +#define QuadSPI_FLSHCR_TCSH_SHIFT (8U) +#define QuadSPI_FLSHCR_TCSH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSH_SHIFT)) & QuadSPI_FLSHCR_TCSH_MASK) + +/*! @name BUF0CR - Buffer0 Configuration Register */ +#define QuadSPI_BUF0CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF0CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF0CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_MSTRID_SHIFT)) & QuadSPI_BUF0CR_MSTRID_MASK) +#define QuadSPI_BUF0CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF0CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF0CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_ADATSZ_SHIFT)) & QuadSPI_BUF0CR_ADATSZ_MASK) +#define QuadSPI_BUF0CR_HP_EN_MASK (0x80000000U) +#define QuadSPI_BUF0CR_HP_EN_SHIFT (31U) +#define QuadSPI_BUF0CR_HP_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_HP_EN_SHIFT)) & QuadSPI_BUF0CR_HP_EN_MASK) + +/*! @name BUF1CR - Buffer1 Configuration Register */ +#define QuadSPI_BUF1CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF1CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF1CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_MSTRID_SHIFT)) & QuadSPI_BUF1CR_MSTRID_MASK) +#define QuadSPI_BUF1CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF1CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF1CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_ADATSZ_SHIFT)) & QuadSPI_BUF1CR_ADATSZ_MASK) + +/*! @name BUF2CR - Buffer2 Configuration Register */ +#define QuadSPI_BUF2CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF2CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF2CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_MSTRID_SHIFT)) & QuadSPI_BUF2CR_MSTRID_MASK) +#define QuadSPI_BUF2CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF2CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF2CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_ADATSZ_SHIFT)) & QuadSPI_BUF2CR_ADATSZ_MASK) + +/*! @name BUF3CR - Buffer3 Configuration Register */ +#define QuadSPI_BUF3CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF3CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF3CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_MSTRID_SHIFT)) & QuadSPI_BUF3CR_MSTRID_MASK) +#define QuadSPI_BUF3CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF3CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF3CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ADATSZ_SHIFT)) & QuadSPI_BUF3CR_ADATSZ_MASK) +#define QuadSPI_BUF3CR_ALLMST_MASK (0x80000000U) +#define QuadSPI_BUF3CR_ALLMST_SHIFT (31U) +#define QuadSPI_BUF3CR_ALLMST(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ALLMST_SHIFT)) & QuadSPI_BUF3CR_ALLMST_MASK) + +/*! @name BFGENCR - Buffer Generic Configuration Register */ +#define QuadSPI_BFGENCR_SEQID_MASK (0xF000U) +#define QuadSPI_BFGENCR_SEQID_SHIFT (12U) +#define QuadSPI_BFGENCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_SEQID_SHIFT)) & QuadSPI_BFGENCR_SEQID_MASK) +#define QuadSPI_BFGENCR_PAR_EN_MASK (0x10000U) +#define QuadSPI_BFGENCR_PAR_EN_SHIFT (16U) +#define QuadSPI_BFGENCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_PAR_EN_SHIFT)) & QuadSPI_BFGENCR_PAR_EN_MASK) + +/*! @name BUF0IND - Buffer0 Top Index Register */ +#define QuadSPI_BUF0IND_TPINDX0_MASK (0xFFFFFFF8U) +#define QuadSPI_BUF0IND_TPINDX0_SHIFT (3U) +#define QuadSPI_BUF0IND_TPINDX0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0IND_TPINDX0_SHIFT)) & QuadSPI_BUF0IND_TPINDX0_MASK) + +/*! @name BUF1IND - Buffer1 Top Index Register */ +#define QuadSPI_BUF1IND_TPINDX1_MASK (0xFFFFFFF8U) +#define QuadSPI_BUF1IND_TPINDX1_SHIFT (3U) +#define QuadSPI_BUF1IND_TPINDX1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1IND_TPINDX1_SHIFT)) & QuadSPI_BUF1IND_TPINDX1_MASK) + +/*! @name BUF2IND - Buffer2 Top Index Register */ +#define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) +#define QuadSPI_BUF2IND_TPINDX2_SHIFT (3U) +#define QuadSPI_BUF2IND_TPINDX2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK) + +/*! @name SFAR - Serial Flash Address Register */ +#define QuadSPI_SFAR_SFADR_MASK (0xFFFFFFFFU) +#define QuadSPI_SFAR_SFADR_SHIFT (0U) +#define QuadSPI_SFAR_SFADR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFAR_SFADR_SHIFT)) & QuadSPI_SFAR_SFADR_MASK) + +/*! @name SMPR - Sampling Register */ +#define QuadSPI_SMPR_SDRSMP_MASK (0x60U) +#define QuadSPI_SMPR_SDRSMP_SHIFT (5U) +#define QuadSPI_SMPR_SDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_SDRSMP_SHIFT)) & QuadSPI_SMPR_SDRSMP_MASK) +#define QuadSPI_SMPR_DDRSMP_MASK (0x70000U) +#define QuadSPI_SMPR_DDRSMP_SHIFT (16U) +#define QuadSPI_SMPR_DDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_DDRSMP_SHIFT)) & QuadSPI_SMPR_DDRSMP_MASK) + +/*! @name RBSR - RX Buffer Status Register */ +#define QuadSPI_RBSR_RDBFL_MASK (0x3F00U) +#define QuadSPI_RBSR_RDBFL_SHIFT (8U) +#define QuadSPI_RBSR_RDBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDBFL_SHIFT)) & QuadSPI_RBSR_RDBFL_MASK) +#define QuadSPI_RBSR_RDCTR_MASK (0xFFFF0000U) +#define QuadSPI_RBSR_RDCTR_SHIFT (16U) +#define QuadSPI_RBSR_RDCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDCTR_SHIFT)) & QuadSPI_RBSR_RDCTR_MASK) + +/*! @name RBCT - RX Buffer Control Register */ +#define QuadSPI_RBCT_WMRK_MASK (0x1FU) +#define QuadSPI_RBCT_WMRK_SHIFT (0U) +#define QuadSPI_RBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_WMRK_SHIFT)) & QuadSPI_RBCT_WMRK_MASK) +#define QuadSPI_RBCT_RXBRD_MASK (0x100U) +#define QuadSPI_RBCT_RXBRD_SHIFT (8U) +#define QuadSPI_RBCT_RXBRD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_RXBRD_SHIFT)) & QuadSPI_RBCT_RXBRD_MASK) + +/*! @name TBSR - TX Buffer Status Register */ +#define QuadSPI_TBSR_TRBFL_MASK (0x1F00U) +#define QuadSPI_TBSR_TRBFL_SHIFT (8U) +#define QuadSPI_TBSR_TRBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRBFL_SHIFT)) & QuadSPI_TBSR_TRBFL_MASK) +#define QuadSPI_TBSR_TRCTR_MASK (0xFFFF0000U) +#define QuadSPI_TBSR_TRCTR_SHIFT (16U) +#define QuadSPI_TBSR_TRCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRCTR_SHIFT)) & QuadSPI_TBSR_TRCTR_MASK) + +/*! @name TBDR - TX Buffer Data Register */ +#define QuadSPI_TBDR_TXDATA_MASK (0xFFFFFFFFU) +#define QuadSPI_TBDR_TXDATA_SHIFT (0U) +#define QuadSPI_TBDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBDR_TXDATA_SHIFT)) & QuadSPI_TBDR_TXDATA_MASK) + +/*! @name SR - Status Register */ +#define QuadSPI_SR_BUSY_MASK (0x1U) +#define QuadSPI_SR_BUSY_SHIFT (0U) +#define QuadSPI_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_BUSY_SHIFT)) & QuadSPI_SR_BUSY_MASK) +#define QuadSPI_SR_IP_ACC_MASK (0x2U) +#define QuadSPI_SR_IP_ACC_SHIFT (1U) +#define QuadSPI_SR_IP_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_IP_ACC_SHIFT)) & QuadSPI_SR_IP_ACC_MASK) +#define QuadSPI_SR_AHB_ACC_MASK (0x4U) +#define QuadSPI_SR_AHB_ACC_SHIFT (2U) +#define QuadSPI_SR_AHB_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB_ACC_SHIFT)) & QuadSPI_SR_AHB_ACC_MASK) +#define QuadSPI_SR_AHBGNT_MASK (0x20U) +#define QuadSPI_SR_AHBGNT_SHIFT (5U) +#define QuadSPI_SR_AHBGNT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBGNT_SHIFT)) & QuadSPI_SR_AHBGNT_MASK) +#define QuadSPI_SR_AHBTRN_MASK (0x40U) +#define QuadSPI_SR_AHBTRN_SHIFT (6U) +#define QuadSPI_SR_AHBTRN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBTRN_SHIFT)) & QuadSPI_SR_AHBTRN_MASK) +#define QuadSPI_SR_AHB0NE_MASK (0x80U) +#define QuadSPI_SR_AHB0NE_SHIFT (7U) +#define QuadSPI_SR_AHB0NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK) +#define QuadSPI_SR_AHB1NE_MASK (0x100U) +#define QuadSPI_SR_AHB1NE_SHIFT (8U) +#define QuadSPI_SR_AHB1NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1NE_SHIFT)) & QuadSPI_SR_AHB1NE_MASK) +#define QuadSPI_SR_AHB2NE_MASK (0x200U) +#define QuadSPI_SR_AHB2NE_SHIFT (9U) +#define QuadSPI_SR_AHB2NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2NE_SHIFT)) & QuadSPI_SR_AHB2NE_MASK) +#define QuadSPI_SR_AHB3NE_MASK (0x400U) +#define QuadSPI_SR_AHB3NE_SHIFT (10U) +#define QuadSPI_SR_AHB3NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3NE_SHIFT)) & QuadSPI_SR_AHB3NE_MASK) +#define QuadSPI_SR_AHB0FUL_MASK (0x800U) +#define QuadSPI_SR_AHB0FUL_SHIFT (11U) +#define QuadSPI_SR_AHB0FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK) +#define QuadSPI_SR_AHB1FUL_MASK (0x1000U) +#define QuadSPI_SR_AHB1FUL_SHIFT (12U) +#define QuadSPI_SR_AHB1FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1FUL_SHIFT)) & QuadSPI_SR_AHB1FUL_MASK) +#define QuadSPI_SR_AHB2FUL_MASK (0x2000U) +#define QuadSPI_SR_AHB2FUL_SHIFT (13U) +#define QuadSPI_SR_AHB2FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2FUL_SHIFT)) & QuadSPI_SR_AHB2FUL_MASK) +#define QuadSPI_SR_AHB3FUL_MASK (0x4000U) +#define QuadSPI_SR_AHB3FUL_SHIFT (14U) +#define QuadSPI_SR_AHB3FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3FUL_SHIFT)) & QuadSPI_SR_AHB3FUL_MASK) +#define QuadSPI_SR_RXWE_MASK (0x10000U) +#define QuadSPI_SR_RXWE_SHIFT (16U) +#define QuadSPI_SR_RXWE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK) +#define QuadSPI_SR_RXFULL_MASK (0x80000U) +#define QuadSPI_SR_RXFULL_SHIFT (19U) +#define QuadSPI_SR_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK) +#define QuadSPI_SR_RXDMA_MASK (0x800000U) +#define QuadSPI_SR_RXDMA_SHIFT (23U) +#define QuadSPI_SR_RXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXDMA_SHIFT)) & QuadSPI_SR_RXDMA_MASK) +#define QuadSPI_SR_TXEDA_MASK (0x1000000U) +#define QuadSPI_SR_TXEDA_SHIFT (24U) +#define QuadSPI_SR_TXEDA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXEDA_SHIFT)) & QuadSPI_SR_TXEDA_MASK) +#define QuadSPI_SR_TXFULL_MASK (0x8000000U) +#define QuadSPI_SR_TXFULL_SHIFT (27U) +#define QuadSPI_SR_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK) +#define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) +#define QuadSPI_SR_DLPSMP_SHIFT (29U) +#define QuadSPI_SR_DLPSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK) + +/*! @name FR - Flag Register */ +#define QuadSPI_FR_TFF_MASK (0x1U) +#define QuadSPI_FR_TFF_SHIFT (0U) +#define QuadSPI_FR_TFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TFF_SHIFT)) & QuadSPI_FR_TFF_MASK) +#define QuadSPI_FR_IPGEF_MASK (0x10U) +#define QuadSPI_FR_IPGEF_SHIFT (4U) +#define QuadSPI_FR_IPGEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPGEF_SHIFT)) & QuadSPI_FR_IPGEF_MASK) +#define QuadSPI_FR_IPIEF_MASK (0x40U) +#define QuadSPI_FR_IPIEF_SHIFT (6U) +#define QuadSPI_FR_IPIEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPIEF_SHIFT)) & QuadSPI_FR_IPIEF_MASK) +#define QuadSPI_FR_IPAEF_MASK (0x80U) +#define QuadSPI_FR_IPAEF_SHIFT (7U) +#define QuadSPI_FR_IPAEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPAEF_SHIFT)) & QuadSPI_FR_IPAEF_MASK) +#define QuadSPI_FR_IUEF_MASK (0x800U) +#define QuadSPI_FR_IUEF_SHIFT (11U) +#define QuadSPI_FR_IUEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IUEF_SHIFT)) & QuadSPI_FR_IUEF_MASK) +#define QuadSPI_FR_ABOF_MASK (0x1000U) +#define QuadSPI_FR_ABOF_SHIFT (12U) +#define QuadSPI_FR_ABOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABOF_SHIFT)) & QuadSPI_FR_ABOF_MASK) +#define QuadSPI_FR_ABSEF_MASK (0x8000U) +#define QuadSPI_FR_ABSEF_SHIFT (15U) +#define QuadSPI_FR_ABSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK) +#define QuadSPI_FR_RBDF_MASK (0x10000U) +#define QuadSPI_FR_RBDF_SHIFT (16U) +#define QuadSPI_FR_RBDF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBDF_SHIFT)) & QuadSPI_FR_RBDF_MASK) +#define QuadSPI_FR_RBOF_MASK (0x20000U) +#define QuadSPI_FR_RBOF_SHIFT (17U) +#define QuadSPI_FR_RBOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBOF_SHIFT)) & QuadSPI_FR_RBOF_MASK) +#define QuadSPI_FR_ILLINE_MASK (0x800000U) +#define QuadSPI_FR_ILLINE_SHIFT (23U) +#define QuadSPI_FR_ILLINE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK) +#define QuadSPI_FR_TBUF_MASK (0x4000000U) +#define QuadSPI_FR_TBUF_SHIFT (26U) +#define QuadSPI_FR_TBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBUF_SHIFT)) & QuadSPI_FR_TBUF_MASK) +#define QuadSPI_FR_TBFF_MASK (0x8000000U) +#define QuadSPI_FR_TBFF_SHIFT (27U) +#define QuadSPI_FR_TBFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBFF_SHIFT)) & QuadSPI_FR_TBFF_MASK) +#define QuadSPI_FR_DLPFF_MASK (0x80000000U) +#define QuadSPI_FR_DLPFF_SHIFT (31U) +#define QuadSPI_FR_DLPFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_DLPFF_SHIFT)) & QuadSPI_FR_DLPFF_MASK) + +/*! @name RSER - Interrupt and DMA Request Select and Enable Register */ +#define QuadSPI_RSER_TFIE_MASK (0x1U) +#define QuadSPI_RSER_TFIE_SHIFT (0U) +#define QuadSPI_RSER_TFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TFIE_SHIFT)) & QuadSPI_RSER_TFIE_MASK) +#define QuadSPI_RSER_IPGEIE_MASK (0x10U) +#define QuadSPI_RSER_IPGEIE_SHIFT (4U) +#define QuadSPI_RSER_IPGEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPGEIE_SHIFT)) & QuadSPI_RSER_IPGEIE_MASK) +#define QuadSPI_RSER_IPIEIE_MASK (0x40U) +#define QuadSPI_RSER_IPIEIE_SHIFT (6U) +#define QuadSPI_RSER_IPIEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPIEIE_SHIFT)) & QuadSPI_RSER_IPIEIE_MASK) +#define QuadSPI_RSER_IPAEIE_MASK (0x80U) +#define QuadSPI_RSER_IPAEIE_SHIFT (7U) +#define QuadSPI_RSER_IPAEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPAEIE_SHIFT)) & QuadSPI_RSER_IPAEIE_MASK) +#define QuadSPI_RSER_IUEIE_MASK (0x800U) +#define QuadSPI_RSER_IUEIE_SHIFT (11U) +#define QuadSPI_RSER_IUEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IUEIE_SHIFT)) & QuadSPI_RSER_IUEIE_MASK) +#define QuadSPI_RSER_ABOIE_MASK (0x1000U) +#define QuadSPI_RSER_ABOIE_SHIFT (12U) +#define QuadSPI_RSER_ABOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABOIE_SHIFT)) & QuadSPI_RSER_ABOIE_MASK) +#define QuadSPI_RSER_ABSEIE_MASK (0x8000U) +#define QuadSPI_RSER_ABSEIE_SHIFT (15U) +#define QuadSPI_RSER_ABSEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABSEIE_SHIFT)) & QuadSPI_RSER_ABSEIE_MASK) +#define QuadSPI_RSER_RBDIE_MASK (0x10000U) +#define QuadSPI_RSER_RBDIE_SHIFT (16U) +#define QuadSPI_RSER_RBDIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDIE_SHIFT)) & QuadSPI_RSER_RBDIE_MASK) +#define QuadSPI_RSER_RBOIE_MASK (0x20000U) +#define QuadSPI_RSER_RBOIE_SHIFT (17U) +#define QuadSPI_RSER_RBOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBOIE_SHIFT)) & QuadSPI_RSER_RBOIE_MASK) +#define QuadSPI_RSER_RBDDE_MASK (0x200000U) +#define QuadSPI_RSER_RBDDE_SHIFT (21U) +#define QuadSPI_RSER_RBDDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDDE_SHIFT)) & QuadSPI_RSER_RBDDE_MASK) +#define QuadSPI_RSER_ILLINIE_MASK (0x800000U) +#define QuadSPI_RSER_ILLINIE_SHIFT (23U) +#define QuadSPI_RSER_ILLINIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ILLINIE_SHIFT)) & QuadSPI_RSER_ILLINIE_MASK) +#define QuadSPI_RSER_TBUIE_MASK (0x4000000U) +#define QuadSPI_RSER_TBUIE_SHIFT (26U) +#define QuadSPI_RSER_TBUIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBUIE_SHIFT)) & QuadSPI_RSER_TBUIE_MASK) +#define QuadSPI_RSER_TBFIE_MASK (0x8000000U) +#define QuadSPI_RSER_TBFIE_SHIFT (27U) +#define QuadSPI_RSER_TBFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFIE_SHIFT)) & QuadSPI_RSER_TBFIE_MASK) +#define QuadSPI_RSER_DLPFIE_MASK (0x80000000U) +#define QuadSPI_RSER_DLPFIE_SHIFT (31U) +#define QuadSPI_RSER_DLPFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_DLPFIE_SHIFT)) & QuadSPI_RSER_DLPFIE_MASK) + +/*! @name SPNDST - Sequence Suspend Status Register */ +#define QuadSPI_SPNDST_SUSPND_MASK (0x1U) +#define QuadSPI_SPNDST_SUSPND_SHIFT (0U) +#define QuadSPI_SPNDST_SUSPND(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SUSPND_SHIFT)) & QuadSPI_SPNDST_SUSPND_MASK) +#define QuadSPI_SPNDST_SPDBUF_MASK (0xC0U) +#define QuadSPI_SPNDST_SPDBUF_SHIFT (6U) +#define QuadSPI_SPNDST_SPDBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SPDBUF_SHIFT)) & QuadSPI_SPNDST_SPDBUF_MASK) +#define QuadSPI_SPNDST_DATLFT_MASK (0xFE00U) +#define QuadSPI_SPNDST_DATLFT_SHIFT (9U) +#define QuadSPI_SPNDST_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_DATLFT_SHIFT)) & QuadSPI_SPNDST_DATLFT_MASK) + +/*! @name SPTRCLR - Sequence Pointer Clear Register */ +#define QuadSPI_SPTRCLR_BFPTRC_MASK (0x1U) +#define QuadSPI_SPTRCLR_BFPTRC_SHIFT (0U) +#define QuadSPI_SPTRCLR_BFPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_BFPTRC_SHIFT)) & QuadSPI_SPTRCLR_BFPTRC_MASK) +#define QuadSPI_SPTRCLR_IPPTRC_MASK (0x100U) +#define QuadSPI_SPTRCLR_IPPTRC_SHIFT (8U) +#define QuadSPI_SPTRCLR_IPPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_IPPTRC_SHIFT)) & QuadSPI_SPTRCLR_IPPTRC_MASK) + +/*! @name SFA1AD - Serial Flash A1 Top Address */ +#define QuadSPI_SFA1AD_TPADA1_MASK (0xFFFFFC00U) +#define QuadSPI_SFA1AD_TPADA1_SHIFT (10U) +#define QuadSPI_SFA1AD_TPADA1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA1AD_TPADA1_SHIFT)) & QuadSPI_SFA1AD_TPADA1_MASK) + +/*! @name SFA2AD - Serial Flash A2 Top Address */ +#define QuadSPI_SFA2AD_TPADA2_MASK (0xFFFFFC00U) +#define QuadSPI_SFA2AD_TPADA2_SHIFT (10U) +#define QuadSPI_SFA2AD_TPADA2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA2AD_TPADA2_SHIFT)) & QuadSPI_SFA2AD_TPADA2_MASK) + +/*! @name SFB1AD - Serial Flash B1Top Address */ +#define QuadSPI_SFB1AD_TPADB1_MASK (0xFFFFFC00U) +#define QuadSPI_SFB1AD_TPADB1_SHIFT (10U) +#define QuadSPI_SFB1AD_TPADB1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB1AD_TPADB1_SHIFT)) & QuadSPI_SFB1AD_TPADB1_MASK) + +/*! @name SFB2AD - Serial Flash B2Top Address */ +#define QuadSPI_SFB2AD_TPADB2_MASK (0xFFFFFC00U) +#define QuadSPI_SFB2AD_TPADB2_SHIFT (10U) +#define QuadSPI_SFB2AD_TPADB2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB2AD_TPADB2_SHIFT)) & QuadSPI_SFB2AD_TPADB2_MASK) + +/*! @name RBDR - RX Buffer Data Register */ +#define QuadSPI_RBDR_RXDATA_MASK (0xFFFFFFFFU) +#define QuadSPI_RBDR_RXDATA_SHIFT (0U) +#define QuadSPI_RBDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBDR_RXDATA_SHIFT)) & QuadSPI_RBDR_RXDATA_MASK) + +/* The count of QuadSPI_RBDR */ +#define QuadSPI_RBDR_COUNT (32U) + +/*! @name LUTKEY - LUT Key Register */ +#define QuadSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) +#define QuadSPI_LUTKEY_KEY_SHIFT (0U) +#define QuadSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUTKEY_KEY_SHIFT)) & QuadSPI_LUTKEY_KEY_MASK) + +/*! @name LCKCR - LUT Lock Configuration Register */ +#define QuadSPI_LCKCR_LOCK_MASK (0x1U) +#define QuadSPI_LCKCR_LOCK_SHIFT (0U) +#define QuadSPI_LCKCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK) +#define QuadSPI_LCKCR_UNLOCK_MASK (0x2U) +#define QuadSPI_LCKCR_UNLOCK_SHIFT (1U) +#define QuadSPI_LCKCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_UNLOCK_SHIFT)) & QuadSPI_LCKCR_UNLOCK_MASK) + +/*! @name LUT - Look-up Table register */ +#define QuadSPI_LUT_OPRND0_MASK (0xFFU) +#define QuadSPI_LUT_OPRND0_SHIFT (0U) +#define QuadSPI_LUT_OPRND0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND0_SHIFT)) & QuadSPI_LUT_OPRND0_MASK) +#define QuadSPI_LUT_PAD0_MASK (0x300U) +#define QuadSPI_LUT_PAD0_SHIFT (8U) +#define QuadSPI_LUT_PAD0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD0_SHIFT)) & QuadSPI_LUT_PAD0_MASK) +#define QuadSPI_LUT_INSTR0_MASK (0xFC00U) +#define QuadSPI_LUT_INSTR0_SHIFT (10U) +#define QuadSPI_LUT_INSTR0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR0_SHIFT)) & QuadSPI_LUT_INSTR0_MASK) +#define QuadSPI_LUT_OPRND1_MASK (0xFF0000U) +#define QuadSPI_LUT_OPRND1_SHIFT (16U) +#define QuadSPI_LUT_OPRND1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND1_SHIFT)) & QuadSPI_LUT_OPRND1_MASK) +#define QuadSPI_LUT_PAD1_MASK (0x3000000U) +#define QuadSPI_LUT_PAD1_SHIFT (24U) +#define QuadSPI_LUT_PAD1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD1_SHIFT)) & QuadSPI_LUT_PAD1_MASK) +#define QuadSPI_LUT_INSTR1_MASK (0xFC000000U) +#define QuadSPI_LUT_INSTR1_SHIFT (26U) +#define QuadSPI_LUT_INSTR1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR1_SHIFT)) & QuadSPI_LUT_INSTR1_MASK) + +/* The count of QuadSPI_LUT */ +#define QuadSPI_LUT_COUNT (64U) + + +/*! + * @} + */ /* end of group QuadSPI_Register_Masks */ + + +/* QuadSPI - Peripheral instance base addresses */ +/** Peripheral QuadSPI base address */ +#define QuadSPI_BASE (0x21E0000u) +/** Peripheral QuadSPI base pointer */ +#define QuadSPI ((QuadSPI_Type *)QuadSPI_BASE) +/** Array initializer of QuadSPI peripheral base addresses */ +#define QuadSPI_BASE_ADDRS { QuadSPI_BASE } +/** Array initializer of QuadSPI peripheral base pointers */ +#define QuadSPI_BASE_PTRS { QuadSPI } +/** Interrupt vectors for the QuadSPI peripheral type */ +#define QuadSPI_IRQS { QSPI_IRQn } + +/*! + * @} + */ /* end of group QuadSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer + * @{ + */ + +/** RNG - Register Layout Typedef */ +typedef struct { + __I uint32_t VER; /**< RNGB version ID register, offset: 0x0 */ + __IO uint32_t CMD; /**< RNGB command register, offset: 0x4 */ + __IO uint32_t CR; /**< RNGB control register, offset: 0x8 */ + __I uint32_t SR; /**< RNGB status register, offset: 0xC */ + __I uint32_t ESR; /**< RNGB error status register, offset: 0x10 */ + __I uint32_t OUT; /**< RNGB Output FIFO, offset: 0x14 */ +} RNG_Type; + +/* ---------------------------------------------------------------------------- + -- RNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Register_Masks RNG Register Masks + * @{ + */ + +/*! @name VER - RNGB version ID register */ +#define RNG_VER_MINOR_MASK (0xFFU) +#define RNG_VER_MINOR_SHIFT (0U) +#define RNG_VER_MINOR(x) (((uint32_t)(((uint32_t)(x)) << RNG_VER_MINOR_SHIFT)) & RNG_VER_MINOR_MASK) +#define RNG_VER_MAJOR_MASK (0xFF00U) +#define RNG_VER_MAJOR_SHIFT (8U) +#define RNG_VER_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << RNG_VER_MAJOR_SHIFT)) & RNG_VER_MAJOR_MASK) +#define RNG_VER_TYPE_MASK (0xF0000000U) +#define RNG_VER_TYPE_SHIFT (28U) +#define RNG_VER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << RNG_VER_TYPE_SHIFT)) & RNG_VER_TYPE_MASK) + +/*! @name CMD - RNGB command register */ +#define RNG_CMD_ST_MASK (0x1U) +#define RNG_CMD_ST_SHIFT (0U) +#define RNG_CMD_ST(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_ST_SHIFT)) & RNG_CMD_ST_MASK) +#define RNG_CMD_GS_MASK (0x2U) +#define RNG_CMD_GS_SHIFT (1U) +#define RNG_CMD_GS(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_GS_SHIFT)) & RNG_CMD_GS_MASK) +#define RNG_CMD_CI_MASK (0x10U) +#define RNG_CMD_CI_SHIFT (4U) +#define RNG_CMD_CI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_CI_SHIFT)) & RNG_CMD_CI_MASK) +#define RNG_CMD_CE_MASK (0x20U) +#define RNG_CMD_CE_SHIFT (5U) +#define RNG_CMD_CE(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_CE_SHIFT)) & RNG_CMD_CE_MASK) +#define RNG_CMD_SR_MASK (0x40U) +#define RNG_CMD_SR_SHIFT (6U) +#define RNG_CMD_SR(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_SR_SHIFT)) & RNG_CMD_SR_MASK) + +/*! @name CR - RNGB control register */ +#define RNG_CR_FUFMOD_MASK (0x3U) +#define RNG_CR_FUFMOD_SHIFT (0U) +#define RNG_CR_FUFMOD(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_FUFMOD_SHIFT)) & RNG_CR_FUFMOD_MASK) +#define RNG_CR_AR_MASK (0x10U) +#define RNG_CR_AR_SHIFT (4U) +#define RNG_CR_AR(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_AR_SHIFT)) & RNG_CR_AR_MASK) +#define RNG_CR_MASKDONE_MASK (0x20U) +#define RNG_CR_MASKDONE_SHIFT (5U) +#define RNG_CR_MASKDONE(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_MASKDONE_SHIFT)) & RNG_CR_MASKDONE_MASK) +#define RNG_CR_MASKERR_MASK (0x40U) +#define RNG_CR_MASKERR_SHIFT (6U) +#define RNG_CR_MASKERR(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_MASKERR_SHIFT)) & RNG_CR_MASKERR_MASK) + +/*! @name SR - RNGB status register */ +#define RNG_SR_BUSY_MASK (0x2U) +#define RNG_SR_BUSY_SHIFT (1U) +#define RNG_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_BUSY_SHIFT)) & RNG_SR_BUSY_MASK) +#define RNG_SR_SLP_MASK (0x4U) +#define RNG_SR_SLP_SHIFT (2U) +#define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK) +#define RNG_SR_RS_MASK (0x8U) +#define RNG_SR_RS_SHIFT (3U) +#define RNG_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_RS_SHIFT)) & RNG_SR_RS_MASK) +#define RNG_SR_STDN_MASK (0x10U) +#define RNG_SR_STDN_SHIFT (4U) +#define RNG_SR_STDN(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_STDN_SHIFT)) & RNG_SR_STDN_MASK) +#define RNG_SR_SDN_MASK (0x20U) +#define RNG_SR_SDN_SHIFT (5U) +#define RNG_SR_SDN(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SDN_SHIFT)) & RNG_SR_SDN_MASK) +#define RNG_SR_NSDN_MASK (0x40U) +#define RNG_SR_NSDN_SHIFT (6U) +#define RNG_SR_NSDN(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_NSDN_SHIFT)) & RNG_SR_NSDN_MASK) +#define RNG_SR_FIFO_LVL_MASK (0xF00U) +#define RNG_SR_FIFO_LVL_SHIFT (8U) +#define RNG_SR_FIFO_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_FIFO_LVL_SHIFT)) & RNG_SR_FIFO_LVL_MASK) +#define RNG_SR_FIFO_SIZE_MASK (0xF000U) +#define RNG_SR_FIFO_SIZE_SHIFT (12U) +#define RNG_SR_FIFO_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_FIFO_SIZE_SHIFT)) & RNG_SR_FIFO_SIZE_MASK) +#define RNG_SR_ERR_MASK (0x10000U) +#define RNG_SR_ERR_SHIFT (16U) +#define RNG_SR_ERR(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERR_SHIFT)) & RNG_SR_ERR_MASK) +#define RNG_SR_ST_PF_MASK (0xE00000U) +#define RNG_SR_ST_PF_SHIFT (21U) +#define RNG_SR_ST_PF(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ST_PF_SHIFT)) & RNG_SR_ST_PF_MASK) +#define RNG_SR_STATPF_MASK (0xFF000000U) +#define RNG_SR_STATPF_SHIFT (24U) +#define RNG_SR_STATPF(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_STATPF_SHIFT)) & RNG_SR_STATPF_MASK) + +/*! @name ESR - RNGB error status register */ +#define RNG_ESR_LFE_MASK (0x1U) +#define RNG_ESR_LFE_SHIFT (0U) +#define RNG_ESR_LFE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_LFE_SHIFT)) & RNG_ESR_LFE_MASK) +#define RNG_ESR_OSCE_MASK (0x2U) +#define RNG_ESR_OSCE_SHIFT (1U) +#define RNG_ESR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_OSCE_SHIFT)) & RNG_ESR_OSCE_MASK) +#define RNG_ESR_STE_MASK (0x4U) +#define RNG_ESR_STE_SHIFT (2U) +#define RNG_ESR_STE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_STE_SHIFT)) & RNG_ESR_STE_MASK) +#define RNG_ESR_SATE_MASK (0x8U) +#define RNG_ESR_SATE_SHIFT (3U) +#define RNG_ESR_SATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_SATE_SHIFT)) & RNG_ESR_SATE_MASK) +#define RNG_ESR_FUFE_MASK (0x10U) +#define RNG_ESR_FUFE_SHIFT (4U) +#define RNG_ESR_FUFE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_FUFE_SHIFT)) & RNG_ESR_FUFE_MASK) + +/*! @name OUT - RNGB Output FIFO */ +#define RNG_OUT_RANDOUT_MASK (0xFFFFFFFFU) +#define RNG_OUT_RANDOUT_SHIFT (0U) +#define RNG_OUT_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OUT_RANDOUT_SHIFT)) & RNG_OUT_RANDOUT_MASK) + + +/*! + * @} + */ /* end of group RNG_Register_Masks */ + + +/* RNG - Peripheral instance base addresses */ +/** Peripheral RNG base address */ +#define RNG_BASE (0x2284000u) +/** Peripheral RNG base pointer */ +#define RNG ((RNG_Type *)RNG_BASE) +/** Array initializer of RNG peripheral base addresses */ +#define RNG_BASE_ADDRS { RNG_BASE } +/** Array initializer of RNG peripheral base pointers */ +#define RNG_BASE_PTRS { RNG } + +/*! + * @} + */ /* end of group RNG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ROMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer + * @{ + */ + +/** ROMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[212]; + __IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */ + __IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */ + __I uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */ + __IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */ + __IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_1[200]; + __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */ +} ROMC_Type; + +/* ---------------------------------------------------------------------------- + -- ROMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Register_Masks ROMC Register Masks + * @{ + */ + +/*! @name ROMPATCHD - ROMC Data Registers */ +#define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) +#define ROMC_ROMPATCHD_DATAX_SHIFT (0U) +#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK) + +/* The count of ROMC_ROMPATCHD */ +#define ROMC_ROMPATCHD_COUNT (8U) + +/*! @name ROMPATCHCNTL - ROMC Control Register */ +#define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU) +#define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U) +#define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK) +#define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U) +#define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U) +#define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK) + +/*! @name ROMPATCHENL - ROMC Enable Register Low */ +#define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU) +#define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U) +#define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK) + +/*! @name ROMPATCHA - ROMC Address Registers */ +#define ROMC_ROMPATCHA_THUMBX_MASK (0x1U) +#define ROMC_ROMPATCHA_THUMBX_SHIFT (0U) +#define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK) +#define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) +#define ROMC_ROMPATCHA_ADDRX_SHIFT (1U) +#define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK) + +/* The count of ROMC_ROMPATCHA */ +#define ROMC_ROMPATCHA_COUNT (16U) + +/*! @name ROMPATCHSR - ROMC Status Register */ +#define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU) +#define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U) +#define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK) +#define ROMC_ROMPATCHSR_SW_MASK (0x20000U) +#define ROMC_ROMPATCHSR_SW_SHIFT (17U) +#define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) + + +/*! + * @} + */ /* end of group ROMC_Register_Masks */ + + +/* ROMC - Peripheral instance base addresses */ +/** Peripheral ROMC base address */ +#define ROMC_BASE (0x21AC000u) +/** Peripheral ROMC base pointer */ +#define ROMC ((ROMC_Type *)ROMC_BASE) +/** Array initializer of ROMC peripheral base addresses */ +#define ROMC_BASE_ADDRS { ROMC_BASE } +/** Array initializer of ROMC peripheral base pointers */ +#define ROMC_BASE_PTRS { ROMC } + +/*! + * @} + */ /* end of group ROMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SDMAARM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMAARM_Peripheral_Access_Layer SDMAARM Peripheral Access Layer + * @{ + */ + +/** SDMAARM - Register Layout Typedef */ +typedef struct { + __IO uint32_t MC0PTR; /**< ARM platform Channel 0 Pointer, offset: 0x0 */ + __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */ + __IO uint32_t STOP_STAT; /**< Channel Stop/Channel Status, offset: 0x8 */ + __IO uint32_t HSTART; /**< Channel Start, offset: 0xC */ + __IO uint32_t EVTOVR; /**< Channel Event Override, offset: 0x10 */ + __IO uint32_t DSPOVR; /**< Channel BP Override, offset: 0x14 */ + __IO uint32_t HOSTOVR; /**< Channel ARM platform Override, offset: 0x18 */ + __IO uint32_t EVTPEND; /**< Channel Event Pending, offset: 0x1C */ + uint8_t RESERVED_0[4]; + __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ + __I uint32_t EVTERR; /**< DMA Request Error Register, offset: 0x28 */ + __IO uint32_t INTRMASK; /**< Channel ARM platform Interrupt Mask, offset: 0x2C */ + __I uint32_t PSW; /**< Schedule Status, offset: 0x30 */ + __I uint32_t EVTERRDBG; /**< DMA Request Error Register, offset: 0x34 */ + __IO uint32_t CONFIG; /**< Configuration Register, offset: 0x38 */ + __IO uint32_t SDMA_LOCK; /**< SDMA LOCK, offset: 0x3C */ + __IO uint32_t ONCE_ENB; /**< OnCE Enable, offset: 0x40 */ + __IO uint32_t ONCE_DATA; /**< OnCE Data Register, offset: 0x44 */ + __IO uint32_t ONCE_INSTR; /**< OnCE Instruction Register, offset: 0x48 */ + __I uint32_t ONCE_STAT; /**< OnCE Status Register, offset: 0x4C */ + __IO uint32_t ONCE_CMD; /**< OnCE Command Register, offset: 0x50 */ + uint8_t RESERVED_1[4]; + __IO uint32_t ILLINSTADDR; /**< Illegal Instruction Trap Address, offset: 0x58 */ + __IO uint32_t CHN0ADDR; /**< Channel 0 Boot Address, offset: 0x5C */ + __I uint32_t EVT_MIRROR; /**< DMA Requests, offset: 0x60 */ + __I uint32_t EVT_MIRROR2; /**< DMA Requests 2, offset: 0x64 */ + uint8_t RESERVED_2[8]; + __IO uint32_t XTRIG_CONF1; /**< Cross-Trigger Events Configuration Register 1, offset: 0x70 */ + __IO uint32_t XTRIG_CONF2; /**< Cross-Trigger Events Configuration Register 2, offset: 0x74 */ + uint8_t RESERVED_3[136]; + __IO uint32_t SDMA_CHNPRI[32]; /**< Channel Priority Registers, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_4[128]; + __IO uint32_t CHNENBL[48]; /**< Channel Enable RAM, array offset: 0x200, array step: 0x4 */ +} SDMAARM_Type; + +/* ---------------------------------------------------------------------------- + -- SDMAARM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks + * @{ + */ + +/*! @name MC0PTR - ARM platform Channel 0 Pointer */ +#define SDMAARM_MC0PTR_MC0PTR_MASK (0xFFFFFFFFU) +#define SDMAARM_MC0PTR_MC0PTR_SHIFT (0U) +#define SDMAARM_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_MC0PTR_MC0PTR_SHIFT)) & SDMAARM_MC0PTR_MC0PTR_MASK) + +/*! @name INTR - Channel Interrupts */ +#define SDMAARM_INTR_HI_MASK (0xFFFFFFFFU) +#define SDMAARM_INTR_HI_SHIFT (0U) +#define SDMAARM_INTR_HI(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTR_HI_SHIFT)) & SDMAARM_INTR_HI_MASK) + +/*! @name STOP_STAT - Channel Stop/Channel Status */ +#define SDMAARM_STOP_STAT_HE_MASK (0xFFFFFFFFU) +#define SDMAARM_STOP_STAT_HE_SHIFT (0U) +#define SDMAARM_STOP_STAT_HE(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_STOP_STAT_HE_SHIFT)) & SDMAARM_STOP_STAT_HE_MASK) + +/*! @name HSTART - Channel Start */ +#define SDMAARM_HSTART_HSTART_HE_MASK (0xFFFFFFFFU) +#define SDMAARM_HSTART_HSTART_HE_SHIFT (0U) +#define SDMAARM_HSTART_HSTART_HE(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_HSTART_HSTART_HE_SHIFT)) & SDMAARM_HSTART_HSTART_HE_MASK) + +/*! @name EVTOVR - Channel Event Override */ +#define SDMAARM_EVTOVR_EO_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTOVR_EO_SHIFT (0U) +#define SDMAARM_EVTOVR_EO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTOVR_EO_SHIFT)) & SDMAARM_EVTOVR_EO_MASK) + +/*! @name DSPOVR - Channel BP Override */ +#define SDMAARM_DSPOVR_DO_MASK (0xFFFFFFFFU) +#define SDMAARM_DSPOVR_DO_SHIFT (0U) +#define SDMAARM_DSPOVR_DO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DSPOVR_DO_SHIFT)) & SDMAARM_DSPOVR_DO_MASK) + +/*! @name HOSTOVR - Channel ARM platform Override */ +#define SDMAARM_HOSTOVR_HO_MASK (0xFFFFFFFFU) +#define SDMAARM_HOSTOVR_HO_SHIFT (0U) +#define SDMAARM_HOSTOVR_HO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_HOSTOVR_HO_SHIFT)) & SDMAARM_HOSTOVR_HO_MASK) + +/*! @name EVTPEND - Channel Event Pending */ +#define SDMAARM_EVTPEND_EP_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTPEND_EP_SHIFT (0U) +#define SDMAARM_EVTPEND_EP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTPEND_EP_SHIFT)) & SDMAARM_EVTPEND_EP_MASK) + +/*! @name RESET - Reset Register */ +#define SDMAARM_RESET_RESET_MASK (0x1U) +#define SDMAARM_RESET_RESET_SHIFT (0U) +#define SDMAARM_RESET_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESET_SHIFT)) & SDMAARM_RESET_RESET_MASK) +#define SDMAARM_RESET_RESCHED_MASK (0x2U) +#define SDMAARM_RESET_RESCHED_SHIFT (1U) +#define SDMAARM_RESET_RESCHED(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESCHED_SHIFT)) & SDMAARM_RESET_RESCHED_MASK) + +/*! @name EVTERR - DMA Request Error Register */ +#define SDMAARM_EVTERR_CHNERR_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTERR_CHNERR_SHIFT (0U) +#define SDMAARM_EVTERR_CHNERR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERR_CHNERR_SHIFT)) & SDMAARM_EVTERR_CHNERR_MASK) + +/*! @name INTRMASK - Channel ARM platform Interrupt Mask */ +#define SDMAARM_INTRMASK_HIMASK_MASK (0xFFFFFFFFU) +#define SDMAARM_INTRMASK_HIMASK_SHIFT (0U) +#define SDMAARM_INTRMASK_HIMASK(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTRMASK_HIMASK_SHIFT)) & SDMAARM_INTRMASK_HIMASK_MASK) + +/*! @name PSW - Schedule Status */ +#define SDMAARM_PSW_CCR_MASK (0xFU) +#define SDMAARM_PSW_CCR_SHIFT (0U) +#define SDMAARM_PSW_CCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCR_SHIFT)) & SDMAARM_PSW_CCR_MASK) +#define SDMAARM_PSW_CCP_MASK (0xF0U) +#define SDMAARM_PSW_CCP_SHIFT (4U) +#define SDMAARM_PSW_CCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCP_SHIFT)) & SDMAARM_PSW_CCP_MASK) +#define SDMAARM_PSW_NCR_MASK (0x1F00U) +#define SDMAARM_PSW_NCR_SHIFT (8U) +#define SDMAARM_PSW_NCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCR_SHIFT)) & SDMAARM_PSW_NCR_MASK) +#define SDMAARM_PSW_NCP_MASK (0xE000U) +#define SDMAARM_PSW_NCP_SHIFT (13U) +#define SDMAARM_PSW_NCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCP_SHIFT)) & SDMAARM_PSW_NCP_MASK) + +/*! @name EVTERRDBG - DMA Request Error Register */ +#define SDMAARM_EVTERRDBG_CHNERR_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTERRDBG_CHNERR_SHIFT (0U) +#define SDMAARM_EVTERRDBG_CHNERR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERRDBG_CHNERR_SHIFT)) & SDMAARM_EVTERRDBG_CHNERR_MASK) + +/*! @name CONFIG - Configuration Register */ +#define SDMAARM_CONFIG_CSM_MASK (0x3U) +#define SDMAARM_CONFIG_CSM_SHIFT (0U) +#define SDMAARM_CONFIG_CSM(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_CSM_SHIFT)) & SDMAARM_CONFIG_CSM_MASK) +#define SDMAARM_CONFIG_ACR_MASK (0x10U) +#define SDMAARM_CONFIG_ACR_SHIFT (4U) +#define SDMAARM_CONFIG_ACR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_ACR_SHIFT)) & SDMAARM_CONFIG_ACR_MASK) +#define SDMAARM_CONFIG_RTDOBS_MASK (0x800U) +#define SDMAARM_CONFIG_RTDOBS_SHIFT (11U) +#define SDMAARM_CONFIG_RTDOBS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_RTDOBS_SHIFT)) & SDMAARM_CONFIG_RTDOBS_MASK) +#define SDMAARM_CONFIG_DSPDMA_MASK (0x1000U) +#define SDMAARM_CONFIG_DSPDMA_SHIFT (12U) +#define SDMAARM_CONFIG_DSPDMA(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_DSPDMA_SHIFT)) & SDMAARM_CONFIG_DSPDMA_MASK) + +/*! @name SDMA_LOCK - SDMA LOCK */ +#define SDMAARM_SDMA_LOCK_LOCK_MASK (0x1U) +#define SDMAARM_SDMA_LOCK_LOCK_SHIFT (0U) +#define SDMAARM_SDMA_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_LOCK_SHIFT)) & SDMAARM_SDMA_LOCK_LOCK_MASK) +#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK (0x2U) +#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT (1U) +#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT)) & SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK) + +/*! @name ONCE_ENB - OnCE Enable */ +#define SDMAARM_ONCE_ENB_ENB_MASK (0x1U) +#define SDMAARM_ONCE_ENB_ENB_SHIFT (0U) +#define SDMAARM_ONCE_ENB_ENB(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_ENB_ENB_SHIFT)) & SDMAARM_ONCE_ENB_ENB_MASK) + +/*! @name ONCE_DATA - OnCE Data Register */ +#define SDMAARM_ONCE_DATA_DATA_MASK (0xFFFFFFFFU) +#define SDMAARM_ONCE_DATA_DATA_SHIFT (0U) +#define SDMAARM_ONCE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_DATA_DATA_SHIFT)) & SDMAARM_ONCE_DATA_DATA_MASK) + +/*! @name ONCE_INSTR - OnCE Instruction Register */ +#define SDMAARM_ONCE_INSTR_INSTR_MASK (0xFFFFU) +#define SDMAARM_ONCE_INSTR_INSTR_SHIFT (0U) +#define SDMAARM_ONCE_INSTR_INSTR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_INSTR_INSTR_SHIFT)) & SDMAARM_ONCE_INSTR_INSTR_MASK) + +/*! @name ONCE_STAT - OnCE Status Register */ +#define SDMAARM_ONCE_STAT_ECDR_MASK (0x7U) +#define SDMAARM_ONCE_STAT_ECDR_SHIFT (0U) +#define SDMAARM_ONCE_STAT_ECDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ECDR_SHIFT)) & SDMAARM_ONCE_STAT_ECDR_MASK) +#define SDMAARM_ONCE_STAT_MST_MASK (0x80U) +#define SDMAARM_ONCE_STAT_MST_SHIFT (7U) +#define SDMAARM_ONCE_STAT_MST(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_MST_SHIFT)) & SDMAARM_ONCE_STAT_MST_MASK) +#define SDMAARM_ONCE_STAT_SWB_MASK (0x100U) +#define SDMAARM_ONCE_STAT_SWB_SHIFT (8U) +#define SDMAARM_ONCE_STAT_SWB(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_SWB_SHIFT)) & SDMAARM_ONCE_STAT_SWB_MASK) +#define SDMAARM_ONCE_STAT_ODR_MASK (0x200U) +#define SDMAARM_ONCE_STAT_ODR_SHIFT (9U) +#define SDMAARM_ONCE_STAT_ODR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ODR_SHIFT)) & SDMAARM_ONCE_STAT_ODR_MASK) +#define SDMAARM_ONCE_STAT_EDR_MASK (0x400U) +#define SDMAARM_ONCE_STAT_EDR_SHIFT (10U) +#define SDMAARM_ONCE_STAT_EDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_EDR_SHIFT)) & SDMAARM_ONCE_STAT_EDR_MASK) +#define SDMAARM_ONCE_STAT_RCV_MASK (0x800U) +#define SDMAARM_ONCE_STAT_RCV_SHIFT (11U) +#define SDMAARM_ONCE_STAT_RCV(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_RCV_SHIFT)) & SDMAARM_ONCE_STAT_RCV_MASK) +#define SDMAARM_ONCE_STAT_PST_MASK (0xF000U) +#define SDMAARM_ONCE_STAT_PST_SHIFT (12U) +#define SDMAARM_ONCE_STAT_PST(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_PST_SHIFT)) & SDMAARM_ONCE_STAT_PST_MASK) + +/*! @name ONCE_CMD - OnCE Command Register */ +#define SDMAARM_ONCE_CMD_CMD_MASK (0xFU) +#define SDMAARM_ONCE_CMD_CMD_SHIFT (0U) +#define SDMAARM_ONCE_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_CMD_CMD_SHIFT)) & SDMAARM_ONCE_CMD_CMD_MASK) + +/*! @name ILLINSTADDR - Illegal Instruction Trap Address */ +#define SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK (0x3FFFU) +#define SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT (0U) +#define SDMAARM_ILLINSTADDR_ILLINSTADDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT)) & SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK) + +/*! @name CHN0ADDR - Channel 0 Boot Address */ +#define SDMAARM_CHN0ADDR_CHN0ADDR_MASK (0x3FFFU) +#define SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT (0U) +#define SDMAARM_CHN0ADDR_CHN0ADDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT)) & SDMAARM_CHN0ADDR_CHN0ADDR_MASK) +#define SDMAARM_CHN0ADDR_SMSZ_MASK (0x4000U) +#define SDMAARM_CHN0ADDR_SMSZ_SHIFT (14U) +#define SDMAARM_CHN0ADDR_SMSZ(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_SMSZ_SHIFT)) & SDMAARM_CHN0ADDR_SMSZ_MASK) + +/*! @name EVT_MIRROR - DMA Requests */ +#define SDMAARM_EVT_MIRROR_EVENTS_MASK (0xFFFFFFFFU) +#define SDMAARM_EVT_MIRROR_EVENTS_SHIFT (0U) +#define SDMAARM_EVT_MIRROR_EVENTS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR_EVENTS_MASK) + +/*! @name EVT_MIRROR2 - DMA Requests 2 */ +#define SDMAARM_EVT_MIRROR2_EVENTS_MASK (0xFFFFU) +#define SDMAARM_EVT_MIRROR2_EVENTS_SHIFT (0U) +#define SDMAARM_EVT_MIRROR2_EVENTS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR2_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR2_EVENTS_MASK) + +/*! @name XTRIG_CONF1 - Cross-Trigger Events Configuration Register 1 */ +#define SDMAARM_XTRIG_CONF1_NUM0_MASK (0x3FU) +#define SDMAARM_XTRIG_CONF1_NUM0_SHIFT (0U) +#define SDMAARM_XTRIG_CONF1_NUM0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM0_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM0_MASK) +#define SDMAARM_XTRIG_CONF1_CNF0_MASK (0x40U) +#define SDMAARM_XTRIG_CONF1_CNF0_SHIFT (6U) +#define SDMAARM_XTRIG_CONF1_CNF0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF0_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF0_MASK) +#define SDMAARM_XTRIG_CONF1_NUM1_MASK (0x3F00U) +#define SDMAARM_XTRIG_CONF1_NUM1_SHIFT (8U) +#define SDMAARM_XTRIG_CONF1_NUM1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM1_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM1_MASK) +#define SDMAARM_XTRIG_CONF1_CNF1_MASK (0x4000U) +#define SDMAARM_XTRIG_CONF1_CNF1_SHIFT (14U) +#define SDMAARM_XTRIG_CONF1_CNF1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF1_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF1_MASK) +#define SDMAARM_XTRIG_CONF1_NUM2_MASK (0x3F0000U) +#define SDMAARM_XTRIG_CONF1_NUM2_SHIFT (16U) +#define SDMAARM_XTRIG_CONF1_NUM2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM2_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM2_MASK) +#define SDMAARM_XTRIG_CONF1_CNF2_MASK (0x400000U) +#define SDMAARM_XTRIG_CONF1_CNF2_SHIFT (22U) +#define SDMAARM_XTRIG_CONF1_CNF2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF2_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF2_MASK) +#define SDMAARM_XTRIG_CONF1_NUM3_MASK (0x3F000000U) +#define SDMAARM_XTRIG_CONF1_NUM3_SHIFT (24U) +#define SDMAARM_XTRIG_CONF1_NUM3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM3_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM3_MASK) +#define SDMAARM_XTRIG_CONF1_CNF3_MASK (0x40000000U) +#define SDMAARM_XTRIG_CONF1_CNF3_SHIFT (30U) +#define SDMAARM_XTRIG_CONF1_CNF3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF3_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF3_MASK) + +/*! @name XTRIG_CONF2 - Cross-Trigger Events Configuration Register 2 */ +#define SDMAARM_XTRIG_CONF2_NUM4_MASK (0x3FU) +#define SDMAARM_XTRIG_CONF2_NUM4_SHIFT (0U) +#define SDMAARM_XTRIG_CONF2_NUM4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM4_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM4_MASK) +#define SDMAARM_XTRIG_CONF2_CNF4_MASK (0x40U) +#define SDMAARM_XTRIG_CONF2_CNF4_SHIFT (6U) +#define SDMAARM_XTRIG_CONF2_CNF4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF4_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF4_MASK) +#define SDMAARM_XTRIG_CONF2_NUM5_MASK (0x3F00U) +#define SDMAARM_XTRIG_CONF2_NUM5_SHIFT (8U) +#define SDMAARM_XTRIG_CONF2_NUM5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM5_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM5_MASK) +#define SDMAARM_XTRIG_CONF2_CNF5_MASK (0x4000U) +#define SDMAARM_XTRIG_CONF2_CNF5_SHIFT (14U) +#define SDMAARM_XTRIG_CONF2_CNF5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF5_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF5_MASK) +#define SDMAARM_XTRIG_CONF2_NUM6_MASK (0x3F0000U) +#define SDMAARM_XTRIG_CONF2_NUM6_SHIFT (16U) +#define SDMAARM_XTRIG_CONF2_NUM6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM6_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM6_MASK) +#define SDMAARM_XTRIG_CONF2_CNF6_MASK (0x400000U) +#define SDMAARM_XTRIG_CONF2_CNF6_SHIFT (22U) +#define SDMAARM_XTRIG_CONF2_CNF6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF6_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF6_MASK) +#define SDMAARM_XTRIG_CONF2_NUM7_MASK (0x3F000000U) +#define SDMAARM_XTRIG_CONF2_NUM7_SHIFT (24U) +#define SDMAARM_XTRIG_CONF2_NUM7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM7_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM7_MASK) +#define SDMAARM_XTRIG_CONF2_CNF7_MASK (0x40000000U) +#define SDMAARM_XTRIG_CONF2_CNF7_SHIFT (30U) +#define SDMAARM_XTRIG_CONF2_CNF7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF7_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF7_MASK) + +/*! @name SDMA_CHNPRI - Channel Priority Registers */ +#define SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK (0x7U) +#define SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT (0U) +#define SDMAARM_SDMA_CHNPRI_CHNPRIn(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT)) & SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK) + +/* The count of SDMAARM_SDMA_CHNPRI */ +#define SDMAARM_SDMA_CHNPRI_COUNT (32U) + +/*! @name CHNENBL - Channel Enable RAM */ +#define SDMAARM_CHNENBL_ENBLn_MASK (0xFFFFFFFFU) +#define SDMAARM_CHNENBL_ENBLn_SHIFT (0U) +#define SDMAARM_CHNENBL_ENBLn(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHNENBL_ENBLn_SHIFT)) & SDMAARM_CHNENBL_ENBLn_MASK) + +/* The count of SDMAARM_CHNENBL */ +#define SDMAARM_CHNENBL_COUNT (48U) + + +/*! + * @} + */ /* end of group SDMAARM_Register_Masks */ + + +/* SDMAARM - Peripheral instance base addresses */ +/** Peripheral SDMAARM base address */ +#define SDMAARM_BASE (0x20EC000u) +/** Peripheral SDMAARM base pointer */ +#define SDMAARM ((SDMAARM_Type *)SDMAARM_BASE) +/** Array initializer of SDMAARM peripheral base addresses */ +#define SDMAARM_BASE_ADDRS { SDMAARM_BASE } +/** Array initializer of SDMAARM peripheral base pointers */ +#define SDMAARM_BASE_PTRS { SDMAARM } +/** Interrupt vectors for the SDMAARM peripheral type */ +#define SDMAARM_IRQS { SDMA_IRQn } + +/*! + * @} + */ /* end of group SDMAARM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer + * @{ + */ + +/** SNVS - Register Layout Typedef */ +/* zuozhongkai 2018/12/13 */ +typedef struct { + __IO uint32_t HPLR; /**< SNVS_HP Lock register, offset: 0x0 */ + __IO uint32_t HPCOMR; /**< SNVS_HP Command register, offset: 0x4 */ + __IO uint32_t HPCR; /**< SNVS_HP Control register, offset: 0x8 */ + __IO uint32_t HPSICR; /**< SNVS_HP Control register, offset: 0x8 */ + __IO uint32_t HPSVCR; + __IO uint32_t HPSR; + __IO uint32_t HPSVSR; + __IO uint32_t HPHACIVR; + __IO uint32_t HPHACR; + __IO uint32_t HPRTCMR; + __IO uint32_t HPRTCLR; + __IO uint32_t HPTAMR; + __IO uint32_t HPTALR; + __IO uint32_t LPLR; + __IO uint32_t LPCR; + __IO uint32_t LPMKCR; + __IO uint32_t LPSVCR; + __IO uint32_t LPTGFCR; + __IO uint32_t LPTDCR; + __IO uint32_t LPSR; + __IO uint32_t LPSRTCMR; + __IO uint32_t LPSRTCLR; + __IO uint32_t LPTAR; + __IO uint32_t LPSMCMR; + __IO uint32_t LPSMCLR; +uint8_t RESERVED_4[4]; +__IO uint32_t LPGPR; /**< SNVS_LP General-Purpose Register, offset: 0x68 */ +uint8_t RESERVED_5[2956]; +__I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ +__I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ +}SNVS_Type; + + +/* ---------------------------------------------------------------------------- + -- SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Register_Masks SNVS Register Masks + * @{ + */ + +/*! @name HPLR - SNVS_HP Lock register */ +#define SNVS_HPLR_MC_SL_MASK (0x10U) +#define SNVS_HPLR_MC_SL_SHIFT (4U) +#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK) +#define SNVS_HPLR_GPR_SL_MASK (0x20U) +#define SNVS_HPLR_GPR_SL_SHIFT (5U) +#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK) + +/*! @name HPCOMR - SNVS_HP Command register */ +#define SNVS_HPCOMR_LP_SWR_MASK (0x10U) +#define SNVS_HPCOMR_LP_SWR_SHIFT (4U) +#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK) +#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U) +#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U) +#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK) +#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) +#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) +#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) + +/*! @name HPCR - SNVS_HP Control register */ +#define SNVS_HPCR_RTC_EN_MASK (0x1U) +#define SNVS_HPCR_RTC_EN_SHIFT (0U) +#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) +#define SNVS_HPCR_HPTA_EN_MASK (0x2U) +#define SNVS_HPCR_HPTA_EN_SHIFT (1U) +#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) +#define SNVS_HPCR_PI_EN_MASK (0x8U) +#define SNVS_HPCR_PI_EN_SHIFT (3U) +#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) +#define SNVS_HPCR_PI_FREQ_MASK (0xF0U) +#define SNVS_HPCR_PI_FREQ_SHIFT (4U) +#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK) +#define SNVS_HPCR_HPCALB_EN_MASK (0x100U) +#define SNVS_HPCR_HPCALB_EN_SHIFT (8U) +#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) +#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) +#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U) +#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) +#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U) +#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U) +#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK) +#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U) +#define SNVS_HPCR_BTN_MASK_SHIFT (27U) +#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) + +/*! @name HPSR - SNVS_HP Status register */ +#define SNVS_HPSR_BTN_MASK (0x40U) +#define SNVS_HPSR_BTN_SHIFT (6U) +#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK) +#define SNVS_HPSR_BI_MASK (0x80U) +#define SNVS_HPSR_BI_SHIFT (7U) +#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK) + +/*! @name HPRTCMR - SNVS_HP Real-Time Counter MSB Register */ +#define SNVS_HPRTCMR_RTC_MASK (0xFFFFFFFFU) +#define SNVS_HPRTCMR_RTC_SHIFT (0U) +#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) + +/*! @name HPRTCLR - SNVS_HP Real-Time Counter LSB Register */ +#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) +#define SNVS_HPRTCLR_RTC_SHIFT (0U) +#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) + +/*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ +#define SNVS_HPTAMR_HPTA_MASK (0x7FFFU) +#define SNVS_HPTAMR_HPTA_SHIFT (0U) +#define SNVS_HPTAMR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_SHIFT)) & SNVS_HPTAMR_HPTA_MASK) + +/*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ +#define SNVS_HPTALR_HPTA_MASK (0xFFFFFFFFU) +#define SNVS_HPTALR_HPTA_SHIFT (0U) +#define SNVS_HPTALR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_SHIFT)) & SNVS_HPTALR_HPTA_MASK) + +/*! @name LPLR - SNVS_LP Lock Register */ +#define SNVS_LPLR_MC_HL_MASK (0x10U) +#define SNVS_LPLR_MC_HL_SHIFT (4U) +#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) +#define SNVS_LPLR_GPR_HL_MASK (0x20U) +#define SNVS_LPLR_GPR_HL_SHIFT (5U) +#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) + +/*! @name LPCR - SNVS_LP Control Register */ +#define SNVS_LPCR_MC_ENV_MASK (0x4U) +#define SNVS_LPCR_MC_ENV_SHIFT (2U) +#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) +#define SNVS_LPCR_DP_EN_MASK (0x20U) +#define SNVS_LPCR_DP_EN_SHIFT (5U) +#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK) +#define SNVS_LPCR_TOP_MASK (0x40U) +#define SNVS_LPCR_TOP_SHIFT (6U) +#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK) +#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U) +#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U) +#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK) +#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U) +#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U) +#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK) +#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U) +#define SNVS_LPCR_DEBOUNCE_SHIFT (18U) +#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK) +#define SNVS_LPCR_ON_TIME_MASK (0x300000U) +#define SNVS_LPCR_ON_TIME_SHIFT (20U) +#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK) +#define SNVS_LPCR_PK_EN_MASK (0x400000U) +#define SNVS_LPCR_PK_EN_SHIFT (22U) +#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK) +#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U) +#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U) +#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK) + +/*! @name LPSR - SNVS_LP Status Register */ +#define SNVS_LPSR_MCR_MASK (0x4U) +#define SNVS_LPSR_MCR_SHIFT (2U) +#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) +#define SNVS_LPSR_EO_MASK (0x20000U) +#define SNVS_LPSR_EO_SHIFT (17U) +#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK) +#define SNVS_LPSR_SPO_MASK (0x40000U) +#define SNVS_LPSR_SPO_SHIFT (18U) +#define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK) + +/*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ +#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) +#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) +#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) +#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) +#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) + +/*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ +#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) +#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) + +/*! @name LPGPR - SNVS_LP General-Purpose Register */ +#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR_GPR_SHIFT (0U) +#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) + +/*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ +#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) +#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) +#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) +#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U) +#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U) +#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK) +#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) +#define SNVS_HPVIDR1_IP_ID_SHIFT (16U) +#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) + +/*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ +#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) +#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) +#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) +#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U) +#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U) +#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK) +#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U) +#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U) +#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK) +#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) +#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) +#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) + + +/*! + * @} + */ /* end of group SNVS_Register_Masks */ + + +/* SNVS - Peripheral instance base addresses */ +/** Peripheral SNVS base address */ +#define SNVS_BASE (0x20CC000u) +/** Peripheral SNVS base pointer */ +#define SNVS ((SNVS_Type *)SNVS_BASE) +/** Array initializer of SNVS peripheral base addresses */ +#define SNVS_BASE_ADDRS { SNVS_BASE } +/** Array initializer of SNVS peripheral base pointers */ +#define SNVS_BASE_PTRS { SNVS } +/** Interrupt vectors for the SNVS peripheral type */ +#define SNVS_IRQS { SNVS_IRQn } +#define SNVS_CONSOLIDATED_IRQS { SNVS_Consolidated_IRQn } +#define SNVS_SECURITY_IRQS { SNVS_Security_IRQn } + +/*! + * @} + */ /* end of group SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPBA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPBA_Peripheral_Access_Layer SPBA Peripheral Access Layer + * @{ + */ + +/** SPBA - Register Layout Typedef */ +typedef struct { + __IO uint32_t PRR[32]; /**< Peripheral Rights Register, array offset: 0x0, array step: 0x4 */ +} SPBA_Type; + +/* ---------------------------------------------------------------------------- + -- SPBA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPBA_Register_Masks SPBA Register Masks + * @{ + */ + +/*! @name PRR - Peripheral Rights Register */ +#define SPBA_PRR_RARA_MASK (0x1U) +#define SPBA_PRR_RARA_SHIFT (0U) +#define SPBA_PRR_RARA(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARA_SHIFT)) & SPBA_PRR_RARA_MASK) +#define SPBA_PRR_RARB_MASK (0x2U) +#define SPBA_PRR_RARB_SHIFT (1U) +#define SPBA_PRR_RARB(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARB_SHIFT)) & SPBA_PRR_RARB_MASK) +#define SPBA_PRR_RARC_MASK (0x4U) +#define SPBA_PRR_RARC_SHIFT (2U) +#define SPBA_PRR_RARC(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARC_SHIFT)) & SPBA_PRR_RARC_MASK) +#define SPBA_PRR_ROI_MASK (0x30000U) +#define SPBA_PRR_ROI_SHIFT (16U) +#define SPBA_PRR_ROI(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_ROI_SHIFT)) & SPBA_PRR_ROI_MASK) +#define SPBA_PRR_RMO_MASK (0xC0000000U) +#define SPBA_PRR_RMO_SHIFT (30U) +#define SPBA_PRR_RMO(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RMO_SHIFT)) & SPBA_PRR_RMO_MASK) + +/* The count of SPBA_PRR */ +#define SPBA_PRR_COUNT (32U) + + +/*! + * @} + */ /* end of group SPBA_Register_Masks */ + + +/* SPBA - Peripheral instance base addresses */ +/** Peripheral SPBA base address */ +#define SPBA_BASE (0x203C000u) +/** Peripheral SPBA base pointer */ +#define SPBA ((SPBA_Type *)SPBA_BASE) +/** Array initializer of SPBA peripheral base addresses */ +#define SPBA_BASE_ADDRS { SPBA_BASE } +/** Array initializer of SPBA peripheral base pointers */ +#define SPBA_BASE_PTRS { SPBA } + +/*! + * @} + */ /* end of group SPBA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer + * @{ + */ + +/** SPDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ + __IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */ + __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ + __IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */ + union { /* offset: 0x10 */ + __IO uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */ + __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ + }; + __I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */ + __I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */ + __I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */ + __I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */ + __I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */ + __I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */ + __IO uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */ + __IO uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */ + __IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */ + __IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */ + uint8_t RESERVED_0[8]; + __I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */ + uint8_t RESERVED_1[8]; + __IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */ +} SPDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SPDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Register_Masks SPDIF Register Masks + * @{ + */ + +/*! @name SCR - SPDIF Configuration Register */ +#define SPDIF_SCR_USRC_SEL_MASK (0x3U) +#define SPDIF_SCR_USRC_SEL_SHIFT (0U) +#define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK) +#define SPDIF_SCR_TXSEL_MASK (0x1CU) +#define SPDIF_SCR_TXSEL_SHIFT (2U) +#define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK) +#define SPDIF_SCR_VALCTRL_MASK (0x20U) +#define SPDIF_SCR_VALCTRL_SHIFT (5U) +#define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK) +#define SPDIF_SCR_DMA_TX_EN_MASK (0x100U) +#define SPDIF_SCR_DMA_TX_EN_SHIFT (8U) +#define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK) +#define SPDIF_SCR_DMA_RX_EN_MASK (0x200U) +#define SPDIF_SCR_DMA_RX_EN_SHIFT (9U) +#define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK) +#define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U) +#define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U) +#define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK) +#define SPDIF_SCR_SOFT_RESET_MASK (0x1000U) +#define SPDIF_SCR_SOFT_RESET_SHIFT (12U) +#define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK) +#define SPDIF_SCR_LOW_POWER_MASK (0x2000U) +#define SPDIF_SCR_LOW_POWER_SHIFT (13U) +#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U) +#define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) +#define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U) +#define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U) +#define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK) +#define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U) +#define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U) +#define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK) +#define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U) +#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U) +#define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK) +#define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U) +#define SPDIF_SCR_RXFIFO_RST_SHIFT (21U) +#define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK) +#define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U) +#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U) +#define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK) +#define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) +#define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) +#define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK) + +/*! @name SRCD - CDText Control Register */ +#define SPDIF_SRCD_USYNCMODE_MASK (0x2U) +#define SPDIF_SRCD_USYNCMODE_SHIFT (1U) +#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK) + +/*! @name SRPC - PhaseConfig Register */ +#define SPDIF_SRPC_GAINSEL_MASK (0x38U) +#define SPDIF_SRPC_GAINSEL_SHIFT (3U) +#define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK) +#define SPDIF_SRPC_LOCK_MASK (0x40U) +#define SPDIF_SRPC_LOCK_SHIFT (6U) +#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) +#define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) +#define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) +#define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK) + +/*! @name SIE - InterruptEn Register */ +#define SPDIF_SIE_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIE_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) +#define SPDIF_SIE_TXEM_MASK (0x2U) +#define SPDIF_SIE_TXEM_SHIFT (1U) +#define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK) +#define SPDIF_SIE_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIE_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK) +#define SPDIF_SIE_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIE_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK) +#define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK) +#define SPDIF_SIE_UQERR_MASK (0x20U) +#define SPDIF_SIE_UQERR_SHIFT (5U) +#define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK) +#define SPDIF_SIE_UQSYNC_MASK (0x40U) +#define SPDIF_SIE_UQSYNC_SHIFT (6U) +#define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK) +#define SPDIF_SIE_QRXOV_MASK (0x80U) +#define SPDIF_SIE_QRXOV_SHIFT (7U) +#define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK) +#define SPDIF_SIE_QRXFUL_MASK (0x100U) +#define SPDIF_SIE_QRXFUL_SHIFT (8U) +#define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK) +#define SPDIF_SIE_URXOV_MASK (0x200U) +#define SPDIF_SIE_URXOV_SHIFT (9U) +#define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK) +#define SPDIF_SIE_URXFUL_MASK (0x400U) +#define SPDIF_SIE_URXFUL_SHIFT (10U) +#define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK) +#define SPDIF_SIE_BITERR_MASK (0x4000U) +#define SPDIF_SIE_BITERR_SHIFT (14U) +#define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK) +#define SPDIF_SIE_SYMERR_MASK (0x8000U) +#define SPDIF_SIE_SYMERR_SHIFT (15U) +#define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK) +#define SPDIF_SIE_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIE_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK) +#define SPDIF_SIE_CNEW_MASK (0x20000U) +#define SPDIF_SIE_CNEW_SHIFT (17U) +#define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK) +#define SPDIF_SIE_TXRESYN_MASK (0x40000U) +#define SPDIF_SIE_TXRESYN_SHIFT (18U) +#define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK) +#define SPDIF_SIE_TXUNOV_MASK (0x80000U) +#define SPDIF_SIE_TXUNOV_SHIFT (19U) +#define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK) +#define SPDIF_SIE_LOCK_MASK (0x100000U) +#define SPDIF_SIE_LOCK_SHIFT (20U) +#define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) + +/*! @name SIC - InterruptClear Register */ +#define SPDIF_SIC_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIC_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) +#define SPDIF_SIC_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIC_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK) +#define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK) +#define SPDIF_SIC_UQERR_MASK (0x20U) +#define SPDIF_SIC_UQERR_SHIFT (5U) +#define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK) +#define SPDIF_SIC_UQSYNC_MASK (0x40U) +#define SPDIF_SIC_UQSYNC_SHIFT (6U) +#define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK) +#define SPDIF_SIC_QRXOV_MASK (0x80U) +#define SPDIF_SIC_QRXOV_SHIFT (7U) +#define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK) +#define SPDIF_SIC_URXOV_MASK (0x200U) +#define SPDIF_SIC_URXOV_SHIFT (9U) +#define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK) +#define SPDIF_SIC_BITERR_MASK (0x4000U) +#define SPDIF_SIC_BITERR_SHIFT (14U) +#define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK) +#define SPDIF_SIC_SYMERR_MASK (0x8000U) +#define SPDIF_SIC_SYMERR_SHIFT (15U) +#define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK) +#define SPDIF_SIC_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIC_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK) +#define SPDIF_SIC_CNEW_MASK (0x20000U) +#define SPDIF_SIC_CNEW_SHIFT (17U) +#define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK) +#define SPDIF_SIC_TXRESYN_MASK (0x40000U) +#define SPDIF_SIC_TXRESYN_SHIFT (18U) +#define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK) +#define SPDIF_SIC_TXUNOV_MASK (0x80000U) +#define SPDIF_SIC_TXUNOV_SHIFT (19U) +#define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK) +#define SPDIF_SIC_LOCK_MASK (0x100000U) +#define SPDIF_SIC_LOCK_SHIFT (20U) +#define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) + +/*! @name SIS - InterruptStat Register */ +#define SPDIF_SIS_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIS_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) +#define SPDIF_SIS_TXEM_MASK (0x2U) +#define SPDIF_SIS_TXEM_SHIFT (1U) +#define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK) +#define SPDIF_SIS_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIS_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK) +#define SPDIF_SIS_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIS_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK) +#define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK) +#define SPDIF_SIS_UQERR_MASK (0x20U) +#define SPDIF_SIS_UQERR_SHIFT (5U) +#define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK) +#define SPDIF_SIS_UQSYNC_MASK (0x40U) +#define SPDIF_SIS_UQSYNC_SHIFT (6U) +#define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK) +#define SPDIF_SIS_QRXOV_MASK (0x80U) +#define SPDIF_SIS_QRXOV_SHIFT (7U) +#define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK) +#define SPDIF_SIS_QRXFUL_MASK (0x100U) +#define SPDIF_SIS_QRXFUL_SHIFT (8U) +#define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK) +#define SPDIF_SIS_URXOV_MASK (0x200U) +#define SPDIF_SIS_URXOV_SHIFT (9U) +#define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK) +#define SPDIF_SIS_URXFUL_MASK (0x400U) +#define SPDIF_SIS_URXFUL_SHIFT (10U) +#define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK) +#define SPDIF_SIS_BITERR_MASK (0x4000U) +#define SPDIF_SIS_BITERR_SHIFT (14U) +#define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK) +#define SPDIF_SIS_SYMERR_MASK (0x8000U) +#define SPDIF_SIS_SYMERR_SHIFT (15U) +#define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK) +#define SPDIF_SIS_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIS_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK) +#define SPDIF_SIS_CNEW_MASK (0x20000U) +#define SPDIF_SIS_CNEW_SHIFT (17U) +#define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK) +#define SPDIF_SIS_TXRESYN_MASK (0x40000U) +#define SPDIF_SIS_TXRESYN_SHIFT (18U) +#define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK) +#define SPDIF_SIS_TXUNOV_MASK (0x80000U) +#define SPDIF_SIS_TXUNOV_SHIFT (19U) +#define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK) +#define SPDIF_SIS_LOCK_MASK (0x100000U) +#define SPDIF_SIS_LOCK_SHIFT (20U) +#define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) + +/*! @name SRL - SPDIFRxLeft Register */ +#define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_SRL_RXDATALEFT_SHIFT (0U) +#define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) + +/*! @name SRR - SPDIFRxRight Register */ +#define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_SRR_RXDATARIGHT_SHIFT (0U) +#define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) + +/*! @name SRCSH - SPDIFRxCChannel_h Register */ +#define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) +#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) +#define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) + +/*! @name SRCSL - SPDIFRxCChannel_l Register */ +#define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) +#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) +#define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) + +/*! @name SRU - UchannelRx Register */ +#define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRU_RXUCHANNEL_SHIFT (0U) +#define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) + +/*! @name SRQ - QchannelRx Register */ +#define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) +#define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) + +/*! @name STL - SPDIFTxLeft Register */ +#define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_STL_TXDATALEFT_SHIFT (0U) +#define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) + +/*! @name STR - SPDIFTxRight Register */ +#define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_STR_TXDATARIGHT_SHIFT (0U) +#define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) + +/*! @name STCSCH - SPDIFTxCChannelCons_h Register */ +#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) +#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) +#define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) + +/*! @name STCSCL - SPDIFTxCChannelCons_l Register */ +#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) +#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) +#define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) + +/*! @name SRFM - FreqMeas Register */ +#define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) +#define SPDIF_SRFM_FREQMEAS_SHIFT (0U) +#define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) + +/*! @name STC - SPDIFTxClk Register */ +#define SPDIF_STC_TXCLK_DF_MASK (0x7FU) +#define SPDIF_STC_TXCLK_DF_SHIFT (0U) +#define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK) +#define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U) +#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U) +#define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK) +#define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U) +#define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U) +#define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK) +#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) +#define SPDIF_STC_SYSCLK_DF_SHIFT (11U) +#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) + + +/*! + * @} + */ /* end of group SPDIF_Register_Masks */ + + +/* SPDIF - Peripheral instance base addresses */ +/** Peripheral SPDIF base address */ +#define SPDIF_BASE (0x2004000u) +/** Peripheral SPDIF base pointer */ +#define SPDIF ((SPDIF_Type *)SPDIF_BASE) +/** Array initializer of SPDIF peripheral base addresses */ +#define SPDIF_BASE_ADDRS { SPDIF_BASE } +/** Array initializer of SPDIF peripheral base pointers */ +#define SPDIF_BASE_PTRS { SPDIF } +/** Interrupt vectors for the SPDIF peripheral type */ +#define SPDIF_IRQS { SPDIF_IRQn } + +/*! + * @} + */ /* end of group SPDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer + * @{ + */ + +/** SRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ + __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x4 */ + __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x8 */ + uint8_t RESERVED_0[8]; + __I uint32_t SISR; /**< SRC Interrupt Status Register, offset: 0x14 */ + uint8_t RESERVED_1[4]; + __I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x1C */ + __IO uint32_t GPR[10]; /**< SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x20, array step: 0x4 */ +} SRC_Type; + +/* ---------------------------------------------------------------------------- + -- SRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Register_Masks SRC Register Masks + * @{ + */ + +/*! @name SCR - SRC Control Register */ +#define SRC_SCR_WARM_RESET_ENABLE_MASK (0x1U) +#define SRC_SCR_WARM_RESET_ENABLE_SHIFT (0U) +#define SRC_SCR_WARM_RESET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_WARM_RESET_ENABLE_SHIFT)) & SRC_SCR_WARM_RESET_ENABLE_MASK) +#define SRC_SCR_WARM_RST_BYPASS_COUNT_MASK (0x60U) +#define SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT (5U) +#define SRC_SCR_WARM_RST_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT)) & SRC_SCR_WARM_RST_BYPASS_COUNT_MASK) +#define SRC_SCR_MASK_WDOG_RST_MASK (0x780U) +#define SRC_SCR_MASK_WDOG_RST_SHIFT (7U) +#define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK) +#define SRC_SCR_EIM_RST_MASK (0x800U) +#define SRC_SCR_EIM_RST_SHIFT (11U) +#define SRC_SCR_EIM_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_EIM_RST_SHIFT)) & SRC_SCR_EIM_RST_MASK) +#define SRC_SCR_CORE0_RST_MASK (0x2000U) +#define SRC_SCR_CORE0_RST_SHIFT (13U) +#define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK) +#define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U) +#define SRC_SCR_CORE0_DBG_RST_SHIFT (17U) +#define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK) +#define SRC_SCR_CORES_DBG_RST_MASK (0x200000U) +#define SRC_SCR_CORES_DBG_RST_SHIFT (21U) +#define SRC_SCR_CORES_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORES_DBG_RST_SHIFT)) & SRC_SCR_CORES_DBG_RST_MASK) +#define SRC_SCR_WDOG3_RST_OPTN_MASK (0x1000000U) +#define SRC_SCR_WDOG3_RST_OPTN_SHIFT (24U) +#define SRC_SCR_WDOG3_RST_OPTN(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_WDOG3_RST_OPTN_SHIFT)) & SRC_SCR_WDOG3_RST_OPTN_MASK) +#define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U) +#define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U) +#define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK) +#define SRC_SCR_MIX_RST_STRCH_MASK (0xC000000U) +#define SRC_SCR_MIX_RST_STRCH_SHIFT (26U) +#define SRC_SCR_MIX_RST_STRCH(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MIX_RST_STRCH_SHIFT)) & SRC_SCR_MIX_RST_STRCH_MASK) +#define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U) +#define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U) +#define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK) + +/*! @name SBMR1 - SRC Boot Mode Register 1 */ +#define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU) +#define SRC_SBMR1_BOOT_CFG1_SHIFT (0U) +#define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK) +#define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U) +#define SRC_SBMR1_BOOT_CFG2_SHIFT (8U) +#define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK) +#define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U) +#define SRC_SBMR1_BOOT_CFG3_SHIFT (16U) +#define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK) +#define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U) +#define SRC_SBMR1_BOOT_CFG4_SHIFT (24U) +#define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK) + +/*! @name SRSR - SRC Reset Status Register */ +#define SRC_SRSR_IPP_RESET_B_MASK (0x1U) +#define SRC_SRSR_IPP_RESET_B_SHIFT (0U) +#define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK) +#define SRC_SRSR_CSU_RESET_B_MASK (0x4U) +#define SRC_SRSR_CSU_RESET_B_SHIFT (2U) +#define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK) +#define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U) +#define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U) +#define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK) +#define SRC_SRSR_WDOG_RST_B_MASK (0x10U) +#define SRC_SRSR_WDOG_RST_B_SHIFT (4U) +#define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK) +#define SRC_SRSR_JTAG_RST_B_MASK (0x20U) +#define SRC_SRSR_JTAG_RST_B_SHIFT (5U) +#define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK) +#define SRC_SRSR_JTAG_SW_RST_MASK (0x40U) +#define SRC_SRSR_JTAG_SW_RST_SHIFT (6U) +#define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK) +#define SRC_SRSR_WDOG3_RST_B_MASK (0x80U) +#define SRC_SRSR_WDOG3_RST_B_SHIFT (7U) +#define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK) +#define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U) +#define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U) +#define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK) +#define SRC_SRSR_WARM_BOOT_MASK (0x10000U) +#define SRC_SRSR_WARM_BOOT_SHIFT (16U) +#define SRC_SRSR_WARM_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WARM_BOOT_SHIFT)) & SRC_SRSR_WARM_BOOT_MASK) + +/*! @name SISR - SRC Interrupt Status Register */ +#define SRC_SISR_CORE0_WDOG_RST_REQ_MASK (0x20U) +#define SRC_SISR_CORE0_WDOG_RST_REQ_SHIFT (5U) +#define SRC_SISR_CORE0_WDOG_RST_REQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_CORE0_WDOG_RST_REQ_SHIFT)) & SRC_SISR_CORE0_WDOG_RST_REQ_MASK) + +/*! @name SBMR2 - SRC Boot Mode Register 2 */ +#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U) +#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U) +#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) +#define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U) +#define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U) +#define SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK) +#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U) +#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U) +#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK) +#define SRC_SBMR2_BMOD_MASK (0x3000000U) +#define SRC_SBMR2_BMOD_SHIFT (24U) +#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) + +/*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */ +#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) +#define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK) + +/* The count of SRC_GPR */ +#define SRC_GPR_COUNT (10U) + + +/*! + * @} + */ /* end of group SRC_Register_Masks */ + + +/* SRC - Peripheral instance base addresses */ +/** Peripheral SRC base address */ +#define SRC_BASE (0x20D8000u) +/** Peripheral SRC base pointer */ +#define SRC ((SRC_Type *)SRC_BASE) +/** Array initializer of SRC peripheral base addresses */ +#define SRC_BASE_ADDRS { SRC_BASE } +/** Array initializer of SRC peripheral base pointers */ +#define SRC_BASE_PTRS { SRC } +/** Interrupt vectors for the SRC peripheral type */ +#define SRC_IRQS { SRC_IRQn } +#define SRC_COMBINED_IRQS { SRC_Combined_IRQn } +/* Backward compatibility */ +#define SRC_SCR_WRE_MASK SRC_SCR_WARM_RESET_ENABLE_MASK +#define SRC_SCR_WRE_SHIFT SRC_SCR_WARM_RESET_ENABLE_SHIFT +#define SRC_SCR_WRE(x) SRC_SCR_WARM_RESET_ENABLE(x) +#define SRC_SCR_WRBC_MASK SRC_SCR_WARM_RST_BYPASS_COUNT_MASK +#define SRC_SCR_WRBC_SHIFT SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT +#define SRC_SCR_WRBC(x) SRC_SCR_WARM_RST_BYPASS_COUNT(x) +#define SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASK +#define SRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFT +#define SRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x) +#define SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASK +#define SRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFT +#define SRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x) +#define SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASK +#define SRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFT +#define SRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x) +#define SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASK +#define SRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFT +#define SRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x) +#define SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASK +#define SRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFT +#define SRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x) +#define SRC_SRSR_WBI_MASK SRC_SRSR_WARM_BOOT_MASK +#define SRC_SRSR_WBI_SHIFT SRC_SRSR_WARM_BOOT_SHIFT +#define SRC_SRSR_WBI(x) SRC_SRSR_WARM_BOOT(x) +/* Extra definition */ +#define SRC_SRSR_W1C_BITS_MASK (SRC_SRSR_WDOG3_RST_B_MASK \ + | SRC_SRSR_JTAG_SW_RST_MASK \ + | SRC_SRSR_JTAG_RST_B_MASK \ + | SRC_SRSR_WDOG_RST_B_MASK \ + | SRC_SRSR_IPP_USER_RESET_B_MASK \ + | SRC_SRSR_CSU_RESET_B_MASK \ + | SRC_SRSR_IPP_RESET_B_MASK) + + +/*! + * @} + */ /* end of group SRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TEMPMON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer + * @{ + */ + +/** TEMPMON - Register Layout Typedef */ +typedef struct { + __IO uint32_t TEMPSENSE0; /**< Tempsensor Control Register 0, offset: 0x0 */ + __IO uint32_t TEMPSENSE0_SET; /**< Tempsensor Control Register 0, offset: 0x4 */ + __IO uint32_t TEMPSENSE0_CLR; /**< Tempsensor Control Register 0, offset: 0x8 */ + __IO uint32_t TEMPSENSE0_TOG; /**< Tempsensor Control Register 0, offset: 0xC */ + __IO uint32_t TEMPSENSE1; /**< Tempsensor Control Register 1, offset: 0x10 */ + __IO uint32_t TEMPSENSE1_SET; /**< Tempsensor Control Register 1, offset: 0x14 */ + __IO uint32_t TEMPSENSE1_CLR; /**< Tempsensor Control Register 1, offset: 0x18 */ + __IO uint32_t TEMPSENSE1_TOG; /**< Tempsensor Control Register 1, offset: 0x1C */ + uint8_t RESERVED_0[240]; + __IO uint32_t TEMPSENSE2; /**< Tempsensor Control Register 2, offset: 0x110 */ + __IO uint32_t TEMPSENSE2_SET; /**< Tempsensor Control Register 2, offset: 0x114 */ + __IO uint32_t TEMPSENSE2_CLR; /**< Tempsensor Control Register 2, offset: 0x118 */ + __IO uint32_t TEMPSENSE2_TOG; /**< Tempsensor Control Register 2, offset: 0x11C */ +} TEMPMON_Type; + +/* ---------------------------------------------------------------------------- + -- TEMPMON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks + * @{ + */ + +/*! @name TEMPSENSE0 - Tempsensor Control Register 0 */ +#define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE0_SET - Tempsensor Control Register 0 */ +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE0_CLR - Tempsensor Control Register 0 */ +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE0_TOG - Tempsensor Control Register 0 */ +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE1 - Tempsensor Control Register 1 */ +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK) + +/*! @name TEMPSENSE1_SET - Tempsensor Control Register 1 */ +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK) + +/*! @name TEMPSENSE1_CLR - Tempsensor Control Register 1 */ +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) + +/*! @name TEMPSENSE1_TOG - Tempsensor Control Register 1 */ +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) + +/*! @name TEMPSENSE2 - Tempsensor Control Register 2 */ +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE2_SET - Tempsensor Control Register 2 */ +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE2_CLR - Tempsensor Control Register 2 */ +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE2_TOG - Tempsensor Control Register 2 */ +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK) + + +/*! + * @} + */ /* end of group TEMPMON_Register_Masks */ + + +/* TEMPMON - Peripheral instance base addresses */ +/** Peripheral TEMPMON base address */ +#define TEMPMON_BASE (0x20C8180u) +/** Peripheral TEMPMON base pointer */ +#define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE) +/** Array initializer of TEMPMON peripheral base addresses */ +#define TEMPMON_BASE_ADDRS { TEMPMON_BASE } +/** Array initializer of TEMPMON peripheral base pointers */ +#define TEMPMON_BASE_PTRS { TEMPMON } +/** Interrupt vectors for the TEMPMON peripheral type */ +#define TEMPMON_IRQS { TEMPMON_IRQn } + +/*! + * @} + */ /* end of group TEMPMON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSC_Peripheral_Access_Layer TSC Peripheral Access Layer + * @{ + */ + +/** TSC - Register Layout Typedef */ +typedef struct { + __IO uint32_t BASIC_SETTING; /**< PS Input Buffer Address, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PS_INPUT_BUFFER_ADDR; /**< PS Input Buffer Address, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t FLOW_CONTROL; /**< Flow Control, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __I uint32_t MEASEURE_VALUE; /**< Measure Value, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __IO uint32_t INT_EN; /**< Interrupt Enable, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t INT_SIG_EN; /**< Interrupt Signal Enable, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t INT_STATUS; /**< Intterrupt Status, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t DEBUG_MODE; /**< , offset: 0x70 */ + uint8_t RESERVED_7[12]; + __IO uint32_t DEBUG_MODE2; /**< , offset: 0x80 */ +} TSC_Type; + +/* ---------------------------------------------------------------------------- + -- TSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSC_Register_Masks TSC Register Masks + * @{ + */ + +/*! @name BASIC_SETTING - PS Input Buffer Address */ +#define TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U) +#define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U) +#define TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK) +#define TSC_BASIC_SETTING__4_5_WIRE_MASK (0x10U) +#define TSC_BASIC_SETTING__4_5_WIRE_SHIFT (4U) +#define TSC_BASIC_SETTING__4_5_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING__4_5_WIRE_SHIFT)) & TSC_BASIC_SETTING__4_5_WIRE_MASK) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK) + +/*! @name PS_INPUT_BUFFER_ADDR - PS Input Buffer Address */ +#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU) +#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_SHIFT (0U) +#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_SHIFT)) & TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_MASK) + +/*! @name FLOW_CONTROL - Flow Control */ +#define TSC_FLOW_CONTROL_SW_RST_MASK (0x1U) +#define TSC_FLOW_CONTROL_SW_RST_SHIFT (0U) +#define TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK) +#define TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U) +#define TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U) +#define TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK) +#define TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U) +#define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U) +#define TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK) +#define TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U) +#define TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U) +#define TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK) +#define TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U) +#define TSC_FLOW_CONTROL_DISABLE_SHIFT (16U) +#define TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK) + +/*! @name MEASEURE_VALUE - Measure Value */ +#define TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU) +#define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U) +#define TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK) +#define TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U) +#define TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U) +#define TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK) + +/*! @name INT_EN - Interrupt Enable */ +#define TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U) +#define TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U) +#define TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK) +#define TSC_INT_EN_DETECT_INT_EN_MASK (0x10U) +#define TSC_INT_EN_DETECT_INT_EN_SHIFT (4U) +#define TSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK) +#define TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U) +#define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U) +#define TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK) + +/*! @name INT_SIG_EN - Interrupt Signal Enable */ +#define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U) +#define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U) +#define TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK) +#define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U) +#define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U) +#define TSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK) +#define TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U) +#define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U) +#define TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK) + +/*! @name INT_STATUS - Intterrupt Status */ +#define TSC_INT_STATUS_MEASURE_MASK (0x1U) +#define TSC_INT_STATUS_MEASURE_SHIFT (0U) +#define TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK) +#define TSC_INT_STATUS_DETECT_MASK (0x10U) +#define TSC_INT_STATUS_DETECT_SHIFT (4U) +#define TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK) +#define TSC_INT_STATUS_VALID_MASK (0x100U) +#define TSC_INT_STATUS_VALID_SHIFT (8U) +#define TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK) +#define TSC_INT_STATUS_IDLE_SW_MASK (0x1000U) +#define TSC_INT_STATUS_IDLE_SW_SHIFT (12U) +#define TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK) + +/*! @name DEBUG_MODE - */ +#define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU) +#define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U) +#define TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_MASK (0x1000U) +#define TSC_DEBUG_MODE_ADC_COCO_SHIFT (12U) +#define TSC_DEBUG_MODE_ADC_COCO(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK) +#define TSC_DEBUG_MODE_EXT_HWTS_MASK (0x1F0000U) +#define TSC_DEBUG_MODE_EXT_HWTS_SHIFT (16U) +#define TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK) +#define TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U) +#define TSC_DEBUG_MODE_TRIGGER_SHIFT (24U) +#define TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK) +#define TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U) +#define TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U) +#define TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK) + +/*! @name DEBUG_MODE2 - */ +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U) +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U) +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK) +#define TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U) +#define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U) +#define TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK) +#define TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U) +#define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U) +#define TSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK) +#define TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U) +#define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U) +#define TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK) + + +/*! + * @} + */ /* end of group TSC_Register_Masks */ + + +/* TSC - Peripheral instance base addresses */ +/** Peripheral TSC base address */ +#define TSC_BASE (0x2040000u) +/** Peripheral TSC base pointer */ +#define TSC ((TSC_Type *)TSC_BASE) +/** Array initializer of TSC peripheral base addresses */ +#define TSC_BASE_ADDRS { TSC_BASE } +/** Array initializer of TSC peripheral base pointers */ +#define TSC_BASE_PTRS { TSC } +/** Interrupt vectors for the TSC peripheral type */ +#define TSC_IRQS { TSC_IRQn } + +/*! + * @} + */ /* end of group TSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer + * @{ + */ + +/** UART - Register Layout Typedef */ +typedef struct { + __I uint32_t URXD; /**< UART Receiver Register, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t UTXD; /**< UART Transmitter Register, offset: 0x40 */ + uint8_t RESERVED_1[60]; + __IO uint32_t UCR1; /**< UART Control Register 1, offset: 0x80 */ + __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ + __IO uint32_t UCR3; /**< UART Control Register 3, offset: 0x88 */ + __IO uint32_t UCR4; /**< UART Control Register 4, offset: 0x8C */ + __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ + __IO uint32_t USR1; /**< UART Status Register 1, offset: 0x94 */ + __IO uint32_t USR2; /**< UART Status Register 2, offset: 0x98 */ + __IO uint32_t UESC; /**< UART Escape Character Register, offset: 0x9C */ + __IO uint32_t UTIM; /**< UART Escape Timer Register, offset: 0xA0 */ + __IO uint32_t UBIR; /**< UART BRM Incremental Register, offset: 0xA4 */ + __IO uint32_t UBMR; /**< UART BRM Modulator Register, offset: 0xA8 */ + __I uint32_t UBRC; /**< UART Baud Rate Count Register, offset: 0xAC */ + __IO uint32_t ONEMS; /**< UART One Millisecond Register, offset: 0xB0 */ + __IO uint32_t UTS; /**< UART Test Register, offset: 0xB4 */ + __IO uint32_t UMCR; /**< UART RS-485 Mode Control Register, offset: 0xB8 */ +} UART_Type; + +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/*! @name URXD - UART Receiver Register */ +#define UART_URXD_RX_DATA_MASK (0xFFU) +#define UART_URXD_RX_DATA_SHIFT (0U) +#define UART_URXD_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_RX_DATA_SHIFT)) & UART_URXD_RX_DATA_MASK) +#define UART_URXD_PRERR_MASK (0x400U) +#define UART_URXD_PRERR_SHIFT (10U) +#define UART_URXD_PRERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_PRERR_SHIFT)) & UART_URXD_PRERR_MASK) +#define UART_URXD_BRK_MASK (0x800U) +#define UART_URXD_BRK_SHIFT (11U) +#define UART_URXD_BRK(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_BRK_SHIFT)) & UART_URXD_BRK_MASK) +#define UART_URXD_FRMERR_MASK (0x1000U) +#define UART_URXD_FRMERR_SHIFT (12U) +#define UART_URXD_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_FRMERR_SHIFT)) & UART_URXD_FRMERR_MASK) +#define UART_URXD_OVRRUN_MASK (0x2000U) +#define UART_URXD_OVRRUN_SHIFT (13U) +#define UART_URXD_OVRRUN(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_OVRRUN_SHIFT)) & UART_URXD_OVRRUN_MASK) +#define UART_URXD_ERR_MASK (0x4000U) +#define UART_URXD_ERR_SHIFT (14U) +#define UART_URXD_ERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_ERR_SHIFT)) & UART_URXD_ERR_MASK) +#define UART_URXD_CHARRDY_MASK (0x8000U) +#define UART_URXD_CHARRDY_SHIFT (15U) +#define UART_URXD_CHARRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_CHARRDY_SHIFT)) & UART_URXD_CHARRDY_MASK) + +/*! @name UTXD - UART Transmitter Register */ +#define UART_UTXD_TX_DATA_MASK (0xFFU) +#define UART_UTXD_TX_DATA_SHIFT (0U) +#define UART_UTXD_TX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_UTXD_TX_DATA_SHIFT)) & UART_UTXD_TX_DATA_MASK) + +/*! @name UCR1 - UART Control Register 1 */ +#define UART_UCR1_UARTEN_MASK (0x1U) +#define UART_UCR1_UARTEN_SHIFT (0U) +#define UART_UCR1_UARTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_UARTEN_SHIFT)) & UART_UCR1_UARTEN_MASK) +#define UART_UCR1_DOZE_MASK (0x2U) +#define UART_UCR1_DOZE_SHIFT (1U) +#define UART_UCR1_DOZE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_DOZE_SHIFT)) & UART_UCR1_DOZE_MASK) +#define UART_UCR1_ATDMAEN_MASK (0x4U) +#define UART_UCR1_ATDMAEN_SHIFT (2U) +#define UART_UCR1_ATDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ATDMAEN_SHIFT)) & UART_UCR1_ATDMAEN_MASK) +#define UART_UCR1_TXDMAEN_MASK (0x8U) +#define UART_UCR1_TXDMAEN_SHIFT (3U) +#define UART_UCR1_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXDMAEN_SHIFT)) & UART_UCR1_TXDMAEN_MASK) +#define UART_UCR1_SNDBRK_MASK (0x10U) +#define UART_UCR1_SNDBRK_SHIFT (4U) +#define UART_UCR1_SNDBRK(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_SNDBRK_SHIFT)) & UART_UCR1_SNDBRK_MASK) +#define UART_UCR1_RTSDEN_MASK (0x20U) +#define UART_UCR1_RTSDEN_SHIFT (5U) +#define UART_UCR1_RTSDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RTSDEN_SHIFT)) & UART_UCR1_RTSDEN_MASK) +#define UART_UCR1_TXMPTYEN_MASK (0x40U) +#define UART_UCR1_TXMPTYEN_SHIFT (6U) +#define UART_UCR1_TXMPTYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXMPTYEN_SHIFT)) & UART_UCR1_TXMPTYEN_MASK) +#define UART_UCR1_IREN_MASK (0x80U) +#define UART_UCR1_IREN_SHIFT (7U) +#define UART_UCR1_IREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IREN_SHIFT)) & UART_UCR1_IREN_MASK) +#define UART_UCR1_RXDMAEN_MASK (0x100U) +#define UART_UCR1_RXDMAEN_SHIFT (8U) +#define UART_UCR1_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RXDMAEN_SHIFT)) & UART_UCR1_RXDMAEN_MASK) +#define UART_UCR1_RRDYEN_MASK (0x200U) +#define UART_UCR1_RRDYEN_SHIFT (9U) +#define UART_UCR1_RRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RRDYEN_SHIFT)) & UART_UCR1_RRDYEN_MASK) +#define UART_UCR1_ICD_MASK (0xC00U) +#define UART_UCR1_ICD_SHIFT (10U) +#define UART_UCR1_ICD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ICD_SHIFT)) & UART_UCR1_ICD_MASK) +#define UART_UCR1_IDEN_MASK (0x1000U) +#define UART_UCR1_IDEN_SHIFT (12U) +#define UART_UCR1_IDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IDEN_SHIFT)) & UART_UCR1_IDEN_MASK) +#define UART_UCR1_TRDYEN_MASK (0x2000U) +#define UART_UCR1_TRDYEN_SHIFT (13U) +#define UART_UCR1_TRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TRDYEN_SHIFT)) & UART_UCR1_TRDYEN_MASK) +#define UART_UCR1_ADBR_MASK (0x4000U) +#define UART_UCR1_ADBR_SHIFT (14U) +#define UART_UCR1_ADBR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADBR_SHIFT)) & UART_UCR1_ADBR_MASK) +#define UART_UCR1_ADEN_MASK (0x8000U) +#define UART_UCR1_ADEN_SHIFT (15U) +#define UART_UCR1_ADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADEN_SHIFT)) & UART_UCR1_ADEN_MASK) + +/*! @name UCR2 - UART Control Register 2 */ +#define UART_UCR2_SRST_MASK (0x1U) +#define UART_UCR2_SRST_SHIFT (0U) +#define UART_UCR2_SRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_SRST_SHIFT)) & UART_UCR2_SRST_MASK) +#define UART_UCR2_RXEN_MASK (0x2U) +#define UART_UCR2_RXEN_SHIFT (1U) +#define UART_UCR2_RXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RXEN_SHIFT)) & UART_UCR2_RXEN_MASK) +#define UART_UCR2_TXEN_MASK (0x4U) +#define UART_UCR2_TXEN_SHIFT (2U) +#define UART_UCR2_TXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_TXEN_SHIFT)) & UART_UCR2_TXEN_MASK) +#define UART_UCR2_ATEN_MASK (0x8U) +#define UART_UCR2_ATEN_SHIFT (3U) +#define UART_UCR2_ATEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ATEN_SHIFT)) & UART_UCR2_ATEN_MASK) +#define UART_UCR2_RTSEN_MASK (0x10U) +#define UART_UCR2_RTSEN_SHIFT (4U) +#define UART_UCR2_RTSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTSEN_SHIFT)) & UART_UCR2_RTSEN_MASK) +#define UART_UCR2_WS_MASK (0x20U) +#define UART_UCR2_WS_SHIFT (5U) +#define UART_UCR2_WS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_WS_SHIFT)) & UART_UCR2_WS_MASK) +#define UART_UCR2_STPB_MASK (0x40U) +#define UART_UCR2_STPB_SHIFT (6U) +#define UART_UCR2_STPB(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_STPB_SHIFT)) & UART_UCR2_STPB_MASK) +#define UART_UCR2_PROE_MASK (0x80U) +#define UART_UCR2_PROE_SHIFT (7U) +#define UART_UCR2_PROE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PROE_SHIFT)) & UART_UCR2_PROE_MASK) +#define UART_UCR2_PREN_MASK (0x100U) +#define UART_UCR2_PREN_SHIFT (8U) +#define UART_UCR2_PREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PREN_SHIFT)) & UART_UCR2_PREN_MASK) +#define UART_UCR2_RTEC_MASK (0x600U) +#define UART_UCR2_RTEC_SHIFT (9U) +#define UART_UCR2_RTEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTEC_SHIFT)) & UART_UCR2_RTEC_MASK) +#define UART_UCR2_ESCEN_MASK (0x800U) +#define UART_UCR2_ESCEN_SHIFT (11U) +#define UART_UCR2_ESCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCEN_SHIFT)) & UART_UCR2_ESCEN_MASK) +#define UART_UCR2_CTS_MASK (0x1000U) +#define UART_UCR2_CTS_SHIFT (12U) +#define UART_UCR2_CTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTS_SHIFT)) & UART_UCR2_CTS_MASK) +#define UART_UCR2_CTSC_MASK (0x2000U) +#define UART_UCR2_CTSC_SHIFT (13U) +#define UART_UCR2_CTSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTSC_SHIFT)) & UART_UCR2_CTSC_MASK) +#define UART_UCR2_IRTS_MASK (0x4000U) +#define UART_UCR2_IRTS_SHIFT (14U) +#define UART_UCR2_IRTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_IRTS_SHIFT)) & UART_UCR2_IRTS_MASK) +#define UART_UCR2_ESCI_MASK (0x8000U) +#define UART_UCR2_ESCI_SHIFT (15U) +#define UART_UCR2_ESCI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCI_SHIFT)) & UART_UCR2_ESCI_MASK) + +/*! @name UCR3 - UART Control Register 3 */ +#define UART_UCR3_ACIEN_MASK (0x1U) +#define UART_UCR3_ACIEN_SHIFT (0U) +#define UART_UCR3_ACIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ACIEN_SHIFT)) & UART_UCR3_ACIEN_MASK) +#define UART_UCR3_INVT_MASK (0x2U) +#define UART_UCR3_INVT_SHIFT (1U) +#define UART_UCR3_INVT(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_INVT_SHIFT)) & UART_UCR3_INVT_MASK) +#define UART_UCR3_RXDMUXSEL_MASK (0x4U) +#define UART_UCR3_RXDMUXSEL_SHIFT (2U) +#define UART_UCR3_RXDMUXSEL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDMUXSEL_SHIFT)) & UART_UCR3_RXDMUXSEL_MASK) +#define UART_UCR3_DTRDEN_MASK (0x8U) +#define UART_UCR3_DTRDEN_SHIFT (3U) +#define UART_UCR3_DTRDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTRDEN_SHIFT)) & UART_UCR3_DTRDEN_MASK) +#define UART_UCR3_AWAKEN_MASK (0x10U) +#define UART_UCR3_AWAKEN_SHIFT (4U) +#define UART_UCR3_AWAKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AWAKEN_SHIFT)) & UART_UCR3_AWAKEN_MASK) +#define UART_UCR3_AIRINTEN_MASK (0x20U) +#define UART_UCR3_AIRINTEN_SHIFT (5U) +#define UART_UCR3_AIRINTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AIRINTEN_SHIFT)) & UART_UCR3_AIRINTEN_MASK) +#define UART_UCR3_RXDSEN_MASK (0x40U) +#define UART_UCR3_RXDSEN_SHIFT (6U) +#define UART_UCR3_RXDSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDSEN_SHIFT)) & UART_UCR3_RXDSEN_MASK) +#define UART_UCR3_ADNIMP_MASK (0x80U) +#define UART_UCR3_ADNIMP_SHIFT (7U) +#define UART_UCR3_ADNIMP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ADNIMP_SHIFT)) & UART_UCR3_ADNIMP_MASK) +#define UART_UCR3_RI_MASK (0x100U) +#define UART_UCR3_RI_SHIFT (8U) +#define UART_UCR3_RI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RI_SHIFT)) & UART_UCR3_RI_MASK) +#define UART_UCR3_DCD_MASK (0x200U) +#define UART_UCR3_DCD_SHIFT (9U) +#define UART_UCR3_DCD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DCD_SHIFT)) & UART_UCR3_DCD_MASK) +#define UART_UCR3_DSR_MASK (0x400U) +#define UART_UCR3_DSR_SHIFT (10U) +#define UART_UCR3_DSR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DSR_SHIFT)) & UART_UCR3_DSR_MASK) +#define UART_UCR3_FRAERREN_MASK (0x800U) +#define UART_UCR3_FRAERREN_SHIFT (11U) +#define UART_UCR3_FRAERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_FRAERREN_SHIFT)) & UART_UCR3_FRAERREN_MASK) +#define UART_UCR3_PARERREN_MASK (0x1000U) +#define UART_UCR3_PARERREN_SHIFT (12U) +#define UART_UCR3_PARERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_PARERREN_SHIFT)) & UART_UCR3_PARERREN_MASK) +#define UART_UCR3_DTREN_MASK (0x2000U) +#define UART_UCR3_DTREN_SHIFT (13U) +#define UART_UCR3_DTREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTREN_SHIFT)) & UART_UCR3_DTREN_MASK) +#define UART_UCR3_DPEC_MASK (0xC000U) +#define UART_UCR3_DPEC_SHIFT (14U) +#define UART_UCR3_DPEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DPEC_SHIFT)) & UART_UCR3_DPEC_MASK) + +/*! @name UCR4 - UART Control Register 4 */ +#define UART_UCR4_DREN_MASK (0x1U) +#define UART_UCR4_DREN_SHIFT (0U) +#define UART_UCR4_DREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_DREN_SHIFT)) & UART_UCR4_DREN_MASK) +#define UART_UCR4_OREN_MASK (0x2U) +#define UART_UCR4_OREN_SHIFT (1U) +#define UART_UCR4_OREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_OREN_SHIFT)) & UART_UCR4_OREN_MASK) +#define UART_UCR4_BKEN_MASK (0x4U) +#define UART_UCR4_BKEN_SHIFT (2U) +#define UART_UCR4_BKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_BKEN_SHIFT)) & UART_UCR4_BKEN_MASK) +#define UART_UCR4_TCEN_MASK (0x8U) +#define UART_UCR4_TCEN_SHIFT (3U) +#define UART_UCR4_TCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_TCEN_SHIFT)) & UART_UCR4_TCEN_MASK) +#define UART_UCR4_LPBYP_MASK (0x10U) +#define UART_UCR4_LPBYP_SHIFT (4U) +#define UART_UCR4_LPBYP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_LPBYP_SHIFT)) & UART_UCR4_LPBYP_MASK) +#define UART_UCR4_IRSC_MASK (0x20U) +#define UART_UCR4_IRSC_SHIFT (5U) +#define UART_UCR4_IRSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IRSC_SHIFT)) & UART_UCR4_IRSC_MASK) +#define UART_UCR4_IDDMAEN_MASK (0x40U) +#define UART_UCR4_IDDMAEN_SHIFT (6U) +#define UART_UCR4_IDDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IDDMAEN_SHIFT)) & UART_UCR4_IDDMAEN_MASK) +#define UART_UCR4_WKEN_MASK (0x80U) +#define UART_UCR4_WKEN_SHIFT (7U) +#define UART_UCR4_WKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_WKEN_SHIFT)) & UART_UCR4_WKEN_MASK) +#define UART_UCR4_ENIRI_MASK (0x100U) +#define UART_UCR4_ENIRI_SHIFT (8U) +#define UART_UCR4_ENIRI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_ENIRI_SHIFT)) & UART_UCR4_ENIRI_MASK) +#define UART_UCR4_INVR_MASK (0x200U) +#define UART_UCR4_INVR_SHIFT (9U) +#define UART_UCR4_INVR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_INVR_SHIFT)) & UART_UCR4_INVR_MASK) +#define UART_UCR4_CTSTL_MASK (0xFC00U) +#define UART_UCR4_CTSTL_SHIFT (10U) +#define UART_UCR4_CTSTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_CTSTL_SHIFT)) & UART_UCR4_CTSTL_MASK) + +/*! @name UFCR - UART FIFO Control Register */ +#define UART_UFCR_RXTL_MASK (0x3FU) +#define UART_UFCR_RXTL_SHIFT (0U) +#define UART_UFCR_RXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RXTL_SHIFT)) & UART_UFCR_RXTL_MASK) +#define UART_UFCR_DCEDTE_MASK (0x40U) +#define UART_UFCR_DCEDTE_SHIFT (6U) +#define UART_UFCR_DCEDTE(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_DCEDTE_SHIFT)) & UART_UFCR_DCEDTE_MASK) +#define UART_UFCR_RFDIV_MASK (0x380U) +#define UART_UFCR_RFDIV_SHIFT (7U) +#define UART_UFCR_RFDIV(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RFDIV_SHIFT)) & UART_UFCR_RFDIV_MASK) +#define UART_UFCR_TXTL_MASK (0xFC00U) +#define UART_UFCR_TXTL_SHIFT (10U) +#define UART_UFCR_TXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_TXTL_SHIFT)) & UART_UFCR_TXTL_MASK) + +/*! @name USR1 - UART Status Register 1 */ +#define UART_USR1_SAD_MASK (0x8U) +#define UART_USR1_SAD_SHIFT (3U) +#define UART_USR1_SAD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_SAD_SHIFT)) & UART_USR1_SAD_MASK) +#define UART_USR1_AWAKE_MASK (0x10U) +#define UART_USR1_AWAKE_SHIFT (4U) +#define UART_USR1_AWAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AWAKE_SHIFT)) & UART_USR1_AWAKE_MASK) +#define UART_USR1_AIRINT_MASK (0x20U) +#define UART_USR1_AIRINT_SHIFT (5U) +#define UART_USR1_AIRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AIRINT_SHIFT)) & UART_USR1_AIRINT_MASK) +#define UART_USR1_RXDS_MASK (0x40U) +#define UART_USR1_RXDS_SHIFT (6U) +#define UART_USR1_RXDS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RXDS_SHIFT)) & UART_USR1_RXDS_MASK) +#define UART_USR1_DTRD_MASK (0x80U) +#define UART_USR1_DTRD_SHIFT (7U) +#define UART_USR1_DTRD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_DTRD_SHIFT)) & UART_USR1_DTRD_MASK) +#define UART_USR1_AGTIM_MASK (0x100U) +#define UART_USR1_AGTIM_SHIFT (8U) +#define UART_USR1_AGTIM(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AGTIM_SHIFT)) & UART_USR1_AGTIM_MASK) +#define UART_USR1_RRDY_MASK (0x200U) +#define UART_USR1_RRDY_SHIFT (9U) +#define UART_USR1_RRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RRDY_SHIFT)) & UART_USR1_RRDY_MASK) +#define UART_USR1_FRAMERR_MASK (0x400U) +#define UART_USR1_FRAMERR_SHIFT (10U) +#define UART_USR1_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_FRAMERR_SHIFT)) & UART_USR1_FRAMERR_MASK) +#define UART_USR1_ESCF_MASK (0x800U) +#define UART_USR1_ESCF_SHIFT (11U) +#define UART_USR1_ESCF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_ESCF_SHIFT)) & UART_USR1_ESCF_MASK) +#define UART_USR1_RTSD_MASK (0x1000U) +#define UART_USR1_RTSD_SHIFT (12U) +#define UART_USR1_RTSD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSD_SHIFT)) & UART_USR1_RTSD_MASK) +#define UART_USR1_TRDY_MASK (0x2000U) +#define UART_USR1_TRDY_SHIFT (13U) +#define UART_USR1_TRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_TRDY_SHIFT)) & UART_USR1_TRDY_MASK) +#define UART_USR1_RTSS_MASK (0x4000U) +#define UART_USR1_RTSS_SHIFT (14U) +#define UART_USR1_RTSS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSS_SHIFT)) & UART_USR1_RTSS_MASK) +#define UART_USR1_PARITYERR_MASK (0x8000U) +#define UART_USR1_PARITYERR_SHIFT (15U) +#define UART_USR1_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_PARITYERR_SHIFT)) & UART_USR1_PARITYERR_MASK) + +/*! @name USR2 - UART Status Register 2 */ +#define UART_USR2_RDR_MASK (0x1U) +#define UART_USR2_RDR_SHIFT (0U) +#define UART_USR2_RDR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RDR_SHIFT)) & UART_USR2_RDR_MASK) +#define UART_USR2_ORE_MASK (0x2U) +#define UART_USR2_ORE_SHIFT (1U) +#define UART_USR2_ORE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ORE_SHIFT)) & UART_USR2_ORE_MASK) +#define UART_USR2_BRCD_MASK (0x4U) +#define UART_USR2_BRCD_SHIFT (2U) +#define UART_USR2_BRCD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_BRCD_SHIFT)) & UART_USR2_BRCD_MASK) +#define UART_USR2_TXDC_MASK (0x8U) +#define UART_USR2_TXDC_SHIFT (3U) +#define UART_USR2_TXDC(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXDC_SHIFT)) & UART_USR2_TXDC_MASK) +#define UART_USR2_RTSF_MASK (0x10U) +#define UART_USR2_RTSF_SHIFT (4U) +#define UART_USR2_RTSF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RTSF_SHIFT)) & UART_USR2_RTSF_MASK) +#define UART_USR2_DCDIN_MASK (0x20U) +#define UART_USR2_DCDIN_SHIFT (5U) +#define UART_USR2_DCDIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDIN_SHIFT)) & UART_USR2_DCDIN_MASK) +#define UART_USR2_DCDDELT_MASK (0x40U) +#define UART_USR2_DCDDELT_SHIFT (6U) +#define UART_USR2_DCDDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDDELT_SHIFT)) & UART_USR2_DCDDELT_MASK) +#define UART_USR2_WAKE_MASK (0x80U) +#define UART_USR2_WAKE_SHIFT (7U) +#define UART_USR2_WAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_WAKE_SHIFT)) & UART_USR2_WAKE_MASK) +#define UART_USR2_IRINT_MASK (0x100U) +#define UART_USR2_IRINT_SHIFT (8U) +#define UART_USR2_IRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IRINT_SHIFT)) & UART_USR2_IRINT_MASK) +#define UART_USR2_RIIN_MASK (0x200U) +#define UART_USR2_RIIN_SHIFT (9U) +#define UART_USR2_RIIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIIN_SHIFT)) & UART_USR2_RIIN_MASK) +#define UART_USR2_RIDELT_MASK (0x400U) +#define UART_USR2_RIDELT_SHIFT (10U) +#define UART_USR2_RIDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIDELT_SHIFT)) & UART_USR2_RIDELT_MASK) +#define UART_USR2_ACST_MASK (0x800U) +#define UART_USR2_ACST_SHIFT (11U) +#define UART_USR2_ACST(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ACST_SHIFT)) & UART_USR2_ACST_MASK) +#define UART_USR2_IDLE_MASK (0x1000U) +#define UART_USR2_IDLE_SHIFT (12U) +#define UART_USR2_IDLE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IDLE_SHIFT)) & UART_USR2_IDLE_MASK) +#define UART_USR2_DTRF_MASK (0x2000U) +#define UART_USR2_DTRF_SHIFT (13U) +#define UART_USR2_DTRF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DTRF_SHIFT)) & UART_USR2_DTRF_MASK) +#define UART_USR2_TXFE_MASK (0x4000U) +#define UART_USR2_TXFE_SHIFT (14U) +#define UART_USR2_TXFE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXFE_SHIFT)) & UART_USR2_TXFE_MASK) +#define UART_USR2_ADET_MASK (0x8000U) +#define UART_USR2_ADET_SHIFT (15U) +#define UART_USR2_ADET(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ADET_SHIFT)) & UART_USR2_ADET_MASK) + +/*! @name UESC - UART Escape Character Register */ +#define UART_UESC_ESC_CHAR_MASK (0xFFU) +#define UART_UESC_ESC_CHAR_SHIFT (0U) +#define UART_UESC_ESC_CHAR(x) (((uint32_t)(((uint32_t)(x)) << UART_UESC_ESC_CHAR_SHIFT)) & UART_UESC_ESC_CHAR_MASK) + +/*! @name UTIM - UART Escape Timer Register */ +#define UART_UTIM_TIM_MASK (0xFFFU) +#define UART_UTIM_TIM_SHIFT (0U) +#define UART_UTIM_TIM(x) (((uint32_t)(((uint32_t)(x)) << UART_UTIM_TIM_SHIFT)) & UART_UTIM_TIM_MASK) + +/*! @name UBIR - UART BRM Incremental Register */ +#define UART_UBIR_INC_MASK (0xFFFFU) +#define UART_UBIR_INC_SHIFT (0U) +#define UART_UBIR_INC(x) (((uint32_t)(((uint32_t)(x)) << UART_UBIR_INC_SHIFT)) & UART_UBIR_INC_MASK) + +/*! @name UBMR - UART BRM Modulator Register */ +#define UART_UBMR_MOD_MASK (0xFFFFU) +#define UART_UBMR_MOD_SHIFT (0U) +#define UART_UBMR_MOD(x) (((uint32_t)(((uint32_t)(x)) << UART_UBMR_MOD_SHIFT)) & UART_UBMR_MOD_MASK) + +/*! @name UBRC - UART Baud Rate Count Register */ +#define UART_UBRC_BCNT_MASK (0xFFFFU) +#define UART_UBRC_BCNT_SHIFT (0U) +#define UART_UBRC_BCNT(x) (((uint32_t)(((uint32_t)(x)) << UART_UBRC_BCNT_SHIFT)) & UART_UBRC_BCNT_MASK) + +/*! @name ONEMS - UART One Millisecond Register */ +#define UART_ONEMS_ONEMS_MASK (0xFFFFFFU) +#define UART_ONEMS_ONEMS_SHIFT (0U) +#define UART_ONEMS_ONEMS(x) (((uint32_t)(((uint32_t)(x)) << UART_ONEMS_ONEMS_SHIFT)) & UART_ONEMS_ONEMS_MASK) + +/*! @name UTS - UART Test Register */ +#define UART_UTS_SOFTRST_MASK (0x1U) +#define UART_UTS_SOFTRST_SHIFT (0U) +#define UART_UTS_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_SOFTRST_SHIFT)) & UART_UTS_SOFTRST_MASK) +#define UART_UTS_RXFULL_MASK (0x8U) +#define UART_UTS_RXFULL_SHIFT (3U) +#define UART_UTS_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXFULL_SHIFT)) & UART_UTS_RXFULL_MASK) +#define UART_UTS_TXFULL_MASK (0x10U) +#define UART_UTS_TXFULL_SHIFT (4U) +#define UART_UTS_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXFULL_SHIFT)) & UART_UTS_TXFULL_MASK) +#define UART_UTS_RXEMPTY_MASK (0x20U) +#define UART_UTS_RXEMPTY_SHIFT (5U) +#define UART_UTS_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXEMPTY_SHIFT)) & UART_UTS_RXEMPTY_MASK) +#define UART_UTS_TXEMPTY_MASK (0x40U) +#define UART_UTS_TXEMPTY_SHIFT (6U) +#define UART_UTS_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXEMPTY_SHIFT)) & UART_UTS_TXEMPTY_MASK) +#define UART_UTS_RXDBG_MASK (0x200U) +#define UART_UTS_RXDBG_SHIFT (9U) +#define UART_UTS_RXDBG(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXDBG_SHIFT)) & UART_UTS_RXDBG_MASK) +#define UART_UTS_LOOPIR_MASK (0x400U) +#define UART_UTS_LOOPIR_SHIFT (10U) +#define UART_UTS_LOOPIR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOPIR_SHIFT)) & UART_UTS_LOOPIR_MASK) +#define UART_UTS_DBGEN_MASK (0x800U) +#define UART_UTS_DBGEN_SHIFT (11U) +#define UART_UTS_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_DBGEN_SHIFT)) & UART_UTS_DBGEN_MASK) +#define UART_UTS_LOOP_MASK (0x1000U) +#define UART_UTS_LOOP_SHIFT (12U) +#define UART_UTS_LOOP(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOP_SHIFT)) & UART_UTS_LOOP_MASK) +#define UART_UTS_FRCPERR_MASK (0x2000U) +#define UART_UTS_FRCPERR_SHIFT (13U) +#define UART_UTS_FRCPERR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_FRCPERR_SHIFT)) & UART_UTS_FRCPERR_MASK) + +/*! @name UMCR - UART RS-485 Mode Control Register */ +#define UART_UMCR_MDEN_MASK (0x1U) +#define UART_UMCR_MDEN_SHIFT (0U) +#define UART_UMCR_MDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_MDEN_SHIFT)) & UART_UMCR_MDEN_MASK) +#define UART_UMCR_SLAM_MASK (0x2U) +#define UART_UMCR_SLAM_SHIFT (1U) +#define UART_UMCR_SLAM(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLAM_SHIFT)) & UART_UMCR_SLAM_MASK) +#define UART_UMCR_TXB8_MASK (0x4U) +#define UART_UMCR_TXB8_SHIFT (2U) +#define UART_UMCR_TXB8(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_TXB8_SHIFT)) & UART_UMCR_TXB8_MASK) +#define UART_UMCR_SADEN_MASK (0x8U) +#define UART_UMCR_SADEN_SHIFT (3U) +#define UART_UMCR_SADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SADEN_SHIFT)) & UART_UMCR_SADEN_MASK) +#define UART_UMCR_SLADDR_MASK (0xFF00U) +#define UART_UMCR_SLADDR_SHIFT (8U) +#define UART_UMCR_SLADDR(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLADDR_SHIFT)) & UART_UMCR_SLADDR_MASK) + + +/*! + * @} + */ /* end of group UART_Register_Masks */ + + +/* UART - Peripheral instance base addresses */ +/** Peripheral UART1 base address */ +#define UART1_BASE (0x2020000u) +/** Peripheral UART1 base pointer */ +#define UART1 ((UART_Type *)UART1_BASE) +/** Peripheral UART2 base address */ +#define UART2_BASE (0x21E8000u) +/** Peripheral UART2 base pointer */ +#define UART2 ((UART_Type *)UART2_BASE) +/** Peripheral UART3 base address */ +#define UART3_BASE (0x21EC000u) +/** Peripheral UART3 base pointer */ +#define UART3 ((UART_Type *)UART3_BASE) +/** Peripheral UART4 base address */ +#define UART4_BASE (0x21F0000u) +/** Peripheral UART4 base pointer */ +#define UART4 ((UART_Type *)UART4_BASE) +/** Peripheral UART5 base address */ +#define UART5_BASE (0x21F4000u) +/** Peripheral UART5 base pointer */ +#define UART5 ((UART_Type *)UART5_BASE) +/** Peripheral UART6 base address */ +#define UART6_BASE (0x21FC000u) +/** Peripheral UART6 base pointer */ +#define UART6 ((UART_Type *)UART6_BASE) +/** Peripheral UART7 base address */ +#define UART7_BASE (0x2018000u) +/** Peripheral UART7 base pointer */ +#define UART7 ((UART_Type *)UART7_BASE) +/** Peripheral UART8 base address */ +#define UART8_BASE (0x2288000u) +/** Peripheral UART8 base pointer */ +#define UART8 ((UART_Type *)UART8_BASE) +/** Array initializer of UART peripheral base addresses */ +#define UART_BASE_ADDRS { 0u, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE, UART6_BASE, UART7_BASE, UART8_BASE } +/** Array initializer of UART peripheral base pointers */ +#define UART_BASE_PTRS { (UART_Type *)0u, UART1, UART2, UART3, UART4, UART5, UART6, UART7, UART8 } +/** Interrupt vectors for the UART peripheral type */ +#define UART_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn, UART3_IRQn, UART4_IRQn, UART5_IRQn, UART6_IRQn, UART7_IRQn, UART8_IRQn } + +/*! + * @} + */ /* end of group UART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint32_t ID; /**< Identification register, offset: 0x0 */ + __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ + __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ + __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ + __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ + __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ + uint8_t RESERVED_0[104]; + __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ + __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ + __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ + __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ + __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ + uint8_t RESERVED_1[108]; + __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ + uint8_t RESERVED_2[1]; + __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ + uint8_t RESERVED_3[20]; + __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ + uint8_t RESERVED_4[2]; + __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ + uint8_t RESERVED_5[24]; + __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */ + __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */ + __IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */ + __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ + uint8_t RESERVED_6[4]; + union { /* offset: 0x154 */ + __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ + __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ + }; + union { /* offset: 0x158 */ + __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ + __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ + }; + uint8_t RESERVED_7[4]; + __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ + __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ + uint8_t RESERVED_8[16]; + __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ + __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ + __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */ + __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ + uint8_t RESERVED_9[28]; + __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ + __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ + __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ + __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ + __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ + __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ + __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ + __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ + __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name ID - Identification register */ +#define USB_ID_ID_MASK (0x3FU) +#define USB_ID_ID_SHIFT (0U) +#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) +#define USB_ID_NID_MASK (0x3F00U) +#define USB_ID_NID_SHIFT (8U) +#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK) +#define USB_ID_REVISION_MASK (0xFF0000U) +#define USB_ID_REVISION_SHIFT (16U) +#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) + +/*! @name HWGENERAL - Hardware General */ +#define USB_HWGENERAL_PHYW_MASK (0x30U) +#define USB_HWGENERAL_PHYW_SHIFT (4U) +#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) +#define USB_HWGENERAL_PHYM_MASK (0x1C0U) +#define USB_HWGENERAL_PHYM_SHIFT (6U) +#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) +#define USB_HWGENERAL_SM_MASK (0x600U) +#define USB_HWGENERAL_SM_SHIFT (9U) +#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) + +/*! @name HWHOST - Host Hardware Parameters */ +#define USB_HWHOST_HC_MASK (0x1U) +#define USB_HWHOST_HC_SHIFT (0U) +#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) +#define USB_HWHOST_NPORT_MASK (0xEU) +#define USB_HWHOST_NPORT_SHIFT (1U) +#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) + +/*! @name HWDEVICE - Device Hardware Parameters */ +#define USB_HWDEVICE_DC_MASK (0x1U) +#define USB_HWDEVICE_DC_SHIFT (0U) +#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) +#define USB_HWDEVICE_DEVEP_MASK (0x3EU) +#define USB_HWDEVICE_DEVEP_SHIFT (1U) +#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) + +/*! @name HWTXBUF - TX Buffer Hardware Parameters */ +#define USB_HWTXBUF_TXBURST_MASK (0xFFU) +#define USB_HWTXBUF_TXBURST_SHIFT (0U) +#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) +#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) +#define USB_HWTXBUF_TXCHANADD_SHIFT (16U) +#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) + +/*! @name HWRXBUF - RX Buffer Hardware Parameters */ +#define USB_HWRXBUF_RXBURST_MASK (0xFFU) +#define USB_HWRXBUF_RXBURST_SHIFT (0U) +#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) +#define USB_HWRXBUF_RXADD_MASK (0xFF00U) +#define USB_HWRXBUF_RXADD_SHIFT (8U) +#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) + +/*! @name GPTIMER0LD - General Purpose Timer #0 Load */ +#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) + +/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ +#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) +#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +#define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) +#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) +#define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) +#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +#define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) + +/*! @name GPTIMER1LD - General Purpose Timer #1 Load */ +#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) + +/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ +#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) +#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +#define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) +#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) +#define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) +#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +#define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) + +/*! @name SBUSCFG - System Bus Config */ +#define USB_SBUSCFG_AHBBRST_MASK (0x7U) +#define USB_SBUSCFG_AHBBRST_SHIFT (0U) +#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) + +/*! @name CAPLENGTH - Capability Registers Length */ +#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) +#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) +#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) + +/*! @name HCIVERSION - Host Controller Interface Version */ +#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) +#define USB_HCIVERSION_HCIVERSION_SHIFT (0U) +#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +#define USB_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USB_HCSPARAMS_N_PORTS_SHIFT (0U) +#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) +#define USB_HCSPARAMS_PPC_MASK (0x10U) +#define USB_HCSPARAMS_PPC_SHIFT (4U) +#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK) +#define USB_HCSPARAMS_N_PCC_MASK (0xF00U) +#define USB_HCSPARAMS_N_PCC_SHIFT (8U) +#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) +#define USB_HCSPARAMS_N_CC_MASK (0xF000U) +#define USB_HCSPARAMS_N_CC_SHIFT (12U) +#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) +#define USB_HCSPARAMS_PI_MASK (0x10000U) +#define USB_HCSPARAMS_PI_SHIFT (16U) +#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK) +#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U) +#define USB_HCSPARAMS_N_PTT_SHIFT (20U) +#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK) +#define USB_HCSPARAMS_N_TT_MASK (0xF000000U) +#define USB_HCSPARAMS_N_TT_SHIFT (24U) +#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) + +/*! @name HCCPARAMS - Host Controller Capability Parameters */ +#define USB_HCCPARAMS_ADC_MASK (0x1U) +#define USB_HCCPARAMS_ADC_SHIFT (0U) +#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) +#define USB_HCCPARAMS_PFL_MASK (0x2U) +#define USB_HCCPARAMS_PFL_SHIFT (1U) +#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK) +#define USB_HCCPARAMS_ASP_MASK (0x4U) +#define USB_HCCPARAMS_ASP_SHIFT (2U) +#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK) +#define USB_HCCPARAMS_IST_MASK (0xF0U) +#define USB_HCCPARAMS_IST_SHIFT (4U) +#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK) +#define USB_HCCPARAMS_EECP_MASK (0xFF00U) +#define USB_HCCPARAMS_EECP_SHIFT (8U) +#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) + +/*! @name DCIVERSION - Device Controller Interface Version */ +#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) +#define USB_DCIVERSION_DCIVERSION_SHIFT (0U) +#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) + +/*! @name DCCPARAMS - Device Controller Capability Parameters */ +#define USB_DCCPARAMS_DEN_MASK (0x1FU) +#define USB_DCCPARAMS_DEN_SHIFT (0U) +#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) +#define USB_DCCPARAMS_DC_MASK (0x80U) +#define USB_DCCPARAMS_DC_SHIFT (7U) +#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK) +#define USB_DCCPARAMS_HC_MASK (0x100U) +#define USB_DCCPARAMS_HC_SHIFT (8U) +#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) + +/*! @name USBCMD - USB Command Register */ +#define USB_USBCMD_RS_MASK (0x1U) +#define USB_USBCMD_RS_SHIFT (0U) +#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) +#define USB_USBCMD_RST_MASK (0x2U) +#define USB_USBCMD_RST_SHIFT (1U) +#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK) +#define USB_USBCMD_FS_1_MASK (0xCU) +#define USB_USBCMD_FS_1_SHIFT (2U) +#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) +#define USB_USBCMD_PSE_MASK (0x10U) +#define USB_USBCMD_PSE_SHIFT (4U) +#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) +#define USB_USBCMD_ASE_MASK (0x20U) +#define USB_USBCMD_ASE_SHIFT (5U) +#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) +#define USB_USBCMD_IAA_MASK (0x40U) +#define USB_USBCMD_IAA_SHIFT (6U) +#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK) +#define USB_USBCMD_ASP_MASK (0x300U) +#define USB_USBCMD_ASP_SHIFT (8U) +#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK) +#define USB_USBCMD_ASPE_MASK (0x800U) +#define USB_USBCMD_ASPE_SHIFT (11U) +#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK) +#define USB_USBCMD_ATDTW_MASK (0x1000U) +#define USB_USBCMD_ATDTW_SHIFT (12U) +#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK) +#define USB_USBCMD_SUTW_MASK (0x2000U) +#define USB_USBCMD_SUTW_SHIFT (13U) +#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) +#define USB_USBCMD_FS_2_MASK (0x8000U) +#define USB_USBCMD_FS_2_SHIFT (15U) +#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) +#define USB_USBCMD_ITC_MASK (0xFF0000U) +#define USB_USBCMD_ITC_SHIFT (16U) +#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) + +/*! @name USBSTS - USB Status Register */ +#define USB_USBSTS_UI_MASK (0x1U) +#define USB_USBSTS_UI_SHIFT (0U) +#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) +#define USB_USBSTS_UEI_MASK (0x2U) +#define USB_USBSTS_UEI_SHIFT (1U) +#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) +#define USB_USBSTS_PCI_MASK (0x4U) +#define USB_USBSTS_PCI_SHIFT (2U) +#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) +#define USB_USBSTS_FRI_MASK (0x8U) +#define USB_USBSTS_FRI_SHIFT (3U) +#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) +#define USB_USBSTS_SEI_MASK (0x10U) +#define USB_USBSTS_SEI_SHIFT (4U) +#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) +#define USB_USBSTS_AAI_MASK (0x20U) +#define USB_USBSTS_AAI_SHIFT (5U) +#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) +#define USB_USBSTS_URI_MASK (0x40U) +#define USB_USBSTS_URI_SHIFT (6U) +#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) +#define USB_USBSTS_SRI_MASK (0x80U) +#define USB_USBSTS_SRI_SHIFT (7U) +#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) +#define USB_USBSTS_SLI_MASK (0x100U) +#define USB_USBSTS_SLI_SHIFT (8U) +#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) +#define USB_USBSTS_ULPII_MASK (0x400U) +#define USB_USBSTS_ULPII_SHIFT (10U) +#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) +#define USB_USBSTS_HCH_MASK (0x1000U) +#define USB_USBSTS_HCH_SHIFT (12U) +#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK) +#define USB_USBSTS_RCL_MASK (0x2000U) +#define USB_USBSTS_RCL_SHIFT (13U) +#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK) +#define USB_USBSTS_PS_MASK (0x4000U) +#define USB_USBSTS_PS_SHIFT (14U) +#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK) +#define USB_USBSTS_AS_MASK (0x8000U) +#define USB_USBSTS_AS_SHIFT (15U) +#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK) +#define USB_USBSTS_NAKI_MASK (0x10000U) +#define USB_USBSTS_NAKI_SHIFT (16U) +#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK) +#define USB_USBSTS_TI0_MASK (0x1000000U) +#define USB_USBSTS_TI0_SHIFT (24U) +#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) +#define USB_USBSTS_TI1_MASK (0x2000000U) +#define USB_USBSTS_TI1_SHIFT (25U) +#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) + +/*! @name USBINTR - Interrupt Enable Register */ +#define USB_USBINTR_UE_MASK (0x1U) +#define USB_USBINTR_UE_SHIFT (0U) +#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) +#define USB_USBINTR_UEE_MASK (0x2U) +#define USB_USBINTR_UEE_SHIFT (1U) +#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK) +#define USB_USBINTR_PCE_MASK (0x4U) +#define USB_USBINTR_PCE_SHIFT (2U) +#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK) +#define USB_USBINTR_FRE_MASK (0x8U) +#define USB_USBINTR_FRE_SHIFT (3U) +#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK) +#define USB_USBINTR_SEE_MASK (0x10U) +#define USB_USBINTR_SEE_SHIFT (4U) +#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK) +#define USB_USBINTR_AAE_MASK (0x20U) +#define USB_USBINTR_AAE_SHIFT (5U) +#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK) +#define USB_USBINTR_URE_MASK (0x40U) +#define USB_USBINTR_URE_SHIFT (6U) +#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK) +#define USB_USBINTR_SRE_MASK (0x80U) +#define USB_USBINTR_SRE_SHIFT (7U) +#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK) +#define USB_USBINTR_SLE_MASK (0x100U) +#define USB_USBINTR_SLE_SHIFT (8U) +#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK) +#define USB_USBINTR_ULPIE_MASK (0x400U) +#define USB_USBINTR_ULPIE_SHIFT (10U) +#define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK) +#define USB_USBINTR_NAKE_MASK (0x10000U) +#define USB_USBINTR_NAKE_SHIFT (16U) +#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK) +#define USB_USBINTR_UAIE_MASK (0x40000U) +#define USB_USBINTR_UAIE_SHIFT (18U) +#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK) +#define USB_USBINTR_UPIE_MASK (0x80000U) +#define USB_USBINTR_UPIE_SHIFT (19U) +#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK) +#define USB_USBINTR_TIE0_MASK (0x1000000U) +#define USB_USBINTR_TIE0_SHIFT (24U) +#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK) +#define USB_USBINTR_TIE1_MASK (0x2000000U) +#define USB_USBINTR_TIE1_SHIFT (25U) +#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) + +/*! @name FRINDEX - USB Frame Index */ +#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) +#define USB_FRINDEX_FRINDEX_SHIFT (0U) +#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) + +/*! @name DEVICEADDR - Device Address */ +#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) +#define USB_DEVICEADDR_USBADRA_SHIFT (24U) +#define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) +#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) +#define USB_DEVICEADDR_USBADR_SHIFT (25U) +#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) + +/*! @name PERIODICLISTBASE - Frame List Base Address */ +#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) +#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) +#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) + +/*! @name ASYNCLISTADDR - Next Asynch. Address */ +#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) +#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) +#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) + +/*! @name ENDPTLISTADDR - Endpoint List Address */ +#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) +#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) +#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) + +/*! @name BURSTSIZE - Programmable Burst Size */ +#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) +#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) +#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) +#define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U) +#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) +#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) + +/*! @name TXFILLTUNING - TX FIFO Fill Tuning */ +#define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU) +#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) +#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) +#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) +#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) +#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) +#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) +#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) +#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) + +/*! @name ENDPTNAK - Endpoint NAK */ +#define USB_ENDPTNAK_EPRN_MASK (0xFFU) +#define USB_ENDPTNAK_EPRN_SHIFT (0U) +#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) +#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) +#define USB_ENDPTNAK_EPTN_SHIFT (16U) +#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) + +/*! @name ENDPTNAKEN - Endpoint NAK Enable */ +#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) +#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) +#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) +#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) +#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) +#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) + +/*! @name CONFIGFLAG - Configure Flag Register */ +#define USB_CONFIGFLAG_CF_MASK (0x1U) +#define USB_CONFIGFLAG_CF_SHIFT (0U) +#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) + +/*! @name PORTSC1 - Port Status & Control */ +#define USB_PORTSC1_CCS_MASK (0x1U) +#define USB_PORTSC1_CCS_SHIFT (0U) +#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) +#define USB_PORTSC1_CSC_MASK (0x2U) +#define USB_PORTSC1_CSC_SHIFT (1U) +#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK) +#define USB_PORTSC1_PE_MASK (0x4U) +#define USB_PORTSC1_PE_SHIFT (2U) +#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK) +#define USB_PORTSC1_PEC_MASK (0x8U) +#define USB_PORTSC1_PEC_SHIFT (3U) +#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) +#define USB_PORTSC1_OCA_MASK (0x10U) +#define USB_PORTSC1_OCA_SHIFT (4U) +#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) +#define USB_PORTSC1_OCC_MASK (0x20U) +#define USB_PORTSC1_OCC_SHIFT (5U) +#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK) +#define USB_PORTSC1_FPR_MASK (0x40U) +#define USB_PORTSC1_FPR_SHIFT (6U) +#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK) +#define USB_PORTSC1_SUSP_MASK (0x80U) +#define USB_PORTSC1_SUSP_SHIFT (7U) +#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK) +#define USB_PORTSC1_PR_MASK (0x100U) +#define USB_PORTSC1_PR_SHIFT (8U) +#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK) +#define USB_PORTSC1_HSP_MASK (0x200U) +#define USB_PORTSC1_HSP_SHIFT (9U) +#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) +#define USB_PORTSC1_LS_MASK (0xC00U) +#define USB_PORTSC1_LS_SHIFT (10U) +#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) +#define USB_PORTSC1_PP_MASK (0x1000U) +#define USB_PORTSC1_PP_SHIFT (12U) +#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK) +#define USB_PORTSC1_PO_MASK (0x2000U) +#define USB_PORTSC1_PO_SHIFT (13U) +#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) +#define USB_PORTSC1_PIC_MASK (0xC000U) +#define USB_PORTSC1_PIC_SHIFT (14U) +#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) +#define USB_PORTSC1_PTC_MASK (0xF0000U) +#define USB_PORTSC1_PTC_SHIFT (16U) +#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) +#define USB_PORTSC1_WKCN_MASK (0x100000U) +#define USB_PORTSC1_WKCN_SHIFT (20U) +#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK) +#define USB_PORTSC1_WKDC_MASK (0x200000U) +#define USB_PORTSC1_WKDC_SHIFT (21U) +#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK) +#define USB_PORTSC1_WKOC_MASK (0x400000U) +#define USB_PORTSC1_WKOC_SHIFT (22U) +#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) +#define USB_PORTSC1_PHCD_MASK (0x800000U) +#define USB_PORTSC1_PHCD_SHIFT (23U) +#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) +#define USB_PORTSC1_PFSC_MASK (0x1000000U) +#define USB_PORTSC1_PFSC_SHIFT (24U) +#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) +#define USB_PORTSC1_PTS_2_MASK (0x2000000U) +#define USB_PORTSC1_PTS_2_SHIFT (25U) +#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) +#define USB_PORTSC1_PSPD_MASK (0xC000000U) +#define USB_PORTSC1_PSPD_SHIFT (26U) +#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) +#define USB_PORTSC1_PTW_MASK (0x10000000U) +#define USB_PORTSC1_PTW_SHIFT (28U) +#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) +#define USB_PORTSC1_STS_MASK (0x20000000U) +#define USB_PORTSC1_STS_SHIFT (29U) +#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK) +#define USB_PORTSC1_PTS_1_MASK (0xC0000000U) +#define USB_PORTSC1_PTS_1_SHIFT (30U) +#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) + +/*! @name OTGSC - On-The-Go Status & control */ +#define USB_OTGSC_VD_MASK (0x1U) +#define USB_OTGSC_VD_SHIFT (0U) +#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) +#define USB_OTGSC_VC_MASK (0x2U) +#define USB_OTGSC_VC_SHIFT (1U) +#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK) +#define USB_OTGSC_OT_MASK (0x8U) +#define USB_OTGSC_OT_SHIFT (3U) +#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK) +#define USB_OTGSC_DP_MASK (0x10U) +#define USB_OTGSC_DP_SHIFT (4U) +#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK) +#define USB_OTGSC_IDPU_MASK (0x20U) +#define USB_OTGSC_IDPU_SHIFT (5U) +#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK) +#define USB_OTGSC_ID_MASK (0x100U) +#define USB_OTGSC_ID_SHIFT (8U) +#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK) +#define USB_OTGSC_AVV_MASK (0x200U) +#define USB_OTGSC_AVV_SHIFT (9U) +#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK) +#define USB_OTGSC_ASV_MASK (0x400U) +#define USB_OTGSC_ASV_SHIFT (10U) +#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK) +#define USB_OTGSC_BSV_MASK (0x800U) +#define USB_OTGSC_BSV_SHIFT (11U) +#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK) +#define USB_OTGSC_BSE_MASK (0x1000U) +#define USB_OTGSC_BSE_SHIFT (12U) +#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK) +#define USB_OTGSC_TOG_1MS_MASK (0x2000U) +#define USB_OTGSC_TOG_1MS_SHIFT (13U) +#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK) +#define USB_OTGSC_DPS_MASK (0x4000U) +#define USB_OTGSC_DPS_SHIFT (14U) +#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK) +#define USB_OTGSC_IDIS_MASK (0x10000U) +#define USB_OTGSC_IDIS_SHIFT (16U) +#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK) +#define USB_OTGSC_AVVIS_MASK (0x20000U) +#define USB_OTGSC_AVVIS_SHIFT (17U) +#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) +#define USB_OTGSC_ASVIS_MASK (0x40000U) +#define USB_OTGSC_ASVIS_SHIFT (18U) +#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) +#define USB_OTGSC_BSVIS_MASK (0x80000U) +#define USB_OTGSC_BSVIS_SHIFT (19U) +#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) +#define USB_OTGSC_BSEIS_MASK (0x100000U) +#define USB_OTGSC_BSEIS_SHIFT (20U) +#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) +#define USB_OTGSC_STATUS_1MS_MASK (0x200000U) +#define USB_OTGSC_STATUS_1MS_SHIFT (21U) +#define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK) +#define USB_OTGSC_DPIS_MASK (0x400000U) +#define USB_OTGSC_DPIS_SHIFT (22U) +#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) +#define USB_OTGSC_IDIE_MASK (0x1000000U) +#define USB_OTGSC_IDIE_SHIFT (24U) +#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK) +#define USB_OTGSC_AVVIE_MASK (0x2000000U) +#define USB_OTGSC_AVVIE_SHIFT (25U) +#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK) +#define USB_OTGSC_ASVIE_MASK (0x4000000U) +#define USB_OTGSC_ASVIE_SHIFT (26U) +#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK) +#define USB_OTGSC_BSVIE_MASK (0x8000000U) +#define USB_OTGSC_BSVIE_SHIFT (27U) +#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK) +#define USB_OTGSC_BSEIE_MASK (0x10000000U) +#define USB_OTGSC_BSEIE_SHIFT (28U) +#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK) +#define USB_OTGSC_EN_1MS_MASK (0x20000000U) +#define USB_OTGSC_EN_1MS_SHIFT (29U) +#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK) +#define USB_OTGSC_DPIE_MASK (0x40000000U) +#define USB_OTGSC_DPIE_SHIFT (30U) +#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) + +/*! @name USBMODE - USB Device Mode */ +#define USB_USBMODE_CM_MASK (0x3U) +#define USB_USBMODE_CM_SHIFT (0U) +#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) +#define USB_USBMODE_ES_MASK (0x4U) +#define USB_USBMODE_ES_SHIFT (2U) +#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) +#define USB_USBMODE_SLOM_MASK (0x8U) +#define USB_USBMODE_SLOM_SHIFT (3U) +#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) +#define USB_USBMODE_SDIS_MASK (0x10U) +#define USB_USBMODE_SDIS_SHIFT (4U) +#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) + +/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) + +/*! @name ENDPTPRIME - Endpoint Prime */ +#define USB_ENDPTPRIME_PERB_MASK (0xFFU) +#define USB_ENDPTPRIME_PERB_SHIFT (0U) +#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) +#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) +#define USB_ENDPTPRIME_PETB_SHIFT (16U) +#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) + +/*! @name ENDPTFLUSH - Endpoint Flush */ +#define USB_ENDPTFLUSH_FERB_MASK (0xFFU) +#define USB_ENDPTFLUSH_FERB_SHIFT (0U) +#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) +#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) +#define USB_ENDPTFLUSH_FETB_SHIFT (16U) +#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) + +/*! @name ENDPTSTAT - Endpoint Status */ +#define USB_ENDPTSTAT_ERBR_MASK (0xFFU) +#define USB_ENDPTSTAT_ERBR_SHIFT (0U) +#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) +#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) +#define USB_ENDPTSTAT_ETBR_SHIFT (16U) +#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) + +/*! @name ENDPTCOMPLETE - Endpoint Complete */ +#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) +#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) +#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) +#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) +#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) +#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) + +/*! @name ENDPTCTRL0 - Endpoint Control0 */ +#define USB_ENDPTCTRL0_RXS_MASK (0x1U) +#define USB_ENDPTCTRL0_RXS_SHIFT (0U) +#define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) +#define USB_ENDPTCTRL0_RXT_MASK (0xCU) +#define USB_ENDPTCTRL0_RXT_SHIFT (2U) +#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK) +#define USB_ENDPTCTRL0_RXE_MASK (0x80U) +#define USB_ENDPTCTRL0_RXE_SHIFT (7U) +#define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK) +#define USB_ENDPTCTRL0_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL0_TXS_SHIFT (16U) +#define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK) +#define USB_ENDPTCTRL0_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL0_TXT_SHIFT (18U) +#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK) +#define USB_ENDPTCTRL0_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL0_TXE_SHIFT (23U) +#define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) + +/*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ +#define USB_ENDPTCTRL_RXS_MASK (0x1U) +#define USB_ENDPTCTRL_RXS_SHIFT (0U) +#define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) +#define USB_ENDPTCTRL_RXD_MASK (0x2U) +#define USB_ENDPTCTRL_RXD_SHIFT (1U) +#define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK) +#define USB_ENDPTCTRL_RXT_MASK (0xCU) +#define USB_ENDPTCTRL_RXT_SHIFT (2U) +#define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK) +#define USB_ENDPTCTRL_RXI_MASK (0x20U) +#define USB_ENDPTCTRL_RXI_SHIFT (5U) +#define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK) +#define USB_ENDPTCTRL_RXR_MASK (0x40U) +#define USB_ENDPTCTRL_RXR_SHIFT (6U) +#define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK) +#define USB_ENDPTCTRL_RXE_MASK (0x80U) +#define USB_ENDPTCTRL_RXE_SHIFT (7U) +#define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK) +#define USB_ENDPTCTRL_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL_TXS_SHIFT (16U) +#define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK) +#define USB_ENDPTCTRL_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL_TXD_SHIFT (17U) +#define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK) +#define USB_ENDPTCTRL_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL_TXT_SHIFT (18U) +#define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK) +#define USB_ENDPTCTRL_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL_TXI_SHIFT (21U) +#define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK) +#define USB_ENDPTCTRL_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL_TXR_SHIFT (22U) +#define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK) +#define USB_ENDPTCTRL_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL_TXE_SHIFT (23U) +#define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) + +/* The count of USB_ENDPTCTRL */ +#define USB_ENDPTCTRL_COUNT (7U) + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB1 base address */ +#define USB1_BASE (0x2184000u) +/** Peripheral USB1 base pointer */ +#define USB1 ((USB_Type *)USB1_BASE) +/** Peripheral USB2 base address */ +#define USB2_BASE (0x2184200u) +/** Peripheral USB2 base pointer */ +#define USB2 ((USB_Type *)USB2_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn } +/* Backward compatibility */ +#define GPTIMER0CTL GPTIMER0CTRL +#define GPTIMER1CTL GPTIMER1CTRL +#define USB_SBUSCFG SBUSCFG +#define EPLISTADDR ENDPTLISTADDR +#define EPSETUPSR ENDPTSETUPSTAT +#define EPPRIME ENDPTPRIME +#define EPFLUSH ENDPTFLUSH +#define EPSR ENDPTSTAT +#define EPCOMPLETE ENDPTCOMPLETE +#define EPCR ENDPTCTRL +#define EPCR0 ENDPTCTRL0 +#define USBHS_ID_ID_MASK USB_ID_ID_MASK +#define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT +#define USBHS_ID_ID(x) USB_ID_ID(x) +#define USBHS_ID_NID_MASK USB_ID_NID_MASK +#define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT +#define USBHS_ID_NID(x) USB_ID_NID(x) +#define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK +#define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT +#define USBHS_ID_REVISION(x) USB_ID_REVISION(x) +#define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK +#define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT +#define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x) +#define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK +#define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT +#define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x) +#define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK +#define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT +#define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x) +#define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK +#define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT +#define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x) +#define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK +#define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT +#define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x) +#define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK +#define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT +#define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x) +#define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK +#define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT +#define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x) +#define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK +#define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT +#define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x) +#define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK +#define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT +#define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x) +#define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK +#define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT +#define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x) +#define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK +#define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT +#define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x) +#define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK +#define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT +#define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x) +#define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK +#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x) +#define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK +#define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x) +#define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK +#define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x) +#define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK +#define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x) +#define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK +#define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT +#define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x) +#define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK +#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x) +#define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK +#define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x) +#define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK +#define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x) +#define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK +#define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x) +#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK +#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT +#define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x) +#define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x) +#define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK +#define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT +#define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x) +#define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK +#define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT +#define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x) +#define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK +#define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT +#define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x) +#define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK +#define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT +#define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x) +#define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK +#define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT +#define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x) +#define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK +#define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT +#define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x) +#define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK +#define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT +#define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x) +#define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK +#define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT +#define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x) +#define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK +#define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT +#define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x) +#define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK +#define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT +#define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x) +#define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK +#define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT +#define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x) +#define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK +#define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT +#define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x) +#define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK +#define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT +#define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x) +#define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK +#define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT +#define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x) +#define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK +#define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT +#define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x) +#define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK +#define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT +#define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x) +#define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK +#define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT +#define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x) +#define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK +#define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT +#define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x) +#define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK +#define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT +#define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x) +#define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK +#define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT +#define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x) +#define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK +#define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT +#define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x) +#define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK +#define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT +#define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x) +#define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK +#define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT +#define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x) +#define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK +#define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT +#define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x) +#define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK +#define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT +#define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x) +#define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK +#define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT +#define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x) +#define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK +#define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT +#define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x) +#define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK +#define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT +#define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x) +#define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK +#define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT +#define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x) +#define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK +#define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT +#define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x) +#define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK +#define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT +#define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x) +#define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK +#define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT +#define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x) +#define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK +#define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT +#define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x) +#define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK +#define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT +#define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x) +#define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK +#define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT +#define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x) +#define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK +#define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT +#define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x) +#define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK +#define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT +#define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x) +#define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK +#define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT +#define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x) +#define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK +#define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT +#define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x) +#define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK +#define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT +#define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x) +#define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK +#define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT +#define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x) +#define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK +#define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT +#define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x) +#define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK +#define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT +#define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x) +#define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK +#define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT +#define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x) +#define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK +#define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT +#define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x) +#define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK +#define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT +#define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x) +#define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK +#define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT +#define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x) +#define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK +#define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT +#define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x) +#define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK +#define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT +#define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x) +#define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK +#define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT +#define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x) +#define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK +#define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT +#define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x) +#define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK +#define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT +#define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x) +#define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK +#define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT +#define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x) +#define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK +#define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT +#define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x) +#define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK +#define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT +#define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x) +#define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK +#define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT +#define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x) +#define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK +#define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT +#define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x) +#define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK +#define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT +#define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x) +#define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK +#define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT +#define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x) +#define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK +#define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT +#define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x) +#define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK +#define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT +#define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x) +#define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK +#define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT +#define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x) +#define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK +#define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT +#define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x) +#define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK +#define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT +#define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x) +#define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK +#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT +#define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x) +#define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK +#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT +#define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x) +#define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK +#define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT +#define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x) +#define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK +#define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT +#define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x) +#define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK +#define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT +#define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x) +#define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK +#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT +#define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x) +#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK +#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT +#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x) +#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK +#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT +#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x) +#define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK +#define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT +#define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x) +#define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK +#define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT +#define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x) +#define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK +#define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT +#define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x) +#define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK +#define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT +#define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x) +#define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK +#define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT +#define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x) +#define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK +#define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT +#define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x) +#define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK +#define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT +#define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x) +#define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK +#define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT +#define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x) +#define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK +#define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT +#define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x) +#define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK +#define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT +#define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x) +#define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK +#define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT +#define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x) +#define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK +#define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT +#define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x) +#define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK +#define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT +#define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x) +#define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK +#define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT +#define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x) +#define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK +#define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT +#define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x) +#define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK +#define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT +#define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x) +#define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK +#define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT +#define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x) +#define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK +#define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT +#define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x) +#define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK +#define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT +#define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x) +#define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK +#define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT +#define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x) +#define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK +#define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT +#define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x) +#define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK +#define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT +#define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x) +#define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK +#define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT +#define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x) +#define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK +#define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT +#define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x) +#define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK +#define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT +#define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x) +#define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK +#define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT +#define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x) +#define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK +#define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT +#define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x) +#define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK +#define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT +#define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x) +#define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK +#define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT +#define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x) +#define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK +#define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT +#define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x) +#define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK +#define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT +#define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x) +#define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK +#define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT +#define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x) +#define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK +#define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT +#define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x) +#define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK +#define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT +#define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x) +#define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK +#define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT +#define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x) +#define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK +#define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT +#define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x) +#define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK +#define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT +#define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x) +#define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK +#define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT +#define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x) +#define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK +#define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT +#define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x) +#define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK +#define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT +#define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x) +#define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK +#define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT +#define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x) +#define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK +#define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT +#define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x) +#define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK +#define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT +#define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x) +#define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK +#define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT +#define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x) +#define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK +#define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT +#define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x) +#define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK +#define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT +#define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x) +#define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK +#define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT +#define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x) +#define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK +#define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT +#define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x) +#define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK +#define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT +#define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x) +#define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK +#define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT +#define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x) +#define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK +#define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT +#define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x) +#define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK +#define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT +#define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x) +#define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK +#define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT +#define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x) +#define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK +#define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT +#define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x) +#define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK +#define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT +#define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x) +#define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK +#define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT +#define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x) +#define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK +#define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT +#define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x) +#define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK +#define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT +#define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x) +#define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK +#define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT +#define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x) +#define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK +#define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT +#define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x) +#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK +#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT +#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) +#define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK +#define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT +#define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x) +#define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK +#define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT +#define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x) +#define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK +#define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT +#define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x) +#define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK +#define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT +#define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x) +#define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK +#define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT +#define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x) +#define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK +#define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT +#define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x) +#define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK +#define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT +#define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x) +#define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK +#define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT +#define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x) +#define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK +#define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT +#define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x) +#define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK +#define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT +#define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x) +#define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK +#define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT +#define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x) +#define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK +#define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT +#define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x) +#define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK +#define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT +#define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x) +#define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK +#define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT +#define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x) +#define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK +#define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT +#define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x) +#define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK +#define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT +#define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x) +#define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK +#define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT +#define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x) +#define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK +#define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT +#define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x) +#define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK +#define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT +#define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x) +#define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK +#define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT +#define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x) +#define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK +#define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT +#define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x) +#define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK +#define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT +#define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x) +#define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK +#define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT +#define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x) +#define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK +#define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT +#define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x) +#define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK +#define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT +#define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x) +#define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK +#define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT +#define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x) +#define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT +#define USBHS_Type USB_Type +#define USBHS_BASE_ADDRS { USB1_BASE, USB2_BASE } +#define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn } + + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBNC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer + * @{ + */ + +/** USBNC - Register Layout Typedef */ +typedef struct { + __IO uint32_t USB_OTGn_CTRL; /**< USB OTGn Control Register, offset: 0x0 */ + uint8_t RESERVED_0[20]; + __IO uint32_t USB_OTGn_PHY_CTRL_0; /**< OTGn UTMI PHY Control 0 Register, offset: 0x18 */ +} USBNC_Type; + +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/*! @name USB_OTGn_CTRL - USB OTGn Control Register */ +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK) +#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U) +#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U) +#define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK) +#define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U) +#define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U) +#define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U) +#define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U) +#define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK) + +/*! @name USB_OTGn_PHY_CTRL_0 - OTGn UTMI PHY Control 0 Register */ +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U) +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U) +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK) + + +/*! + * @} + */ /* end of group USBNC_Register_Masks */ + + +/* USBNC - Peripheral instance base addresses */ +/** Peripheral USBNC1 base address */ +#define USBNC1_BASE (0x2184800u) +/** Peripheral USBNC1 base pointer */ +#define USBNC1 ((USBNC_Type *)USBNC1_BASE) +/** Peripheral USBNC2 base address */ +#define USBNC2_BASE (0x2184804u) +/** Peripheral USBNC2 base pointer */ +#define USBNC2 ((USBNC_Type *)USBNC2_BASE) +/** Array initializer of USBNC peripheral base addresses */ +#define USBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE } +/** Array initializer of USBNC peripheral base pointers */ +#define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 } + +/*! + * @} + */ /* end of group USBNC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ + __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ + __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ + __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ + __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ + __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ + __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */ + __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */ + __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */ + __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */ + __I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */ + uint8_t RESERVED_1[12]; + __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ + __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ + __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ + __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ + __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - USB PHY Power-Down Register */ +#define USBPHY_PWD_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_RSVD0_SHIFT (0U) +#define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK) +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) +#define USBPHY_PWD_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_RSVD1_SHIFT (13U) +#define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK) +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +#define USBPHY_PWD_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_RSVD2_SHIFT (21U) +#define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK) + +/*! @name PWD_SET - USB PHY Power-Down Register */ +#define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_SET_RSVD0_SHIFT (0U) +#define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK) +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) +#define USBPHY_PWD_SET_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_SET_RSVD1_SHIFT (13U) +#define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK) +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +#define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_SET_RSVD2_SHIFT (21U) +#define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK) + +/*! @name PWD_CLR - USB PHY Power-Down Register */ +#define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_CLR_RSVD0_SHIFT (0U) +#define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK) +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) +#define USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_CLR_RSVD1_SHIFT (13U) +#define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK) +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +#define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_CLR_RSVD2_SHIFT (21U) +#define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK) + +/*! @name PWD_TOG - USB PHY Power-Down Register */ +#define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_TOG_RSVD0_SHIFT (0U) +#define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK) +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) +#define USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_TOG_RSVD1_SHIFT (13U) +#define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK) +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +#define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_TOG_RSVD2_SHIFT (21U) +#define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK) + +/*! @name TX - USB PHY Transmitter Control Register */ +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) +#define USBPHY_TX_RSVD0_MASK (0xF0U) +#define USBPHY_TX_RSVD0_SHIFT (4U) +#define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK) +#define USBPHY_TX_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK) +#define USBPHY_TX_RSVD1_MASK (0xF000U) +#define USBPHY_TX_RSVD1_SHIFT (12U) +#define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK) +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) +#define USBPHY_TX_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_RSVD2_SHIFT (20U) +#define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_RSVD5_SHIFT (29U) +#define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK) + +/*! @name TX_SET - USB PHY Transmitter Control Register */ +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) +#define USBPHY_TX_SET_RSVD0_MASK (0xF0U) +#define USBPHY_TX_SET_RSVD0_SHIFT (4U) +#define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK) +#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK) +#define USBPHY_TX_SET_RSVD1_MASK (0xF000U) +#define USBPHY_TX_SET_RSVD1_SHIFT (12U) +#define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK) +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) +#define USBPHY_TX_SET_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_SET_RSVD2_SHIFT (20U) +#define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_SET_RSVD5_SHIFT (29U) +#define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK) + +/*! @name TX_CLR - USB PHY Transmitter Control Register */ +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) +#define USBPHY_TX_CLR_RSVD0_MASK (0xF0U) +#define USBPHY_TX_CLR_RSVD0_SHIFT (4U) +#define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK) +#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK) +#define USBPHY_TX_CLR_RSVD1_MASK (0xF000U) +#define USBPHY_TX_CLR_RSVD1_SHIFT (12U) +#define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK) +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) +#define USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_CLR_RSVD2_SHIFT (20U) +#define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_CLR_RSVD5_SHIFT (29U) +#define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK) + +/*! @name TX_TOG - USB PHY Transmitter Control Register */ +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) +#define USBPHY_TX_TOG_RSVD0_MASK (0xF0U) +#define USBPHY_TX_TOG_RSVD0_SHIFT (4U) +#define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK) +#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK) +#define USBPHY_TX_TOG_RSVD1_MASK (0xF000U) +#define USBPHY_TX_TOG_RSVD1_SHIFT (12U) +#define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK) +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) +#define USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_TOG_RSVD2_SHIFT (20U) +#define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_TOG_RSVD5_SHIFT (29U) +#define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK) + +/*! @name RX - USB PHY Receiver Control Register */ +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) +#define USBPHY_RX_RSVD0_MASK (0x8U) +#define USBPHY_RX_RSVD0_SHIFT (3U) +#define USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK) +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) +#define USBPHY_RX_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_RSVD1_SHIFT (7U) +#define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK) +#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) +#define USBPHY_RX_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_RSVD2_SHIFT (23U) +#define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK) + +/*! @name RX_SET - USB PHY Receiver Control Register */ +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) +#define USBPHY_RX_SET_RSVD0_MASK (0x8U) +#define USBPHY_RX_SET_RSVD0_SHIFT (3U) +#define USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK) +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) +#define USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_SET_RSVD1_SHIFT (7U) +#define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK) +#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) +#define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_SET_RSVD2_SHIFT (23U) +#define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK) + +/*! @name RX_CLR - USB PHY Receiver Control Register */ +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) +#define USBPHY_RX_CLR_RSVD0_MASK (0x8U) +#define USBPHY_RX_CLR_RSVD0_SHIFT (3U) +#define USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK) +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) +#define USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_CLR_RSVD1_SHIFT (7U) +#define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK) +#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) +#define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_CLR_RSVD2_SHIFT (23U) +#define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK) + +/*! @name RX_TOG - USB PHY Receiver Control Register */ +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) +#define USBPHY_RX_TOG_RSVD0_MASK (0x8U) +#define USBPHY_RX_TOG_RSVD0_SHIFT (3U) +#define USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK) +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) +#define USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_TOG_RSVD1_SHIFT (7U) +#define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK) +#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) +#define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_TOG_RSVD2_SHIFT (23U) +#define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK) + +/*! @name CTRL - USB PHY General Control Register */ +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK) +#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) + +/*! @name CTRL_SET - USB PHY General Control Register */ +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_SET_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) + +/*! @name CTRL_CLR - USB PHY General Control Register */ +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_CLR_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) + +/*! @name CTRL_TOG - USB PHY General Control Register */ +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_TOG_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) + +/*! @name STATUS - USB PHY Status Register */ +#define USBPHY_STATUS_RSVD0_MASK (0x7U) +#define USBPHY_STATUS_RSVD0_SHIFT (0U) +#define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) +#define USBPHY_STATUS_RSVD1_MASK (0x30U) +#define USBPHY_STATUS_RSVD1_SHIFT (4U) +#define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) +#define USBPHY_STATUS_RSVD2_MASK (0x80U) +#define USBPHY_STATUS_RSVD2_SHIFT (7U) +#define USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK) +#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) +#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) +#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) +#define USBPHY_STATUS_RSVD3_MASK (0x200U) +#define USBPHY_STATUS_RSVD3_SHIFT (9U) +#define USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK) +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +#define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U) +#define USBPHY_STATUS_RSVD4_SHIFT (11U) +#define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK) + +/*! @name DEBUG - USB PHY Debug Register */ +#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK) +#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK) +#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK) +#define USBPHY_DEBUG_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK) + +/*! @name DEBUG_SET - USB PHY Debug Register */ +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_SET_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_SET_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_SET_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK) +#define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK) + +/*! @name DEBUG_CLR - USB PHY Debug Register */ +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK) +#define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK) + +/*! @name DEBUG_TOG - USB PHY Debug Register */ +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK) +#define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK) + +/*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */ +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK) + +/*! @name DEBUG1 - UTMI Debug Status Register 1 */ +#define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK) +#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK) + +/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ +#define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK) + +/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ +#define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK) + +/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ +#define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK) + +/*! @name VERSION - UTMI RTL Version */ +#define USBPHY_VERSION_STEP_MASK (0xFFFFU) +#define USBPHY_VERSION_STEP_SHIFT (0U) +#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) +#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) +#define USBPHY_VERSION_MINOR_SHIFT (16U) +#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) +#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) +#define USBPHY_VERSION_MAJOR_SHIFT (24U) +#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +/** Peripheral USBPHY1 base address */ +#define USBPHY1_BASE (0x20C9000u) +/** Peripheral USBPHY1 base pointer */ +#define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) +/** Peripheral USBPHY2 base address */ +#define USBPHY2_BASE (0x20CA000u) +/** Peripheral USBPHY2 base pointer */ +#define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) +/** Array initializer of USBPHY peripheral base addresses */ +#define USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE } +/** Array initializer of USBPHY peripheral base pointers */ +#define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 } +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer + * @{ + */ + +/** USB_ANALOG - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x60 */ + __IO uint32_t VBUS_DETECT; /**< USB VBUS Detect Register, array offset: 0x0, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_SET; /**< USB VBUS Detect Register, array offset: 0x4, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_CLR; /**< USB VBUS Detect Register, array offset: 0x8, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_TOG; /**< USB VBUS Detect Register, array offset: 0xC, array step: 0x60 */ + __IO uint32_t CHRG_DETECT; /**< USB Charger Detect Register, array offset: 0x10, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_SET; /**< USB Charger Detect Register, array offset: 0x14, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_CLR; /**< USB Charger Detect Register, array offset: 0x18, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_TOG; /**< USB Charger Detect Register, array offset: 0x1C, array step: 0x60 */ + __I uint32_t VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, array offset: 0x20, array step: 0x60 */ + uint8_t RESERVED_0[12]; + __I uint32_t CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, array offset: 0x30, array step: 0x60 */ + uint8_t RESERVED_1[28]; + __IO uint32_t MISC; /**< USB Misc Register, array offset: 0x50, array step: 0x60 */ + __IO uint32_t MISC_SET; /**< USB Misc Register, array offset: 0x54, array step: 0x60 */ + __IO uint32_t MISC_CLR; /**< USB Misc Register, array offset: 0x58, array step: 0x60 */ + __IO uint32_t MISC_TOG; /**< USB Misc Register, array offset: 0x5C, array step: 0x60 */ + } INSTANCE[2]; + __I uint32_t DIGPROG; /**< Chip Silicon Version, offset: 0xC0 */ +} USB_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks + * @{ + */ + +/*! @name VBUS_DETECT - USB VBUS Detect Register */ +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT */ +#define USB_ANALOG_VBUS_DETECT_COUNT (2U) + +/*! @name VBUS_DETECT_SET - USB VBUS Detect Register */ +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT_SET */ +#define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U) + +/*! @name VBUS_DETECT_CLR - USB VBUS Detect Register */ +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT_CLR */ +#define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U) + +/*! @name VBUS_DETECT_TOG - USB VBUS Detect Register */ +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT_TOG */ +#define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U) + +/*! @name CHRG_DETECT - USB Charger Detect Register */ +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT */ +#define USB_ANALOG_CHRG_DETECT_COUNT (2U) + +/*! @name CHRG_DETECT_SET - USB Charger Detect Register */ +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT_SET */ +#define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U) + +/*! @name CHRG_DETECT_CLR - USB Charger Detect Register */ +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT_CLR */ +#define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U) + +/*! @name CHRG_DETECT_TOG - USB Charger Detect Register */ +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT_TOG */ +#define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U) + +/*! @name VBUS_DETECT_STAT - USB VBUS Detect Status Register */ +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U) +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT_STAT */ +#define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U) + +/*! @name CHRG_DETECT_STAT - USB Charger Detect Status Register */ +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U) +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U) +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT_STAT */ +#define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U) + +/*! @name MISC - USB Misc Register */ +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK) + +/* The count of USB_ANALOG_MISC */ +#define USB_ANALOG_MISC_COUNT (2U) + +/*! @name MISC_SET - USB Misc Register */ +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK) + +/* The count of USB_ANALOG_MISC_SET */ +#define USB_ANALOG_MISC_SET_COUNT (2U) + +/*! @name MISC_CLR - USB Misc Register */ +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK) + +/* The count of USB_ANALOG_MISC_CLR */ +#define USB_ANALOG_MISC_CLR_COUNT (2U) + +/*! @name MISC_TOG - USB Misc Register */ +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK) + +/* The count of USB_ANALOG_MISC_TOG */ +#define USB_ANALOG_MISC_TOG_COUNT (2U) + +/*! @name DIGPROG - Chip Silicon Version */ +#define USB_ANALOG_DIGPROG_MINOR_MASK (0xFFU) +#define USB_ANALOG_DIGPROG_MINOR_SHIFT (0U) +#define USB_ANALOG_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MINOR_SHIFT)) & USB_ANALOG_DIGPROG_MINOR_MASK) +#define USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK (0xFF00U) +#define USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT (8U) +#define USB_ANALOG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK) +#define USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U) +#define USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT (16U) +#define USB_ANALOG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK) + + +/*! + * @} + */ /* end of group USB_ANALOG_Register_Masks */ + + +/* USB_ANALOG - Peripheral instance base addresses */ +/** Peripheral USB_ANALOG base address */ +#define USB_ANALOG_BASE (0x20C81A0u) +/** Peripheral USB_ANALOG base pointer */ +#define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE) +/** Array initializer of USB_ANALOG peripheral base addresses */ +#define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE } +/** Array initializer of USB_ANALOG peripheral base pointers */ +#define USB_ANALOG_BASE_PTRS { USB_ANALOG } + +/*! + * @} + */ /* end of group USB_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USDHC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer + * @{ + */ + +/** USDHC - Register Layout Typedef */ +typedef struct { + __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ + __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ + __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ + __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ + __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ + __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ + __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ + __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ + __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ + __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ + __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ + __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ + __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ + __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ + __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ + __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ + __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ + __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ + __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ + __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */ + __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ + __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ + __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ + uint8_t RESERVED_2[84]; + __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ + __IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */ + __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ + __IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */ +} USDHC_Type; + +/* ---------------------------------------------------------------------------- + -- USDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Register_Masks USDHC Register Masks + * @{ + */ + +/*! @name DS_ADDR - DMA System Address */ +#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) +#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) +#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) + +/*! @name BLK_ATT - Block Attributes */ +#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) +#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) +#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) +#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) +#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) +#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) + +/*! @name CMD_ARG - Command Argument */ +#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) +#define USDHC_CMD_ARG_CMDARG_SHIFT (0U) +#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) + +/*! @name CMD_XFR_TYP - Command Transfer Type */ +#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) +#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) +#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) +#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) +#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) +#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) +#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) +#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) +#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) +#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) +#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) +#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) +#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) +#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) +#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) +#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) +#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) +#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) + +/*! @name CMD_RSP0 - Command Response0 */ +#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) +#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) + +/*! @name CMD_RSP1 - Command Response1 */ +#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) +#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) + +/*! @name CMD_RSP2 - Command Response2 */ +#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) +#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) + +/*! @name CMD_RSP3 - Command Response3 */ +#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) +#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) + +/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) + +/*! @name PRES_STATE - Present State */ +#define USDHC_PRES_STATE_CIHB_MASK (0x1U) +#define USDHC_PRES_STATE_CIHB_SHIFT (0U) +#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) +#define USDHC_PRES_STATE_CDIHB_MASK (0x2U) +#define USDHC_PRES_STATE_CDIHB_SHIFT (1U) +#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) +#define USDHC_PRES_STATE_DLA_MASK (0x4U) +#define USDHC_PRES_STATE_DLA_SHIFT (2U) +#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) +#define USDHC_PRES_STATE_SDSTB_MASK (0x8U) +#define USDHC_PRES_STATE_SDSTB_SHIFT (3U) +#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) +#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) +#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) +#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) +#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) +#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) +#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) +#define USDHC_PRES_STATE_PEROFF_MASK (0x40U) +#define USDHC_PRES_STATE_PEROFF_SHIFT (6U) +#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) +#define USDHC_PRES_STATE_SDOFF_MASK (0x80U) +#define USDHC_PRES_STATE_SDOFF_SHIFT (7U) +#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) +#define USDHC_PRES_STATE_WTA_MASK (0x100U) +#define USDHC_PRES_STATE_WTA_SHIFT (8U) +#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) +#define USDHC_PRES_STATE_RTA_MASK (0x200U) +#define USDHC_PRES_STATE_RTA_SHIFT (9U) +#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) +#define USDHC_PRES_STATE_BWEN_MASK (0x400U) +#define USDHC_PRES_STATE_BWEN_SHIFT (10U) +#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) +#define USDHC_PRES_STATE_BREN_MASK (0x800U) +#define USDHC_PRES_STATE_BREN_SHIFT (11U) +#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) +#define USDHC_PRES_STATE_RTR_MASK (0x1000U) +#define USDHC_PRES_STATE_RTR_SHIFT (12U) +#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) +#define USDHC_PRES_STATE_TSCD_MASK (0x8000U) +#define USDHC_PRES_STATE_TSCD_SHIFT (15U) +#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) +#define USDHC_PRES_STATE_CINST_MASK (0x10000U) +#define USDHC_PRES_STATE_CINST_SHIFT (16U) +#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) +#define USDHC_PRES_STATE_CDPL_MASK (0x40000U) +#define USDHC_PRES_STATE_CDPL_SHIFT (18U) +#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) +#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) +#define USDHC_PRES_STATE_WPSPL_SHIFT (19U) +#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) +#define USDHC_PRES_STATE_CLSL_MASK (0x800000U) +#define USDHC_PRES_STATE_CLSL_SHIFT (23U) +#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) +#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) +#define USDHC_PRES_STATE_DLSL_SHIFT (24U) +#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) + +/*! @name PROT_CTRL - Protocol Control */ +#define USDHC_PROT_CTRL_LCTL_MASK (0x1U) +#define USDHC_PROT_CTRL_LCTL_SHIFT (0U) +#define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) +#define USDHC_PROT_CTRL_DTW_MASK (0x6U) +#define USDHC_PROT_CTRL_DTW_SHIFT (1U) +#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) +#define USDHC_PROT_CTRL_D3CD_MASK (0x8U) +#define USDHC_PROT_CTRL_D3CD_SHIFT (3U) +#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) +#define USDHC_PROT_CTRL_EMODE_MASK (0x30U) +#define USDHC_PROT_CTRL_EMODE_SHIFT (4U) +#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) +#define USDHC_PROT_CTRL_CDTL_MASK (0x40U) +#define USDHC_PROT_CTRL_CDTL_SHIFT (6U) +#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) +#define USDHC_PROT_CTRL_CDSS_MASK (0x80U) +#define USDHC_PROT_CTRL_CDSS_SHIFT (7U) +#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) +#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) +#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) +#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) +#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) +#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) +#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) +#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) +#define USDHC_PROT_CTRL_CREQ_SHIFT (17U) +#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) +#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) +#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) +#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) +#define USDHC_PROT_CTRL_IABG_MASK (0x80000U) +#define USDHC_PROT_CTRL_IABG_SHIFT (19U) +#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) +#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) +#define USDHC_PROT_CTRL_WECINT_SHIFT (24U) +#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) +#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) +#define USDHC_PROT_CTRL_WECINS_SHIFT (25U) +#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) +#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) +#define USDHC_PROT_CTRL_WECRM_SHIFT (26U) +#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) +#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U) +#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U) +#define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) + +/*! @name SYS_CTRL - System Control */ +#define USDHC_SYS_CTRL_DVS_MASK (0xF0U) +#define USDHC_SYS_CTRL_DVS_SHIFT (4U) +#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) +#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) +#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) +#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) +#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) +#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) +#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) +#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) +#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) +#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) +#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) +#define USDHC_SYS_CTRL_RSTA_SHIFT (24U) +#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) +#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) +#define USDHC_SYS_CTRL_RSTC_SHIFT (25U) +#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) +#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) +#define USDHC_SYS_CTRL_RSTD_SHIFT (26U) +#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) +#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) +#define USDHC_SYS_CTRL_INITA_SHIFT (27U) +#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) +#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) +#define USDHC_SYS_CTRL_RSTT_SHIFT (28U) +#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) + +/*! @name INT_STATUS - Interrupt Status */ +#define USDHC_INT_STATUS_CC_MASK (0x1U) +#define USDHC_INT_STATUS_CC_SHIFT (0U) +#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) +#define USDHC_INT_STATUS_TC_MASK (0x2U) +#define USDHC_INT_STATUS_TC_SHIFT (1U) +#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) +#define USDHC_INT_STATUS_BGE_MASK (0x4U) +#define USDHC_INT_STATUS_BGE_SHIFT (2U) +#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) +#define USDHC_INT_STATUS_DINT_MASK (0x8U) +#define USDHC_INT_STATUS_DINT_SHIFT (3U) +#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) +#define USDHC_INT_STATUS_BWR_MASK (0x10U) +#define USDHC_INT_STATUS_BWR_SHIFT (4U) +#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) +#define USDHC_INT_STATUS_BRR_MASK (0x20U) +#define USDHC_INT_STATUS_BRR_SHIFT (5U) +#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) +#define USDHC_INT_STATUS_CINS_MASK (0x40U) +#define USDHC_INT_STATUS_CINS_SHIFT (6U) +#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) +#define USDHC_INT_STATUS_CRM_MASK (0x80U) +#define USDHC_INT_STATUS_CRM_SHIFT (7U) +#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) +#define USDHC_INT_STATUS_CINT_MASK (0x100U) +#define USDHC_INT_STATUS_CINT_SHIFT (8U) +#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) +#define USDHC_INT_STATUS_RTE_MASK (0x1000U) +#define USDHC_INT_STATUS_RTE_SHIFT (12U) +#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) +#define USDHC_INT_STATUS_TP_MASK (0x4000U) +#define USDHC_INT_STATUS_TP_SHIFT (14U) +#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) +#define USDHC_INT_STATUS_CTOE_MASK (0x10000U) +#define USDHC_INT_STATUS_CTOE_SHIFT (16U) +#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) +#define USDHC_INT_STATUS_CCE_MASK (0x20000U) +#define USDHC_INT_STATUS_CCE_SHIFT (17U) +#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) +#define USDHC_INT_STATUS_CEBE_MASK (0x40000U) +#define USDHC_INT_STATUS_CEBE_SHIFT (18U) +#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) +#define USDHC_INT_STATUS_CIE_MASK (0x80000U) +#define USDHC_INT_STATUS_CIE_SHIFT (19U) +#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) +#define USDHC_INT_STATUS_DTOE_MASK (0x100000U) +#define USDHC_INT_STATUS_DTOE_SHIFT (20U) +#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) +#define USDHC_INT_STATUS_DCE_MASK (0x200000U) +#define USDHC_INT_STATUS_DCE_SHIFT (21U) +#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) +#define USDHC_INT_STATUS_DEBE_MASK (0x400000U) +#define USDHC_INT_STATUS_DEBE_SHIFT (22U) +#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) +#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) +#define USDHC_INT_STATUS_AC12E_SHIFT (24U) +#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) +#define USDHC_INT_STATUS_TNE_MASK (0x4000000U) +#define USDHC_INT_STATUS_TNE_SHIFT (26U) +#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) +#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) +#define USDHC_INT_STATUS_DMAE_SHIFT (28U) +#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) + +/*! @name INT_STATUS_EN - Interrupt Status Enable */ +#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) +#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) +#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) +#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) +#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) +#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) +#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) +#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) +#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) +#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) +#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) +#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) +#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) +#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) +#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) +#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) +#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) +#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) +#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) +#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) +#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) +#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) +#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) +#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) +#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) +#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) +#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) +#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) +#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) +#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) +#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U) +#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U) +#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) +#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) +#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) +#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) +#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) +#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) +#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) +#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) +#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) +#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) +#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) +#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) +#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) +#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) +#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) +#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) +#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) +#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) +#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) +#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) +#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) +#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) +#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) +#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) +#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) +#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) +#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) +#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) +#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) +#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) +#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) + +/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ +#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) +#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) +#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) +#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) +#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) +#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) +#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) +#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) +#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) +#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) +#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) +#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) +#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) +#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) +#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) +#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) +#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) +#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) +#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) +#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) +#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) +#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U) +#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U) +#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) +#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) +#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) +#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) +#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) +#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) +#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) +#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) +#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) +#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) +#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) +#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) +#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) +#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) +#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) + +/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) + +/*! @name HOST_CTRL_CAP - Host Controller Capabilities */ +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) +#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) +#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) +#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) +#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) +#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) +#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) +#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) +#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) +#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) +#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) +#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) +#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) +#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) +#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) +#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) +#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) +#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) +#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) +#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) +#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) +#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) +#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) +#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) +#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) + +/*! @name WTMK_LVL - Watermark Level */ +#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) +#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) +#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) +#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U) +#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U) +#define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK) +#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) +#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) +#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) +#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) +#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) +#define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) + +/*! @name MIX_CTRL - Mixer Control */ +#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) +#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) +#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) +#define USDHC_MIX_CTRL_BCEN_MASK (0x2U) +#define USDHC_MIX_CTRL_BCEN_SHIFT (1U) +#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) +#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) +#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) +#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) +#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) +#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) +#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) +#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) +#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) +#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) +#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) +#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) +#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) +#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) +#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) +#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) +#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) +#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) +#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) +#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) +#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) +#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) +#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) +#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) +#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) +#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) + +/*! @name FORCE_EVENT - Force Event */ +#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) +#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) +#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) +#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) +#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) +#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) +#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) +#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) +#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) +#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) +#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) +#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) +#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) +#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) +#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) +#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) +#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) +#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) +#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) +#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) +#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) +#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) +#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) +#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) +#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) +#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) +#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) +#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) +#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) +#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) +#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) +#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) +#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) +#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) +#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) +#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) +#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) +#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) +#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) +#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) +#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) + +/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */ +#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) +#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) +#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) +#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) +#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) +#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) +#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) + +/*! @name ADMA_SYS_ADDR - ADMA System Address */ +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) + +/*! @name DLL_CTRL - DLL (Delay Line) Control */ +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) + +/*! @name DLL_STATUS - DLL Status */ +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) + +/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) + +/*! @name VEND_SPEC - Vendor Specific Register */ +#define USDHC_VEND_SPEC_EXT_DMA_EN_MASK (0x1U) +#define USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT (0U) +#define USDHC_VEND_SPEC_EXT_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT)) & USDHC_VEND_SPEC_EXT_DMA_EN_MASK) +#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) +#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) +#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) +#define USDHC_VEND_SPEC_DAT3_CD_POL_MASK (0x10U) +#define USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT (4U) +#define USDHC_VEND_SPEC_DAT3_CD_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT)) & USDHC_VEND_SPEC_DAT3_CD_POL_MASK) +#define USDHC_VEND_SPEC_CD_POL_MASK (0x20U) +#define USDHC_VEND_SPEC_CD_POL_SHIFT (5U) +#define USDHC_VEND_SPEC_CD_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CD_POL_SHIFT)) & USDHC_VEND_SPEC_CD_POL_MASK) +#define USDHC_VEND_SPEC_WP_POL_MASK (0x40U) +#define USDHC_VEND_SPEC_WP_POL_SHIFT (6U) +#define USDHC_VEND_SPEC_WP_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_WP_POL_SHIFT)) & USDHC_VEND_SPEC_WP_POL_MASK) +#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK (0x80U) +#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT (7U) +#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT)) & USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) +#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK (0x800U) +#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT (11U) +#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK) +#define USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK (0x1000U) +#define USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT (12U) +#define USDHC_VEND_SPEC_HCLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK) +#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK (0x2000U) +#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT (13U) +#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK) +#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK (0x4000U) +#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT (14U) +#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) +#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) +#define USDHC_VEND_SPEC_INT_ST_VAL_MASK (0xFF0000U) +#define USDHC_VEND_SPEC_INT_ST_VAL_SHIFT (16U) +#define USDHC_VEND_SPEC_INT_ST_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_INT_ST_VAL_SHIFT)) & USDHC_VEND_SPEC_INT_ST_VAL_MASK) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) +#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) + +/*! @name MMC_BOOT - MMC Boot Register */ +#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) +#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) +#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) +#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) +#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) +#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) +#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) +#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) +#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) +#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) +#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) +#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) + +/*! @name VEND_SPEC2 - Vendor Specific 2 Register */ +#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK (0x1U) +#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT (0U) +#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK) +#define USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK (0x2U) +#define USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT (1U) +#define USDHC_VEND_SPEC2_SDR104_OE_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK) +#define USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK (0x4U) +#define USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT (2U) +#define USDHC_VEND_SPEC2_SDR104_NSD_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) +#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK (0x80U) +#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT (7U) +#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x800000U) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (23U) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) + +/*! @name TUNING_CTRL - Tuning Control Register */ +#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU) +#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) +#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) +#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) +#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) +#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) + + +/*! + * @} + */ /* end of group USDHC_Register_Masks */ + + +/* USDHC - Peripheral instance base addresses */ +/** Peripheral USDHC1 base address */ +#define USDHC1_BASE (0x2190000u) +/** Peripheral USDHC1 base pointer */ +#define USDHC1 ((USDHC_Type *)USDHC1_BASE) +/** Peripheral USDHC2 base address */ +#define USDHC2_BASE (0x2194000u) +/** Peripheral USDHC2 base pointer */ +#define USDHC2 ((USDHC_Type *)USDHC2_BASE) +/** Array initializer of USDHC peripheral base addresses */ +#define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE } +/** Array initializer of USDHC peripheral base pointers */ +#define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 } +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn } + +/*! + * @} + */ /* end of group USDHC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */ + __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */ + __I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */ + __IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */ + __IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */ +} WDOG_Type; + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/*! @name WCR - Watchdog Control Register */ +#define WDOG_WCR_WDZST_MASK (0x1U) +#define WDOG_WCR_WDZST_SHIFT (0U) +#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) +#define WDOG_WCR_WDBG_MASK (0x2U) +#define WDOG_WCR_WDBG_SHIFT (1U) +#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) +#define WDOG_WCR_WDE_MASK (0x4U) +#define WDOG_WCR_WDE_SHIFT (2U) +#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) +#define WDOG_WCR_WDT_MASK (0x8U) +#define WDOG_WCR_WDT_SHIFT (3U) +#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) +#define WDOG_WCR_SRS_MASK (0x10U) +#define WDOG_WCR_SRS_SHIFT (4U) +#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) +#define WDOG_WCR_WDA_MASK (0x20U) +#define WDOG_WCR_WDA_SHIFT (5U) +#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) +#define WDOG_WCR_SRE_MASK (0x40U) +#define WDOG_WCR_SRE_SHIFT (6U) +#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) +#define WDOG_WCR_WDW_MASK (0x80U) +#define WDOG_WCR_WDW_SHIFT (7U) +#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) +#define WDOG_WCR_WT_MASK (0xFF00U) +#define WDOG_WCR_WT_SHIFT (8U) +#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) + +/*! @name WSR - Watchdog Service Register */ +#define WDOG_WSR_WSR_MASK (0xFFFFU) +#define WDOG_WSR_WSR_SHIFT (0U) +#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) + +/*! @name WRSR - Watchdog Reset Status Register */ +#define WDOG_WRSR_SFTW_MASK (0x1U) +#define WDOG_WRSR_SFTW_SHIFT (0U) +#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) +#define WDOG_WRSR_TOUT_MASK (0x2U) +#define WDOG_WRSR_TOUT_SHIFT (1U) +#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) +#define WDOG_WRSR_POR_MASK (0x10U) +#define WDOG_WRSR_POR_SHIFT (4U) +#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) + +/*! @name WICR - Watchdog Interrupt Control Register */ +#define WDOG_WICR_WICT_MASK (0xFFU) +#define WDOG_WICR_WICT_SHIFT (0U) +#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) +#define WDOG_WICR_WTIS_MASK (0x4000U) +#define WDOG_WICR_WTIS_SHIFT (14U) +#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) +#define WDOG_WICR_WIE_MASK (0x8000U) +#define WDOG_WICR_WIE_SHIFT (15U) +#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) + +/*! @name WMCR - Watchdog Miscellaneous Control Register */ +#define WDOG_WMCR_PDE_MASK (0x1U) +#define WDOG_WMCR_PDE_SHIFT (0U) +#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) + + +/*! + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG1 base address */ +#define WDOG1_BASE (0x20BC000u) +/** Peripheral WDOG1 base pointer */ +#define WDOG1 ((WDOG_Type *)WDOG1_BASE) +/** Peripheral WDOG2 base address */ +#define WDOG2_BASE (0x20C0000u) +/** Peripheral WDOG2 base pointer */ +#define WDOG2 ((WDOG_Type *)WDOG2_BASE) +/** Peripheral WDOG3 base address */ +#define WDOG3_BASE (0x21E4000u) +/** Peripheral WDOG3 base pointer */ +#define WDOG3 ((WDOG_Type *)WDOG3_BASE) +/** Array initializer of WDOG peripheral base addresses */ +#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE, WDOG3_BASE } +/** Array initializer of WDOG peripheral base pointers */ +#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2, WDOG3 } +/** Interrupt vectors for the WDOG peripheral type */ +#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn, WDOG3_IRQn } + +/*! + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Peripheral_Access_Layer XTALOSC24M Peripheral Access Layer + * @{ + */ + +/** XTALOSC24M - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[336]; + __IO uint32_t OSC_CONFIG0; /**< XTAL OSC Configuration 0 Register, offset: 0x150 */ + __IO uint32_t OSC_CONFIG0_SET; /**< XTAL OSC Configuration 0 Register, offset: 0x154 */ + __IO uint32_t OSC_CONFIG0_CLR; /**< XTAL OSC Configuration 0 Register, offset: 0x158 */ + __IO uint32_t OSC_CONFIG0_TOG; /**< XTAL OSC Configuration 0 Register, offset: 0x15C */ + __IO uint32_t OSC_CONFIG1; /**< XTAL OSC Configuration 1 Register, offset: 0x160 */ + __IO uint32_t OSC_CONFIG1_SET; /**< XTAL OSC Configuration 1 Register, offset: 0x164 */ + __IO uint32_t OSC_CONFIG1_CLR; /**< XTAL OSC Configuration 1 Register, offset: 0x168 */ + __IO uint32_t OSC_CONFIG1_TOG; /**< XTAL OSC Configuration 1 Register, offset: 0x16C */ + __IO uint32_t OSC_CONFIG2; /**< XTAL OSC Configuration 2 Register, offset: 0x170 */ + __IO uint32_t OSC_CONFIG2_SET; /**< XTAL OSC Configuration 2 Register, offset: 0x174 */ + __IO uint32_t OSC_CONFIG2_CLR; /**< XTAL OSC Configuration 2 Register, offset: 0x178 */ + __IO uint32_t OSC_CONFIG2_TOG; /**< XTAL OSC Configuration 2 Register, offset: 0x17C */ +} XTALOSC24M_Type; + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks + * @{ + */ + +/*! @name OSC_CONFIG0 - XTAL OSC Configuration 0 Register */ +#define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK) + +/*! @name OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register */ +#define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK) + +/*! @name OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register */ +#define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK) + +/*! @name OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register */ +#define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK) + +/*! @name OSC_CONFIG1 - XTAL OSC Configuration 1 Register */ +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK) + +/*! @name OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register */ +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK) + +/*! @name OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register */ +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK) + +/*! @name OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register */ +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK) + +/*! @name OSC_CONFIG2 - XTAL OSC Configuration 2 Register */ +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK) + +/*! @name OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register */ +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK) + +/*! @name OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register */ +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK) + +/*! @name OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register */ +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK) + + +/*! + * @} + */ /* end of group XTALOSC24M_Register_Masks */ + + +/* XTALOSC24M - Peripheral instance base addresses */ +/** Peripheral XTALOSC24M base address */ +#define XTALOSC24M_BASE (0x20C8150u) +/** Peripheral XTALOSC24M base pointer */ +#define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE) +/** Array initializer of XTALOSC24M peripheral base addresses */ +#define XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE } +/** Array initializer of XTALOSC24M peripheral base pointers */ +#define XTALOSC24M_BASE_PTRS { XTALOSC24M } + +/*! + * @} + */ /* end of group XTALOSC24M_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _MCIMX6Y2_H_ */ + diff --git a/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/chip/chip.h b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/chip/chip.h new file mode 100644 index 00000000..6ef88064 --- /dev/null +++ b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/chip/chip.h @@ -0,0 +1,25 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _PLATFORM_H_ +#define _PLATFORM_H_ + +#define INTERRUPT_MAX 128 +#define KERNEL_BASE 0X87800000 + +#endif /* _CHIP_H_ */ + diff --git a/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/chip/gic.h b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/chip/gic.h new file mode 100644 index 00000000..9bb044a8 --- /dev/null +++ b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/chip/gic.h @@ -0,0 +1,27 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _GIC_H_ +#define _GIC_H_ + +#define GICD_OFFSET 0x1000 +#define GICC_OFFSET 0x2000 +#define GIC_PRIO_BITS 5 /**< Number of Bits used for Priority Levels */ +#define GIC_NRS 1 /**< how many gic on this chip? */ + +#endif /* _GIC_H_ */ + diff --git a/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/clock.h b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/clock.h new file mode 100644 index 00000000..cc0c1b51 --- /dev/null +++ b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/clock.h @@ -0,0 +1,25 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _CLOCK_H_ +#define _CLOCK_H_ + +void clock_init(void); +void clock_enable(void); + +#endif + diff --git a/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/core_ca7.h b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/core_ca7.h new file mode 100644 index 00000000..d2a3bebd --- /dev/null +++ b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/core_ca7.h @@ -0,0 +1,723 @@ +#ifndef __CORTEX_CA7_H +#define __CORTEX_CA7_H + +#include +#include + +#define FORCEDINLINE __attribute__((always_inline)) +#define __ASM __asm /* GNU C语言内嵌汇编关键字 */ +#define __INLINE inline /* GNU内联关键字 */ +#define __STATIC_INLINE static inline + + +#define __IM volatile const /* 只读 */ +#define __OM volatile /* 只写 */ +#define __IOM volatile /* 读写 */ +#define __STRINGIFY(x) #x + +/* C语言实现MCR指令 */ +#define __MCR(coproc, opcode_1, src, CRn, CRm, opcode_2) \ + __ASM volatile ("MCR " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \ + "%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " \ + __STRINGIFY(opcode_2) \ + : : "r" (src) ) + +/* C语言实现MRC指令 */ +#define __MRC(coproc, opcode_1, CRn, CRm, opcode_2) \ + ({ \ + uint32_t __dst; \ + __ASM volatile ("MRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \ + "%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " \ + __STRINGIFY(opcode_2) \ + : "=r" (__dst) ); \ + __dst; \ + }) + +/* 其他一些C语言内嵌汇编 */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_APSR(uint32_t apsr) +{ + __ASM volatile ("MSR apsr, %0" : : "r" (apsr) : "cc"); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc"); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void) +{ + uint32_t result; + + __ASM volatile ("VMRS %0, fpexc" : "=r" (result) ); + return result; +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) +{ + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc)); +} + + +/******************************************************************************* + * 一些内核寄存器定义和抽象 + 定义如下几个内核寄存器: + - CPSR + - CP15 + ******************************************************************************/ + +/* CPSR寄存器 + * 参考资料：ARM Cortex-A(armV7)编程手册V4.0.pdf P46 + */ +typedef union +{ + struct + { + uint32_t M:5; /*!< bit: 0.. 4 Mode field */ + uint32_t T:1; /*!< bit: 5 Thumb execution state bit */ + uint32_t F:1; /*!< bit: 6 FIQ mask bit */ + uint32_t I:1; /*!< bit: 7 IRQ mask bit */ + uint32_t A:1; /*!< bit: 8 Asynchronous abort mask bit */ + uint32_t E:1; /*!< bit: 9 Endianness execution state bit */ + uint32_t IT1:6; /*!< bit: 10..15 If-Then execution state bits 2-7 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved0:4; /*!< bit: 20..23 Reserved */ + uint32_t J:1; /*!< bit: 24 Jazelle bit */ + uint32_t IT0:2; /*!< bit: 25..26 If-Then execution state bits 0-1 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CPSR_Type; + + +/* CP15的SCTLR寄存器 + * 参考资料：Cortex-A7 Technical ReferenceManua.pdf P105 + */ +typedef union +{ + struct + { + uint32_t M:1; /*!< bit: 0 MMU enable */ + uint32_t A:1; /*!< bit: 1 Alignment check enable */ + uint32_t C:1; /*!< bit: 2 Cache enable */ + uint32_t _reserved0:2; /*!< bit: 3.. 4 Reserved */ + uint32_t CP15BEN:1; /*!< bit: 5 CP15 barrier enable */ + uint32_t _reserved1:1; /*!< bit: 6 Reserved */ + uint32_t B:1; /*!< bit: 7 Endianness model */ + uint32_t _reserved2:2; /*!< bit: 8.. 9 Reserved */ + uint32_t SW:1; /*!< bit: 10 SWP and SWPB enable */ + uint32_t Z:1; /*!< bit: 11 Branch prediction enable */ + uint32_t I:1; /*!< bit: 12 Instruction cache enable */ + uint32_t V:1; /*!< bit: 13 Vectors bit */ + uint32_t RR:1; /*!< bit: 14 Round Robin select */ + uint32_t _reserved3:2; /*!< bit:15..16 Reserved */ + uint32_t HA:1; /*!< bit: 17 Hardware Access flag enable */ + uint32_t _reserved4:1; /*!< bit: 18 Reserved */ + uint32_t WXN:1; /*!< bit: 19 Write permission implies XN */ + uint32_t UWXN:1; /*!< bit: 20 Unprivileged write permission implies PL1 XN */ + uint32_t FI:1; /*!< bit: 21 Fast interrupts configuration enable */ + uint32_t U:1; /*!< bit: 22 Alignment model */ + uint32_t _reserved5:1; /*!< bit: 23 Reserved */ + uint32_t VE:1; /*!< bit: 24 Interrupt Vectors Enable */ + uint32_t EE:1; /*!< bit: 25 Exception Endianness */ + uint32_t _reserved6:1; /*!< bit: 26 Reserved */ + uint32_t NMFI:1; /*!< bit: 27 Non-maskable FIQ (NMFI) support */ + uint32_t TRE:1; /*!< bit: 28 TEX remap enable. */ + uint32_t AFE:1; /*!< bit: 29 Access flag enable */ + uint32_t TE:1; /*!< bit: 30 Thumb Exception enable */ + uint32_t _reserved7:1; /*!< bit: 31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} SCTLR_Type; + +/* CP15 寄存器SCTLR各个位定义 */ +#define SCTLR_TE_Pos 30U /*!< SCTLR: TE Position */ +#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< SCTLR: TE Mask */ + +#define SCTLR_AFE_Pos 29U /*!< SCTLR: AFE Position */ +#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< SCTLR: AFE Mask */ + +#define SCTLR_TRE_Pos 28U /*!< SCTLR: TRE Position */ +#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< SCTLR: TRE Mask */ + +#define SCTLR_NMFI_Pos 27U /*!< SCTLR: NMFI Position */ +#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< SCTLR: NMFI Mask */ + +#define SCTLR_EE_Pos 25U /*!< SCTLR: EE Position */ +#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< SCTLR: EE Mask */ + +#define SCTLR_VE_Pos 24U /*!< SCTLR: VE Position */ +#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< SCTLR: VE Mask */ + +#define SCTLR_U_Pos 22U /*!< SCTLR: U Position */ +#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< SCTLR: U Mask */ + +#define SCTLR_FI_Pos 21U /*!< SCTLR: FI Position */ +#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< SCTLR: FI Mask */ + +#define SCTLR_UWXN_Pos 20U /*!< SCTLR: UWXN Position */ +#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< SCTLR: UWXN Mask */ + +#define SCTLR_WXN_Pos 19U /*!< SCTLR: WXN Position */ +#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< SCTLR: WXN Mask */ + +#define SCTLR_HA_Pos 17U /*!< SCTLR: HA Position */ +#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< SCTLR: HA Mask */ + +#define SCTLR_RR_Pos 14U /*!< SCTLR: RR Position */ +#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< SCTLR: RR Mask */ + +#define SCTLR_V_Pos 13U /*!< SCTLR: V Position */ +#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< SCTLR: V Mask */ + +#define SCTLR_I_Pos 12U /*!< SCTLR: I Position */ +#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< SCTLR: I Mask */ + +#define SCTLR_Z_Pos 11U /*!< SCTLR: Z Position */ +#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< SCTLR: Z Mask */ + +#define SCTLR_SW_Pos 10U /*!< SCTLR: SW Position */ +#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< SCTLR: SW Mask */ + +#define SCTLR_B_Pos 7U /*!< SCTLR: B Position */ +#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< SCTLR: B Mask */ + +#define SCTLR_CP15BEN_Pos 5U /*!< SCTLR: CP15BEN Position */ +#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< SCTLR: CP15BEN Mask */ + +#define SCTLR_C_Pos 2U /*!< SCTLR: C Position */ +#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< SCTLR: C Mask */ + +#define SCTLR_A_Pos 1U /*!< SCTLR: A Position */ +#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< SCTLR: A Mask */ + +#define SCTLR_M_Pos 0U /*!< SCTLR: M Position */ +#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< SCTLR: M Mask */ + +/* CP15的ACTLR寄存器 + * 参考资料:Cortex-A7 Technical ReferenceManua.pdf P113 + */ +typedef union +{ + struct + { + uint32_t _reserved0:6; /*!< bit: 0.. 5 Reserved */ + uint32_t SMP:1; /*!< bit: 6 Enables coherent requests to the processor */ + uint32_t _reserved1:3; /*!< bit: 7.. 9 Reserved */ + uint32_t DODMBS:1; /*!< bit: 10 Disable optimized data memory barrier behavior */ + uint32_t L2RADIS:1; /*!< bit: 11 L2 Data Cache read-allocate mode disable */ + uint32_t L1RADIS:1; /*!< bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< bit:13..14 L1 Data prefetch control */ + uint32_t DDVM:1; /*!< bit: 15 Disable Distributed Virtual Memory (DVM) transactions */ + uint32_t _reserved3:12; /*!< bit:16..27 Reserved */ + uint32_t DDI:1; /*!< bit: 28 Disable dual issue */ + uint32_t _reserved7:3; /*!< bit:29..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} ACTLR_Type; + +#define ACTLR_DDI_Pos 28U /*!< ACTLR: DDI Position */ +#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< ACTLR: DDI Mask */ + +#define ACTLR_DDVM_Pos 15U /*!< ACTLR: DDVM Position */ +#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< ACTLR: DDVM Mask */ + +#define ACTLR_L1PCTL_Pos 13U /*!< ACTLR: L1PCTL Position */ +#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< ACTLR: L1PCTL Mask */ + +#define ACTLR_L1RADIS_Pos 12U /*!< ACTLR: L1RADIS Position */ +#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< ACTLR: L1RADIS Mask */ + +#define ACTLR_L2RADIS_Pos 11U /*!< ACTLR: L2RADIS Position */ +#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< ACTLR: L2RADIS Mask */ + +#define ACTLR_DODMBS_Pos 10U /*!< ACTLR: DODMBS Position */ +#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< ACTLR: DODMBS Mask */ + +#define ACTLR_SMP_Pos 6U /*!< ACTLR: SMP Position */ +#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< ACTLR: SMP Mask */ + + +/* CP15的CPACR寄存器 + * 参考资料：Cortex-A7 Technical ReferenceManua.pdf P115 + */ +typedef union +{ + struct + { + uint32_t _reserved0:20; /*!< bit: 0..19 Reserved */ + uint32_t cp10:2; /*!< bit:20..21 Access rights for coprocessor 10 */ + uint32_t cp11:2; /*!< bit:22..23 Access rights for coprocessor 11 */ + uint32_t _reserved1:6; /*!< bit:24..29 Reserved */ + uint32_t D32DIS:1; /*!< bit: 30 Disable use of registers D16-D31 of the VFP register file */ + uint32_t ASEDIS:1; /*!< bit: 31 Disable Advanced SIMD Functionality */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CPACR_Type; + +#define CPACR_ASEDIS_Pos 31U /*!< CPACR: ASEDIS Position */ +#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< CPACR: ASEDIS Mask */ + +#define CPACR_D32DIS_Pos 30U /*!< CPACR: D32DIS Position */ +#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< CPACR: D32DIS Mask */ + +#define CPACR_cp11_Pos 22U /*!< CPACR: cp11 Position */ +#define CPACR_cp11_Msk (3UL << CPACR_cp11_Pos) /*!< CPACR: cp11 Mask */ + +#define CPACR_cp10_Pos 20U /*!< CPACR: cp10 Position */ +#define CPACR_cp10_Msk (3UL << CPACR_cp10_Pos) /*!< CPACR: cp10 Mask */ + + +/* CP15的DFSR寄存器 + * 参考资料：Cortex-A7 Technical ReferenceManua.pdf P128 + */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< bit: 0.. 3 Fault Status bits bit 0-3 */ + uint32_t Domain:4; /*!< bit: 4.. 7 Fault on which domain */ + uint32_t _reserved0:2; /*!< bit: 8.. 9 Reserved */ + uint32_t FS1:1; /*!< bit: 10 Fault Status bits bit 4 */ + uint32_t WnR:1; /*!< bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< bit: 12 External abort type */ + uint32_t CM:1; /*!< bit: 13 Cache maintenance fault */ + uint32_t _reserved1:18; /*!< bit:14..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} DFSR_Type; + +#define DFSR_CM_Pos 13U /*!< DFSR: CM Position */ +#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< DFSR: CM Mask */ + +#define DFSR_Ext_Pos 12U /*!< DFSR: Ext Position */ +#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< DFSR: Ext Mask */ + +#define DFSR_WnR_Pos 11U /*!< DFSR: WnR Position */ +#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< DFSR: WnR Mask */ + +#define DFSR_FS1_Pos 10U /*!< DFSR: FS1 Position */ +#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< DFSR: FS1 Mask */ + +#define DFSR_Domain_Pos 4U /*!< DFSR: Domain Position */ +#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< DFSR: Domain Mask */ + +#define DFSR_FS0_Pos 0U /*!< DFSR: FS0 Position */ +#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< DFSR: FS0 Mask */ + + +/* CP15的IFSR寄存器 + * 参考资料：Cortex-A7 Technical ReferenceManua.pdf P131 + */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< bit: 0.. 3 Fault Status bits bit 0-3 */ + uint32_t _reserved0:6; /*!< bit: 4.. 9 Reserved */ + uint32_t FS1:1; /*!< bit: 10 Fault Status bits bit 4 */ + uint32_t _reserved1:1; /*!< bit: 11 Reserved */ + uint32_t ExT:1; /*!< bit: 12 External abort type */ + uint32_t _reserved2:19; /*!< bit:13..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IFSR_Type; + +#define IFSR_ExT_Pos 12U /*!< IFSR: ExT Position */ +#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< IFSR: ExT Mask */ + +#define IFSR_FS1_Pos 10U /*!< IFSR: FS1 Position */ +#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< IFSR: FS1 Mask */ + +#define IFSR_FS0_Pos 0U /*!< IFSR: FS0 Position */ +#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< IFSR: FS0 Mask */ + + +/* CP15的ISR寄存器 + * 参考资料：ARM ArchitectureReference Manual ARMv7-A and ARMv7-R edition.pdf P1640 + */ +typedef union +{ + struct + { + uint32_t _reserved0:6; /*!< bit: 0.. 5 Reserved */ + uint32_t F:1; /*!< bit: 6 FIQ pending bit */ + uint32_t I:1; /*!< bit: 7 IRQ pending bit */ + uint32_t A:1; /*!< bit: 8 External abort pending bit */ + uint32_t _reserved1:23; /*!< bit:14..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} ISR_Type; + +#define ISR_A_Pos 13U /*!< ISR: A Position */ +#define ISR_A_Msk (1UL << ISR_A_Pos) /*!< ISR: A Mask */ + +#define ISR_I_Pos 12U /*!< ISR: I Position */ +#define ISR_I_Msk (1UL << ISR_I_Pos) /*!< ISR: I Mask */ + +#define ISR_F_Pos 11U /*!< ISR: F Position */ +#define ISR_F_Msk (1UL << ISR_F_Pos) /*!< ISR: F Mask */ + + +/* Mask and shift a bit field value for use in a register bit range. */ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/* Mask and shift a register value to extract a bit filed value. */ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + + +/******************************************************************************* + * CP15 访问函数 + ******************************************************************************/ + +FORCEDINLINE __STATIC_INLINE uint32_t __get_SCTLR(void) +{ + return __MRC(15, 0, 1, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) +{ + __MCR(15, 0, sctlr, 1, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_ACTLR(void) +{ + return __MRC(15, 0, 1, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE void __set_ACTLR(uint32_t actlr) +{ + __MCR(15, 0, actlr, 1, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_CPACR(void) +{ + return __MRC(15, 0, 1, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE void __set_CPACR(uint32_t cpacr) +{ + __MCR(15, 0, cpacr, 1, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_TTBR0(void) +{ + return __MRC(15, 0, 2, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) +{ + __MCR(15, 0, ttbr0, 2, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_TTBR1(void) +{ + return __MRC(15, 0, 2, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE void __set_TTBR1(uint32_t ttbr1) +{ + __MCR(15, 0, ttbr1, 2, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_TTBCR(void) +{ + return __MRC(15, 0, 2, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE void __set_TTBCR(uint32_t ttbcr) +{ + __MCR(15, 0, ttbcr, 2, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_DACR(void) +{ + return __MRC(15, 0, 3, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_DACR(uint32_t dacr) +{ + __MCR(15, 0, dacr, 3, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_DFSR(void) +{ + return __MRC(15, 0, 5, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_DFSR(uint32_t dfsr) +{ + __MCR(15, 0, dfsr, 5, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_IFSR(void) +{ + return __MRC(15, 0, 5, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE void __set_IFSR(uint32_t ifsr) +{ + __MCR(15, 0, ifsr, 5, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_DFAR(void) +{ + return __MRC(15, 0, 6, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_DFAR(uint32_t dfar) +{ + __MCR(15, 0, dfar, 6, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_IFAR(void) +{ + return __MRC(15, 0, 6, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE void __set_IFAR(uint32_t ifar) +{ + __MCR(15, 0, ifar, 6, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_VBAR(void) +{ + return __MRC(15, 0, 12, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_VBAR(uint32_t vbar) +{ + __MCR(15, 0, vbar, 12, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_ISR(void) +{ + return __MRC(15, 0, 12, 1, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_ISR(uint32_t isr) +{ + __MCR(15, 0, isr, 12, 1, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_CONTEXTIDR(void) +{ + return __MRC(15, 0, 13, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE void __set_CONTEXTIDR(uint32_t contextidr) +{ + __MCR(15, 0, contextidr, 13, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_CBAR(void) +{ + return __MRC(15, 4, 15, 0, 0); +} + +/******************************************************************************* + * GIC相关内容 + *有关GIC的内容，参考：ARM Generic Interrupt Controller(ARM GIC控制器)V2.0.pdf + ******************************************************************************/ + +/* + * GIC寄存器描述结构体， + * GIC分为分发器端和CPU接口端 + */ +typedef struct +{ + uint32_t RESERVED0[1024]; + __IOM uint32_t D_CTLR; /*!< Offset: 0x1000 (R/W) Distributor Control Register */ + __IM uint32_t D_TYPER; /*!< Offset: 0x1004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t D_IIDR; /*!< Offset: 0x1008 (R/ ) Distributor Implementer Identification Register */ + uint32_t RESERVED1[29]; + __IOM uint32_t D_IGROUPR[16]; /*!< Offset: 0x1080 - 0x0BC (R/W) Interrupt Group Registers */ + uint32_t RESERVED2[16]; + __IOM uint32_t D_ISENABLER[16]; /*!< Offset: 0x1100 - 0x13C (R/W) Interrupt Set-Enable Registers */ + uint32_t RESERVED3[16]; + __IOM uint32_t D_ICENABLER[16]; /*!< Offset: 0x1180 - 0x1BC (R/W) Interrupt Clear-Enable Registers */ + uint32_t RESERVED4[16]; + __IOM uint32_t D_ISPENDR[16]; /*!< Offset: 0x1200 - 0x23C (R/W) Interrupt Set-Pending Registers */ + uint32_t RESERVED5[16]; + __IOM uint32_t D_ICPENDR[16]; /*!< Offset: 0x1280 - 0x2BC (R/W) Interrupt Clear-Pending Registers */ + uint32_t RESERVED6[16]; + __IOM uint32_t D_ISACTIVER[16]; /*!< Offset: 0x1300 - 0x33C (R/W) Interrupt Set-Active Registers */ + uint32_t RESERVED7[16]; + __IOM uint32_t D_ICACTIVER[16]; /*!< Offset: 0x1380 - 0x3BC (R/W) Interrupt Clear-Active Registers */ + uint32_t RESERVED8[16]; + __IOM uint8_t D_IPRIORITYR[512]; /*!< Offset: 0x1400 - 0x5FC (R/W) Interrupt Priority Registers */ + uint32_t RESERVED9[128]; + __IOM uint8_t D_ITARGETSR[512]; /*!< Offset: 0x1800 - 0x9FC (R/W) Interrupt Targets Registers */ + uint32_t RESERVED10[128]; + __IOM uint32_t D_ICFGR[32]; /*!< Offset: 0x1C00 - 0xC7C (R/W) Interrupt configuration registers */ + uint32_t RESERVED11[32]; + __IM uint32_t D_PPISR; /*!< Offset: 0x1D00 (R/ ) Private Peripheral Interrupt Status Register */ + __IM uint32_t D_SPISR[15]; /*!< Offset: 0x1D04 - 0xD3C (R/ ) Shared Peripheral Interrupt Status Registers */ + uint32_t RESERVED12[112]; + __OM uint32_t D_SGIR; /*!< Offset: 0x1F00 ( /W) Software Generated Interrupt Register */ + uint32_t RESERVED13[3]; + __IOM uint8_t D_CPENDSGIR[16]; /*!< Offset: 0x1F10 - 0xF1C (R/W) SGI Clear-Pending Registers */ + __IOM uint8_t D_SPENDSGIR[16]; /*!< Offset: 0x1F20 - 0xF2C (R/W) SGI Set-Pending Registers */ + uint32_t RESERVED14[40]; + __IM uint32_t D_PIDR4; /*!< Offset: 0x1FD0 (R/ ) Peripheral ID4 Register */ + __IM uint32_t D_PIDR5; /*!< Offset: 0x1FD4 (R/ ) Peripheral ID5 Register */ + __IM uint32_t D_PIDR6; /*!< Offset: 0x1FD8 (R/ ) Peripheral ID6 Register */ + __IM uint32_t D_PIDR7; /*!< Offset: 0x1FDC (R/ ) Peripheral ID7 Register */ + __IM uint32_t D_PIDR0; /*!< Offset: 0x1FE0 (R/ ) Peripheral ID0 Register */ + __IM uint32_t D_PIDR1; /*!< Offset: 0x1FE4 (R/ ) Peripheral ID1 Register */ + __IM uint32_t D_PIDR2; /*!< Offset: 0x1FE8 (R/ ) Peripheral ID2 Register */ + __IM uint32_t D_PIDR3; /*!< Offset: 0x1FEC (R/ ) Peripheral ID3 Register */ + __IM uint32_t D_CIDR0; /*!< Offset: 0x1FF0 (R/ ) Component ID0 Register */ + __IM uint32_t D_CIDR1; /*!< Offset: 0x1FF4 (R/ ) Component ID1 Register */ + __IM uint32_t D_CIDR2; /*!< Offset: 0x1FF8 (R/ ) Component ID2 Register */ + __IM uint32_t D_CIDR3; /*!< Offset: 0x1FFC (R/ ) Component ID3 Register */ + + __IOM uint32_t C_CTLR; /*!< Offset: 0x2000 (R/W) CPU Interface Control Register */ + __IOM uint32_t C_PMR; /*!< Offset: 0x2004 (R/W) Interrupt Priority Mask Register */ + __IOM uint32_t C_BPR; /*!< Offset: 0x2008 (R/W) Binary Point Register */ + __IM uint32_t C_IAR; /*!< Offset: 0x200C (R/ ) Interrupt Acknowledge Register */ + __OM uint32_t C_EOIR; /*!< Offset: 0x2010 ( /W) End Of Interrupt Register */ + __IM uint32_t C_RPR; /*!< Offset: 0x2014 (R/ ) Running Priority Register */ + __IM uint32_t C_HPPIR; /*!< Offset: 0x2018 (R/ ) Highest Priority Pending Interrupt Register */ + __IOM uint32_t C_ABPR; /*!< Offset: 0x201C (R/W) Aliased Binary Point Register */ + __IM uint32_t C_AIAR; /*!< Offset: 0x2020 (R/ ) Aliased Interrupt Acknowledge Register */ + __OM uint32_t C_AEOIR; /*!< Offset: 0x2024 ( /W) Aliased End Of Interrupt Register */ + __IM uint32_t C_AHPPIR; /*!< Offset: 0x2028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ + uint32_t RESERVED15[41]; + __IOM uint32_t C_APR0; /*!< Offset: 0x20D0 (R/W) Active Priority Register */ + uint32_t RESERVED16[3]; + __IOM uint32_t C_NSAPR0; /*!< Offset: 0x20E0 (R/W) Non-secure Active Priority Register */ + uint32_t RESERVED17[6]; + __IM uint32_t C_IIDR; /*!< Offset: 0x20FC (R/ ) CPU Interface Identification Register */ + uint32_t RESERVED18[960]; + __OM uint32_t C_DIR; /*!< Offset: 0x3000 ( /W) Deactivate Interrupt Register */ +} GIC_Type; + + +/* + * GIC初始化 + * 为了简单使用GIC的group0 + */ +FORCEDINLINE __STATIC_INLINE void GIC_Init(void) +{ + uint32_t i; + uint32_t irqRegs; + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + irqRegs = (gic->D_TYPER & 0x1FUL) + 1; + + /* On POR, all SPI is in group 0, level-sensitive and using 1-N model */ + + /* Disable all PPI, SGI and SPI */ + for (i = 0; i < irqRegs; i++) + gic->D_ICENABLER[i] = 0xFFFFFFFFUL; + + /* Make all interrupts have higher priority */ + gic->C_PMR = (0xFFUL << (8 - __GIC_PRIO_BITS)) & 0xFFUL; + + /* No subpriority, all priority level allows preemption */ + gic->C_BPR = 7 - __GIC_PRIO_BITS; + + /* Enable group0 distribution */ + gic->D_CTLR = 1UL; + + /* Enable group0 signaling */ + gic->C_CTLR = 1UL; +} + +/* + * 使能指定的中断 + */ +FORCEDINLINE __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + gic->D_ISENABLER[((uint32_t)(int32_t)IRQn) >> 5] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + +/* + * 关闭指定的中断 + */ + +FORCEDINLINE __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + gic->D_ICENABLER[((uint32_t)(int32_t)IRQn) >> 5] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + +/* + * 返回中断号 + */ +FORCEDINLINE __STATIC_INLINE uint32_t GIC_AcknowledgeIRQ(void) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + return gic->C_IAR & 0x1FFFUL; +} + +/* + * 向EOIR写入发送中断的中断号来释放中断 + */ +FORCEDINLINE __STATIC_INLINE void GIC_DeactivateIRQ(uint32_t value) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + gic->C_EOIR = value; +} + +/* + * 获取运行优先级 + */ +FORCEDINLINE __STATIC_INLINE uint32_t GIC_GetRunningPriority(void) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + return gic->C_RPR & 0xFFUL; +} + +/* + * 设置组优先级 + */ +FORCEDINLINE __STATIC_INLINE void GIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + gic->C_BPR = PriorityGroup & 0x7UL; +} + +/* + * 获取组优先级 + */ +FORCEDINLINE __STATIC_INLINE uint32_t GIC_GetPriorityGrouping(void) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + return gic->C_BPR & 0x7UL; +} + +/* + * 设置优先级 + */ +FORCEDINLINE __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + gic->D_IPRIORITYR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8UL - __GIC_PRIO_BITS)) & (uint32_t)0xFFUL); +} + +/* + * 获取优先级 + */ +FORCEDINLINE __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + return(((uint32_t)gic->D_IPRIORITYR[((uint32_t)(int32_t)IRQn)] >> (8UL - __GIC_PRIO_BITS))); +} + + +#endif diff --git a/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/imx6ul.h b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/imx6ul.h new file mode 100644 index 00000000..715ef1f7 --- /dev/null +++ b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/imx6ul.h @@ -0,0 +1,28 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _IMX6UL_H_ +#define _IMX6UL_H_ + +#include "MCIMX6Y2.h" +#include "core_ca7.h" + +#include "clock.h" +#include "systick.h" + +#endif /* _IMX6UL_H_ */ + diff --git a/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/systick.h b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/systick.h new file mode 100644 index 00000000..0a436bca --- /dev/null +++ b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include/systick.h @@ -0,0 +1,7 @@ +#ifndef _SYSTICK_H_ +#define _SYSTICK_H_ + +void systick_init(k_tick_t tick_per_second); + +#endif /* _SYSTICK_H_ */ + diff --git a/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/systick.c b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/systick.c new file mode 100644 index 00000000..f85684ea --- /dev/null +++ b/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/systick.c @@ -0,0 +1,37 @@ +#include "tos_k.h" +#include "imx6ul.h" + +static void epit1_init(unsigned int frac, unsigned int value) +{ + if (frac > 0XFFF) { + frac = 0XFFF; + } + + EPIT1->CR = 0; + + EPIT1->CR = (1 << 24 | frac << 4 | 1 << 3 | 1 << 2 | 1 << 1); + + EPIT1->LR = value; + EPIT1->CMPR = 0; + + GIC_EnableIRQ(EPIT1_IRQn); + + EPIT1->CR |= 1 << 0; +} + +void systick_handler(void *arg) +{ + if (EPIT1->SR & (1 << 0)) { + tos_tick_handler(); + } + + EPIT1->SR |= 1 << 0; +} + +void systick_init(k_tick_t tick_per_second) +{ + epit1_init(0, 66000000 / tick_per_second); + + tos_interrupt_handler_register(EPIT1_IRQn, (int_handler_t)systick_handler, NULL); +} + diff --git a/arch/arm/arm-v7a/cortex-a7/gcc/exceptions.S b/arch/arm/arm-v7a/cortex-a7/gcc/exceptions.S new file mode 100644 index 00000000..3c859151 --- /dev/null +++ b/arch/arm/arm-v7a/cortex-a7/gcc/exceptions.S @@ -0,0 +1,202 @@ +/* Fuchsia's code is nice here, so I learn from it(fine, almost copy). thanks */ + +.syntax unified +.text + +/* macros to align and unalign the stack on 8 byte boundary for ABI compliance */ +.macro stack_align, tempreg + /* make sure the stack is aligned */ + mov \tempreg, sp + tst sp, #4 + subeq sp, #4 + push { \tempreg } + + /* tempreg holds the original stack */ +.endm + +.macro stack_restore, tempreg + /* restore the potentially unaligned stack */ + pop { \tempreg } + mov sp, \tempreg +.endm + +/* save and disable the vfp unit */ +.macro vfp_save, temp1 + /* save old fpexc */ + vmrs \temp1, fpexc + + push { \temp1 } + + /* hard disable the vfp unit */ + bic \temp1, #(1<<30) + vmsr fpexc, \temp1 +.endm + +/* restore the vfp enable/disable state */ +.macro vfp_restore, temp1 + /* restore fpexc */ + pop { \temp1 } + + vmsr fpexc, \temp1 +.endm + +/* Save callee trashed registers. + * At exit r0 contains a pointer to the register frame. + */ +.macro save + /* save spsr and r14 onto the svc stack */ + srsdb #0x13! + + /* switch to svc mode, interrupts disabled */ + cpsid i, #0x13 + + /* save callee trashed regs and lr */ + push { r0-r3, r12, lr } + +#if 0 + #if (defined(__VFP_FP__) && !defined(__SOFTFP__)) + /* save and disable the vfp unit */ + vfp_save r0 + #endif +#endif + + /* make sure the stack is 8 byte aligned */ + stack_align r0 + + /* r0 now holds the pointer to the original iframe (before alignment) */ +.endm + +.macro save_offset, offset + sub lr, \offset + save +.endm + +.macro restore + /* undo the stack alignment we did before */ + stack_restore r0 + +#if 0 + #if (defined(__VFP_FP__) && !defined(__SOFTFP__)) + /* restore the old state of the vfp unit */ + vfp_restore r0 + #endif +#endif + + pop { r0-r3, r12, lr } + + /* return to whence we came from */ + rfeia sp! +.endm + +/* Save all registers. + * At exit r0 contains a pointer to the register frame. + */ +.macro saveall + /* save spsr and r14 onto the svc stack */ + srsdb #0x13! + + /* switch to svc mode, interrupts disabled */ + cpsid i,#0x13 + + /* save all regs */ + push { r0-r12, lr } + + #if 0 + #if (defined(__VFP_FP__) && !defined(__SOFTFP__)) + /* save and disable the vfp unit */ + vfp_save r0 + #endif + #endif + + /* make sure the stack is 8 byte aligned */ + stack_align r0 + + /* r0 now holds the pointer to the original iframe (before alignment) */ +.endm + +.macro saveall_offset, offset + sub lr, \offset + saveall +.endm + +.macro restoreall + /* undo the stack alignment we did before */ + stack_restore r0 + + #if 0 + #if (defined(__VFP_FP__) && !defined(__SOFTFP__)) + /* restore the old state of the vfp unit */ + vfp_restore r0 + #endif + #endif + + pop { r0-r12, r14 } + + /* return to whence we came from */ + rfeia sp! +.endm + + .extern tos_knl_irq_enter + .extern tos_knl_irq_leave + +.global arm_undefined +arm_undefined: + save + /* r0 now holds pointer to iframe */ + + bl arm_undefined_handler + + restore + + +.global arm_syscall +arm_syscall: + b . + + +.global arm_prefetch_abort +arm_prefetch_abort: + saveall_offset #4 + /* r0 now holds pointer to iframe */ + + bl arm_prefetch_abort_handler + + restoreall + + +.global arm_data_abort +arm_data_abort: + saveall_offset #8 + /* r0 now holds pointer to iframe */ + + bl arm_data_abort_handler + + restoreall + + +.global arm_reserved +arm_reserved: + b . + + +.global arm_irq +arm_irq: + saveall_offset #4 + + /* r0 now holds pointer to iframe */ + bl tos_knl_irq_enter + + /* call into higher level code */ + bl interrupt_irq + + bl tos_knl_irq_leave + + restoreall + + +.global arm_fiq +arm_fiq: + b . + +.end + diff --git a/arch/arm/arm-v7a/cortex-a7/gcc/port.h b/arch/arm/arm-v7a/cortex-a7/gcc/port.h new file mode 100644 index 00000000..10a6c89b --- /dev/null +++ b/arch/arm/arm-v7a/cortex-a7/gcc/port.h @@ -0,0 +1,73 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _PORT_H_ +#define _PORT_H_ + +__PORT__ void port_int_disable(void); + +__PORT__ void port_int_enable(void); + +__PORT__ cpu_cpsr_t port_cpsr_save(void); + +__PORT__ void port_cpsr_restore(cpu_cpsr_t cpsr); + +__PORT__ void port_cpu_reset(void); + +__PORT__ void port_sched_start(void) __NO_RETURN__; + +__PORT__ void port_context_switch(void); + +__PORT__ void port_irq_context_switch(void); + +__PORT__ void port_systick_config(uint32_t cycle_per_tick); + +__PORT__ void port_systick_priority_set(uint32_t prio); + +#if TOS_CFG_TICKLESS_EN > 0u + +__PORT__ void port_systick_resume(void); + +__PORT__ void port_systick_suspend(void); + +__PORT__ void port_systick_reload(uint32_t cycle_per_tick); + +__PORT__ void port_systick_pending_reset(void); + +__PORT__ k_time_t port_systick_max_delay_millisecond(void); + +#endif + +#if TOS_CFG_PWR_MGR_EN > 0u + +__PORT__ void port_sleep_mode_enter(void); + +__PORT__ void port_stop_mode_enter(void); + +__PORT__ void port_standby_mode_enter(void); + +#endif + + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u +__PORT__ void HardFault_Handler(void); + +__PORT__ void port_fault_diagnosis(void); +#endif + +#endif /* _PORT_H_ */ + diff --git a/arch/arm/arm-v7a/cortex-a7/gcc/port_c.c b/arch/arm/arm-v7a/cortex-a7/gcc/port_c.c new file mode 100644 index 00000000..58653f79 --- /dev/null +++ b/arch/arm/arm-v7a/cortex-a7/gcc/port_c.c @@ -0,0 +1,134 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#include "tos_k.h" + +__PORT__ void port_cpu_reset(void) +{ + +} + +__PORT__ void port_systick_config(uint32_t cycle_per_tick) +{ + +} + +__PORT__ void port_systick_priority_set(uint32_t prio) +{ + +} + +#if TOS_CFG_TICKLESS_EN > 0u + +__PORT__ k_time_t port_systick_max_delay_millisecond(void) +{ + +} + +__PORT__ void port_systick_resume(void) +{ + +} + +__PORT__ void port_systick_suspend(void) +{ + +} + +__PORT__ void port_systick_reload(uint32_t cycle_per_tick) +{ + +} + +__PORT__ void port_systick_pending_reset(void) +{ +} + +#endif + +#if TOS_CFG_PWR_MGR_EN > 0u + +__PORT__ void port_sleep_mode_enter(void) +{ +#if 0 +#if 1 + HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI); +#else + HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); +#endif +#endif +} + +__PORT__ void port_stop_mode_enter(void) +{ +#if 0 + HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); +#endif +} + +__PORT__ void port_standby_mode_enter(void) +{ +#if 0 + HAL_PWR_EnterSTANDBYMode(); +#endif +} + +#endif + +#if TOS_CFG_FAULT_BACKTRACE_EN > 0u +__PORT__ void port_fault_diagnosis(void) +{ + // k_fault_log_writer("fault diagnosis does not supported in CORTEX M0\n"); +} + +#if 0 +/*------------------ RealView Compiler -----------------*/ +/* V5 */ +#if defined(__CC_ARM) + +__PORT__ __ASM__ void HardFault_Handler(void) +{ + IMPORT fault_backtrace + + MOV r0, lr + TST lr, #0x04 + ITE EQ + MRSEQ r1, MSP + MRSNE r1, PSP + BL fault_backtrace +} + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + +__PORT__ void __NAKED__ HardFault_Handler(void) +{ + __ASM__ __VOLATILE__ ( + "MOV r0, lr\n\t" + "TST lr, #0x04\n\t" + "ITE EQ\n\t" + "MRSEQ r1, MSP\n\t" + "MRSNE r1, PSP\n\t" + "BL fault_backtrace\n\t" + ); +} + +#endif /* ARMCC VERSION */ +#endif + +#endif /* TOS_CFG_FAULT_BACKTRACE_EN */ + diff --git a/arch/arm/arm-v7a/cortex-a7/gcc/port_config.h b/arch/arm/arm-v7a/cortex-a7/gcc/port_config.h new file mode 100644 index 00000000..fd077913 --- /dev/null +++ b/arch/arm/arm-v7a/cortex-a7/gcc/port_config.h @@ -0,0 +1,35 @@ +/*---------------------------------------------------------------------------- + * Tencent is pleased to support the open source community by making TencentOS + * available. + * + * Copyright (C) 2019 THL A29 Limited, a Tencent company. All rights reserved. + * If you have downloaded a copy of the TencentOS binary from Tencent, please + * note that the TencentOS binary is licensed under the BSD 3-Clause License. + * + * If you have downloaded a copy of the TencentOS source code from Tencent, + * please note that TencentOS source code is licensed under the BSD 3-Clause + * License, except for the third-party components listed below which are + * subject to different license terms. Your integration of TencentOS into your + * own projects may require compliance with the BSD 3-Clause License, as well + * as the other licenses applicable to the third-party components included + * within TencentOS. + *---------------------------------------------------------------------------*/ + +#ifndef _PORT_CONFIG_H_ +#define _PORT_CONFIG_H_ + +#define TOS_CFG_CPU_ADDR_SIZE CPU_WORD_SIZE_32 +#define TOS_CFG_CPU_DATA_SIZE CPU_WORD_SIZE_32 +#define TOS_CFG_CPU_STK_GROWTH CPU_STK_GROWTH_DESCENDING +// #define TOS_CFG_CPU_HRTIMER_SIZE CPU_WORD_SIZE_32 +#define TOS_CFG_CPU_HRTIMER_EN 0u +#define TOS_CFG_CPU_LEAD_ZEROS_ASM_PRESENT 0u + +#if (defined(__VFP_FP__) && !defined(__SOFTFP__)) +#define TOS_CFG_CPU_ARM_FPU_EN 1u +#else +#define TOS_CFG_CPU_ARM_FPU_EN 0u +#endif + +#endif /* _PORT_CONFIG_H_ */ + diff --git a/arch/arm/arm-v7a/cortex-a7/gcc/port_s.S b/arch/arm/arm-v7a/cortex-a7/gcc/port_s.S new file mode 100644 index 00000000..4ce5132c --- /dev/null +++ b/arch/arm/arm-v7a/cortex-a7/gcc/port_s.S @@ -0,0 +1,80 @@ + .global port_int_disable + .global port_int_enable + .global port_cpsr_save + .global port_cpsr_restore + .global port_sched_start + .global port_context_switch + .global port_irq_context_switch + + .extern k_curr_task + .extern k_next_task + + .syntax unified + .align 2 + .text + +.type port_int_disable, %function +port_int_disable: + CPSID I + +.type port_int_enable, %function +port_int_enable: + CPSIE I + +.type port_cpsr_save, %function +port_cpsr_save: + MRS R0, CPSR + CPSID I + BX LR + +.type port_cpsr_restore, %function +port_cpsr_restore: + MSR CPSR, R0 + BX LR + +.type port_sched_start, %function +port_sched_start: + B .L__context_restore + +.type port_context_switch, %function +port_context_switch: +.L__context_save: + STR R0, [SP, #-0xC] /* backup R0 */ + + MRS R0, CPSR + TST LR, #0x01 + ORRNE R0, R0, 0x20 /* set thumb bit*/ + + STMFD SP!, { R0 } /* save CPSR */ + STMFD SP!, { LR } /* save PC */ + + LDR R0, [SP, #-0x4] /* restore R0 */ + STMFD SP!, { R0 - R12, LR } + + /* k_curr_task->sp = SP */ + LDR R0, =k_curr_task + LDR R0, [R0] + STR SP, [R0] + +.L__context_restore: + /* k_curr_task = k_next_task */ + LDR R0, =k_next_task + LDR R0, [R0] + LDR R1, =k_curr_task + STR R0, [R1] + + /* SP = k_next_task->sp */ + LDR SP, [R0] + + LDMFD SP!, { R0 - R12, LR } + RFEIA SP! + +.type port_irq_context_switch, %function +port_irq_context_switch: + /* we already store the k_curr_task's context onto its stack by arm_irq(see saveall_offset) */ + + /* ATTENTION: our kernel always runs in SVC mode even in user task, + if one day we make the user task run in USR mode(although I cannot see any meaning to do this in RTOS), + we must deal with more logic */ + B .L__context_restore /* magnificent */ + diff --git a/arch/arm/arm-v7a/cortex-a7/gcc/start.S b/arch/arm/arm-v7a/cortex-a7/gcc/start.S new file mode 100644 index 00000000..43539eb8 --- /dev/null +++ b/arch/arm/arm-v7a/cortex-a7/gcc/start.S @@ -0,0 +1,150 @@ +.equ MODE_USR, 0x10 +.equ MODE_FIQ, 0x11 +.equ MODE_IRQ, 0x12 +.equ MODE_SVC, 0x13 +.equ MODE_ABT, 0x17 +.equ MODE_UND, 0x1B +.equ MODE_SYS, 0x1F + +.equ BIT_I, 0x80 @ when I bit is set, IRQ is disabled +.equ BIT_F, 0x40 @ when F bit is set, FIQ is disabled + +.equ STACK_SIZE_USR, 0x00000100 +.equ STACK_SIZE_FIQ, 0x00000100 +.equ STACK_SIZE_IRQ, 0x00001000 +.equ STACK_SIZE_ABT, 0x00000100 +.equ STACK_SIZE_UND, 0x00000100 +.equ STACK_SIZE_SYS, 0x00000800 +.equ STACK_SIZE_SVC, 0x00001000 + +.syntax unified + +.section ".text.vector", "ax" +.code 32 +.align 0 +.global _start +_start: +_vector: + ldr pc, vector_reset + ldr pc, vector_undefined + ldr pc, vector_swi + ldr pc, vector_prefetch_abort + ldr pc, vector_data_abort + ldr pc, vector_reserved + ldr pc, vector_irq + ldr pc, vector_fiq + +.align 3 + +vector_reset: + .word arm_reset + +vector_undefined: + .word arm_undefined + +vector_swi: + .word arm_syscall + +vector_prefetch_abort: + .word arm_prefetch_abort + +vector_data_abort: + .word arm_data_abort + +vector_reserved: + .word arm_reserved + +vector_irq: + .word arm_irq + +vector_fiq: + .word arm_fiq + +.section ".text", "ax" +.global arm_reset +arm_reset: +.L__cache_disable: + mrc p15, 0, r12, c1, c0, 0 /* read SCTLR */ + bic r12, #(1 << 12) /* i-cache disable */ + bic r12, #(1 << 2 | 1 << 0) /* d-cache, mmu disable */ + mcr p15, 0, r12, c1, c0, 0 /* write SCTLR */ + + /* set up the stack */ +.L__stack_setup: + cpsid i, #MODE_IRQ /* irq */ + ldr sp, =__irq_stack_limit + + cpsid i, #MODE_FIQ /* fiq */ + ldr sp, =__fiq_stack_limit + + cpsid i, #MODE_ABT /* abort */ + ldr sp, =__abt_stack_limit + + cpsid i, #MODE_UND /* undefined */ + ldr sp, =__und_stack_limit + + cpsid i, #MODE_SYS /* system */ + ldr sp, =__sys_stack_limit + + cpsid i, #MODE_SVC /* supervisor */ + ldr sp, =__svc_stack_limit + + /* init vector table */ +.L__vector_setup: + dsb + isb + ldr r0, =_vector + mcr p15, 0, r0, c12, c0, #0 /* write VBAR */ + dsb + isb + + /* clear bss */ +.L__bss_clear: + ldr r0, =__bss_start__ + ldr r1, =__bss_end__ + mov r2, #0 + +.L__bss_loop: + cmp r0, r1 + strlt r2, [r0], #4 + blt .L__bss_loop + + bl main + b . + +.section ".bss.prebss.exc_stk", "wa" +.bss +.align 2 + +__usr_stack_base: +.space STACK_SIZE_USR +__usr_stack_limit: + +__fiq_stack_base: +.space STACK_SIZE_FIQ +__fiq_stack_limit: + +__irq_stack_base: +.space STACK_SIZE_IRQ +__irq_stack_limit: + +__abt_stack_base: +.space STACK_SIZE_ABT +__abt_stack_limit: + +__und_stack_base: +.space STACK_SIZE_UND +__und_stack_limit: + +__sys_stack_base: +.space STACK_SIZE_SYS +__sys_stack_limit: + +__svc_stack_base: +.space STACK_SIZE_SVC +__svc_stack_limit: + +.size __usr_stack_base, . - __usr_stack_base + +.end + diff --git a/arch/arm/arm-v7a/lds/link.ld.S b/arch/arm/arm-v7a/lds/link.ld.S new file mode 100644 index 00000000..1b059655 --- /dev/null +++ b/arch/arm/arm-v7a/lds/link.ld.S @@ -0,0 +1,90 @@ +#include "chip/chip.h" + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) + +ENTRY(_start) + +SECTIONS +{ + . = KERNEL_BASE; + + _start = .; + + .text : AT(KERNEL_BASE) { + __text_start = .; + + KEEP(*(.text.vector)) + *(.text) + *(.text.*) + + KEEP(*(.init)) + KEEP(*(.fini)) + } + + .ARM.extab : ALIGN(4) { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : ALIGN(4) { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } + __exidx_end = .; + + .dummy_post_text : { + __text_end = .; + } + + .rodata : ALIGN(4) { + __rodata_start = .; + *(.rodata) + *(.rodata.*) + } + + .dummy_post_rodata : { + __rodata_end = .; + } + + .data : ALIGN(4) { + __data_start = .; + *(.data) + *(.data.*) + } + + .ctors : ALIGN(4) { + __ctor_list = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.ctors .init_array*)) + __ctor_end = .; + } + + .dtors : ALIGN(4) { + __dtor_list = .; + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.dtors .fini_array*)) + __dtor_end = .; + } + + .dummy_post_rodata : { + __data_end = .; + } + + .bss : ALIGN(4) { + KEEP(*(.bss.prebss.*)) + . = ALIGN(4); + __bss_start__ = .; + *(.bss .bss.*) + *(COMMON) + + . = ALIGN(4); + __bss_end__ = .; + } + + _end = .; + + /* Strip unnecessary stuff */ + /DISCARD/ : { *(.comment .note) } +} + diff --git a/arch/arm/arm-v7m/common/tos_cpu.c b/arch/arm/arm-v7m/common/tos_cpu.c index 5b94d7b8..2dc1ef25 100644 --- a/arch/arm/arm-v7m/common/tos_cpu.c +++ b/arch/arm/arm-v7m/common/tos_cpu.c @@ -15,7 +15,7 @@ * within TencentOS. *---------------------------------------------------------------------------*/ -#include +#include "tos_k.h" __API__ uint32_t tos_cpu_clz(uint32_t val) { diff --git a/arch/arm/arm-v7m/cortex-m0+/gcc/port_s.S b/arch/arm/arm-v7m/cortex-m0+/gcc/port_s.S index 28e5520b..45cd6571 100644 --- a/arch/arm/arm-v7m/cortex-m0+/gcc/port_s.S +++ b/arch/arm/arm-v7m/cortex-m0+/gcc/port_s.S @@ -58,7 +58,7 @@ port_sched_start: LDR R1, =NVIC_PENDSV_PRI - + STR R1, [R0] MOVS R0, #0 @@ -102,7 +102,7 @@ PendSV_Handler: SUBS R0, R0, #0x20 STMIA R0!, {R4 - R7} - MOV R4, R8 + MOV R4, R8 MOV R5, R9 MOV R6, R10 MOV R7, R11 @@ -123,11 +123,11 @@ PendSVHandler_nosave: LDMIA R0!, {R4 - R7} LDMIA R0!, {R2 - R3} - MOV R8, R2 + MOV R8, R2 MOV R9, R3 - LDMIA R0!, {R2 - R3} - MOV R10, R2 - MOV R11, R3 + LDMIA R0!, {R2 - R3} + MOV R10, R2 + MOV R11, R3 MSR PSP, R0 MOV R0, R14 diff --git a/arch/arm/arm-v7m/cortex-m4/armcc/port_s.S b/arch/arm/arm-v7m/cortex-m4/armcc/port_s.S index 952ce2fa..3af74b32 100644 --- a/arch/arm/arm-v7m/cortex-m4/armcc/port_s.S +++ b/arch/arm/arm-v7m/cortex-m4/armcc/port_s.S @@ -1,4 +1,4 @@ - EXPORT port_int_disable + EXPORT port_int_disable EXPORT port_int_enable EXPORT port_cpsr_save @@ -28,7 +28,7 @@ NVIC_PENDSVSET EQU 0x10000000 PRESERVE8 - GLOBAL port_int_disable + GLOBAL port_int_disable port_int_disable CPSID I BX LR diff --git a/arch/arm/arm-v7m/cortex-m7/armcc/port_s.S b/arch/arm/arm-v7m/cortex-m7/armcc/port_s.S index 7a054c77..2f976cc0 100644 --- a/arch/arm/arm-v7m/cortex-m7/armcc/port_s.S +++ b/arch/arm/arm-v7m/cortex-m7/armcc/port_s.S @@ -59,7 +59,7 @@ port_clz BX LR - GLOBAL port_sched_start + GLOBAL port_sched_start port_sched_start CPSID I diff --git a/arch/arm/arm-v7m/cortex-m7/gcc/port_s.S b/arch/arm/arm-v7m/cortex-m7/gcc/port_s.S index fded2b1f..8aef4770 100644 --- a/arch/arm/arm-v7m/cortex-m7/gcc/port_s.S +++ b/arch/arm/arm-v7m/cortex-m7/gcc/port_s.S @@ -112,7 +112,7 @@ port_sched_start: @ restore r0, r3 LDMFD SP!, {R0 - R3} @ load R12 and LR - LDMFD SP!, {R12, LR} + LDMFD SP!, {R12, LR} @ load PC and discard xPSR LDMFD SP!, {R1, R2} @@ -191,7 +191,7 @@ _context_restore: @ Load PSP with new process SP MSR PSP, R0 - + CPSIE I @ R0-R3, R12, LR, PC, xPSR restored automatically here diff --git a/arch/arm/arm-v8m/common/tos_cpu.c b/arch/arm/arm-v8m/common/tos_cpu.c index 5b94d7b8..2dc1ef25 100644 --- a/arch/arm/arm-v8m/common/tos_cpu.c +++ b/arch/arm/arm-v8m/common/tos_cpu.c @@ -15,7 +15,7 @@ * within TencentOS. *---------------------------------------------------------------------------*/ -#include +#include "tos_k.h" __API__ uint32_t tos_cpu_clz(uint32_t val) { diff --git a/arch/arm/arm-v8m/cortex-m23/gcc/port_s.S b/arch/arm/arm-v8m/cortex-m23/gcc/port_s.S index 28e5520b..45cd6571 100644 --- a/arch/arm/arm-v8m/cortex-m23/gcc/port_s.S +++ b/arch/arm/arm-v8m/cortex-m23/gcc/port_s.S @@ -58,7 +58,7 @@ port_sched_start: LDR R1, =NVIC_PENDSV_PRI - + STR R1, [R0] MOVS R0, #0 @@ -102,7 +102,7 @@ PendSV_Handler: SUBS R0, R0, #0x20 STMIA R0!, {R4 - R7} - MOV R4, R8 + MOV R4, R8 MOV R5, R9 MOV R6, R10 MOV R7, R11 @@ -123,11 +123,11 @@ PendSVHandler_nosave: LDMIA R0!, {R4 - R7} LDMIA R0!, {R2 - R3} - MOV R8, R2 + MOV R8, R2 MOV R9, R3 - LDMIA R0!, {R2 - R3} - MOV R10, R2 - MOV R11, R3 + LDMIA R0!, {R2 - R3} + MOV R10, R2 + MOV R11, R3 MSR PSP, R0 MOV R0, R14 diff --git a/arch/linux/common/tos_cpu.c b/arch/linux/common/tos_cpu.c index 08662153..246ec2bf 100644 --- a/arch/linux/common/tos_cpu.c +++ b/arch/linux/common/tos_cpu.c @@ -15,7 +15,7 @@ * within TencentOS. *---------------------------------------------------------------------------*/ -#include +#include "tos_k.h" __API__ uint32_t tos_cpu_clz(uint32_t val) { diff --git a/arch/risc-v/rv32i/gcc/port_s.S b/arch/risc-v/rv32i/gcc/port_s.S index f085f874..c4adb91d 100644 --- a/arch/risc-v/rv32i/gcc/port_s.S +++ b/arch/risc-v/rv32i/gcc/port_s.S @@ -361,3 +361,4 @@ irq_task_switch: sw s11, __reg_s11__OFFSET(sp) j switch_task + diff --git a/board/ALPHA_I.MX_emmc_256ddr/Makefile b/board/ALPHA_I.MX_emmc_256ddr/Makefile new file mode 100644 index 00000000..ff8b3b7e --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/Makefile @@ -0,0 +1,126 @@ +TOP_DIR := ../.. + +CROSS_COMPILE ?= arm-linux-gnueabihf- +TARGET ?= TencentOS_tiny + +CC := $(CROSS_COMPILE)gcc +LD := $(CROSS_COMPILE)ld +OBJCOPY := $(CROSS_COMPILE)objcopy +OBJDUMP := $(CROSS_COMPILE)objdump +GCC_VERSION := 6.5.0 # 4.9.4 + +LD_SCRIPT_S := link.ld.S +LD_SCRIPT_DIR := $(TOP_DIR)/arch/arm/arm-v7a/lds +LD_SCRIPT := link.ld + +GCC_DIR := D:\Green\gcc-arm-linux-gnueabihf +OUT_ROOT := out +OBJ_DIR := obj +LIB_DIR := lib +TARGET_DIR := target +OUT_DIR := $(OUT_ROOT)/$(OBJ_DIR) $(OUT_ROOT)/$(LIB_DIR) $(OUT_ROOT)/$(TARGET_DIR) + +NOECHO := @ + +LIBPATH := -lgcc -L$(GCC_DIR)/lib/gcc/arm-linux-gnueabihf/$(GCC_VERSION) + +INCDIRS := \ + $(TOP_DIR)/kernel/core/include \ + $(TOP_DIR)/kernel/pm/include \ + $(TOP_DIR)/arch/arm/arm-v7a/common/include \ + $(TOP_DIR)/arch/arm/arm-v7a/cortex-a7/gcc \ + $(TOP_DIR)/arch/arm/arm-v7a/cortex-a7/chip/imx6ul/include \ + imx6ul \ + TOS_CONFIG \ + stdio/include \ + bsp/clk \ + bsp/led \ + bsp/delay \ + bsp/beep \ + bsp/gpio \ + bsp/key \ + bsp/exit \ + bsp/int \ + bsp/epittimer \ + bsp/keyfilter \ + bsp/uart \ + bsp/lcd \ + bsp/rtc \ + bsp/i2c \ + bsp/ap3216c \ + bsp/spi \ + bsp/icm20608 \ + bsp/touchscreen \ + bsp/backlight + +SRCDIRS := \ + src \ + $(TOP_DIR)/kernel/core \ + $(TOP_DIR)/arch/arm/arm-v7a/cortex-a7/gcc \ + $(TOP_DIR)/arch/arm/arm-v7a/common \ + $(TOP_DIR)/arch/arm/arm-v7a/cortex-a7/chip/imx6ul \ + stdio/lib \ + bsp/clk \ + bsp/led \ + bsp/delay \ + bsp/beep \ + bsp/gpio \ + bsp/key \ + bsp/exit \ + bsp/int \ + bsp/epittimer \ + bsp/keyfilter \ + bsp/uart \ + bsp/lcd \ + bsp/rtc \ + bsp/i2c \ + bsp/ap3216c \ + bsp/spi \ + bsp/icm20608 \ + bsp/touchscreen \ + bsp/backlight + +INCLUDE := $(patsubst %, -I %, $(INCDIRS)) + +SFILES := $(foreach dir, $(SRCDIRS), $(wildcard $(dir)/*.S)) +CFILES := $(foreach dir, $(SRCDIRS), $(wildcard $(dir)/*.c)) + +SFILENDIR := $(notdir $(SFILES)) +CFILENDIR := $(notdir $(CFILES)) + +SOBJS := $(patsubst %, $(OUT_ROOT)/$(OBJ_DIR)/%, $(SFILENDIR:.S=.o)) +COBJS := $(patsubst %, $(OUT_ROOT)/$(OBJ_DIR)/%, $(CFILENDIR:.c=.o)) +OBJS := $(SOBJS) $(COBJS) + +VPATH := $(SRCDIRS) + +.PHONY: clean $(OUT_DIR) + +$(TARGET).bin : $(OUT_DIR) $(OBJS) $(LD_SCRIPT) + @echo "LD $(TARGET).elf" + $(NOECHO)$(LD) -T$(LD_SCRIPT) -o $(OUT_ROOT)/$(TARGET_DIR)/$(TARGET).elf $(OBJS) $(LIBPATH) + @echo "OBJCOPY $(TARGET).bin" + $(NOECHO)$(OBJCOPY) -O binary -S $(OUT_ROOT)/$(TARGET_DIR)/$(TARGET).elf $(OUT_ROOT)/$(TARGET_DIR)/$@ + @echo "OBJDUMP $(TARGET).asm" + $(NOECHO)$(OBJDUMP) -D -m arm $(OUT_ROOT)/$(TARGET_DIR)/$(TARGET).elf > $(OUT_ROOT)/$(TARGET_DIR)/$(TARGET).asm + +$(LD_SCRIPT): $(LD_SCRIPT_DIR)/$(LD_SCRIPT_S) + @echo "generate link script" + $(NOECHO)$(CC) $(INCLUDE) -E -P -o $@ $< + +$(OUT_DIR) : + @mkdir -p $@ + +# $(NOECHO)$(CC) -march=armv7-a -nostdlib -fno-builtin -Wall -c -O2 $(INCLUDE) -o $@ $< +$(SOBJS) : $(OUT_ROOT)/$(OBJ_DIR)/%.o : %.S + @echo "CC $(notdir $<)" + $(NOECHO)$(CC) -Wall -nostdlib -fno-builtin -c -O2 $(INCLUDE) -o $@ $< + +# $(NOECHO)$(CC) -march=armv7-a -mfpu=neon-vfpv4 -mfloat-abi=hard -Wa,-mimplicit-it=thumb -nostdlib -fno-builtin -Wall -c -O2 $(INCLUDE) -o $@ $< +$(COBJS) : $(OUT_ROOT)/$(OBJ_DIR)/%.o : %.c + @echo "CC $(notdir $<)" + $(NOECHO)$(CC) -Wall -Wa,-mimplicit-it=thumb -nostdlib -fno-builtin -c -O2 $(INCLUDE) -o $@ $< + +clean: + @rm -rf $(OUT_ROOT) $(LD_SCRIPT) + diff --git a/board/ALPHA_I.MX_emmc_256ddr/README.md b/board/ALPHA_I.MX_emmc_256ddr/README.md new file mode 100644 index 00000000..7267df9e --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/README.md @@ -0,0 +1,18 @@ +# TencentOS tiny Cortex V7-A支持(基于正点原子阿尔法alpha开发板) + +## 如何运行 + +1. 安装arm交叉编译器（本构建采用6.5.0版本） +2. 在TencentOS-tiny\board\ALPHA_I.MX_emmc_256ddr目录下，根据自己的arm交叉编译器版本及安装目录，对应修改Makefile中的如下变量： + - GCC_VERSION + - GCC_DIR +3. 在TencentOS-tiny\board\ALPHA_I.MX_emmc_256ddr目录下执行make命令 +4. 利用正点原子官方的imxdownload工具，将out/target/TencenOS_tiny.bin烧写到SD卡中 +5. 将SD卡插入阿尔法开发板，接上串口，开发板复位上电，可从串口中看到两个任务以一定的时序交叉运行（业务入口文件为TencentOS-tiny\board\ALPHA_I.MX_emmc_256ddr\src\main.c）。 + +## 注意 + +1. 正点原子阿尔法开发板的相关板级驱动，由正点原子官方示例提供，并已提前征得正点原子官方同意将相关源码作为示例代码集成。 + +2. 正点原子官方烧写工具目前只支持linux平台。 +3. 后续TencentOS tiny会集成自己的镜像烧写工具（原子官方的烧写工具可定制性稍有欠缺） \ No newline at end of file diff --git a/board/ALPHA_I.MX_emmc_256ddr/TOS_CONFIG/tos_config.h b/board/ALPHA_I.MX_emmc_256ddr/TOS_CONFIG/tos_config.h new file mode 100644 index 00000000..4e769e66 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/TOS_CONFIG/tos_config.h @@ -0,0 +1,53 @@ +#ifndef _TOS_CONFIG_H_ +#define _TOS_CONFIG_H_ + +#define TOS_CFG_TASK_PRIO_MAX 10u + +#define TOS_CFG_ROUND_ROBIN_EN 0u + +#define TOS_CFG_OBJECT_VERIFY_EN 1u + +#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 0u + +#define TOS_CFG_EVENT_EN 1u + +#define TOS_CFG_MMBLK_EN 1u + +#define TOS_CFG_MMHEAP_EN 1u + +#define TOS_CFG_MMHEAP_DEFAULT_POOL_EN 1u + +#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x8000 + +#define TOS_CFG_MUTEX_EN 1u + +#define TOS_CFG_MESSAGE_QUEUE_EN 1u + +#define TOS_CFG_MAIL_QUEUE_EN 1u + +#define TOS_CFG_PRIORITY_MESSAGE_QUEUE_EN 1u + +#define TOS_CFG_PRIORITY_MAIL_QUEUE_EN 1u + +#define TOS_CFG_TIMER_EN 0u + +#define TOS_CFG_PWR_MGR_EN 0u + +#define TOS_CFG_TICKLESS_EN 0u + +#define TOS_CFG_SEM_EN 1u + +#define TOS_CFG_TASK_STACK_DRAUGHT_DEPTH_DETACT_EN 1u + +#define TOS_CFG_FAULT_BACKTRACE_EN 0u + +#define TOS_CFG_IDLE_TASK_STK_SIZE 512u + +#define TOS_CFG_CPU_TICK_PER_SECOND 1000u + +#define TOS_CFG_CPU_CLOCK 528000000 + +#define TOS_CFG_TIMER_AS_PROC 1u + +#endif + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/ap3216c/bsp_ap3216c.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/ap3216c/bsp_ap3216c.c new file mode 100644 index 00000000..27b77165 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/ap3216c/bsp_ap3216c.c @@ -0,0 +1,139 @@ +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_ap3216c.c +作者 : 左忠凯 +版本 : V1.0 +描述 : AP3216C驱动文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/3/26 左忠凯创建 +***************************************************************/ +#include "bsp_ap3216c.h" +#include "bsp_i2c.h" +#include "bsp_delay.h" +#include "cc.h" +#include "printf.h" + +/* + * @description : 初始化AP3216C + * @param : 无 + * @return : 0 成功，其他值 错误代码 + */ +unsigned char ap3216c_init(void) +{ + unsigned char data = 0; + + /* 1、IO初始化，配置I2C IO属性 + * I2C1_SCL -> UART4_TXD + * I2C1_SDA -> UART4_RXD + */ + IOMUXC_SetPinMux(IOMUXC_UART4_TX_DATA_I2C1_SCL, 1); + IOMUXC_SetPinMux(IOMUXC_UART4_RX_DATA_I2C1_SDA, 1); + + /* + *bit 16:0 HYS关闭 + *bit [15:14]: 1 默认47K上拉 + *bit [13]: 1 pull功能 + *bit [12]: 1 pull/keeper使能 + *bit [11]: 0 关闭开路输出 + *bit [7:6]: 10 速度100Mhz + *bit [5:3]: 110 驱动能力为R0/6 + *bit [0]: 1 高转换率 + */ + IOMUXC_SetPinConfig(IOMUXC_UART4_TX_DATA_I2C1_SCL, 0x70B0); + IOMUXC_SetPinConfig(IOMUXC_UART4_RX_DATA_I2C1_SDA, 0X70B0); + + i2c_init(I2C1); /* 初始化I2C1 */ + + /* 2、初始化AP3216C */ + ap3216c_writeonebyte(AP3216C_ADDR, AP3216C_SYSTEMCONG, 0X04); /* 复位AP3216C */ + delayms(50); /* AP33216C复位至少10ms */ + ap3216c_writeonebyte(AP3216C_ADDR, AP3216C_SYSTEMCONG, 0X03); /* 开启ALS、PS+IR */ + data = ap3216c_readonebyte(AP3216C_ADDR, AP3216C_SYSTEMCONG); /* 读取刚刚写进去的0X03 */ + if(data == 0X03) + return 0; /* AP3216C正常 */ + else + return 1; /* AP3216C失败 */ +} + +/* + * @description : 向AP3216C写入数据 + * @param - addr: 设备地址 + * @param - reg : 要写入的寄存器 + * @param - data: 要写入的数据 + * @return : 操作结果 + */ +unsigned char ap3216c_writeonebyte(unsigned char addr,unsigned char reg, unsigned char data) +{ + unsigned char status=0; + unsigned char writedata=data; + struct i2c_transfer masterXfer; + + /* 配置I2C xfer结构体 */ + masterXfer.slaveAddress = addr; /* 设备地址 */ + masterXfer.direction = kI2C_Write; /* 写入数据 */ + masterXfer.subaddress = reg; /* 要写入的寄存器地址 */ + masterXfer.subaddressSize = 1; /* 地址长度一个字节 */ + masterXfer.data = &writedata; /* 要写入的数据 */ + masterXfer.dataSize = 1; /* 写入数据长度1个字节 */ + + if(i2c_master_transfer(I2C1, &masterXfer)) + status=1; + + return status; +} + +/* + * @description : 从AP3216C读取一个字节的数据 + * @param - addr: 设备地址 + * @param - reg : 要读取的寄存器 + * @return : 读取到的数据。 + */ +unsigned char ap3216c_readonebyte(unsigned char addr,unsigned char reg) +{ + unsigned char val=0; + + struct i2c_transfer masterXfer; + masterXfer.slaveAddress = addr; /* 设备地址 */ + masterXfer.direction = kI2C_Read; /* 读取数据 */ + masterXfer.subaddress = reg; /* 要读取的寄存器地址 */ + masterXfer.subaddressSize = 1; /* 地址长度一个字节 */ + masterXfer.data = &val; /* 接收数据缓冲区 */ + masterXfer.dataSize = 1; /* 读取数据长度1个字节 */ + i2c_master_transfer(I2C1, &masterXfer); + + return val; +} + +/* + * @description : 读取AP3216C的数据，读取原始数据，包括ALS,PS和IR, 注意！ + * : 如果同时打开ALS,IR+PS的话两次数据读取的时间间隔要大于112.5ms + * @param - ir : ir数据 + * @param - ps : ps数据 + * @param - ps : als数据 + * @return : 无。 + */ +void ap3216c_readdata(unsigned short *ir, unsigned short *ps, unsigned short *als) +{ + unsigned char buf[6]; + unsigned char i; + + /* 循环读取所有传感器数据 */ + for(i = 0; i < 6; i++) + { + buf[i] = ap3216c_readonebyte(AP3216C_ADDR, AP3216C_IRDATALOW + i); + } + + if(buf[0] & 0X80) /* IR_OF位为1,则数据无效 */ + *ir = 0; + else /* 读取IR传感器的数据 */ + *ir = ((unsigned short)buf[1] << 2) | (buf[0] & 0X03); + + *als = ((unsigned short)buf[3] << 8) | buf[2]; /* 读取ALS传感器的数据 */ + + if(buf[4] & 0x40) /* IR_OF位为1,则数据无效 */ + *ps = 0; + else /* 读取PS传感器的数据 */ + *ps = ((unsigned short)(buf[5] & 0X3F) << 4) | (buf[4] & 0X0F); +} + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/ap3216c/bsp_ap3216c.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/ap3216c/bsp_ap3216c.h new file mode 100644 index 00000000..5054a4da --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/ap3216c/bsp_ap3216c.h @@ -0,0 +1,36 @@ +#ifndef _BSP_AP3216C_H +#define _BSP_AP3216C_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_ap3216c.h +作者 : 左忠凯 +版本 : V1.0 +描述 : AP3216C驱动头文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/3/26 左忠凯创建 +***************************************************************/ +#include "bsp.h" + +#define AP3216C_ADDR 0X1E /* AP3216C器件地址 */ + +/* AP3316C寄存器 */ +#define AP3216C_SYSTEMCONG 0x00 /* 配置寄存器 */ +#define AP3216C_INTSTATUS 0X01 /* 中断状态寄存器 */ +#define AP3216C_INTCLEAR 0X02 /* 中断清除寄存器 */ +#define AP3216C_IRDATALOW 0x0A /* IR数据低字节 */ +#define AP3216C_IRDATAHIGH 0x0B /* IR数据高字节 */ +#define AP3216C_ALSDATALOW 0x0C /* ALS数据低字节 */ +#define AP3216C_ALSDATAHIGH 0X0D /* ALS数据高字节 */ +#define AP3216C_PSDATALOW 0X0E /* PS数据低字节 */ +#define AP3216C_PSDATAHIGH 0X0F /* PS数据高字节 */ + +/* 函数声明 */ +unsigned char ap3216c_init(void); +unsigned char ap3216c_readonebyte(unsigned char addr,unsigned char reg); +unsigned char ap3216c_writeonebyte(unsigned char addr,unsigned char reg, unsigned char data); +void ap3216c_readdata(unsigned short *ir, unsigned short *ps, unsigned short *als); + +#endif + + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/backlight/bsp_backlight.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/backlight/bsp_backlight.c new file mode 100644 index 00000000..5529ac79 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/backlight/bsp_backlight.c @@ -0,0 +1,160 @@ +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_backlight.c +作者 : 左忠凯 +版本 : V1.0 +描述 : LCD背光PWM驱动文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/22 左忠凯创建 +***************************************************************/ +#include "bsp_backlight.h" +#include "bsp_int.h" +#include "printf.h" + + + +/* 背光设备 */ +struct backlight_dev_struc backlight_dev; + +/* + * @description : pwm1中断处理函数 + * @param : 无 + * @return : 无 + */ +void pwm1_irqhandler(void) +{ + + if(PWM1->PWMSR & (1 << 3)) /* FIFO为空中断 */ + { + /* 将占空比信息写入到FIFO中,其实就是设置占空比 */ + pwm1_setduty(backlight_dev.pwm_duty); + PWM1->PWMSR |= (1 << 3); /* 写1清除中断标志位 */ + } +} + +/* + * @description : 初始化背光PWM + * @param : 无 + * @return : 无 + */ +void backlight_init(void) +{ + unsigned char i = 0; + + /* 1、背光PWM IO初始化 */ + IOMUXC_SetPinMux(IOMUXC_GPIO1_IO08_PWM1_OUT, 0); /* 复用为PWM1_OUT */ + + /* 配置PWM IO属性 + *bit 16:0 HYS关闭 + *bit [15:14]: 10 100K上拉 + *bit [13]: 1 pull功能 + *bit [12]: 1 pull/keeper使能 + *bit [11]: 0 关闭开路输出 + *bit [7:6]: 10 速度100Mhz + *bit [5:3]: 010 驱动能力为R0/2 + *bit [0]: 0 低转换率 + */ + IOMUXC_SetPinConfig(IOMUXC_GPIO1_IO08_PWM1_OUT, 0XB090); + + /* 2、初始化PWM1 */ + /* + * 初始化寄存器PWMCR + * bit[27:26] : 01 当FIFO中空余位置大于等于2的时候FIFO空标志值位 + * bit[25] : + 0 停止模式下PWM不工作 + * bit[24] : 0 休眠模式下PWM不工作 + * bit[23] : 0 等待模式下PWM不工作 + * bit[22] : 0 调试模式下PWM不工作 + * bit[21] : 0 关闭字节交换 + * bit[20] : 0 关闭半字数据交换 + * bit[19:18] : 00 PWM输出引脚在计数器重新计数的时候输出高电平 + * 在计数器计数值达到比较值以后输出低电平 + * bit[17:16] : 01 PWM时钟源选择IPG CLK = 66MHz + * bit[15:4] : 65 分频系数为65+1=66，PWM时钟源 = 66MHZ/66=1MHz + * bit[3] : 0 PWM不复位 + * bit[2:1] : 00 FIFO中的sample数据每个只能使用一次。 + * bit[0] : 0 先关闭PWM，后面再使能 + */ + PWM1->PWMCR = 0; /* 寄存器先清零 */ + PWM1->PWMCR |= (1 << 26) | (1 << 16) | (65 << 4); + + /* 设置PWM周期为1000,那么PWM频率就是1M/1000 = 1KHz。 */ + pwm1_setperiod_value(1000); + + /* 设置占空比，默认50%占空比 ,写四次是因为有4个FIFO */ + backlight_dev.pwm_duty = 50; + for(i = 0; i < 4; i++) + { + pwm1_setduty(backlight_dev.pwm_duty); + } + + /* 使能FIFO空中断，设置寄存器PWMIR寄存器的bit0为1 */ + PWM1->PWMIR |= 1 << 0; + system_register_irqhandler(PWM1_IRQn, (system_irq_handler_t)pwm1_irqhandler, NULL); /* 注册中断服务函数 */ + GIC_EnableIRQ(PWM1_IRQn); /* 使能GIC中对应的中断 */ + PWM1->PWMSR = 0; /* PWM中断状态寄存器清零 */ + + pwm1_enable(); /* 使能PWM1 */ + + +} + +/* + * @description : 使能PWM + * @param : 无 + * @return : 无 + */ +void pwm1_enable(void) +{ + PWM1->PWMCR |= 1 << 0; +} + +/* + * @description : 设置Sample寄存器，Sample数据会写入到FIFO中， + * 所谓的Sample寄存器，就相当于比较寄存器，假如PWMCR中的POUTC + * 设置为00的时候。当PWM计数器中的计数值小于Sample的时候 + * 就会输出高电平，当PWM计数器值大于Sample的时候输出底电平, + * 因此可以通过设置Sample寄存器来设置占空比 + * @param - value : 寄存器值，范围0~0XFFFF + * @return : 无 + */ +void pwm1_setsample_value(unsigned int value) +{ + PWM1->PWMSAR = (value & 0XFFFF); +} + +/* + * @description : 设置PWM周期，就是设置寄存器PWMPR，PWM周期公式如下 + * PWM_FRE = PWM_CLK / (PERIOD + 2)， 比如当前PWM_CLK=1MHz + * 要产生1KHz的PWM，那么PERIOD = 1000000/1K - 2 = 998 + * @param - value : 周期值，范围0~0XFFFF + * @return : 无 + */ +void pwm1_setperiod_value(unsigned int value) +{ + unsigned int regvalue = 0; + + if(value < 2) + regvalue = 2; + else + regvalue = value - 2; + PWM1->PWMPR = (regvalue & 0XFFFF); +} + +/* + * @description : 设置PWM占空比 + * @param - value : 占空比0~100，对应0%~100% + * @return : 无 + */ +void pwm1_setduty(unsigned char duty) +{ + unsigned short preiod; + unsigned short sample; + + backlight_dev.pwm_duty = duty; + preiod = PWM1->PWMPR + 2; + sample = preiod * backlight_dev.pwm_duty / 100; + pwm1_setsample_value(sample); +} + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/backlight/bsp_backlight.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/backlight/bsp_backlight.h new file mode 100644 index 00000000..5b4abbd8 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/backlight/bsp_backlight.h @@ -0,0 +1,30 @@ +#ifndef _BACKLIGHT_H +#define _BACKLIGHT_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_backlight.c +作者 : 左忠凯 +版本 : V1.0 +描述 : LCD背光PWM驱动头文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/22 左忠凯创建 +***************************************************************/ +#include "bsp.h" + +/* 背光PWM结构体 */ +struct backlight_dev_struc +{ + unsigned char pwm_duty; /* 占空比 */ +}; + + +/* 函数声明 */ +void backlight_init(void); +void pwm1_enable(void); +void pwm1_setsample_value(unsigned int value); +void pwm1_setperiod_value(unsigned int value); +void pwm1_setduty(unsigned char duty); +void pwm1_irqhandler(void); + +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/beep/bsp_beep.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/beep/bsp_beep.c new file mode 100644 index 00000000..351981f2 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/beep/bsp_beep.c @@ -0,0 +1,54 @@ +#include "bsp_beep.h" +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_beep.c +作者 : 左忠凯 +版本 : V1.0 +描述 : 蜂鸣器驱动文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯创建 +***************************************************************/ + +/* + * @description : 初始化蜂鸣器对应的IO + * @param : 无 + * @return : 无 + */ +void beep_init(void) +{ + /* 1、初始化IO复用，复用为GPIO5_IO01 */ + IOMUXC_SetPinMux(IOMUXC_SNVS_SNVS_TAMPER1_GPIO5_IO01,0); + + + /* 2、、配置GPIO1_IO03的IO属性 + *bit 16:0 HYS关闭 + *bit [15:14]: 00 默认下拉 + *bit [13]: 0 kepper功能 + *bit [12]: 1 pull/keeper使能 + *bit [11]: 0 关闭开路输出 + *bit [7:6]: 10 速度100Mhz + *bit [5:3]: 110 R0/6驱动能力 + *bit [0]: 0 低转换率 + */ + IOMUXC_SetPinConfig(IOMUXC_SNVS_SNVS_TAMPER1_GPIO5_IO01,0X10B0); + + /* 3、初始化GPIO,GPIO5_IO01设置为输出 */ + GPIO5->GDIR |= (1 << 1); + + /* 4、设置GPIO5_IO01输出高电平，关闭蜂鸣器 */ + GPIO5->DR |= (1 << 1); +} + +/* + * @description : 蜂鸣器控制函数，控制蜂鸣器打开还是关闭 + * @param - status : 0，关闭蜂鸣器，1 打开蜂鸣器 + * @return : 无 + */ +void beep_switch(int status) +{ + if(status == ON) + GPIO5->DR &= ~(1 << 1); /* 打开蜂鸣器 */ + else if(status == OFF) + GPIO5->DR |= (1 << 1); /* 关闭蜂鸣器 */ +} diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/beep/bsp_beep.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/beep/bsp_beep.h new file mode 100644 index 00000000..27533514 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/beep/bsp_beep.h @@ -0,0 +1,20 @@ +#ifndef __BSP_BEEP_H +#define __BSP_BEEP_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_beep.h +作者 : 左忠凯 +版本 : V1.0 +描述 : 蜂鸣器驱动头文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯创建 +***************************************************************/ +#include "bsp.h" + + +/* 函数声明 */ +void beep_init(void); +void beep_switch(int status); +#endif + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/bmp280/bsp_bmp280.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/bmp280/bsp_bmp280.c new file mode 100644 index 00000000..dbe1a260 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/bmp280/bsp_bmp280.c @@ -0,0 +1,291 @@ +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_bmp280. +作者 : 左忠凯 +版本 : V1.0 +描述 : BMP280驱动文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/17 左忠凯创建 +***************************************************************/ +#include "bsp_bmp280.h" +#include "bsp_delay.h" +#include "bsp_spi.h" +#include "printf.h" + +/* BMP280属性结构体 */ +struct bmp280_dev_struc bmp280_dev; + +/* + * @description : 初始化BMP280 + * @param : 无 + * @return : 0 初始化成功，其他值 初始化失败 + */ +unsigned char bmp280_init(void) +{ + unsigned char regvalue; + gpio_pin_config_t cs_config; + + /* 1、初始化SPI */ + spi3_init(); + + /* 2、初始化片选引脚 */ + IOMUXC_SetPinMux(IOMUXC_UART2_TX_DATA_GPIO1_IO20, 0); + IOMUXC_SetPinConfig(IOMUXC_UART2_TX_DATA_GPIO1_IO20, 0X10B0); + cs_config.direction = kGPIO_DigitalOutput; + cs_config.outputLogic = 1; + gpio_init(GPIO1, 20, &cs_config); + + /* 4、配置BMP280 */ + regvalue = bmp280_read_reg(BMP280_ID_REG);/* 读取ID */ + if(regvalue == BMP280_ID_VALUE) + { + printf("bmp280 id = %#X\r\n", regvalue); + } else { + return 1; + } + + bmp280_write_reg(BMP280_RESET_REG, BMP280_RESET_VALUE); /* 复位BMP280 */ + bmp280_write_reg(BMP280_CTRLMEAS_REG, 0); /* 进入睡眠模式才可以写控制寄存器 */ + + /* 设置BMP280使用Ultra high resolution模式，即： + * osrs_p为X16，osrs_t为X2，IIR Filter为16 + */ + + /* + *配置BMP280控制寄存器CONFIG_REG + *bit[7:5] : 000 normal模式下的T_standby，0.5ms + *bit[4:2] : 111 IIR滤波器的时间常量 X16 + *bit[0] : 0 禁止3线SPI模式 + */ + bmp280_write_reg(BMP280_CONFIG_REG, 0x1C); + + /* + *配置BMP280测量寄存器CTRLMEAS_REG + *bit[7:5] : 010 温度采样率x2 17bit/0.0025°C + *bit[4:2] : 111 压力采样率x16 20bit/0.16Pa + *bit[1:0] : 11 normal模式 + */ + bmp280_write_reg(BMP280_CTRLMEAS_REG, 0x5F); + + bmp280_get_calibparam(); /* 计算参数 */ + + return 0; +} + +/* + * @description : 计算BMP280的计算参数 + * @param : 无 + * @return : 无 + */ +void bmp280_get_calibparam(void) +{ + unsigned char param_buf[BMP280_TRIMPARAM_LEN]; + + /* 读取BMP280的参数 */ + bmp280_read_len(BMP280_TRIMPARAM_FRG, param_buf, BMP280_TRIMPARAM_LEN); + + /* 计算参数 */ + bmp280_dev.calib_param.dig_T1 = (u16)((((u16)((u8)param_buf[1])) << 8) | param_buf[0]); + bmp280_dev.calib_param.dig_T2 = (s16)((((s16)((s8)param_buf[3])) << 8) | param_buf[2]); + bmp280_dev.calib_param.dig_T3 = (s16)((((s16)((s8)param_buf[5])) << 8) | param_buf[4]); + bmp280_dev.calib_param.dig_P1 = (u16)((((u16)((u8)param_buf[7])) << 8) | param_buf[6]); + bmp280_dev.calib_param.dig_P2 = (s16)((((s16)((s8)param_buf[9])) << 8) | param_buf[8]); + bmp280_dev.calib_param.dig_P3 = (s16)((((s16)((s8)param_buf[11])) << 8) | param_buf[10]); + bmp280_dev.calib_param.dig_P4 = (s16)((((s16)((s8)param_buf[13])) << 8) | param_buf[12]); + bmp280_dev.calib_param.dig_P5 = (s16)((((s16)((s8)param_buf[15])) << 8) | param_buf[14]); + bmp280_dev.calib_param.dig_P6 = (s16)((((s16)((s8)param_buf[17])) << 8) | param_buf[16]); + bmp280_dev.calib_param.dig_P7 = (s16)((((s16)((s8)param_buf[19])) << 8) | param_buf[18]); + bmp280_dev.calib_param.dig_P8 = (s16)((((s16)((s8)param_buf[21])) << 8) | param_buf[20]); + bmp280_dev.calib_param.dig_P9 = (s16)((((s16)((s8)param_buf[23])) << 8) | param_buf[22]); +} + +/* + * @description : 读取BMP280寄存器值 + * @param - reg : 要读取的寄存器地址 + * @return : 读取到的寄存器值 + */ +unsigned char bmp280_read_reg(unsigned char reg) +{ + unsigned char reg_val; + + /* BMP280在使用SPI接口的时候寄存器地址 + * 只有低7位有效,寄存器地址最高位是读/写标志位 + * 读的时候要为1，写的时候要为0。 + */ + reg |= 0x80; + + BMP280_CSN(0); /* 使能SPI传输 */ + spi3ch0_readwrite_byte(reg); /* 发送寄存器地址 */ + reg_val = spi3ch0_readwrite_byte(0XFF); /* 读取寄存器的值 */ + BMP280_CSN(1); /* 禁止SPI传输 */ + return(reg_val); /* 返回读取到的寄存器值 */ +} + +/* + * @description : 读取BMP280连续多个寄存器 + * @param - reg : 要读取的寄存器地址 + * @return : 读取到的寄存器值 + */ +void bmp280_read_len(unsigned char reg, unsigned char *buf, unsigned char len) +{ + unsigned char i; + + /* BMP280在使用SPI接口的时候寄存器地址 + * 只有低7位有效,寄存器地址最高位是读/写标志位 + * 读的时候要为1，写的时候要为0。 + */ + reg |= 0x80; + + BMP280_CSN(0); /* 使能SPI传输 */ + spi3ch0_readwrite_byte(reg); /* 发送寄存器地址 */ + for(i = 0; i < len; i++) /* 顺序读取寄存器的值 */ + { + buf[i]=spi3ch0_readwrite_byte(0XFF); + } + BMP280_CSN(1); /* 禁止SPI传输 */ +} + +/* + * @description : 写BMP280指定寄存器 + * @param - reg : 要读取的寄存器地址 + * @param - value: 要写入的值 + * @return : 无 + */ +void bmp280_write_reg(unsigned char reg, unsigned char value) +{ + /* BMP280在使用SPI接口的时候寄存器地址 + * 只有低7位有效,寄存器地址最高位是读/写标志位 + * 读的时候要为1，写的时候要为0。 + */ + reg &= ~0x80; + + BMP280_CSN(0); /* 使能SPI传输 */ + spi3ch0_readwrite_byte(reg); /* 发送寄存器地址 */ + spi3ch0_readwrite_byte(value); /* 发送要写入的值 */ + BMP280_CSN(1); /* 禁止SPI传输 */ +} + +/* + * @description : 获取BMP280原始的温度数据值 + * @param : 无 + * @return : 原始的温度数据值 + */ +signed int bmp280_get_uncomptemp(void) +{ + unsigned char temp_value[3]; + signed int uncomp_temp = 0; + bmp280_read_len(BMP280_TEMPMSB_REG, temp_value, 3); + + uncomp_temp = (s32)((((u32)(temp_value[0])) << 12) + | (((u32)(temp_value[1])) << 4) + | ((u32)temp_value[2] >> 4)); + return uncomp_temp; +} + +/* + * @description : 获取BMP280原始的压力数据值 + * @param : 无 + * @return : 原始的温度数据值 + */ +signed int bmp280_get_uncomppres(void) +{ + unsigned char pres_value[3]; + signed int uncomp_pres = 0; + + bmp280_read_len(BMP280_PRESMSB_REG, pres_value, 3); + + uncomp_pres = (s32)((((u32)(pres_value[0])) << 12) + | (((u32)(pres_value[1])) << 4) + | ((u32)pres_value[2] >> 4)); + return uncomp_pres; +} + +/* + * @description : 从BMP280的原始温度数据值计算出真实的温度数据值 + * @param - uncomptemp : 原始的温度数据值 + * @return : 得到的真实的数据值，这里将温度值扩大了100倍 + * 比如5123 = 51.23°C。 + */ +signed int bmp280_get_actualtemp(signed int uncomptemp) +{ + s32 v_x1_u32r = 0, v_x2_u32r = 0; + s32 temperature = 0; + + /* 计算温度值，X1 */ + v_x1_u32r = ((((uncomptemp >> 3) - ((s32)bmp280_dev.calib_param.dig_T1 << 1))) + * ((s32)bmp280_dev.calib_param.dig_T2)) >> 11; + + /* 计算温度值，X2 */ + v_x2_u32r = (((((uncomptemp >> 4)- ((s32)bmp280_dev.calib_param.dig_T1)) + * ((uncomptemp >> 4) - ((s32)bmp280_dev.calib_param.dig_T1))) >> 12) + * ((s32)bmp280_dev.calib_param.dig_T3)) >> 14; + + + /* 计算t_fine */ + bmp280_dev.calib_param.t_fine = v_x1_u32r + v_x2_u32r; + + /* 计算真实的温度值 */ + temperature = (bmp280_dev.calib_param.t_fine * 5 + 128) >> 8; + + return temperature; +} + +/* + * @description : 从BMP280的原始气压数据值计算出真实的气压数据值 + * @param - uncomppres : 原始的气压数据值 + * @return : 得到的真实的气压数据值，比如23658就是: + * 23658Pa = 236.58hPa = 236.58 milllibar。 + */ +unsigned int bmp280_get_actualpres(s32 uncomppres) +{ + s32 v_x1_u32r = 0; + s32 v_x2_u32r = 0; + u32 v_pressure_u32 = 0; + + /* 计算X1 */ + v_x1_u32r = (((s32)bmp280_dev.calib_param.t_fine) >> 1) - (s32)64000; + + /* 计算X2*/ + v_x2_u32r = (((v_x1_u32r >> 2) * (v_x1_u32r >> 2)) >> 11) * ((s32)bmp280_dev.calib_param.dig_P6); + v_x2_u32r = v_x2_u32r + ((v_x1_u32r * ((s32)bmp280_dev.calib_param.dig_P5)) << 1); + v_x2_u32r = (v_x2_u32r >> 2) + (((s32)bmp280_dev.calib_param.dig_P4) << 16); + + /* 计算X1*/ + v_x1_u32r = (((bmp280_dev.calib_param.dig_P3 * (((v_x1_u32r >> 2) * (v_x1_u32r >> 2)) >> 13)) >> 3) + + ((((s32)bmp280_dev.calib_param.dig_P2) * v_x1_u32r) >> 1)) >> 18; + v_x1_u32r = ((((32768 + v_x1_u32r)) * ((s32)bmp280_dev.calib_param.dig_P1)) >> 15); + + /* 计算气压值 */ + v_pressure_u32 = (((u32)(((s32)1048576) - uncomppres) - (v_x2_u32r >> 12))) * 3125; + + /* 检查溢出 */ + if (v_pressure_u32 < 0x80000000) + { + if (v_x1_u32r != 0) + v_pressure_u32 = (v_pressure_u32 << 1) / ((u32)v_x1_u32r); + else + return BMP280_INVALID_DATA; + } else { + + if (v_x1_u32r != 0) + v_pressure_u32 = (v_pressure_u32 / (u32)v_x1_u32r) * 2; + else + return BMP280_INVALID_DATA; + } + + /* 计算X1 */ + v_x1_u32r = (((s32)bmp280_dev.calib_param.dig_P9) * ((s32)(((v_pressure_u32 >> 3) + * (v_pressure_u32 >> 3)) >> 13))) >> 12; + + /* 计算X2*/ + v_x2_u32r = (((s32)(v_pressure_u32 >> 2)) * ((s32)bmp280_dev.calib_param.dig_P8)) >> 13; + + /* 计算真实的气压值*/ + v_pressure_u32 = (u32)((s32)v_pressure_u32 + ((v_x1_u32r + v_x2_u32r + + bmp280_dev.calib_param.dig_P7) >> 4)); + + return v_pressure_u32; +} + + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/bmp280/bsp_bmp280.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/bmp280/bsp_bmp280.h new file mode 100644 index 00000000..5e9f8f24 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/bmp280/bsp_bmp280.h @@ -0,0 +1,88 @@ +#ifndef _BSP_BMP280_H +#define _BSP_BMP280_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_bmp280.h +作者 : 左忠凯 +版本 : V1.0 +描述 : BMP280驱动头文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/17 左忠凯创建 +***************************************************************/ +#include "bsp.h" +#include "bsp_gpio.h" + +/* 宏定义 */ +#define BMP280_CSN(n) (n ? gpio_pinwrite(GPIO1, 20, 1) : gpio_pinwrite(GPIO1, 20, 0)) //SPI片选信号 + +#define BMP280_ID_VALUE 0X58 /* BMP280 ID值 */ +#define BMP280_RESET_VALUE 0XB6 /* BMP280复位值 */ + + +/* BMP280寄存器宏定义 */ +#define BMP280_TEMPXLSB_REG 0XFC /* 温度值的bit[3:0]寄存器 */ +#define BMP280_TEMPLSB_REG 0XFB /* 温度值的bit[11:4]寄存器 */ +#define BMP280_TEMPMSB_REG 0XFA /* 温度值的bit[19:12]寄存器 */ +#define BMP280_PRESXLSB_REG 0XF9 /* 压力值的bit[3:0]寄存器 */ +#define BMP280_PRESLSB_REG 0XF8 /* 压力值的bit[11:4]寄存器 */ +#define BMP280_PRESMSB_REG 0XF7 /* 压力值的bit[19:12]寄存器 */ +#define BMP280_CONFIG_REG 0XF5 /* 配置寄存器 */ +#define BMP280_CTRLMEAS_REG 0XF4 /* 测量配置寄存器 */ +#define BMP280_STATUS_REG 0XF3 /* 状态寄存器 */ +#define BMP280_RESET_REG 0XE0 /* 复位寄存器 */ +#define BMP280_ID_REG 0XD0 /* ID寄存器 */ + +#define BMP280_TRIMPARAM_FRG 0X88 /* 参数组寄存器首地址 */ +#define BMP280_TRIMPARAM_LEN 24 /* 参数组寄存器长度 */ + +#define BMP280_INVALID_DATA 0 /* 无效的数据 */ + +/* + * BMP280 参数结构体 + */ +struct bmp280_calib_param +{ + unsigned short dig_T1; /* T1参数 */ + short dig_T2; /* T2参数 */ + short dig_T3; /* T3参数 */ + unsigned short dig_P1; /* P1参数 */ + short dig_P2; /* P2参数 */ + short dig_P3; /* P3参数 */ + short dig_P4; /* P4参数 */ + short dig_P5; /* P5参数 */ + short dig_P6; /* P6参数 */ + short dig_P7; /* P7参数 */ + short dig_P8; /* P8参数 */ + short dig_P9; /* P9参数 */ + signed int t_fine; /* t_fine参数*/ +}; + +/* + * BMP280结构体 + */ +struct bmp280_dev_struc +{ + struct bmp280_calib_param calib_param; + + signed int uncomp_temp; /* 原始的温度值 */ + signed int uncomp_pres; /* 原始的压力值 */ + signed int actual_temp; /* 真实的温度值 */ + signed int actual_pres; /* 真实的压力值 */ + +}; + +extern struct bmp280_dev_struc bmp280_dev; + +/* 函数声明 */ +unsigned char bmp280_init(void); +unsigned char bmp280_read_reg(unsigned char reg); +void bmp280_read_len(unsigned char reg, unsigned char *buf, unsigned char len); +void bmp280_write_reg(unsigned char reg, unsigned char value); +void bmp280_get_calibparam(void); +signed int bmp280_get_uncomptemp(void); +signed int bmp280_get_uncomppres(void); +signed int bmp280_get_actualtemp(signed int uncomptemp); +unsigned int bmp280_get_actualpres(s32 uncomppres); + +#endif \ No newline at end of file diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/clk/bsp_clk.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/clk/bsp_clk.c new file mode 100644 index 00000000..22b7dee5 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/clk/bsp_clk.c @@ -0,0 +1,126 @@ +#include "bsp_clk.h" + +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_clk.c +作者 : 左忠凯 +版本 : V1.0 +描述 : 系统时钟驱动。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/3 左忠凯创建 + V2.0 2019/1/3 左忠凯修改 + 添加了函数imx6u_clkinit()，完成I.MX6U的系统时钟初始化 + V2.1 2019/3/1 左忠凯修改 + 添加UART时钟源配置代码 +***************************************************************/ + +/* + * @description : 使能I.MX6U所有外设时钟 + * @param : 无 + * @return : 无 + */ +void clk_enable(void) +{ + CCM->CCGR0 = 0XFFFFFFFF; + CCM->CCGR1 = 0XFFFFFFFF; + CCM->CCGR2 = 0XFFFFFFFF; + CCM->CCGR3 = 0XFFFFFFFF; + CCM->CCGR4 = 0XFFFFFFFF; + CCM->CCGR5 = 0XFFFFFFFF; + CCM->CCGR6 = 0XFFFFFFFF; +} + +/* + * @description : 初始化系统时钟，设置系统时钟为528Mhz，并且设置PLL2和PLL3各个 + PFD时钟,所有的时钟频率均按照I.MX6U官方手册推荐的值. + * @param : 无 + * @return : 无 + */ +void imx6u_clkinit(void) +{ + unsigned int reg = 0; + /* 1、设置ARM内核时钟为528MHz */ + /* 1.1、判断当前ARM内核是使用的那个时钟源启动的，正常情况下ARM内核是由pll1_sw_clk驱动的，而 + * pll1_sw_clk有两个来源：pll1_main_clk和tep_clk(参考手册648页)。 + * 如果我们要让ARM内核跑到528M的话那必须选择pll1_main_clk作为pll1的时钟源。 + * 如果我们要修改pll1_main_clk时钟的话就必须先将pll1_sw_clk从pll1_main_clk切换到step_clk, + * 当修改完pll1_main_clk以后在将pll1_sw_clk切换回pll1_main_clk。而step_clk的时钟源可以选择 + * 板子上的24MHz晶振。 + */ + + if((((CCM->CCSR) >> 2) & 0x1 ) == 0) /* 当前pll1_sw_clk使用的pll1_main_clk*/ + { + CCM->CCSR &= ~(1 << 8); /* 配置step_clk时钟源为24MH OSC */ + CCM->CCSR |= (1 << 2); /* 配置pll1_sw_clk时钟源为step_clk */ + } + + /* 1.2、设置pll1_main_clk为1056MHz,也就是528*2=1056MHZ, + * 因为pll1_sw_clk进ARM内核的时候会被二分频！ + * 配置CCM_ANLOG->PLL_ARM寄存器 + * bit13: 1 使能时钟输出 + * bit[6:0]: 88, 由公式：Fout = Fin * div_select / 2.0，1056=24*div_select/2.0, + * 得出：div_select= 88 + */ + CCM_ANALOG->PLL_ARM = (1 << 13) | ((88 << 0) & 0X7F); /* 配置pll1_main_clk=1056MHz */ + CCM->CCSR &= ~(1 << 2); /* 将pll_sw_clk时钟重新切换回pll1_main_clk */ + CCM->CACRR = 1; /* ARM内核时钟为pll1_sw_clk/2=1056/2=528Mhz */ + + /* 2、设置PLL2(SYS PLL)各个PFD */ + reg = CCM_ANALOG->PFD_528; + reg &= ~(0X3F3F3F3F); /* 清除原来的设置 */ + reg |= 32<<24; /* PLL2_PFD3=528*18/32=297Mhz */ + reg |= 24<<16; /* PLL2_PFD2=528*18/24=396Mhz(DDR使用的时钟，最大400Mhz) */ + reg |= 16<<8; /* PLL2_PFD1=528*18/16=594Mhz */ + reg |= 27<<0; /* PLL2_PFD0=528*18/27=352Mhz */ + CCM_ANALOG->PFD_528=reg; /* 设置PLL2_PFD0~3 */ + + /* 3、设置PLL3(USB1)各个PFD */ + reg = 0; /* 清零 */ + reg = CCM_ANALOG->PFD_480; + reg &= ~(0X3F3F3F3F); /* 清除原来的设置 */ + reg |= 19<<24; /* PLL3_PFD3=480*18/19=454.74Mhz */ + reg |= 17<<16; /* PLL3_PFD2=480*18/17=508.24Mhz */ + reg |= 16<<8; /* PLL3_PFD1=480*18/16=540Mhz */ + reg |= 12<<0; /* PLL3_PFD0=480*18/12=720Mhz */ + CCM_ANALOG->PFD_480=reg; /* 设置PLL3_PFD0~3 */ + + /* 4、设置AHB时钟 最小6Mhz， 最大132Mhz (boot rom自动设置好了可以不用设置)*/ + CCM->CBCMR &= ~(3 << 18); /* 清除设置*/ + CCM->CBCMR |= (1 << 18); /* pre_periph_clk=PLL2_PFD2=396MHz */ + CCM->CBCDR &= ~(1 << 25); /* periph_clk=pre_periph_clk=396MHz */ + while(CCM->CDHIPR & (1 << 5));/* 等待握手完成 */ + + /* 修改AHB_PODF位的时候需要先禁止AHB_CLK_ROOT的输出，但是 + * 我没有找到关闭AHB_CLK_ROOT输出的的寄存器，所以就没法设置。 + * 下面设置AHB_PODF的代码仅供学习参考不能直接拿来使用！！ + * 内部boot rom将AHB_PODF设置为了3分频，即使我们不设置AHB_PODF， + * AHB_ROOT_CLK也依旧等于396/3=132Mhz。 + */ +#if 0 + /* 要先关闭AHB_ROOT_CLK输出，否则时钟设置会出错 */ + CCM->CBCDR &= ~(7 << 10); /* CBCDR的AHB_PODF清零 */ + CCM->CBCDR |= 2 << 10; /* AHB_PODF 3分频，AHB_CLK_ROOT=132MHz */ + while(CCM->CDHIPR & (1 << 1));/ +* 等待握手完成 */ +#endif + + /* 5、设置IPG_CLK_ROOT最小3Mhz，最大66Mhz (boot rom自动设置好了可以不用设置)*/ + CCM->CBCDR &= ~(3 << 8); /* CBCDR的IPG_PODF清零 */ + CCM->CBCDR |= 1 << 8; /* IPG_PODF 2分频，IPG_CLK_ROOT=66MHz */ + + /* 6、设置PERCLK_CLK_ROOT时钟 */ + CCM->CSCMR1 &= ~(1 << 6); /* PERCLK_CLK_ROOT时钟源为IPG */ + CCM->CSCMR1 &= ~(7 << 0); /* PERCLK_PODF位清零，即1分频 */ + + /* 设置UART时钟源频率为80M */ + CCM->CSCDR1 &= ~(1 << 6); /* UART时钟源为pll3_80m */ + CCM->CSCDR1 &= ~0X3F; /* UART时钟1分频 */ + +#if 0 + /* 设置ECSPI时钟源为60Mhz */ + CCM->CSCDR2 &= ~(1 << 18); /* ECSPI时钟源为pll3_60m*/ + CCM->CSCDR2 &= ~(0X3F << 19); /* ECSPI 1分频 */ +#endif +} + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/clk/bsp_clk.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/clk/bsp_clk.h new file mode 100644 index 00000000..09bfb591 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/clk/bsp_clk.h @@ -0,0 +1,21 @@ +#ifndef __BSP_CLK_H +#define __BSP_CLK_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_clk.h +作者 : 左忠凯 +版本 : V1.0 +描述 : 系统时钟驱动头文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯创建 +***************************************************************/ + +#include "bsp.h" + +/* 函数声明 */ +void clk_enable(void); +void imx6u_clkinit(void); + + +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/delay/bsp_delay.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/delay/bsp_delay.c new file mode 100644 index 00000000..73dcbe36 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/delay/bsp_delay.c @@ -0,0 +1,180 @@ +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_delay.c +作者 : 左忠凯 +版本 : V1.0 +描述 : 延时文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯创建 + + V2.0 2019/1/15 左忠凯修改 + 使用定时器GPT实现高精度延时,添加了： + delay_init 延时初始化函数 + gpt1_irqhandler gpt1定时器中断处理函数 + delayus us延时函数 + delayms ms延时函数 +***************************************************************/ +#include "bsp_delay.h" + +/* + * @description : 延时有关硬件初始化,主要是GPT定时器 + GPT定时器时钟源选择ipg_clk=66Mhz + * @param : 无 + * @return : 无 + */ +void delay_init(void) +{ + GPT1->CR = 0; /* 清零，bit0也为0，即停止GPT */ + + GPT1->CR = 1 << 15; /* bit15置1进入软复位 */ + while((GPT1->CR >> 15) & 0x01); /*等待复位完成 */ + + /* + * GPT的CR寄存器,GPT通用设置 + * bit22:20 000 输出比较1的输出功能关闭，也就是对应的引脚没反应 + * bit9: 0 Restart模式,当CNT等于OCR1的时候就产生中断 + * bit8:6 001 GPT时钟源选择ipg_clk=66Mhz + * bit + */ + GPT1->CR = (1<<6); + + /* + * GPT的PR寄存器，GPT的分频设置 + * bit11:0 设置分频值，设置为0表示1分频， + * 以此类推，最大可以设置为0XFFF，也就是最大4096分频 + */ + GPT1->PR = 65; /* 设置为65，即66分频，因此GPT1时钟为66M/(65+1)=1MHz */ + + /* + * GPT的OCR1寄存器，GPT的输出比较1比较计数值， + * GPT的时钟为1Mz，那么计数器每计一个值就是就是1us。 + * 为了实现较大的计数，我们将比较值设置为最大的0XFFFFFFFF, + * 这样一次计满就是：0XFFFFFFFFus = 4294967296us = 4295s = 71.5min + * 也就是说一次计满最多71.5分钟，存在溢出 + */ + GPT1->OCR[0] = 0XFFFFFFFF; + + GPT1->CR |= 1<<0; //使能GPT1 + + /* 一下屏蔽的代码是GPT定时器中断代码， + * 如果想学习GPT定时器的话可以参考一下代码。 + */ +#if 0 + /* + * GPT的PR寄存器，GPT的分频设置 + * bit11:0 设置分频值，设置为0表示1分频， + * 以此类推，最大可以设置为0XFFF，也就是最大4096分频 + */ + GPT1->PR = 65; //设置为1，即65+1=66分频，因此GPT1时钟为66M/66=1MHz + + + /* + * GPT的OCR1寄存器，GPT的输出比较1比较计数值， + * 当GPT的计数值等于OCR1里面值时候，输出比较1就会发生中断 + * 这里定时500ms产生中断，因此就应该为1000000/2=500000; + */ + GPT1->OCR[0] = 500000; + + /* + * GPT的IR寄存器，使能通道1的比较中断 + * bit0： 0 使能输出比较中断 + */ + GPT1->IR |= 1 << 0; + + /* + * 使能GIC里面相应的中断，并且注册中断处理函数 + */ + GIC_EnableIRQ(GPT1_IRQn); //使能GIC中对应的中断 + system_register_irqhandler(GPT1_IRQn, (system_irq_handler_t)gpt1_irqhandler, NULL); //注册中断服务函数 +#endif + +} + +#if 0 +/* 中断处理函数 */ +void gpt1_irqhandler(void) +{ + static unsigned char state = 0; + + state = !state; + + /* + * GPT的SR寄存器，状态寄存器 + * bit2： 1 输出比较1发生中断 + */ + if(GPT1->SR & (1<<0)) + { + led_switch(LED2, state); + } + + GPT1->SR |= 1<<0; /* 清除中断标志位 */ +} +#endif + +/* + * @description : 微秒(us)级延时 + * @param - value : 需要延时的us数,最大延时0XFFFFFFFFus + * @return : 无 + */ +void delayus(unsigned int usdelay) +{ + unsigned long oldcnt,newcnt; + unsigned long tcntvalue = 0; /* 走过的总时间 */ + + oldcnt = GPT1->CNT; + while(1) + { + newcnt = GPT1->CNT; + if(newcnt != oldcnt) + { + if(newcnt > oldcnt) /* GPT是向上计数器,并且没有溢出 */ + tcntvalue += newcnt - oldcnt; + else /* 发生溢出 */ + tcntvalue += 0XFFFFFFFF-oldcnt + newcnt; + oldcnt = newcnt; + if(tcntvalue >= usdelay)/* 延时时间到了 */ + break; /* 跳出 */ + } + } +} + +/* + * @description : 毫秒(ms)级延时 + * @param - msdelay : 需要延时的ms数 + * @return : 无 + */ +void delayms(unsigned int msdelay) +{ + int i = 0; + for(i=0; i 0XFFF) + frac = 0XFFF; + + EPIT1->CR = 0; /* 先清零CR寄存器 */ + + /* + * CR寄存器: + * bit25:24 01 时钟源选择Peripheral clock=66MHz + * bit15:4 frac 分频值 + * bit3: 1 当计数器到0的话从LR重新加载数值 + * bit2: 1 比较中断使能 + * bit1: 1 初始计数值来源于LR寄存器值 + * bit0: 0 先关闭EPIT1 + */ + EPIT1->CR = (1<<24 | frac << 4 | 1<<3 | 1<<2 | 1<<1); + + EPIT1->LR = value; /* 倒计数值 */ + EPIT1->CMPR = 0; /* 比较寄存器，当计数器值和此寄存器值相等的话就会产生中断 */ + + /* 使能GIC中对应的中断 */ + GIC_EnableIRQ(EPIT1_IRQn); + + /* 注册中断服务函数 */ + +#if 0 + system_register_irqhandler(EPIT1_IRQn, (system_irq_handler_t)epit1_irqhandler, NULL); +#else + tos_interrupt_handler_register(EPIT1_IRQn, (int_handler_t)epit1_irqhandler, NULL); +#endif + + EPIT1->CR |= 1<<0; /* 使能EPIT1 */ +} + +/* + * @description : EPIT中断处理函数 + * @param : 无 + * @return : 无 + */ +void epit1_irqhandler(void *arg) +{ + static unsigned char state = 0; + printf("######\r\n"); + + state = !state; + if(EPIT1->SR & (1<<0)) /* 判断比较事件发生 */ + { + led_switch(LED0, state); /* 定时器周期到，反转LED */ + } + + EPIT1->SR |= 1<<0; /* 清除中断标志位 */ +} + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/epittimer/bsp_epittimer.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/epittimer/bsp_epittimer.h new file mode 100644 index 00000000..d54da8f8 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/epittimer/bsp_epittimer.h @@ -0,0 +1,20 @@ +#ifndef _BSP_EPITTIMER_H +#define _BSP_EPITTIMER_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_epittimer.h +作者 : 左忠凯 +版本 : V1.0 +描述 : EPIT定时器驱动头文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/5 左忠凯创建 +***************************************************************/ +#include "bsp.h" + + +/* 函数声明 */ +void epit1_init(unsigned int frac, unsigned int value); +void epit1_irqhandler(void *arg); + +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/exit/bsp_exit.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/exit/bsp_exit.c new file mode 100644 index 00000000..4d5e82b7 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/exit/bsp_exit.c @@ -0,0 +1,71 @@ +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_exit.c +作者 : 左忠凯 +版本 : V1.0 +描述 : 外部中断驱动。 +其他 : 配置按键对应的GPIP为中断模式 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯创建 +***************************************************************/ +#include "bsp_exit.h" +#include "bsp_gpio.h" +#include "bsp_delay.h" +#include "bsp_beep.h" +#include "bsp_int.h" + +#include "tos_k.h" + +/* + * @description : 初始化外部中断 + * @param : 无 + * @return : 无 + */ +void exit_init(void) +{ + gpio_pin_config_t key_config; + + /* 1、设置IO复用 */ + IOMUXC_SetPinMux(IOMUXC_UART1_CTS_B_GPIO1_IO18,0); /* 复用为GPIO1_IO18 */ + IOMUXC_SetPinConfig(IOMUXC_UART1_CTS_B_GPIO1_IO18,0xF080); + + /* 2、初始化GPIO为中断模式 */ + key_config.direction = kGPIO_DigitalInput; + key_config.interruptMode = kGPIO_IntFallingEdge; + key_config.outputLogic = 1; + gpio_init(GPIO1, 18, &key_config); + + GIC_EnableIRQ(GPIO1_Combined_16_31_IRQn); /* 使能GIC中对应的中断 */ +#if 0 + system_register_irqhandler(GPIO1_Combined_16_31_IRQn, (system_irq_handler_t)gpio1_io18_irqhandler, NULL); /* 注册中断服务函数 */ +#else + tos_interrupt_handler_register(GPIO1_Combined_16_31_IRQn, (int_handler_t)gpio1_io18_irqhandler, NULL); +#endif + gpio_enableint(GPIO1, 18); /* 使能GPIO1_IO18的中断功能 */ +} + +/* + * @description : GPIO1_IO18最终的中断处理函数 + * @param : 无 + * @return : 无 + */ +void gpio1_io18_irqhandler(void *arg) +{ + static unsigned char state = 0; + + /* + *采用延时消抖，中断服务函数中禁止使用延时函数！因为中断服务需要 + *快进快出！！这里为了演示所以采用了延时函数进行消抖，后面我们会讲解 + *定时器中断消抖法！！！ + */ + + delay(10); + if (gpio_pinread(GPIO1, 18) == 0) /* 按键按下了 */ + { + state = !state; + beep_switch(state); + } + + gpio_clearintflags(GPIO1, 18); /* 清除中断标志位 */ +} + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/exit/bsp_exit.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/exit/bsp_exit.h new file mode 100644 index 00000000..1ca7313a --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/exit/bsp_exit.h @@ -0,0 +1,19 @@ +#ifndef _BSP_EXIT_H +#define _BSP_EXIT_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_exit.c +作者 : 左忠凯 +版本 : V1.0 +描述 : 外部中断驱动头文件。 +其他 : 配置按键对应的GPIP为中断模式 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯创建 +***************************************************************/ +#include "bsp.h" + +/* 函数声明 */ +void exit_init(void); /* 中断初始化 */ +void gpio1_io18_irqhandler(void *arg); /* 中断处理函数 */ + +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/gpio/bsp_gpio.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/gpio/bsp_gpio.c new file mode 100644 index 00000000..93f4db24 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/gpio/bsp_gpio.c @@ -0,0 +1,153 @@ +#include "bsp_gpio.h" +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_gpio.h +作者 : 左忠凯 +版本 : V1.0 +描述 : GPIO操作文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯创建 + V2.0 2019/1/4 左忠凯修改: + 修改gpio_init()函数，支持中断配置. + 添加gpio_intconfig()函数，初始化中断 + 添加gpio_enableint()函数，使能中断 + 添加gpio_clearintflags()函数，清除中断标志位 + +***************************************************************/ + +/* + * @description : GPIO初始化。 + * @param - base : 要初始化的GPIO组。 + * @param - pin : 要初始化GPIO在组内的编号。 + * @param - config : GPIO配置结构体。 + * @return : 无 + */ +void gpio_init(GPIO_Type *base, int pin, gpio_pin_config_t *config) +{ + base->IMR &= ~(1U << pin); + + if(config->direction == kGPIO_DigitalInput) /* GPIO作为输入 */ + { + base->GDIR &= ~( 1 << pin); + } + else /* 输出 */ + { + base->GDIR |= 1 << pin; + gpio_pinwrite(base,pin, config->outputLogic); /* 设置默认输出电平 */ + } + gpio_intconfig(base, pin, config->interruptMode); /* 中断功能配置 */ +} + +/* + * @description : 读取指定GPIO的电平值 。 + * @param - base : 要读取的GPIO组。 + * @param - pin : 要读取的GPIO脚号。 + * @return : 无 + */ + int gpio_pinread(GPIO_Type *base, int pin) + { + return (((base->DR) >> pin) & 0x1); + } + +/* + * @description : 指定GPIO输出高或者低电平 。 + * @param - base : 要输出的的GPIO组。 + * @param - pin : 要输出的GPIO脚号。 + * @param - value : 要输出的电平，1 输出高电平， 0 输出低低电平 + * @return : 无 + */ +void gpio_pinwrite(GPIO_Type *base, int pin, int value) +{ + if (value == 0U) + { + base->DR &= ~(1U << pin); /* 输出低电平 */ + } + else + { + base->DR |= (1U << pin); /* 输出高电平 */ + } +} + +/* + * @description : 设置GPIO的中断配置功能 + * @param - base : 要配置的IO所在的GPIO组。 + * @param - pin : 要配置的GPIO脚号。 + * @param - pinInterruptMode: 中断模式，参考枚举类型gpio_interrupt_mode_t + * @return : 无 + */ +void gpio_intconfig(GPIO_Type* base, unsigned int pin, gpio_interrupt_mode_t pin_int_mode) +{ + volatile uint32_t *icr; + uint32_t icrShift; + + icrShift = pin; + + base->EDGE_SEL &= ~(1U << pin); + + if(pin < 16) /* 低16位 */ + { + icr = &(base->ICR1); + } + else /* 高16位 */ + { + icr = &(base->ICR2); + icrShift -= 16; + } + switch(pin_int_mode) + { + case(kGPIO_IntLowLevel): + *icr &= ~(3U << (2 * icrShift)); + break; + case(kGPIO_IntHighLevel): + *icr = (*icr & (~(3U << (2 * icrShift)))) | (1U << (2 * icrShift)); + break; + case(kGPIO_IntRisingEdge): + *icr = (*icr & (~(3U << (2 * icrShift)))) | (2U << (2 * icrShift)); + break; + case(kGPIO_IntFallingEdge): + *icr |= (3U << (2 * icrShift)); + break; + case(kGPIO_IntRisingOrFallingEdge): + base->EDGE_SEL |= (1U << pin); + break; + default: + break; + } +} + + +/* + * @description : 使能GPIO的中断功能 + * @param - base : 要使能的IO所在的GPIO组。 + * @param - pin : 要使能的GPIO在组内的编号。 + * @return : 无 + */ +void gpio_enableint(GPIO_Type* base, unsigned int pin) +{ + base->IMR |= (1 << pin); +} + +/* + * @description : 禁止GPIO的中断功能 + * @param - base : 要禁止的IO所在的GPIO组。 + * @param - pin : 要禁止的GPIO在组内的编号。 + * @return : 无 + */ +void gpio_disableint(GPIO_Type* base, unsigned int pin) +{ + base->IMR &= ~(1 << pin); +} + +/* + * @description : 清除中断标志位(写1清除) + * @param - base : 要清除的IO所在的GPIO组。 + * @param - pin : 要清除的GPIO掩码。 + * @return : 无 + */ +void gpio_clearintflags(GPIO_Type* base, unsigned int pin) +{ + base->ISR |= (1 << pin); +} + + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/gpio/bsp_gpio.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/gpio/bsp_gpio.h new file mode 100644 index 00000000..034dae4e --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/gpio/bsp_gpio.h @@ -0,0 +1,61 @@ +#ifndef _BSP_GPIO_H +#define _BSP_GPIO_H +#define _BSP_KEY_H +#include "bsp.h" +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_gpio.h +作者 : 左忠凯 +版本 : V1.0 +描述 : GPIO操作文件头文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯创建 + V2.0 2019/1/4 左忠凯修改 + 添加GPIO中断相关定义 + +***************************************************************/ + +/* + * 枚举类型和结构体定义 + */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /* 输入 */ + kGPIO_DigitalOutput = 1U, /* 输出 */ +} gpio_pin_direction_t; + +/* + * GPIO中断触发类型枚举 + */ +typedef enum _gpio_interrupt_mode +{ + kGPIO_NoIntmode = 0U, /* 无中断功能 */ + kGPIO_IntLowLevel = 1U, /* 低电平触发 */ + kGPIO_IntHighLevel = 2U, /* 高电平触发 */ + kGPIO_IntRisingEdge = 3U, /* 上升沿触发 */ + kGPIO_IntFallingEdge = 4U, /* 下降沿触发 */ + kGPIO_IntRisingOrFallingEdge = 5U, /* 上升沿和下降沿都触发 */ +} gpio_interrupt_mode_t; + +/* + * GPIO配置结构体 + */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t direction; /* GPIO方向:输入还是输出 */ + uint8_t outputLogic; /* 如果是输出的话，默认输出电平 */ + gpio_interrupt_mode_t interruptMode; /* 中断方式 */ +} gpio_pin_config_t; + + +/* 函数声明 */ +void gpio_init(GPIO_Type *base, int pin, gpio_pin_config_t *config); +int gpio_pinread(GPIO_Type *base, int pin); +void gpio_pinwrite(GPIO_Type *base, int pin, int value); +void gpio_intconfig(GPIO_Type* base, unsigned int pin, gpio_interrupt_mode_t pinInterruptMode); +void gpio_enableint(GPIO_Type* base, unsigned int pin); +void gpio_disableint(GPIO_Type* base, unsigned int pin); +void gpio_clearintflags(GPIO_Type* base, unsigned int pin); + +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/i2c/bsp_i2c.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/i2c/bsp_i2c.c new file mode 100644 index 00000000..65620075 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/i2c/bsp_i2c.c @@ -0,0 +1,315 @@ +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_i2c.c +作者 : 左忠凯 +版本 : V1.0 +描述 : IIC驱动文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/15 左忠凯创建 +***************************************************************/ +#include "bsp_i2c.h" +#include "bsp_delay.h" +#include "printf.h" + +/* + * @description : 初始化I2C，波特率100KHZ + * @param - base : 要初始化的IIC设置 + * @return : 无 + */ +void i2c_init(I2C_Type *base) +{ + /* 1、配置I2C */ + base->I2CR &= ~(1 << 7); /* 要访问I2C的寄存器，首先需要先关闭I2C */ + + /* 设置波特率为100K + * I2C的时钟源来源于IPG_CLK_ROOT=66Mhz + * IC2 时钟 = PERCLK_ROOT/dividison(IFDR寄存器) + * 设置寄存器IFDR,IFDR寄存器参考IMX6UL参考手册P1260页，表29-3， + * 根据表29-3里面的值，挑选出一个还是的分频数，比如本例程我们 + * 设置I2C的波特率为100K， 因此当分频值=66000000/100000=660. + * 在表29-3里面查找，没有660这个值，但是有640，因此就用640, + * 即寄存器IFDR的IC位设置为0X15 + */ + base->IFDR = 0X15 << 0; + + /* + * 设置寄存器I2CR，开启I2C + * bit[7] : 1 使能I2C,I2CR寄存器其他位其作用之前，此位必须最先置1 + */ + base->I2CR |= (1<<7); +} + +/* + * @description : 发送重新开始信号 + * @param - base : 要使用的IIC + * @param - addrss : 设备地址 + * @param - direction : 方向 + * @return : 0 正常 其他值 出错 + */ +unsigned char i2c_master_repeated_start(I2C_Type *base, unsigned char address, enum i2c_direction direction) +{ + /* I2C忙并且工作在从模式,跳出 */ + if(base->I2SR & (1 << 5) && (((base->I2CR) & (1 << 5)) == 0)) + return 1; + + /* + * 设置寄存器I2CR + * bit[4]: 1 发送 + * bit[2]: 1 产生重新开始信号 + */ + base->I2CR |= (1 << 4) | (1 << 2); + + /* + * 设置寄存器I2DR + * bit[7:0] : 要发送的数据，这里写入从设备地址 + * 参考资料:IMX6UL参考手册P1249 + */ + base->I2DR = ((unsigned int)address << 1) | ((direction == kI2C_Read)? 1 : 0); + + return 0; +} + +/* + * @description : 发送开始信号 + * @param - base : 要使用的IIC + * @param - addrss : 设备地址 + * @param - direction : 方向 + * @return : 0 正常 其他值 出错 + */ +unsigned char i2c_master_start(I2C_Type *base, unsigned char address, enum i2c_direction direction) +{ + if(base->I2SR & (1 << 5)) /* I2C忙 */ + return 1; + + /* + * 设置寄存器I2CR + * bit[5]: 1 主模式 + * bit[4]: 1 发送 + */ + base->I2CR |= (1 << 5) | (1 << 4); + + /* + * 设置寄存器I2DR + * bit[7:0] : 要发送的数据，这里写入从设备地址 + * 参考资料:IMX6UL参考手册P1249 + */ + base->I2DR = ((unsigned int)address << 1) | ((direction == kI2C_Read)? 1 : 0); + return 0; +} + +/* + * @description : 检查并清除错误 + * @param - base : 要使用的IIC + * @param - status : 状态 + * @return : 状态结果 + */ +unsigned char i2c_check_and_clear_error(I2C_Type *base, unsigned int status) +{ + /* 检查是否发生仲裁丢失错误 */ + if(status & (1<<4)) + { + base->I2SR &= ~(1<<4); /* 清除仲裁丢失错误位 */ + + base->I2CR &= ~(1 << 7); /* 先关闭I2C */ + base->I2CR |= (1 << 7); /* 重新打开I2C */ + return I2C_STATUS_ARBITRATIONLOST; + } + else if(status & (1 << 0)) /* 没有接收到从机的应答信号 */ + { + return I2C_STATUS_NAK; /* 返回NAK(No acknowledge) */ + } + return I2C_STATUS_OK; +} + +/* + * @description : 停止信号 + * @param - base : 要使用的IIC + * @param : 无 + * @return : 状态结果 + */ +unsigned char i2c_master_stop(I2C_Type *base) +{ + unsigned short timeout = 0xffff; + + /* + * 清除I2CR的bit[5:3]这三位 + */ + base->I2CR &= ~((1 << 5) | (1 << 4) | (1 << 3)); + + /* 等待忙结束 */ + while((base->I2SR & (1 << 5))) + { + timeout--; + if(timeout == 0) /* 超时跳出 */ + return I2C_STATUS_TIMEOUT; + } + return I2C_STATUS_OK; +} + +/* + * @description : 发送数据 + * @param - base : 要使用的IIC + * @param - buf : 要发送的数据 + * @param - size : 要发送的数据大小 + * @param - flags : 标志 + * @return : 无 + */ +void i2c_master_write(I2C_Type *base, const unsigned char *buf, unsigned int size) +{ + /* 等待传输完成 */ + while(!(base->I2SR & (1 << 7))); + + base->I2SR &= ~(1 << 1); /* 清除标志位 */ + base->I2CR |= 1 << 4; /* 发送数据 */ + + while(size--) + { + base->I2DR = *buf++; /* 将buf中的数据写入到I2DR寄存器 */ + + while(!(base->I2SR & (1 << 1))); /* 等待传输完成 */ + base->I2SR &= ~(1 << 1); /* 清除标志位 */ + + /* 检查ACK */ + if(i2c_check_and_clear_error(base, base->I2SR)) + break; + } + + base->I2SR &= ~(1 << 1); + i2c_master_stop(base); /* 发送停止信号 */ +} + +/* + * @description : 读取数据 + * @param - base : 要使用的IIC + * @param - buf : 读取到数据 + * @param - size : 要读取的数据大小 + * @return : 无 + */ +void i2c_master_read(I2C_Type *base, unsigned char *buf, unsigned int size) +{ + volatile uint8_t dummy = 0; + + dummy++; /* 防止编译报错 */ + + /* 等待传输完成 */ + while(!(base->I2SR & (1 << 7))); + + base->I2SR &= ~(1 << 1); /* 清除中断挂起位 */ + base->I2CR &= ~((1 << 4) | (1 << 3)); /* 接收数据 */ + + /* 如果只接收一个字节数据的话发送NACK信号 */ + if(size == 1) + base->I2CR |= (1 << 3); + + dummy = base->I2DR; /* 假读 */ + + while(size--) + { + while(!(base->I2SR & (1 << 1))); /* 等待传输完成 */ + base->I2SR &= ~(1 << 1); /* 清除标志位 */ + + if(size == 0) + { + i2c_master_stop(base); /* 发送停止信号 */ + } + + if(size == 1) + { + base->I2CR |= (1 << 3); + } + *buf++ = base->I2DR; + } +} + +/* + * @description : I2C数据传输，包括读和写 + * @param - base: 要使用的IIC + * @param - xfer: 传输结构体 + * @return : 传输结果,0 成功，其他值 失败; + */ +unsigned char i2c_master_transfer(I2C_Type *base, struct i2c_transfer *xfer) +{ + unsigned char ret = 0; + enum i2c_direction direction = xfer->direction; + + base->I2SR &= ~((1 << 1) | (1 << 4)); /* 清除标志位 */ + + /* 等待传输完成 */ + while(!((base->I2SR >> 7) & 0X1)){}; + + /* 如果是读的话，要先发送寄存器地址，所以要先将方向改为写 */ + if ((xfer->subaddressSize > 0) && (xfer->direction == kI2C_Read)) + { + direction = kI2C_Write; + } + + ret = i2c_master_start(base, xfer->slaveAddress, direction); /* 发送开始信号 */ + if(ret) + { + return ret; + } + + while(!(base->I2SR & (1 << 1))){}; /* 等待传输完成 */ + + ret = i2c_check_and_clear_error(base, base->I2SR); /* 检查是否出现传输错误 */ + if(ret) + { + i2c_master_stop(base); /* 发送出错，发送停止信号 */ + return ret; + } + + /* 发送寄存器地址 */ + if(xfer->subaddressSize) + { + do + { + base->I2SR &= ~(1 << 1); /* 清除标志位 */ + xfer->subaddressSize--; /* 地址长度减一 */ + + base->I2DR = ((xfer->subaddress) >> (8 * xfer->subaddressSize)); //向I2DR寄存器写入子地址 + + while(!(base->I2SR & (1 << 1))); /* 等待传输完成 */ + + /* 检查是否有错误发生 */ + ret = i2c_check_and_clear_error(base, base->I2SR); + if(ret) + { + i2c_master_stop(base); /* 发送停止信号 */ + return ret; + } + } while ((xfer->subaddressSize > 0) && (ret == I2C_STATUS_OK)); + + if(xfer->direction == kI2C_Read) /* 读取数据 */ + { + base->I2SR &= ~(1 << 1); /* 清除中断挂起位 */ + i2c_master_repeated_start(base, xfer->slaveAddress, kI2C_Read); /* 发送重复开始信号和从机地址 */ + while(!(base->I2SR & (1 << 1))){};/* 等待传输完成 */ + + /* 检查是否有错误发生 */ + ret = i2c_check_and_clear_error(base, base->I2SR); + if(ret) + { + ret = I2C_STATUS_ADDRNAK; + i2c_master_stop(base); /* 发送停止信号 */ + return ret; + } + + } + } + + + /* 发送数据 */ + if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0)) + { + i2c_master_write(base, xfer->data, xfer->dataSize); + } + + /* 读取数据 */ + if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0)) + { + i2c_master_read(base, xfer->data, xfer->dataSize); + } + return 0; +} + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/i2c/bsp_i2c.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/i2c/bsp_i2c.h new file mode 100644 index 00000000..75b90389 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/i2c/bsp_i2c.h @@ -0,0 +1,61 @@ +#ifndef _BSP_I2C_H +#define _BSP_I2C_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_i2c.c +作者 : 左忠凯 +版本 : V1.0 +描述 : IIC驱动文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/15 左忠凯创建 +***************************************************************/ +#include "bsp.h" + +/* 相关宏定义 */ +#define I2C_STATUS_OK (0) +#define I2C_STATUS_BUSY (1) +#define I2C_STATUS_IDLE (2) +#define I2C_STATUS_NAK (3) +#define I2C_STATUS_ARBITRATIONLOST (4) +#define I2C_STATUS_TIMEOUT (5) +#define I2C_STATUS_ADDRNAK (6) + + +/* + * I2C方向枚举类型 + */ +enum i2c_direction +{ + kI2C_Write = 0x0, /* 主机向从机写数据 */ + kI2C_Read = 0x1, /* 主机从从机读数据 */ +} ; + +/* + * 主机传输结构体 + */ +struct i2c_transfer +{ + unsigned char slaveAddress; /* 7位从机地址 */ + enum i2c_direction direction; /* 传输方向 */ + unsigned int subaddress; /* 寄存器地址 */ + unsigned char subaddressSize; /* 寄存器地址长度 */ + unsigned char *volatile data; /* 数据缓冲区 */ + volatile unsigned int dataSize; /* 数据缓冲区长度 */ +}; + + +/* + *函数声明 + */ +void i2c_init(I2C_Type *base); +unsigned char i2c_master_start(I2C_Type *base, unsigned char address, enum i2c_direction direction); +unsigned char i2c_master_repeated_start(I2C_Type *base, unsigned char address, enum i2c_direction direction); +unsigned char i2c_check_and_clear_error(I2C_Type *base, unsigned int status); +unsigned char i2c_master_stop(I2C_Type *base); +void i2c_master_write(I2C_Type *base, const unsigned char *buf, unsigned int size); +void i2c_master_read(I2C_Type *base, unsigned char *buf, unsigned int size); +unsigned char i2c_master_transfer(I2C_Type *base, struct i2c_transfer *xfer); + + +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/icm20608/bsp_icm20608.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/icm20608/bsp_icm20608.c new file mode 100644 index 00000000..90cdc5c3 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/icm20608/bsp_icm20608.c @@ -0,0 +1,241 @@ +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_icm20608.c +作者 : 左忠凯 +版本 : V1.0 +描述 : ICM20608驱动文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/3/26 左忠凯创建 +***************************************************************/ +#include "bsp_icm20608.h" +#include "bsp_delay.h" +#include "bsp_spi.h" +#include "printf.h" + +struct icm20608_dev_struc icm20608_dev; /* icm20608设备 */ + +/* + * @description : 初始化ICM20608 + * @param : 无 + * @return : 0 初始化成功，其他值 初始化失败 + */ +unsigned char icm20608_init(void) +{ + unsigned char regvalue; + gpio_pin_config_t cs_config; + + /* 1、ESPI3 IO初始化 + * ECSPI3_SCLK -> UART2_RXD + * ECSPI3_MISO -> UART2_RTS + * ECSPI3_MOSI -> UART2_CTS + */ + IOMUXC_SetPinMux(IOMUXC_UART2_RX_DATA_ECSPI3_SCLK, 0); + IOMUXC_SetPinMux(IOMUXC_UART2_CTS_B_ECSPI3_MOSI, 0); + IOMUXC_SetPinMux(IOMUXC_UART2_RTS_B_ECSPI3_MISO, 0); + + /* 配置SPI SCLK MISO MOSI IO属性 + *bit 16: 0 HYS关闭 + *bit [15:14]: 00 默认100K下拉 + *bit [13]: 0 keeper功能 + *bit [12]: 1 pull/keeper使能 + *bit [11]: 0 关闭开路输出 + *bit [7:6]: 10 速度100Mhz + *bit [5:3]: 110 驱动能力为R0/6 + *bit [0]: 1 高转换率 + */ + IOMUXC_SetPinConfig(IOMUXC_UART2_RX_DATA_ECSPI3_SCLK, 0x10B1); + IOMUXC_SetPinConfig(IOMUXC_UART2_CTS_B_ECSPI3_MOSI, 0x10B1); + IOMUXC_SetPinConfig(IOMUXC_UART2_RTS_B_ECSPI3_MISO, 0x10B1); + + + IOMUXC_SetPinMux(IOMUXC_UART2_TX_DATA_GPIO1_IO20, 0); + IOMUXC_SetPinConfig(IOMUXC_UART2_TX_DATA_GPIO1_IO20, 0X10B0); + cs_config.direction = kGPIO_DigitalOutput; + cs_config.outputLogic = 0; + gpio_init(GPIO1, 20, &cs_config); + + /* 2、初始化SPI */ + spi_init(ECSPI3); + + icm20608_write_reg(ICM20_PWR_MGMT_1, 0x80); /* 复位，复位后为0x40,睡眠模式 */ + delayms(50); + icm20608_write_reg(ICM20_PWR_MGMT_1, 0x01); /* 关闭睡眠，自动选择时钟 */ + delayms(50); + + regvalue = icm20608_read_reg(ICM20_WHO_AM_I); + printf("icm20608 id = %#X\r\n", regvalue); + if(regvalue != ICM20608G_ID && regvalue != ICM20608D_ID) + return 1; + + icm20608_write_reg(ICM20_SMPLRT_DIV, 0x00); /* 输出速率是内部采样率 */ + icm20608_write_reg(ICM20_GYRO_CONFIG, 0x18); /* 陀螺仪±2000dps量程 */ + icm20608_write_reg(ICM20_ACCEL_CONFIG, 0x18); /* 加速度计±16G量程 */ + icm20608_write_reg(ICM20_CONFIG, 0x04); /* 陀螺仪低通滤波BW=20Hz */ + icm20608_write_reg(ICM20_ACCEL_CONFIG2, 0x04); /* 加速度计低通滤波BW=21.2Hz */ + icm20608_write_reg(ICM20_PWR_MGMT_2, 0x00); /* 打开加速度计和陀螺仪所有轴 */ + icm20608_write_reg(ICM20_LP_MODE_CFG, 0x00); /* 关闭低功耗 */ + icm20608_write_reg(ICM20_FIFO_EN, 0x00); /* 关闭FIFO */ + return 0; +} + + +/* + * @description : 写ICM20608指定寄存器 + * @param - reg : 要读取的寄存器地址 + * @param - value: 要写入的值 + * @return : 无 + */ +void icm20608_write_reg(unsigned char reg, unsigned char value) +{ + /* ICM20608在使用SPI接口的时候寄存器地址 + * 只有低7位有效,寄存器地址最高位是读/写标志位 + * 读的时候要为1，写的时候要为0。 + */ + reg &= ~0X80; + + ICM20608_CSN(0); /* 使能SPI传输 */ + spich0_readwrite_byte(ECSPI3, reg); /* 发送寄存器地址 */ + spich0_readwrite_byte(ECSPI3, value); /* 发送要写入的值 */ + ICM20608_CSN(1); /* 禁止SPI传输 */ +} + +/* + * @description : 读取ICM20608寄存器值 + * @param - reg : 要读取的寄存器地址 + * @return : 读取到的寄存器值 + */ +unsigned char icm20608_read_reg(unsigned char reg) +{ + unsigned char reg_val; + + /* ICM20608在使用SPI接口的时候寄存器地址 + * 只有低7位有效,寄存器地址最高位是读/写标志位 + * 读的时候要为1，写的时候要为0。 + */ + reg |= 0x80; + + ICM20608_CSN(0); /* 使能SPI传输 */ + spich0_readwrite_byte(ECSPI3, reg); /* 发送寄存器地址 */ + reg_val = spich0_readwrite_byte(ECSPI3, 0XFF); /* 读取寄存器的值 */ + ICM20608_CSN(1); /* 禁止SPI传输 */ + return(reg_val); /* 返回读取到的寄存器值 */ +} + +/* + * @description : 读取ICM20608连续多个寄存器 + * @param - reg : 要读取的寄存器地址 + * @return : 读取到的寄存器值 + */ +void icm20608_read_len(unsigned char reg, unsigned char *buf, unsigned char len) +{ + unsigned char i; + + /* ICM20608在使用SPI接口的时候寄存器地址，只有低7位有效, + * 寄存器地址最高位是读/写标志位读的时候要为1，写的时候要为0。 + */ + reg |= 0x80; + + ICM20608_CSN(0); /* 使能SPI传输 */ + spich0_readwrite_byte(ECSPI3, reg); /* 发送寄存器地址 */ + for(i = 0; i < len; i++) /* 顺序读取寄存器的值 */ + { + buf[i] = spich0_readwrite_byte(ECSPI3, 0XFF); + } + ICM20608_CSN(1); /* 禁止SPI传输 */ +} + +/* + * @description : 获取陀螺仪的分辨率 + * @param : 无 + * @return : 获取到的分辨率 + */ +float icm20608_gyro_scaleget(void) +{ + unsigned char data; + float gyroscale; + + data = (icm20608_read_reg(ICM20_GYRO_CONFIG) >> 3) & 0X3; + switch(data) { + case 0: + gyroscale = 131; + break; + case 1: + gyroscale = 65.5; + break; + case 2: + gyroscale = 32.8; + break; + case 3: + gyroscale = 16.4; + break; + } + return gyroscale; +} + +/* + * @description : 获取加速度计的分辨率 + * @param : 无 + * @return : 获取到的分辨率 + */ +unsigned short icm20608_accel_scaleget(void) +{ + unsigned char data; + unsigned short accelscale; + + data = (icm20608_read_reg(ICM20_ACCEL_CONFIG) >> 3) & 0X3; + switch(data) { + case 0: + accelscale = 16384; + break; + case 1: + accelscale = 8192; + break; + case 2: + accelscale = 4096; + break; + case 3: + accelscale = 2048; + break; + } + return accelscale; +} + + +/* + * @description : 读取ICM20608的加速度、陀螺仪和温度原始值 + * @param : 无 + * @return : 无 + */ +void icm20608_getdata(void) +{ + float gyroscale; + unsigned short accescale; + unsigned char data[14]; + + icm20608_read_len(ICM20_ACCEL_XOUT_H, data, 14); + + gyroscale = icm20608_gyro_scaleget(); + accescale = icm20608_accel_scaleget(); + + icm20608_dev.accel_x_adc = (signed short)((data[0] << 8) | data[1]); + icm20608_dev.accel_y_adc = (signed short)((data[2] << 8) | data[3]); + icm20608_dev.accel_z_adc = (signed short)((data[4] << 8) | data[5]); + icm20608_dev.temp_adc = (signed short)((data[6] << 8) | data[7]); + icm20608_dev.gyro_x_adc = (signed short)((data[8] << 8) | data[9]); + icm20608_dev.gyro_y_adc = (signed short)((data[10] << 8) | data[11]); + icm20608_dev.gyro_z_adc = (signed short)((data[12] << 8) | data[13]); + + /* 计算实际值 */ + icm20608_dev.gyro_x_act = ((float)(icm20608_dev.gyro_x_adc) / gyroscale) * 100; + icm20608_dev.gyro_y_act = ((float)(icm20608_dev.gyro_y_adc) / gyroscale) * 100; + icm20608_dev.gyro_z_act = ((float)(icm20608_dev.gyro_z_adc) / gyroscale) * 100; + + icm20608_dev.accel_x_act = ((float)(icm20608_dev.accel_x_adc) / accescale) * 100; + icm20608_dev.accel_y_act = ((float)(icm20608_dev.accel_y_adc) / accescale) * 100; + icm20608_dev.accel_z_act = ((float)(icm20608_dev.accel_z_adc) / accescale) * 100; + + icm20608_dev.temp_act = (((float)(icm20608_dev.temp_adc) - 25 ) / 326.8 + 25) * 100; +} + + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/icm20608/bsp_icm20608.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/icm20608/bsp_icm20608.h new file mode 100644 index 00000000..a37a9cba --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/icm20608/bsp_icm20608.h @@ -0,0 +1,131 @@ +#ifndef _BSP_ICM20608_H +#define _BSP_ICM20608_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_icm20608.h +作者 : 左忠凯 +版本 : V1.0 +描述 : ICM20608驱动文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/3/26 左忠凯创建 +***************************************************************/ +#include "bsp.h" +#include "bsp_gpio.h" + + +/* 宏定义 */ +#define ICM20608_CSN(n) (n ? gpio_pinwrite(GPIO1, 20, 1) : gpio_pinwrite(GPIO1, 20, 0)) /* SPI片选信号 */ + +#define ICM20608G_ID 0XAF /* ID值 */ +#define ICM20608D_ID 0XAE /* ID值 */ + +/* ICM20608寄存器 + *复位后所有寄存器地址都为0，除了 + *Register 107(0X6B) Power Management 1 = 0x40 + *Register 117(0X75) WHO_AM_I = 0xAF或0xAE + */ +/* 陀螺仪和加速度自测(出产时设置，用于与用户的自检输出值比较） */ +#define ICM20_SELF_TEST_X_GYRO 0x00 +#define ICM20_SELF_TEST_Y_GYRO 0x01 +#define ICM20_SELF_TEST_Z_GYRO 0x02 +#define ICM20_SELF_TEST_X_ACCEL 0x0D +#define ICM20_SELF_TEST_Y_ACCEL 0x0E +#define ICM20_SELF_TEST_Z_ACCEL 0x0F + +/* 陀螺仪静态偏移 */ +#define ICM20_XG_OFFS_USRH 0x13 +#define ICM20_XG_OFFS_USRL 0x14 +#define ICM20_YG_OFFS_USRH 0x15 +#define ICM20_YG_OFFS_USRL 0x16 +#define ICM20_ZG_OFFS_USRH 0x17 +#define ICM20_ZG_OFFS_USRL 0x18 + +#define ICM20_SMPLRT_DIV 0x19 +#define ICM20_CONFIG 0x1A +#define ICM20_GYRO_CONFIG 0x1B +#define ICM20_ACCEL_CONFIG 0x1C +#define ICM20_ACCEL_CONFIG2 0x1D +#define ICM20_LP_MODE_CFG 0x1E +#define ICM20_ACCEL_WOM_THR 0x1F +#define ICM20_FIFO_EN 0x23 +#define ICM20_FSYNC_INT 0x36 +#define ICM20_INT_PIN_CFG 0x37 +#define ICM20_INT_ENABLE 0x38 +#define ICM20_INT_STATUS 0x3A + +/* 加速度输出 */ +#define ICM20_ACCEL_XOUT_H 0x3B +#define ICM20_ACCEL_XOUT_L 0x3C +#define ICM20_ACCEL_YOUT_H 0x3D +#define ICM20_ACCEL_YOUT_L 0x3E +#define ICM20_ACCEL_ZOUT_H 0x3F +#define ICM20_ACCEL_ZOUT_L 0x40 + +/* 温度输出 */ +#define ICM20_TEMP_OUT_H 0x41 +#define ICM20_TEMP_OUT_L 0x42 + +/* 陀螺仪输出 */ +#define ICM20_GYRO_XOUT_H 0x43 +#define ICM20_GYRO_XOUT_L 0x44 +#define ICM20_GYRO_YOUT_H 0x45 +#define ICM20_GYRO_YOUT_L 0x46 +#define ICM20_GYRO_ZOUT_H 0x47 +#define ICM20_GYRO_ZOUT_L 0x48 + +#define ICM20_SIGNAL_PATH_RESET 0x68 +#define ICM20_ACCEL_INTEL_CTRL 0x69 +#define ICM20_USER_CTRL 0x6A +#define ICM20_PWR_MGMT_1 0x6B +#define ICM20_PWR_MGMT_2 0x6C +#define ICM20_FIFO_COUNTH 0x72 +#define ICM20_FIFO_COUNTL 0x73 +#define ICM20_FIFO_R_W 0x74 +#define ICM20_WHO_AM_I 0x75 + +/* 加速度静态偏移 */ +#define ICM20_XA_OFFSET_H 0x77 +#define ICM20_XA_OFFSET_L 0x78 +#define ICM20_YA_OFFSET_H 0x7A +#define ICM20_YA_OFFSET_L 0x7B +#define ICM20_ZA_OFFSET_H 0x7D +#define ICM20_ZA_OFFSET_L 0x7E + +/* + * ICM20608结构体 + */ +struct icm20608_dev_struc +{ + signed int gyro_x_adc; /* 陀螺仪X轴原始值 */ + signed int gyro_y_adc; /* 陀螺仪Y轴原始值 */ + signed int gyro_z_adc; /* 陀螺仪Z轴原始值 */ + signed int accel_x_adc; /* 加速度计X轴原始值 */ + signed int accel_y_adc; /* 加速度计Y轴原始值 */ + signed int accel_z_adc; /* 加速度计Z轴原始值 */ + signed int temp_adc; /* 温度原始值 */ + + /* 下面是计算得到的实际值，扩大100倍 */ + signed int gyro_x_act; /* 陀螺仪X轴实际值 */ + signed int gyro_y_act; /* 陀螺仪Y轴实际值 */ + signed int gyro_z_act; /* 陀螺仪Z轴实际值 */ + signed int accel_x_act; /* 加速度计X轴实际值 */ + signed int accel_y_act; /* 加速度计Y轴实际值 */ + signed int accel_z_act; /* 加速度计Z轴实际值 */ + signed int temp_act; /* 温度实际值 */ +}; + +struct icm20608_dev_struc icm20608_dev; /* icm20608设备 */ + + +/* 函数声明 */ +unsigned char icm20608_init(void); +void icm20608_write_reg(unsigned char reg, unsigned char value); +unsigned char icm20608_read_reg(unsigned char reg); +void icm20608_read_len(unsigned char reg, unsigned char *buf, unsigned char len); +void icm20608_getdata(void); + + +#endif + + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/int/bsp_int.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/int/bsp_int.c new file mode 100644 index 00000000..d273179b --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/int/bsp_int.c @@ -0,0 +1,102 @@ +#include "bsp_int.h" +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_int.c +作者 : 左忠凯 +版本 : V1.0 +描述 : 中断驱动文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯创建 +***************************************************************/ + +/* 中断嵌套计数器 */ +static unsigned int irqNesting; + +/* 中断服务函数表 */ +static sys_irq_handle_t irqTable[NUMBER_OF_INT_VECTORS]; + +/* + * @description : 中断初始化函数 + * @param : 无 + * @return : 无 + */ +void int_init(void) +{ + GIC_Init(); /* 初始化GIC */ + system_irqtable_init(); /* 初始化中断表 */ + __set_VBAR((uint32_t)0x87800000); /* 中断向量表偏移，偏移到起始地址 */ +} + +/* + * @description : 初始化中断服务函数表 + * @param : 无 + * @return : 无 + */ +void system_irqtable_init(void) +{ + unsigned int i = 0; + irqNesting = 0; + + /* 先将所有的中断服务函数设置为默认值 */ + for(i = 0; i < NUMBER_OF_INT_VECTORS; i++) + { + system_register_irqhandler((IRQn_Type)i,default_irqhandler, NULL); + } +} + +/* + * @description : 给指定的中断号注册中断服务函数 + * @param - irq : 要注册的中断号 + * @param - handler : 要注册的中断处理函数 + * @param - usrParam : 中断服务处理函数参数 + * @return : 无 + */ +void system_register_irqhandler(IRQn_Type irq, system_irq_handler_t handler, void *userParam) +{ + irqTable[irq].irqHandler = handler; + irqTable[irq].userParam = userParam; +} + +/* + * @description : C语言中断服务函数，irq汇编中断服务函数会 + 调用此函数，此函数通过在中断服务列表中查 + 找指定中断号所对应的中断处理函数并执行。 + * @param - giccIar : 中断号 + * @return : 无 + */ +void system_irqhandler(unsigned int giccIar) +{ + + uint32_t intNum = giccIar & 0x3FFUL; + + /* 检查中断号是否符合要求 */ + if ((intNum == 1023) || (intNum >= NUMBER_OF_INT_VECTORS)) + { + return; + } + + irqNesting++; /* 中断嵌套计数器加一 */ + + /* 根据传递进来的中断号，在irqTable中调用确定的中断服务函数*/ + irqTable[intNum].irqHandler(intNum, irqTable[intNum].userParam); + + irqNesting--; /* 中断执行完成，中断嵌套寄存器减一 */ + +} + +/* + * @description : 默认中断服务函数 + * @param - giccIar : 中断号 + * @param - usrParam : 中断服务处理函数参数 + * @return : 无 + */ +void default_irqhandler(unsigned int giccIar, void *userParam) +{ + while(1) + { + } +} + + + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/int/bsp_int.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/int/bsp_int.h new file mode 100644 index 00000000..7bf58908 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/int/bsp_int.h @@ -0,0 +1,36 @@ +#ifndef _BSP_INT_H +#define _BSP_INT_H +#include "bsp.h" +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_int.c +作者 : 左忠凯 +版本 : V1.0 +描述 : 中断驱动头文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯创建 +***************************************************************/ + +/* 中断服务函数形式 */ +typedef void (*system_irq_handler_t) (unsigned int giccIar, void *param); + + +/* 中断服务函数结构体*/ +typedef struct _sys_irq_handle +{ + system_irq_handler_t irqHandler; /* 中断服务函数 */ + void *userParam; /* 中断服务函数参数 */ +} sys_irq_handle_t; + + +/* 函数声明 */ +void int_init(void); +void system_irqtable_init(void); +void system_register_irqhandler(IRQn_Type irq, system_irq_handler_t handler, void *userParam); +void system_irqhandler(unsigned int giccIar); +void default_irqhandler(unsigned int giccIar, void *userParam); + + + +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/key/bsp_key.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/key/bsp_key.c new file mode 100644 index 00000000..dc098cce --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/key/bsp_key.c @@ -0,0 +1,70 @@ +#include "bsp_key.h" +#include "bsp_gpio.h" +#include "bsp_delay.h" +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_key.h +作者 : 左忠凯 +版本 : V1.0 +描述 : 按键驱动文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯创建 +***************************************************************/ + +/* + * @description : 初始化按键 + * @param : 无 + * @return : 无 + */ +void key_init(void) +{ + gpio_pin_config_t key_config; + + /* 1、初始化IO复用, 复用为GPIO1_IO18 */ + IOMUXC_SetPinMux(IOMUXC_UART1_CTS_B_GPIO1_IO18,0); + + /* 2、、配置UART1_CTS_B的IO属性 + *bit 16:0 HYS关闭 + *bit [15:14]: 11 默认22K上拉 + *bit [13]: 1 pull功能 + *bit [12]: 1 pull/keeper使能 + *bit [11]: 0 关闭开路输出 + *bit [7:6]: 10 速度100Mhz + *bit [5:3]: 000 关闭输出 + *bit [0]: 0 低转换率 + */ + IOMUXC_SetPinConfig(IOMUXC_UART1_CTS_B_GPIO1_IO18,0xF080); + + /* 3、初始化GPIO */ + //GPIO1->GDIR &= ~(1 << 18); /* GPIO1_IO18设置为输入 */ + key_config.direction = kGPIO_DigitalInput; + gpio_init(GPIO1,18, &key_config); + +} + +/* + * @description : 获取按键值 + * @param : 无 + * @return : 0 没有按键按下，其他值:对应的按键值 + */ +int key_getvalue(void) +{ + int ret = 0; + static unsigned char release = 1; /* 按键松开 */ + + if((release==1)&&(gpio_pinread(GPIO1, 18) == 0)) /* KEY0 */ + { + delay(10); /* 延时消抖 */ + release = 0; /* 标记按键按下 */ + if(gpio_pinread(GPIO1, 18) == 0) + ret = KEY0_VALUE; + } + else if(gpio_pinread(GPIO1, 18) == 1) + { + ret = 0; + release = 1; /* 标记按键释放 */ + } + + return ret; +} diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/key/bsp_key.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/key/bsp_key.h new file mode 100644 index 00000000..4c1198e7 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/key/bsp_key.h @@ -0,0 +1,29 @@ +#ifndef _BSP_KEY_H +#define _BSP_KEY_H +#include "bsp.h" +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_key.h +作者 : 左忠凯 +版本 : V1.0 +描述 : 按键驱动头文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯创建 +***************************************************************/ + + +/* 定义按键值 */ +enum keyvalue{ + KEY_NONE = 0, + KEY0_VALUE, + KEY1_VALUE, + KEY2_VALUE, +}; + +/* 函数声明 */ +void key_init(void); +int key_getvalue(void); + + +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/keyfilter/bsp_keyfilter.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/keyfilter/bsp_keyfilter.c new file mode 100644 index 00000000..320f7060 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/keyfilter/bsp_keyfilter.c @@ -0,0 +1,152 @@ +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_keyfilter.c +作者 : 左忠凯 +版本 : V1.0 +描述 : 定时器按键消抖驱动。 +其他 : 按键采用中断方式，按下按键触发按键中断，在按键中断里面 + 使能定时器定时中断。使用定时器定时中断来完成消抖延时， + 定时器中断周期就是延时时间。如果定时器定时中断触发， + 表示消抖完成(延时周期完成)，即可执行按键处理函数。 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/5 左忠凯创建 +***************************************************************/ +#include "bsp_key.h" +#include "bsp_gpio.h" +#include "bsp_int.h" +#include "bsp_beep.h" +#include "bsp_keyfilter.h" + +/* + * @description : 按键初始化 + * @param : 无 + * @return : 无 + */ +void filterkey_init(void) +{ + gpio_pin_config_t key_config; + + /* 1、初始化IO复用 */ + IOMUXC_SetPinMux(IOMUXC_UART1_CTS_B_GPIO1_IO18,0); /* 复用为GPIO1_IO18 */ + + /* 2、、配置GPIO1_IO18的IO属性 + *bit 16:0 HYS关闭 + *bit [15:14]: 11 默认22K上拉 + *bit [13]: 1 pull功能 + *bit [12]: 1 pull/keeper使能 + *bit [11]: 0 关闭开路输出 + *bit [7:6]: 10 速度100Mhz + *bit [5:3]: 000 关闭输出 + *bit [0]: 0 低转换率 + */ + IOMUXC_SetPinConfig(IOMUXC_UART1_CTS_B_GPIO1_IO18,0xF080); + + /* 3、初始化GPIO为中断 */ + key_config.direction = kGPIO_DigitalInput; + key_config.interruptMode = kGPIO_IntFallingEdge; + key_config.outputLogic = 1; + gpio_init(GPIO1, 18, &key_config); + + GIC_EnableIRQ(GPIO1_Combined_16_31_IRQn); /* 使能GIC中对应的中断 */ + + /* 注册中断服务函数 */ + system_register_irqhandler(GPIO1_Combined_16_31_IRQn, + (system_irq_handler_t)gpio1_16_31_irqhandler, + NULL); + + gpio_enableint(GPIO1, 18); /* 使能GPIO1_IO18的中断功能 */ + + filtertimer_init(66000000/100); /* 初始化定时器,10ms */ +} + + +/* + * @description : 初始化用于消抖的定时器，默认关闭定时器 + * @param - value : 定时器EPIT计数值 + * @return : 无 + */ +void filtertimer_init(unsigned int value) +{ + EPIT1->CR = 0; //先清零 + + /* + * CR寄存器: + * bit25:24 01 时钟源选择Peripheral clock=66MHz + * bit15:4 0 1分频 + * bit3: 1 当计数器到0的话从LR重新加载数值 + * bit2: 1 比较中断使能 + * bit1: 1 初始计数值来源于LR寄存器值 + * bit0: 0 先关闭EPIT1 + */ + EPIT1->CR = (1<<24 | 1<<3 | 1<<2 | 1<<1); + + /* 计数值 */ + EPIT1->LR = value; + + /* 比较寄存器，当计数器值和此寄存器值相等的话就会产生中断 */ + EPIT1->CMPR = 0; + + GIC_EnableIRQ(EPIT1_IRQn); /* 使能GIC中对应的中断 */ + + /* 注册中断服务函数 */ + system_register_irqhandler(EPIT1_IRQn, (system_irq_handler_t)filtertimer_irqhandler, NULL); +} + +/* + * @description : 关闭定时器 + * @param : 无 + * @return : 无 + */ +void filtertimer_stop(void) +{ + EPIT1->CR &= ~(1<<0); /* 关闭定时器 */ +} + +/* + * @description : 重启定时器 + * @param - value : 定时器EPIT计数值 + * @return : 无 + */ +void filtertimer_restart(unsigned int value) +{ + EPIT1->CR &= ~(1<<0); /* 先关闭定时器 */ + EPIT1->LR = value; /* 计数值 */ + EPIT1->CR |= (1<<0); /* 打开定时器 */ +} + +/* + * @description : 定时器中断处理函数 + * @param : 无 + * @return : 无 + */ +void filtertimer_irqhandler(void) +{ + static unsigned char state = OFF; + + if(EPIT1->SR & (1<<0)) /* 判断比较事件是否发生 */ + { + filtertimer_stop(); /* 关闭定时器 */ + if(gpio_pinread(GPIO1, 18) == 0) /* KEY0 */ + { + state = !state; + beep_switch(state); /* 反转蜂鸣器 */ + } + } + + EPIT1->SR |= 1<<0; /* 清除中断标志位 */ +} + +/* + * @description : GPIO中断处理函数 + * @param : 无 + * @return : 无 + */ +void gpio1_16_31_irqhandler(void) +{ + /* 开启定时器 */ + filtertimer_restart(66000000/100); + + /* 清除中断标志位 */ + gpio_clearintflags(GPIO1, 18); +} + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/keyfilter/bsp_keyfilter.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/keyfilter/bsp_keyfilter.h new file mode 100644 index 00000000..0a3492ff --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/keyfilter/bsp_keyfilter.h @@ -0,0 +1,23 @@ +#ifndef _BSP_KEYFILTER_H +#define _BSP_KEYFILTER_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_keyfilter.c +作者 : 左忠凯 +版本 : V1.0 +描述 : 定时器按键消抖驱动头文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/5 左忠凯创建 +***************************************************************/ + + +/* 函数声明 */ +void filterkey_init(void); +void filtertimer_init(unsigned int value); +void filtertimer_stop(void); +void filtertimer_restart(unsigned int value); +void filtertimer_irqhandler(void); +void gpio1_16_31_irqhandler(void); + +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/lcd/bsp_lcd.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/lcd/bsp_lcd.c new file mode 100644 index 00000000..67e41707 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/lcd/bsp_lcd.c @@ -0,0 +1,413 @@ +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_lcd.c +作者 : 左忠凯 +版本 : V1.0 +描述 : LCD驱动文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/3 左忠凯创建 +***************************************************************/ +#include "bsp_lcd.h" +#include "bsp_gpio.h" +#include "bsp_delay.h" +#include "printf.h" + +/* 液晶屏参数结构体 */ +struct tftlcd_typedef tftlcd_dev; + +/* + * @description : 始化LCD + * @param : 无 + * @return : 无 + */ +void lcd_init(void) +{ + lcdgpio_init(); /* 初始化IO */ + lcdclk_init(32, 3, 5); /* 初始化LCD时钟 */ + + lcd_reset(); /* 复位LCD */ + delayms(10); /* 延时10ms */ + lcd_noreset(); /* 结束复位 */ + + /* TFTLCD参数结构体初始化 */ + tftlcd_dev.height = 600; + tftlcd_dev.width = 1024; + tftlcd_dev.pixsize = 4; /* ARGB8888模式，每个像素4字节 */ + tftlcd_dev.vspw = 3; + tftlcd_dev.vbpd = 20; + tftlcd_dev.vfpd = 12; + tftlcd_dev.hspw = 20; + tftlcd_dev.hbpd = 140; + tftlcd_dev.hfpd = 160; + tftlcd_dev.framebuffer = LCD_FRAMEBUF_ADDR; + tftlcd_dev.backcolor = LCD_WHITE; /* 背景色为白色 */ + tftlcd_dev.forecolor = LCD_BLACK; /* 前景色为黑色 */ + + /* 初始化ELCDIF的CTRL寄存器 + * bit [31] 0 : 停止复位 + * bit [19] 1 : 旁路计数器模式 + * bit [17] 1 : LCD工作在dotclk模式 + * bit [15:14] 00 : 输入数据不交换 + * bit [13:12] 00 : CSC不交换 + * bit [11:10] 11 : 24位总线宽度 + * bit [9:8] 11 : 24位数据宽度,也就是RGB888 + * bit [5] 1 : elcdif工作在主模式 + * bit [1] 0 : 所有的24位均有效 + */ + LCDIF->CTRL |= (1 << 19) | (1 << 17) | (0 << 14) | (0 << 12) | + (3 << 10) | (3 << 8) | (1 << 5) | (0 << 1); + /* + * 初始化ELCDIF的寄存器CTRL1 + * bit [19:16] : 0X7 ARGB模式下，传输24位数据，A通道不用传输 + */ + LCDIF->CTRL1 = 0X7 << 16; + + /* + * 初始化ELCDIF的寄存器TRANSFER_COUNT寄存器 + * bit [31:16] : 高度 + * bit [15:0] : 宽度 + */ + LCDIF->TRANSFER_COUNT = (tftlcd_dev.height << 16) | (tftlcd_dev.width << 0); + + /* + * 初始化ELCDIF的VDCTRL0寄存器 + * bit [29] 0 : VSYNC输出 + * bit [28] 1 : 使能ENABLE输出 + * bit [27] 0 : VSYNC低电平有效 + * bit [26] 0 : HSYNC低电平有效 + * bit [25] 0 : DOTCLK上升沿有效 + * bit [24] 1 : ENABLE信号高电平有效 + * bit [21] 1 : DOTCLK模式下设置为1 + * bit [20] 1 : DOTCLK模式下设置为1 + * bit [17:0] : vsw参数 + */ + LCDIF->VDCTRL0 = 0; //先清零 + LCDIF->VDCTRL0 = (0 << 29) | (1 << 28) | (0 << 27) | + (0 << 26) | (0 << 25) | (1 << 24) | + (1 << 21) | (1 << 20) | (tftlcd_dev.vspw << 0); + /* + * 初始化ELCDIF的VDCTRL1寄存器 + * 设置VSYNC总周期 + */ + LCDIF->VDCTRL1 = tftlcd_dev.height + tftlcd_dev.vspw + tftlcd_dev.vfpd + tftlcd_dev.vbpd; //VSYNC周期 + + /* + * 初始化ELCDIF的VDCTRL2寄存器 + * 设置HSYNC周期 + * bit[31:18] ：hsw + * bit[17:0] : HSYNC总周期 + */ + LCDIF->VDCTRL2 = (tftlcd_dev.hspw << 18) | (tftlcd_dev.width + tftlcd_dev.hspw + tftlcd_dev.hfpd + tftlcd_dev.hbpd); + + /* + * 初始化ELCDIF的VDCTRL3寄存器 + * 设置HSYNC周期 + * bit[27:16] ：水平等待时钟数 + * bit[15:0] : 垂直等待时钟数 + */ + LCDIF->VDCTRL3 = ((tftlcd_dev.hbpd + tftlcd_dev.hspw) << 16) | (tftlcd_dev.vbpd + tftlcd_dev.vspw); + + /* + * 初始化ELCDIF的VDCTRL4寄存器 + * 设置HSYNC周期 + * bit[18] 1 : 当使用VSHYNC、HSYNC、DOTCLK的话此为置1 + * bit[17:0] : 宽度 + */ + + LCDIF->VDCTRL4 = (1<<18) | (tftlcd_dev.width); + + /* + * 初始化ELCDIF的CUR_BUF和NEXT_BUF寄存器 + * 设置当前显存地址和下一帧的显存地址 + */ + LCDIF->CUR_BUF = (unsigned int)tftlcd_dev.framebuffer; + LCDIF->NEXT_BUF = (unsigned int)tftlcd_dev.framebuffer; + + + lcd_enable(); /* 使能LCD */ + delayms(10); + lcd_clear(LCD_WHITE); /* 清屏 */ + +} + +/* + * IO引脚: LCD_DATA00 -> LCD_B0 + * LCD_DATA01 -> LCD_B1 + * LCD_DATA02 -> LCD_B2 + * LCD_DATA03 -> LCD_B3 + * LCD_DATA04 -> LCD_B4 + * LCD_DATA05 -> LCD_B5 + * LCD_DATA06 -> LCD_B6 + * LCD_DATA07 -> LCD_B7 + * + * LCD_DATA08 -> LCD_G0 + * LCD_DATA09 -> LCD_G1 + * LCD_DATA010 -> LCD_G2 + * LCD_DATA011 -> LCD_G3 + * LCD_DATA012 -> LCD_G4 + * LCD_DATA012 -> LCD_G4 + * LCD_DATA013 -> LCD_G5 + * LCD_DATA014 -> LCD_G6 + * LCD_DATA015 -> LCD_G7 + * + * LCD_DATA016 -> LCD_R0 + * LCD_DATA017 -> LCD_R1 + * LCD_DATA018 -> LCD_R2 + * LCD_DATA019 -> LCD_R3 + * LCD_DATA020 -> LCD_R4 + * LCD_DATA021 -> LCD_R5 + * LCD_DATA022 -> LCD_R6 + * LCD_DATA023 -> LCD_R7 + * + * LCD_CLK -> LCD_CLK + * LCD_VSYNC -> LCD_VSYNC + * LCD_HSYNC -> LCD_HSYNC + * LCD_DE -> LCD_DE + * LCD_BL -> GPIO1_IO08 + */ + +/* + * @description : LCD GPIO初始化 + * @param : 无 + * @return : 无 + */ +void lcdgpio_init(void) +{ + gpio_pin_config_t gpio_config; + + + /* 1、IO初始化复用功能 */ + IOMUXC_SetPinMux(IOMUXC_LCD_DATA00_LCDIF_DATA00,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA01_LCDIF_DATA01,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA02_LCDIF_DATA02,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA03_LCDIF_DATA03,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA04_LCDIF_DATA04,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA05_LCDIF_DATA05,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA06_LCDIF_DATA06,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA07_LCDIF_DATA07,0); + + IOMUXC_SetPinMux(IOMUXC_LCD_DATA08_LCDIF_DATA08,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA09_LCDIF_DATA09,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA10_LCDIF_DATA10,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA11_LCDIF_DATA11,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA12_LCDIF_DATA12,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA13_LCDIF_DATA13,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA14_LCDIF_DATA14,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA15_LCDIF_DATA15,0); + + IOMUXC_SetPinMux(IOMUXC_LCD_DATA16_LCDIF_DATA16,0); + +IOMUXC_SetPinMux(IOMUXC_LCD_DATA17_LCDIF_DATA17,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA18_LCDIF_DATA18,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA19_LCDIF_DATA19,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA20_LCDIF_DATA20,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA21_LCDIF_DATA21,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA22_LCDIF_DATA22,0); + IOMUXC_SetPinMux(IOMUXC_LCD_DATA23_LCDIF_DATA23,0); + + IOMUXC_SetPinMux(IOMUXC_LCD_CLK_LCDIF_CLK,0); + IOMUXC_SetPinMux(IOMUXC_LCD_ENABLE_LCDIF_ENABLE,0); + IOMUXC_SetPinMux(IOMUXC_LCD_HSYNC_LCDIF_HSYNC,0); + IOMUXC_SetPinMux(IOMUXC_LCD_VSYNC_LCDIF_VSYNC,0); + + IOMUXC_SetPinMux(IOMUXC_GPIO1_IO08_GPIO1_IO08,0); /* 背光BL引脚 */ + + /* 2、配置LCD IO属性 + *bit 16:0 HYS关闭 + *bit [15:14]: 0 默认22K上拉 + *bit [13]: 0 pull功能 + *bit [12]: 0 pull/keeper使能 + *bit [11]: 0 关闭开路输出 + *bit [7:6]: 10 速度100Mhz + *bit [5:3]: 111 驱动能力为R0/7 + *bit [0]: 1 高转换率 + */ + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA00_LCDIF_DATA00,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA01_LCDIF_DATA01,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA02_LCDIF_DATA02,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA03_LCDIF_DATA03,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA04_LCDIF_DATA04,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA05_LCDIF_DATA05,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA06_LCDIF_DATA06,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA07_LCDIF_DATA07,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA08_LCDIF_DATA08,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA09_LCDIF_DATA09,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA10_LCDIF_DATA10,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA11_LCDIF_DATA11,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA12_LCDIF_DATA12,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA13_LCDIF_DATA13,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA14_LCDIF_DATA14,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA15_LCDIF_DATA15,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA16_LCDIF_DATA16,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA17_LCDIF_DATA17,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA18_LCDIF_DATA18,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA19_LCDIF_DATA19,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA20_LCDIF_DATA20,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA21_LCDIF_DATA21,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA22_LCDIF_DATA22,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_DATA23_LCDIF_DATA23,0xB9); + + IOMUXC_SetPinConfig(IOMUXC_LCD_CLK_LCDIF_CLK,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_ENABLE_LCDIF_ENABLE,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_HSYNC_LCDIF_HSYNC,0xB9); + IOMUXC_SetPinConfig(IOMUXC_LCD_VSYNC_LCDIF_VSYNC,0xB9); + + IOMUXC_SetPinConfig(IOMUXC_GPIO1_IO08_GPIO1_IO08,0xB9); /* 背光BL引脚 */ + + /* GPIO初始化 */ + gpio_config.direction = kGPIO_DigitalOutput; /* 输出 */ + gpio_config.outputLogic = 1; /* 默认关闭背光 */ + gpio_init(GPIO1, 8, &gpio_config); /* 背光默认打开 */ + gpio_pinwrite(GPIO1, 8, 1); /* 打开背光 */ +} + +/* + * @description : LCD时钟初始化, LCD时钟计算公式如下： + * LCD CLK = 24 * loopDiv / prediv / div + * @param - loopDiv : loopDivider值 + * @param - loopDiv : lcdifprediv值 + * @param - div : lcdifdiv值 + * @return : 无 + */ +void lcdclk_init(unsigned char loopDiv, unsigned char prediv, unsigned char div) +{ + /* 先初始化video pll + * VIDEO PLL = OSC24M * (loopDivider + (denominator / numerator)) / postDivider + *不使用小数分频器，因此denominator和numerator设置为0 + */ + CCM_ANALOG->PLL_VIDEO_NUM = 0; /* 不使用小数分频器 */ + CCM_ANALOG->PLL_VIDEO_DENOM = 0; + + /* + * PLL_VIDEO寄存器设置 + * bit[13]: 1 使能VIDEO PLL时钟 + * bit[20:19] 2 设置postDivider为1分频 + * bit[6:0] : 32 设置loopDivider寄存器 + */ + CCM_ANALOG->PLL_VIDEO = (2 << 19) | (1 << 13) | (loopDiv << 0); + + /* + * MISC2寄存器设置 + * bit[31:30]: 0 VIDEO的post-div设置，时钟源来源于postDivider，1分频 + */ + CCM_ANALOG->MISC2 &= ~(3 << 30); + CCM_ANALOG->MISC2 = 0 << 30; + + /* LCD时钟源来源与PLL5，也就是VIDEO PLL */ + CCM->CSCDR2 &= ~(7 << 15); + CCM->CSCDR2 |= (2 << 15); /* 设置LCDIF_PRE_CLK使用PLL5 */ + + /* 设置LCDIF_PRE分频 */ + CCM->CSCDR2 &= ~(7 << 12); + CCM->CSCDR2 |= (prediv - 1) << 12; /* 设置分频 */ + + /* 设置LCDIF分频 */ + CCM->CBCMR &= ~(7 << 23); + CCM->CBCMR |= (div - 1) << 23; + + /* 设置LCD时钟源为LCDIF_PRE时钟 */ + CCM->CSCDR2 &= ~(7 << 9); /* 清除原来的设置 */ + CCM->CSCDR2 |= (0 << 9); /* LCDIF_PRE时钟源选择LCDIF_PRE时钟 */ +} + +/* + * @description : 复位ELCDIF接口 + * @param : 无 + * @return : 无 + */ +void lcd_reset(void) +{ + LCDIF->CTRL = 1<<31; /* 强制复位 */ +} + +/* + * @description : 结束复位ELCDIF接口 + * @param : 无 + * @return : 无 + */ +void lcd_noreset(void) +{ + LCDIF->CTRL = 0<<31; /* 取消强制复位 */ +} + +/* + * @description : 使能ELCDIF接口 + * @param : 无 + * @return : 无 + */ +void lcd_enable(void) +{ + LCDIF->CTRL |= 1<<0; /* 使能ELCDIF */ +} + +/* + * @description : 画点函数 + * @param - x : x轴坐标 + * @param - y : y轴坐标 + * @param - color : 颜色值 + * @return : 无 + */ +void lcd_drawpoint(unsigned short x,unsigned short y,unsigned int color) +{ + *(unsigned int*)((unsigned int)tftlcd_dev.framebuffer + + tftlcd_dev.pixsize * (tftlcd_dev.width * y+x))=color; +} + + +/* + * @description : 读取指定点的颜色值 + * @param - x : x轴坐标 + * @param - y : y轴坐标 + * @return : 读取到的指定点的颜色值 + */ +inline unsigned int lcd_readpoint(unsigned short x,unsigned short y) +{ + return *(unsigned int*)((unsigned int)tftlcd_dev.framebuffer + + tftlcd_dev.pixsize * (tftlcd_dev.width * y + x)); +} + +/* + * @description : 清屏 + * @param - color : 颜色值 + * @return : 读取到的指定点的颜色值 + */ +void lcd_clear(unsigned int color) +{ + unsigned int num; + unsigned int i = 0; + + unsigned int *startaddr=(unsigned int*)tftlcd_dev.framebuffer; //指向帧缓存首地址 + num=(unsigned int)tftlcd_dev.width * tftlcd_dev.height; //缓冲区总长度 + for(i = 0; i < num; i++) + { + startaddr[i] = color; + } +} + +/* + * @description : 以指定的颜色填充一块矩形 + * @param - x0 : 矩形起始点坐标X轴 + * @param - y0 : 矩形起始点坐标Y轴 + * @param - x1 : 矩形终止点坐标X轴 + * @param - y1 : 矩形终止点坐标Y轴 + * @param - color : 要填充的颜色 + * @return : 读取到的指定点的颜色值 + */ +void lcd_fill(unsigned short x0, unsigned short y0, + unsigned short x1, unsigned short y1, unsigned int color) +{ + unsigned short x, y; + + if(x0 < 0) x0 = 0; + if(y0 < 0) y0 = 0; + if(x1 >= tftlcd_dev.width) x1 = tftlcd_dev.width - 1; + if(y1 >= tftlcd_dev.height) y1 = tftlcd_dev.height - 1; + + for(y = y0; y <= y1; y++) + { + for(x = x0; x <= x1; x++) + lcd_drawpoint(x, y, color); + } +} + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/lcd/bsp_lcd.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/lcd/bsp_lcd.h new file mode 100644 index 00000000..463fbf24 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/lcd/bsp_lcd.h @@ -0,0 +1,79 @@ +#ifndef _BSP_LCD_H +#define _BSP_LCD_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_lcd.h +作者 : 左忠凯 +版本 : V1.0 +描述 : LCD驱动文件头文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/3 左忠凯创建 +***************************************************************/ +#include "bsp.h" + + +/* 颜色 */ +#define LCD_BLUE 0x000000FF +#define LCD_GREEN 0x0000FF00 +#define LCD_RED 0x00FF0000 +#define LCD_CYAN 0x0000FFFF +#define LCD_MAGENTA 0x00FF00FF +#define LCD_YELLOW 0x00FFFF00 +#define LCD_LIGHTBLUE 0x008080FF +#define LCD_LIGHTGREEN 0x0080FF80 +#define LCD_LIGHTRED 0x00FF8080 +#define LCD_LIGHTCYAN 0x0080FFFF +#define LCD_LIGHTMAGENTA 0x00FF80FF +#define LCD_LIGHTYELLOW 0x00FFFF80 +#define LCD_DARKBLUE 0x00000080 +#define LCD_DARKGREEN 0x00008000 +#define LCD_DARKRED 0x00800000 +#define LCD_DARKCYAN 0x00008080 +#define LCD_DARKMAGENTA 0x00800080 +#define LCD_DARKYELLOW 0x00808000 +#define LCD_WHITE 0x00FFFFFF +#define LCD_LIGHTGRAY 0x00D3D3D3 +#define LCD_GRAY 0x00808080 +#define LCD_DARKGRAY 0x00404040 +#define LCD_BLACK 0x00000000 +#define LCD_BROWN 0x00A52A2A +#define LCD_ORANGE 0x00FFA500 +#define LCD_TRANSPARENT 0x00000000 + +/* LCD显存地址 */ +#define LCD_FRAMEBUF_ADDR (0x89000000) + +/* LCD控制参数结构体 */ +struct tftlcd_typedef{ + unsigned short height; /* LCD屏幕高度 */ + unsigned short width; /* LCD屏幕宽度 */ + unsigned char pixsize; /* LCD每个像素所占字节大小 */ + unsigned short vspw; + unsigned short vbpd; + unsigned short vfpd; + unsigned short hspw; + unsigned short hbpd; + unsigned short hfpd; + unsigned int framebuffer; /* LCD显存首地址 */ + unsigned int forecolor; /* 前景色 */ + unsigned int backcolor; /* 背景色 */ +}; + +extern struct tftlcd_typedef tftlcd_dev; + + +/* 函数声明 */ +void lcd_init(void); +void lcdgpio_init(void); +void lcdclk_init(unsigned char loopDiv, unsigned char prediv, unsigned char div); +void lcd_reset(void); +void lcd_noreset(void); +void lcd_enable(void); +void video_pllinit(unsigned char loopdivi, unsigned char postdivi); + +void lcd_drawpoint(unsigned short x,unsigned short y,unsigned int color); +inline unsigned int lcd_readpoint(unsigned short x,unsigned short y); +void lcd_clear(unsigned int color); +void lcd_fill(unsigned short x0, unsigned short y0, unsigned short x1, unsigned short y1, unsigned int color); +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/lcd/bsp_lcdapi.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/lcd/bsp_lcdapi.c new file mode 100644 index 00000000..3239f4da --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/lcd/bsp_lcdapi.c @@ -0,0 +1,274 @@ +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_lcdapi.c +作者 : 左忠凯 +版本 : V1.0 +描述 : LCD API函数文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/3/18 左忠凯创建 +***************************************************************/ +#include "bsp_lcdapi.h" +#include "font.h" + +/* + * @description : 画线函数 + * @param - x1 : 线起始点坐标X轴 + * @param - y1 : 线起始点坐标Y轴 + * @param - x2 : 线终止点坐标X轴 + * @param - y2 : 线终止点坐标Y轴 + * @return : 无 + */ +void lcd_drawline(unsigned short x1, unsigned short y1, unsigned short x2, unsigned short y2) +{ + u16 t; + int xerr = 0, yerr = 0, delta_x, delta_y, distance; + int incx, incy, uRow, uCol; + delta_x = x2 - x1; /* 计算坐标增量 */ + delta_y = y2 - y1; + uRow = x1; + uCol = y1; + if(delta_x > 0) /* 设置单步方向 */ + incx = 1; + else if(delta_x==0) /* 垂直线 */ + incx = 0; + else + { + incx = -1; + delta_x = -delta_x; + } + if(delta_y>0) + incy=1; + else if(delta_y == 0) /* 水平线 */ + incy=0; + else + { + incy = -1; + delta_y = -delta_y; + } + if( delta_x > delta_y) /*选取基本增量坐标轴 */ + distance = delta_x; + else + distance = delta_y; + for(t = 0; t <= distance+1; t++ ) /* 画线输出 */ + { + + lcd_drawpoint(uRow, uCol, tftlcd_dev.forecolor);/* 画点 */ + xerr += delta_x ; + yerr += delta_y ; + if(xerr > distance) + { + xerr -= distance; + uRow += incx; + } + if(yerr > distance) + { + yerr -= distance; + uCol += incy; + } + } +} + +/* + * @description : 画矩形函数 + * @param - x1 : 矩形坐上角坐标X轴 + * @param - y1 : 矩形坐上角坐标Y轴 + * @param - x2 : 矩形右下角坐标X轴 + * @param - y2 : 矩形右下角坐标Y轴 + * @return : 无 + */ +void lcd_draw_rectangle(unsigned short x1, unsigned short y1, unsigned short x2, unsigned short y2) +{ + lcd_drawline(x1, y1, x2, y1); + lcd_drawline(x1, y1, x1, y2); + lcd_drawline(x1, y2, x2, y2); + lcd_drawline(x2, y1, x2, y2); +} + +/* + * @description : 在指定位置画一个指定大小的圆 + * @param - x0 : 圆心坐标X轴 + * @param - y0 : 圆心坐标Y轴 + * @param - y2 : 圆形半径 + * @return : 无 + */ +void lcd_draw_Circle(unsigned short x0,unsigned short y0,unsigned char r) +{ + int mx = x0, my = y0; + int x = 0, y = r; + + int d = 1 - r; + while(y > x) /* y>x即第一象限的第1区八分圆 */ + { + lcd_drawpoint(x + mx, y + my, tftlcd_dev.forecolor); + lcd_drawpoint(y + mx, x + my, tftlcd_dev.forecolor); + lcd_drawpoint(-x + mx, y + my, tftlcd_dev.forecolor); + lcd_drawpoint(-y + mx, x + my, tftlcd_dev.forecolor); + + lcd_drawpoint(-x + mx, -y + my, tftlcd_dev.forecolor); + lcd_drawpoint(-y + mx, -x + my, tftlcd_dev.forecolor); + lcd_drawpoint(x + mx, -y + my, tftlcd_dev.forecolor); + lcd_drawpoint(y + mx, -x + my, tftlcd_dev.forecolor); + if( d < 0) + { + d = d + 2 * x + 3; + } + else + { + d= d + 2 * (x - y) + 5; + y--; + } + x++; + } +} + +/* + * @description : 在指定位置显示一个字符 + * @param - x : 起始坐标X轴 + * @param - y : 起始坐标Y轴 + * @param - num : 显示字符 + * @param - size: 字体大小, 可选12/16/24/32 + * @param - mode: 叠加方式(1)还是非叠加方式(0) + * @return : 无 + */ +void lcd_showchar(unsigned short x, unsigned short y, + unsigned char num, unsigned char size, + unsigned char mode) +{ + unsigned char temp, t1, t; + unsigned short y0 = y; + unsigned char csize = (size / 8+ ((size % 8) ? 1 : 0)) * (size / 2); /* 得到字体一个字符对应点阵集所占的字节数 */ + num = num - ' '; /*得到偏移后的值（ASCII字库是从空格开始取模，所以-' '就是对应字符的字库） */ + for(t = 0; t < csize; t++) + { + if(size == 12) temp = asc2_1206[num][t]; /* 调用1206字体 */ + else if(size == 16)temp = asc2_1608[num][t]; /* 调用1608字体 */ + else if(size == 24)temp = asc2_2412[num][t]; /* 调用2412字体 */ + else if(size == 32)temp = asc2_3216[num][t]; /* 调用3216字体 */ + else return; /* 没有的字库 */ + for(t1 = 0; t1 < 8; t1++) + { + if(temp & 0x80)lcd_drawpoint(x, y, tftlcd_dev.forecolor); + else if(mode==0)lcd_drawpoint(x, y, tftlcd_dev.backcolor); + temp <<= 1; + y++; + if(y >= tftlcd_dev.height) return; /* 超区域了 */ + if((y - y0) == size) + { + y = y0; + x++; + if(x >= tftlcd_dev.width) return; /* 超区域了 */ + break; + } + } + } +} + +/* + * @description : 计算m的n次方 + * @param - m : 要计算的值 + * @param - n : n次方 + * @return : m^n次方. + */ +unsigned int lcd_pow(unsigned char m,unsigned char n) +{ + unsigned int result = 1; + while(n--) result *= m; + return result; +} + +/* + * @description : 显示指定的数字，高位为0的话不显示 + * @param - x : 起始坐标点X轴。 + * @param - y : 起始坐标点Y轴。 + * @param - num : 数值(0~999999999)。 + * @param - len : 数字位数。 + * @param - size: 字体大小 + * @return : 无 + */ +void lcd_shownum(unsigned short x, + unsigned short y, + unsigned int num, + unsigned char len, + unsigned char size) +{ + unsigned char t, temp; + unsigned char enshow = 0; + for(t = 0; t < len; t++) + { + temp = (num / lcd_pow(10, len - t - 1)) % 10; + if(enshow == 0 && t < (len - 1)) + { + if(temp == 0) + { + lcd_showchar(x + (size / 2) * t, y, ' ', size, 0); + continue; + }else enshow = 1; + } + lcd_showchar(x + (size / 2) * t, y, temp + '0', size, 0); + } +} + +/* + * @description : 显示指定的数字，高位为0,还是显示 + * @param - x : 起始坐标点X轴。 + * @param - y : 起始坐标点Y轴。 + * @param - num : 数值(0~999999999)。 + * @param - len : 数字位数。 + * @param - size : 字体大小 + * @param - mode : [7]:0,不填充;1,填充0. + * [6:1]:保留 + * [0]:0,非叠加显示;1,叠加显示. + * @return : 无 + */ +void lcd_showxnum(unsigned short x, unsigned short y, + unsigned int num, unsigned char len, + unsigned char size, unsigned char mode) +{ + unsigned char t, temp; + unsigned char enshow = 0; + for(t = 0; t < len; t++) + { + temp = (num / lcd_pow(10, len - t- 1)) % 10; + if(enshow == 0 && t < (len - 1)) + { + if(temp == 0) + { + if(mode & 0X80) lcd_showchar(x + (size / 2) * t, y, '0', size, mode & 0X01); + else lcd_showchar(x + (size / 2) * t, y , ' ', size, mode & 0X01); + continue; + }else enshow=1; + + } + lcd_showchar( x + (size / 2) * t, y, temp + '0' , size , mode & 0X01); + } +} + +/* + * @description : 显示一串字符串 + * @param - x : 起始坐标点X轴。 + * @param - y : 起始坐标点Y轴。 + * @param - width : 字符串显示区域长度 + * @param - height : 字符串显示区域高度 + * @param - size : 字体大小 + * @param - p : 要显示的字符串首地址 + * @return : 无 + */ +void lcd_show_string(unsigned short x,unsigned short y, + unsigned short width,unsigned short height, + unsigned char size,char *p) +{ + unsigned char x0 = x; + width += x; + height += y; + while((*p <= '~') &&(*p >= ' ')) /* 判断是不是非法字符! */ + { + if(x >= width) {x = x0; y += size;} + if(y >= height) break; /* 退出 */ + lcd_showchar(x, y, *p , size, 0); + x += size / 2; + p++; + } +} + + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/lcd/bsp_lcdapi.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/lcd/bsp_lcdapi.h new file mode 100644 index 00000000..b4444c3a --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/lcd/bsp_lcdapi.h @@ -0,0 +1,28 @@ +#ifndef BSP_LCDAPI_H +#define BSP_LCDAPI_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_lcdapi.h +作者 : 左忠凯 +版本 : V1.0 +描述 : LCD显示API函数。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/3/18 左忠凯创建 +***************************************************************/ +#include "bsp.h" +#include "bsp_lcd.h" + +/* 函数声明 */ +void lcd_drawline(unsigned short x1, unsigned short y1, unsigned short x2, unsigned short y2); +void lcd_draw_rectangle(unsigned short x1, unsigned short y1, unsigned short x2, unsigned short y2); +void lcd_draw_Circle(unsigned short x0,unsigned short y0,unsigned char r); +void lcd_showchar(unsigned short x,unsigned short y,unsigned char num,unsigned char size, unsigned char mode); +unsigned int lcd_pow(unsigned char m,unsigned char n); +void lcd_shownum(unsigned short x, unsigned short y, unsigned int num, unsigned char len,unsigned char size); +void lcd_showxnum(unsigned short x, unsigned short y, unsigned int num, unsigned char len, unsigned char size, unsigned char mode); +void lcd_show_string(unsigned short x,unsigned short y, +unsigned short width, unsigned short height, unsigned char size,char *p); + +#endif + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/lcd/font.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/lcd/font.h new file mode 100644 index 00000000..fd9d510b --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/lcd/font.h @@ -0,0 +1,406 @@ +#ifndef __FONT_H +#define __FONT_H + +//常用ASCII表 +//偏移量32 +//ASCII字符集: !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~ +//PC2LCD2002取模方式设置：阴码+逐列式+顺向+C51格式 +//总共：3个字符集（12*12、16*16、24*24和32*32），用户可以自行新增其他分辨率的字符集。 +//每个字符所占用的字节数为:(size/8+((size%8)?1:0))*(size/2),其中size:是字库生成时的点阵大小(12/16/24/32...) + +//12*12 ASCII字符集点阵 +const unsigned char asc2_1206[95][12]={ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/ +{0x00,0x00,0x00,0x00,0x3F,0x40,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/ +{0x00,0x00,0x30,0x00,0x40,0x00,0x30,0x00,0x40,0x00,0x00,0x00},/*""",2*/ +{0x09,0x00,0x0B,0xC0,0x3D,0x00,0x0B,0xC0,0x3D,0x00,0x09,0x00},/*"#",3*/ +{0x18,0xC0,0x24,0x40,0x7F,0xE0,0x22,0x40,0x31,0x80,0x00,0x00},/*"$",4*/ +{0x18,0x00,0x24,0xC0,0x1B,0x00,0x0D,0x80,0x32,0x40,0x01,0x80},/*"%",5*/ +{0x03,0x80,0x1C,0x40,0x27,0x40,0x1C,0x80,0x07,0x40,0x00,0x40},/*"&",6*/ +{0x10,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x80,0x20,0x40,0x40,0x20},/*"(",8*/ +{0x00,0x00,0x40,0x20,0x20,0x40,0x1F,0x80,0x00,0x00,0x00,0x00},/*")",9*/ +{0x09,0x00,0x06,0x00,0x1F,0x80,0x06,0x00,0x09,0x00,0x00,0x00},/*"*",10*/ +{0x04,0x00,0x04,0x00,0x3F,0x80,0x04,0x00,0x04,0x00,0x00,0x00},/*"+",11*/ +{0x00,0x10,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/ +{0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x00,0x00},/*"-",13*/ +{0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/ +{0x00,0x20,0x01,0xC0,0x06,0x00,0x38,0x00,0x40,0x00,0x00,0x00},/*"/",15*/ +{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"0",16*/ +{0x00,0x00,0x10,0x40,0x3F,0xC0,0x00,0x40,0x00,0x00,0x00,0x00},/*"1",17*/ +{0x18,0xC0,0x21,0x40,0x22,0x40,0x24,0x40,0x18,0x40,0x00,0x00},/*"2",18*/ +{0x10,0x80,0x20,0x40,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"3",19*/ +{0x02,0x00,0x0D,0x00,0x11,0x00,0x3F,0xC0,0x01,0x40,0x00,0x00},/*"4",20*/ +{0x3C,0x80,0x24,0x40,0x24,0x40,0x24,0x40,0x23,0x80,0x00,0x00},/*"5",21*/ +{0x1F,0x80,0x24,0x40,0x24,0x40,0x34,0x40,0x03,0x80,0x00,0x00},/*"6",22*/ +{0x30,0x00,0x20,0x00,0x27,0xC0,0x38,0x00,0x20,0x00,0x00,0x00},/*"7",23*/ +{0x1B,0x80,0x24,0x40,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"8",24*/ +{0x1C,0x00,0x22,0xC0,0x22,0x40,0x22,0x40,0x1F,0x80,0x00,0x00},/*"9",25*/ +{0x00,0x00,0x00,0x00,0x08,0x40,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/ +{0x00,0x00,0x00,0x00,0x04,0x60,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/ +{0x00,0x00,0x04,0x00,0x0A,0x00,0x11,0x00,0x20,0x80,0x40,0x40},/*"<",28*/ +{0x09,0x00,0x09,0x00,0x09,0x00,0x09,0x00,0x09,0x00,0x00,0x00},/*"=",29*/ +{0x00,0x00,0x40,0x40,0x20,0x80,0x11,0x00,0x0A,0x00,0x04,0x00},/*">",30*/ +{0x18,0x00,0x20,0x00,0x23,0x40,0x24,0x00,0x18,0x00,0x00,0x00},/*"?",31*/ +{0x1F,0x80,0x20,0x40,0x27,0x40,0x29,0x40,0x1F,0x40,0x00,0x00},/*"@",32*/ +{0x00,0x40,0x07,0xC0,0x39,0x00,0x0F,0x00,0x01,0xC0,0x00,0x40},/*"A",33*/ +{0x20,0x40,0x3F,0xC0,0x24,0x40,0x24,0x40,0x1B,0x80,0x00,0x00},/*"B",34*/ +{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x30,0x80,0x00,0x00},/*"C",35*/ +{0x20,0x40,0x3F,0xC0,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"D",36*/ +{0x20,0x40,0x3F,0xC0,0x24,0x40,0x2E,0x40,0x30,0xC0,0x00,0x00},/*"E",37*/ +{0x20,0x40,0x3F,0xC0,0x24,0x40,0x2E,0x00,0x30,0x00,0x00,0x00},/*"F",38*/ +{0x0F,0x00,0x10,0x80,0x20,0x40,0x22,0x40,0x33,0x80,0x02,0x00},/*"G",39*/ +{0x20,0x40,0x3F,0xC0,0x04,0x00,0x04,0x00,0x3F,0xC0,0x20,0x40},/*"H",40*/ +{0x20,0x40,0x20,0x40,0x3F,0xC0,0x20,0x40,0x20,0x40,0x00,0x00},/*"I",41*/ +{0x00,0x60,0x20,0x20,0x20,0x20,0x3F,0xC0,0x20,0x00,0x20,0x00},/*"J",42*/ +{0x20,0x40,0x3F,0xC0,0x24,0x40,0x0B,0x00,0x30,0xC0,0x20,0x40},/*"K",43*/ +{0x20,0x40,0x3F,0xC0,0x20,0x40,0x00,0x40,0x00,0x40,0x00,0xC0},/*"L",44*/ +{0x3F,0xC0,0x3C,0x00,0x03,0xC0,0x3C,0x00,0x3F,0xC0,0x00,0x00},/*"M",45*/ +{0x20,0x40,0x3F,0xC0,0x0C,0x40,0x23,0x00,0x3F,0xC0,0x20,0x00},/*"N",46*/ +{0x1F,0x80,0x20,0x40,0x20,0x40,0x20,0x40,0x1F,0x80,0x00,0x00},/*"O",47*/ +{0x20,0x40,0x3F,0xC0,0x24,0x40,0x24,0x00,0x18,0x00,0x00,0x00},/*"P",48*/ +{0x1F,0x80,0x21,0x40,0x21,0x40,0x20,0xE0,0x1F,0xA0,0x00,0x00},/*"Q",49*/ +{0x20,0x40,0x3F,0xC0,0x24,0x40,0x26,0x00,0x19,0xC0,0x00,0x40},/*"R",50*/ +{0x18,0xC0,0x24,0x40,0x24,0x40,0x22,0x40,0x31,0x80,0x00,0x00},/*"S",51*/ +{0x30,0x00,0x20,0x40,0x3F,0xC0,0x20,0x40,0x30,0x00,0x00,0x00},/*"T",52*/ +{0x20,0x00,0x3F,0x80,0x00,0x40,0x00,0x40,0x3F,0x80,0x20,0x00},/*"U",53*/ +{0x20,0x00,0x3E,0x00,0x01,0xC0,0x07,0x00,0x38,0x00,0x20,0x00},/*"V",54*/ +{0x38,0x00,0x07,0xC0,0x3C,0x00,0x07,0xC0,0x38,0x00,0x00,0x00},/*"W",55*/ +{0x20,0x40,0x39,0xC0,0x06,0x00,0x39,0xC0,0x20,0x40,0x00,0x00},/*"X",56*/ +{0x20,0x00,0x38,0x40,0x07,0xC0,0x38,0x40,0x20,0x00,0x00,0x00},/*"Y",57*/ +{0x30,0x40,0x21,0xC0,0x26,0x40,0x38,0x40,0x20,0xC0,0x00,0x00},/*"Z",58*/ +{0x00,0x00,0x00,0x00,0x7F,0xE0,0x40,0x20,0x40,0x20,0x00,0x00},/*"[",59*/ +{0x00,0x00,0x70,0x00,0x0C,0x00,0x03,0x80,0x00,0x40,0x00,0x00},/*"\",60*/ +{0x00,0x00,0x40,0x20,0x40,0x20,0x7F,0xE0,0x00,0x00,0x00,0x00},/*"]",61*/ +{0x00,0x00,0x20,0x00,0x40,0x00,0x20,0x00,0x00,0x00,0x00,0x00},/*"^",62*/ +{0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10},/*"_",63*/ +{0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/ +{0x00,0x00,0x02,0x80,0x05,0x40,0x05,0x40,0x03,0xC0,0x00,0x40},/*"a",65*/ +{0x20,0x00,0x3F,0xC0,0x04,0x40,0x04,0x40,0x03,0x80,0x00,0x00},/*"b",66*/ +{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x40,0x06,0x40,0x00,0x00},/*"c",67*/ +{0x00,0x00,0x03,0x80,0x04,0x40,0x24,0x40,0x3F,0xC0,0x00,0x40},/*"d",68*/ +{0x00,0x00,0x03,0x80,0x05,0x40,0x05,0x40,0x03,0x40,0x00,0x00},/*"e",69*/ +{0x00,0x00,0x04,0x40,0x1F,0xC0,0x24,0x40,0x24,0x40,0x20,0x00},/*"f",70*/ +{0x00,0x00,0x02,0xE0,0x05,0x50,0x05,0x50,0x06,0x50,0x04,0x20},/*"g",71*/ +{0x20,0x40,0x3F,0xC0,0x04,0x40,0x04,0x00,0x03,0xC0,0x00,0x40},/*"h",72*/ +{0x00,0x00,0x04,0x40,0x27,0xC0,0x00,0x40,0x00,0x00,0x00,0x00},/*"i",73*/ +{0x00,0x10,0x00,0x10,0x04,0x10,0x27,0xE0,0x00,0x00,0x00,0x00},/*"j",74*/ +{0x20,0x40,0x3F,0xC0,0x01,0x40,0x07,0x00,0x04,0xC0,0x04,0x40},/*"k",75*/ +{0x20,0x40,0x20,0x40,0x3F,0xC0,0x00,0x40,0x00,0x40,0x00,0x00},/*"l",76*/ +{0x07,0xC0,0x04,0x00,0x07,0xC0,0x04,0x00,0x03,0xC0,0x00,0x00},/*"m",77*/ +{0x04,0x40,0x07,0xC0,0x04,0x40,0x04,0x00,0x03,0xC0,0x00,0x40},/*"n",78*/ +{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x40,0x03,0x80,0x00,0x00},/*"o",79*/ +{0x04,0x10,0x07,0xF0,0x04,0x50,0x04,0x40,0x03,0x80,0x00,0x00},/*"p",80*/ +{0x00,0x00,0x03,0x80,0x04,0x40,0x04,0x50,0x07,0xF0,0x00,0x10},/*"q",81*/ +{0x04,0x40,0x07,0xC0,0x02,0x40,0x04,0x00,0x04,0x00,0x00,0x00},/*"r",82*/ +{0x00,0x00,0x06,0x40,0x05,0x40,0x05,0x40,0x04,0xC0,0x00,0x00},/*"s",83*/ +{0x00,0x00,0x04,0x00,0x1F,0x80,0x04,0x40,0x00,0x40,0x00,0x00},/*"t",84*/ +{0x04,0x00,0x07,0x80,0x00,0x40,0x04,0x40,0x07,0xC0,0x00,0x40},/*"u",85*/ +{0x04,0x00,0x07,0x00,0x04,0xC0,0x01,0x80,0x06,0x00,0x04,0x00},/*"v",86*/ +{0x06,0x00,0x01,0xC0,0x07,0x00,0x01,0xC0,0x06,0x00,0x00,0x00},/*"w",87*/ +{0x04,0x40,0x06,0xC0,0x01,0x00,0x06,0xC0,0x04,0x40,0x00,0x00},/*"x",88*/ +{0x04,0x10,0x07,0x10,0x04,0xE0,0x01,0x80,0x06,0x00,0x04,0x00},/*"y",89*/ +{0x00,0x00,0x04,0x40,0x05,0xC0,0x06,0x40,0x04,0x40,0x00,0x00},/*"z",90*/ +{0x00,0x00,0x00,0x00,0x04,0x00,0x7B,0xE0,0x40,0x20,0x00,0x00},/*"{",91*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xF0,0x00,0x00,0x00,0x00},/*"|",92*/ +{0x00,0x00,0x40,0x20,0x7B,0xE0,0x04,0x00,0x00,0x00,0x00,0x00},/*"}",93*/ +{0x40,0x00,0x80,0x00,0x40,0x00,0x20,0x00,0x20,0x00,0x40,0x00},/*"~",94*/ +}; + +//16*16 ASCII字符集点阵 +const unsigned char asc2_1608[95][16]={ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0xCC,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/ +{0x00,0x00,0x08,0x00,0x30,0x00,0x60,0x00,0x08,0x00,0x30,0x00,0x60,0x00,0x00,0x00},/*""",2*/ +{0x02,0x20,0x03,0xFC,0x1E,0x20,0x02,0x20,0x03,0xFC,0x1E,0x20,0x02,0x20,0x00,0x00},/*"#",3*/ +{0x00,0x00,0x0E,0x18,0x11,0x04,0x3F,0xFF,0x10,0x84,0x0C,0x78,0x00,0x00,0x00,0x00},/*"$",4*/ +{0x0F,0x00,0x10,0x84,0x0F,0x38,0x00,0xC0,0x07,0x78,0x18,0x84,0x00,0x78,0x00,0x00},/*"%",5*/ +{0x00,0x78,0x0F,0x84,0x10,0xC4,0x11,0x24,0x0E,0x98,0x00,0xE4,0x00,0x84,0x00,0x08},/*"&",6*/ +{0x08,0x00,0x68,0x00,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xE0,0x18,0x18,0x20,0x04,0x40,0x02,0x00,0x00},/*"(",8*/ +{0x00,0x00,0x40,0x02,0x20,0x04,0x18,0x18,0x07,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*")",9*/ +{0x02,0x40,0x02,0x40,0x01,0x80,0x0F,0xF0,0x01,0x80,0x02,0x40,0x02,0x40,0x00,0x00},/*"*",10*/ +{0x00,0x80,0x00,0x80,0x00,0x80,0x0F,0xF8,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x00},/*"+",11*/ +{0x00,0x01,0x00,0x0D,0x00,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/ +{0x00,0x00,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80},/*"-",13*/ +{0x00,0x00,0x00,0x0C,0x00,0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/ +{0x00,0x00,0x00,0x06,0x00,0x18,0x00,0x60,0x01,0x80,0x06,0x00,0x18,0x00,0x20,0x00},/*"/",15*/ +{0x00,0x00,0x07,0xF0,0x08,0x08,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"0",16*/ +{0x00,0x00,0x08,0x04,0x08,0x04,0x1F,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"1",17*/ +{0x00,0x00,0x0E,0x0C,0x10,0x14,0x10,0x24,0x10,0x44,0x11,0x84,0x0E,0x0C,0x00,0x00},/*"2",18*/ +{0x00,0x00,0x0C,0x18,0x10,0x04,0x11,0x04,0x11,0x04,0x12,0x88,0x0C,0x70,0x00,0x00},/*"3",19*/ +{0x00,0x00,0x00,0xE0,0x03,0x20,0x04,0x24,0x08,0x24,0x1F,0xFC,0x00,0x24,0x00,0x00},/*"4",20*/ +{0x00,0x00,0x1F,0x98,0x10,0x84,0x11,0x04,0x11,0x04,0x10,0x88,0x10,0x70,0x00,0x00},/*"5",21*/ +{0x00,0x00,0x07,0xF0,0x08,0x88,0x11,0x04,0x11,0x04,0x18,0x88,0x00,0x70,0x00,0x00},/*"6",22*/ +{0x00,0x00,0x1C,0x00,0x10,0x00,0x10,0xFC,0x13,0x00,0x1C,0x00,0x10,0x00,0x00,0x00},/*"7",23*/ +{0x00,0x00,0x0E,0x38,0x11,0x44,0x10,0x84,0x10,0x84,0x11,0x44,0x0E,0x38,0x00,0x00},/*"8",24*/ +{0x00,0x00,0x07,0x00,0x08,0x8C,0x10,0x44,0x10,0x44,0x08,0x88,0x07,0xF0,0x00,0x00},/*"9",25*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x0C,0x03,0x0C,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/ +{0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/ +{0x00,0x00,0x00,0x80,0x01,0x40,0x02,0x20,0x04,0x10,0x08,0x08,0x10,0x04,0x00,0x00},/*"<",28*/ +{0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x02,0x20,0x00,0x00},/*"=",29*/ +{0x00,0x00,0x10,0x04,0x08,0x08,0x04,0x10,0x02,0x20,0x01,0x40,0x00,0x80,0x00,0x00},/*">",30*/ +{0x00,0x00,0x0E,0x00,0x12,0x00,0x10,0x0C,0x10,0x6C,0x10,0x80,0x0F,0x00,0x00,0x00},/*"?",31*/ +{0x03,0xE0,0x0C,0x18,0x13,0xE4,0x14,0x24,0x17,0xC4,0x08,0x28,0x07,0xD0,0x00,0x00},/*"@",32*/ +{0x00,0x04,0x00,0x3C,0x03,0xC4,0x1C,0x40,0x07,0x40,0x00,0xE4,0x00,0x1C,0x00,0x04},/*"A",33*/ +{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x04,0x11,0x04,0x0E,0x88,0x00,0x70,0x00,0x00},/*"B",34*/ +{0x03,0xE0,0x0C,0x18,0x10,0x04,0x10,0x04,0x10,0x04,0x10,0x08,0x1C,0x10,0x00,0x00},/*"C",35*/ +{0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"D",36*/ +{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x04,0x17,0xC4,0x10,0x04,0x08,0x18,0x00,0x00},/*"E",37*/ +{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x00,0x17,0xC0,0x10,0x00,0x08,0x00,0x00,0x00},/*"F",38*/ +{0x03,0xE0,0x0C,0x18,0x10,0x04,0x10,0x04,0x10,0x44,0x1C,0x78,0x00,0x40,0x00,0x00},/*"G",39*/ +{0x10,0x04,0x1F,0xFC,0x10,0x84,0x00,0x80,0x00,0x80,0x10,0x84,0x1F,0xFC,0x10,0x04},/*"H",40*/ +{0x00,0x00,0x10,0x04,0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x04,0x00,0x00,0x00,0x00},/*"I",41*/ +{0x00,0x03,0x00,0x01,0x10,0x01,0x10,0x01,0x1F,0xFE,0x10,0x00,0x10,0x00,0x00,0x00},/*"J",42*/ +{0x10,0x04,0x1F,0xFC,0x11,0x04,0x03,0x80,0x14,0x64,0x18,0x1C,0x10,0x04,0x00,0x00},/*"K",43*/ +{0x10,0x04,0x1F,0xFC,0x10,0x04,0x00,0x04,0x00,0x04,0x00,0x04,0x00,0x0C,0x00,0x00},/*"L",44*/ +{0x10,0x04,0x1F,0xFC,0x1F,0x00,0x00,0xFC,0x1F,0x00,0x1F,0xFC,0x10,0x04,0x00,0x00},/*"M",45*/ +{0x10,0x04,0x1F,0xFC,0x0C,0x04,0x03,0x00,0x00,0xE0,0x10,0x18,0x1F,0xFC,0x10,0x00},/*"N",46*/ +{0x07,0xF0,0x08,0x08,0x10,0x04,0x10,0x04,0x10,0x04,0x08,0x08,0x07,0xF0,0x00,0x00},/*"O",47*/ +{0x10,0x04,0x1F,0xFC,0x10,0x84,0x10,0x80,0x10,0x80,0x10,0x80,0x0F,0x00,0x00,0x00},/*"P",48*/ +{0x07,0xF0,0x08,0x18,0x10,0x24,0x10,0x24,0x10,0x1C,0x08,0x0A,0x07,0xF2,0x00,0x00},/*"Q",49*/ +{0x10,0x04,0x1F,0xFC,0x11,0x04,0x11,0x00,0x11,0xC0,0x11,0x30,0x0E,0x0C,0x00,0x04},/*"R",50*/ +{0x00,0x00,0x0E,0x1C,0x11,0x04,0x10,0x84,0x10,0x84,0x10,0x44,0x1C,0x38,0x00,0x00},/*"S",51*/ +{0x18,0x00,0x10,0x00,0x10,0x04,0x1F,0xFC,0x10,0x04,0x10,0x00,0x18,0x00,0x00,0x00},/*"T",52*/ +{0x10,0x00,0x1F,0xF8,0x10,0x04,0x00,0x04,0x00,0x04,0x10,0x04,0x1F,0xF8,0x10,0x00},/*"U",53*/ +{0x10,0x00,0x1E,0x00,0x11,0xE0,0x00,0x1C,0x00,0x70,0x13,0x80,0x1C,0x00,0x10,0x00},/*"V",54*/ +{0x1F,0xC0,0x10,0x3C,0x00,0xE0,0x1F,0x00,0x00,0xE0,0x10,0x3C,0x1F,0xC0,0x00,0x00},/*"W",55*/ +{0x10,0x04,0x18,0x0C,0x16,0x34,0x01,0xC0,0x01,0xC0,0x16,0x34,0x18,0x0C,0x10,0x04},/*"X",56*/ +{0x10,0x00,0x1C,0x00,0x13,0x04,0x00,0xFC,0x13,0x04,0x1C,0x00,0x10,0x00,0x00,0x00},/*"Y",57*/ +{0x08,0x04,0x10,0x1C,0x10,0x64,0x10,0x84,0x13,0x04,0x1C,0x04,0x10,0x18,0x00,0x00},/*"Z",58*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0xFE,0x40,0x02,0x40,0x02,0x40,0x02,0x00,0x00},/*"[",59*/ +{0x00,0x00,0x30,0x00,0x0C,0x00,0x03,0x80,0x00,0x60,0x00,0x1C,0x00,0x03,0x00,0x00},/*"\",60*/ +{0x00,0x00,0x40,0x02,0x40,0x02,0x40,0x02,0x7F,0xFE,0x00,0x00,0x00,0x00,0x00,0x00},/*"]",61*/ +{0x00,0x00,0x00,0x00,0x20,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x00,0x00},/*"^",62*/ +{0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01,0x00,0x01},/*"_",63*/ +{0x00,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/ +{0x00,0x00,0x00,0x98,0x01,0x24,0x01,0x44,0x01,0x44,0x01,0x44,0x00,0xFC,0x00,0x04},/*"a",65*/ +{0x10,0x00,0x1F,0xFC,0x00,0x88,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x70,0x00,0x00},/*"b",66*/ +{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x00},/*"c",67*/ +{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x11,0x08,0x1F,0xFC,0x00,0x04},/*"d",68*/ +{0x00,0x00,0x00,0xF8,0x01,0x44,0x01,0x44,0x01,0x44,0x01,0x44,0x00,0xC8,0x00,0x00},/*"e",69*/ +{0x00,0x00,0x01,0x04,0x01,0x04,0x0F,0xFC,0x11,0x04,0x11,0x04,0x11,0x00,0x18,0x00},/*"f",70*/ +{0x00,0x00,0x00,0xD6,0x01,0x29,0x01,0x29,0x01,0x29,0x01,0xC9,0x01,0x06,0x00,0x00},/*"g",71*/ +{0x10,0x04,0x1F,0xFC,0x00,0x84,0x01,0x00,0x01,0x00,0x01,0x04,0x00,0xFC,0x00,0x04},/*"h",72*/ +{0x00,0x00,0x01,0x04,0x19,0x04,0x19,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"i",73*/ +{0x00,0x00,0x00,0x03,0x00,0x01,0x01,0x01,0x19,0x01,0x19,0xFE,0x00,0x00,0x00,0x00},/*"j",74*/ +{0x10,0x04,0x1F,0xFC,0x00,0x24,0x00,0x40,0x01,0xB4,0x01,0x0C,0x01,0x04,0x00,0x00},/*"k",75*/ +{0x00,0x00,0x10,0x04,0x10,0x04,0x1F,0xFC,0x00,0x04,0x00,0x04,0x00,0x00,0x00,0x00},/*"l",76*/ +{0x01,0x04,0x01,0xFC,0x01,0x04,0x01,0x00,0x01,0xFC,0x01,0x04,0x01,0x00,0x00,0xFC},/*"m",77*/ +{0x01,0x04,0x01,0xFC,0x00,0x84,0x01,0x00,0x01,0x00,0x01,0x04,0x00,0xFC,0x00,0x04},/*"n",78*/ +{0x00,0x00,0x00,0xF8,0x01,0x04,0x01,0x04,0x01,0x04,0x01,0x04,0x00,0xF8,0x00,0x00},/*"o",79*/ +{0x01,0x01,0x01,0xFF,0x00,0x85,0x01,0x04,0x01,0x04,0x00,0x88,0x00,0x70,0x00,0x00},/*"p",80*/ +{0x00,0x00,0x00,0x70,0x00,0x88,0x01,0x04,0x01,0x04,0x01,0x05,0x01,0xFF,0x00,0x01},/*"q",81*/ +{0x01,0x04,0x01,0x04,0x01,0xFC,0x00,0x84,0x01,0x04,0x01,0x00,0x01,0x80,0x00,0x00},/*"r",82*/ +{0x00,0x00,0x00,0xCC,0x01,0x24,0x01,0x24,0x01,0x24,0x01,0x24,0x01,0x98,0x00,0x00},/*"s",83*/ +{0x00,0x00,0x01,0x00,0x01,0x00,0x07,0xF8,0x01,0x04,0x01,0x04,0x00,0x00,0x00,0x00},/*"t",84*/ +{0x01,0x00,0x01,0xF8,0x00,0x04,0x00,0x04,0x00,0x04,0x01,0x08,0x01,0xFC,0x00,0x04},/*"u",85*/ +{0x01,0x00,0x01,0x80,0x01,0x70,0x00,0x0C,0x00,0x10,0x01,0x60,0x01,0x80,0x01,0x00},/*"v",86*/ +{0x01,0xF0,0x01,0x0C,0x00,0x30,0x01,0xC0,0x00,0x30,0x01,0x0C,0x01,0xF0,0x01,0x00},/*"w",87*/ +{0x00,0x00,0x01,0x04,0x01,0x8C,0x00,0x74,0x01,0x70,0x01,0x8C,0x01,0x04,0x00,0x00},/*"x",88*/ +{0x01,0x01,0x01,0x81,0x01,0x71,0x00,0x0E,0x00,0x18,0x01,0x60,0x01,0x80,0x01,0x00},/*"y",89*/ +{0x00,0x00,0x01,0x84,0x01,0x0C,0x01,0x34,0x01,0x44,0x01,0x84,0x01,0x0C,0x00,0x00},/*"z",90*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x3E,0xFC,0x40,0x02,0x40,0x02},/*"{",91*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00},/*"|",92*/ +{0x00,0x00,0x40,0x02,0x40,0x02,0x3E,0xFC,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"}",93*/ +{0x00,0x00,0x60,0x00,0x80,0x00,0x80,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x20,0x00},/*"~",94*/ +}; + +//24*24 ASICII字符集点阵 +const unsigned char asc2_2412[95][36]={ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x80,0x38,0x0F,0xFE,0x38,0x0F,0x80,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x06,0x00,0x00,0x0C,0x00,0x00,0x38,0x00,0x00,0x31,0x00,0x00,0x06,0x00,0x00,0x0C,0x00,0x00,0x38,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00},/*""",2*/ +{0x00,0x00,0x00,0x00,0x61,0x80,0x00,0x67,0xF8,0x07,0xF9,0x80,0x00,0x61,0x80,0x00,0x61,0x80,0x00,0x61,0x80,0x00,0x61,0x80,0x00,0x67,0xF8,0x07,0xF9,0x80,0x00,0x61,0x80,0x00,0x00,0x00},/*"#",3*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x01,0xC0,0xE0,0x03,0xE0,0xF0,0x06,0x30,0x08,0x04,0x18,0x08,0x1F,0xFF,0xFE,0x04,0x0E,0x08,0x07,0x87,0xF0,0x03,0x81,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*"$",4*/ +{0x01,0xF0,0x00,0x06,0x0C,0x00,0x04,0x04,0x08,0x06,0x0C,0x70,0x01,0xF9,0xC0,0x00,0x0E,0x00,0x00,0x3B,0xE0,0x00,0xEC,0x18,0x07,0x08,0x08,0x04,0x0C,0x18,0x00,0x03,0xE0,0x00,0x00,0x00},/*"%",5*/ +{0x00,0x01,0xE0,0x00,0x07,0xF0,0x03,0xF8,0x18,0x04,0x1C,0x08,0x04,0x17,0x08,0x07,0xE1,0xD0,0x03,0xC0,0xE0,0x00,0x23,0xB0,0x00,0x3C,0x08,0x00,0x20,0x08,0x00,0x00,0x10,0x00,0x00,0x00},/*"&",6*/ +{0x00,0x00,0x00,0x01,0x00,0x00,0x31,0x00,0x00,0x32,0x00,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x00,0x01,0xFF,0xC0,0x07,0x80,0xF0,0x0C,0x00,0x18,0x10,0x00,0x04,0x20,0x00,0x02,0x00,0x00,0x00},/*"(",8*/ +{0x00,0x00,0x00,0x20,0x00,0x02,0x10,0x00,0x04,0x0C,0x00,0x18,0x07,0x80,0xF0,0x01,0xFF,0xC0,0x00,0x7F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*")",9*/ +{0x00,0x00,0x00,0x00,0x42,0x00,0x00,0x66,0x00,0x00,0x66,0x00,0x00,0x3C,0x00,0x00,0x18,0x00,0x03,0xFF,0xC0,0x00,0x18,0x00,0x00,0x3C,0x00,0x00,0x66,0x00,0x00,0x66,0x00,0x00,0x42,0x00},/*"*",10*/ +{0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x01,0xFF,0xC0,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00},/*"+",11*/ +{0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x31,0x00,0x00,0x32,0x00,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/ +{0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00},/*"-",13*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x00,0x00,0x38,0x00,0x00,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/ +{0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x1C,0x00,0x00,0x70,0x00,0x01,0x80,0x00,0x0E,0x00,0x00,0x38,0x00,0x00,0xC0,0x00,0x07,0x00,0x00,0x1C,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00},/*"/",15*/ +{0x00,0x00,0x00,0x00,0x7F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x18,0x04,0x00,0x08,0x04,0x00,0x08,0x06,0x00,0x18,0x03,0x80,0x70,0x01,0xFF,0xE0,0x00,0x7F,0x80,0x00,0x00,0x00},/*"0",16*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x08,0x01,0x00,0x08,0x01,0x00,0x08,0x03,0xFF,0xF8,0x07,0xFF,0xF8,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"1",17*/ +{0x00,0x00,0x00,0x01,0xC0,0x38,0x02,0xC0,0x58,0x04,0x00,0x98,0x04,0x01,0x18,0x04,0x02,0x18,0x04,0x04,0x18,0x06,0x1C,0x18,0x03,0xF8,0x18,0x01,0xE0,0xF8,0x00,0x00,0x00,0x00,0x00,0x00},/*"2",18*/ +{0x00,0x00,0x00,0x01,0xC0,0xE0,0x03,0xC0,0xF0,0x04,0x00,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x06,0x18,0x08,0x03,0xF4,0x18,0x01,0xE7,0xF0,0x00,0x01,0xE0,0x00,0x00,0x00,0x00,0x00,0x00},/*"3",19*/ +{0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x0D,0x00,0x00,0x11,0x00,0x00,0x61,0x00,0x00,0x81,0x08,0x03,0x01,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x01,0x08,0x00,0x01,0x08,0x00,0x00,0x00},/*"4",20*/ +{0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0xFC,0xD0,0x06,0x08,0x08,0x06,0x10,0x08,0x06,0x10,0x08,0x06,0x10,0x08,0x06,0x18,0x38,0x06,0x0F,0xF0,0x06,0x07,0xC0,0x00,0x00,0x00,0x00,0x00,0x00},/*"5",21*/ +{0x00,0x00,0x00,0x00,0x3F,0x80,0x01,0xFF,0xE0,0x03,0x84,0x30,0x02,0x08,0x18,0x04,0x10,0x08,0x04,0x10,0x08,0x04,0x10,0x08,0x07,0x18,0x10,0x03,0x0F,0xF0,0x00,0x07,0xC0,0x00,0x00,0x00},/*"6",22*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xC0,0x00,0x07,0x00,0x00,0x06,0x00,0x00,0x06,0x00,0xF8,0x06,0x07,0xF8,0x06,0x18,0x00,0x06,0xE0,0x00,0x07,0x00,0x00,0x06,0x00,0x00,0x00,0x00,0x00},/*"7",23*/ +{0x00,0x00,0x00,0x01,0xE1,0xE0,0x03,0xF7,0xF0,0x06,0x34,0x10,0x04,0x18,0x08,0x04,0x18,0x08,0x04,0x0C,0x08,0x04,0x0C,0x08,0x06,0x16,0x18,0x03,0xF3,0xF0,0x01,0xC1,0xE0,0x00,0x00,0x00},/*"8",24*/ +{0x00,0x00,0x00,0x00,0xF8,0x00,0x03,0xFC,0x30,0x03,0x06,0x38,0x04,0x02,0x08,0x04,0x02,0x08,0x04,0x02,0x08,0x04,0x04,0x10,0x03,0x08,0xF0,0x01,0xFF,0xC0,0x00,0x7F,0x00,0x00,0x00,0x00},/*"9",25*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0x38,0x00,0x70,0x38,0x00,0x70,0x38,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x1A,0x00,0x30,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x14,0x00,0x00,0x22,0x00,0x00,0x41,0x00,0x00,0x80,0x80,0x01,0x00,0x40,0x02,0x00,0x20,0x04,0x00,0x10,0x08,0x00,0x08,0x00,0x00,0x00},/*"<",28*/ +{0x00,0x00,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x21,0x00,0x00,0x00,0x00},/*"=",29*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x08,0x04,0x00,0x10,0x02,0x00,0x20,0x01,0x00,0x40,0x00,0x80,0x80,0x00,0x41,0x00,0x00,0x22,0x00,0x00,0x14,0x00,0x00,0x08,0x00,0x00,0x00,0x00},/*">",30*/ +{0x00,0x00,0x00,0x03,0xC0,0x00,0x04,0xC0,0x00,0x04,0x00,0x00,0x08,0x00,0x38,0x08,0x0F,0x38,0x08,0x08,0x38,0x08,0x10,0x00,0x0C,0x30,0x00,0x07,0xE0,0x00,0x03,0xC0,0x00,0x00,0x00,0x00},/*"?",31*/ +{0x00,0x00,0x00,0x00,0x3F,0x80,0x00,0xFF,0xE0,0x03,0x80,0x70,0x02,0x0F,0x10,0x06,0x70,0x88,0x04,0xC0,0x88,0x04,0x83,0x08,0x04,0x7F,0x88,0x02,0xC0,0x90,0x03,0x01,0x20,0x00,0xFE,0x40},/*"@",32*/ +{0x00,0x00,0x08,0x00,0x00,0x18,0x00,0x01,0xF8,0x00,0x3E,0x08,0x01,0xC2,0x00,0x07,0x02,0x00,0x07,0xE2,0x00,0x00,0xFE,0x00,0x00,0x1F,0xC8,0x00,0x01,0xF8,0x00,0x00,0x38,0x00,0x00,0x08},/*"A",33*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x06,0x18,0x08,0x03,0xF4,0x18,0x01,0xE7,0xF0,0x00,0x01,0xE0,0x00,0x00,0x00},/*"B",34*/ +{0x00,0x00,0x00,0x00,0x3F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x02,0x00,0x18,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x10,0x06,0x00,0x20,0x07,0x80,0xC0,0x00,0x00,0x00},/*"C",35*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x18,0x02,0x00,0x10,0x03,0x80,0x70,0x01,0xFF,0xE0,0x00,0x7F,0x80,0x00,0x00,0x00},/*"D",36*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x08,0x08,0x04,0x3E,0x08,0x04,0x00,0x08,0x06,0x00,0x18,0x01,0x00,0x60,0x00,0x00,0x00},/*"E",37*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x00,0x04,0x08,0x00,0x04,0x08,0x00,0x04,0x3E,0x00,0x06,0x00,0x00,0x06,0x00,0x00,0x01,0x80,0x00,0x00,0x00,0x00},/*"F",38*/ +{0x00,0x00,0x00,0x00,0x3F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x18,0x04,0x00,0x08,0x04,0x02,0x08,0x04,0x02,0x08,0x02,0x03,0xF0,0x07,0x83,0xF0,0x00,0x02,0x00,0x00,0x02,0x00},/*"G",39*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x04,0x08,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08},/*"H",40*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"I",41*/ +{0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x07,0x00,0x00,0x01,0x04,0x00,0x01,0x04,0x00,0x01,0x04,0x00,0x03,0x07,0xFF,0xFE,0x07,0xFF,0xFC,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00},/*"J",42*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x0C,0x08,0x00,0x18,0x00,0x00,0x3E,0x00,0x04,0xC7,0x80,0x05,0x03,0xC8,0x06,0x00,0xF8,0x04,0x00,0x38,0x04,0x00,0x18,0x00,0x00,0x08},/*"K",43*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x18,0x00,0x00,0x60,0x00,0x00,0x00},/*"L",44*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0x80,0x08,0x07,0xFC,0x00,0x00,0x7F,0xC0,0x00,0x03,0xF8,0x00,0x07,0xC0,0x00,0x78,0x00,0x07,0x80,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08},/*"M",45*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0x00,0x08,0x03,0xC0,0x00,0x00,0xE0,0x00,0x00,0x38,0x00,0x00,0x1E,0x00,0x00,0x07,0x00,0x00,0x01,0xC0,0x04,0x00,0xF0,0x07,0xFF,0xF8,0x04,0x00,0x00},/*"N",46*/ +{0x00,0x00,0x00,0x00,0x7F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x18,0x04,0x00,0x08,0x04,0x00,0x08,0x06,0x00,0x18,0x03,0x00,0x30,0x01,0xFF,0xE0,0x00,0x7F,0x80,0x00,0x00,0x00},/*"O",47*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x04,0x08,0x04,0x04,0x00,0x04,0x04,0x00,0x04,0x04,0x00,0x04,0x04,0x00,0x06,0x0C,0x00,0x03,0xF8,0x00,0x01,0xF0,0x00,0x00,0x00,0x00},/*"P",48*/ +{0x00,0x00,0x00,0x00,0x7F,0x80,0x01,0xFF,0xE0,0x03,0x80,0x70,0x06,0x00,0x88,0x04,0x00,0x88,0x04,0x00,0xC8,0x06,0x00,0x3C,0x03,0x00,0x3E,0x01,0xFF,0xE6,0x00,0x7F,0x84,0x00,0x00,0x00},/*"Q",49*/ +{0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x08,0x08,0x04,0x08,0x00,0x04,0x0C,0x00,0x04,0x0F,0x00,0x04,0x0B,0xC0,0x06,0x10,0xF0,0x03,0xF0,0x38,0x01,0xE0,0x08,0x00,0x00,0x08},/*"R",50*/ +{0x00,0x00,0x00,0x01,0xE0,0xF8,0x03,0xF0,0x30,0x06,0x30,0x10,0x04,0x18,0x08,0x04,0x18,0x08,0x04,0x0C,0x08,0x04,0x0C,0x08,0x02,0x06,0x18,0x02,0x07,0xF0,0x07,0x81,0xE0,0x00,0x00,0x00},/*"S",51*/ +{0x01,0x80,0x00,0x06,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x08,0x07,0xFF,0xF8,0x07,0xFF,0xF8,0x04,0x00,0x08,0x04,0x00,0x00,0x04,0x00,0x00,0x06,0x00,0x00,0x01,0x80,0x00},/*"T",52*/ +{0x04,0x00,0x00,0x07,0xFF,0xE0,0x07,0xFF,0xF0,0x04,0x00,0x18,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x04,0x00,0x10,0x07,0xFF,0xE0,0x04,0x00,0x00},/*"U",53*/ +{0x04,0x00,0x00,0x06,0x00,0x00,0x07,0xE0,0x00,0x07,0xFE,0x00,0x04,0x1F,0xE0,0x00,0x01,0xF8,0x00,0x00,0x38,0x00,0x01,0xE0,0x04,0x3E,0x00,0x07,0xC0,0x00,0x06,0x00,0x00,0x04,0x00,0x00},/*"V",54*/ +{0x04,0x00,0x00,0x07,0xE0,0x00,0x07,0xFF,0xC0,0x04,0x1F,0xF8,0x00,0x07,0xC0,0x07,0xF8,0x00,0x07,0xFF,0x80,0x04,0x3F,0xF8,0x00,0x07,0xC0,0x04,0xF8,0x00,0x07,0x00,0x00,0x04,0x00,0x00},/*"W",55*/ +{0x00,0x00,0x00,0x04,0x00,0x08,0x06,0x00,0x18,0x07,0xC0,0x78,0x05,0xF1,0xC8,0x00,0x3E,0x00,0x00,0x1F,0x80,0x04,0x63,0xE8,0x07,0x80,0xF8,0x06,0x00,0x18,0x04,0x00,0x08,0x00,0x00,0x00},/*"X",56*/ +{0x04,0x00,0x00,0x06,0x00,0x00,0x07,0x80,0x00,0x07,0xE0,0x08,0x04,0x7C,0x08,0x00,0x1F,0xF8,0x00,0x07,0xF8,0x00,0x18,0x08,0x04,0xE0,0x08,0x07,0x00,0x00,0x06,0x00,0x00,0x04,0x00,0x00},/*"Y",57*/ +{0x00,0x00,0x00,0x01,0x00,0x08,0x06,0x00,0x38,0x04,0x00,0xF8,0x04,0x03,0xE8,0x04,0x0F,0x08,0x04,0x7C,0x08,0x05,0xF0,0x08,0x07,0xC0,0x08,0x07,0x00,0x18,0x04,0x00,0x60,0x00,0x00,0x00},/*"Z",58*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0xFF,0xFE,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x00,0x00,0x00},/*"[",59*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x07,0x00,0x00,0x00,0xC0,0x00,0x00,0x38,0x00,0x00,0x06,0x00,0x00,0x01,0xC0,0x00,0x00,0x30,0x00,0x00,0x0E,0x00,0x00,0x01,0x00,0x00,0x00},/*"\",60*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x20,0x00,0x02,0x3F,0xFF,0xFE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"]",61*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x10,0x00,0x00,0x30,0x00,0x00,0x20,0x00,0x00,0x30,0x00,0x00,0x10,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"^",62*/ +{0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01,0x00,0x00,0x01},/*"_",63*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x10,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/ +{0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x19,0xF8,0x00,0x1B,0x18,0x00,0x22,0x08,0x00,0x26,0x08,0x00,0x24,0x08,0x00,0x24,0x10,0x00,0x3F,0xF8,0x00,0x1F,0xF8,0x00,0x00,0x08,0x00,0x00,0x18},/*"a",65*/ +{0x00,0x00,0x00,0x04,0x00,0x00,0x07,0xFF,0xF8,0x0F,0xFF,0xF0,0x00,0x18,0x18,0x00,0x10,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x30,0x18,0x00,0x1F,0xF0,0x00,0x0F,0xC0,0x00,0x00,0x00},/*"b",66*/ +{0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x18,0x30,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x3C,0x08,0x00,0x1C,0x10,0x00,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00},/*"c",67*/ +{0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x38,0x18,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x04,0x10,0x10,0x07,0xFF,0xF8,0x0F,0xFF,0xF0,0x00,0x00,0x10,0x00,0x00,0x00},/*"d",68*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x12,0x30,0x00,0x22,0x18,0x00,0x22,0x08,0x00,0x22,0x08,0x00,0x32,0x08,0x00,0x1E,0x10,0x00,0x0E,0x20,0x00,0x00,0x00},/*"e",69*/ +{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x20,0x08,0x00,0x20,0x08,0x01,0xFF,0xF8,0x03,0xFF,0xF8,0x06,0x20,0x08,0x04,0x20,0x08,0x04,0x20,0x08,0x07,0x20,0x00,0x03,0x00,0x00,0x00,0x00,0x00},/*"f",70*/ +{0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x0E,0x6E,0x00,0x1F,0xF3,0x00,0x31,0xB1,0x00,0x20,0xB1,0x00,0x20,0xB1,0x00,0x31,0x91,0x00,0x1F,0x13,0x00,0x2E,0x1E,0x00,0x20,0x0E,0x00,0x30,0x00},/*"g",71*/ +{0x00,0x00,0x00,0x04,0x00,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x10,0x08,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x1F,0xF8,0x00,0x00,0x08,0x00,0x00,0x00},/*"h",72*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x06,0x3F,0xF8,0x06,0x3F,0xF8,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"i",73*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x03,0x00,0x20,0x01,0x00,0x20,0x01,0x00,0x20,0x03,0x06,0x3F,0xFE,0x06,0x3F,0xFC,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"j",74*/ +{0x00,0x00,0x00,0x04,0x00,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x01,0x88,0x00,0x03,0x00,0x00,0x2F,0xC0,0x00,0x38,0xF8,0x00,0x20,0x38,0x00,0x20,0x08,0x00,0x00,0x08,0x00,0x00,0x00},/*"k",75*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x08,0x04,0x00,0x08,0x04,0x00,0x08,0x07,0xFF,0xF8,0x0F,0xFF,0xF8,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00},/*"l",76*/ +{0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x10,0x08,0x00,0x20,0x00,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x10,0x08,0x00,0x20,0x00,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x00,0x08},/*"m",77*/ +{0x00,0x00,0x00,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x10,0x08,0x00,0x10,0x00,0x00,0x20,0x00,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x1F,0xF8,0x00,0x00,0x08,0x00,0x00,0x00},/*"n",78*/ +{0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x0F,0xF0,0x00,0x18,0x30,0x00,0x30,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x30,0x08,0x00,0x18,0x30,0x00,0x0F,0xF0,0x00,0x07,0xC0,0x00,0x00,0x00},/*"o",79*/ +{0x00,0x00,0x00,0x00,0x20,0x01,0x00,0x3F,0xFF,0x00,0x3F,0xFF,0x00,0x10,0x11,0x00,0x20,0x09,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x30,0x38,0x00,0x1F,0xF0,0x00,0x0F,0xC0,0x00,0x00,0x00},/*"p",80*/ +{0x00,0x00,0x00,0x00,0x07,0xC0,0x00,0x1F,0xF0,0x00,0x38,0x18,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x09,0x00,0x10,0x11,0x00,0x1F,0xFF,0x00,0x3F,0xFF,0x00,0x00,0x01,0x00,0x00,0x00},/*"q",81*/ +{0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x3F,0xF8,0x00,0x3F,0xF8,0x00,0x08,0x08,0x00,0x10,0x08,0x00,0x20,0x08,0x00,0x20,0x00,0x00,0x30,0x00,0x00,0x30,0x00,0x00,0x00,0x00},/*"r",82*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0x78,0x00,0x1E,0x18,0x00,0x33,0x08,0x00,0x23,0x08,0x00,0x21,0x08,0x00,0x21,0x88,0x00,0x21,0x98,0x00,0x30,0xF0,0x00,0x38,0x60,0x00,0x00,0x00},/*"s",83*/ +{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0xFF,0xF0,0x03,0xFF,0xF8,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00,0x00},/*"t",84*/ +{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x3F,0xF0,0x00,0x7F,0xF8,0x00,0x00,0x18,0x00,0x00,0x08,0x00,0x00,0x08,0x00,0x20,0x10,0x00,0x3F,0xF8,0x00,0x7F,0xF0,0x00,0x00,0x10,0x00,0x00,0x00},/*"u",85*/ +{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x30,0x00,0x00,0x3C,0x00,0x00,0x3F,0x80,0x00,0x23,0xF0,0x00,0x00,0x78,0x00,0x00,0x70,0x00,0x23,0x80,0x00,0x3C,0x00,0x00,0x30,0x00,0x00,0x20,0x00},/*"v",86*/ +{0x00,0x20,0x00,0x00,0x3C,0x00,0x00,0x3F,0xE0,0x00,0x23,0xF8,0x00,0x00,0xE0,0x00,0x27,0x00,0x00,0x3E,0x00,0x00,0x3F,0xE0,0x00,0x21,0xF8,0x00,0x01,0xE0,0x00,0x3E,0x00,0x00,0x20,0x00},/*"w",87*/ +{0x00,0x00,0x00,0x00,0x20,0x08,0x00,0x20,0x08,0x00,0x38,0x38,0x00,0x3E,0x68,0x00,0x27,0x80,0x00,0x03,0xC8,0x00,0x2C,0xF8,0x00,0x38,0x38,0x00,0x20,0x18,0x00,0x20,0x08,0x00,0x00,0x00},/*"x",88*/ +{0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x30,0x03,0x00,0x3C,0x01,0x00,0x3F,0x83,0x00,0x23,0xEC,0x00,0x00,0x70,0x00,0x23,0x80,0x00,0x3C,0x00,0x00,0x20,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"y",89*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x08,0x00,0x20,0x38,0x00,0x20,0xF8,0x00,0x23,0xE8,0x00,0x2F,0x88,0x00,0x3E,0x08,0x00,0x38,0x08,0x00,0x20,0x18,0x00,0x00,0x70,0x00,0x00,0x00},/*"z",90*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x14,0x00,0x1F,0xF7,0xFC,0x30,0x00,0x06,0x20,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00},/*"{",91*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"|",92*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x02,0x30,0x00,0x06,0x1F,0xF7,0xFC,0x00,0x14,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"}",93*/ +{0x00,0x00,0x00,0x18,0x00,0x00,0x60,0x00,0x00,0x40,0x00,0x00,0x40,0x00,0x00,0x20,0x00,0x00,0x10,0x00,0x00,0x08,0x00,0x00,0x04,0x00,0x00,0x04,0x00,0x00,0x0C,0x00,0x00,0x10,0x00,0x00},/*"~",94*/ +}; + +//32*32 ASCII字符集点阵 +const unsigned char asc2_3216[95][128]={ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xF0,0x00,0xC0,0x07,0xFF,0xE1,0xE0,0x07,0xF0,0x01,0xE0,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x01,0xC0,0x00,0x00,0x07,0x80,0x00,0x00,0x1F,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x1C,0x20,0x00,0x00,0x01,0xC0,0x00,0x00,0x07,0x80,0x00,0x00,0x1F,0x00,0x00,0x00,0x1E,0x00,0x00,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*""",2*/ +{0x00,0x00,0x00,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0F,0xE0,0x00,0x1F,0xFC,0x00,0x03,0xF8,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0F,0xE0,0x00,0x1F,0xFC,0x00,0x03,0xF8,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x18,0x0C,0x00,0x00,0x00,0x00,0x00},/*"#",3*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x80,0x00,0x78,0x07,0xC0,0x00,0xFC,0x06,0x40,0x01,0x0E,0x00,0x20,0x03,0x07,0x00,0x20,0x02,0x03,0x80,0x20,0x0F,0xFF,0xFF,0xFC,0x02,0x01,0xC0,0x20,0x02,0x00,0xE0,0x60,0x01,0x30,0x70,0x40,0x01,0xF0,0x3F,0x80,0x00,0xF0,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"$",4*/ +{0x00,0xFE,0x00,0x00,0x01,0xFF,0x00,0x00,0x03,0x01,0x80,0x00,0x02,0x00,0x80,0x60,0x03,0x01,0x81,0xC0,0x01,0xFF,0x07,0x00,0x00,0xFE,0x18,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0xBF,0x00,0x00,0x0C,0xFF,0xC0,0x00,0x71,0x80,0x60,0x01,0xC1,0x00,0x20,0x03,0x01,0x80,0x60,0x00,0x00,0xFF,0xC0,0x00,0x00,0x3F,0x00,0x00,0x00,0x00,0x00},/*"%",5*/ +{0x00,0x00,0x1F,0x00,0x00,0x00,0x7F,0xC0,0x00,0xFC,0xC0,0xC0,0x01,0xFF,0x80,0x60,0x03,0x03,0xE0,0x20,0x02,0x02,0x78,0x20,0x02,0x06,0x1E,0x20,0x03,0xFC,0x07,0x40,0x01,0xF0,0x03,0x80,0x00,0x01,0x03,0xC0,0x00,0x01,0x1C,0x60,0x00,0x01,0xE0,0x20,0x00,0x01,0x00,0x20,0x00,0x01,0x00,0x40,0x00,0x00,0x01,0x80,0x00,0x00,0x00,0x00},/*"&",6*/ +{0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x1C,0x60,0x00,0x00,0x1C,0x40,0x00,0x00,0x1F,0x80,0x00,0x00,0x0F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xF8,0x00,0x00,0x3F,0xFF,0x00,0x00,0x78,0x07,0xC0,0x01,0xC0,0x00,0xE0,0x03,0x00,0x00,0x30,0x04,0x00,0x00,0x08,0x08,0x00,0x00,0x04,0x10,0x00,0x00,0x02,0x00,0x00,0x00,0x00},/*"(",8*/ +{0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x02,0x08,0x00,0x00,0x04,0x04,0x00,0x00,0x08,0x03,0x00,0x00,0x30,0x01,0xC0,0x00,0xE0,0x00,0x78,0x07,0xC0,0x00,0x3F,0xFF,0x00,0x00,0x07,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*")",9*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0x18,0x00,0x00,0x0E,0x38,0x00,0x00,0x0E,0x38,0x00,0x00,0x06,0x30,0x00,0x00,0x03,0x60,0x00,0x00,0x61,0x43,0x80,0x00,0xFF,0xFF,0x80,0x00,0x61,0x43,0x00,0x00,0x03,0x60,0x00,0x00,0x06,0x30,0x00,0x00,0x0E,0x38,0x00,0x00,0x0E,0x38,0x00,0x00,0x0C,0x18,0x00,0x00,0x00,0x00,0x00},/*"*",10*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x7F,0xFF,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00},/*"+",11*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0xE3,0x00,0x00,0x00,0xE2,0x00,0x00,0x00,0xFC,0x00,0x00,0x00,0x78,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*",",12*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00},/*"-",13*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x00,0x00,0x01,0xE0,0x00,0x00,0x01,0xE0,0x00,0x00,0x00,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x0E,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x0E,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x0E,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"/",15*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x7F,0xFF,0x00,0x00,0xF0,0x07,0x80,0x01,0x80,0x00,0xC0,0x03,0x00,0x00,0x60,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0x00,0x00,0x60,0x01,0x80,0x00,0xC0,0x00,0xE0,0x03,0x80,0x00,0x7F,0xFF,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x00,0x00},/*"0",16*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x20,0x00,0x80,0x00,0x20,0x00,0x80,0x00,0x20,0x00,0x80,0x00,0x60,0x01,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"1",17*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x00,0xE0,0x00,0x98,0x01,0x60,0x01,0x00,0x02,0x60,0x02,0x00,0x04,0x60,0x02,0x00,0x08,0x60,0x02,0x00,0x10,0x60,0x02,0x00,0x20,0x60,0x02,0x00,0x40,0x60,0x03,0x00,0x80,0x60,0x01,0x83,0x00,0x60,0x01,0xFE,0x00,0xE0,0x00,0x7C,0x07,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"2",18*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0x80,0x01,0xF0,0x07,0xC0,0x01,0x00,0x00,0x40,0x02,0x00,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x03,0x03,0x80,0x20,0x01,0x86,0x80,0x40,0x01,0xFC,0xC0,0xC0,0x00,0x78,0x7F,0x80,0x00,0x00,0x1E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"3",19*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x48,0x00,0x00,0x01,0x88,0x00,0x00,0x06,0x08,0x00,0x00,0x0C,0x08,0x10,0x00,0x30,0x08,0x10,0x00,0x40,0x08,0x10,0x01,0xFF,0xFF,0xF0,0x03,0xFF,0xFF,0xF0,0x03,0xFF,0xFF,0xF0,0x00,0x00,0x08,0x10,0x00,0x00,0x08,0x10,0x00,0x00,0x08,0x10,0x00,0x00,0x00,0x00},/*"4",20*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x80,0x00,0x1F,0x86,0x40,0x03,0xE1,0x00,0x20,0x03,0x02,0x00,0x20,0x03,0x04,0x00,0x20,0x03,0x04,0x00,0x20,0x03,0x04,0x00,0x20,0x03,0x04,0x00,0x20,0x03,0x06,0x00,0x40,0x03,0x03,0x01,0xC0,0x03,0x01,0xFF,0x80,0x03,0x00,0x7E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"5",21*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0xFC,0x00,0x00,0x3F,0xFF,0x00,0x00,0x70,0xC3,0x80,0x00,0x81,0x80,0xC0,0x01,0x01,0x00,0x60,0x03,0x02,0x00,0x20,0x02,0x02,0x00,0x20,0x02,0x02,0x00,0x20,0x02,0x02,0x00,0x20,0x02,0x03,0x00,0x40,0x01,0xC1,0x80,0xC0,0x00,0xC0,0xFF,0x80,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00},/*"6",22*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x00,0x03,0xC0,0x00,0x00,0x03,0x80,0x00,0x00,0x03,0x00,0x00,0x00,0x03,0x00,0x07,0xE0,0x03,0x00,0x3F,0xE0,0x03,0x01,0xC0,0x00,0x03,0x06,0x00,0x00,0x03,0x18,0x00,0x00,0x03,0x60,0x00,0x00,0x03,0x80,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"7",23*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x00,0x00,0x78,0x3F,0x80,0x00,0xFC,0x60,0xC0,0x01,0x8E,0xC0,0x40,0x03,0x07,0x80,0x20,0x02,0x03,0x00,0x20,0x02,0x01,0x80,0x20,0x02,0x01,0x80,0x20,0x02,0x01,0xC0,0x20,0x03,0x01,0xE0,0x40,0x01,0x86,0x70,0xC0,0x00,0xFC,0x3F,0x80,0x00,0x78,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"8",24*/ +{0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x00,0x00,0xFF,0x81,0xC0,0x01,0xC0,0xC1,0xC0,0x01,0x00,0x60,0x20,0x02,0x00,0x20,0x20,0x02,0x00,0x20,0x20,0x02,0x00,0x20,0x20,0x02,0x00,0x20,0x60,0x02,0x00,0x40,0xC0,0x01,0x00,0xC1,0x80,0x00,0xC1,0x8F,0x00,0x00,0x7F,0xFE,0x00,0x00,0x1F,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"9",25*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0xC0,0x00,0x07,0x81,0xE0,0x00,0x07,0x81,0xE0,0x00,0x03,0x00,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x66,0x00,0x06,0x00,0x78,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*";",27*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x01,0xC0,0x00,0x00,0x03,0x60,0x00,0x00,0x06,0x30,0x00,0x00,0x0C,0x18,0x00,0x00,0x18,0x0C,0x00,0x00,0x30,0x06,0x00,0x00,0x60,0x03,0x00,0x00,0xC0,0x01,0x80,0x01,0x00,0x00,0x40,0x02,0x00,0x00,0x20,0x04,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"<",28*/ +{0x00,0x00,0x00,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x04,0x10,0x00,0x00,0x00,0x00,0x00},/*"=",29*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x10,0x02,0x00,0x00,0x20,0x01,0x00,0x00,0x40,0x00,0xC0,0x01,0x80,0x00,0x60,0x03,0x00,0x00,0x30,0x06,0x00,0x00,0x18,0x0C,0x00,0x00,0x0C,0x18,0x00,0x00,0x06,0x30,0x00,0x00,0x03,0x60,0x00,0x00,0x01,0xC0,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*">",30*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x00,0x00,0x01,0xF8,0x00,0x00,0x02,0x38,0x00,0x00,0x02,0x00,0x00,0x00,0x04,0x00,0x00,0xC0,0x04,0x00,0x79,0xE0,0x04,0x00,0x81,0xE0,0x04,0x01,0x00,0xC0,0x04,0x03,0x00,0x00,0x02,0x02,0x00,0x00,0x03,0x06,0x00,0x00,0x01,0xFC,0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00,0x00,0x00},/*"?",31*/ +{0x00,0x00,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x3F,0xFE,0x00,0x00,0x70,0x07,0x80,0x00,0xC0,0x00,0xC0,0x01,0x01,0xF8,0x40,0x03,0x07,0xFC,0x20,0x02,0x1E,0x04,0x20,0x02,0x30,0x08,0x20,0x02,0x20,0x30,0x20,0x02,0x3F,0xFC,0x20,0x01,0x3F,0x04,0x40,0x01,0x80,0x0C,0xC0,0x00,0xE0,0x31,0x80,0x00,0x1F,0xC2,0x00,0x00,0x00,0x00,0x00},/*"@",32*/ +{0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x60,0x00,0x00,0x03,0xE0,0x00,0x00,0x3E,0x20,0x00,0x03,0xE0,0x20,0x00,0x3E,0x20,0x00,0x03,0xE0,0x20,0x00,0x03,0x80,0x20,0x00,0x07,0xFC,0x20,0x00,0x00,0x3F,0xE0,0x00,0x00,0x03,0xFE,0x20,0x00,0x00,0x3F,0xE0,0x00,0x00,0x01,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"A",33*/ +{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x03,0x03,0x00,0x20,0x01,0x86,0x80,0x60,0x01,0xFC,0xC0,0xC0,0x00,0xF8,0x7F,0x80,0x00,0x00,0x1F,0x00,0x00,0x00,0x00,0x00},/*"B",34*/ +{0x00,0x00,0x00,0x00,0x00,0x07,0xF8,0x00,0x00,0x3F,0xFF,0x00,0x00,0x70,0x07,0x80,0x00,0xC0,0x00,0xC0,0x01,0x00,0x00,0x40,0x03,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x01,0x00,0x00,0x40,0x01,0x80,0x00,0xC0,0x03,0xC0,0x01,0x80,0x00,0x30,0x06,0x00,0x00,0x00,0x00,0x00},/*"C",35*/ +{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0x00,0x00,0x60,0x01,0x00,0x00,0x40,0x01,0x80,0x00,0xC0,0x00,0xF0,0x07,0x80,0x00,0x7F,0xFE,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x00,0x00},/*"D",36*/ +{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x03,0x80,0x20,0x02,0x0F,0xE0,0x20,0x03,0x00,0x00,0x60,0x03,0xC0,0x00,0xE0,0x00,0x60,0x03,0x00,0x00,0x00,0x00,0x00},/*"E",37*/ +{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x20,0x02,0x01,0x00,0x00,0x02,0x01,0x00,0x00,0x02,0x01,0x00,0x00,0x02,0x01,0x00,0x00,0x02,0x03,0x80,0x00,0x03,0x0F,0xE0,0x00,0x03,0x00,0x00,0x00,0x03,0xC0,0x00,0x00,0x00,0x60,0x00,0x00},/*"F",38*/ +{0x00,0x00,0x00,0x00,0x00,0x07,0xF8,0x00,0x00,0x3F,0xFE,0x00,0x00,0x70,0x07,0x80,0x01,0xC0,0x01,0xC0,0x01,0x00,0x00,0x40,0x03,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x01,0x00,0x20,0x20,0x01,0x00,0x20,0x40,0x03,0xC0,0x3F,0x80,0x00,0x30,0x3F,0x80,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00},/*"G",39*/ +{0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x80,0x20,0x02,0x00,0x80,0x20,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x02,0x00,0x80,0x20,0x02,0x00,0x80,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"H",40*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"I",41*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x00,0x00,0x00,0x0F,0x00,0x00,0x00,0x0F,0x00,0x00,0x00,0x01,0x02,0x00,0x00,0x01,0x02,0x00,0x00,0x01,0x02,0x00,0x00,0x03,0x02,0x00,0x00,0x06,0x03,0xFF,0xFF,0xFC,0x03,0xFF,0xFF,0xF8,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"J",42*/ +{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0xC0,0x20,0x02,0x01,0x00,0x20,0x00,0x07,0x80,0x00,0x00,0x0F,0xE0,0x00,0x00,0x30,0xF8,0x00,0x02,0x60,0x3E,0x20,0x03,0x80,0x0F,0x20,0x03,0x00,0x03,0xE0,0x02,0x00,0x00,0xE0,0x02,0x00,0x00,0x20,0x00,0x00,0x00,0x20},/*"K",43*/ +{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0xE0,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00},/*"L",44*/ +{0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xE0,0x00,0x20,0x03,0xFF,0x00,0x20,0x00,0x1F,0xF0,0x00,0x00,0x01,0xFF,0x80,0x00,0x00,0x0F,0xE0,0x00,0x00,0x1E,0x00,0x00,0x03,0xE0,0x00,0x00,0x3E,0x00,0x20,0x03,0xE0,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20},/*"M",45*/ +{0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x03,0x80,0x00,0x20,0x03,0xF0,0x00,0x20,0x00,0xFC,0x00,0x00,0x00,0x1F,0x00,0x00,0x00,0x07,0xC0,0x00,0x00,0x01,0xF0,0x00,0x00,0x00,0x7C,0x00,0x02,0x00,0x1F,0x80,0x02,0x00,0x07,0xE0,0x03,0xFF,0xFF,0xE0,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"N",46*/ +{0x00,0x00,0x00,0x00,0x00,0x0F,0xF8,0x00,0x00,0x3F,0xFE,0x00,0x00,0xF0,0x07,0x80,0x01,0x80,0x00,0xC0,0x01,0x00,0x00,0x40,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x01,0x00,0x00,0x40,0x01,0x80,0x00,0xC0,0x00,0xF0,0x03,0x80,0x00,0x3F,0xFE,0x00,0x00,0x0F,0xF8,0x00,0x00,0x00,0x00,0x00},/*"O",47*/ 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+{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x7F,0xFF,0xE0,0x01,0xFF,0xFF,0xE0,0x01,0x04,0x00,0x20,0x03,0x04,0x00,0x20,0x02,0x04,0x00,0x20,0x02,0x04,0x00,0x20,0x02,0x04,0x00,0x00,0x02,0x00,0x00,0x00,0x01,0xC0,0x00,0x00,0x01,0xC0,0x00,0x00},/*"f",70*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x00,0x00,0xE3,0x3E,0x00,0x03,0xFF,0xC2,0x00,0x02,0x0C,0xC3,0x00,0x04,0x04,0xC1,0x00,0x04,0x04,0xC1,0x00,0x04,0x04,0xC1,0x00,0x04,0x04,0xC1,0x00,0x06,0x0C,0xC1,0x00,0x03,0xF8,0xC3,0x00,0x05,0xF0,0x62,0x00,0x06,0x00,0x7E,0x00,0x06,0x00,0x3C,0x00,0x00,0x00,0x00},/*"g",71*/ +{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xE0,0x00,0x01,0x00,0x20,0x00,0x02,0x00,0x20,0x00,0x06,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x20,0x00,0x03,0xFF,0xE0,0x00,0x01,0xFF,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20},/*"h",72*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x03,0x87,0xFF,0xE0,0x03,0x8F,0xFF,0xE0,0x03,0x80,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"i",73*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x04,0x00,0x01,0x00,0x04,0x00,0x01,0x00,0x04,0x00,0x03,0x00,0x04,0x00,0x06,0x03,0x87,0xFF,0xFC,0x03,0x8F,0xFF,0xF8,0x03,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"j",74*/ +{0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xE0,0x00,0x00,0x08,0x20,0x00,0x00,0x10,0x20,0x00,0x00,0x30,0x00,0x00,0x00,0xFC,0x00,0x00,0x05,0x8E,0x00,0x00,0x07,0x07,0xA0,0x00,0x06,0x01,0xE0,0x00,0x04,0x00,0xE0,0x00,0x04,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"k",75*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x02,0x00,0x00,0x20,0x03,0xFF,0xFF,0xE0,0x07,0xFF,0xFF,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"l",76*/ +{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x07,0xFF,0xE0,0x00,0x0F,0xFF,0xE0,0x00,0x02,0x00,0x20,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x07,0xFF,0xE0,0x00,0x03,0xFF,0xE0,0x00,0x02,0x00,0x20,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x07,0xFF,0xE0,0x00,0x03,0xFF,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"m",77*/ +{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x07,0xFF,0xE0,0x00,0x0F,0xFF,0xE0,0x00,0x01,0x00,0x20,0x00,0x02,0x00,0x20,0x00,0x02,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x20,0x00,0x03,0xFF,0xE0,0x00,0x01,0xFF,0xE0,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20},/*"n",78*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0xFF,0x80,0x00,0x03,0x81,0xC0,0x00,0x02,0x00,0x40,0x00,0x06,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x20,0x00,0x02,0x00,0x40,0x00,0x03,0x81,0xC0,0x00,0x01,0xFF,0x80,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00},/*"o",79*/ +{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x01,0x00,0x04,0x00,0x01,0x00,0x07,0xFF,0xFF,0x00,0x0F,0xFF,0xFF,0x00,0x01,0x00,0xC1,0x00,0x02,0x00,0x41,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x06,0x00,0x40,0x00,0x03,0x01,0xC0,0x00,0x01,0xFF,0x80,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00},/*"p",80*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x01,0xFF,0x80,0x00,0x03,0x80,0xC0,0x00,0x02,0x00,0x60,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x02,0x00,0x41,0x00,0x03,0x00,0xC1,0x00,0x03,0xFF,0xFF,0x00,0x07,0xFF,0xFF,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x01},/*"q",81*/ +{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x0F,0xFF,0xE0,0x00,0x0F,0xFF,0xE0,0x00,0x00,0xC0,0x20,0x00,0x01,0x00,0x20,0x00,0x02,0x00,0x20,0x00,0x06,0x00,0x20,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00},/*"r",82*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0xE0,0x00,0x01,0xC0,0xE0,0x00,0x03,0xE0,0x40,0x00,0x06,0x30,0x20,0x00,0x04,0x30,0x20,0x00,0x04,0x18,0x20,0x00,0x04,0x18,0x20,0x00,0x04,0x18,0x20,0x00,0x04,0x0C,0x20,0x00,0x02,0x0C,0x60,0x00,0x03,0x07,0xC0,0x00,0x07,0x83,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"s",83*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x1F,0xFF,0x80,0x00,0xFF,0xFF,0xC0,0x00,0x04,0x00,0x60,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x40,0x00,0x00,0x01,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"t",84*/ +{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x07,0xFF,0x80,0x00,0x0F,0xFF,0xC0,0x00,0x00,0x00,0x60,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x04,0x00,0x40,0x00,0x04,0x00,0x80,0x00,0x07,0xFF,0xE0,0x00,0x0F,0xFF,0xC0,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40},/*"u",85*/ +{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x07,0x80,0x00,0x00,0x07,0xF0,0x00,0x00,0x04,0xFE,0x00,0x00,0x04,0x1F,0xC0,0x00,0x00,0x03,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x1C,0x00,0x00,0x04,0x60,0x00,0x00,0x07,0x80,0x00,0x00,0x06,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"v",86*/ +{0x00,0x04,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0x07,0xC0,0x00,0x00,0x07,0xFC,0x00,0x00,0x04,0x3F,0x80,0x00,0x00,0x03,0xE0,0x00,0x04,0x0F,0x80,0x00,0x06,0xF0,0x00,0x00,0x07,0xF0,0x00,0x00,0x07,0xFF,0x80,0x00,0x04,0x0F,0xE0,0x00,0x00,0x03,0x80,0x00,0x04,0x3C,0x00,0x00,0x07,0xC0,0x00,0x00,0x06,0x00,0x00,0x00,0x04,0x00,0x00},/*"w",87*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x04,0x00,0x20,0x00,0x04,0x00,0x60,0x00,0x07,0x00,0xE0,0x00,0x07,0x83,0x20,0x00,0x07,0xE6,0x00,0x00,0x04,0xF8,0x00,0x00,0x00,0x3C,0x00,0x00,0x04,0x5E,0x20,0x00,0x05,0x87,0xA0,0x00,0x06,0x01,0xE0,0x00,0x04,0x00,0x60,0x00,0x04,0x00,0x20,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x00},/*"x",88*/ +{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x03,0x00,0x07,0x00,0x03,0x00,0x07,0xE0,0x01,0x00,0x04,0xF8,0x01,0x00,0x04,0x1F,0x02,0x00,0x00,0x07,0xFC,0x00,0x00,0x00,0xE0,0x00,0x00,0x07,0x00,0x00,0x04,0x38,0x00,0x00,0x07,0xC0,0x00,0x00,0x06,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00},/*"y",89*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x80,0x60,0x00,0x06,0x00,0xE0,0x00,0x04,0x03,0xE0,0x00,0x04,0x07,0xA0,0x00,0x04,0x0E,0x20,0x00,0x04,0x3C,0x20,0x00,0x04,0x70,0x20,0x00,0x05,0xE0,0x20,0x00,0x07,0x80,0x20,0x00,0x07,0x00,0x60,0x00,0x04,0x00,0xE0,0x00,0x00,0x03,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"z",90*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x01,0x40,0x00,0x07,0xFE,0x3F,0xF8,0x08,0x00,0x00,0x04,0x10,0x00,0x00,0x02,0x10,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"{",91*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"|",92*/ +{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x02,0x10,0x00,0x00,0x02,0x08,0x00,0x00,0x04,0x07,0xFE,0x3F,0xF8,0x00,0x01,0x40,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"}",93*/ +{0x00,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x0C,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"~",94*/ +}; +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/led/bsp_led.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/led/bsp_led.c new file mode 100644 index 00000000..c5ddc516 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/led/bsp_led.c @@ -0,0 +1,61 @@ +#include "bsp_led.h" +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_led.c +作者 : 左忠凯 +版本 : V1.0 +描述 : LED驱动文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯创建 +***************************************************************/ + +/* + * @description : 初始化LED对应的GPIO + * @param : 无 + * @return : 无 + */ +void led_init(void) +{ + /* 1、初始化IO复用 */ + IOMUXC_SetPinMux(IOMUXC_GPIO1_IO03_GPIO1_IO03,0); /* 复用为GPIO1_IO03 */ + + + /* 2、、配置GPIO1_IO03的IO属性 + *bit 16:0 HYS关闭 + *bit [15:14]: 00 默认下拉 + *bit [13]: 0 kepper功能 + *bit [12]: 1 pull/keeper使能 + *bit [11]: 0 关闭开路输出 + *bit [7:6]: 10 速度100Mhz + *bit [5:3]: 110 R0/6驱动能力 + *bit [0]: 0 低转换率 + */ + IOMUXC_SetPinConfig(IOMUXC_GPIO1_IO03_GPIO1_IO03,0X10B0); + + /* 3、初始化GPIO,GPIO1_IO03设置为输出*/ + GPIO1->GDIR |= (1 << 3); + + /* 4、设置GPIO1_IO03输出低电平，打开LED0*/ + GPIO1->DR &= ~(1 << 3); +} + + +/* + * @description : LED控制函数，控制LED打开还是关闭 + * @param - led : 要控制的LED灯编号 + * @param - status : 0，关闭LED0，1 打开LED0 + * @return : 无 + */ +void led_switch(int led, int status) +{ + switch(led) + { + case LED0: + if(status == ON) + GPIO1->DR &= ~(1<<3); /* 打开LED0 */ + else if(status == OFF) + GPIO1->DR |= (1<<3); /* 关闭LED0 */ + break; + } +} diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/led/bsp_led.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/led/bsp_led.h new file mode 100644 index 00000000..1cf381f9 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/led/bsp_led.h @@ -0,0 +1,21 @@ +#ifndef __BSP_LED_H +#define __BSP_LED_H +#include "bsp.h" +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_led.h +作者 : 左忠凯 +版本 : V1.0 +描述 : LED驱动头文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯创建 +***************************************************************/ + +#define LED0 0 + +/* 函数声明 */ +void led_init(void); +void led_switch(int led, int status); +#endif + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/mpu9250/bsp_mpu9250.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/mpu9250/bsp_mpu9250.c new file mode 100644 index 00000000..bdf68ee8 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/mpu9250/bsp_mpu9250.c @@ -0,0 +1,236 @@ +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_mpu9250.c +作者 : 左忠凯 +版本 : V1.0 +描述 : MPU9250驱动文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/15 左忠凯创建 +***************************************************************/ +#include "bsp_mpu9250.h" +#include "bsp_i2c.h" +#include "bsp_delay.h" +#include "printf.h" + + +/* + * @description : 初始化MPU9250 + * @param : 无 + * @return : 0 成功，其他值 错误代码 + */ +unsigned char mpu9250_init(void) +{ + unsigned char data = 0; + + i2c_init(); /* 初始化IIC */ + mpu_write_byte(MPU9250_ADDR,MPU_PWR_MGMT1_REG,0X80);//复位MPU9250 + delayms(100); //延时100ms + mpu_write_byte(MPU9250_ADDR,MPU_PWR_MGMT1_REG,0X00);//唤醒MPU9250 + mpu_set_gyro_range(3); //陀螺仪传感器,±2000dps + mpu_set_accel_range(0); //加速度传感器,±2g + mpu_set_rate(50); //设置采样率50Hz + mpu_write_byte(MPU9250_ADDR,MPU_INT_EN_REG,0X00); //关闭所有中断 + mpu_write_byte(MPU9250_ADDR,MPU_USER_CTRL_REG,0X00);//I2C主模式关闭 + mpu_write_byte(MPU9250_ADDR,MPU_FIFO_EN_REG,0X00); //关闭FIFO + mpu_write_byte(MPU9250_ADDR,MPU_INTBP_CFG_REG,0X82);//INT引脚低电平有效，开启bypass模式，可以直接读取磁力计 + + data = mpu_read_byte(MPU9250_ADDR,MPU_DEVICE_ID_REG); + if(data == MPU6500_ID) + { + printf("MPU9250 ID=%#X\r\n", data); + mpu_write_byte(MPU9250_ADDR, MPU_PWR_MGMT1_REG, 0X01); /* 设置CLKSEL,PLL X轴为参考 */ + mpu_write_byte(MPU9250_ADDR, MPU_PWR_MGMT2_REG, 0X00); /* 加速度与陀螺仪都工作 */ + mpu_set_rate(50); /* 设置采样率为50Hz */ + } + else { + return 1; + + } + + data = mpu_read_byte(AK8963_ADDR, MAG_WIA); /* 读取AK8963 ID */ + if(data == AK8963_ID) + { + printf("AK8963_ID=%#X\r\n", data); + mpu_write_byte(AK8963_ADDR, MAG_CNTL1, 0X11); /* 设置AK8963为单次测量模式 */ + }else return 2; + + return 0; +} + +/* + * @description : 向MPU9250写入数据 + * @param - addr: 设备地址 + * @param - reg : 要写入的寄存器 + * @param - data: 要写入的数据 + * @return : 操作结果 + */ +unsigned char mpu_write_byte(unsigned char addr,unsigned char reg, unsigned char data) +{ + unsigned char status=0; + unsigned char writedata=data; + struct i2c_transfer masterXfer; + + /* 配置I2C xfer结构体 */ + masterXfer.slaveAddress = addr; /* 设备地址 */ + masterXfer.direction = kI2C_Write; /* 写入数据 */ + masterXfer.subaddress = reg; /* 要写入的寄存器地址 */ + masterXfer.subaddressSize = 1; /* 地址长度一个字节 */ + masterXfer.data = &writedata; /* 要写入的数据 */ + masterXfer.dataSize = 1; /* 写入数据长度1个字节 */ + + if(i2c_master_transfer(&masterXfer)) + status=1; + + return status; +} + +/* + * @description : 从MPU9250读取一个字节的数据 + * @param - addr: 设备地址 + * @param - reg : 要读取的寄存器 + * @return : 读取到的数据。 + */ +unsigned char mpu_read_byte(unsigned char addr,unsigned char reg) +{ + unsigned char val=0; + + struct i2c_transfer masterXfer; + masterXfer.slaveAddress = addr; /* 设备地址 */ + masterXfer.direction = kI2C_Read; /* 读取数据 */ + masterXfer.subaddress = reg; /* 要读取的寄存器地址 */ + masterXfer.subaddressSize = 1; /* 地址长度一个字节 */ + masterXfer.data = &val; /* 接收数据缓冲区 */ + masterXfer.dataSize = 1; /* 读取数据长度1个字节 */ + i2c_master_transfer(&masterXfer); + + return val; +} + +/* + * @description : 从MPU9250读取多个字节的数据 + * @param - addr: 设备地址 + * @param - reg : 要读取的开始寄存器地址 + * @param - len : 要读取的数据长度. + * @param - buf : 读取到的数据缓冲区 + * @return : 无 + */ +void mpu_read_len(unsigned char addr,unsigned char reg,unsigned char len,unsigned char *buf) +{ + struct i2c_transfer masterXfer; + + masterXfer.slaveAddress = addr; /* 设备地址 */ + masterXfer.direction = kI2C_Read; /* 读取数据 */ + masterXfer.subaddress = reg; /* 要读取的寄存器地址 */ + masterXfer.subaddressSize = 1; /* 地址长度一个字节 */ + masterXfer.data = buf; /* 接收数据缓冲区 */ + masterXfer.dataSize = len; /* 读取数据长度1个字节 */ + i2c_master_transfer(&masterXfer); +} + +/* + * @description : 设置MPU9250陀螺仪量程 + * @param - range : 量程范围,0,±250dps;1,±500dps;2,±1000dps;3,±2000dps + * @return : 操作结果 0,设置成功 其他,设置失败 + */ +unsigned char mpu_set_gyro_range(unsigned char range) +{ + return mpu_write_byte(MPU9250_ADDR, MPU_GYRO_CFG_REG, range << 3);//设置陀螺仪满量程范围 +} + +/* + * @description : 设置MPU9250加速度量程 + * @param - range : 量程范围,0,±2g;1,±4g;2,±8g;3,±16g + * @return : 操作结果 0,设置成功 其他,设置失败 + */ +unsigned char mpu_set_accel_range(unsigned char range) +{ + return mpu_write_byte(MPU9250_ADDR, MPU_ACCEL_CFG_REG,range << 3);//设置加速度传感器满量程范围 +} + +/* + * @description : 设置MPU9250的数字低通滤波器 + * @param - range : 数字低通滤波频率(Hz) + * @return : 操作结果 0,设置成功 其他,设置失败 + */ +unsigned char mpu_set_lpf(unsigned short fre) +{ + unsigned char data = 0; + + if(fre >= 188) data=1; + else if(fre >= 98) data=2; + else if(fre >= 42) data=3; + else if(fre >= 20) data=4; + else if(fre >= 10) data=5; + else data = 6; + return mpu_write_byte(MPU9250_ADDR,MPU_CFG_REG,data); +} + +/* + * @description : 设置MPU9250采样率(假定Fs=1KHz) + * @param - rate: 4~1000(Hz) + * @return : 操作结果 0,设置成功 其他,设置失败 + */ +unsigned char mpu_set_rate(unsigned short rate) +{ + unsigned char data; + if(rate > 1000) rate = 1000; + if(rate < 4) rate = 4; + data = 1000 / rate - 1; + data = mpu_write_byte(MPU9250_ADDR,MPU_SAMPLE_RATE_REG,data); /* 设置数字低通滤波器 */ + return mpu_set_lpf(rate / 2); /* 自动设置LPF为采样率的一半 */ +} + +/* + * @description : 得到陀螺仪值(原始值) + * @param - gx : 陀螺仪X轴原始数据 + * @param - gy : 陀螺仪Y轴原始数据 + * @param - gz ：陀螺仪Z轴原始数据 + * @return : 0,设置成功 其他,设置失败 + */ +void mpu_get_gyroscope(short *gx,short *gy,short *gz) +{ + unsigned char buf[6]; + + mpu_read_len(MPU9250_ADDR, MPU_GYRO_XOUTH_REG, 6, buf); + *gx=((short)buf[0] << 8) | buf[1]; + *gy=((short)buf[2] << 8) | buf[3]; + *gz=((short)buf[4] << 8) | buf[5]; +} + +/* + * @description : 得到加速度原始值 + * @param - ax : 加速度X轴原始数据 + * @param - ay : 加速度Y轴原始数据 + * @param - az ：加速度Z轴原始数据 + * @return : 0,设置成功 其他,设置失败 + */ +void mpu_get_accelerometer(short *ax,short *ay,short *az) +{ + unsigned char buf[6]; + + mpu_read_len(MPU9250_ADDR, MPU_ACCEL_XOUTH_REG, 6, buf); + *ax=((short)buf[0] << 8) | buf[1]; + *ay=((short)buf[2] << 8) | buf[3]; + *az=((short)buf[4] << 8) | buf[5]; +} + +/* + * @description : 得到原始磁力计值 + * @param - mx : 磁力计X轴原始数据 + * @param - my : 磁力计Y轴原始数据 + * @param - mz ：磁力计Z轴原始数据 + * @return : 0,设置成功 其他,设置失败 + */ +void mpu_get_magnetometer(short *mx, short *my, short *mz) +{ + unsigned char buf[6]; + + mpu_read_len(AK8963_ADDR, MAG_XOUT_L , 6, buf); + *mx = ((short)buf[1] << 8) | buf[0]; + *my = ((short)buf[3] << 8) | buf[2]; + *mz = ((short)buf[5] << 8) | buf[4]; + + mpu_write_byte(AK8963_ADDR, MAG_CNTL1, 0X11); /* AK8963每次读完以后都需要重新设置为单次测量模式 */ +} + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/mpu9250/bsp_mpu9250.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/mpu9250/bsp_mpu9250.h new file mode 100644 index 00000000..ff17c720 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/mpu9250/bsp_mpu9250.h @@ -0,0 +1,116 @@ +#ifndef _BSP_MPU9250_H +#define _BSP_MPU9250_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_mpu9250.h +作者 : 左忠凯 +版本 : V1.0 +描述 : MPU9250驱动头文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯创建 +***************************************************************/ +#include "bsp.h" + +#define MPU9250_ADDR 0X68 /* MPU6500的器件IIC地址 */ +#define MPU6500_ID 0X71 /* MPU6500的器件ID */ + +/*MPU9250内部封装了一个AK8963磁力计,地址和ID如下: */ +#define AK8963_ADDR 0X0C /* AK8963的I2C地址 */ +#define AK8963_ID 0X48 /* AK8963的器件ID */ + +/* MPU6500的内部寄存器 */ +#define MPU_SELF_TESTX_REG 0X0D //自检寄存器X +#define MPU_SELF_TESTY_REG 0X0E //自检寄存器Y +#define MPU_SELF_TESTZ_REG 0X0F //自检寄存器Z +#define MPU_SELF_TESTA_REG 0X10 //自检寄存器A +#define MPU_SAMPLE_RATE_REG 0X19 //采样频率分频器 +#define MPU_CFG_REG 0X1A //配置寄存器 +#define MPU_GYRO_CFG_REG 0X1B //陀螺仪配置寄存器 +#define MPU_ACCEL_CFG_REG 0X1C //加速度计配置寄存器 +#define MPU_MOTION_DET_REG 0X1F //运动检测阀值设置寄存器 +#define MPU_FIFO_EN_REG 0X23 //FIFO使能寄存器 +#define MPU_I2CMST_CTRL_REG 0X24 //IIC主机控制寄存器 +#define MPU_I2CSLV0_ADDR_REG 0X25 //IIC从机0器件地址寄存器 +#define MPU_I2CSLV0_REG 0X26 //IIC从机0数据地址寄存器 +#define MPU_I2CSLV0_CTRL_REG 0X27 //IIC从机0控制寄存器 +#define MPU_I2CSLV1_ADDR_REG 0X28 //IIC从机1器件地址寄存器 +#define MPU_I2CSLV1_REG 0X29 //IIC从机1数据地址寄存器 +#define MPU_I2CSLV1_CTRL_REG 0X2A //IIC从机1控制寄存器 +#define MPU_I2CSLV2_ADDR_REG 0X2B //IIC从机2器件地址寄存器 +#define MPU_I2CSLV2_REG 0X2C //IIC从机2数据地址寄存器 +#define MPU_I2CSLV2_CTRL_REG 0X2D //IIC从机2控制寄存器 +#define MPU_I2CSLV3_ADDR_REG 0X2E //IIC从机3器件地址寄存器 +#define MPU_I2CSLV3_REG 0X2F //IIC从机3数据地址寄存器 +#define MPU_I2CSLV3_CTRL_REG 0X30 //IIC从机3控制寄存器 +#define MPU_I2CSLV4_ADDR_REG 0X31 //IIC从机4器件地址寄存器 +#define MPU_I2CSLV4_REG 0X32 //IIC从机4数据地址寄存器 +#define MPU_I2CSLV4_DO_REG 0X33 //IIC从机4写数据寄存器 +#define MPU_I2CSLV4_CTRL_REG 0X34 //IIC从机4控制寄存器 +#define MPU_I2CSLV4_DI_REG 0X35 //IIC从机4读数据寄存器 + +#define MPU_I2CMST_STA_REG 0X36 //IIC主机状态寄存器 +#define MPU_INTBP_CFG_REG 0X37 //中断/旁路设置寄存器 +#define MPU_INT_EN_REG 0X38 //中断使能寄存器 +#define MPU_INT_STA_REG 0X3A //中断状态寄存器 + +#define MPU_ACCEL_XOUTH_REG 0X3B //加速度值,X轴高8位寄存器 +#define MPU_ACCEL_XOUTL_REG 0X3C //加速度值,X轴低8位寄存器 +#define MPU_ACCEL_YOUTH_REG 0X3D //加速度值,Y轴高8位寄存器 +#define MPU_ACCEL_YOUTL_REG 0X3E //加速度值,Y轴低8位寄存器 +#define MPU_ACCEL_ZOUTH_REG 0X3F //加速度值,Z轴高8位寄存器 +#define MPU_ACCEL_ZOUTL_REG 0X40 //加速度值,Z轴低8位寄存器 + +#define MPU_TEMP_OUTH_REG 0X41 //温度值高八位寄存器 +#define MPU_TEMP_OUTL_REG 0X42 //温度值低8位寄存器 + +#define MPU_GYRO_XOUTH_REG 0X43 //陀螺仪值,X轴高8位寄存器 +#define MPU_GYRO_XOUTL_REG 0X44 //陀螺仪值,X轴低8位寄存器 +#define MPU_GYRO_YOUTH_REG 0X45 //陀螺仪值,Y轴高8位寄存器 +#define MPU_GYRO_YOUTL_REG 0X46 //陀螺仪值,Y轴低8位寄存器 +#define MPU_GYRO_ZOUTH_REG 0X47 //陀螺仪值,Z轴高8位寄存器 +#define MPU_GYRO_ZOUTL_REG 0X48 //陀螺仪值,Z轴低8位寄存器 + +#define MPU_I2CSLV0_DO_REG 0X63 //IIC从机0数据寄存器 +#define MPU_I2CSLV1_DO_REG 0X64 //IIC从机1数据寄存器 +#define MPU_I2CSLV2_DO_REG 0X65 //IIC从机2数据寄存器 +#define MPU_I2CSLV3_DO_REG 0X66 //IIC从机3数据寄存器 + +#define MPU_I2CMST_DELAY_REG 0X67 //IIC主机延时管理寄存器 +#define MPU_SIGPATH_RST_REG 0X68 //信号通道复位寄存器 +#define MPU_MDETECT_CTRL_REG 0X69 //运动检测控制寄存器 +#define MPU_USER_CTRL_REG 0X6A //用户控制寄存器 +#define MPU_PWR_MGMT1_REG 0X6B //电源管理寄存器1 +#define MPU_PWR_MGMT2_REG 0X6C //电源管理寄存器2 +#define MPU_FIFO_CNTH_REG 0X72 //FIFO计数寄存器高八位 +#define MPU_FIFO_CNTL_REG 0X73 //FIFO计数寄存器低八位 +#define MPU_FIFO_RW_REG 0X74 //FIFO读写寄存器 +#define MPU_DEVICE_ID_REG 0X75 //器件ID寄存器 + +/*AK8963的内部寄存器 */ +#define MAG_WIA 0x00 //AK8963的器件ID寄存器地址 +#define MAG_CNTL1 0X0A +#define MAG_CNTL2 0X0B + +#define MAG_XOUT_L 0X03 +#define MAG_XOUT_H 0X04 +#define MAG_YOUT_L 0X05 +#define MAG_YOUT_H 0X06 +#define MAG_ZOUT_L 0X07 +#define MAG_ZOUT_H 0X08 + + +/* 函数声明 */ +unsigned char mpu9250_init(void); +unsigned char mpu_write_byte(unsigned char addr,unsigned char reg, unsigned char data); +unsigned char mpu_read_byte(unsigned char addr,unsigned char reg); +void mpu_read_Len(unsigned char addr,unsigned char reg,unsigned char len,unsigned char *buf); +unsigned char mpu_set_gyro_range(unsigned char range); +unsigned char mpu_set_accel_range(unsigned char range); +unsigned char mpu_set_lpf(unsigned short fre); +unsigned char mpu_set_rate(unsigned short rate); +void mpu_get_gyroscope(short *gx,short *gy,short *gz); +void mpu_get_accelerometer(short *ax,short *ay,short *az); +void mpu_get_magnetometer(short *mx, short *my, short *mz); + +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/rtc/bsp_rtc.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/rtc/bsp_rtc.c new file mode 100644 index 00000000..60d71f31 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/rtc/bsp_rtc.c @@ -0,0 +1,230 @@ +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_rtc.c +作者 : 左忠凯 +版本 : V1.0 +描述 : RTC驱动文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/3 左忠凯创建 +***************************************************************/ +#include "bsp_rtc.h" +#include "printf.h" + +/* + * 描述:初始化RTC + */ +void rtc_init(void) +{ + /* + * 设置HPCOMR寄存器 + * bit[31] 1 : 允许访问SNVS寄存器，一定要置1 + * bit[8] 1 : 此位置1，需要签署NDA协议才能看到此位的详细说明， + * 这里不置1也没问题 + */ + SNVS->HPCOMR |= (1 << 31) | (1 << 8); + +#if 0 + struct rtc_datetime rtcdate; + + rtcdate.year = 2018U; + rtcdate.month = 12U; + rtcdate.day = 13U; + rtcdate.hour = 14U; + rtcdate.minute = 52; + rtcdate.second = 0; + rtc_setDatetime(&rtcdate); //初始化时间和日期 +#endif + + rtc_enable(); //使能RTC + +} + +/* + * 描述: 开启RTC + */ +void rtc_enable(void) +{ + /* + * LPCR寄存器bit0置1，使能RTC + */ + SNVS->LPCR |= 1 << 0; + while(!(SNVS->LPCR & 0X01));//等待使能完成 + +} + +/* + * 描述: 关闭RTC + */ +void rtc_disable(void) +{ + /* + * LPCR寄存器bit0置0，关闭RTC + */ + SNVS->LPCR &= ~(1 << 0); + while(SNVS->LPCR & 0X01);//等待关闭完成 +} + +/* + * @description : 判断指定年份是否为闰年，闰年条件如下: + * @param - year: 要判断的年份 + * @return : 1 是闰年，0 不是闰年 + */ +unsigned char rtc_isleapyear(unsigned short year) +{ + unsigned char value=0; + + if(year % 400 == 0) + value = 1; + else + { + if((year % 4 == 0) && (year % 100 != 0)) + value = 1; + else + value = 0; + } + return value; +} + +/* + * @description : 将时间转换为秒数 + * @param - datetime: 要转换日期和时间。 + * @return : 转换后的秒数 + */ +unsigned int rtc_coverdate_to_seconds(struct rtc_datetime *datetime) +{ + unsigned short i = 0; + unsigned int seconds = 0; + unsigned int days = 0; + unsigned short monthdays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; + + for(i = 1970; i < datetime->year; i++) + { + days += DAYS_IN_A_YEAR; /* 平年，每年365天 */ + if(rtc_isleapyear(i)) days += 1;/* 闰年多加一天 */ + } + + days += monthdays[datetime->month]; + if(rtc_isleapyear(i) && (datetime->month >= 3)) days += 1;/* 闰年，并且当前月份大于等于3月的话加一天 */ + + days += datetime->day - 1; + + seconds = days * SECONDS_IN_A_DAY + + datetime->hour * SECONDS_IN_A_HOUR + + datetime->minute * SECONDS_IN_A_MINUTE + + datetime->second; + + return seconds; +} + +/* + * @description : 设置时间和日期 + * @param - datetime: 要设置的日期和时间 + * @return : 无 + */ +void rtc_setdatetime(struct rtc_datetime *datetime) +{ + + unsigned int seconds = 0; + unsigned int tmp = SNVS->LPCR; + + rtc_disable(); /* 设置寄存器HPRTCMR和HPRTCLR的时候一定要先关闭RTC */ + + + /* 先将时间转换为秒 */ + seconds = rtc_coverdate_to_seconds(datetime); + + SNVS->LPSRTCMR = (unsigned int)(seconds >> 17); /* 设置高16位 */ + SNVS->LPSRTCLR = (unsigned int)(seconds << 15); /* 设置地16位 */ + + /* 如果此前RTC是打开的在设置完RTC时间以后需要重新打开RTC */ + if (tmp & 0x1) + rtc_enable(); +} + +/* + * @description : 将秒数转换为时间 + * @param - seconds : 要转换的秒数 + * @param - datetime: 转换后的日期和时间 + * @return : 无 + */ +void rtc_convertseconds_to_datetime(unsigned int seconds, struct rtc_datetime *datetime) +{ + unsigned int x; + unsigned int secondsRemaining, days; + unsigned short daysInYear; + + /* 每个月的天数 */ + unsigned char daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + secondsRemaining = seconds; /* 剩余秒数初始化 */ + days = secondsRemaining / SECONDS_IN_A_DAY + 1; /* 根据秒数计算天数,加1是当前天数 */ + secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; /*计算天数以后剩余的秒数 */ + + /* 计算时、分、秒 */ + datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; + secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; + datetime->minute = secondsRemaining / 60; + datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; + + /* 计算年 */ + daysInYear = DAYS_IN_A_YEAR; + datetime->year = YEAR_RANGE_START; + while(days > daysInYear) + { + /* 根据天数计算年 */ + days -= daysInYear; + datetime->year++; + + /* 处理闰年 */ + if (!rtc_isleapyear(datetime->year)) + daysInYear = DAYS_IN_A_YEAR; + else /*闰年，天数加一 */ + daysInYear = DAYS_IN_A_YEAR + 1; + } + /*根据剩余的天数计算月份 */ + if(rtc_isleapyear(datetime->year)) /* 如果是闰年的话2月加一天 */ + daysPerMonth[2] = 29; + + for(x = 1; x <= 12; x++) + { + if (days <= daysPerMonth[x]) + { + datetime->month = x; + break; + } + else + { + days -= daysPerMonth[x]; + } + } + + datetime->day = days; + +} + +/* + * @description : 获取RTC当前秒数 + * @param : 无 + * @return : 当前秒数 + */ +unsigned int rtc_getseconds(void) +{ + unsigned int seconds = 0; + + seconds = (SNVS->LPSRTCMR << 17) | (SNVS->LPSRTCLR >> 15); + return seconds; +} + +/* + * @description : 获取当前时间 + * @param - datetime: 获取到的时间，日期等参数 + * @return : 无 + */ +void rtc_getdatetime(struct rtc_datetime *datetime) +{ + unsigned int seconds = 0; + seconds = rtc_getseconds(); + rtc_convertseconds_to_datetime(seconds, datetime); +} + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/rtc/bsp_rtc.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/rtc/bsp_rtc.h new file mode 100644 index 00000000..4855bd1a --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/rtc/bsp_rtc.h @@ -0,0 +1,46 @@ +#ifndef _BSP_RTC_H +#define _BSP_RTC_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_rtc.c +作者 : 左忠凯 +版本 : V1.0 +描述 : RTC驱动头文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/3 左忠凯创建 +***************************************************************/ +#include "bsp.h" + +/* 相关宏定义 */ +#define SECONDS_IN_A_DAY (86400) /* 一天86400秒 */ +#define SECONDS_IN_A_HOUR (3600) /* 一个小时3600秒 */ +#define SECONDS_IN_A_MINUTE (60) /* 一分钟60秒 */ +#define DAYS_IN_A_YEAR (365) /* 一年365天 */ +#define YEAR_RANGE_START (1970) /* 开始年份1970年 */ +#define YEAR_RANGE_END (2099) /* 结束年份2099年 */ + + +/* 时间日期结构体 */ +struct rtc_datetime +{ + unsigned short year; /* 范围为:1970 ~ 2099 */ + unsigned char month; /* 范围为:1 ~ 12 */ + unsigned char day; /* 范围为:1 ~ 31 (不同的月，天数不同).*/ + unsigned char hour; /* 范围为:0 ~ 23 */ + unsigned char minute; /* 范围为:0 ~ 59 */ + unsigned char second; /* 范围为:0 ~ 59 */ +}; + + +/* 函数声明 */ +void rtc_init(void); +void rtc_enable(void); +void rtc_disable(void); +unsigned int rtc_coverdate_to_seconds(struct rtc_datetime *datetime); +unsigned int rtc_getseconds(void); +void rtc_setdatetime(struct rtc_datetime *datetime); +void rtc_getdatetime(struct rtc_datetime *datetime) +; + +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/spi/bsp_spi.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/spi/bsp_spi.c new file mode 100644 index 00000000..8dd7ff80 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/spi/bsp_spi.c @@ -0,0 +1,92 @@ +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_spi.c +作者 : 左忠凯 +版本 : V1.0 +描述 : SPI驱动文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/17 左忠凯创建 +***************************************************************/ +#include "bsp_spi.h" +#include "bsp_gpio.h" +#include "printf.h" + +/* + * @description : 初始化SPI + * @param - base : 要初始化的SPI + * @return : 无 + */ +void spi_init(ECSPI_Type *base) +{ + /* 1、配置SPI3 */ + base->CONREG = 0; /* 先清除控制寄存器 */ + + /* 配置CONREG寄存器 + * bit0 : 1 使能ECSPI + * bit3 : 1 当向TXFIFO写入数据以后立即开启SPI突发。 + * bit[7:4] : 0001 SPI通道0主模式，根据实际情况选择， + * 开发板上的BMP280接在SS0上，所以设置通道2为主模式 + * bit[19:18]: 00 选中通道0(其实不需要，因为片选信号我们我们自己控制) + * bit[31:20]: 0x7 突发长度为8个bit。 + */ + base->CONREG |= (1 << 0) | (1 << 3) | (1 << 4) | (7 << 20); /* 配置CONREG寄存器 */ + + /* + * ECSPI通道0设置,即设置CONFIGREG寄存器 + * bit0: 0 通道0 PHA为0 + * bit4: 0 通道0 SCLK高电平有效 + * bit8: 0 通道0片选信号 当SMC为1的时候此位无效 + * bit12： 0 通道0 POL为0 + * bit16： 0 通道0 数据线空闲时高电平 + * bit20: 0 通道0 时钟线空闲时低电平 + */ + base->CONFIGREG = 0; /* 设置通道寄存器 */ + + /* + * ECSPI通道0设置，设置采样周期 + * bit[14:0] : 0X2000 采样等待周期，比如当SPI时钟为10MHz的时候 + * 0X2000就等于1/10000 * 0X2000 = 0.8192ms，也就是连续 + * 读取数据的时候每次之间间隔0.8ms + * bit15 : 0 采样时钟源为SPI CLK + * bit[21:16]: 0 片选延时，可设置为0~63 + */ + base->PERIODREG = 0X0000; /* 设置采样周期寄存器 */ + + /* + * ECSPI的SPI时钟配置，SPI的时钟源来源于pll3_sw_clk/8=480/8=60MHz + * 通过设置CONREG寄存器的PER_DIVIDER(bit[11:8])和POST_DIVEDER(bit[15:12])来 + * 对SPI时钟源分频，获取到我们想要的SPI时钟： + * SPI CLK = (SourceCLK / PER_DIVIDER) / (2^POST_DIVEDER) + * 比如我们现在要设置SPI时钟为10MHz，那么PER_DIVEIDER和POST_DEIVIDER设置如下： + * PER_DIVIDER = 0X5。 + * POST_DIVIDER = 0X0。 + * SPI CLK = 60000000/(0X9 + 1) = 60000000=6MHz + */ + base->CONREG &= ~((0XF << 12) | (0XF << 8)); /* 清除PER_DIVDER和POST_DIVEDER以前的设置 */ + base->CONREG |= (0X9 << 12); /* 设置SPI CLK = 6MHz */ +} + +/* + * @description : SPI通道0发送/接收一个字节的数据 + * @param - base : 要使用的SPI + * @param - txdata : 要发送的数据 + * @return : 无 + */ +unsigned char spich0_readwrite_byte(ECSPI_Type *base, unsigned char txdata) +{ + uint32_t spirxdata = 0; + uint32_t spitxdata = txdata; + + /* 选择通道0 */ + base->CONREG &= ~(3 << 18); + base->CONREG |= (0 << 18); + + while((base->STATREG & (1 << 0)) == 0){} /* 等待发送FIFO为空 */ + base->TXDATA = spitxdata; + + while((base->STATREG & (1 << 3)) == 0){} /* 等待接收FIFO有数据 */ + spirxdata = base->RXDATA; + return spirxdata; +} + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/spi/bsp_spi.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/spi/bsp_spi.h new file mode 100644 index 00000000..f38e511f --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/spi/bsp_spi.h @@ -0,0 +1,20 @@ +#ifndef _BSP_SPI_H +#define _BSP_SPI_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_spi.h +作者 : 左忠凯 +版本 : V1.0 +描述 : SPI驱动头文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/17 左忠凯创建 +***************************************************************/ +#include "bsp.h" + +/* 函数声明 */ +void spi_init(ECSPI_Type *base); +unsigned char spich0_readwrite_byte(ECSPI_Type *base, unsigned char txdata); + +#endif + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/touchscreen/bsp_touchscreen.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/touchscreen/bsp_touchscreen.c new file mode 100644 index 00000000..c5de563f --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/touchscreen/bsp_touchscreen.c @@ -0,0 +1,239 @@ +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_touchscreen.c +作者 : 左忠凯 +版本 : V1.0 +描述 : 触摸屏驱动文件，触摸芯片为FT5426 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/21 左忠凯创建 +***************************************************************/ +#include "bsp_touchscreen.h" +#include "bsp_i2c.h" +#include "bsp_int.h" +#include "bsp_delay.h" +#include "printf.h" + +struct ft5426_dev_struc ft5426_dev; + +/* + * @description : 初始化触摸屏，其实就是初始化FT5426 + * @param : 无 + * @return : 无 + */ +void touchscreen_init(void) +{ + unsigned char reg_value[2]; + + ft5426_dev.initfalg = FT5426_INIT_NOTFINISHED; + + /* 1、初始化IIC2 IO + * I2C2_SCL -> UART5_TXD + * I2C2_SDA -> UART5_RXD + */ + IOMUXC_SetPinMux(IOMUXC_UART5_TX_DATA_I2C2_SCL,1); + IOMUXC_SetPinMux(IOMUXC_UART5_RX_DATA_I2C2_SDA,1); + + /* 配置I2C2 IO属性 + *bit 16:0 HYS关闭 + *bit [15:14]: 1 默认47K上拉 + *bit [13]: 1 pull功能 + *bit [12]: 1 pull/keeper使能 + *bit [11]: 0 关闭开路输出 + *bit [7:6]: 10 速度100Mhz + *bit [5:3]: 110 驱动能力为R0/6 + *bit [0]: 1 高转换率 + */ + IOMUXC_SetPinConfig(IOMUXC_UART5_TX_DATA_I2C2_SCL,0x70B0); + IOMUXC_SetPinConfig(IOMUXC_UART5_RX_DATA_I2C2_SDA,0X70B0); + + /* 2、初始化触摸屏中断IO和复位IO */ + gpio_pin_config_t ctintpin_config; + + IOMUXC_SetPinMux(IOMUXC_GPIO1_IO09_GPIO1_IO09,0); /* 复用为GPIO1_IO9 */ + IOMUXC_SetPinMux(IOMUXC_SNVS_SNVS_TAMPER9_GPIO5_IO09,0);/* 复用为GPIO5_IO9 */ + + + IOMUXC_SetPinConfig(IOMUXC_GPIO1_IO09_GPIO1_IO09,0xF080); + IOMUXC_SetPinConfig(IOMUXC_SNVS_SNVS_TAMPER9_GPIO5_IO09,0X10B0); + + /* 中断IO初始化 */ + ctintpin_config.direction = kGPIO_DigitalInput; + ctintpin_config.interruptMode = kGPIO_IntRisingOrFallingEdge; + gpio_init(GPIO1, 9, &ctintpin_config); + + GIC_EnableIRQ(GPIO1_Combined_0_15_IRQn); /* 使能GIC中对应的中断 */ + system_register_irqhandler(GPIO1_Combined_0_15_IRQn, (system_irq_handler_t)gpio1_io9_irqhandler, NULL); /* 注册中断服务函数 */ + gpio_enableint(GPIO1, 9); /* 使能GPIO1_IO18的中断功能 */ + + /* 复位IO初始化 */ + ctintpin_config.direction=kGPIO_DigitalOutput; + ctintpin_config.interruptMode=kGPIO_NoIntmode; + ctintpin_config.outputLogic=1; + gpio_init(GPIO5, 9, &ctintpin_config); + + /* 3、初始化I2C */ + i2c_init(I2C2); + + /* 4、初始化FT5426 */ + gpio_pinwrite(GPIO5, 9, 0); /* 复位FT5426 */ + delayms(20); + gpio_pinwrite(GPIO5, 9, 1); /* 停止复位FT5426 */ + delayms(20); + + ft5426_write_byte(FT5426_ADDR, FT5426_DEVICE_MODE, 0); /* 进入正常模式 */ + ft5426_write_byte(FT5426_ADDR, FT5426_IDG_MODE, 1); /* FT5426中断模式 */ + + + ft426_read_len(FT5426_ADDR, FT5426_IDGLIB_VERSION, 2, reg_value); + printf("Touch Frimware Version:%#X\r\n", ((unsigned short)reg_value[0] << 8) + reg_value[1]); + + ft5426_dev.initfalg = FT5426_INIT_FINISHED; /* 标记FT5426初始化完成 */ + ft5426_dev.intflag = 0; +} + +/* + * @description : GPIO1_IO9最终的中断处理函数 + * @param : 无 + * @return : 无 + */ +void gpio1_io9_irqhandler(void) +{ + if(ft5426_dev.initfalg == FT5426_INIT_FINISHED) + { + //ft5426_dev.intflag = 1; + ft5426_read_tpcoord(); + } + gpio_clearintflags(GPIO1, 9); /* 清除中断标志位 */ +} + + +/* + * @description : 向FT5429写入数据 + * @param - addr: 设备地址 + * @param - reg : 要写入的寄存器 + * @param - data: 要写入的数据 + * @return : 操作结果 + */ +unsigned char ft5426_write_byte(unsigned char addr,unsigned char reg, unsigned char data) +{ + unsigned char status=0; + unsigned char writedata=data; + struct i2c_transfer masterXfer; + + /* 配置I2C xfer结构体 */ + masterXfer.slaveAddress = addr; /* 设备地址 */ + masterXfer.direction = kI2C_Write; /* 写入数据 */ + masterXfer.subaddress = reg; /* 要写入的寄存器地址 */ + masterXfer.subaddressSize = 1; /* 地址长度一个字节 */ + masterXfer.data = &writedata; /* 要写入的数据 */ + masterXfer.dataSize = 1; /* 写入数据长度1个字节 */ + + if(i2c_master_transfer(I2C2, &masterXfer)) + status=1; + + return status; +} + +/* + * @description : 从FT5426读取一个字节的数据 + * @param - addr: 设备地址 + * @param - reg : 要读取的寄存器 + * @return : 读取到的数据。 + */ +unsigned char ft5426_read_byte(unsigned char addr,unsigned char reg) +{ + unsigned char val=0; + + struct i2c_transfer masterXfer; + masterXfer.slaveAddress = addr; /* 设备地址 */ + masterXfer.direction = kI2C_Read; /* 读取数据 */ + masterXfer.subaddress = reg; /* 要读取的寄存器地址 */ + masterXfer.subaddressSize = 1; /* 地址长度一个字节 */ + masterXfer.data = &val; /* 接收数据缓冲区 */ + masterXfer.dataSize = 1; /* 读取数据长度1个字节 */ + i2c_master_transfer(I2C2, &masterXfer); + + return val; +} + +/* + * @description : 从FT5429读取多个字节的数据 + * @param - addr: 设备地址 + * @param - reg : 要读取的开始寄存器地址 + * @param - len : 要读取的数据长度. + * @param - buf : 读取到的数据缓冲区 + * @return : 无 + */ +void ft426_read_len(unsigned char addr,unsigned char reg,unsigned char len,unsigned char *buf) +{ + struct i2c_transfer masterXfer; + + masterXfer.slaveAddress = addr; /* 设备地址 */ + masterXfer.direction = kI2C_Read; /* 读取数据 */ + masterXfer.subaddress = reg; /* 要读取的寄存器地址 */ + masterXfer.subaddressSize = 1; /* 地址长度一个字节 */ + masterXfer.data = buf; /* 接收数据缓冲区 */ + masterXfer.dataSize = len; /* 读取数据长度1个字节 */ + i2c_master_transfer(I2C2, &masterXfer); +} + +/* + * @description : 读取当前触摸点个数 + * @param : 无 + * @return : 无 + */ +void ft5426_read_tpnum(void) +{ + ft5426_dev.point_num = ft5426_read_byte(FT5426_ADDR, FT5426_TD_STATUS); +} + +/* + * @description : 读取当前所有触摸点的坐标 + * @param : 无 + * @return : 无 + */ +void ft5426_read_tpcoord(void) +{ + unsigned char i = 0; + unsigned char type = 0; + //unsigned char id = 0; + unsigned char pointbuf[FT5426_XYCOORDREG_NUM]; + + ft5426_dev.point_num = ft5426_read_byte(FT5426_ADDR, FT5426_TD_STATUS); + + /* + * 从寄存器FT5426_TOUCH1_XH开始，连续读取30个寄存器的值，这30个寄存器 + * 保存着5个点的触摸值，每个点占用6个寄存器。 + */ + ft426_read_len(FT5426_ADDR, FT5426_TOUCH1_XH, FT5426_XYCOORDREG_NUM, pointbuf); + + for(i = 0; i < ft5426_dev.point_num ; i++) + { + unsigned char *buf = &pointbuf[i * 6]; + /* 以第一个触摸点为例，寄存器TOUCH1_XH(地址0X03),各位描述如下： + * bit7:6 Event flag 0:按下 1:释放 2：接触 3：没有事件 + * bit5:4 保留 + * bit3:0 X轴触摸点的11~8位。 + */ + ft5426_dev.x[i] = ((buf[2] << 8) | buf[3]) & 0x0fff; + ft5426_dev.y[i] = ((buf[0] << 8) | buf[1]) & 0x0fff; + + type = buf[0] >> 6; /* 获取触摸类型 */ + + + /* 以第一个触摸点为例，寄存器TOUCH1_YH(地址0X05),各位描述如下： + * bit7:4 Touch ID 触摸ID，表示是哪个触摸点 + * bit3:0 Y轴触摸点的11~8位。 + */ + //id = (buf[2] >> 4) & 0x0f; + + if(type == FT5426_TOUCH_EVENT_DOWN || type == FT5426_TOUCH_EVENT_ON )/* 按下 */ + { + + } else { /* 释放 */ + + } + } +} + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/touchscreen/bsp_touchscreen.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/touchscreen/bsp_touchscreen.h new file mode 100644 index 00000000..78ad040f --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/touchscreen/bsp_touchscreen.h @@ -0,0 +1,62 @@ +#ifndef _TOUCHSCREEN_H +#define _TOUCHSCREEN_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_touchscreen.c +作者 : 左忠凯 +版本 : V1.0 +描述 : 触摸屏驱动头文件,触摸芯片为FT5426 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/21 左忠凯创建 +***************************************************************/ +#include "bsp.h" +#include "bsp_gpio.h" + +/* 宏定义 */ +#define FT5426_ADDR 0X38 /* FT5426设备地址 */ + +#define FT5426_DEVICE_MODE 0X00 /* 模式寄存器 */ +#define FT5426_IDGLIB_VERSION 0XA1 /* 固件版本寄存器 */ +#define FT5426_IDG_MODE 0XA4 /* 模式寄存器 */ +#define FT5426_TD_STATUS 0X02 /* 触摸状态寄存器 */ +#define FT5426_TOUCH1_XH 0X03 /* 触摸点坐标寄存器, + * 一个触摸点用6个寄存器存储坐标数据 + */ + +#define FT5426_XYCOORDREG_NUM 30 /* 触摸点坐标寄存器数量 */ +#define FT5426_INIT_FINISHED 1 /* 触摸屏初始化完成 */ +#define FT5426_INIT_NOTFINISHED 0 /* 触摸屏初始化未完成 */ + +#define FT5426_TOUCH_EVENT_DOWN 0x00 /* 按下 */ +#define FT5426_TOUCH_EVENT_UP 0x01 /* 释放 */ +#define FT5426_TOUCH_EVENT_ON 0x02 /* 接触 */ +#define FT5426_TOUCH_EVENT_RESERVED 0x03 /* 没有事件 */ + + +/* 触摸屏结构体 */ +struct ft5426_dev_struc +{ + unsigned char initfalg; /* 触摸屏初始化状态 */ + unsigned char intflag; /* 标记中断有没有发生 */ + unsigned char point_num; /* 触摸点 */ + unsigned short x[5]; /* X轴坐标 */ + unsigned short y[5]; /* Y轴坐标 */ + +}; + +extern struct ft5426_dev_struc ft5426_dev; + +/* 函数声明 */ +void touchscreen_init(void); + +void gpio1_io9_irqhandler(void); +unsigned char ft5426_write_byte(unsigned char addr,unsigned char reg, unsigned char data); +unsigned char ft5426_read_byte(unsigned char addr,unsigned char reg); +void ft426_read_len(unsigned char addr,unsigned char reg,unsigned char len,unsigned char *buf); +void ft5426_read_tpnum(void); +void ft5426_read_tpcoord(void); + + +#endif + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/uart/bsp_uart.c b/board/ALPHA_I.MX_emmc_256ddr/bsp/uart/bsp_uart.c new file mode 100644 index 00000000..7a1aa39d --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/uart/bsp_uart.c @@ -0,0 +1,287 @@ +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_led.c +作者 : 左忠凯 +版本 : V1.0 +描述 : 串口驱动文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/15 左忠凯创建 +***************************************************************/ +#include "bsp_uart.h" + +/* + * @description : 初始化串口1,波特率为115200 + * @param : 无 + * @return : 无 + */ +void uart_init(void) +{ + /* 1、初始化串口IO */ + uart_io_init(); + + /* 2、初始化UART1 */ + uart_disable(UART1); /* 先关闭UART1 */ + uart_softreset(UART1); /* 软件复位UART1 */ + + UART1-> +UCR1 = 0; /* 先清除UCR1寄存器 */ + + /* + * 设置UART的UCR2寄存器，设置内容包括字长，停止位，校验模式，关闭RTS硬件流控 + * bit14: 1 忽略RTS引脚 + * bit8: 0 关闭奇偶校验 + * bit6: 0 1位停止位 + * bit5: 1 8位数据位 + * bit2: 1 打开发送 + * bit1: 1 打开接收 + */ + UART1->UCR2 |= (1<<14) | (1<<5) | (1<<2) | (1<<1); + + /* + * UART1的UCR3寄存器 + * bit2: 1 必须设置为1！参考IMX6ULL参考手册3642页 + */ + UART1->UCR3 |= 1<<2; + + /* + * 设置UART的UCR1寄存器，关闭自动波特率 + * bit14: 0 关闭自动波特率检测,我们自己设置波特率 + */ + UART1->UCR1 &= ~(1<<14); + + + /* + * 设置波特率 + * 波特率计算公式:Baud Rate = Ref Freq / (16 * (UBMR + 1)/(UBIR+1)) + * 如果要设置波特率为115200，那么可以使用如下参数: + * Ref Freq = 80M 也就是寄存器UFCR的bit9:7=101, 表示1分频 + * UBMR = 3124 + * UBIR = 71 + * 因此波特率= 80000000/(16 * (3124+1)/(71+1))=80000000/(16 * 3125/72) = (80000000*72) / (16*3125) = 115200 + */ + UART1->UFCR = 5<<7; //ref freq等于ipg_clk/1=80Mhz + UART1->UBIR = 71; + UART1->UBMR = 3124; + + /* 使能串口 */ + uart_enable(UART1); +} + +/* + * @description : 初始化串口1所使用的IO引脚 + * @param : 无 + * @return : 无 + */ +void uart_io_init(void) +{ + /* 1、初始化IO复用 + * UART1_RXD -> UART1_TX_DATA + * UART1_TXD -> UART1_RX_DATA + */ + IOMUXC_SetPinMux(IOMUXC_UART1_TX_DATA_UART1_TX,0); /* 复用为UART1_TX */ + IOMUXC_SetPinMux(IOMUXC_UART1_RX_DATA_UART1_RX,0); /* 复用为UART1_RX */ + + /* 2、配置UART1_TX_DATA、UART1_RX_DATA的IO属性 + *bit 16:0 HYS关闭 + *bit [15:14]: 00 默认100K下拉 + *bit [13]: 0 keeper功能 + *bit [12]: 1 pull/keeper使能 + *bit [11]: 0 关闭开路输出 + *bit [7:6]: 10 速度100Mhz + *bit [5:3]: 110 驱动能力R0/6 + *bit [0]: 0 低转换率 + */ + IOMUXC_SetPinConfig(IOMUXC_UART1_TX_DATA_UART1_TX,0x10B0); + IOMUXC_SetPinConfig(IOMUXC_UART1_RX_DATA_UART1_RX,0x10B0); +} + +/* + * @description : 波特率计算公式， + * 可以用此函数计算出指定串口对应的UFCR， + * UBIR和UBMR这三个寄存器的值 + * @param - base : 要计算的串口。 + * @param - baudrate : 要使用的波特率。 + * @param - srcclock_hz :串口时钟源频率，单位Hz + * @return : 无 + */ +void uart_setbaudrate(UART_Type *base, unsigned int baudrate, unsigned int srcclock_hz) +{ + uint32_t numerator = 0u; //分子 + uint32_t denominator = 0U; //分母 + uint32_t divisor = 0U; + uint32_t refFreqDiv = 0U; + uint32_t divider = 1U; + uint64_t baudDiff = 0U; + uint64_t tempNumerator = 0U; + uint32_t tempDenominator = 0u; + + /* get the approximately maximum divisor */ + numerator = srcclock_hz; + denominator = baudrate << 4; + divisor = 1; + + while (denominator != 0) + { + divisor = denominator; + denominator = numerator % denominator; + numerator = divisor; + } + + numerator = srcclock_hz / divisor; + denominator = (baudrate << 4) / divisor; + + /* numerator ranges from 1 ~ 7 * 64k */ + /* denominator ranges from 1 ~ 64k */ + if ((numerator > (UART_UBIR_INC_MASK * 7)) || (denominator > UART_UBIR_INC_MASK)) + { + uint32_t m = (numerator - 1) / (UART_UBIR_INC_MASK * 7) + 1; + uint32_t n = (denominator - 1) / UART_UBIR_INC_MASK + 1; + uint32_t max = m > n ? m : n; + numerator /= max; + denominator /= max; + if (0 == numerator) + { + numerator = 1; + } + if (0 == denominator) + { + denominator = 1; + } + } + divider = (numerator - 1) / UART_UBIR_INC_MASK + 1; + + switch (divider) + { + case 1: + refFreqDiv = 0x05; + break; + case 2: + refFreqDiv = 0x04; + break; + case 3: + refFreqDiv = 0x03; + break; + case 4: + refFreqDiv = 0x02; + break; + case 5: + refFreqDiv = 0x01; + break; + case 6: + refFreqDiv = 0x00; + break; + case 7: + refFreqDiv = 0x06; + break; + default: + refFreqDiv = 0x05; + break; + } + /* Compare the difference between baudRate_Bps and calculated baud rate. + * Baud Rate = Ref Freq / (16 * (UBMR + 1)/(UBIR+1)). + * baudDiff = (srcClock_Hz/divider)/( 16 * ((numerator / divider)/ denominator). + */ + tempNumerator = srcclock_hz; + tempDenominator = (numerator << 4); + divisor = 1; + /* get the approximately maximum divisor */ + while (tempDenominator != 0) + { + divisor = tempDenominator; + tempDenominator = tempNumerator % tempDenominator; + tempNumerator = divisor; + } + tempNumerator = srcclock_hz / divisor; + tempDenominator = (numerator << 4) / divisor; + baudDiff = (tempNumerator * denominator) / tempDenominator; + baudDiff = (baudDiff >= baudrate) ? (baudDiff - baudrate) : (baudrate - baudDiff); + + if (baudDiff < (baudrate / 100) * 3) + { + base->UFCR &= ~UART_UFCR_RFDIV_MASK; + base->UFCR |= UART_UFCR_RFDIV(refFreqDiv); + base->UBIR = UART_UBIR_INC(denominator - 1); //要先写UBIR寄存器，然后在写UBMR寄存器，3592页 + base->UBMR = UART_UBMR_MOD(numerator / divider - 1); + //base->ONEMS = UART_ONEMS_ONEMS(srcclock_hz / (1000 * divider)); + } + +} + +/* + * @description : 关闭指定的UART + * @param - base: 要关闭的UART + * @return : 无 + */ +void uart_disable(UART_Type *base) +{ + base->UCR1 &= ~(1<<0); +} + +/* + * @description : 打开指定的UART + * @param - base: 要打开的UART + * @return : 无 + */ +void uart_enable(UART_Type *base) +{ + base->UCR1 |= (1<<0); +} + +/* + * @description : 复位指定的UART + * @param - base: 要复位的UART + * @return : 无 + */ +void uart_softreset(UART_Type *base) +{ + base->UCR2 &= ~(1<<0); /* UCR2的bit0为0，复位UART */ + while((base->UCR2 & 0x1) == 0); /* 等待复位完成 */ +} + +/* + * @description : 发送一个字符 + * @param - c : 要发送的字符 + * @return : 无 + */ +void uart_putc(unsigned char c) +{ + while(((UART1->USR2 >> 3) &0X01) == 0);/* 等待上一次发送完成 */ + UART1->UTXD = c & 0XFF; /* 发送数据 */ +} + +/* + * @description : 发送一个字符串 + * @param - str : 要发送的字符串 + * @return : 无 + */ +void uart_puts(char *str) +{ + char *p = str; + + while(*p) + uart_putc(*p++); +} + +/* + * @description : 接收一个字符 + * @param : 无 + * @return : 接收到的字符 + */ +unsigned char uart_getc(void) +{ + while((UART1->USR2 & 0x1) == 0);/* 等待接收完成 */ + return UART1->URXD; /* 返回接收到的数据 */ +} + +/* + * @description : 防止编译器报错 + * @param : 无 + * @return : 无 + */ +void raise(int sig_nr) +{ + +} + + diff --git a/board/ALPHA_I.MX_emmc_256ddr/bsp/uart/bsp_uart.h b/board/ALPHA_I.MX_emmc_256ddr/bsp/uart/bsp_uart.h new file mode 100644 index 00000000..8f1dde30 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/bsp/uart/bsp_uart.h @@ -0,0 +1,28 @@ +#ifndef _BSP_UART_H +#define _BSP_UART_H +#include "bsp.h" +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp_led.c +作者 : 左忠凯 +版本 : V1.0 +描述 : 串口驱动文件头文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/15 左忠凯创建 +***************************************************************/ + +/* 函数声明 */ +void uart_init(void); +void uart_io_init(void); +void uart_disable(UART_Type *base); +void uart_enable(UART_Type *base); +void uart_softreset(UART_Type *base); +void uart_setbaudrate(UART_Type *base, unsigned int baudrate, unsigned int srcclock_hz); +void uart_putc(unsigned char c); +void uart_puts(char *str); +unsigned char uart_getc(void); +void raise(int sig_nr); + + +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/imx6ul/MCIMX6Y2.h b/board/ALPHA_I.MX_emmc_256ddr/imx6ul/MCIMX6Y2.h new file mode 100644 index 00000000..fe15c75b --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/imx6ul/MCIMX6Y2.h @@ -0,0 +1,42103 @@ +/************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : fsl_iomuxc.h +作者 : 左忠凯修改NXP官方SDK +版本 : V1.0 +描述 : NXP官方SDK的寄存器结构体和相关位定义文档 +其他 : NXP官方SDK的寄存器结构体和相关位定义文档，默认基于IAR的， + 由左忠凯移植到Liux下。 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯移植 +**************************************************************/ + + +#ifndef _MCIMX6Y2_H_ +#define _MCIMX6Y2_H_ /**< Symbol preventing repeated inclusion */ + +#include "cc.h" /* cc.h为自行添加的文件 */ + + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0300U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 160 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + Software0_IRQn = 0, /**< Cortex-A7 Software Generated Interrupt 0 */ + Software1_IRQn = 1, /**< Cortex-A7 Software Generated Interrupt 1 */ + Software2_IRQn = 2, /**< Cortex-A7 Software Generated Interrupt 2 */ + Software3_IRQn = 3, /**< Cortex-A7 Software Generated Interrupt 3 */ + Software4_IRQn = 4, /**< Cortex-A7 Software Generated Interrupt 4 */ + Software5_IRQn = 5, /**< Cortex-A7 Software Generated Interrupt 5 */ + Software6_IRQn = 6, /**< Cortex-A7 Software Generated Interrupt 6 */ + Software7_IRQn = 7, /**< Cortex-A7 Software Generated Interrupt 7 */ + Software8_IRQn = 8, /**< Cortex-A7 Software Generated Interrupt 8 */ + Software9_IRQn = 9, /**< Cortex-A7 Software Generated Interrupt 9 */ + Software10_IRQn = 10, /**< Cortex-A7 Software Generated Interrupt 10 */ + Software11_IRQn = 11, /**< Cortex-A7 Software Generated Interrupt 11 */ + Software12_IRQn = 12, /**< Cortex-A7 Software Generated Interrupt 12 */ + Software13_IRQn = 13, /**< Cortex-A7 Software Generated Interrupt 13 */ + Software14_IRQn = 14, /**< Cortex-A7 Software Generated Interrupt 14 */ + Software15_IRQn = 15, /**< Cortex-A7 Software Generated Interrupt 15 */ + VirtualMaintenance_IRQn = 25, /**< Cortex-A7 Virtual Maintenance Interrupt */ + HypervisorTimer_IRQn = 26, /**< Cortex-A7 Hypervisor Timer Interrupt */ + VirtualTimer_IRQn = 27, /**< Cortex-A7 Virtual Timer Interrupt */ + LegacyFastInt_IRQn = 28, /**< Cortex-A7 Legacy nFIQ signal Interrupt */ + SecurePhyTimer_IRQn = 29, /**< Cortex-A7 Secure Physical Timer Interrupt */ + NonSecurePhyTimer_IRQn = 30, /**< Cortex-A7 Non-secure Physical Timer Interrupt */ + LegacyIRQ_IRQn = 31, /**< Cortex-A7 Legacy nIRQ Interrupt */ + + /* Device specific interrupts */ + IOMUXC_IRQn = 32, /**< General Purpose Register 1 from IOMUXC. Used to notify cores on exception condition while boot. */ + DAP_IRQn = 33, /**< Debug Access Port interrupt request. */ + SDMA_IRQn = 34, /**< SDMA interrupt request from all channels. */ + TSC_IRQn = 35, /**< TSC interrupt. */ + SNVS_IRQn = 36, /**< Logic OR of SNVS_LP and SNVS_HP interrupts. */ + LCDIF_IRQn = 37, /**< LCDIF sync interrupt. */ + RNGB_IRQn = 38, /**< RNGB interrupt. */ + CSI_IRQn = 39, /**< CMOS Sensor Interface interrupt request. */ + PXP_IRQ0_IRQn = 40, /**< PXP interrupt pxp_irq_0. */ + SCTR_IRQ0_IRQn = 41, /**< SCTR compare interrupt ipi_int[0]. */ + SCTR_IRQ1_IRQn = 42, /**< SCTR compare interrupt ipi_int[1]. */ + WDOG3_IRQn = 43, /**< WDOG3 timer reset interrupt request. */ + Reserved44_IRQn = 44, /**< Reserved */ + APBH_IRQn = 45, /**< DMA Logical OR of APBH DMA channels 0-3 completion and error interrupts. */ + WEIM_IRQn = 46, /**< WEIM interrupt request. */ + RAWNAND_BCH_IRQn = 47, /**< BCH operation complete interrupt. */ + RAWNAND_GPMI_IRQn = 48, /**< GPMI operation timeout error interrupt. */ + UART6_IRQn = 49, /**< UART6 interrupt request. */ + PXP_IRQ1_IRQn = 50, /**< PXP interrupt pxp_irq_1. */ + SNVS_Consolidated_IRQn = 51, /**< SNVS consolidated interrupt. */ + SNVS_Security_IRQn = 52, /**< SNVS security interrupt. */ + CSU_IRQn = 53, /**< CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted. */ + USDHC1_IRQn = 54, /**< USDHC1 (Enhanced SDHC) interrupt request. */ + USDHC2_IRQn = 55, /**< USDHC2 (Enhanced SDHC) interrupt request. */ + SAI3_RX_IRQn = 56, /**< SAI3 interrupt ipi_int_sai_rx. */ + SAI3_TX_IRQn = 57, /**< SAI3 interrupt ipi_int_sai_tx. */ + UART1_IRQn = 58, /**< UART1 interrupt request. */ + UART2_IRQn = 59, /**< UART2 interrupt request. */ + UART3_IRQn = 60, /**< UART3 interrupt request. */ + UART4_IRQn = 61, /**< UART4 interrupt request. */ + UART5_IRQn = 62, /**< UART5 interrupt request. */ + eCSPI1_IRQn = 63, /**< eCSPI1 interrupt request. */ + eCSPI2_IRQn = 64, /**< eCSPI2 interrupt request. */ + eCSPI3_IRQn = 65, /**< eCSPI3 interrupt request. */ + eCSPI4_IRQn = 66, /**< eCSPI4 interrupt request. */ + I2C4_IRQn = 67, /**< I2C4 interrupt request. */ + I2C1_IRQn = 68, /**< I2C1 interrupt request. */ + I2C2_IRQn = 69, /**< I2C2 interrupt request. */ + I2C3_IRQn = 70, /**< I2C3 interrupt request. */ + UART7_IRQn = 71, /**< UART-7 ORed interrupt. */ + UART8_IRQn = 72, /**< UART-8 ORed interrupt. */ + Reserved73_IRQn = 73, /**< Reserved */ + USB_OTG2_IRQn = 74, /**< USBO2 USB OTG2 */ + USB_OTG1_IRQn = 75, /**< USBO2 USB OTG1 */ + USB_PHY1_IRQn = 76, /**< UTMI0 interrupt request. */ + USB_PHY2_IRQn = 77, /**< UTMI1 interrupt request. */ + DCP_IRQ_IRQn = 78, /**< DCP interrupt request dcp_irq. */ + DCP_VMI_IRQ_IRQn = 79, /**< DCP interrupt request dcp_vmi_irq. */ + DCP_SEC_IRQ_IRQn = 80, /**< DCP interrupt request secure_irq. */ + TEMPMON_IRQn = 81, /**< Temperature Monitor Temperature Sensor (temperature greater than threshold) interrupt request. */ + ASRC_IRQn = 82, /**< ASRC interrupt request. */ + ESAI_IRQn = 83, /**< ESAI interrupt request. */ + SPDIF_IRQn = 84, /**< SPDIF interrupt. */ + Reserved85_IRQn = 85, /**< Reserved */ + PMU_IRQ1_IRQn = 86, /**< Brown-out event on either the 1.1, 2.5 or 3.0 regulators. */ + GPT1_IRQn = 87, /**< Logical OR of GPT1 rollover interrupt line, input capture 1 and 2 lines, output compare 1, 2, and 3 interrupt lines. */ + EPIT1_IRQn = 88, /**< EPIT1 output compare interrupt. */ + EPIT2_IRQn = 89, /**< EPIT2 output compare interrupt. */ + GPIO1_INT7_IRQn = 90, /**< INT7 interrupt request. */ + GPIO1_INT6_IRQn = 91, /**< INT6 interrupt request. */ + GPIO1_INT5_IRQn = 92, /**< INT5 interrupt request. */ + GPIO1_INT4_IRQn = 93, /**< INT4 interrupt request. */ + GPIO1_INT3_IRQn = 94, /**< INT3 interrupt request. */ + GPIO1_INT2_IRQn = 95, /**< INT2 interrupt request. */ + GPIO1_INT1_IRQn = 96, /**< INT1 interrupt request. */ + GPIO1_INT0_IRQn = 97, /**< INT0 interrupt request. */ + GPIO1_Combined_0_15_IRQn = 98, /**< Combined interrupt indication for GPIO1 signals 0 - 15. */ + GPIO1_Combined_16_31_IRQn = 99, /**< Combined interrupt indication for GPIO1 signals 16 - 31. */ + GPIO2_Combined_0_15_IRQn = 100, /**< Combined interrupt indication for GPIO2 signals 0 - 15. */ + GPIO2_Combined_16_31_IRQn = 101, /**< Combined interrupt indication for GPIO2 signals 16 - 31. */ + GPIO3_Combined_0_15_IRQn = 102, /**< Combined interrupt indication for GPIO3 signals 0 - 15. */ + GPIO3_Combined_16_31_IRQn = 103, /**< Combined interrupt indication for GPIO3 signals 16 - 31. */ + GPIO4_Combined_0_15_IRQn = 104, /**< Combined interrupt indication for GPIO4 signals 0 - 15. */ + GPIO4_Combined_16_31_IRQn = 105, /**< Combined interrupt indication for GPIO4 signals 16 - 31. */ + GPIO5_Combined_0_15_IRQn = 106, /**< Combined interrupt indication for GPIO5 signals 0 - 15. */ + GPIO5_Combined_16_31_IRQn = 107, /**< Combined interrupt indication for GPIO5 signals 16 - 31. */ + Reserved108_IRQn = 108, /**< Reserved */ + Reserved109_IRQn = 109, /**< Reserved */ + Reserved110_IRQn = 110, /**< Reserved */ + Reserved111_IRQn = 111, /**< Reserved */ + WDOG1_IRQn = 112, /**< WDOG1 timer reset interrupt request. */ + WDOG2_IRQn = 113, /**< WDOG2 timer reset interrupt request. */ + KPP_IRQn = 114, /**< Key Pad interrupt request. */ + PWM1_IRQn = 115, /**< hasRegInstance(`PWM1`)?`Cumulative interrupt line for PWM1. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.`:`Reserved`) */ + PWM2_IRQn = 116, /**< hasRegInstance(`PWM2`)?`Cumulative interrupt line for PWM2. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.`:`Reserved`) */ + PWM3_IRQn = 117, /**< hasRegInstance(`PWM3`)?`Cumulative interrupt line for PWM3. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.`:`Reserved`) */ + PWM4_IRQn = 118, /**< hasRegInstance(`PWM4`)?`Cumulative interrupt line for PWM4. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts.`:`Reserved`) */ + CCM_IRQ1_IRQn = 119, /**< CCM interrupt request ipi_int_1. */ + CCM_IRQ2_IRQn = 120, /**< CCM interrupt request ipi_int_2. */ + GPC_IRQn = 121, /**< GPC interrupt request 1. */ + Reserved122_IRQn = 122, /**< Reserved */ + SRC_IRQn = 123, /**< SRC interrupt request src_ipi_int_1. */ + Reserved124_IRQn = 124, /**< Reserved */ + Reserved125_IRQn = 125, /**< Reserved */ + CPU_PerformanceUnit_IRQn = 126, /**< Performance Unit interrupt ~ipi_pmu_irq_b. */ + CPU_CTI_Trigger_IRQn = 127, /**< CTI trigger outputs interrupt ~ipi_cti_irq_b. */ + SRC_Combined_IRQn = 128, /**< Combined CPU wdog interrupts (4x) out of SRC. */ + SAI1_IRQn = 129, /**< SAI1 interrupt request. */ + SAI2_IRQn = 130, /**< SAI2 interrupt request. */ + Reserved131_IRQn = 131, /**< Reserved */ + ADC1_IRQn = 132, /**< ADC1 interrupt request. */ + ADC_5HC_IRQn = 133, /**< ADC_5HC interrupt request. */ + Reserved134_IRQn = 134, /**< Reserved */ + Reserved135_IRQn = 135, /**< Reserved */ + SJC_IRQn = 136, /**< SJC interrupt from General Purpose register. */ + CAAM_Job_Ring0_IRQn = 137, /**< CAAM job ring 0 interrupt ipi_caam_irq0. */ + CAAM_Job_Ring1_IRQn = 138, /**< CAAM job ring 1 interrupt ipi_caam_irq1. */ + QSPI_IRQn = 139, /**< QSPI1 interrupt request ipi_int_ored. */ + TZASC_IRQn = 140, /**< TZASC (PL380) interrupt request. */ + GPT2_IRQn = 141, /**< Logical OR of GPT2 rollover interrupt line, input capture 1 and 2 lines, output compare 1, 2 and 3 interrupt lines. */ + CAN1_IRQn = 142, /**< Combined interrupt of ini_int_busoff,ini_int_error,ipi_int_mbor,ipi_int_txwarning and ipi_int_waken */ + CAN2_IRQn = 143, /**< Combined interrupt of ini_int_busoff,ini_int_error,ipi_int_mbor,ipi_int_txwarning and ipi_int_waken */ + Reserved144_IRQn = 144, /**< Reserved */ + Reserved145_IRQn = 145, /**< Reserved */ + PWM5_IRQn = 146, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM6_IRQn = 147, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM7_IRQn = 148, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM8_IRQn = 149, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + ENET1_IRQn = 150, /**< ENET1 interrupt */ + ENET1_1588_IRQn = 151, /**< ENET1 1588 Timer interrupt [synchronous] request. */ + ENET2_IRQn = 152, /**< ENET2 interrupt */ + ENET2_1588_IRQn = 153, /**< MAC 0 1588 Timer interrupt [synchronous] request. */ + Reserved154_IRQn = 154, /**< Reserved */ + Reserved155_IRQn = 155, /**< Reserved */ + Reserved156_IRQn = 156, /**< Reserved */ + Reserved157_IRQn = 157, /**< Reserved */ + Reserved158_IRQn = 158, /**< Reserved */ + PMU_IRQ2_IRQn = 159 /**< Brown-out event on either core, gpu or soc regulators. */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Configuration of the Cortex-A7 Processor and Core Peripherals + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-A7 Processor and Core Peripherals + * @{ + */ + +#define __CA7_REV 0x0005 /**< Core revision r0p5 */ +#define __GIC_PRIO_BITS 5 /**< Number of Bits used for Priority Levels */ +#define __FPU_PRESENT 1 /**< FPU present or not */ + + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_mux_ctl_pad +{ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_MOD = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TMS = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TDO = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TDI = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TCK = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_JTAG_TRST_B = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART1_CTS_B = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART1_RTS_B = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART2_CTS_B = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART2_RTS_B = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART4_TX_DATA = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART4_RX_DATA = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART5_TX_DATA = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_UART5_RX_DATA = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_RX_DATA0 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_RX_DATA1 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_RX_EN = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_TX_DATA0 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_TX_DATA1 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_TX_EN = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET1_RX_ER = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_RX_DATA0 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_RX_DATA1 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_RX_EN = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_TX_DATA0 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_TX_DATA1 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_TX_EN = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_ENET2_RX_ER = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_CLK = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_RESET = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA00 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA01 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA02 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA03 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA04 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA05 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA06 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA07 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA08 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA09 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA10 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA11 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA12 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA13 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA14 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA15 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA16 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA17 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA18 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA19 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA20 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA21 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA22 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_LCD_DATA23 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_RE_B = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_WE_B = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_ALE = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_WP_B = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_READY_B = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_CLE = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_NAND_DQS = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_CMD = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_CLK = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_MCLK = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA00 = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA01 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA02 = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA03 = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA04 = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA05 = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA06 = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_CSI_DATA07 = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */ +} iomuxc_sw_mux_ctl_pad_t; + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD_DDR + * + * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD_DDR collections. + */ +typedef enum _iomuxc_sw_pad_ctl_pad_ddr +{ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 = 16U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 = 17U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B = 18U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B = 19U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B = 20U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B = 21U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B = 22U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 = 23U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 = 24U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 = 25U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 = 26U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 = 27U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 = 28U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 = 29U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P = 30U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P = 31U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P = 32U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ + kIOMUXC_SW_PAD_CTL_PAD_DRAM_RESET = 33U, /**< IOMUXC SW_PAD_CTL_PAD_DDR index */ +} iomuxc_sw_pad_ctl_pad_ddr_t; + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_pad_ctl_pad +{ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_MOD = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TMS = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDO = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDI = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TCK = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART1_CTS_B = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART1_RTS_B = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART2_CTS_B = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART2_RTS_B = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART4_TX_DATA = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART4_RX_DATA = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART5_TX_DATA = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_UART5_RX_DATA = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_RX_DATA0 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_RX_DATA1 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_RX_EN = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_TX_DATA0 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_TX_DATA1 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_TX_EN = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET1_RX_ER = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_RX_DATA0 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_RX_DATA1 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_RX_EN = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_TX_DATA0 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_TX_DATA1 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_TX_EN = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_ENET2_RX_ER = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_CLK = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_RESET = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA00 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA01 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA02 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA03 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA04 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA05 = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA06 = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA07 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA08 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA09 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA10 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA11 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA12 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA13 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA14 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA15 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA16 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA17 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA18 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA19 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA20 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA21 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA22 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_LCD_DATA23 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_RE_B = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_WE_B = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_ALE = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_WP_B = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_READY_B = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_CLE = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_NAND_DQS = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_CMD = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_CLK = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_MCLK = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA00 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA01 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA02 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA03 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA04 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA05 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA06 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_CSI_DATA07 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */ +} iomuxc_sw_pad_ctl_pad_t; + +/*! + * @brief Enumeration for the IOMUXC select input + * + * Defines the enumeration for the IOMUXC select input collections. + */ +typedef enum _iomuxc_select_input +{ + kIOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG2_ID_SELECT_INPUT = 1U, /**< IOMUXC select input index */ + kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA05_SELECT_INPUT = 5U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA00_SELECT_INPUT = 6U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA01_SELECT_INPUT = 7U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA04_SELECT_INPUT = 8U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA06_SELECT_INPUT = 9U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA07_SELECT_INPUT = 10U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA08_SELECT_INPUT = 11U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA09_SELECT_INPUT = 12U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA10_SELECT_INPUT = 13U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA11_SELECT_INPUT = 14U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA12_SELECT_INPUT = 15U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA13_SELECT_INPUT = 16U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA14_SELECT_INPUT = 17U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA15_SELECT_INPUT = 18U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA16_SELECT_INPUT = 19U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA17_SELECT_INPUT = 20U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA18_SELECT_INPUT = 21U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA19_SELECT_INPUT = 22U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA20_SELECT_INPUT = 23U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA21_SELECT_INPUT = 24U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA22_SELECT_INPUT = 25U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA23_SELECT_INPUT = 26U, /**< IOMUXC select input index */ + kIOMUXC_CSI_HSYNC_SELECT_INPUT = 27U, /**< IOMUXC select input index */ + kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 28U, /**< IOMUXC select input index */ + kIOMUXC_CSI_VSYNC_SELECT_INPUT = 29U, /**< IOMUXC select input index */ + kIOMUXC_CSI_FIELD_SELECT_INPUT = 30U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI1_SCLK_SELECT_INPUT = 31U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI1_MISO_SELECT_INPUT = 32U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI1_MOSI_SELECT_INPUT = 33U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI1_SS0_B_SELECT_INPUT = 34U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI2_SCLK_SELECT_INPUT = 35U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI2_MISO_SELECT_INPUT = 36U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI2_MOSI_SELECT_INPUT = 37U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI2_SS0_B_SELECT_INPUT = 38U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI3_SCLK_SELECT_INPUT = 39U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI3_MISO_SELECT_INPUT = 40U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI3_MOSI_SELECT_INPUT = 41U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI3_SS0_B_SELECT_INPUT = 42U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI4_SCLK_SELECT_INPUT = 43U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI4_MISO_SELECT_INPUT = 44U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI4_MOSI_SELECT_INPUT = 45U, /**< IOMUXC select input index */ + kIOMUXC_ECSPI4_SS0_B_SELECT_INPUT = 46U, /**< IOMUXC select input index */ + kIOMUXC_ENET1_REF_CLK1_SELECT_INPUT = 47U, /**< IOMUXC select input index */ + kIOMUXC_ENET1_MAC0_MDIO_SELECT_INPUT = 48U, /**< IOMUXC select input index */ + kIOMUXC_ENET2_REF_CLK2_SELECT_INPUT = 49U, /**< IOMUXC select input index */ + kIOMUXC_ENET2_MAC0_MDIO_SELECT_INPUT = 50U, /**< IOMUXC select input index */ + kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 51U, /**< IOMUXC select input index */ + kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 52U, /**< IOMUXC select input index */ + kIOMUXC_GPT1_CAPTURE1_SELECT_INPUT = 53U, /**< IOMUXC select input index */ + kIOMUXC_GPT1_CAPTURE2_SELECT_INPUT = 54U, /**< IOMUXC select input index */ + kIOMUXC_GPT1_CLK_SELECT_INPUT = 55U, /**< IOMUXC select input index */ + kIOMUXC_GPT2_CAPTURE1_SELECT_INPUT = 56U, /**< IOMUXC select input index */ + kIOMUXC_GPT2_CAPTURE2_SELECT_INPUT = 57U, /**< IOMUXC select input index */ + kIOMUXC_GPT2_CLK_SELECT_INPUT = 58U, /**< IOMUXC select input index */ + kIOMUXC_I2C1_SCL_SELECT_INPUT = 59U, /**< IOMUXC select input index */ + kIOMUXC_I2C1_SDA_SELECT_INPUT = 60U, /**< IOMUXC select input index */ + kIOMUXC_I2C2_SCL_SELECT_INPUT = 61U, /**< IOMUXC select input index */ + kIOMUXC_I2C2_SDA_SELECT_INPUT = 62U, /**< IOMUXC select input index */ + kIOMUXC_I2C3_SCL_SELECT_INPUT = 63U, /**< IOMUXC select input index */ + kIOMUXC_I2C3_SDA_SELECT_INPUT = 64U, /**< IOMUXC select input index */ + kIOMUXC_I2C4_SCL_SELECT_INPUT = 65U, /**< IOMUXC select input index */ + kIOMUXC_I2C4_SDA_SELECT_INPUT = 66U, /**< IOMUXC select input index */ + kIOMUXC_KPP_COL0_SELECT_INPUT = 67U, /**< IOMUXC select input index */ + kIOMUXC_KPP_COL1_SELECT_INPUT = 68U, /**< IOMUXC select input index */ + kIOMUXC_KPP_COL2_SELECT_INPUT = 69U, /**< IOMUXC select input index */ + kIOMUXC_KPP_ROW0_SELECT_INPUT = 70U, /**< IOMUXC select input index */ + kIOMUXC_KPP_ROW1_SELECT_INPUT = 71U, /**< IOMUXC select input index */ + kIOMUXC_KPP_ROW2_SELECT_INPUT = 72U, /**< IOMUXC select input index */ + kIOMUXC_LCD_BUSY_SELECT_INPUT = 73U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_MCLK_SELECT_INPUT = 74U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA_SELECT_INPUT = 75U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 76U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 77U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_MCLK_SELECT_INPUT = 78U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_RX_DATA_SELECT_INPUT = 79U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 80U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 81U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_MCLK_SELECT_INPUT = 82U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_RX_DATA_SELECT_INPUT = 83U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_TX_BCLK_SELECT_INPUT = 84U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_TX_SYNC_SELECT_INPUT = 85U, /**< IOMUXC select input index */ + kIOMUXC_SDMA_EVENTS0_SELECT_INPUT = 86U, /**< IOMUXC select input index */ + kIOMUXC_SDMA_EVENTS1_SELECT_INPUT = 87U, /**< IOMUXC select input index */ + kIOMUXC_SPDIF_IN_SELECT_INPUT = 88U, /**< IOMUXC select input index */ + kIOMUXC_SPDIF_EXT_CLK_SELECT_INPUT = 89U, /**< IOMUXC select input index */ + kIOMUXC_UART1_RTS_B_SELECT_INPUT = 90U, /**< IOMUXC select input index */ + kIOMUXC_UART1_RX_DATA_SELECT_INPUT = 91U, /**< IOMUXC select input index */ + kIOMUXC_UART2_RTS_B_SELECT_INPUT = 92U, /**< IOMUXC select input index */ + kIOMUXC_UART2_RX_DATA_SELECT_INPUT = 93U, /**< IOMUXC select input index */ + kIOMUXC_UART3_RTS_B_SELECT_INPUT = 94U, /**< IOMUXC select input index */ + kIOMUXC_UART3_RX_DATA_SELECT_INPUT = 95U, /**< IOMUXC select input index */ + kIOMUXC_UART4_RTS_B_SELECT_INPUT = 96U, /**< IOMUXC select input index */ + kIOMUXC_UART4_RX_DATA_SELECT_INPUT = 97U, /**< IOMUXC select input index */ + kIOMUXC_UART5_RTS_B_SELECT_INPUT = 98U, /**< IOMUXC select input index */ + kIOMUXC_UART5_RX_DATA_SELECT_INPUT = 99U, /**< IOMUXC select input index */ + kIOMUXC_UART6_RTS_B_SELECT_INPUT = 100U, /**< IOMUXC select input index */ + kIOMUXC_UART6_RX_DATA_SELECT_INPUT = 101U, /**< IOMUXC select input index */ + kIOMUXC_UART7_RTS_B_SELECT_INPUT = 102U, /**< IOMUXC select input index */ + kIOMUXC_UART7_RX_DATA_SELECT_INPUT = 103U, /**< IOMUXC select input index */ + kIOMUXC_UART8_RTS_B_SELECT_INPUT = 104U, /**< IOMUXC select input index */ + kIOMUXC_UART8_RX_DATA_SELECT_INPUT = 105U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 106U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG_OC_SELECT_INPUT = 107U, /**< IOMUXC select input index */ + kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 108U, /**< IOMUXC select input index */ + kIOMUXC_USDHC1_WP_SELECT_INPUT = 109U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CLK_SELECT_INPUT = 110U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 111U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CMD_SELECT_INPUT = 112U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 113U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 114U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 115U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 116U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 117U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 118U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 119U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 120U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_WP_SELECT_INPUT = 121U, /**< IOMUXC select input index */ +} iomuxc_select_input_t; + +/* @} */ + +/*! + * @brief Enumeration for the IOMUXC group + * + * Defines the enumeration for the IOMUXC group collections. + */ +typedef enum _iomuxc_grp +{ + kIOMUXC_SW_PAD_CTL_GRP_ADDDS = 0U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL = 1U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_B0DS = 2U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRPK = 3U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_CTLDS = 4U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_B1DS = 5U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRHYS = 6U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRPKE = 7U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDRMODE = 8U, /**< IOMUXC group index */ + kIOMUXC_SW_PAD_CTL_GRP_DDR_TYPE = 9U, /**< IOMUXC group index */ +} iomuxc_grp_t; + +/* @} */ + +/*! + * @addtogroup iomuxc_snvs_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC_SNVS SW_MUX_CTL_PAD + * + * Defines the enumeration for the IOMUXC_SNVS SW_MUX_CTL_PAD collections. + */ +typedef enum _iomuxc_snvs_sw_mux_ctl_pad +{ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_BOOT_MODE0 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_BOOT_MODE1 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER0 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER1 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER2 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER3 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER4 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER5 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER6 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER7 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER8 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SNVS_SW_MUX_CTL_PAD_SNVS_TAMPER9 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ +} iomuxc_snvs_sw_mux_ctl_pad_t; + +/*! + * @addtogroup iomuxc_snvs_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC_SNVS SW_PAD_CTL_PAD + * + * Defines the enumeration for the IOMUXC_SNVS SW_PAD_CTL_PAD collections. + */ +typedef enum _iomuxc_snvs_sw_pad_ctl_pad +{ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_PMIC_ON_REQ = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_CCM_PMIC_STBY_REQ = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_BOOT_MODE0 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_BOOT_MODE1 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER0 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER1 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER2 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER3 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER4 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER5 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER6 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER7 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER8 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SNVS_SW_PAD_CTL_PAD_SNVS_TAMPER9 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ +} iomuxc_snvs_sw_pad_ctl_pad_t; + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t HC[1]; /**< Control register, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[4]; + __I uint32_t HS; /**< Status register, offset: 0x8 */ + __I uint32_t R[1]; /**< Data result register, array offset: 0xC, array step: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CFG; /**< Configuration register, offset: 0x14 */ + __IO uint32_t GC; /**< General control register, offset: 0x18 */ + __IO uint32_t GS; /**< General status register, offset: 0x1C */ + __IO uint32_t CV; /**< Compare value register, offset: 0x20 */ + __IO uint32_t OFS; /**< Offset correction value register, offset: 0x24 */ + __IO uint32_t CAL; /**< Calibration value register, offset: 0x28 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name HC - Control register */ +#define ADC_HC_ADCH_MASK (0x1FU) +#define ADC_HC_ADCH_SHIFT (0U) +#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) +#define ADC_HC_AIEN_MASK (0x80U) +#define ADC_HC_AIEN_SHIFT (7U) +#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK) + +/* The count of ADC_HC */ +#define ADC_HC_COUNT (1U) + +/*! @name HS - Status register */ +#define ADC_HS_COCO0_MASK (0x1U) +#define ADC_HS_COCO0_SHIFT (0U) +#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK) + +/*! @name R - Data result register */ +#define ADC_R_CDATA_MASK (0xFFFU) +#define ADC_R_CDATA_SHIFT (0U) +#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK) + +/* The count of ADC_R */ +#define ADC_R_COUNT (1U) + +/*! @name CFG - Configuration register */ +#define ADC_CFG_ADICLK_MASK (0x3U) +#define ADC_CFG_ADICLK_SHIFT (0U) +#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) +#define ADC_CFG_MODE_MASK (0xCU) +#define ADC_CFG_MODE_SHIFT (2U) +#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) +#define ADC_CFG_ADLSMP_MASK (0x10U) +#define ADC_CFG_ADLSMP_SHIFT (4U) +#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) +#define ADC_CFG_ADIV_MASK (0x60U) +#define ADC_CFG_ADIV_SHIFT (5U) +#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) +#define ADC_CFG_ADLPC_MASK (0x80U) +#define ADC_CFG_ADLPC_SHIFT (7U) +#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) +#define ADC_CFG_ADSTS_MASK (0x300U) +#define ADC_CFG_ADSTS_SHIFT (8U) +#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) +#define ADC_CFG_ADHSC_MASK (0x400U) +#define ADC_CFG_ADHSC_SHIFT (10U) +#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) +#define ADC_CFG_REFSEL_MASK (0x1800U) +#define ADC_CFG_REFSEL_SHIFT (11U) +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) +#define ADC_CFG_ADTRG_MASK (0x2000U) +#define ADC_CFG_ADTRG_SHIFT (13U) +#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) +#define ADC_CFG_AVGS_MASK (0xC000U) +#define ADC_CFG_AVGS_SHIFT (14U) +#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) +#define ADC_CFG_OVWREN_MASK (0x10000U) +#define ADC_CFG_OVWREN_SHIFT (16U) +#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) + +/*! @name GC - General control register */ +#define ADC_GC_ADACKEN_MASK (0x1U) +#define ADC_GC_ADACKEN_SHIFT (0U) +#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) +#define ADC_GC_DMAEN_MASK (0x2U) +#define ADC_GC_DMAEN_SHIFT (1U) +#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) +#define ADC_GC_ACREN_MASK (0x4U) +#define ADC_GC_ACREN_SHIFT (2U) +#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) +#define ADC_GC_ACFGT_MASK (0x8U) +#define ADC_GC_ACFGT_SHIFT (3U) +#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) +#define ADC_GC_ACFE_MASK (0x10U) +#define ADC_GC_ACFE_SHIFT (4U) +#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) +#define ADC_GC_AVGE_MASK (0x20U) +#define ADC_GC_AVGE_SHIFT (5U) +#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) +#define ADC_GC_ADCO_MASK (0x40U) +#define ADC_GC_ADCO_SHIFT (6U) +#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) +#define ADC_GC_CAL_MASK (0x80U) +#define ADC_GC_CAL_SHIFT (7U) +#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) + +/*! @name GS - General status register */ +#define ADC_GS_ADACT_MASK (0x1U) +#define ADC_GS_ADACT_SHIFT (0U) +#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) +#define ADC_GS_CALF_MASK (0x2U) +#define ADC_GS_CALF_SHIFT (1U) +#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) +#define ADC_GS_AWKST_MASK (0x4U) +#define ADC_GS_AWKST_SHIFT (2U) +#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) + +/*! @name CV - Compare value register */ +#define ADC_CV_CV1_MASK (0xFFFU) +#define ADC_CV_CV1_SHIFT (0U) +#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) +#define ADC_CV_CV2_MASK (0xFFF0000U) +#define ADC_CV_CV2_SHIFT (16U) +#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) + +/*! @name OFS - Offset correction value register */ +#define ADC_OFS_OFS_MASK (0xFFFU) +#define ADC_OFS_OFS_SHIFT (0U) +#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) +#define ADC_OFS_SIGN_MASK (0x1000U) +#define ADC_OFS_SIGN_SHIFT (12U) +#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) + +/*! @name CAL - Calibration value register */ +#define ADC_CAL_CAL_CODE_MASK (0xFU) +#define ADC_CAL_CAL_CODE_SHIFT (0U) +#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x2198000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { 0u, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ADC_5HC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_5HC_Peripheral_Access_Layer ADC_5HC Peripheral Access Layer + * @{ + */ + +/** ADC_5HC - Register Layout Typedef */ +typedef struct { + __IO uint32_t HC[5]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */ + __I uint32_t HS; /**< Status register for HW triggers, offset: 0x14 */ + __I uint32_t R[5]; /**< Data result register for HW triggers, array offset: 0x18, array step: 0x4 */ + __IO uint32_t CFG; /**< Configuration register, offset: 0x2C */ + __IO uint32_t GC; /**< General control register, offset: 0x30 */ + __IO uint32_t GS; /**< General status register, offset: 0x34 */ + __IO uint32_t CV; /**< Compare value register, offset: 0x38 */ + __IO uint32_t OFS; /**< Offset correction value register, offset: 0x3C */ + __IO uint32_t CAL; /**< Calibration value register, offset: 0x40 */ +} ADC_5HC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC_5HC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_5HC_Register_Masks ADC_5HC Register Masks + * @{ + */ + +/*! @name HC - Control register for hardware triggers */ +#define ADC_5HC_HC_ADCH_MASK (0x1FU) +#define ADC_5HC_HC_ADCH_SHIFT (0U) +#define ADC_5HC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HC_ADCH_SHIFT)) & ADC_5HC_HC_ADCH_MASK) +#define ADC_5HC_HC_AIEN_MASK (0x80U) +#define ADC_5HC_HC_AIEN_SHIFT (7U) +#define ADC_5HC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HC_AIEN_SHIFT)) & ADC_5HC_HC_AIEN_MASK) + +/* The count of ADC_5HC_HC */ +#define ADC_5HC_HC_COUNT (5U) + +/*! @name HS - Status register for HW triggers */ +#define ADC_5HC_HS_COCO0_MASK (0x1U) +#define ADC_5HC_HS_COCO0_SHIFT (0U) +#define ADC_5HC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO0_SHIFT)) & ADC_5HC_HS_COCO0_MASK) +#define ADC_5HC_HS_COCO1_MASK (0x2U) +#define ADC_5HC_HS_COCO1_SHIFT (1U) +#define ADC_5HC_HS_COCO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO1_SHIFT)) & ADC_5HC_HS_COCO1_MASK) +#define ADC_5HC_HS_COCO2_MASK (0x4U) +#define ADC_5HC_HS_COCO2_SHIFT (2U) +#define ADC_5HC_HS_COCO2(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO2_SHIFT)) & ADC_5HC_HS_COCO2_MASK) +#define ADC_5HC_HS_COCO3_MASK (0x8U) +#define ADC_5HC_HS_COCO3_SHIFT (3U) +#define ADC_5HC_HS_COCO3(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO3_SHIFT)) & ADC_5HC_HS_COCO3_MASK) +#define ADC_5HC_HS_COCO4_MASK (0x10U) +#define ADC_5HC_HS_COCO4_SHIFT (4U) +#define ADC_5HC_HS_COCO4(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_HS_COCO4_SHIFT)) & ADC_5HC_HS_COCO4_MASK) + +/*! @name R - Data result register for HW triggers */ +#define ADC_5HC_R_CDATA_MASK (0xFFFU) +#define ADC_5HC_R_CDATA_SHIFT (0U) +#define ADC_5HC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_R_CDATA_SHIFT)) & ADC_5HC_R_CDATA_MASK) + +/* The count of ADC_5HC_R */ +#define ADC_5HC_R_COUNT (5U) + +/*! @name CFG - Configuration register */ +#define ADC_5HC_CFG_ADICLK_MASK (0x3U) +#define ADC_5HC_CFG_ADICLK_SHIFT (0U) +#define ADC_5HC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADICLK_SHIFT)) & ADC_5HC_CFG_ADICLK_MASK) +#define ADC_5HC_CFG_MODE_MASK (0xCU) +#define ADC_5HC_CFG_MODE_SHIFT (2U) +#define ADC_5HC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_MODE_SHIFT)) & ADC_5HC_CFG_MODE_MASK) +#define ADC_5HC_CFG_ADLSMP_MASK (0x10U) +#define ADC_5HC_CFG_ADLSMP_SHIFT (4U) +#define ADC_5HC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADLSMP_SHIFT)) & ADC_5HC_CFG_ADLSMP_MASK) +#define ADC_5HC_CFG_ADIV_MASK (0x60U) +#define ADC_5HC_CFG_ADIV_SHIFT (5U) +#define ADC_5HC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADIV_SHIFT)) & ADC_5HC_CFG_ADIV_MASK) +#define ADC_5HC_CFG_ADLPC_MASK (0x80U) +#define ADC_5HC_CFG_ADLPC_SHIFT (7U) +#define ADC_5HC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADLPC_SHIFT)) & ADC_5HC_CFG_ADLPC_MASK) +#define ADC_5HC_CFG_ADSTS_MASK (0x300U) +#define ADC_5HC_CFG_ADSTS_SHIFT (8U) +#define ADC_5HC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADSTS_SHIFT)) & ADC_5HC_CFG_ADSTS_MASK) +#define ADC_5HC_CFG_ADHSC_MASK (0x400U) +#define ADC_5HC_CFG_ADHSC_SHIFT (10U) +#define ADC_5HC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADHSC_SHIFT)) & ADC_5HC_CFG_ADHSC_MASK) +#define ADC_5HC_CFG_REFSEL_MASK (0x1800U) +#define ADC_5HC_CFG_REFSEL_SHIFT (11U) +#define ADC_5HC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_REFSEL_SHIFT)) & ADC_5HC_CFG_REFSEL_MASK) +#define ADC_5HC_CFG_ADTRG_MASK (0x2000U) +#define ADC_5HC_CFG_ADTRG_SHIFT (13U) +#define ADC_5HC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_ADTRG_SHIFT)) & ADC_5HC_CFG_ADTRG_MASK) +#define ADC_5HC_CFG_AVGS_MASK (0xC000U) +#define ADC_5HC_CFG_AVGS_SHIFT (14U) +#define ADC_5HC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_AVGS_SHIFT)) & ADC_5HC_CFG_AVGS_MASK) +#define ADC_5HC_CFG_OVWREN_MASK (0x10000U) +#define ADC_5HC_CFG_OVWREN_SHIFT (16U) +#define ADC_5HC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CFG_OVWREN_SHIFT)) & ADC_5HC_CFG_OVWREN_MASK) + +/*! @name GC - General control register */ +#define ADC_5HC_GC_ADACKEN_MASK (0x1U) +#define ADC_5HC_GC_ADACKEN_SHIFT (0U) +#define ADC_5HC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ADACKEN_SHIFT)) & ADC_5HC_GC_ADACKEN_MASK) +#define ADC_5HC_GC_DMAEN_MASK (0x2U) +#define ADC_5HC_GC_DMAEN_SHIFT (1U) +#define ADC_5HC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_DMAEN_SHIFT)) & ADC_5HC_GC_DMAEN_MASK) +#define ADC_5HC_GC_ACREN_MASK (0x4U) +#define ADC_5HC_GC_ACREN_SHIFT (2U) +#define ADC_5HC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ACREN_SHIFT)) & ADC_5HC_GC_ACREN_MASK) +#define ADC_5HC_GC_ACFGT_MASK (0x8U) +#define ADC_5HC_GC_ACFGT_SHIFT (3U) +#define ADC_5HC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ACFGT_SHIFT)) & ADC_5HC_GC_ACFGT_MASK) +#define ADC_5HC_GC_ACFE_MASK (0x10U) +#define ADC_5HC_GC_ACFE_SHIFT (4U) +#define ADC_5HC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ACFE_SHIFT)) & ADC_5HC_GC_ACFE_MASK) +#define ADC_5HC_GC_AVGE_MASK (0x20U) +#define ADC_5HC_GC_AVGE_SHIFT (5U) +#define ADC_5HC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_AVGE_SHIFT)) & ADC_5HC_GC_AVGE_MASK) +#define ADC_5HC_GC_ADCO_MASK (0x40U) +#define ADC_5HC_GC_ADCO_SHIFT (6U) +#define ADC_5HC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_ADCO_SHIFT)) & ADC_5HC_GC_ADCO_MASK) +#define ADC_5HC_GC_CAL_MASK (0x80U) +#define ADC_5HC_GC_CAL_SHIFT (7U) +#define ADC_5HC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GC_CAL_SHIFT)) & ADC_5HC_GC_CAL_MASK) + +/*! @name GS - General status register */ +#define ADC_5HC_GS_ADACT_MASK (0x1U) +#define ADC_5HC_GS_ADACT_SHIFT (0U) +#define ADC_5HC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GS_ADACT_SHIFT)) & ADC_5HC_GS_ADACT_MASK) +#define ADC_5HC_GS_CALF_MASK (0x2U) +#define ADC_5HC_GS_CALF_SHIFT (1U) +#define ADC_5HC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GS_CALF_SHIFT)) & ADC_5HC_GS_CALF_MASK) +#define ADC_5HC_GS_AWKST_MASK (0x4U) +#define ADC_5HC_GS_AWKST_SHIFT (2U) +#define ADC_5HC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_GS_AWKST_SHIFT)) & ADC_5HC_GS_AWKST_MASK) + +/*! @name CV - Compare value register */ +#define ADC_5HC_CV_CV1_MASK (0xFFFU) +#define ADC_5HC_CV_CV1_SHIFT (0U) +#define ADC_5HC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CV_CV1_SHIFT)) & ADC_5HC_CV_CV1_MASK) +#define ADC_5HC_CV_CV2_MASK (0xFFF0000U) +#define ADC_5HC_CV_CV2_SHIFT (16U) +#define ADC_5HC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CV_CV2_SHIFT)) & ADC_5HC_CV_CV2_MASK) + +/*! @name OFS - Offset correction value register */ +#define ADC_5HC_OFS_OFS_MASK (0xFFFU) +#define ADC_5HC_OFS_OFS_SHIFT (0U) +#define ADC_5HC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_OFS_OFS_SHIFT)) & ADC_5HC_OFS_OFS_MASK) +#define ADC_5HC_OFS_SIGN_MASK (0x1000U) +#define ADC_5HC_OFS_SIGN_SHIFT (12U) +#define ADC_5HC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_OFS_SIGN_SHIFT)) & ADC_5HC_OFS_SIGN_MASK) + +/*! @name CAL - Calibration value register */ +#define ADC_5HC_CAL_CAL_CODE_MASK (0xFU) +#define ADC_5HC_CAL_CAL_CODE_SHIFT (0U) +#define ADC_5HC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_5HC_CAL_CAL_CODE_SHIFT)) & ADC_5HC_CAL_CAL_CODE_MASK) + + +/*! + * @} + */ /* end of group ADC_5HC_Register_Masks */ + + +/* ADC_5HC - Peripheral instance base addresses */ +/** Peripheral ADC_5HC base address */ +#define ADC_5HC_BASE (0x219C000u) +/** Peripheral ADC_5HC base pointer */ +#define ADC_5HC ((ADC_5HC_Type *)ADC_5HC_BASE) +/** Array initializer of ADC_5HC peripheral base addresses */ +#define ADC_5HC_BASE_ADDRS { ADC_5HC_BASE } +/** Array initializer of ADC_5HC peripheral base pointers */ +#define ADC_5HC_BASE_PTRS { ADC_5HC } +/** Interrupt vectors for the ADC_5HC peripheral type */ +#define ADC_5HC_IRQS { ADC_5HC_IRQn } + +/*! + * @} + */ /* end of group ADC_5HC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer + * @{ + */ + +/** AIPSTZ - Register Layout Typedef */ +typedef struct { + __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */ + __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */ + __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */ + __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */ + __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */ +} AIPSTZ_Type; + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks + * @{ + */ + +/*! @name MPR - Master Priviledge Registers */ +#define AIPSTZ_MPR_MPROT5_MASK (0xF00U) +#define AIPSTZ_MPR_MPROT5_SHIFT (8U) +#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) +#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U) +#define AIPSTZ_MPR_MPROT3_SHIFT (16U) +#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) +#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U) +#define AIPSTZ_MPR_MPROT2_SHIFT (20U) +#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) +#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U) +#define AIPSTZ_MPR_MPROT1_SHIFT (24U) +#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) +#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) +#define AIPSTZ_MPR_MPROT0_SHIFT (28U) +#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) + +/*! @name OPACR - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR_OPAC7_MASK (0xFU) +#define AIPSTZ_OPACR_OPAC7_SHIFT (0U) +#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) +#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U) +#define AIPSTZ_OPACR_OPAC6_SHIFT (4U) +#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK) +#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U) +#define AIPSTZ_OPACR_OPAC5_SHIFT (8U) +#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK) +#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U) +#define AIPSTZ_OPACR_OPAC4_SHIFT (12U) +#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK) +#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U) +#define AIPSTZ_OPACR_OPAC3_SHIFT (16U) +#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK) +#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U) +#define AIPSTZ_OPACR_OPAC2_SHIFT (20U) +#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK) +#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U) +#define AIPSTZ_OPACR_OPAC1_SHIFT (24U) +#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK) +#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) +#define AIPSTZ_OPACR_OPAC0_SHIFT (28U) +#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) + +/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) +#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) +#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) +#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U) +#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U) +#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK) +#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U) +#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U) +#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK) +#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U) +#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U) +#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK) +#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U) +#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U) +#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK) +#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U) +#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U) +#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK) +#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U) +#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U) +#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK) +#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) +#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) +#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) + +/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) +#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) +#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) +#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U) +#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U) +#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK) +#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U) +#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U) +#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK) +#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U) +#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U) +#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK) +#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U) +#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U) +#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK) +#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U) +#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U) +#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK) +#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U) +#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U) +#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK) +#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) +#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) +#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) + +/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) +#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) +#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) +#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U) +#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U) +#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK) +#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U) +#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U) +#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK) +#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U) +#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U) +#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK) +#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U) +#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U) +#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK) +#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U) +#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U) +#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK) +#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U) +#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U) +#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK) +#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) +#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) +#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) + +/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */ +#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) +#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) +#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) +#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) +#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) +#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) + + +/*! + * @} + */ /* end of group AIPSTZ_Register_Masks */ + + +/* AIPSTZ - Peripheral instance base addresses */ +/** Peripheral AIPSTZ1 base address */ +#define AIPSTZ1_BASE (0x207C000u) +/** Peripheral AIPSTZ1 base pointer */ +#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE) +/** Peripheral AIPSTZ2 base address */ +#define AIPSTZ2_BASE (0x217C000u) +/** Peripheral AIPSTZ2 base pointer */ +#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE) +/** Peripheral AIPSTZ3 base address */ +#define AIPSTZ3_BASE (0x227C000u) +/** Peripheral AIPSTZ3 base pointer */ +#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE) +/** Array initializer of AIPSTZ peripheral base addresses */ +#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE } +/** Array initializer of AIPSTZ peripheral base pointers */ +#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3 } + +/*! + * @} + */ /* end of group AIPSTZ_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- APBH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer + * @{ + */ + +/** APBH - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */ + __IO uint32_t CTRL0_SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */ + __IO uint32_t CTRL0_CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */ + __IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */ + __IO uint32_t CTRL1; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */ + __IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */ + __IO uint32_t CTRL1_CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */ + __IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */ + __IO uint32_t CTRL2; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */ + __IO uint32_t CTRL2_SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */ + __IO uint32_t CTRL2_CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */ + __IO uint32_t CTRL2_TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */ + __IO uint32_t CHANNEL_CTRL; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */ + __IO uint32_t CHANNEL_CTRL_SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */ + __IO uint32_t CHANNEL_CTRL_CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */ + __IO uint32_t CHANNEL_CTRL_TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */ + __I uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */ + uint8_t RESERVED_1[12]; + __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */ + uint8_t RESERVED_2[156]; + __I uint32_t CH0_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x100 */ + uint8_t RESERVED_3[12]; + __IO uint32_t CH0_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x110 */ + uint8_t RESERVED_4[12]; + __I uint32_t CH0_CMD; /**< APBH DMA Channel n Command Register, offset: 0x120 */ + uint8_t RESERVED_5[12]; + __I uint32_t CH0_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x130 */ + uint8_t RESERVED_6[12]; + __IO uint32_t CH0_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x140 */ + uint8_t RESERVED_7[12]; + __I uint32_t CH0_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x150 */ + uint8_t RESERVED_8[12]; + __I uint32_t CH0_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x160 */ + uint8_t RESERVED_9[12]; + __I uint32_t CH1_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x170 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CH1_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x180 */ + uint8_t RESERVED_11[12]; + __I uint32_t CH1_CMD; /**< APBH DMA Channel n Command Register, offset: 0x190 */ + uint8_t RESERVED_12[12]; + __I uint32_t CH1_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x1A0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CH1_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x1B0 */ + uint8_t RESERVED_14[12]; + __I uint32_t CH1_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1C0 */ + uint8_t RESERVED_15[12]; + __I uint32_t CH1_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1D0 */ + uint8_t RESERVED_16[12]; + __I uint32_t CH2_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x1E0 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CH2_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x1F0 */ + uint8_t RESERVED_18[12]; + __I uint32_t CH2_CMD; /**< APBH DMA Channel n Command Register, offset: 0x200 */ + uint8_t RESERVED_19[12]; + __I uint32_t CH2_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x210 */ + uint8_t RESERVED_20[12]; + __IO uint32_t CH2_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x220 */ + uint8_t RESERVED_21[12]; + __I uint32_t CH2_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x230 */ + uint8_t RESERVED_22[12]; + __I uint32_t CH2_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x240 */ + uint8_t RESERVED_23[12]; + __I uint32_t CH3_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x250 */ + uint8_t RESERVED_24[12]; + __IO uint32_t CH3_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x260 */ + uint8_t RESERVED_25[12]; + __I uint32_t CH3_CMD; /**< APBH DMA Channel n Command Register, offset: 0x270 */ + uint8_t RESERVED_26[12]; + __I uint32_t CH3_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x280 */ + uint8_t RESERVED_27[12]; + __IO uint32_t CH3_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x290 */ + uint8_t RESERVED_28[12]; + __I uint32_t CH3_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2A0 */ + uint8_t RESERVED_29[12]; + __I uint32_t CH3_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2B0 */ + uint8_t RESERVED_30[12]; + __I uint32_t CH4_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x2C0 */ + uint8_t RESERVED_31[12]; + __IO uint32_t CH4_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x2D0 */ + uint8_t RESERVED_32[12]; + __I uint32_t CH4_CMD; /**< APBH DMA Channel n Command Register, offset: 0x2E0 */ + uint8_t RESERVED_33[12]; + __I uint32_t CH4_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x2F0 */ + uint8_t RESERVED_34[12]; + __IO uint32_t CH4_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x300 */ + uint8_t RESERVED_35[12]; + __I uint32_t CH4_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x310 */ + uint8_t RESERVED_36[12]; + __I uint32_t CH4_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x320 */ + uint8_t RESERVED_37[12]; + __I uint32_t CH5_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x330 */ + uint8_t RESERVED_38[12]; + __IO uint32_t CH5_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x340 */ + uint8_t RESERVED_39[12]; + __I uint32_t CH5_CMD; /**< APBH DMA Channel n Command Register, offset: 0x350 */ + uint8_t RESERVED_40[12]; + __I uint32_t CH5_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x360 */ + uint8_t RESERVED_41[12]; + __IO uint32_t CH5_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x370 */ + uint8_t RESERVED_42[12]; + __I uint32_t CH5_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x380 */ + uint8_t RESERVED_43[12]; + __I uint32_t CH5_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x390 */ + uint8_t RESERVED_44[12]; + __I uint32_t CH6_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x3A0 */ + uint8_t RESERVED_45[12]; + __IO uint32_t CH6_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x3B0 */ + uint8_t RESERVED_46[12]; + __I uint32_t CH6_CMD; /**< APBH DMA Channel n Command Register, offset: 0x3C0 */ + uint8_t RESERVED_47[12]; + __I uint32_t CH6_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x3D0 */ + uint8_t RESERVED_48[12]; + __IO uint32_t CH6_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x3E0 */ + uint8_t RESERVED_49[12]; + __I uint32_t CH6_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x3F0 */ + uint8_t RESERVED_50[12]; + __I uint32_t CH6_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x400 */ + uint8_t RESERVED_51[12]; + __I uint32_t CH7_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x410 */ + uint8_t RESERVED_52[12]; + __IO uint32_t CH7_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x420 */ + uint8_t RESERVED_53[12]; + __I uint32_t CH7_CMD; /**< APBH DMA Channel n Command Register, offset: 0x430 */ + uint8_t RESERVED_54[12]; + __I uint32_t CH7_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x440 */ + uint8_t RESERVED_55[12]; + __IO uint32_t CH7_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x450 */ + uint8_t RESERVED_56[12]; + __I uint32_t CH7_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x460 */ + uint8_t RESERVED_57[12]; + __I uint32_t CH7_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x470 */ + uint8_t RESERVED_58[12]; + __I uint32_t CH8_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x480 */ + uint8_t RESERVED_59[12]; + __IO uint32_t CH8_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x490 */ + uint8_t RESERVED_60[12]; + __I uint32_t CH8_CMD; /**< APBH DMA Channel n Command Register, offset: 0x4A0 */ + uint8_t RESERVED_61[12]; + __I uint32_t CH8_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x4B0 */ + uint8_t RESERVED_62[12]; + __IO uint32_t CH8_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x4C0 */ + uint8_t RESERVED_63[12]; + __I uint32_t CH8_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4D0 */ + uint8_t RESERVED_64[12]; + __I uint32_t CH8_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4E0 */ + uint8_t RESERVED_65[12]; + __I uint32_t CH9_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x4F0 */ + uint8_t RESERVED_66[12]; + __IO uint32_t CH9_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x500 */ + uint8_t RESERVED_67[12]; + __I uint32_t CH9_CMD; /**< APBH DMA Channel n Command Register, offset: 0x510 */ + uint8_t RESERVED_68[12]; + __I uint32_t CH9_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x520 */ + uint8_t RESERVED_69[12]; + __IO uint32_t CH9_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x530 */ + uint8_t RESERVED_70[12]; + __I uint32_t CH9_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x540 */ + uint8_t RESERVED_71[12]; + __I uint32_t CH9_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x550 */ + uint8_t RESERVED_72[12]; + __I uint32_t CH10_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x560 */ + uint8_t RESERVED_73[12]; + __IO uint32_t CH10_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x570 */ + uint8_t RESERVED_74[12]; + __I uint32_t CH10_CMD; /**< APBH DMA Channel n Command Register, offset: 0x580 */ + uint8_t RESERVED_75[12]; + __I uint32_t CH10_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x590 */ + uint8_t RESERVED_76[12]; + __IO uint32_t CH10_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x5A0 */ + uint8_t RESERVED_77[12]; + __I uint32_t CH10_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5B0 */ + uint8_t RESERVED_78[12]; + __I uint32_t CH10_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5C0 */ + uint8_t RESERVED_79[12]; + __I uint32_t CH11_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x5D0 */ + uint8_t RESERVED_80[12]; + __IO uint32_t CH11_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x5E0 */ + uint8_t RESERVED_81[12]; + __I uint32_t CH11_CMD; /**< APBH DMA Channel n Command Register, offset: 0x5F0 */ + uint8_t RESERVED_82[12]; + __I uint32_t CH11_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x600 */ + uint8_t RESERVED_83[12]; + __IO uint32_t CH11_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x610 */ + uint8_t RESERVED_84[12]; + __I uint32_t CH11_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x620 */ + uint8_t RESERVED_85[12]; + __I uint32_t CH11_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x630 */ + uint8_t RESERVED_86[12]; + __I uint32_t CH12_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x640 */ + uint8_t RESERVED_87[12]; + __IO uint32_t CH12_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x650 */ + uint8_t RESERVED_88[12]; + __I uint32_t CH12_CMD; /**< APBH DMA Channel n Command Register, offset: 0x660 */ + uint8_t RESERVED_89[12]; + __I uint32_t CH12_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x670 */ + uint8_t RESERVED_90[12]; + __IO uint32_t CH12_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x680 */ + uint8_t RESERVED_91[12]; + __I uint32_t CH12_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x690 */ + uint8_t RESERVED_92[12]; + __I uint32_t CH12_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x6A0 */ + uint8_t RESERVED_93[12]; + __I uint32_t CH13_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x6B0 */ + uint8_t RESERVED_94[12]; + __IO uint32_t CH13_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x6C0 */ + uint8_t RESERVED_95[12]; + __I uint32_t CH13_CMD; /**< APBH DMA Channel n Command Register, offset: 0x6D0 */ + uint8_t RESERVED_96[12]; + __I uint32_t CH13_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x6E0 */ + uint8_t RESERVED_97[12]; + __IO uint32_t CH13_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x6F0 */ + uint8_t RESERVED_98[12]; + __I uint32_t CH13_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x700 */ + uint8_t RESERVED_99[12]; + __I uint32_t CH13_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x710 */ + uint8_t RESERVED_100[12]; + __I uint32_t CH14_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x720 */ + uint8_t RESERVED_101[12]; + __IO uint32_t CH14_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x730 */ + uint8_t RESERVED_102[12]; + __I uint32_t CH14_CMD; /**< APBH DMA Channel n Command Register, offset: 0x740 */ + uint8_t RESERVED_103[12]; + __I uint32_t CH14_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x750 */ + uint8_t RESERVED_104[12]; + __IO uint32_t CH14_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x760 */ + uint8_t RESERVED_105[12]; + __I uint32_t CH14_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x770 */ + uint8_t RESERVED_106[12]; + __I uint32_t CH14_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x780 */ + uint8_t RESERVED_107[12]; + __I uint32_t CH15_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x790 */ + uint8_t RESERVED_108[12]; + __IO uint32_t CH15_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x7A0 */ + uint8_t RESERVED_109[12]; + __I uint32_t CH15_CMD; /**< APBH DMA Channel n Command Register, offset: 0x7B0 */ + uint8_t RESERVED_110[12]; + __I uint32_t CH15_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x7C0 */ + uint8_t RESERVED_111[12]; + __IO uint32_t CH15_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x7D0 */ + uint8_t RESERVED_112[12]; + __I uint32_t CH15_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7E0 */ + uint8_t RESERVED_113[12]; + __I uint32_t CH15_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7F0 */ + uint8_t RESERVED_114[12]; + __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */ +} APBH_Type; + +/* ---------------------------------------------------------------------------- + -- APBH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup APBH_Register_Masks APBH Register Masks + * @{ + */ + +/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */ +#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U) +#define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_RSVD0_SHIFT (16U) +#define APBH_CTRL0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_RSVD0_SHIFT)) & APBH_CTRL0_RSVD0_MASK) +#define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK) +#define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK) +#define APBH_CTRL0_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK) +#define APBH_CTRL0_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_SFTRST_SHIFT (31U) +#define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK) + +/*! @name CTRL0_SET - AHB to APBH Bridge Control and Status Register 0 */ +#define APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT (0U) +#define APBH_CTRL0_SET_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_SET_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_SET_RSVD0_SHIFT (16U) +#define APBH_CTRL0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_RSVD0_SHIFT)) & APBH_CTRL0_SET_RSVD0_MASK) +#define APBH_CTRL0_SET_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_SET_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_SET_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_APB_BURST_EN_SHIFT)) & APBH_CTRL0_SET_APB_BURST_EN_MASK) +#define APBH_CTRL0_SET_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_SET_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_SET_AHB_BURST8_EN_MASK) +#define APBH_CTRL0_SET_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_SET_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_SHIFT)) & APBH_CTRL0_SET_CLKGATE_MASK) +#define APBH_CTRL0_SET_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_SET_SFTRST_SHIFT (31U) +#define APBH_CTRL0_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_SFTRST_SHIFT)) & APBH_CTRL0_SET_SFTRST_MASK) + +/*! @name CTRL0_CLR - AHB to APBH Bridge Control and Status Register 0 */ +#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT (0U) +#define APBH_CTRL0_CLR_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_CLR_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_CLR_RSVD0_SHIFT (16U) +#define APBH_CTRL0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_RSVD0_SHIFT)) & APBH_CTRL0_CLR_RSVD0_MASK) +#define APBH_CTRL0_CLR_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_CLR_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_CLR_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_APB_BURST_EN_SHIFT)) & APBH_CTRL0_CLR_APB_BURST_EN_MASK) +#define APBH_CTRL0_CLR_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_CLR_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_CLR_AHB_BURST8_EN_MASK) +#define APBH_CTRL0_CLR_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_CLR_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_MASK) +#define APBH_CTRL0_CLR_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_CLR_SFTRST_SHIFT (31U) +#define APBH_CTRL0_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_SFTRST_SHIFT)) & APBH_CTRL0_CLR_SFTRST_MASK) + +/*! @name CTRL0_TOG - AHB to APBH Bridge Control and Status Register 0 */ +#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK (0xFFFFU) +#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT (0U) +#define APBH_CTRL0_TOG_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK) +#define APBH_CTRL0_TOG_RSVD0_MASK (0xFFF0000U) +#define APBH_CTRL0_TOG_RSVD0_SHIFT (16U) +#define APBH_CTRL0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_RSVD0_SHIFT)) & APBH_CTRL0_TOG_RSVD0_MASK) +#define APBH_CTRL0_TOG_APB_BURST_EN_MASK (0x10000000U) +#define APBH_CTRL0_TOG_APB_BURST_EN_SHIFT (28U) +#define APBH_CTRL0_TOG_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_APB_BURST_EN_SHIFT)) & APBH_CTRL0_TOG_APB_BURST_EN_MASK) +#define APBH_CTRL0_TOG_AHB_BURST8_EN_MASK (0x20000000U) +#define APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT (29U) +#define APBH_CTRL0_TOG_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_TOG_AHB_BURST8_EN_MASK) +#define APBH_CTRL0_TOG_CLKGATE_MASK (0x40000000U) +#define APBH_CTRL0_TOG_CLKGATE_SHIFT (30U) +#define APBH_CTRL0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_MASK) +#define APBH_CTRL0_TOG_SFTRST_MASK (0x80000000U) +#define APBH_CTRL0_TOG_SFTRST_SHIFT (31U) +#define APBH_CTRL0_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_SFTRST_SHIFT)) & APBH_CTRL0_TOG_SFTRST_MASK) + +/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */ +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK) + +/*! @name CTRL1_SET - AHB to APBH Bridge Control and Status Register 1 */ +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK) + +/*! @name CTRL1_CLR - AHB to APBH Bridge Control and Status Register 1 */ +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK) + +/*! @name CTRL1_TOG - AHB to APBH Bridge Control and Status Register 1 */ +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK (0x1U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT (0U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK (0x2U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT (1U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK (0x4U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT (2U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK (0x8U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT (3U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK (0x10U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT (4U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK (0x20U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT (5U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK (0x40U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT (6U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK (0x80U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT (7U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK (0x100U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT (8U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK (0x200U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT (9U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK (0x400U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT (10U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK (0x800U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT (11U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK (0x1000U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT (12U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK (0x2000U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT (13U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK (0x4000U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT (14U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK (0x8000U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT (15U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U) +#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U) +#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U) +#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U) +#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U) +#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U) +#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U) +#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U) +#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U) +#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U) +#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U) +#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U) +#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U) +#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U) +#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U) +#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U) +#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK) + +/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */ +#define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK) +#define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U) +#define APBH_CTRL2_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U) +#define APBH_CTRL2_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U) +#define APBH_CTRL2_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U) +#define APBH_CTRL2_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U) +#define APBH_CTRL2_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U) +#define APBH_CTRL2_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U) +#define APBH_CTRL2_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U) +#define APBH_CTRL2_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U) +#define APBH_CTRL2_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U) +#define APBH_CTRL2_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U) +#define APBH_CTRL2_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U) +#define APBH_CTRL2_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U) +#define APBH_CTRL2_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U) +#define APBH_CTRL2_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U) +#define APBH_CTRL2_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK) +#define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U) +#define APBH_CTRL2_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK) + +/*! @name CTRL2_SET - AHB to APBH Bridge Control and Status Register 2 */ +#define APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_SET_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_SET_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_SET_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_SET_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_SET_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_SET_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_SET_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_SET_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_SET_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_SET_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_SET_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_SET_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_SET_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_SET_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_SET_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_SET_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK) +#define APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT (16U) +#define APBH_CTRL2_SET_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT (17U) +#define APBH_CTRL2_SET_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT (18U) +#define APBH_CTRL2_SET_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT (19U) +#define APBH_CTRL2_SET_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT (20U) +#define APBH_CTRL2_SET_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT (21U) +#define APBH_CTRL2_SET_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT (22U) +#define APBH_CTRL2_SET_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT (23U) +#define APBH_CTRL2_SET_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT (24U) +#define APBH_CTRL2_SET_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT (25U) +#define APBH_CTRL2_SET_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT (26U) +#define APBH_CTRL2_SET_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT (27U) +#define APBH_CTRL2_SET_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT (28U) +#define APBH_CTRL2_SET_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT (29U) +#define APBH_CTRL2_SET_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT (30U) +#define APBH_CTRL2_SET_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK) +#define APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT (31U) +#define APBH_CTRL2_SET_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK) + +/*! @name CTRL2_CLR - AHB to APBH Bridge Control and Status Register 2 */ +#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_CLR_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_CLR_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_CLR_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_CLR_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_CLR_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_CLR_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_CLR_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_CLR_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_CLR_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_CLR_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_CLR_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_CLR_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_CLR_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_CLR_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_CLR_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_CLR_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK) +#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT (16U) +#define APBH_CTRL2_CLR_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT (17U) +#define APBH_CTRL2_CLR_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT (18U) +#define APBH_CTRL2_CLR_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT (19U) +#define APBH_CTRL2_CLR_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT (20U) +#define APBH_CTRL2_CLR_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT (21U) +#define APBH_CTRL2_CLR_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT (22U) +#define APBH_CTRL2_CLR_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT (23U) +#define APBH_CTRL2_CLR_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT (24U) +#define APBH_CTRL2_CLR_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT (25U) +#define APBH_CTRL2_CLR_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT (26U) +#define APBH_CTRL2_CLR_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT (27U) +#define APBH_CTRL2_CLR_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT (28U) +#define APBH_CTRL2_CLR_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT (29U) +#define APBH_CTRL2_CLR_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT (30U) +#define APBH_CTRL2_CLR_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK) +#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT (31U) +#define APBH_CTRL2_CLR_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK) + +/*! @name CTRL2_TOG - AHB to APBH Bridge Control and Status Register 2 */ +#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK (0x1U) +#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT (0U) +#define APBH_CTRL2_TOG_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK (0x2U) +#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT (1U) +#define APBH_CTRL2_TOG_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK (0x4U) +#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT (2U) +#define APBH_CTRL2_TOG_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK (0x8U) +#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT (3U) +#define APBH_CTRL2_TOG_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK (0x10U) +#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT (4U) +#define APBH_CTRL2_TOG_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK (0x20U) +#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT (5U) +#define APBH_CTRL2_TOG_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK (0x40U) +#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT (6U) +#define APBH_CTRL2_TOG_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK (0x80U) +#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT (7U) +#define APBH_CTRL2_TOG_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK (0x100U) +#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT (8U) +#define APBH_CTRL2_TOG_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK (0x200U) +#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT (9U) +#define APBH_CTRL2_TOG_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK (0x400U) +#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT (10U) +#define APBH_CTRL2_TOG_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK (0x800U) +#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT (11U) +#define APBH_CTRL2_TOG_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK (0x1000U) +#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT (12U) +#define APBH_CTRL2_TOG_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK (0x2000U) +#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT (13U) +#define APBH_CTRL2_TOG_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK (0x4000U) +#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT (14U) +#define APBH_CTRL2_TOG_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK (0x8000U) +#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT (15U) +#define APBH_CTRL2_TOG_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK) +#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK (0x10000U) +#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT (16U) +#define APBH_CTRL2_TOG_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK (0x20000U) +#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT (17U) +#define APBH_CTRL2_TOG_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK (0x40000U) +#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT (18U) +#define APBH_CTRL2_TOG_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK (0x80000U) +#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT (19U) +#define APBH_CTRL2_TOG_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK (0x100000U) +#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT (20U) +#define APBH_CTRL2_TOG_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK (0x200000U) +#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT (21U) +#define APBH_CTRL2_TOG_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK (0x400000U) +#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT (22U) +#define APBH_CTRL2_TOG_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK (0x800000U) +#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT (23U) +#define APBH_CTRL2_TOG_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK (0x1000000U) +#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT (24U) +#define APBH_CTRL2_TOG_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK (0x2000000U) +#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT (25U) +#define APBH_CTRL2_TOG_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK (0x4000000U) +#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT (26U) +#define APBH_CTRL2_TOG_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK (0x8000000U) +#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT (27U) +#define APBH_CTRL2_TOG_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK (0x10000000U) +#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT (28U) +#define APBH_CTRL2_TOG_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK (0x20000000U) +#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT (29U) +#define APBH_CTRL2_TOG_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK (0x40000000U) +#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT (30U) +#define APBH_CTRL2_TOG_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK) +#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK (0x80000000U) +#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT (31U) +#define APBH_CTRL2_TOG_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK) + +/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */ +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U) +#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U) +#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK) + +/*! @name CHANNEL_CTRL_SET - AHB to APBH Bridge Channel Register */ +#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT (0U) +#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT (16U) +#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK) + +/*! @name CHANNEL_CTRL_CLR - AHB to APBH Bridge Channel Register */ +#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT (0U) +#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT (16U) +#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK) + +/*! @name CHANNEL_CTRL_TOG - AHB to APBH Bridge Channel Register */ +#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK (0xFFFFU) +#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT (0U) +#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK) +#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK (0xFFFF0000U) +#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT (16U) +#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK) + +/*! @name DEVSEL - AHB to APBH DMA Device Assignment Register */ +#define APBH_DEVSEL_CH0_MASK (0x3U) +#define APBH_DEVSEL_CH0_SHIFT (0U) +#define APBH_DEVSEL_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH0_SHIFT)) & APBH_DEVSEL_CH0_MASK) +#define APBH_DEVSEL_CH1_MASK (0xCU) +#define APBH_DEVSEL_CH1_SHIFT (2U) +#define APBH_DEVSEL_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH1_SHIFT)) & APBH_DEVSEL_CH1_MASK) +#define APBH_DEVSEL_CH2_MASK (0x30U) +#define APBH_DEVSEL_CH2_SHIFT (4U) +#define APBH_DEVSEL_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH2_SHIFT)) & APBH_DEVSEL_CH2_MASK) +#define APBH_DEVSEL_CH3_MASK (0xC0U) +#define APBH_DEVSEL_CH3_SHIFT (6U) +#define APBH_DEVSEL_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH3_SHIFT)) & APBH_DEVSEL_CH3_MASK) +#define APBH_DEVSEL_CH4_MASK (0x300U) +#define APBH_DEVSEL_CH4_SHIFT (8U) +#define APBH_DEVSEL_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH4_SHIFT)) & APBH_DEVSEL_CH4_MASK) +#define APBH_DEVSEL_CH5_MASK (0xC00U) +#define APBH_DEVSEL_CH5_SHIFT (10U) +#define APBH_DEVSEL_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH5_SHIFT)) & APBH_DEVSEL_CH5_MASK) +#define APBH_DEVSEL_CH6_MASK (0x3000U) +#define APBH_DEVSEL_CH6_SHIFT (12U) +#define APBH_DEVSEL_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH6_SHIFT)) & APBH_DEVSEL_CH6_MASK) +#define APBH_DEVSEL_CH7_MASK (0xC000U) +#define APBH_DEVSEL_CH7_SHIFT (14U) +#define APBH_DEVSEL_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH7_SHIFT)) & APBH_DEVSEL_CH7_MASK) +#define APBH_DEVSEL_CH8_MASK (0x30000U) +#define APBH_DEVSEL_CH8_SHIFT (16U) +#define APBH_DEVSEL_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH8_SHIFT)) & APBH_DEVSEL_CH8_MASK) +#define APBH_DEVSEL_CH9_MASK (0xC0000U) +#define APBH_DEVSEL_CH9_SHIFT (18U) +#define APBH_DEVSEL_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH9_SHIFT)) & APBH_DEVSEL_CH9_MASK) +#define APBH_DEVSEL_CH10_MASK (0x300000U) +#define APBH_DEVSEL_CH10_SHIFT (20U) +#define APBH_DEVSEL_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH10_SHIFT)) & APBH_DEVSEL_CH10_MASK) +#define APBH_DEVSEL_CH11_MASK (0xC00000U) +#define APBH_DEVSEL_CH11_SHIFT (22U) +#define APBH_DEVSEL_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH11_SHIFT)) & APBH_DEVSEL_CH11_MASK) +#define APBH_DEVSEL_CH12_MASK (0x3000000U) +#define APBH_DEVSEL_CH12_SHIFT (24U) +#define APBH_DEVSEL_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH12_SHIFT)) & APBH_DEVSEL_CH12_MASK) +#define APBH_DEVSEL_CH13_MASK (0xC000000U) +#define APBH_DEVSEL_CH13_SHIFT (26U) +#define APBH_DEVSEL_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH13_SHIFT)) & APBH_DEVSEL_CH13_MASK) +#define APBH_DEVSEL_CH14_MASK (0x30000000U) +#define APBH_DEVSEL_CH14_SHIFT (28U) +#define APBH_DEVSEL_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH14_SHIFT)) & APBH_DEVSEL_CH14_MASK) +#define APBH_DEVSEL_CH15_MASK (0xC0000000U) +#define APBH_DEVSEL_CH15_SHIFT (30U) +#define APBH_DEVSEL_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH15_SHIFT)) & APBH_DEVSEL_CH15_MASK) + +/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */ +#define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U) +#define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U) +#define APBH_DMA_BURST_SIZE_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK) +#define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU) +#define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U) +#define APBH_DMA_BURST_SIZE_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK) +#define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U) +#define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U) +#define APBH_DMA_BURST_SIZE_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK) +#define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U) +#define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U) +#define APBH_DMA_BURST_SIZE_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK) +#define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U) +#define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U) +#define APBH_DMA_BURST_SIZE_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK) +#define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U) +#define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U) +#define APBH_DMA_BURST_SIZE_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK) +#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U) +#define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U) +#define APBH_DMA_BURST_SIZE_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK) +#define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U) +#define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U) +#define APBH_DMA_BURST_SIZE_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK) +#define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U) +#define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U) +#define APBH_DMA_BURST_SIZE_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK) +#define APBH_DMA_BURST_SIZE_CH9_MASK (0xC0000U) +#define APBH_DMA_BURST_SIZE_CH9_SHIFT (18U) +#define APBH_DMA_BURST_SIZE_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH9_SHIFT)) & APBH_DMA_BURST_SIZE_CH9_MASK) +#define APBH_DMA_BURST_SIZE_CH10_MASK (0x300000U) +#define APBH_DMA_BURST_SIZE_CH10_SHIFT (20U) +#define APBH_DMA_BURST_SIZE_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH10_SHIFT)) & APBH_DMA_BURST_SIZE_CH10_MASK) +#define APBH_DMA_BURST_SIZE_CH11_MASK (0xC00000U) +#define APBH_DMA_BURST_SIZE_CH11_SHIFT (22U) +#define APBH_DMA_BURST_SIZE_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH11_SHIFT)) & APBH_DMA_BURST_SIZE_CH11_MASK) +#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3000000U) +#define APBH_DMA_BURST_SIZE_CH12_SHIFT (24U) +#define APBH_DMA_BURST_SIZE_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH12_SHIFT)) & APBH_DMA_BURST_SIZE_CH12_MASK) +#define APBH_DMA_BURST_SIZE_CH13_MASK (0xC000000U) +#define APBH_DMA_BURST_SIZE_CH13_SHIFT (26U) +#define APBH_DMA_BURST_SIZE_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH13_SHIFT)) & APBH_DMA_BURST_SIZE_CH13_MASK) +#define APBH_DMA_BURST_SIZE_CH14_MASK (0x30000000U) +#define APBH_DMA_BURST_SIZE_CH14_SHIFT (28U) +#define APBH_DMA_BURST_SIZE_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH14_SHIFT)) & APBH_DMA_BURST_SIZE_CH14_MASK) +#define APBH_DMA_BURST_SIZE_CH15_MASK (0xC0000000U) +#define APBH_DMA_BURST_SIZE_CH15_SHIFT (30U) +#define APBH_DMA_BURST_SIZE_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH15_SHIFT)) & APBH_DMA_BURST_SIZE_CH15_MASK) + +/*! @name DEBUG - AHB to APBH DMA Debug Register */ +#define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U) +#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U) +#define APBH_DEBUG_GPMI_ONE_FIFO(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK) + +/*! @name CH0_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH0_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH0_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH0_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH0_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH0_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH0_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH0_CMD_COMMAND_MASK (0x3U) +#define APBH_CH0_CMD_COMMAND_SHIFT (0U) +#define APBH_CH0_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_COMMAND_SHIFT)) & APBH_CH0_CMD_COMMAND_MASK) +#define APBH_CH0_CMD_CHAIN_MASK (0x4U) +#define APBH_CH0_CMD_CHAIN_SHIFT (2U) +#define APBH_CH0_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CHAIN_SHIFT)) & APBH_CH0_CMD_CHAIN_MASK) +#define APBH_CH0_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH0_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH0_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_IRQONCMPLT_SHIFT)) & APBH_CH0_CMD_IRQONCMPLT_MASK) +#define APBH_CH0_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH0_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH0_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDLOCK_SHIFT)) & APBH_CH0_CMD_NANDLOCK_MASK) +#define APBH_CH0_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH0_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH0_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH0_CMD_NANDWAIT4READY_MASK) +#define APBH_CH0_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH0_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH0_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_SEMAPHORE_SHIFT)) & APBH_CH0_CMD_SEMAPHORE_MASK) +#define APBH_CH0_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH0_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH0_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH0_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH0_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH0_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH0_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH0_CMD_HALTONTERMINATE_MASK) +#define APBH_CH0_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH0_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH0_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CMDWORDS_SHIFT)) & APBH_CH0_CMD_CMDWORDS_MASK) +#define APBH_CH0_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH0_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH0_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_XFER_COUNT_SHIFT)) & APBH_CH0_CMD_XFER_COUNT_MASK) + +/*! @name CH0_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH0_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH0_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH0_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_BAR_ADDRESS_SHIFT)) & APBH_CH0_BAR_ADDRESS_MASK) + +/*! @name CH0_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH0_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH0_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH0_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH0_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH0_SEMA_PHORE_SHIFT (16U) +#define APBH_CH0_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_PHORE_SHIFT)) & APBH_CH0_SEMA_PHORE_MASK) + +/*! @name CH0_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH0_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH0_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH0_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH0_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH0_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH0_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH0_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RSVD1_SHIFT)) & APBH_CH0_DEBUG1_RSVD1_MASK) +#define APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH0_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH0_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH0_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH0_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH0_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_LOCK_SHIFT)) & APBH_CH0_DEBUG1_LOCK_MASK) +#define APBH_CH0_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH0_DEBUG1_READY_SHIFT (26U) +#define APBH_CH0_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_READY_SHIFT)) & APBH_CH0_DEBUG1_READY_MASK) +#define APBH_CH0_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH0_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH0_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_SENSE_SHIFT)) & APBH_CH0_DEBUG1_SENSE_MASK) +#define APBH_CH0_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH0_DEBUG1_END_SHIFT (28U) +#define APBH_CH0_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_END_SHIFT)) & APBH_CH0_DEBUG1_END_MASK) +#define APBH_CH0_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH0_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH0_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_KICK_SHIFT)) & APBH_CH0_DEBUG1_KICK_MASK) +#define APBH_CH0_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH0_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH0_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_BURST_SHIFT)) & APBH_CH0_DEBUG1_BURST_MASK) +#define APBH_CH0_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH0_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH0_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_REQ_SHIFT)) & APBH_CH0_DEBUG1_REQ_MASK) + +/*! @name CH0_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH0_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH0_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH0_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH0_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH0_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH0_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_APB_BYTES_MASK) + +/*! @name CH1_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH1_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH1_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH1_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH1_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH1_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH1_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH1_CMD_COMMAND_MASK (0x3U) +#define APBH_CH1_CMD_COMMAND_SHIFT (0U) +#define APBH_CH1_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_COMMAND_SHIFT)) & APBH_CH1_CMD_COMMAND_MASK) +#define APBH_CH1_CMD_CHAIN_MASK (0x4U) +#define APBH_CH1_CMD_CHAIN_SHIFT (2U) +#define APBH_CH1_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CHAIN_SHIFT)) & APBH_CH1_CMD_CHAIN_MASK) +#define APBH_CH1_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH1_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH1_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_IRQONCMPLT_SHIFT)) & APBH_CH1_CMD_IRQONCMPLT_MASK) +#define APBH_CH1_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH1_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH1_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDLOCK_SHIFT)) & APBH_CH1_CMD_NANDLOCK_MASK) +#define APBH_CH1_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH1_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH1_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH1_CMD_NANDWAIT4READY_MASK) +#define APBH_CH1_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH1_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH1_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_SEMAPHORE_SHIFT)) & APBH_CH1_CMD_SEMAPHORE_MASK) +#define APBH_CH1_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH1_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH1_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH1_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH1_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH1_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH1_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH1_CMD_HALTONTERMINATE_MASK) +#define APBH_CH1_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH1_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH1_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CMDWORDS_SHIFT)) & APBH_CH1_CMD_CMDWORDS_MASK) +#define APBH_CH1_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH1_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH1_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_XFER_COUNT_SHIFT)) & APBH_CH1_CMD_XFER_COUNT_MASK) + +/*! @name CH1_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH1_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH1_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH1_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_BAR_ADDRESS_SHIFT)) & APBH_CH1_BAR_ADDRESS_MASK) + +/*! @name CH1_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH1_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH1_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH1_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH1_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH1_SEMA_PHORE_SHIFT (16U) +#define APBH_CH1_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_PHORE_SHIFT)) & APBH_CH1_SEMA_PHORE_MASK) + +/*! @name CH1_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH1_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH1_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH1_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH1_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH1_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH1_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH1_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RSVD1_SHIFT)) & APBH_CH1_DEBUG1_RSVD1_MASK) +#define APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH1_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH1_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH1_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH1_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH1_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_LOCK_SHIFT)) & APBH_CH1_DEBUG1_LOCK_MASK) +#define APBH_CH1_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH1_DEBUG1_READY_SHIFT (26U) +#define APBH_CH1_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_READY_SHIFT)) & APBH_CH1_DEBUG1_READY_MASK) +#define APBH_CH1_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH1_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH1_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_SENSE_SHIFT)) & APBH_CH1_DEBUG1_SENSE_MASK) +#define APBH_CH1_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH1_DEBUG1_END_SHIFT (28U) +#define APBH_CH1_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_END_SHIFT)) & APBH_CH1_DEBUG1_END_MASK) +#define APBH_CH1_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH1_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH1_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_KICK_SHIFT)) & APBH_CH1_DEBUG1_KICK_MASK) +#define APBH_CH1_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH1_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH1_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_BURST_SHIFT)) & APBH_CH1_DEBUG1_BURST_MASK) +#define APBH_CH1_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH1_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH1_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_REQ_SHIFT)) & APBH_CH1_DEBUG1_REQ_MASK) + +/*! @name CH1_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH1_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH1_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH1_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH1_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH1_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH1_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_APB_BYTES_MASK) + +/*! @name CH2_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH2_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH2_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH2_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH2_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH2_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH2_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH2_CMD_COMMAND_MASK (0x3U) +#define APBH_CH2_CMD_COMMAND_SHIFT (0U) +#define APBH_CH2_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_COMMAND_SHIFT)) & APBH_CH2_CMD_COMMAND_MASK) +#define APBH_CH2_CMD_CHAIN_MASK (0x4U) +#define APBH_CH2_CMD_CHAIN_SHIFT (2U) +#define APBH_CH2_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CHAIN_SHIFT)) & APBH_CH2_CMD_CHAIN_MASK) +#define APBH_CH2_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH2_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH2_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_IRQONCMPLT_SHIFT)) & APBH_CH2_CMD_IRQONCMPLT_MASK) +#define APBH_CH2_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH2_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH2_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDLOCK_SHIFT)) & APBH_CH2_CMD_NANDLOCK_MASK) +#define APBH_CH2_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH2_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH2_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH2_CMD_NANDWAIT4READY_MASK) +#define APBH_CH2_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH2_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH2_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_SEMAPHORE_SHIFT)) & APBH_CH2_CMD_SEMAPHORE_MASK) +#define APBH_CH2_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH2_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH2_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH2_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH2_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH2_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH2_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH2_CMD_HALTONTERMINATE_MASK) +#define APBH_CH2_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH2_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH2_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CMDWORDS_SHIFT)) & APBH_CH2_CMD_CMDWORDS_MASK) +#define APBH_CH2_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH2_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH2_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_XFER_COUNT_SHIFT)) & APBH_CH2_CMD_XFER_COUNT_MASK) + +/*! @name CH2_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH2_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH2_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH2_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_BAR_ADDRESS_SHIFT)) & APBH_CH2_BAR_ADDRESS_MASK) + +/*! @name CH2_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH2_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH2_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH2_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH2_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH2_SEMA_PHORE_SHIFT (16U) +#define APBH_CH2_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_PHORE_SHIFT)) & APBH_CH2_SEMA_PHORE_MASK) + +/*! @name CH2_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH2_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH2_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH2_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH2_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH2_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH2_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH2_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RSVD1_SHIFT)) & APBH_CH2_DEBUG1_RSVD1_MASK) +#define APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH2_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH2_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH2_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH2_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH2_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_LOCK_SHIFT)) & APBH_CH2_DEBUG1_LOCK_MASK) +#define APBH_CH2_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH2_DEBUG1_READY_SHIFT (26U) +#define APBH_CH2_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_READY_SHIFT)) & APBH_CH2_DEBUG1_READY_MASK) +#define APBH_CH2_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH2_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH2_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_SENSE_SHIFT)) & APBH_CH2_DEBUG1_SENSE_MASK) +#define APBH_CH2_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH2_DEBUG1_END_SHIFT (28U) +#define APBH_CH2_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_END_SHIFT)) & APBH_CH2_DEBUG1_END_MASK) +#define APBH_CH2_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH2_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH2_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_KICK_SHIFT)) & APBH_CH2_DEBUG1_KICK_MASK) +#define APBH_CH2_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH2_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH2_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_BURST_SHIFT)) & APBH_CH2_DEBUG1_BURST_MASK) +#define APBH_CH2_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH2_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH2_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_REQ_SHIFT)) & APBH_CH2_DEBUG1_REQ_MASK) + +/*! @name CH2_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH2_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH2_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH2_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH2_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH2_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH2_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_APB_BYTES_MASK) + +/*! @name CH3_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH3_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH3_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH3_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH3_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH3_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH3_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH3_CMD_COMMAND_MASK (0x3U) +#define APBH_CH3_CMD_COMMAND_SHIFT (0U) +#define APBH_CH3_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_COMMAND_SHIFT)) & APBH_CH3_CMD_COMMAND_MASK) +#define APBH_CH3_CMD_CHAIN_MASK (0x4U) +#define APBH_CH3_CMD_CHAIN_SHIFT (2U) +#define APBH_CH3_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CHAIN_SHIFT)) & APBH_CH3_CMD_CHAIN_MASK) +#define APBH_CH3_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH3_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH3_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_IRQONCMPLT_SHIFT)) & APBH_CH3_CMD_IRQONCMPLT_MASK) +#define APBH_CH3_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH3_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH3_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDLOCK_SHIFT)) & APBH_CH3_CMD_NANDLOCK_MASK) +#define APBH_CH3_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH3_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH3_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH3_CMD_NANDWAIT4READY_MASK) +#define APBH_CH3_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH3_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH3_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_SEMAPHORE_SHIFT)) & APBH_CH3_CMD_SEMAPHORE_MASK) +#define APBH_CH3_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH3_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH3_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH3_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH3_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH3_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH3_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH3_CMD_HALTONTERMINATE_MASK) +#define APBH_CH3_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH3_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH3_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CMDWORDS_SHIFT)) & APBH_CH3_CMD_CMDWORDS_MASK) +#define APBH_CH3_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH3_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH3_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_XFER_COUNT_SHIFT)) & APBH_CH3_CMD_XFER_COUNT_MASK) + +/*! @name CH3_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH3_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH3_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH3_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_BAR_ADDRESS_SHIFT)) & APBH_CH3_BAR_ADDRESS_MASK) + +/*! @name CH3_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH3_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH3_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH3_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH3_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH3_SEMA_PHORE_SHIFT (16U) +#define APBH_CH3_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_PHORE_SHIFT)) & APBH_CH3_SEMA_PHORE_MASK) + +/*! @name CH3_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH3_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH3_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH3_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH3_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH3_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH3_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH3_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RSVD1_SHIFT)) & APBH_CH3_DEBUG1_RSVD1_MASK) +#define APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH3_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH3_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH3_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH3_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH3_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_LOCK_SHIFT)) & APBH_CH3_DEBUG1_LOCK_MASK) +#define APBH_CH3_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH3_DEBUG1_READY_SHIFT (26U) +#define APBH_CH3_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_READY_SHIFT)) & APBH_CH3_DEBUG1_READY_MASK) +#define APBH_CH3_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH3_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH3_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_SENSE_SHIFT)) & APBH_CH3_DEBUG1_SENSE_MASK) +#define APBH_CH3_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH3_DEBUG1_END_SHIFT (28U) +#define APBH_CH3_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_END_SHIFT)) & APBH_CH3_DEBUG1_END_MASK) +#define APBH_CH3_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH3_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH3_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_KICK_SHIFT)) & APBH_CH3_DEBUG1_KICK_MASK) +#define APBH_CH3_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH3_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH3_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_BURST_SHIFT)) & APBH_CH3_DEBUG1_BURST_MASK) +#define APBH_CH3_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH3_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH3_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_REQ_SHIFT)) & APBH_CH3_DEBUG1_REQ_MASK) + +/*! @name CH3_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH3_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH3_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH3_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH3_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH3_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH3_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_APB_BYTES_MASK) + +/*! @name CH4_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH4_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH4_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH4_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH4_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH4_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH4_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH4_CMD_COMMAND_MASK (0x3U) +#define APBH_CH4_CMD_COMMAND_SHIFT (0U) +#define APBH_CH4_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_COMMAND_SHIFT)) & APBH_CH4_CMD_COMMAND_MASK) +#define APBH_CH4_CMD_CHAIN_MASK (0x4U) +#define APBH_CH4_CMD_CHAIN_SHIFT (2U) +#define APBH_CH4_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CHAIN_SHIFT)) & APBH_CH4_CMD_CHAIN_MASK) +#define APBH_CH4_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH4_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH4_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_IRQONCMPLT_SHIFT)) & APBH_CH4_CMD_IRQONCMPLT_MASK) +#define APBH_CH4_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH4_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH4_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDLOCK_SHIFT)) & APBH_CH4_CMD_NANDLOCK_MASK) +#define APBH_CH4_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH4_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH4_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH4_CMD_NANDWAIT4READY_MASK) +#define APBH_CH4_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH4_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH4_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_SEMAPHORE_SHIFT)) & APBH_CH4_CMD_SEMAPHORE_MASK) +#define APBH_CH4_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH4_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH4_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH4_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH4_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH4_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH4_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH4_CMD_HALTONTERMINATE_MASK) +#define APBH_CH4_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH4_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH4_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CMDWORDS_SHIFT)) & APBH_CH4_CMD_CMDWORDS_MASK) +#define APBH_CH4_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH4_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH4_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_XFER_COUNT_SHIFT)) & APBH_CH4_CMD_XFER_COUNT_MASK) + +/*! @name CH4_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH4_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH4_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH4_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_BAR_ADDRESS_SHIFT)) & APBH_CH4_BAR_ADDRESS_MASK) + +/*! @name CH4_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH4_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH4_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH4_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH4_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH4_SEMA_PHORE_SHIFT (16U) +#define APBH_CH4_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_PHORE_SHIFT)) & APBH_CH4_SEMA_PHORE_MASK) + +/*! @name CH4_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH4_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH4_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH4_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH4_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH4_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH4_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH4_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RSVD1_SHIFT)) & APBH_CH4_DEBUG1_RSVD1_MASK) +#define APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH4_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH4_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH4_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH4_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH4_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_LOCK_SHIFT)) & APBH_CH4_DEBUG1_LOCK_MASK) +#define APBH_CH4_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH4_DEBUG1_READY_SHIFT (26U) +#define APBH_CH4_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_READY_SHIFT)) & APBH_CH4_DEBUG1_READY_MASK) +#define APBH_CH4_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH4_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH4_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_SENSE_SHIFT)) & APBH_CH4_DEBUG1_SENSE_MASK) +#define APBH_CH4_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH4_DEBUG1_END_SHIFT (28U) +#define APBH_CH4_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_END_SHIFT)) & APBH_CH4_DEBUG1_END_MASK) +#define APBH_CH4_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH4_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH4_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_KICK_SHIFT)) & APBH_CH4_DEBUG1_KICK_MASK) +#define APBH_CH4_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH4_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH4_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_BURST_SHIFT)) & APBH_CH4_DEBUG1_BURST_MASK) +#define APBH_CH4_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH4_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH4_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_REQ_SHIFT)) & APBH_CH4_DEBUG1_REQ_MASK) + +/*! @name CH4_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH4_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH4_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH4_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH4_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH4_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH4_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_APB_BYTES_MASK) + +/*! @name CH5_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH5_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH5_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH5_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH5_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH5_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH5_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH5_CMD_COMMAND_MASK (0x3U) +#define APBH_CH5_CMD_COMMAND_SHIFT (0U) +#define APBH_CH5_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_COMMAND_SHIFT)) & APBH_CH5_CMD_COMMAND_MASK) +#define APBH_CH5_CMD_CHAIN_MASK (0x4U) +#define APBH_CH5_CMD_CHAIN_SHIFT (2U) +#define APBH_CH5_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CHAIN_SHIFT)) & APBH_CH5_CMD_CHAIN_MASK) +#define APBH_CH5_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH5_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH5_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_IRQONCMPLT_SHIFT)) & APBH_CH5_CMD_IRQONCMPLT_MASK) +#define APBH_CH5_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH5_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH5_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK) +#define APBH_CH5_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH5_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH5_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH5_CMD_NANDWAIT4READY_MASK) +#define APBH_CH5_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH5_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH5_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_SEMAPHORE_SHIFT)) & APBH_CH5_CMD_SEMAPHORE_MASK) +#define APBH_CH5_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH5_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH5_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH5_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH5_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH5_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH5_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH5_CMD_HALTONTERMINATE_MASK) +#define APBH_CH5_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH5_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH5_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CMDWORDS_SHIFT)) & APBH_CH5_CMD_CMDWORDS_MASK) +#define APBH_CH5_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH5_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH5_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_XFER_COUNT_SHIFT)) & APBH_CH5_CMD_XFER_COUNT_MASK) + +/*! @name CH5_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH5_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH5_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH5_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_BAR_ADDRESS_SHIFT)) & APBH_CH5_BAR_ADDRESS_MASK) + +/*! @name CH5_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH5_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH5_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH5_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH5_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH5_SEMA_PHORE_SHIFT (16U) +#define APBH_CH5_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_PHORE_SHIFT)) & APBH_CH5_SEMA_PHORE_MASK) + +/*! @name CH5_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH5_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH5_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH5_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH5_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH5_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH5_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH5_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RSVD1_SHIFT)) & APBH_CH5_DEBUG1_RSVD1_MASK) +#define APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH5_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH5_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH5_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH5_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH5_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_LOCK_SHIFT)) & APBH_CH5_DEBUG1_LOCK_MASK) +#define APBH_CH5_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH5_DEBUG1_READY_SHIFT (26U) +#define APBH_CH5_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_READY_SHIFT)) & APBH_CH5_DEBUG1_READY_MASK) +#define APBH_CH5_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH5_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH5_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_SENSE_SHIFT)) & APBH_CH5_DEBUG1_SENSE_MASK) +#define APBH_CH5_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH5_DEBUG1_END_SHIFT (28U) +#define APBH_CH5_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_END_SHIFT)) & APBH_CH5_DEBUG1_END_MASK) +#define APBH_CH5_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH5_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH5_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_KICK_SHIFT)) & APBH_CH5_DEBUG1_KICK_MASK) +#define APBH_CH5_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH5_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH5_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_BURST_SHIFT)) & APBH_CH5_DEBUG1_BURST_MASK) +#define APBH_CH5_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH5_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH5_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_REQ_SHIFT)) & APBH_CH5_DEBUG1_REQ_MASK) + +/*! @name CH5_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH5_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH5_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH5_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH5_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH5_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH5_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_APB_BYTES_MASK) + +/*! @name CH6_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH6_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH6_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH6_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH6_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH6_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH6_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH6_CMD_COMMAND_MASK (0x3U) +#define APBH_CH6_CMD_COMMAND_SHIFT (0U) +#define APBH_CH6_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_COMMAND_SHIFT)) & APBH_CH6_CMD_COMMAND_MASK) +#define APBH_CH6_CMD_CHAIN_MASK (0x4U) +#define APBH_CH6_CMD_CHAIN_SHIFT (2U) +#define APBH_CH6_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CHAIN_SHIFT)) & APBH_CH6_CMD_CHAIN_MASK) +#define APBH_CH6_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH6_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH6_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_IRQONCMPLT_SHIFT)) & APBH_CH6_CMD_IRQONCMPLT_MASK) +#define APBH_CH6_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH6_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH6_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDLOCK_SHIFT)) & APBH_CH6_CMD_NANDLOCK_MASK) +#define APBH_CH6_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH6_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH6_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH6_CMD_NANDWAIT4READY_MASK) +#define APBH_CH6_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH6_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH6_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_SEMAPHORE_SHIFT)) & APBH_CH6_CMD_SEMAPHORE_MASK) +#define APBH_CH6_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH6_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH6_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH6_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH6_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH6_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH6_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH6_CMD_HALTONTERMINATE_MASK) +#define APBH_CH6_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH6_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH6_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CMDWORDS_SHIFT)) & APBH_CH6_CMD_CMDWORDS_MASK) +#define APBH_CH6_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH6_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH6_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_XFER_COUNT_SHIFT)) & APBH_CH6_CMD_XFER_COUNT_MASK) + +/*! @name CH6_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH6_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH6_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH6_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_BAR_ADDRESS_SHIFT)) & APBH_CH6_BAR_ADDRESS_MASK) + +/*! @name CH6_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH6_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH6_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH6_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH6_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH6_SEMA_PHORE_SHIFT (16U) +#define APBH_CH6_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_PHORE_SHIFT)) & APBH_CH6_SEMA_PHORE_MASK) + +/*! @name CH6_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH6_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH6_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH6_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH6_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH6_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH6_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH6_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RSVD1_SHIFT)) & APBH_CH6_DEBUG1_RSVD1_MASK) +#define APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH6_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH6_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH6_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH6_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH6_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_LOCK_SHIFT)) & APBH_CH6_DEBUG1_LOCK_MASK) +#define APBH_CH6_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH6_DEBUG1_READY_SHIFT (26U) +#define APBH_CH6_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_READY_SHIFT)) & APBH_CH6_DEBUG1_READY_MASK) +#define APBH_CH6_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH6_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH6_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_SENSE_SHIFT)) & APBH_CH6_DEBUG1_SENSE_MASK) +#define APBH_CH6_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH6_DEBUG1_END_SHIFT (28U) +#define APBH_CH6_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_END_SHIFT)) & APBH_CH6_DEBUG1_END_MASK) +#define APBH_CH6_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH6_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH6_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_KICK_SHIFT)) & APBH_CH6_DEBUG1_KICK_MASK) +#define APBH_CH6_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH6_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH6_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_BURST_SHIFT)) & APBH_CH6_DEBUG1_BURST_MASK) +#define APBH_CH6_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH6_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH6_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_REQ_SHIFT)) & APBH_CH6_DEBUG1_REQ_MASK) + +/*! @name CH6_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH6_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH6_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH6_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH6_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH6_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH6_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_APB_BYTES_MASK) + +/*! @name CH7_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH7_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH7_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH7_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH7_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH7_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH7_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH7_CMD_COMMAND_MASK (0x3U) +#define APBH_CH7_CMD_COMMAND_SHIFT (0U) +#define APBH_CH7_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_COMMAND_SHIFT)) & APBH_CH7_CMD_COMMAND_MASK) +#define APBH_CH7_CMD_CHAIN_MASK (0x4U) +#define APBH_CH7_CMD_CHAIN_SHIFT (2U) +#define APBH_CH7_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CHAIN_SHIFT)) & APBH_CH7_CMD_CHAIN_MASK) +#define APBH_CH7_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH7_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH7_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_IRQONCMPLT_SHIFT)) & APBH_CH7_CMD_IRQONCMPLT_MASK) +#define APBH_CH7_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH7_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH7_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_NANDLOCK_SHIFT)) & APBH_CH7_CMD_NANDLOCK_MASK) +#define APBH_CH7_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH7_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH7_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH7_CMD_NANDWAIT4READY_MASK) +#define APBH_CH7_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH7_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH7_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_SEMAPHORE_SHIFT)) & APBH_CH7_CMD_SEMAPHORE_MASK) +#define APBH_CH7_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH7_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH7_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH7_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH7_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH7_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH7_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH7_CMD_HALTONTERMINATE_MASK) +#define APBH_CH7_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH7_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH7_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CMDWORDS_SHIFT)) & APBH_CH7_CMD_CMDWORDS_MASK) +#define APBH_CH7_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH7_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH7_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_XFER_COUNT_SHIFT)) & APBH_CH7_CMD_XFER_COUNT_MASK) + +/*! @name CH7_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH7_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH7_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH7_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_BAR_ADDRESS_SHIFT)) & APBH_CH7_BAR_ADDRESS_MASK) + +/*! @name CH7_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH7_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH7_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH7_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH7_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH7_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH7_SEMA_PHORE_SHIFT (16U) +#define APBH_CH7_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_SEMA_PHORE_SHIFT)) & APBH_CH7_SEMA_PHORE_MASK) + +/*! @name CH7_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH7_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH7_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH7_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH7_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH7_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH7_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH7_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RSVD1_SHIFT)) & APBH_CH7_DEBUG1_RSVD1_MASK) +#define APBH_CH7_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH7_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH7_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH7_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH7_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH7_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH7_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH7_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH7_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH7_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH7_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH7_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH7_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH7_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH7_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH7_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH7_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_LOCK_SHIFT)) & APBH_CH7_DEBUG1_LOCK_MASK) +#define APBH_CH7_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH7_DEBUG1_READY_SHIFT (26U) +#define APBH_CH7_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_READY_SHIFT)) & APBH_CH7_DEBUG1_READY_MASK) +#define APBH_CH7_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH7_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH7_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_SENSE_SHIFT)) & APBH_CH7_DEBUG1_SENSE_MASK) +#define APBH_CH7_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH7_DEBUG1_END_SHIFT (28U) +#define APBH_CH7_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_END_SHIFT)) & APBH_CH7_DEBUG1_END_MASK) +#define APBH_CH7_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH7_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH7_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_KICK_SHIFT)) & APBH_CH7_DEBUG1_KICK_MASK) +#define APBH_CH7_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH7_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH7_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_BURST_SHIFT)) & APBH_CH7_DEBUG1_BURST_MASK) +#define APBH_CH7_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH7_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH7_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG1_REQ_SHIFT)) & APBH_CH7_DEBUG1_REQ_MASK) + +/*! @name CH7_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH7_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH7_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH7_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH7_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH7_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH7_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH7_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH7_DEBUG2_APB_BYTES_MASK) + +/*! @name CH8_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH8_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH8_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH8_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH8_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH8_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH8_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH8_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH8_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH8_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH8_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH8_CMD_COMMAND_MASK (0x3U) +#define APBH_CH8_CMD_COMMAND_SHIFT (0U) +#define APBH_CH8_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_COMMAND_SHIFT)) & APBH_CH8_CMD_COMMAND_MASK) +#define APBH_CH8_CMD_CHAIN_MASK (0x4U) +#define APBH_CH8_CMD_CHAIN_SHIFT (2U) +#define APBH_CH8_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_CHAIN_SHIFT)) & APBH_CH8_CMD_CHAIN_MASK) +#define APBH_CH8_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH8_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH8_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_IRQONCMPLT_SHIFT)) & APBH_CH8_CMD_IRQONCMPLT_MASK) +#define APBH_CH8_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH8_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH8_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_NANDLOCK_SHIFT)) & APBH_CH8_CMD_NANDLOCK_MASK) +#define APBH_CH8_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH8_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH8_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH8_CMD_NANDWAIT4READY_MASK) +#define APBH_CH8_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH8_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH8_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_SEMAPHORE_SHIFT)) & APBH_CH8_CMD_SEMAPHORE_MASK) +#define APBH_CH8_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH8_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH8_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH8_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH8_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH8_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH8_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH8_CMD_HALTONTERMINATE_MASK) +#define APBH_CH8_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH8_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH8_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_CMDWORDS_SHIFT)) & APBH_CH8_CMD_CMDWORDS_MASK) +#define APBH_CH8_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH8_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH8_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_CMD_XFER_COUNT_SHIFT)) & APBH_CH8_CMD_XFER_COUNT_MASK) + +/*! @name CH8_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH8_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH8_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH8_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_BAR_ADDRESS_SHIFT)) & APBH_CH8_BAR_ADDRESS_MASK) + +/*! @name CH8_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH8_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH8_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH8_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH8_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH8_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH8_SEMA_PHORE_SHIFT (16U) +#define APBH_CH8_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_SEMA_PHORE_SHIFT)) & APBH_CH8_SEMA_PHORE_MASK) + +/*! @name CH8_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH8_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH8_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH8_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH8_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH8_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH8_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH8_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RSVD1_SHIFT)) & APBH_CH8_DEBUG1_RSVD1_MASK) +#define APBH_CH8_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH8_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH8_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH8_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH8_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH8_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH8_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH8_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH8_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH8_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH8_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH8_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH8_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH8_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH8_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH8_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH8_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_LOCK_SHIFT)) & APBH_CH8_DEBUG1_LOCK_MASK) +#define APBH_CH8_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH8_DEBUG1_READY_SHIFT (26U) +#define APBH_CH8_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_READY_SHIFT)) & APBH_CH8_DEBUG1_READY_MASK) +#define APBH_CH8_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH8_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH8_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_SENSE_SHIFT)) & APBH_CH8_DEBUG1_SENSE_MASK) +#define APBH_CH8_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH8_DEBUG1_END_SHIFT (28U) +#define APBH_CH8_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_END_SHIFT)) & APBH_CH8_DEBUG1_END_MASK) +#define APBH_CH8_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH8_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH8_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_KICK_SHIFT)) & APBH_CH8_DEBUG1_KICK_MASK) +#define APBH_CH8_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH8_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH8_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_BURST_SHIFT)) & APBH_CH8_DEBUG1_BURST_MASK) +#define APBH_CH8_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH8_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH8_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG1_REQ_SHIFT)) & APBH_CH8_DEBUG1_REQ_MASK) + +/*! @name CH8_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH8_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH8_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH8_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH8_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH8_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH8_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH8_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH8_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH8_DEBUG2_APB_BYTES_MASK) + +/*! @name CH9_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH9_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH9_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH9_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH9_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH9_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH9_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH9_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH9_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH9_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH9_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH9_CMD_COMMAND_MASK (0x3U) +#define APBH_CH9_CMD_COMMAND_SHIFT (0U) +#define APBH_CH9_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_COMMAND_SHIFT)) & APBH_CH9_CMD_COMMAND_MASK) +#define APBH_CH9_CMD_CHAIN_MASK (0x4U) +#define APBH_CH9_CMD_CHAIN_SHIFT (2U) +#define APBH_CH9_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_CHAIN_SHIFT)) & APBH_CH9_CMD_CHAIN_MASK) +#define APBH_CH9_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH9_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH9_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_IRQONCMPLT_SHIFT)) & APBH_CH9_CMD_IRQONCMPLT_MASK) +#define APBH_CH9_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH9_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH9_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_NANDLOCK_SHIFT)) & APBH_CH9_CMD_NANDLOCK_MASK) +#define APBH_CH9_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH9_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH9_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH9_CMD_NANDWAIT4READY_MASK) +#define APBH_CH9_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH9_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH9_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_SEMAPHORE_SHIFT)) & APBH_CH9_CMD_SEMAPHORE_MASK) +#define APBH_CH9_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH9_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH9_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH9_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH9_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH9_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH9_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH9_CMD_HALTONTERMINATE_MASK) +#define APBH_CH9_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH9_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH9_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_CMDWORDS_SHIFT)) & APBH_CH9_CMD_CMDWORDS_MASK) +#define APBH_CH9_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH9_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH9_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_CMD_XFER_COUNT_SHIFT)) & APBH_CH9_CMD_XFER_COUNT_MASK) + +/*! @name CH9_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH9_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH9_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH9_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_BAR_ADDRESS_SHIFT)) & APBH_CH9_BAR_ADDRESS_MASK) + +/*! @name CH9_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH9_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH9_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH9_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH9_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH9_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH9_SEMA_PHORE_SHIFT (16U) +#define APBH_CH9_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_SEMA_PHORE_SHIFT)) & APBH_CH9_SEMA_PHORE_MASK) + +/*! @name CH9_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH9_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH9_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH9_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH9_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH9_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH9_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH9_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RSVD1_SHIFT)) & APBH_CH9_DEBUG1_RSVD1_MASK) +#define APBH_CH9_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH9_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH9_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH9_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH9_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH9_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH9_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH9_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH9_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH9_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH9_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH9_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH9_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH9_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH9_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH9_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH9_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_LOCK_SHIFT)) & APBH_CH9_DEBUG1_LOCK_MASK) +#define APBH_CH9_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH9_DEBUG1_READY_SHIFT (26U) +#define APBH_CH9_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_READY_SHIFT)) & APBH_CH9_DEBUG1_READY_MASK) +#define APBH_CH9_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH9_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH9_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_SENSE_SHIFT)) & APBH_CH9_DEBUG1_SENSE_MASK) +#define APBH_CH9_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH9_DEBUG1_END_SHIFT (28U) +#define APBH_CH9_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_END_SHIFT)) & APBH_CH9_DEBUG1_END_MASK) +#define APBH_CH9_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH9_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH9_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_KICK_SHIFT)) & APBH_CH9_DEBUG1_KICK_MASK) +#define APBH_CH9_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH9_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH9_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_BURST_SHIFT)) & APBH_CH9_DEBUG1_BURST_MASK) +#define APBH_CH9_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH9_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH9_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG1_REQ_SHIFT)) & APBH_CH9_DEBUG1_REQ_MASK) + +/*! @name CH9_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH9_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH9_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH9_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH9_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH9_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH9_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH9_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH9_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH9_DEBUG2_APB_BYTES_MASK) + +/*! @name CH10_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH10_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH10_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH10_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH10_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH10_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH10_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH10_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH10_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH10_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH10_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH10_CMD_COMMAND_MASK (0x3U) +#define APBH_CH10_CMD_COMMAND_SHIFT (0U) +#define APBH_CH10_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_COMMAND_SHIFT)) & APBH_CH10_CMD_COMMAND_MASK) +#define APBH_CH10_CMD_CHAIN_MASK (0x4U) +#define APBH_CH10_CMD_CHAIN_SHIFT (2U) +#define APBH_CH10_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_CHAIN_SHIFT)) & APBH_CH10_CMD_CHAIN_MASK) +#define APBH_CH10_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH10_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH10_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_IRQONCMPLT_SHIFT)) & APBH_CH10_CMD_IRQONCMPLT_MASK) +#define APBH_CH10_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH10_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH10_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_NANDLOCK_SHIFT)) & APBH_CH10_CMD_NANDLOCK_MASK) +#define APBH_CH10_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH10_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH10_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH10_CMD_NANDWAIT4READY_MASK) +#define APBH_CH10_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH10_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH10_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_SEMAPHORE_SHIFT)) & APBH_CH10_CMD_SEMAPHORE_MASK) +#define APBH_CH10_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH10_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH10_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH10_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH10_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH10_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH10_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH10_CMD_HALTONTERMINATE_MASK) +#define APBH_CH10_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH10_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH10_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_CMDWORDS_SHIFT)) & APBH_CH10_CMD_CMDWORDS_MASK) +#define APBH_CH10_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH10_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH10_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_CMD_XFER_COUNT_SHIFT)) & APBH_CH10_CMD_XFER_COUNT_MASK) + +/*! @name CH10_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH10_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH10_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH10_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_BAR_ADDRESS_SHIFT)) & APBH_CH10_BAR_ADDRESS_MASK) + +/*! @name CH10_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH10_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH10_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH10_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH10_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH10_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH10_SEMA_PHORE_SHIFT (16U) +#define APBH_CH10_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_SEMA_PHORE_SHIFT)) & APBH_CH10_SEMA_PHORE_MASK) + +/*! @name CH10_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH10_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH10_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH10_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH10_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH10_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH10_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH10_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RSVD1_SHIFT)) & APBH_CH10_DEBUG1_RSVD1_MASK) +#define APBH_CH10_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH10_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH10_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH10_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH10_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH10_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH10_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH10_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH10_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH10_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH10_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH10_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH10_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH10_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH10_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH10_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH10_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_LOCK_SHIFT)) & APBH_CH10_DEBUG1_LOCK_MASK) +#define APBH_CH10_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH10_DEBUG1_READY_SHIFT (26U) +#define APBH_CH10_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_READY_SHIFT)) & APBH_CH10_DEBUG1_READY_MASK) +#define APBH_CH10_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH10_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH10_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_SENSE_SHIFT)) & APBH_CH10_DEBUG1_SENSE_MASK) +#define APBH_CH10_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH10_DEBUG1_END_SHIFT (28U) +#define APBH_CH10_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_END_SHIFT)) & APBH_CH10_DEBUG1_END_MASK) +#define APBH_CH10_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH10_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH10_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_KICK_SHIFT)) & APBH_CH10_DEBUG1_KICK_MASK) +#define APBH_CH10_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH10_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH10_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_BURST_SHIFT)) & APBH_CH10_DEBUG1_BURST_MASK) +#define APBH_CH10_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH10_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH10_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG1_REQ_SHIFT)) & APBH_CH10_DEBUG1_REQ_MASK) + +/*! @name CH10_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH10_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH10_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH10_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH10_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH10_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH10_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH10_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH10_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH10_DEBUG2_APB_BYTES_MASK) + +/*! @name CH11_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH11_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH11_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH11_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH11_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH11_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH11_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH11_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH11_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH11_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH11_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH11_CMD_COMMAND_MASK (0x3U) +#define APBH_CH11_CMD_COMMAND_SHIFT (0U) +#define APBH_CH11_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_COMMAND_SHIFT)) & APBH_CH11_CMD_COMMAND_MASK) +#define APBH_CH11_CMD_CHAIN_MASK (0x4U) +#define APBH_CH11_CMD_CHAIN_SHIFT (2U) +#define APBH_CH11_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_CHAIN_SHIFT)) & APBH_CH11_CMD_CHAIN_MASK) +#define APBH_CH11_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH11_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH11_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_IRQONCMPLT_SHIFT)) & APBH_CH11_CMD_IRQONCMPLT_MASK) +#define APBH_CH11_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH11_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH11_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_NANDLOCK_SHIFT)) & APBH_CH11_CMD_NANDLOCK_MASK) +#define APBH_CH11_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH11_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH11_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH11_CMD_NANDWAIT4READY_MASK) +#define APBH_CH11_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH11_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH11_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_SEMAPHORE_SHIFT)) & APBH_CH11_CMD_SEMAPHORE_MASK) +#define APBH_CH11_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH11_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH11_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH11_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH11_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH11_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH11_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH11_CMD_HALTONTERMINATE_MASK) +#define APBH_CH11_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH11_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH11_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_CMDWORDS_SHIFT)) & APBH_CH11_CMD_CMDWORDS_MASK) +#define APBH_CH11_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH11_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH11_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_CMD_XFER_COUNT_SHIFT)) & APBH_CH11_CMD_XFER_COUNT_MASK) + +/*! @name CH11_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH11_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH11_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH11_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_BAR_ADDRESS_SHIFT)) & APBH_CH11_BAR_ADDRESS_MASK) + +/*! @name CH11_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH11_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH11_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH11_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH11_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH11_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH11_SEMA_PHORE_SHIFT (16U) +#define APBH_CH11_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_SEMA_PHORE_SHIFT)) & APBH_CH11_SEMA_PHORE_MASK) + +/*! @name CH11_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH11_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH11_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH11_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH11_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH11_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH11_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH11_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RSVD1_SHIFT)) & APBH_CH11_DEBUG1_RSVD1_MASK) +#define APBH_CH11_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH11_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH11_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH11_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH11_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH11_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH11_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH11_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH11_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH11_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH11_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH11_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH11_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH11_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH11_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH11_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH11_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_LOCK_SHIFT)) & APBH_CH11_DEBUG1_LOCK_MASK) +#define APBH_CH11_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH11_DEBUG1_READY_SHIFT (26U) +#define APBH_CH11_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_READY_SHIFT)) & APBH_CH11_DEBUG1_READY_MASK) +#define APBH_CH11_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH11_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH11_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_SENSE_SHIFT)) & APBH_CH11_DEBUG1_SENSE_MASK) +#define APBH_CH11_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH11_DEBUG1_END_SHIFT (28U) +#define APBH_CH11_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_END_SHIFT)) & APBH_CH11_DEBUG1_END_MASK) +#define APBH_CH11_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH11_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH11_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_KICK_SHIFT)) & APBH_CH11_DEBUG1_KICK_MASK) +#define APBH_CH11_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH11_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH11_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_BURST_SHIFT)) & APBH_CH11_DEBUG1_BURST_MASK) +#define APBH_CH11_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH11_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH11_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG1_REQ_SHIFT)) & APBH_CH11_DEBUG1_REQ_MASK) + +/*! @name CH11_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH11_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH11_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH11_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH11_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH11_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH11_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH11_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH11_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH11_DEBUG2_APB_BYTES_MASK) + +/*! @name CH12_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH12_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH12_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH12_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH12_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH12_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH12_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH12_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH12_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH12_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH12_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH12_CMD_COMMAND_MASK (0x3U) +#define APBH_CH12_CMD_COMMAND_SHIFT (0U) +#define APBH_CH12_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_COMMAND_SHIFT)) & APBH_CH12_CMD_COMMAND_MASK) +#define APBH_CH12_CMD_CHAIN_MASK (0x4U) +#define APBH_CH12_CMD_CHAIN_SHIFT (2U) +#define APBH_CH12_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_CHAIN_SHIFT)) & APBH_CH12_CMD_CHAIN_MASK) +#define APBH_CH12_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH12_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH12_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_IRQONCMPLT_SHIFT)) & APBH_CH12_CMD_IRQONCMPLT_MASK) +#define APBH_CH12_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH12_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH12_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_NANDLOCK_SHIFT)) & APBH_CH12_CMD_NANDLOCK_MASK) +#define APBH_CH12_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH12_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH12_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH12_CMD_NANDWAIT4READY_MASK) +#define APBH_CH12_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH12_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH12_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_SEMAPHORE_SHIFT)) & APBH_CH12_CMD_SEMAPHORE_MASK) +#define APBH_CH12_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH12_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH12_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH12_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH12_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH12_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH12_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH12_CMD_HALTONTERMINATE_MASK) +#define APBH_CH12_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH12_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH12_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_CMDWORDS_SHIFT)) & APBH_CH12_CMD_CMDWORDS_MASK) +#define APBH_CH12_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH12_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH12_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_CMD_XFER_COUNT_SHIFT)) & APBH_CH12_CMD_XFER_COUNT_MASK) + +/*! @name CH12_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH12_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH12_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH12_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_BAR_ADDRESS_SHIFT)) & APBH_CH12_BAR_ADDRESS_MASK) + +/*! @name CH12_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH12_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH12_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH12_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH12_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH12_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH12_SEMA_PHORE_SHIFT (16U) +#define APBH_CH12_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_SEMA_PHORE_SHIFT)) & APBH_CH12_SEMA_PHORE_MASK) + +/*! @name CH12_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH12_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH12_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH12_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH12_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH12_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH12_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH12_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RSVD1_SHIFT)) & APBH_CH12_DEBUG1_RSVD1_MASK) +#define APBH_CH12_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH12_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH12_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH12_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH12_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH12_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH12_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH12_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH12_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH12_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH12_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH12_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH12_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH12_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH12_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH12_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH12_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_LOCK_SHIFT)) & APBH_CH12_DEBUG1_LOCK_MASK) +#define APBH_CH12_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH12_DEBUG1_READY_SHIFT (26U) +#define APBH_CH12_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_READY_SHIFT)) & APBH_CH12_DEBUG1_READY_MASK) +#define APBH_CH12_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH12_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH12_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_SENSE_SHIFT)) & APBH_CH12_DEBUG1_SENSE_MASK) +#define APBH_CH12_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH12_DEBUG1_END_SHIFT (28U) +#define APBH_CH12_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_END_SHIFT)) & APBH_CH12_DEBUG1_END_MASK) +#define APBH_CH12_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH12_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH12_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_KICK_SHIFT)) & APBH_CH12_DEBUG1_KICK_MASK) +#define APBH_CH12_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH12_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH12_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_BURST_SHIFT)) & APBH_CH12_DEBUG1_BURST_MASK) +#define APBH_CH12_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH12_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH12_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG1_REQ_SHIFT)) & APBH_CH12_DEBUG1_REQ_MASK) + +/*! @name CH12_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH12_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH12_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH12_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH12_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH12_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH12_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH12_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH12_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH12_DEBUG2_APB_BYTES_MASK) + +/*! @name CH13_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH13_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH13_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH13_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH13_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH13_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH13_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH13_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH13_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH13_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH13_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH13_CMD_COMMAND_MASK (0x3U) +#define APBH_CH13_CMD_COMMAND_SHIFT (0U) +#define APBH_CH13_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_COMMAND_SHIFT)) & APBH_CH13_CMD_COMMAND_MASK) +#define APBH_CH13_CMD_CHAIN_MASK (0x4U) +#define APBH_CH13_CMD_CHAIN_SHIFT (2U) +#define APBH_CH13_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_CHAIN_SHIFT)) & APBH_CH13_CMD_CHAIN_MASK) +#define APBH_CH13_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH13_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH13_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_IRQONCMPLT_SHIFT)) & APBH_CH13_CMD_IRQONCMPLT_MASK) +#define APBH_CH13_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH13_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH13_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_NANDLOCK_SHIFT)) & APBH_CH13_CMD_NANDLOCK_MASK) +#define APBH_CH13_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH13_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH13_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH13_CMD_NANDWAIT4READY_MASK) +#define APBH_CH13_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH13_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH13_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_SEMAPHORE_SHIFT)) & APBH_CH13_CMD_SEMAPHORE_MASK) +#define APBH_CH13_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH13_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH13_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH13_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH13_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH13_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH13_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH13_CMD_HALTONTERMINATE_MASK) +#define APBH_CH13_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH13_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH13_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_CMDWORDS_SHIFT)) & APBH_CH13_CMD_CMDWORDS_MASK) +#define APBH_CH13_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH13_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH13_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_CMD_XFER_COUNT_SHIFT)) & APBH_CH13_CMD_XFER_COUNT_MASK) + +/*! @name CH13_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH13_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH13_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH13_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_BAR_ADDRESS_SHIFT)) & APBH_CH13_BAR_ADDRESS_MASK) + +/*! @name CH13_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH13_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH13_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH13_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH13_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH13_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH13_SEMA_PHORE_SHIFT (16U) +#define APBH_CH13_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_SEMA_PHORE_SHIFT)) & APBH_CH13_SEMA_PHORE_MASK) + +/*! @name CH13_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH13_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH13_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH13_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH13_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH13_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH13_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH13_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RSVD1_SHIFT)) & APBH_CH13_DEBUG1_RSVD1_MASK) +#define APBH_CH13_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH13_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH13_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH13_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH13_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH13_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH13_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH13_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH13_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH13_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH13_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH13_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH13_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH13_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH13_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH13_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH13_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_LOCK_SHIFT)) & APBH_CH13_DEBUG1_LOCK_MASK) +#define APBH_CH13_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH13_DEBUG1_READY_SHIFT (26U) +#define APBH_CH13_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_READY_SHIFT)) & APBH_CH13_DEBUG1_READY_MASK) +#define APBH_CH13_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH13_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH13_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_SENSE_SHIFT)) & APBH_CH13_DEBUG1_SENSE_MASK) +#define APBH_CH13_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH13_DEBUG1_END_SHIFT (28U) +#define APBH_CH13_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_END_SHIFT)) & APBH_CH13_DEBUG1_END_MASK) +#define APBH_CH13_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH13_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH13_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_KICK_SHIFT)) & APBH_CH13_DEBUG1_KICK_MASK) +#define APBH_CH13_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH13_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH13_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_BURST_SHIFT)) & APBH_CH13_DEBUG1_BURST_MASK) +#define APBH_CH13_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH13_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH13_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG1_REQ_SHIFT)) & APBH_CH13_DEBUG1_REQ_MASK) + +/*! @name CH13_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH13_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH13_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH13_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH13_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH13_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH13_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH13_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH13_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH13_DEBUG2_APB_BYTES_MASK) + +/*! @name CH14_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH14_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH14_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH14_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH14_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH14_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH14_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH14_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH14_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH14_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH14_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH14_CMD_COMMAND_MASK (0x3U) +#define APBH_CH14_CMD_COMMAND_SHIFT (0U) +#define APBH_CH14_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_COMMAND_SHIFT)) & APBH_CH14_CMD_COMMAND_MASK) +#define APBH_CH14_CMD_CHAIN_MASK (0x4U) +#define APBH_CH14_CMD_CHAIN_SHIFT (2U) +#define APBH_CH14_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_CHAIN_SHIFT)) & APBH_CH14_CMD_CHAIN_MASK) +#define APBH_CH14_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH14_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH14_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_IRQONCMPLT_SHIFT)) & APBH_CH14_CMD_IRQONCMPLT_MASK) +#define APBH_CH14_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH14_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH14_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_NANDLOCK_SHIFT)) & APBH_CH14_CMD_NANDLOCK_MASK) +#define APBH_CH14_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH14_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH14_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH14_CMD_NANDWAIT4READY_MASK) +#define APBH_CH14_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH14_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH14_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_SEMAPHORE_SHIFT)) & APBH_CH14_CMD_SEMAPHORE_MASK) +#define APBH_CH14_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH14_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH14_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH14_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH14_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH14_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH14_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH14_CMD_HALTONTERMINATE_MASK) +#define APBH_CH14_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH14_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH14_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_CMDWORDS_SHIFT)) & APBH_CH14_CMD_CMDWORDS_MASK) +#define APBH_CH14_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH14_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH14_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_CMD_XFER_COUNT_SHIFT)) & APBH_CH14_CMD_XFER_COUNT_MASK) + +/*! @name CH14_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH14_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH14_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH14_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_BAR_ADDRESS_SHIFT)) & APBH_CH14_BAR_ADDRESS_MASK) + +/*! @name CH14_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH14_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH14_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH14_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH14_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH14_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH14_SEMA_PHORE_SHIFT (16U) +#define APBH_CH14_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_SEMA_PHORE_SHIFT)) & APBH_CH14_SEMA_PHORE_MASK) + +/*! @name CH14_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH14_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH14_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH14_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH14_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH14_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH14_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH14_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RSVD1_SHIFT)) & APBH_CH14_DEBUG1_RSVD1_MASK) +#define APBH_CH14_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH14_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH14_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH14_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH14_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH14_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH14_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH14_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH14_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH14_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH14_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH14_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH14_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH14_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH14_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH14_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH14_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_LOCK_SHIFT)) & APBH_CH14_DEBUG1_LOCK_MASK) +#define APBH_CH14_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH14_DEBUG1_READY_SHIFT (26U) +#define APBH_CH14_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_READY_SHIFT)) & APBH_CH14_DEBUG1_READY_MASK) +#define APBH_CH14_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH14_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH14_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_SENSE_SHIFT)) & APBH_CH14_DEBUG1_SENSE_MASK) +#define APBH_CH14_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH14_DEBUG1_END_SHIFT (28U) +#define APBH_CH14_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_END_SHIFT)) & APBH_CH14_DEBUG1_END_MASK) +#define APBH_CH14_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH14_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH14_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_KICK_SHIFT)) & APBH_CH14_DEBUG1_KICK_MASK) +#define APBH_CH14_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH14_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH14_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_BURST_SHIFT)) & APBH_CH14_DEBUG1_BURST_MASK) +#define APBH_CH14_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH14_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH14_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG1_REQ_SHIFT)) & APBH_CH14_DEBUG1_REQ_MASK) + +/*! @name CH14_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH14_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH14_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH14_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH14_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH14_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH14_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH14_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH14_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH14_DEBUG2_APB_BYTES_MASK) + +/*! @name CH15_CURCMDAR - APBH DMA Channel n Current Command Address Register */ +#define APBH_CH15_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH15_CURCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH15_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH15_CURCMDAR_CMD_ADDR_MASK) + +/*! @name CH15_NXTCMDAR - APBH DMA Channel n Next Command Address Register */ +#define APBH_CH15_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU) +#define APBH_CH15_NXTCMDAR_CMD_ADDR_SHIFT (0U) +#define APBH_CH15_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH15_NXTCMDAR_CMD_ADDR_MASK) + +/*! @name CH15_CMD - APBH DMA Channel n Command Register */ +#define APBH_CH15_CMD_COMMAND_MASK (0x3U) +#define APBH_CH15_CMD_COMMAND_SHIFT (0U) +#define APBH_CH15_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_COMMAND_SHIFT)) & APBH_CH15_CMD_COMMAND_MASK) +#define APBH_CH15_CMD_CHAIN_MASK (0x4U) +#define APBH_CH15_CMD_CHAIN_SHIFT (2U) +#define APBH_CH15_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_CHAIN_SHIFT)) & APBH_CH15_CMD_CHAIN_MASK) +#define APBH_CH15_CMD_IRQONCMPLT_MASK (0x8U) +#define APBH_CH15_CMD_IRQONCMPLT_SHIFT (3U) +#define APBH_CH15_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_IRQONCMPLT_SHIFT)) & APBH_CH15_CMD_IRQONCMPLT_MASK) +#define APBH_CH15_CMD_NANDLOCK_MASK (0x10U) +#define APBH_CH15_CMD_NANDLOCK_SHIFT (4U) +#define APBH_CH15_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_NANDLOCK_SHIFT)) & APBH_CH15_CMD_NANDLOCK_MASK) +#define APBH_CH15_CMD_NANDWAIT4READY_MASK (0x20U) +#define APBH_CH15_CMD_NANDWAIT4READY_SHIFT (5U) +#define APBH_CH15_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH15_CMD_NANDWAIT4READY_MASK) +#define APBH_CH15_CMD_SEMAPHORE_MASK (0x40U) +#define APBH_CH15_CMD_SEMAPHORE_SHIFT (6U) +#define APBH_CH15_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_SEMAPHORE_SHIFT)) & APBH_CH15_CMD_SEMAPHORE_MASK) +#define APBH_CH15_CMD_WAIT4ENDCMD_MASK (0x80U) +#define APBH_CH15_CMD_WAIT4ENDCMD_SHIFT (7U) +#define APBH_CH15_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH15_CMD_WAIT4ENDCMD_MASK) +#define APBH_CH15_CMD_HALTONTERMINATE_MASK (0x100U) +#define APBH_CH15_CMD_HALTONTERMINATE_SHIFT (8U) +#define APBH_CH15_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH15_CMD_HALTONTERMINATE_MASK) +#define APBH_CH15_CMD_CMDWORDS_MASK (0xF000U) +#define APBH_CH15_CMD_CMDWORDS_SHIFT (12U) +#define APBH_CH15_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_CMDWORDS_SHIFT)) & APBH_CH15_CMD_CMDWORDS_MASK) +#define APBH_CH15_CMD_XFER_COUNT_MASK (0xFFFF0000U) +#define APBH_CH15_CMD_XFER_COUNT_SHIFT (16U) +#define APBH_CH15_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_CMD_XFER_COUNT_SHIFT)) & APBH_CH15_CMD_XFER_COUNT_MASK) + +/*! @name CH15_BAR - APBH DMA Channel n Buffer Address Register */ +#define APBH_CH15_BAR_ADDRESS_MASK (0xFFFFFFFFU) +#define APBH_CH15_BAR_ADDRESS_SHIFT (0U) +#define APBH_CH15_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_BAR_ADDRESS_SHIFT)) & APBH_CH15_BAR_ADDRESS_MASK) + +/*! @name CH15_SEMA - APBH DMA Channel n Semaphore Register */ +#define APBH_CH15_SEMA_INCREMENT_SEMA_MASK (0xFFU) +#define APBH_CH15_SEMA_INCREMENT_SEMA_SHIFT (0U) +#define APBH_CH15_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH15_SEMA_INCREMENT_SEMA_MASK) +#define APBH_CH15_SEMA_PHORE_MASK (0xFF0000U) +#define APBH_CH15_SEMA_PHORE_SHIFT (16U) +#define APBH_CH15_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_SEMA_PHORE_SHIFT)) & APBH_CH15_SEMA_PHORE_MASK) + +/*! @name CH15_DEBUG1 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH15_DEBUG1_STATEMACHINE_MASK (0x1FU) +#define APBH_CH15_DEBUG1_STATEMACHINE_SHIFT (0U) +#define APBH_CH15_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH15_DEBUG1_STATEMACHINE_MASK) +#define APBH_CH15_DEBUG1_RSVD1_MASK (0xFFFE0U) +#define APBH_CH15_DEBUG1_RSVD1_SHIFT (5U) +#define APBH_CH15_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RSVD1_SHIFT)) & APBH_CH15_DEBUG1_RSVD1_MASK) +#define APBH_CH15_DEBUG1_WR_FIFO_FULL_MASK (0x100000U) +#define APBH_CH15_DEBUG1_WR_FIFO_FULL_SHIFT (20U) +#define APBH_CH15_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH15_DEBUG1_WR_FIFO_FULL_MASK) +#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U) +#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U) +#define APBH_CH15_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH15_DEBUG1_WR_FIFO_EMPTY_MASK) +#define APBH_CH15_DEBUG1_RD_FIFO_FULL_MASK (0x400000U) +#define APBH_CH15_DEBUG1_RD_FIFO_FULL_SHIFT (22U) +#define APBH_CH15_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH15_DEBUG1_RD_FIFO_FULL_MASK) +#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U) +#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U) +#define APBH_CH15_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH15_DEBUG1_RD_FIFO_EMPTY_MASK) +#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U) +#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U) +#define APBH_CH15_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH15_DEBUG1_NEXTCMDADDRVALID_MASK) +#define APBH_CH15_DEBUG1_LOCK_MASK (0x2000000U) +#define APBH_CH15_DEBUG1_LOCK_SHIFT (25U) +#define APBH_CH15_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_LOCK_SHIFT)) & APBH_CH15_DEBUG1_LOCK_MASK) +#define APBH_CH15_DEBUG1_READY_MASK (0x4000000U) +#define APBH_CH15_DEBUG1_READY_SHIFT (26U) +#define APBH_CH15_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_READY_SHIFT)) & APBH_CH15_DEBUG1_READY_MASK) +#define APBH_CH15_DEBUG1_SENSE_MASK (0x8000000U) +#define APBH_CH15_DEBUG1_SENSE_SHIFT (27U) +#define APBH_CH15_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_SENSE_SHIFT)) & APBH_CH15_DEBUG1_SENSE_MASK) +#define APBH_CH15_DEBUG1_END_MASK (0x10000000U) +#define APBH_CH15_DEBUG1_END_SHIFT (28U) +#define APBH_CH15_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_END_SHIFT)) & APBH_CH15_DEBUG1_END_MASK) +#define APBH_CH15_DEBUG1_KICK_MASK (0x20000000U) +#define APBH_CH15_DEBUG1_KICK_SHIFT (29U) +#define APBH_CH15_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_KICK_SHIFT)) & APBH_CH15_DEBUG1_KICK_MASK) +#define APBH_CH15_DEBUG1_BURST_MASK (0x40000000U) +#define APBH_CH15_DEBUG1_BURST_SHIFT (30U) +#define APBH_CH15_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_BURST_SHIFT)) & APBH_CH15_DEBUG1_BURST_MASK) +#define APBH_CH15_DEBUG1_REQ_MASK (0x80000000U) +#define APBH_CH15_DEBUG1_REQ_SHIFT (31U) +#define APBH_CH15_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG1_REQ_SHIFT)) & APBH_CH15_DEBUG1_REQ_MASK) + +/*! @name CH15_DEBUG2 - AHB to APBH DMA Channel n Debug Information */ +#define APBH_CH15_DEBUG2_AHB_BYTES_MASK (0xFFFFU) +#define APBH_CH15_DEBUG2_AHB_BYTES_SHIFT (0U) +#define APBH_CH15_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH15_DEBUG2_AHB_BYTES_MASK) +#define APBH_CH15_DEBUG2_APB_BYTES_MASK (0xFFFF0000U) +#define APBH_CH15_DEBUG2_APB_BYTES_SHIFT (16U) +#define APBH_CH15_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH15_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH15_DEBUG2_APB_BYTES_MASK) + +/*! @name VERSION - APBH Bridge Version Register */ +#define APBH_VERSION_STEP_MASK (0xFFFFU) +#define APBH_VERSION_STEP_SHIFT (0U) +#define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK) +#define APBH_VERSION_MINOR_MASK (0xFF0000U) +#define APBH_VERSION_MINOR_SHIFT (16U) +#define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK) +#define APBH_VERSION_MAJOR_MASK (0xFF000000U) +#define APBH_VERSION_MAJOR_SHIFT (24U) +#define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK) + + +/*! + * @} + */ /* end of group APBH_Register_Masks */ + + +/* APBH - Peripheral instance base addresses */ +/** Peripheral APBH base address */ +#define APBH_BASE (0x1804000u) +/** Peripheral APBH base pointer */ +#define APBH ((APBH_Type *)APBH_BASE) +/** Array initializer of APBH peripheral base addresses */ +#define APBH_BASE_ADDRS { APBH_BASE } +/** Array initializer of APBH peripheral base pointers */ +#define APBH_BASE_PTRS { APBH } +/** Interrupt vectors for the APBH peripheral type */ +#define APBH_IRQS { APBH_IRQn } + +/*! + * @} + */ /* end of group APBH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ASRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer + * @{ + */ + +/** ASRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t ASRCTR; /**< ASRC Control Register, offset: 0x0 */ + __IO uint32_t ASRIER; /**< ASRC Interrupt Enable Register, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ASRCNCR; /**< ASRC Channel Number Configuration Register, offset: 0xC */ + __IO uint32_t ASRCFG; /**< ASRC Filter Configuration Status Register, offset: 0x10 */ + __IO uint32_t ASRCSR; /**< ASRC Clock Source Register, offset: 0x14 */ + __IO uint32_t ASRCDR1; /**< ASRC Clock Divider Register 1, offset: 0x18 */ + __IO uint32_t ASRCDR2; /**< ASRC Clock Divider Register 2, offset: 0x1C */ + __I uint32_t ASRSTR; /**< ASRC Status Register, offset: 0x20 */ + uint8_t RESERVED_1[28]; + __IO uint32_t ASRPMn[5]; /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */ + __IO uint32_t ASRTFR1; /**< ASRC ASRC Task Queue FIFO Register 1, offset: 0x54 */ + uint8_t RESERVED_2[4]; + __IO uint32_t ASRCCR; /**< ASRC Channel Counter Register, offset: 0x5C */ + __IO uint32_t ASRDIA; /**< ASRC Data Input Register for Pair x, offset: 0x60 */ + __I uint32_t ASRDOA; /**< ASRC Data Output Register for Pair x, offset: 0x64 */ + __IO uint32_t ASRDIB; /**< ASRC Data Input Register for Pair x, offset: 0x68 */ + __I uint32_t ASRDOB; /**< ASRC Data Output Register for Pair x, offset: 0x6C */ + __IO uint32_t ASRDIC; /**< ASRC Data Input Register for Pair x, offset: 0x70 */ + __I uint32_t ASRDOC; /**< ASRC Data Output Register for Pair x, offset: 0x74 */ + uint8_t RESERVED_3[8]; + __IO uint32_t ASRIDRHA; /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */ + __IO uint32_t ASRIDRLA; /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */ + __IO uint32_t ASRIDRHB; /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */ + __IO uint32_t ASRIDRLB; /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */ + __IO uint32_t ASRIDRHC; /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */ + __IO uint32_t ASRIDRLC; /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */ + __IO uint32_t ASR76K; /**< ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98 */ + __IO uint32_t ASR56K; /**< ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C */ + __IO uint32_t ASRMCRA; /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */ + __I uint32_t ASRFSTA; /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */ + __IO uint32_t ASRMCRB; /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */ + __I uint32_t ASRFSTB; /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */ + __IO uint32_t ASRMCRC; /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */ + __I uint32_t ASRFSTC; /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */ + uint8_t RESERVED_4[8]; + __IO uint32_t ASRMCR1[3]; /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */ +} ASRC_Type; + +/* ---------------------------------------------------------------------------- + -- ASRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASRC_Register_Masks ASRC Register Masks + * @{ + */ + +/*! @name ASRCTR - ASRC Control Register */ +#define ASRC_ASRCTR_ASRCEN_MASK (0x1U) +#define ASRC_ASRCTR_ASRCEN_SHIFT (0U) +#define ASRC_ASRCTR_ASRCEN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK) +#define ASRC_ASRCTR_ASREA_MASK (0x2U) +#define ASRC_ASRCTR_ASREA_SHIFT (1U) +#define ASRC_ASRCTR_ASREA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK) +#define ASRC_ASRCTR_ASREB_MASK (0x4U) +#define ASRC_ASRCTR_ASREB_SHIFT (2U) +#define ASRC_ASRCTR_ASREB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK) +#define ASRC_ASRCTR_ASREC_MASK (0x8U) +#define ASRC_ASRCTR_ASREC_SHIFT (3U) +#define ASRC_ASRCTR_ASREC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK) +#define ASRC_ASRCTR_SRST_MASK (0x10U) +#define ASRC_ASRCTR_SRST_SHIFT (4U) +#define ASRC_ASRCTR_SRST(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK) +#define ASRC_ASRCTR_IDRA_MASK (0x2000U) +#define ASRC_ASRCTR_IDRA_SHIFT (13U) +#define ASRC_ASRCTR_IDRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK) +#define ASRC_ASRCTR_USRA_MASK (0x4000U) +#define ASRC_ASRCTR_USRA_SHIFT (14U) +#define ASRC_ASRCTR_USRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK) +#define ASRC_ASRCTR_IDRB_MASK (0x8000U) +#define ASRC_ASRCTR_IDRB_SHIFT (15U) +#define ASRC_ASRCTR_IDRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK) +#define ASRC_ASRCTR_USRB_MASK (0x10000U) +#define ASRC_ASRCTR_USRB_SHIFT (16U) +#define ASRC_ASRCTR_USRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK) +#define ASRC_ASRCTR_IDRC_MASK (0x20000U) +#define ASRC_ASRCTR_IDRC_SHIFT (17U) +#define ASRC_ASRCTR_IDRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK) +#define ASRC_ASRCTR_USRC_MASK (0x40000U) +#define ASRC_ASRCTR_USRC_SHIFT (18U) +#define ASRC_ASRCTR_USRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK) +#define ASRC_ASRCTR_ATSA_MASK (0x100000U) +#define ASRC_ASRCTR_ATSA_SHIFT (20U) +#define ASRC_ASRCTR_ATSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK) +#define ASRC_ASRCTR_ATSB_MASK (0x200000U) +#define ASRC_ASRCTR_ATSB_SHIFT (21U) +#define ASRC_ASRCTR_ATSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK) +#define ASRC_ASRCTR_ATSC_MASK (0x400000U) +#define ASRC_ASRCTR_ATSC_SHIFT (22U) +#define ASRC_ASRCTR_ATSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK) + +/*! @name ASRIER - ASRC Interrupt Enable Register */ +#define ASRC_ASRIER_ADIEA_MASK (0x1U) +#define ASRC_ASRIER_ADIEA_SHIFT (0U) +#define ASRC_ASRIER_ADIEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK) +#define ASRC_ASRIER_ADIEB_MASK (0x2U) +#define ASRC_ASRIER_ADIEB_SHIFT (1U) +#define ASRC_ASRIER_ADIEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK) +#define ASRC_ASRIER_ADIEC_MASK (0x4U) +#define ASRC_ASRIER_ADIEC_SHIFT (2U) +#define ASRC_ASRIER_ADIEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK) +#define ASRC_ASRIER_ADOEA_MASK (0x8U) +#define ASRC_ASRIER_ADOEA_SHIFT (3U) +#define ASRC_ASRIER_ADOEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK) +#define ASRC_ASRIER_ADOEB_MASK (0x10U) +#define ASRC_ASRIER_ADOEB_SHIFT (4U) +#define ASRC_ASRIER_ADOEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK) +#define ASRC_ASRIER_ADOEC_MASK (0x20U) +#define ASRC_ASRIER_ADOEC_SHIFT (5U) +#define ASRC_ASRIER_ADOEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK) +#define ASRC_ASRIER_AOLIE_MASK (0x40U) +#define ASRC_ASRIER_AOLIE_SHIFT (6U) +#define ASRC_ASRIER_AOLIE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK) +#define ASRC_ASRIER_AFPWE_MASK (0x80U) +#define ASRC_ASRIER_AFPWE_SHIFT (7U) +#define ASRC_ASRIER_AFPWE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK) + +/*! @name ASRCNCR - ASRC Channel Number Configuration Register */ +#define ASRC_ASRCNCR_ANCA_MASK (0xFU) +#define ASRC_ASRCNCR_ANCA_SHIFT (0U) +#define ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK) +#define ASRC_ASRCNCR_ANCB_MASK (0xF0U) +#define ASRC_ASRCNCR_ANCB_SHIFT (4U) +#define ASRC_ASRCNCR_ANCB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK) +#define ASRC_ASRCNCR_ANCC_MASK (0xF00U) +#define ASRC_ASRCNCR_ANCC_SHIFT (8U) +#define ASRC_ASRCNCR_ANCC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK) + +/*! @name ASRCFG - ASRC Filter Configuration Status Register */ +#define ASRC_ASRCFG_PREMODA_MASK (0xC0U) +#define ASRC_ASRCFG_PREMODA_SHIFT (6U) +#define ASRC_ASRCFG_PREMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK) +#define ASRC_ASRCFG_POSTMODA_MASK (0x300U) +#define ASRC_ASRCFG_POSTMODA_SHIFT (8U) +#define ASRC_ASRCFG_POSTMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK) +#define ASRC_ASRCFG_PREMODB_MASK (0xC00U) +#define ASRC_ASRCFG_PREMODB_SHIFT (10U) +#define ASRC_ASRCFG_PREMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK) +#define ASRC_ASRCFG_POSTMODB_MASK (0x3000U) +#define ASRC_ASRCFG_POSTMODB_SHIFT (12U) +#define ASRC_ASRCFG_POSTMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK) +#define ASRC_ASRCFG_PREMODC_MASK (0xC000U) +#define ASRC_ASRCFG_PREMODC_SHIFT (14U) +#define ASRC_ASRCFG_PREMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK) +#define ASRC_ASRCFG_POSTMODC_MASK (0x30000U) +#define ASRC_ASRCFG_POSTMODC_SHIFT (16U) +#define ASRC_ASRCFG_POSTMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK) +#define ASRC_ASRCFG_NDPRA_MASK (0x40000U) +#define ASRC_ASRCFG_NDPRA_SHIFT (18U) +#define ASRC_ASRCFG_NDPRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK) +#define ASRC_ASRCFG_NDPRB_MASK (0x80000U) +#define ASRC_ASRCFG_NDPRB_SHIFT (19U) +#define ASRC_ASRCFG_NDPRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK) +#define ASRC_ASRCFG_NDPRC_MASK (0x100000U) +#define ASRC_ASRCFG_NDPRC_SHIFT (20U) +#define ASRC_ASRCFG_NDPRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK) +#define ASRC_ASRCFG_INIRQA_MASK (0x200000U) +#define ASRC_ASRCFG_INIRQA_SHIFT (21U) +#define ASRC_ASRCFG_INIRQA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK) +#define ASRC_ASRCFG_INIRQB_MASK (0x400000U) +#define ASRC_ASRCFG_INIRQB_SHIFT (22U) +#define ASRC_ASRCFG_INIRQB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK) +#define ASRC_ASRCFG_INIRQC_MASK (0x800000U) +#define ASRC_ASRCFG_INIRQC_SHIFT (23U) +#define ASRC_ASRCFG_INIRQC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK) + +/*! @name ASRCSR - ASRC Clock Source Register */ +#define ASRC_ASRCSR_AICSA_MASK (0xFU) +#define ASRC_ASRCSR_AICSA_SHIFT (0U) +#define ASRC_ASRCSR_AICSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK) +#define ASRC_ASRCSR_AICSB_MASK (0xF0U) +#define ASRC_ASRCSR_AICSB_SHIFT (4U) +#define ASRC_ASRCSR_AICSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK) +#define ASRC_ASRCSR_AICSC_MASK (0xF00U) +#define ASRC_ASRCSR_AICSC_SHIFT (8U) +#define ASRC_ASRCSR_AICSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK) +#define ASRC_ASRCSR_AOCSA_MASK (0xF000U) +#define ASRC_ASRCSR_AOCSA_SHIFT (12U) +#define ASRC_ASRCSR_AOCSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK) +#define ASRC_ASRCSR_AOCSB_MASK (0xF0000U) +#define ASRC_ASRCSR_AOCSB_SHIFT (16U) +#define ASRC_ASRCSR_AOCSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK) +#define ASRC_ASRCSR_AOCSC_MASK (0xF00000U) +#define ASRC_ASRCSR_AOCSC_SHIFT (20U) +#define ASRC_ASRCSR_AOCSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK) + +/*! @name ASRCDR1 - ASRC Clock Divider Register 1 */ +#define ASRC_ASRCDR1_AICPA_MASK (0x7U) +#define ASRC_ASRCDR1_AICPA_SHIFT (0U) +#define ASRC_ASRCDR1_AICPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK) +#define ASRC_ASRCDR1_AICDA_MASK (0x38U) +#define ASRC_ASRCDR1_AICDA_SHIFT (3U) +#define ASRC_ASRCDR1_AICDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK) +#define ASRC_ASRCDR1_AICPB_MASK (0x1C0U) +#define ASRC_ASRCDR1_AICPB_SHIFT (6U) +#define ASRC_ASRCDR1_AICPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK) +#define ASRC_ASRCDR1_AICDB_MASK (0xE00U) +#define ASRC_ASRCDR1_AICDB_SHIFT (9U) +#define ASRC_ASRCDR1_AICDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK) +#define ASRC_ASRCDR1_AOCPA_MASK (0x7000U) +#define ASRC_ASRCDR1_AOCPA_SHIFT (12U) +#define ASRC_ASRCDR1_AOCPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK) +#define ASRC_ASRCDR1_AOCDA_MASK (0x38000U) +#define ASRC_ASRCDR1_AOCDA_SHIFT (15U) +#define ASRC_ASRCDR1_AOCDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK) +#define ASRC_ASRCDR1_AOCPB_MASK (0x1C0000U) +#define ASRC_ASRCDR1_AOCPB_SHIFT (18U) +#define ASRC_ASRCDR1_AOCPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK) +#define ASRC_ASRCDR1_AOCDB_MASK (0xE00000U) +#define ASRC_ASRCDR1_AOCDB_SHIFT (21U) +#define ASRC_ASRCDR1_AOCDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK) + +/*! @name ASRCDR2 - ASRC Clock Divider Register 2 */ +#define ASRC_ASRCDR2_AICPC_MASK (0x7U) +#define ASRC_ASRCDR2_AICPC_SHIFT (0U) +#define ASRC_ASRCDR2_AICPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK) +#define ASRC_ASRCDR2_AICDC_MASK (0x38U) +#define ASRC_ASRCDR2_AICDC_SHIFT (3U) +#define ASRC_ASRCDR2_AICDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK) +#define ASRC_ASRCDR2_AOCPC_MASK (0x1C0U) +#define ASRC_ASRCDR2_AOCPC_SHIFT (6U) +#define ASRC_ASRCDR2_AOCPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK) +#define ASRC_ASRCDR2_AOCDC_MASK (0xE00U) +#define ASRC_ASRCDR2_AOCDC_SHIFT (9U) +#define ASRC_ASRCDR2_AOCDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK) + +/*! @name ASRSTR - ASRC Status Register */ +#define ASRC_ASRSTR_AIDEA_MASK (0x1U) +#define ASRC_ASRSTR_AIDEA_SHIFT (0U) +#define ASRC_ASRSTR_AIDEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK) +#define ASRC_ASRSTR_AIDEB_MASK (0x2U) +#define ASRC_ASRSTR_AIDEB_SHIFT (1U) +#define ASRC_ASRSTR_AIDEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK) +#define ASRC_ASRSTR_AIDEC_MASK (0x4U) +#define ASRC_ASRSTR_AIDEC_SHIFT (2U) +#define ASRC_ASRSTR_AIDEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK) +#define ASRC_ASRSTR_AODFA_MASK (0x8U) +#define ASRC_ASRSTR_AODFA_SHIFT (3U) +#define ASRC_ASRSTR_AODFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK) +#define ASRC_ASRSTR_AODFB_MASK (0x10U) +#define ASRC_ASRSTR_AODFB_SHIFT (4U) +#define ASRC_ASRSTR_AODFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK) +#define ASRC_ASRSTR_AODFC_MASK (0x20U) +#define ASRC_ASRSTR_AODFC_SHIFT (5U) +#define ASRC_ASRSTR_AODFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK) +#define ASRC_ASRSTR_AOLE_MASK (0x40U) +#define ASRC_ASRSTR_AOLE_SHIFT (6U) +#define ASRC_ASRSTR_AOLE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK) +#define ASRC_ASRSTR_FPWT_MASK (0x80U) +#define ASRC_ASRSTR_FPWT_SHIFT (7U) +#define ASRC_ASRSTR_FPWT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK) +#define ASRC_ASRSTR_AIDUA_MASK (0x100U) +#define ASRC_ASRSTR_AIDUA_SHIFT (8U) +#define ASRC_ASRSTR_AIDUA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK) +#define ASRC_ASRSTR_AIDUB_MASK (0x200U) +#define ASRC_ASRSTR_AIDUB_SHIFT (9U) +#define ASRC_ASRSTR_AIDUB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK) +#define ASRC_ASRSTR_AIDUC_MASK (0x400U) +#define ASRC_ASRSTR_AIDUC_SHIFT (10U) +#define ASRC_ASRSTR_AIDUC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK) +#define ASRC_ASRSTR_AODOA_MASK (0x800U) +#define ASRC_ASRSTR_AODOA_SHIFT (11U) +#define ASRC_ASRSTR_AODOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK) +#define ASRC_ASRSTR_AODOB_MASK (0x1000U) +#define ASRC_ASRSTR_AODOB_SHIFT (12U) +#define ASRC_ASRSTR_AODOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK) +#define ASRC_ASRSTR_AODOC_MASK (0x2000U) +#define ASRC_ASRSTR_AODOC_SHIFT (13U) +#define ASRC_ASRSTR_AODOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK) +#define ASRC_ASRSTR_AIOLA_MASK (0x4000U) +#define ASRC_ASRSTR_AIOLA_SHIFT (14U) +#define ASRC_ASRSTR_AIOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK) +#define ASRC_ASRSTR_AIOLB_MASK (0x8000U) +#define ASRC_ASRSTR_AIOLB_SHIFT (15U) +#define ASRC_ASRSTR_AIOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK) +#define ASRC_ASRSTR_AIOLC_MASK (0x10000U) +#define ASRC_ASRSTR_AIOLC_SHIFT (16U) +#define ASRC_ASRSTR_AIOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK) +#define ASRC_ASRSTR_AOOLA_MASK (0x20000U) +#define ASRC_ASRSTR_AOOLA_SHIFT (17U) +#define ASRC_ASRSTR_AOOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK) +#define ASRC_ASRSTR_AOOLB_MASK (0x40000U) +#define ASRC_ASRSTR_AOOLB_SHIFT (18U) +#define ASRC_ASRSTR_AOOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK) +#define ASRC_ASRSTR_AOOLC_MASK (0x80000U) +#define ASRC_ASRSTR_AOOLC_SHIFT (19U) +#define ASRC_ASRSTR_AOOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK) +#define ASRC_ASRSTR_ATQOL_MASK (0x100000U) +#define ASRC_ASRSTR_ATQOL_SHIFT (20U) +#define ASRC_ASRSTR_ATQOL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK) +#define ASRC_ASRSTR_DSLCNT_MASK (0x200000U) +#define ASRC_ASRSTR_DSLCNT_SHIFT (21U) +#define ASRC_ASRSTR_DSLCNT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK) + +/*! @name ASRPMn - ASRC Parameter Register n */ +#define ASRC_ASRPMn_PARAMETER_VALUE_MASK (0xFFFFFFU) +#define ASRC_ASRPMn_PARAMETER_VALUE_SHIFT (0U) +#define ASRC_ASRPMn_PARAMETER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPMn_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPMn_PARAMETER_VALUE_MASK) + +/* The count of ASRC_ASRPMn */ +#define ASRC_ASRPMn_COUNT (5U) + +/*! @name ASRTFR1 - ASRC ASRC Task Queue FIFO Register 1 */ +#define ASRC_ASRTFR1_TF_BASE_MASK (0x1FC0U) +#define ASRC_ASRTFR1_TF_BASE_SHIFT (6U) +#define ASRC_ASRTFR1_TF_BASE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK) +#define ASRC_ASRTFR1_TF_FILL_MASK (0xFE000U) +#define ASRC_ASRTFR1_TF_FILL_SHIFT (13U) +#define ASRC_ASRTFR1_TF_FILL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK) + +/*! @name ASRCCR - ASRC Channel Counter Register */ +#define ASRC_ASRCCR_ACIA_MASK (0xFU) +#define ASRC_ASRCCR_ACIA_SHIFT (0U) +#define ASRC_ASRCCR_ACIA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK) +#define ASRC_ASRCCR_ACIB_MASK (0xF0U) +#define ASRC_ASRCCR_ACIB_SHIFT (4U) +#define ASRC_ASRCCR_ACIB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK) +#define ASRC_ASRCCR_ACIC_MASK (0xF00U) +#define ASRC_ASRCCR_ACIC_SHIFT (8U) +#define ASRC_ASRCCR_ACIC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK) +#define ASRC_ASRCCR_ACOA_MASK (0xF000U) +#define ASRC_ASRCCR_ACOA_SHIFT (12U) +#define ASRC_ASRCCR_ACOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK) +#define ASRC_ASRCCR_ACOB_MASK (0xF0000U) +#define ASRC_ASRCCR_ACOB_SHIFT (16U) +#define ASRC_ASRCCR_ACOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK) +#define ASRC_ASRCCR_ACOC_MASK (0xF00000U) +#define ASRC_ASRCCR_ACOC_SHIFT (20U) +#define ASRC_ASRCCR_ACOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK) + +/*! @name ASRDIA - ASRC Data Input Register for Pair x */ +#define ASRC_ASRDIA_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDIA_DATA_SHIFT (0U) +#define ASRC_ASRDIA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK) + +/*! @name ASRDOA - ASRC Data Output Register for Pair x */ +#define ASRC_ASRDOA_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDOA_DATA_SHIFT (0U) +#define ASRC_ASRDOA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK) + +/*! @name ASRDIB - ASRC Data Input Register for Pair x */ +#define ASRC_ASRDIB_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDIB_DATA_SHIFT (0U) +#define ASRC_ASRDIB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK) + +/*! @name ASRDOB - ASRC Data Output Register for Pair x */ +#define ASRC_ASRDOB_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDOB_DATA_SHIFT (0U) +#define ASRC_ASRDOB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK) + +/*! @name ASRDIC - ASRC Data Input Register for Pair x */ +#define ASRC_ASRDIC_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDIC_DATA_SHIFT (0U) +#define ASRC_ASRDIC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK) + +/*! @name ASRDOC - ASRC Data Output Register for Pair x */ +#define ASRC_ASRDOC_DATA_MASK (0xFFFFFFU) +#define ASRC_ASRDOC_DATA_SHIFT (0U) +#define ASRC_ASRDOC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK) + +/*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */ +#define ASRC_ASRIDRHA_IDRATIOA_H_MASK (0xFFU) +#define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT (0U) +#define ASRC_ASRIDRHA_IDRATIOA_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK) + +/*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */ +#define ASRC_ASRIDRLA_IDRATIOA_L_MASK (0xFFFFFFU) +#define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT (0U) +#define ASRC_ASRIDRLA_IDRATIOA_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK) + +/*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */ +#define ASRC_ASRIDRHB_IDRATIOB_H_MASK (0xFFU) +#define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT (0U) +#define ASRC_ASRIDRHB_IDRATIOB_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK) + +/*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */ +#define ASRC_ASRIDRLB_IDRATIOB_L_MASK (0xFFFFFFU) +#define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT (0U) +#define ASRC_ASRIDRLB_IDRATIOB_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK) + +/*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */ +#define ASRC_ASRIDRHC_IDRATIOC_H_MASK (0xFFU) +#define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT (0U) +#define ASRC_ASRIDRHC_IDRATIOC_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK) + +/*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */ +#define ASRC_ASRIDRLC_IDRATIOC_L_MASK (0xFFFFFFU) +#define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT (0U) +#define ASRC_ASRIDRLC_IDRATIOC_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK) + +/*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */ +#define ASRC_ASR76K_ASR76K_MASK (0x1FFFFU) +#define ASRC_ASR76K_ASR76K_SHIFT (0U) +#define ASRC_ASR76K_ASR76K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK) + +/*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */ +#define ASRC_ASR56K_ASR56K_MASK (0x1FFFFU) +#define ASRC_ASR56K_ASR56K_SHIFT (0U) +#define ASRC_ASR56K_ASR56K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK) + +/*! @name ASRMCRA - ASRC Misc Control Register for Pair A */ +#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK (0x3FU) +#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT (0U) +#define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK) +#define ASRC_ASRMCRA_RSYNOFA_MASK (0x400U) +#define ASRC_ASRMCRA_RSYNOFA_SHIFT (10U) +#define ASRC_ASRMCRA_RSYNOFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK) +#define ASRC_ASRMCRA_RSYNIFA_MASK (0x800U) +#define ASRC_ASRMCRA_RSYNIFA_SHIFT (11U) +#define ASRC_ASRMCRA_RSYNIFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK) +#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK (0x3F000U) +#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT (12U) +#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK) +#define ASRC_ASRMCRA_BYPASSPOLYA_MASK (0x100000U) +#define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT (20U) +#define ASRC_ASRMCRA_BYPASSPOLYA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK) +#define ASRC_ASRMCRA_BUFSTALLA_MASK (0x200000U) +#define ASRC_ASRMCRA_BUFSTALLA_SHIFT (21U) +#define ASRC_ASRMCRA_BUFSTALLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK) +#define ASRC_ASRMCRA_EXTTHRSHA_MASK (0x400000U) +#define ASRC_ASRMCRA_EXTTHRSHA_SHIFT (22U) +#define ASRC_ASRMCRA_EXTTHRSHA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK) +#define ASRC_ASRMCRA_ZEROBUFA_MASK (0x800000U) +#define ASRC_ASRMCRA_ZEROBUFA_SHIFT (23U) +#define ASRC_ASRMCRA_ZEROBUFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK) + +/*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */ +#define ASRC_ASRFSTA_INFIFO_FILLA_MASK (0x7FU) +#define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT (0U) +#define ASRC_ASRFSTA_INFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK) +#define ASRC_ASRFSTA_IAEA_MASK (0x800U) +#define ASRC_ASRFSTA_IAEA_SHIFT (11U) +#define ASRC_ASRFSTA_IAEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK) +#define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK (0x7F000U) +#define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT (12U) +#define ASRC_ASRFSTA_OUTFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK) +#define ASRC_ASRFSTA_OAFA_MASK (0x800000U) +#define ASRC_ASRFSTA_OAFA_SHIFT (23U) +#define ASRC_ASRFSTA_OAFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK) + +/*! @name ASRMCRB - ASRC Misc Control Register for Pair B */ +#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK (0x3FU) +#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT (0U) +#define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK) +#define ASRC_ASRMCRB_RSYNOFB_MASK (0x400U) +#define ASRC_ASRMCRB_RSYNOFB_SHIFT (10U) +#define ASRC_ASRMCRB_RSYNOFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK) +#define ASRC_ASRMCRB_RSYNIFB_MASK (0x800U) +#define ASRC_ASRMCRB_RSYNIFB_SHIFT (11U) +#define ASRC_ASRMCRB_RSYNIFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK) +#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK (0x3F000U) +#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT (12U) +#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK) +#define ASRC_ASRMCRB_BYPASSPOLYB_MASK (0x100000U) +#define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT (20U) +#define ASRC_ASRMCRB_BYPASSPOLYB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK) +#define ASRC_ASRMCRB_BUFSTALLB_MASK (0x200000U) +#define ASRC_ASRMCRB_BUFSTALLB_SHIFT (21U) +#define ASRC_ASRMCRB_BUFSTALLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK) +#define ASRC_ASRMCRB_EXTTHRSHB_MASK (0x400000U) +#define ASRC_ASRMCRB_EXTTHRSHB_SHIFT (22U) +#define ASRC_ASRMCRB_EXTTHRSHB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK) +#define ASRC_ASRMCRB_ZEROBUFB_MASK (0x800000U) +#define ASRC_ASRMCRB_ZEROBUFB_SHIFT (23U) +#define ASRC_ASRMCRB_ZEROBUFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK) + +/*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */ +#define ASRC_ASRFSTB_INFIFO_FILLB_MASK (0x7FU) +#define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT (0U) +#define ASRC_ASRFSTB_INFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK) +#define ASRC_ASRFSTB_IAEB_MASK (0x800U) +#define ASRC_ASRFSTB_IAEB_SHIFT (11U) +#define ASRC_ASRFSTB_IAEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK) +#define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK (0x7F000U) +#define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT (12U) +#define ASRC_ASRFSTB_OUTFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK) +#define ASRC_ASRFSTB_OAFB_MASK (0x800000U) +#define ASRC_ASRFSTB_OAFB_SHIFT (23U) +#define ASRC_ASRFSTB_OAFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK) + +/*! @name ASRMCRC - ASRC Misc Control Register for Pair C */ +#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK (0x3FU) +#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT (0U) +#define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK) +#define ASRC_ASRMCRC_RSYNOFC_MASK (0x400U) +#define ASRC_ASRMCRC_RSYNOFC_SHIFT (10U) +#define ASRC_ASRMCRC_RSYNOFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK) +#define ASRC_ASRMCRC_RSYNIFC_MASK (0x800U) +#define ASRC_ASRMCRC_RSYNIFC_SHIFT (11U) +#define ASRC_ASRMCRC_RSYNIFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK) +#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK (0x3F000U) +#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT (12U) +#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK) +#define ASRC_ASRMCRC_BYPASSPOLYC_MASK (0x100000U) +#define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT (20U) +#define ASRC_ASRMCRC_BYPASSPOLYC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK) +#define ASRC_ASRMCRC_BUFSTALLC_MASK (0x200000U) +#define ASRC_ASRMCRC_BUFSTALLC_SHIFT (21U) +#define ASRC_ASRMCRC_BUFSTALLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK) +#define ASRC_ASRMCRC_EXTTHRSHC_MASK (0x400000U) +#define ASRC_ASRMCRC_EXTTHRSHC_SHIFT (22U) +#define ASRC_ASRMCRC_EXTTHRSHC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK) +#define ASRC_ASRMCRC_ZEROBUFC_MASK (0x800000U) +#define ASRC_ASRMCRC_ZEROBUFC_SHIFT (23U) +#define ASRC_ASRMCRC_ZEROBUFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK) + +/*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */ +#define ASRC_ASRFSTC_INFIFO_FILLC_MASK (0x7FU) +#define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT (0U) +#define ASRC_ASRFSTC_INFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK) +#define ASRC_ASRFSTC_IAEC_MASK (0x800U) +#define ASRC_ASRFSTC_IAEC_SHIFT (11U) +#define ASRC_ASRFSTC_IAEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK) +#define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK (0x7F000U) +#define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT (12U) +#define ASRC_ASRFSTC_OUTFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK) +#define ASRC_ASRFSTC_OAFC_MASK (0x800000U) +#define ASRC_ASRFSTC_OAFC_SHIFT (23U) +#define ASRC_ASRFSTC_OAFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK) + +/*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */ +#define ASRC_ASRMCR1_OW16_MASK (0x1U) +#define ASRC_ASRMCR1_OW16_SHIFT (0U) +#define ASRC_ASRMCR1_OW16(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK) +#define ASRC_ASRMCR1_OSGN_MASK (0x2U) +#define ASRC_ASRMCR1_OSGN_SHIFT (1U) +#define ASRC_ASRMCR1_OSGN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK) +#define ASRC_ASRMCR1_OMSB_MASK (0x4U) +#define ASRC_ASRMCR1_OMSB_SHIFT (2U) +#define ASRC_ASRMCR1_OMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK) +#define ASRC_ASRMCR1_IMSB_MASK (0x100U) +#define ASRC_ASRMCR1_IMSB_SHIFT (8U) +#define ASRC_ASRMCR1_IMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK) +#define ASRC_ASRMCR1_IWD_MASK (0xE00U) +#define ASRC_ASRMCR1_IWD_SHIFT (9U) +#define ASRC_ASRMCR1_IWD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK) + +/* The count of ASRC_ASRMCR1 */ +#define ASRC_ASRMCR1_COUNT (3U) + + +/*! + * @} + */ /* end of group ASRC_Register_Masks */ + + +/* ASRC - Peripheral instance base addresses */ +/** Peripheral ASRC base address */ +#define ASRC_BASE (0x2034000u) +/** Peripheral ASRC base pointer */ +#define ASRC ((ASRC_Type *)ASRC_BASE) +/** Array initializer of ASRC peripheral base addresses */ +#define ASRC_BASE_ADDRS { ASRC_BASE } +/** Array initializer of ASRC peripheral base pointers */ +#define ASRC_BASE_PTRS { ASRC } +/** Interrupt vectors for the ASRC peripheral type */ +#define ASRC_IRQS { ASRC_IRQn } + +/*! + * @} + */ /* end of group ASRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BCH Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer + * @{ + */ + +/** BCH - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */ + __I uint32_t STATUS0; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */ + __I uint32_t STATUS0_SET; /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */ + __I uint32_t STATUS0_CLR; /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */ + __I uint32_t STATUS0_TOG; /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */ + __IO uint32_t MODE; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */ + __IO uint32_t MODE_SET; /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */ + __IO uint32_t MODE_CLR; /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */ + __IO uint32_t MODE_TOG; /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */ + __IO uint32_t ENCODEPTR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */ + __IO uint32_t ENCODEPTR_SET; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */ + __IO uint32_t ENCODEPTR_CLR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */ + __IO uint32_t ENCODEPTR_TOG; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */ + __IO uint32_t DATAPTR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */ + __IO uint32_t DATAPTR_SET; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */ + __IO uint32_t DATAPTR_CLR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */ + __IO uint32_t DATAPTR_TOG; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */ + __IO uint32_t METAPTR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */ + __IO uint32_t METAPTR_SET; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */ + __IO uint32_t METAPTR_CLR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */ + __IO uint32_t METAPTR_TOG; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */ + uint8_t RESERVED_0[16]; + __IO uint32_t LAYOUTSELECT; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */ + __IO uint32_t LAYOUTSELECT_SET; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */ + __IO uint32_t LAYOUTSELECT_CLR; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */ + __IO uint32_t LAYOUTSELECT_TOG; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */ + __IO uint32_t FLASH0LAYOUT0; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */ + __IO uint32_t FLASH0LAYOUT0_SET; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */ + __IO uint32_t FLASH0LAYOUT0_CLR; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */ + __IO uint32_t FLASH0LAYOUT0_TOG; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */ + __IO uint32_t FLASH0LAYOUT1; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */ + __IO uint32_t FLASH0LAYOUT1_SET; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */ + __IO uint32_t FLASH0LAYOUT1_CLR; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */ + __IO uint32_t FLASH0LAYOUT1_TOG; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */ + __IO uint32_t FLASH1LAYOUT0; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */ + __IO uint32_t FLASH1LAYOUT0_SET; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */ + __IO uint32_t FLASH1LAYOUT0_CLR; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */ + __IO uint32_t FLASH1LAYOUT0_TOG; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */ + __IO uint32_t FLASH1LAYOUT1; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */ + __IO uint32_t FLASH1LAYOUT1_SET; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */ + __IO uint32_t FLASH1LAYOUT1_CLR; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */ + __IO uint32_t FLASH1LAYOUT1_TOG; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */ + __IO uint32_t FLASH2LAYOUT0; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */ + __IO uint32_t FLASH2LAYOUT0_SET; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */ + __IO uint32_t FLASH2LAYOUT0_CLR; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */ + __IO uint32_t FLASH2LAYOUT0_TOG; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */ + __IO uint32_t FLASH2LAYOUT1; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */ + __IO uint32_t FLASH2LAYOUT1_SET; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */ + __IO uint32_t FLASH2LAYOUT1_CLR; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */ + __IO uint32_t FLASH2LAYOUT1_TOG; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */ + __IO uint32_t FLASH3LAYOUT0; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */ + __IO uint32_t FLASH3LAYOUT0_SET; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */ + __IO uint32_t FLASH3LAYOUT0_CLR; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */ + __IO uint32_t FLASH3LAYOUT0_TOG; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */ + __IO uint32_t FLASH3LAYOUT1; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */ + __IO uint32_t FLASH3LAYOUT1_SET; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */ + __IO uint32_t FLASH3LAYOUT1_CLR; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */ + __IO uint32_t FLASH3LAYOUT1_TOG; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */ + __IO uint32_t DEBUG0; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */ + __IO uint32_t DEBUG0_SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */ + __IO uint32_t DEBUG0_CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */ + __IO uint32_t DEBUG0_TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */ + __I uint32_t DBGKESREAD; /**< KES Debug Read Register, offset: 0x110 */ + __I uint32_t DBGKESREAD_SET; /**< KES Debug Read Register, offset: 0x114 */ + __I uint32_t DBGKESREAD_CLR; /**< KES Debug Read Register, offset: 0x118 */ + __I uint32_t DBGKESREAD_TOG; /**< KES Debug Read Register, offset: 0x11C */ + __I uint32_t DBGCSFEREAD; /**< Chien Search Debug Read Register, offset: 0x120 */ + __I uint32_t DBGCSFEREAD_SET; /**< Chien Search Debug Read Register, offset: 0x124 */ + __I uint32_t DBGCSFEREAD_CLR; /**< Chien Search Debug Read Register, offset: 0x128 */ + __I uint32_t DBGCSFEREAD_TOG; /**< Chien Search Debug Read Register, offset: 0x12C */ + __I uint32_t DBGSYNDGENREAD; /**< Syndrome Generator Debug Read Register, offset: 0x130 */ + __I uint32_t DBGSYNDGENREAD_SET; /**< Syndrome Generator Debug Read Register, offset: 0x134 */ + __I uint32_t DBGSYNDGENREAD_CLR; /**< Syndrome Generator Debug Read Register, offset: 0x138 */ + __I uint32_t DBGSYNDGENREAD_TOG; /**< Syndrome Generator Debug Read Register, offset: 0x13C */ + __I uint32_t DBGAHBMREAD; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */ + __I uint32_t DBGAHBMREAD_SET; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */ + __I uint32_t DBGAHBMREAD_CLR; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */ + __I uint32_t DBGAHBMREAD_TOG; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */ + __I uint32_t BLOCKNAME; /**< Block Name Register, offset: 0x150 */ + __I uint32_t BLOCKNAME_SET; /**< Block Name Register, offset: 0x154 */ + __I uint32_t BLOCKNAME_CLR; /**< Block Name Register, offset: 0x158 */ + __I uint32_t BLOCKNAME_TOG; /**< Block Name Register, offset: 0x15C */ + __I uint32_t VERSION; /**< BCH Version Register, offset: 0x160 */ + __I uint32_t VERSION_SET; /**< BCH Version Register, offset: 0x164 */ + __I uint32_t VERSION_CLR; /**< BCH Version Register, offset: 0x168 */ + __I uint32_t VERSION_TOG; /**< BCH Version Register, offset: 0x16C */ + __IO uint32_t DEBUG1; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */ + __IO uint32_t DEBUG1_SET; /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */ + __IO uint32_t DEBUG1_CLR; /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */ + __IO uint32_t DEBUG1_TOG; /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */ +} BCH_Type; + +/* ---------------------------------------------------------------------------- + -- BCH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BCH_Register_Masks BCH Register Masks + * @{ + */ + +/*! @name CTRL - Hardware BCH ECC Accelerator Control Register */ +#define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK) +#define BCH_CTRL_RSVD0_MASK (0x2U) +#define BCH_CTRL_RSVD0_SHIFT (1U) +#define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK) +#define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK) +#define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK) +#define BCH_CTRL_RSVD1_MASK (0xF0U) +#define BCH_CTRL_RSVD1_SHIFT (4U) +#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK) +#define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK) +#define BCH_CTRL_RSVD2_MASK (0x200U) +#define BCH_CTRL_RSVD2_SHIFT (9U) +#define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK) +#define BCH_CTRL_RSVD3_MASK (0xF800U) +#define BCH_CTRL_RSVD3_SHIFT (11U) +#define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK) +#define BCH_CTRL_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK) +#define BCH_CTRL_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK) +#define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK) +#define BCH_CTRL_RSVD4_MASK (0x300000U) +#define BCH_CTRL_RSVD4_SHIFT (20U) +#define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK) +#define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK) +#define BCH_CTRL_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_RSVD5_SHIFT (23U) +#define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK) +#define BCH_CTRL_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_CLKGATE_SHIFT (30U) +#define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK) +#define BCH_CTRL_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_SFTRST_SHIFT (31U) +#define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK) + +/*! @name CTRL_SET - Hardware BCH ECC Accelerator Control Register */ +#define BCH_CTRL_SET_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_SET_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_SET_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_MASK) +#define BCH_CTRL_SET_RSVD0_MASK (0x2U) +#define BCH_CTRL_SET_RSVD0_SHIFT (1U) +#define BCH_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD0_SHIFT)) & BCH_CTRL_SET_RSVD0_MASK) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK) +#define BCH_CTRL_SET_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_SET_BM_ERROR_IRQ_MASK) +#define BCH_CTRL_SET_RSVD1_MASK (0xF0U) +#define BCH_CTRL_SET_RSVD1_SHIFT (4U) +#define BCH_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD1_SHIFT)) & BCH_CTRL_SET_RSVD1_MASK) +#define BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_SET_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK) +#define BCH_CTRL_SET_RSVD2_MASK (0x200U) +#define BCH_CTRL_SET_RSVD2_SHIFT (9U) +#define BCH_CTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD2_SHIFT)) & BCH_CTRL_SET_RSVD2_MASK) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK) +#define BCH_CTRL_SET_RSVD3_MASK (0xF800U) +#define BCH_CTRL_SET_RSVD3_SHIFT (11U) +#define BCH_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD3_SHIFT)) & BCH_CTRL_SET_RSVD3_MASK) +#define BCH_CTRL_SET_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_SET_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_SET_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENABLE_SHIFT)) & BCH_CTRL_SET_M2M_ENABLE_MASK) +#define BCH_CTRL_SET_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_SET_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_SET_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENCODE_SHIFT)) & BCH_CTRL_SET_M2M_ENCODE_MASK) +#define BCH_CTRL_SET_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_SET_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_SET_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_LAYOUT_SHIFT)) & BCH_CTRL_SET_M2M_LAYOUT_MASK) +#define BCH_CTRL_SET_RSVD4_MASK (0x300000U) +#define BCH_CTRL_SET_RSVD4_SHIFT (20U) +#define BCH_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD4_SHIFT)) & BCH_CTRL_SET_RSVD4_MASK) +#define BCH_CTRL_SET_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_SET_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_SET_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_SET_DEBUGSYNDROME_MASK) +#define BCH_CTRL_SET_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_SET_RSVD5_SHIFT (23U) +#define BCH_CTRL_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD5_SHIFT)) & BCH_CTRL_SET_RSVD5_MASK) +#define BCH_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_SET_CLKGATE_SHIFT (30U) +#define BCH_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_CLKGATE_SHIFT)) & BCH_CTRL_SET_CLKGATE_MASK) +#define BCH_CTRL_SET_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_SET_SFTRST_SHIFT (31U) +#define BCH_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_SFTRST_SHIFT)) & BCH_CTRL_SET_SFTRST_MASK) + +/*! @name CTRL_CLR - Hardware BCH ECC Accelerator Control Register */ +#define BCH_CTRL_CLR_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_CLR_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_MASK) +#define BCH_CTRL_CLR_RSVD0_MASK (0x2U) +#define BCH_CTRL_CLR_RSVD0_SHIFT (1U) +#define BCH_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD0_SHIFT)) & BCH_CTRL_CLR_RSVD0_MASK) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK) +#define BCH_CTRL_CLR_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_CLR_BM_ERROR_IRQ_MASK) +#define BCH_CTRL_CLR_RSVD1_MASK (0xF0U) +#define BCH_CTRL_CLR_RSVD1_SHIFT (4U) +#define BCH_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD1_SHIFT)) & BCH_CTRL_CLR_RSVD1_MASK) +#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_CLR_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK) +#define BCH_CTRL_CLR_RSVD2_MASK (0x200U) +#define BCH_CTRL_CLR_RSVD2_SHIFT (9U) +#define BCH_CTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD2_SHIFT)) & BCH_CTRL_CLR_RSVD2_MASK) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK) +#define BCH_CTRL_CLR_RSVD3_MASK (0xF800U) +#define BCH_CTRL_CLR_RSVD3_SHIFT (11U) +#define BCH_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD3_SHIFT)) & BCH_CTRL_CLR_RSVD3_MASK) +#define BCH_CTRL_CLR_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_CLR_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_CLR_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENABLE_SHIFT)) & BCH_CTRL_CLR_M2M_ENABLE_MASK) +#define BCH_CTRL_CLR_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_CLR_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_CLR_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENCODE_SHIFT)) & BCH_CTRL_CLR_M2M_ENCODE_MASK) +#define BCH_CTRL_CLR_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_CLR_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_CLR_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_LAYOUT_SHIFT)) & BCH_CTRL_CLR_M2M_LAYOUT_MASK) +#define BCH_CTRL_CLR_RSVD4_MASK (0x300000U) +#define BCH_CTRL_CLR_RSVD4_SHIFT (20U) +#define BCH_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD4_SHIFT)) & BCH_CTRL_CLR_RSVD4_MASK) +#define BCH_CTRL_CLR_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_CLR_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_CLR_DEBUGSYNDROME_MASK) +#define BCH_CTRL_CLR_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_CLR_RSVD5_SHIFT (23U) +#define BCH_CTRL_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD5_SHIFT)) & BCH_CTRL_CLR_RSVD5_MASK) +#define BCH_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_CLR_CLKGATE_SHIFT (30U) +#define BCH_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_CLKGATE_SHIFT)) & BCH_CTRL_CLR_CLKGATE_MASK) +#define BCH_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_CLR_SFTRST_SHIFT (31U) +#define BCH_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_SFTRST_SHIFT)) & BCH_CTRL_CLR_SFTRST_MASK) + +/*! @name CTRL_TOG - Hardware BCH ECC Accelerator Control Register */ +#define BCH_CTRL_TOG_COMPLETE_IRQ_MASK (0x1U) +#define BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT (0U) +#define BCH_CTRL_TOG_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_MASK) +#define BCH_CTRL_TOG_RSVD0_MASK (0x2U) +#define BCH_CTRL_TOG_RSVD0_SHIFT (1U) +#define BCH_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD0_SHIFT)) & BCH_CTRL_TOG_RSVD0_MASK) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK (0x4U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT (2U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK) +#define BCH_CTRL_TOG_BM_ERROR_IRQ_MASK (0x8U) +#define BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT (3U) +#define BCH_CTRL_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_TOG_BM_ERROR_IRQ_MASK) +#define BCH_CTRL_TOG_RSVD1_MASK (0xF0U) +#define BCH_CTRL_TOG_RSVD1_SHIFT (4U) +#define BCH_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD1_SHIFT)) & BCH_CTRL_TOG_RSVD1_MASK) +#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK (0x100U) +#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT (8U) +#define BCH_CTRL_TOG_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK) +#define BCH_CTRL_TOG_RSVD2_MASK (0x200U) +#define BCH_CTRL_TOG_RSVD2_SHIFT (9U) +#define BCH_CTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD2_SHIFT)) & BCH_CTRL_TOG_RSVD2_MASK) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK (0x400U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT (10U) +#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK) +#define BCH_CTRL_TOG_RSVD3_MASK (0xF800U) +#define BCH_CTRL_TOG_RSVD3_SHIFT (11U) +#define BCH_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD3_SHIFT)) & BCH_CTRL_TOG_RSVD3_MASK) +#define BCH_CTRL_TOG_M2M_ENABLE_MASK (0x10000U) +#define BCH_CTRL_TOG_M2M_ENABLE_SHIFT (16U) +#define BCH_CTRL_TOG_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENABLE_SHIFT)) & BCH_CTRL_TOG_M2M_ENABLE_MASK) +#define BCH_CTRL_TOG_M2M_ENCODE_MASK (0x20000U) +#define BCH_CTRL_TOG_M2M_ENCODE_SHIFT (17U) +#define BCH_CTRL_TOG_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENCODE_SHIFT)) & BCH_CTRL_TOG_M2M_ENCODE_MASK) +#define BCH_CTRL_TOG_M2M_LAYOUT_MASK (0xC0000U) +#define BCH_CTRL_TOG_M2M_LAYOUT_SHIFT (18U) +#define BCH_CTRL_TOG_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_LAYOUT_SHIFT)) & BCH_CTRL_TOG_M2M_LAYOUT_MASK) +#define BCH_CTRL_TOG_RSVD4_MASK (0x300000U) +#define BCH_CTRL_TOG_RSVD4_SHIFT (20U) +#define BCH_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD4_SHIFT)) & BCH_CTRL_TOG_RSVD4_MASK) +#define BCH_CTRL_TOG_DEBUGSYNDROME_MASK (0x400000U) +#define BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT (22U) +#define BCH_CTRL_TOG_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_TOG_DEBUGSYNDROME_MASK) +#define BCH_CTRL_TOG_RSVD5_MASK (0x3F800000U) +#define BCH_CTRL_TOG_RSVD5_SHIFT (23U) +#define BCH_CTRL_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD5_SHIFT)) & BCH_CTRL_TOG_RSVD5_MASK) +#define BCH_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define BCH_CTRL_TOG_CLKGATE_SHIFT (30U) +#define BCH_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_CLKGATE_SHIFT)) & BCH_CTRL_TOG_CLKGATE_MASK) +#define BCH_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define BCH_CTRL_TOG_SFTRST_SHIFT (31U) +#define BCH_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_SFTRST_SHIFT)) & BCH_CTRL_TOG_SFTRST_MASK) + +/*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */ +#define BCH_STATUS0_RSVD0_MASK (0x3U) +#define BCH_STATUS0_RSVD0_SHIFT (0U) +#define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK) +#define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK) +#define BCH_STATUS0_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK) +#define BCH_STATUS0_ALLONES_MASK (0x10U) +#define BCH_STATUS0_ALLONES_SHIFT (4U) +#define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK) +#define BCH_STATUS0_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_RSVD1_SHIFT (5U) +#define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK) +#define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_STATUS_BLK0_SHIFT (8U) +#define BCH_STATUS0_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK) +#define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK) +#define BCH_STATUS0_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_HANDLE_SHIFT (20U) +#define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK) + +/*! @name STATUS0_SET - Hardware ECC Accelerator Status Register 0 */ +#define BCH_STATUS0_SET_RSVD0_MASK (0x3U) +#define BCH_STATUS0_SET_RSVD0_SHIFT (0U) +#define BCH_STATUS0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_RSVD0_SHIFT)) & BCH_STATUS0_SET_RSVD0_MASK) +#define BCH_STATUS0_SET_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_SET_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_SET_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_SET_UNCORRECTABLE_MASK) +#define BCH_STATUS0_SET_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_SET_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_SET_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_CORRECTED_SHIFT)) & BCH_STATUS0_SET_CORRECTED_MASK) +#define BCH_STATUS0_SET_ALLONES_MASK (0x10U) +#define BCH_STATUS0_SET_ALLONES_SHIFT (4U) +#define BCH_STATUS0_SET_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_ALLONES_SHIFT)) & BCH_STATUS0_SET_ALLONES_MASK) +#define BCH_STATUS0_SET_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_SET_RSVD1_SHIFT (5U) +#define BCH_STATUS0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_RSVD1_SHIFT)) & BCH_STATUS0_SET_RSVD1_MASK) +#define BCH_STATUS0_SET_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_SET_STATUS_BLK0_SHIFT (8U) +#define BCH_STATUS0_SET_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_STATUS_BLK0_SHIFT)) & BCH_STATUS0_SET_STATUS_BLK0_MASK) +#define BCH_STATUS0_SET_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_SET_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_SET_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_COMPLETED_CE_SHIFT)) & BCH_STATUS0_SET_COMPLETED_CE_MASK) +#define BCH_STATUS0_SET_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_SET_HANDLE_SHIFT (20U) +#define BCH_STATUS0_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_SET_HANDLE_SHIFT)) & BCH_STATUS0_SET_HANDLE_MASK) + +/*! @name STATUS0_CLR - Hardware ECC Accelerator Status Register 0 */ +#define BCH_STATUS0_CLR_RSVD0_MASK (0x3U) +#define BCH_STATUS0_CLR_RSVD0_SHIFT (0U) +#define BCH_STATUS0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD0_SHIFT)) & BCH_STATUS0_CLR_RSVD0_MASK) +#define BCH_STATUS0_CLR_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_CLR_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_CLR_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_CLR_UNCORRECTABLE_MASK) +#define BCH_STATUS0_CLR_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_CLR_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_CLR_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_CORRECTED_SHIFT)) & BCH_STATUS0_CLR_CORRECTED_MASK) +#define BCH_STATUS0_CLR_ALLONES_MASK (0x10U) +#define BCH_STATUS0_CLR_ALLONES_SHIFT (4U) +#define BCH_STATUS0_CLR_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_ALLONES_SHIFT)) & BCH_STATUS0_CLR_ALLONES_MASK) +#define BCH_STATUS0_CLR_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_CLR_RSVD1_SHIFT (5U) +#define BCH_STATUS0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_RSVD1_SHIFT)) & BCH_STATUS0_CLR_RSVD1_MASK) +#define BCH_STATUS0_CLR_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_CLR_STATUS_BLK0_SHIFT (8U) +#define BCH_STATUS0_CLR_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_STATUS_BLK0_SHIFT)) & BCH_STATUS0_CLR_STATUS_BLK0_MASK) +#define BCH_STATUS0_CLR_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_CLR_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_CLR_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_COMPLETED_CE_SHIFT)) & BCH_STATUS0_CLR_COMPLETED_CE_MASK) +#define BCH_STATUS0_CLR_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_CLR_HANDLE_SHIFT (20U) +#define BCH_STATUS0_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CLR_HANDLE_SHIFT)) & BCH_STATUS0_CLR_HANDLE_MASK) + +/*! @name STATUS0_TOG - Hardware ECC Accelerator Status Register 0 */ +#define BCH_STATUS0_TOG_RSVD0_MASK (0x3U) +#define BCH_STATUS0_TOG_RSVD0_SHIFT (0U) +#define BCH_STATUS0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_RSVD0_SHIFT)) & BCH_STATUS0_TOG_RSVD0_MASK) +#define BCH_STATUS0_TOG_UNCORRECTABLE_MASK (0x4U) +#define BCH_STATUS0_TOG_UNCORRECTABLE_SHIFT (2U) +#define BCH_STATUS0_TOG_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_TOG_UNCORRECTABLE_MASK) +#define BCH_STATUS0_TOG_CORRECTED_MASK (0x8U) +#define BCH_STATUS0_TOG_CORRECTED_SHIFT (3U) +#define BCH_STATUS0_TOG_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_CORRECTED_SHIFT)) & BCH_STATUS0_TOG_CORRECTED_MASK) +#define BCH_STATUS0_TOG_ALLONES_MASK (0x10U) +#define BCH_STATUS0_TOG_ALLONES_SHIFT (4U) +#define BCH_STATUS0_TOG_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_ALLONES_SHIFT)) & BCH_STATUS0_TOG_ALLONES_MASK) +#define BCH_STATUS0_TOG_RSVD1_MASK (0xE0U) +#define BCH_STATUS0_TOG_RSVD1_SHIFT (5U) +#define BCH_STATUS0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_RSVD1_SHIFT)) & BCH_STATUS0_TOG_RSVD1_MASK) +#define BCH_STATUS0_TOG_STATUS_BLK0_MASK (0xFF00U) +#define BCH_STATUS0_TOG_STATUS_BLK0_SHIFT (8U) +#define BCH_STATUS0_TOG_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_STATUS_BLK0_SHIFT)) & BCH_STATUS0_TOG_STATUS_BLK0_MASK) +#define BCH_STATUS0_TOG_COMPLETED_CE_MASK (0xF0000U) +#define BCH_STATUS0_TOG_COMPLETED_CE_SHIFT (16U) +#define BCH_STATUS0_TOG_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_COMPLETED_CE_SHIFT)) & BCH_STATUS0_TOG_COMPLETED_CE_MASK) +#define BCH_STATUS0_TOG_HANDLE_MASK (0xFFF00000U) +#define BCH_STATUS0_TOG_HANDLE_SHIFT (20U) +#define BCH_STATUS0_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_TOG_HANDLE_SHIFT)) & BCH_STATUS0_TOG_HANDLE_MASK) + +/*! @name MODE - Hardware ECC Accelerator Mode Register */ +#define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK) +#define BCH_MODE_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_RSVD_SHIFT (8U) +#define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK) + +/*! @name MODE_SET - Hardware ECC Accelerator Mode Register */ +#define BCH_MODE_SET_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_SET_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_SET_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_SET_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_SET_ERASE_THRESHOLD_MASK) +#define BCH_MODE_SET_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_SET_RSVD_SHIFT (8U) +#define BCH_MODE_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_SET_RSVD_SHIFT)) & BCH_MODE_SET_RSVD_MASK) + +/*! @name MODE_CLR - Hardware ECC Accelerator Mode Register */ +#define BCH_MODE_CLR_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_CLR_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_CLR_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_CLR_ERASE_THRESHOLD_MASK) +#define BCH_MODE_CLR_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_CLR_RSVD_SHIFT (8U) +#define BCH_MODE_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_CLR_RSVD_SHIFT)) & BCH_MODE_CLR_RSVD_MASK) + +/*! @name MODE_TOG - Hardware ECC Accelerator Mode Register */ +#define BCH_MODE_TOG_ERASE_THRESHOLD_MASK (0xFFU) +#define BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT (0U) +#define BCH_MODE_TOG_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_TOG_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_TOG_ERASE_THRESHOLD_MASK) +#define BCH_MODE_TOG_RSVD_MASK (0xFFFFFF00U) +#define BCH_MODE_TOG_RSVD_SHIFT (8U) +#define BCH_MODE_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_TOG_RSVD_SHIFT)) & BCH_MODE_TOG_RSVD_MASK) + +/*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */ +#define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK) + +/*! @name ENCODEPTR_SET - Hardware BCH ECC Loopback Encode Buffer Register */ +#define BCH_ENCODEPTR_SET_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_SET_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_SET_ADDR_SHIFT)) & BCH_ENCODEPTR_SET_ADDR_MASK) + +/*! @name ENCODEPTR_CLR - Hardware BCH ECC Loopback Encode Buffer Register */ +#define BCH_ENCODEPTR_CLR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_CLR_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_CLR_ADDR_SHIFT)) & BCH_ENCODEPTR_CLR_ADDR_MASK) + +/*! @name ENCODEPTR_TOG - Hardware BCH ECC Loopback Encode Buffer Register */ +#define BCH_ENCODEPTR_TOG_ADDR_MASK (0xFFFFFFFFU) +#define BCH_ENCODEPTR_TOG_ADDR_SHIFT (0U) +#define BCH_ENCODEPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_TOG_ADDR_SHIFT)) & BCH_ENCODEPTR_TOG_ADDR_MASK) + +/*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */ +#define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_ADDR_SHIFT (0U) +#define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK) + +/*! @name DATAPTR_SET - Hardware BCH ECC Loopback Data Buffer Register */ +#define BCH_DATAPTR_SET_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_SET_ADDR_SHIFT (0U) +#define BCH_DATAPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_SET_ADDR_SHIFT)) & BCH_DATAPTR_SET_ADDR_MASK) + +/*! @name DATAPTR_CLR - Hardware BCH ECC Loopback Data Buffer Register */ +#define BCH_DATAPTR_CLR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_CLR_ADDR_SHIFT (0U) +#define BCH_DATAPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_CLR_ADDR_SHIFT)) & BCH_DATAPTR_CLR_ADDR_MASK) + +/*! @name DATAPTR_TOG - Hardware BCH ECC Loopback Data Buffer Register */ +#define BCH_DATAPTR_TOG_ADDR_MASK (0xFFFFFFFFU) +#define BCH_DATAPTR_TOG_ADDR_SHIFT (0U) +#define BCH_DATAPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_TOG_ADDR_SHIFT)) & BCH_DATAPTR_TOG_ADDR_MASK) + +/*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */ +#define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_ADDR_SHIFT (0U) +#define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK) + +/*! @name METAPTR_SET - Hardware BCH ECC Loopback Metadata Buffer Register */ +#define BCH_METAPTR_SET_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_SET_ADDR_SHIFT (0U) +#define BCH_METAPTR_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_SET_ADDR_SHIFT)) & BCH_METAPTR_SET_ADDR_MASK) + +/*! @name METAPTR_CLR - Hardware BCH ECC Loopback Metadata Buffer Register */ +#define BCH_METAPTR_CLR_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_CLR_ADDR_SHIFT (0U) +#define BCH_METAPTR_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_CLR_ADDR_SHIFT)) & BCH_METAPTR_CLR_ADDR_MASK) + +/*! @name METAPTR_TOG - Hardware BCH ECC Loopback Metadata Buffer Register */ +#define BCH_METAPTR_TOG_ADDR_MASK (0xFFFFFFFFU) +#define BCH_METAPTR_TOG_ADDR_SHIFT (0U) +#define BCH_METAPTR_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_TOG_ADDR_SHIFT)) & BCH_METAPTR_TOG_ADDR_MASK) + +/*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */ +#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK) + +/*! @name LAYOUTSELECT_SET - Hardware ECC Accelerator Layout Select Register */ +#define BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_SET_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_SET_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_SET_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_SET_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_SET_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_SET_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_SET_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_SET_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_SET_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_SET_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_SET_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_SET_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_SET_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_SET_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_SET_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_SET_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_SET_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_SET_CS15_SELECT_MASK) + +/*! @name LAYOUTSELECT_CLR - Hardware ECC Accelerator Layout Select Register */ +#define BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_CLR_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_CLR_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_CLR_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_CLR_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_CLR_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_CLR_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_CLR_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_CLR_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_CLR_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_CLR_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_CLR_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_CLR_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_CLR_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_CLR_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_CLR_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_CLR_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CLR_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CLR_CS15_SELECT_MASK) + +/*! @name LAYOUTSELECT_TOG - Hardware ECC Accelerator Layout Select Register */ +#define BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK (0x3U) +#define BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT (0U) +#define BCH_LAYOUTSELECT_TOG_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS0_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK (0xCU) +#define BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT (2U) +#define BCH_LAYOUTSELECT_TOG_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS1_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK (0x30U) +#define BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT (4U) +#define BCH_LAYOUTSELECT_TOG_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS2_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK (0xC0U) +#define BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT (6U) +#define BCH_LAYOUTSELECT_TOG_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS3_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK (0x300U) +#define BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT (8U) +#define BCH_LAYOUTSELECT_TOG_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS4_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK (0xC00U) +#define BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT (10U) +#define BCH_LAYOUTSELECT_TOG_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS5_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK (0x3000U) +#define BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT (12U) +#define BCH_LAYOUTSELECT_TOG_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS6_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK (0xC000U) +#define BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT (14U) +#define BCH_LAYOUTSELECT_TOG_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS7_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK (0x30000U) +#define BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT (16U) +#define BCH_LAYOUTSELECT_TOG_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS8_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK (0xC0000U) +#define BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT (18U) +#define BCH_LAYOUTSELECT_TOG_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS9_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK (0x300000U) +#define BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT (20U) +#define BCH_LAYOUTSELECT_TOG_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS10_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK (0xC00000U) +#define BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT (22U) +#define BCH_LAYOUTSELECT_TOG_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS11_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK (0x3000000U) +#define BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT (24U) +#define BCH_LAYOUTSELECT_TOG_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS12_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK (0xC000000U) +#define BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT (26U) +#define BCH_LAYOUTSELECT_TOG_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS13_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK (0x30000000U) +#define BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT (28U) +#define BCH_LAYOUTSELECT_TOG_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS14_SELECT_MASK) +#define BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK (0xC0000000U) +#define BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT (30U) +#define BCH_LAYOUTSELECT_TOG_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_TOG_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_TOG_CS15_SELECT_MASK) + +/*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */ +#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_ECC0_SHIFT (11U) +#define BCH_FLASH0LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK) + +/*! @name FLASH0LAYOUT0_SET - Hardware BCH ECC Flash 0 Layout 0 Register */ +#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT (11U) +#define BCH_FLASH0LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_SET_NBLOCKS_MASK) + +/*! @name FLASH0LAYOUT0_CLR - Hardware BCH ECC Flash 0 Layout 0 Register */ +#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT (11U) +#define BCH_FLASH0LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_CLR_NBLOCKS_MASK) + +/*! @name FLASH0LAYOUT0_TOG - Hardware BCH ECC Flash 0 Layout 0 Register */ +#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT (11U) +#define BCH_FLASH0LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH0LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_TOG_NBLOCKS_MASK) + +/*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */ +#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_ECCN_SHIFT (11U) +#define BCH_FLASH0LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK) + +/*! @name FLASH0LAYOUT1_SET - Hardware BCH ECC Flash 0 Layout 1 Register */ +#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT (11U) +#define BCH_FLASH0LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_SET_PAGE_SIZE_MASK) + +/*! @name FLASH0LAYOUT1_CLR - Hardware BCH ECC Flash 0 Layout 1 Register */ +#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT (11U) +#define BCH_FLASH0LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_CLR_PAGE_SIZE_MASK) + +/*! @name FLASH0LAYOUT1_TOG - Hardware BCH ECC Flash 0 Layout 1 Register */ +#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH0LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT (11U) +#define BCH_FLASH0LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_TOG_PAGE_SIZE_MASK) + +/*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */ +#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_ECC0_SHIFT (11U) +#define BCH_FLASH1LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK) + +/*! @name FLASH1LAYOUT0_SET - Hardware BCH ECC Flash 1 Layout 0 Register */ +#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT (11U) +#define BCH_FLASH1LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_SET_NBLOCKS_MASK) + +/*! @name FLASH1LAYOUT0_CLR - Hardware BCH ECC Flash 1 Layout 0 Register */ +#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT (11U) +#define BCH_FLASH1LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_CLR_NBLOCKS_MASK) + +/*! @name FLASH1LAYOUT0_TOG - Hardware BCH ECC Flash 1 Layout 0 Register */ +#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT (11U) +#define BCH_FLASH1LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH1LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_TOG_NBLOCKS_MASK) + +/*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */ +#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_ECCN_SHIFT (11U) +#define BCH_FLASH1LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK) + +/*! @name FLASH1LAYOUT1_SET - Hardware BCH ECC Flash 1 Layout 1 Register */ +#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT (11U) +#define BCH_FLASH1LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_SET_PAGE_SIZE_MASK) + +/*! @name FLASH1LAYOUT1_CLR - Hardware BCH ECC Flash 1 Layout 1 Register */ +#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT (11U) +#define BCH_FLASH1LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_CLR_PAGE_SIZE_MASK) + +/*! @name FLASH1LAYOUT1_TOG - Hardware BCH ECC Flash 1 Layout 1 Register */ +#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH1LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT (11U) +#define BCH_FLASH1LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_TOG_PAGE_SIZE_MASK) + +/*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */ +#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_ECC0_SHIFT (11U) +#define BCH_FLASH2LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK) + +/*! @name FLASH2LAYOUT0_SET - Hardware BCH ECC Flash 2 Layout 0 Register */ +#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT (11U) +#define BCH_FLASH2LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_SET_NBLOCKS_MASK) + +/*! @name FLASH2LAYOUT0_CLR - Hardware BCH ECC Flash 2 Layout 0 Register */ +#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT (11U) +#define BCH_FLASH2LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_CLR_NBLOCKS_MASK) + +/*! @name FLASH2LAYOUT0_TOG - Hardware BCH ECC Flash 2 Layout 0 Register */ +#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT (11U) +#define BCH_FLASH2LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH2LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_TOG_NBLOCKS_MASK) + +/*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */ +#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_ECCN_SHIFT (11U) +#define BCH_FLASH2LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK) + +/*! @name FLASH2LAYOUT1_SET - Hardware BCH ECC Flash 2 Layout 1 Register */ +#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT (11U) +#define BCH_FLASH2LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_SET_PAGE_SIZE_MASK) + +/*! @name FLASH2LAYOUT1_CLR - Hardware BCH ECC Flash 2 Layout 1 Register */ +#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT (11U) +#define BCH_FLASH2LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_CLR_PAGE_SIZE_MASK) + +/*! @name FLASH2LAYOUT1_TOG - Hardware BCH ECC Flash 2 Layout 1 Register */ +#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH2LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT (11U) +#define BCH_FLASH2LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_TOG_PAGE_SIZE_MASK) + +/*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */ +#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_ECC0_SHIFT (11U) +#define BCH_FLASH3LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK) + +/*! @name FLASH3LAYOUT0_SET - Hardware BCH ECC Flash 3 Layout 0 Register */ +#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_SET_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_SET_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT0_SET_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT (11U) +#define BCH_FLASH3LAYOUT0_SET_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_SET_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_SET_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_SET_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_SET_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_SET_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_SET_NBLOCKS_MASK) + +/*! @name FLASH3LAYOUT0_CLR - Hardware BCH ECC Flash 3 Layout 0 Register */ +#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT0_CLR_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT (11U) +#define BCH_FLASH3LAYOUT0_CLR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_CLR_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_CLR_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_CLR_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_CLR_NBLOCKS_MASK) + +/*! @name FLASH3LAYOUT0_TOG - Hardware BCH ECC Flash 3 Layout 0 Register */ +#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_DATA0_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT0_TOG_ECC0_MASK (0xF800U) +#define BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT (11U) +#define BCH_FLASH3LAYOUT0_TOG_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_ECC0_MASK) +#define BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK (0xFF0000U) +#define BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT0_TOG_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_META_SIZE_MASK) +#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK (0xFF000000U) +#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT (24U) +#define BCH_FLASH3LAYOUT0_TOG_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_TOG_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_TOG_NBLOCKS_MASK) + +/*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */ +#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_ECCN_SHIFT (11U) +#define BCH_FLASH3LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK) + +/*! @name FLASH3LAYOUT1_SET - Hardware BCH ECC Flash 3 Layout 1 Register */ +#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_SET_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_SET_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_SET_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT1_SET_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT (11U) +#define BCH_FLASH3LAYOUT1_SET_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_SET_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_SET_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_SET_PAGE_SIZE_MASK) + +/*! @name FLASH3LAYOUT1_CLR - Hardware BCH ECC Flash 3 Layout 1 Register */ +#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT1_CLR_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT (11U) +#define BCH_FLASH3LAYOUT1_CLR_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_CLR_PAGE_SIZE_MASK) + +/*! @name FLASH3LAYOUT1_TOG - Hardware BCH ECC Flash 3 Layout 1 Register */ +#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK (0x3FFU) +#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT (0U) +#define BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_DATAN_SIZE_MASK) +#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_MASK (0x400U) +#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_SHIFT (10U) +#define BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_GF13_0_GF14_1_MASK) +#define BCH_FLASH3LAYOUT1_TOG_ECCN_MASK (0xF800U) +#define BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT (11U) +#define BCH_FLASH3LAYOUT1_TOG_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_ECCN_MASK) +#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK (0xFFFF0000U) +#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT (16U) +#define BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_TOG_PAGE_SIZE_MASK) + +/*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */ +#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_RSVD0_SHIFT (6U) +#define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT (8U) +#define BCH_DEBUG0_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK) +#define BCH_DEBUG0_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT (9U) +#define BCH_DEBUG0_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK) +#define BCH_DEBUG0_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK) +#define BCH_DEBUG0_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_KES_STANDALONE_SHIFT (11U) +#define BCH_DEBUG0_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK) +#define BCH_DEBUG0_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK) +#define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT (13U) +#define BCH_DEBUG0_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK) +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_RSVD1_SHIFT (25U) +#define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK) + +/*! @name DEBUG0_SET - Hardware BCH ECC Debug Register0 */ +#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_SET_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_SET_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_SET_RSVD0_SHIFT (6U) +#define BCH_DEBUG0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD0_SHIFT)) & BCH_DEBUG0_SET_RSVD0_MASK) +#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT (8U) +#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT (9U) +#define BCH_DEBUG0_SET_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_SET_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK) +#define BCH_DEBUG0_SET_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_SET_KES_STANDALONE_SHIFT (11U) +#define BCH_DEBUG0_SET_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_SET_KES_STANDALONE_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_SET_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT (13U) +#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK) +#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_SET_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_SET_RSVD1_SHIFT (25U) +#define BCH_DEBUG0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD1_SHIFT)) & BCH_DEBUG0_SET_RSVD1_MASK) + +/*! @name DEBUG0_CLR - Hardware BCH ECC Debug Register0 */ +#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_CLR_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_CLR_RSVD0_SHIFT (6U) +#define BCH_DEBUG0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD0_SHIFT)) & BCH_DEBUG0_CLR_RSVD0_MASK) +#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT (8U) +#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT (9U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_CLR_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK) +#define BCH_DEBUG0_CLR_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT (11U) +#define BCH_DEBUG0_CLR_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_CLR_KES_STANDALONE_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_CLR_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT (13U) +#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK) +#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_CLR_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_CLR_RSVD1_SHIFT (25U) +#define BCH_DEBUG0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD1_SHIFT)) & BCH_DEBUG0_CLR_RSVD1_MASK) + +/*! @name DEBUG0_TOG - Hardware BCH ECC Debug Register0 */ +#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK (0x3FU) +#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT (0U) +#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK) +#define BCH_DEBUG0_TOG_RSVD0_MASK (0xC0U) +#define BCH_DEBUG0_TOG_RSVD0_SHIFT (6U) +#define BCH_DEBUG0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD0_SHIFT)) & BCH_DEBUG0_TOG_RSVD0_MASK) +#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK (0x100U) +#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT (8U) +#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK (0x200U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT (9U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK (0x400U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT (10U) +#define BCH_DEBUG0_TOG_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK) +#define BCH_DEBUG0_TOG_KES_STANDALONE_MASK (0x800U) +#define BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT (11U) +#define BCH_DEBUG0_TOG_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_TOG_KES_STANDALONE_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK (0x1000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT (12U) +#define BCH_DEBUG0_TOG_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK (0x2000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT (13U) +#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U) +#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK (0x8000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT (15U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK) +#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U) +#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK) +#define BCH_DEBUG0_TOG_RSVD1_MASK (0xFE000000U) +#define BCH_DEBUG0_TOG_RSVD1_SHIFT (25U) +#define BCH_DEBUG0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD1_SHIFT)) & BCH_DEBUG0_TOG_RSVD1_MASK) + +/*! @name DBGKESREAD - KES Debug Read Register */ +#define BCH_DBGKESREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK) + +/*! @name DBGKESREAD_SET - KES Debug Read Register */ +#define BCH_DBGKESREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_SET_VALUES_SHIFT)) & BCH_DBGKESREAD_SET_VALUES_MASK) + +/*! @name DBGKESREAD_CLR - KES Debug Read Register */ +#define BCH_DBGKESREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_CLR_VALUES_SHIFT)) & BCH_DBGKESREAD_CLR_VALUES_MASK) + +/*! @name DBGKESREAD_TOG - KES Debug Read Register */ +#define BCH_DBGKESREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGKESREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGKESREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_TOG_VALUES_SHIFT)) & BCH_DBGKESREAD_TOG_VALUES_MASK) + +/*! @name DBGCSFEREAD - Chien Search Debug Read Register */ +#define BCH_DBGCSFEREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK) + +/*! @name DBGCSFEREAD_SET - Chien Search Debug Read Register */ +#define BCH_DBGCSFEREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_SET_VALUES_SHIFT)) & BCH_DBGCSFEREAD_SET_VALUES_MASK) + +/*! @name DBGCSFEREAD_CLR - Chien Search Debug Read Register */ +#define BCH_DBGCSFEREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_CLR_VALUES_SHIFT)) & BCH_DBGCSFEREAD_CLR_VALUES_MASK) + +/*! @name DBGCSFEREAD_TOG - Chien Search Debug Read Register */ +#define BCH_DBGCSFEREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGCSFEREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGCSFEREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_TOG_VALUES_SHIFT)) & BCH_DBGCSFEREAD_TOG_VALUES_MASK) + +/*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */ +#define BCH_DBGSYNDGENREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK) + +/*! @name DBGSYNDGENREAD_SET - Syndrome Generator Debug Read Register */ +#define BCH_DBGSYNDGENREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_SET_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_SET_VALUES_MASK) + +/*! @name DBGSYNDGENREAD_CLR - Syndrome Generator Debug Read Register */ +#define BCH_DBGSYNDGENREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_CLR_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_CLR_VALUES_MASK) + +/*! @name DBGSYNDGENREAD_TOG - Syndrome Generator Debug Read Register */ +#define BCH_DBGSYNDGENREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGSYNDGENREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_TOG_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_TOG_VALUES_MASK) + +/*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */ +#define BCH_DBGAHBMREAD_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK) + +/*! @name DBGAHBMREAD_SET - Bus Master and ECC Controller Debug Read Register */ +#define BCH_DBGAHBMREAD_SET_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_SET_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_SET_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_SET_VALUES_SHIFT)) & BCH_DBGAHBMREAD_SET_VALUES_MASK) + +/*! @name DBGAHBMREAD_CLR - Bus Master and ECC Controller Debug Read Register */ +#define BCH_DBGAHBMREAD_CLR_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_CLR_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_CLR_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_CLR_VALUES_SHIFT)) & BCH_DBGAHBMREAD_CLR_VALUES_MASK) + +/*! @name DBGAHBMREAD_TOG - Bus Master and ECC Controller Debug Read Register */ +#define BCH_DBGAHBMREAD_TOG_VALUES_MASK (0xFFFFFFFFU) +#define BCH_DBGAHBMREAD_TOG_VALUES_SHIFT (0U) +#define BCH_DBGAHBMREAD_TOG_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_TOG_VALUES_SHIFT)) & BCH_DBGAHBMREAD_TOG_VALUES_MASK) + +/*! @name BLOCKNAME - Block Name Register */ +#define BCH_BLOCKNAME_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK) + +/*! @name BLOCKNAME_SET - Block Name Register */ +#define BCH_BLOCKNAME_SET_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_SET_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_SET_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_SET_NAME_SHIFT)) & BCH_BLOCKNAME_SET_NAME_MASK) + +/*! @name BLOCKNAME_CLR - Block Name Register */ +#define BCH_BLOCKNAME_CLR_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_CLR_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_CLR_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_CLR_NAME_SHIFT)) & BCH_BLOCKNAME_CLR_NAME_MASK) + +/*! @name BLOCKNAME_TOG - Block Name Register */ +#define BCH_BLOCKNAME_TOG_NAME_MASK (0xFFFFFFFFU) +#define BCH_BLOCKNAME_TOG_NAME_SHIFT (0U) +#define BCH_BLOCKNAME_TOG_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_TOG_NAME_SHIFT)) & BCH_BLOCKNAME_TOG_NAME_MASK) + +/*! @name VERSION - BCH Version Register */ +#define BCH_VERSION_STEP_MASK (0xFFFFU) +#define BCH_VERSION_STEP_SHIFT (0U) +#define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK) +#define BCH_VERSION_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_MINOR_SHIFT (16U) +#define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK) +#define BCH_VERSION_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_MAJOR_SHIFT (24U) +#define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK) + +/*! @name VERSION_SET - BCH Version Register */ +#define BCH_VERSION_SET_STEP_MASK (0xFFFFU) +#define BCH_VERSION_SET_STEP_SHIFT (0U) +#define BCH_VERSION_SET_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_STEP_SHIFT)) & BCH_VERSION_SET_STEP_MASK) +#define BCH_VERSION_SET_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_SET_MINOR_SHIFT (16U) +#define BCH_VERSION_SET_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_MINOR_SHIFT)) & BCH_VERSION_SET_MINOR_MASK) +#define BCH_VERSION_SET_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_SET_MAJOR_SHIFT (24U) +#define BCH_VERSION_SET_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_SET_MAJOR_SHIFT)) & BCH_VERSION_SET_MAJOR_MASK) + +/*! @name VERSION_CLR - BCH Version Register */ +#define BCH_VERSION_CLR_STEP_MASK (0xFFFFU) +#define BCH_VERSION_CLR_STEP_SHIFT (0U) +#define BCH_VERSION_CLR_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_STEP_SHIFT)) & BCH_VERSION_CLR_STEP_MASK) +#define BCH_VERSION_CLR_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_CLR_MINOR_SHIFT (16U) +#define BCH_VERSION_CLR_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_MINOR_SHIFT)) & BCH_VERSION_CLR_MINOR_MASK) +#define BCH_VERSION_CLR_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_CLR_MAJOR_SHIFT (24U) +#define BCH_VERSION_CLR_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_CLR_MAJOR_SHIFT)) & BCH_VERSION_CLR_MAJOR_MASK) + +/*! @name VERSION_TOG - BCH Version Register */ +#define BCH_VERSION_TOG_STEP_MASK (0xFFFFU) +#define BCH_VERSION_TOG_STEP_SHIFT (0U) +#define BCH_VERSION_TOG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_STEP_SHIFT)) & BCH_VERSION_TOG_STEP_MASK) +#define BCH_VERSION_TOG_MINOR_MASK (0xFF0000U) +#define BCH_VERSION_TOG_MINOR_SHIFT (16U) +#define BCH_VERSION_TOG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_MINOR_SHIFT)) & BCH_VERSION_TOG_MINOR_MASK) +#define BCH_VERSION_TOG_MAJOR_MASK (0xFF000000U) +#define BCH_VERSION_TOG_MAJOR_SHIFT (24U) +#define BCH_VERSION_TOG_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_TOG_MAJOR_SHIFT)) & BCH_VERSION_TOG_MAJOR_MASK) + +/*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */ +#define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_RSVD_SHIFT (9U) +#define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK) +#define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT (31U) +#define BCH_DEBUG1_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK) + +/*! @name DEBUG1_SET - Hardware BCH ECC Debug Register 1 */ +#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_SET_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_SET_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_SET_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_SET_RSVD_SHIFT (9U) +#define BCH_DEBUG1_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_RSVD_SHIFT)) & BCH_DEBUG1_SET_RSVD_MASK) +#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK_SHIFT (31U) +#define BCH_DEBUG1_SET_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_SET_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_SET_DEBUG1_PREERASECHK_MASK) + +/*! @name DEBUG1_CLR - Hardware BCH ECC Debug Register 1 */ +#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_CLR_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_CLR_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_CLR_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_CLR_RSVD_SHIFT (9U) +#define BCH_DEBUG1_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_RSVD_SHIFT)) & BCH_DEBUG1_CLR_RSVD_MASK) +#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_SHIFT (31U) +#define BCH_DEBUG1_CLR_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_CLR_DEBUG1_PREERASECHK_MASK) + +/*! @name DEBUG1_TOG - Hardware BCH ECC Debug Register 1 */ +#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK (0x1FFU) +#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT (0U) +#define BCH_DEBUG1_TOG_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_TOG_ERASED_ZERO_COUNT_MASK) +#define BCH_DEBUG1_TOG_RSVD_MASK (0x7FFFFE00U) +#define BCH_DEBUG1_TOG_RSVD_SHIFT (9U) +#define BCH_DEBUG1_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_RSVD_SHIFT)) & BCH_DEBUG1_TOG_RSVD_MASK) +#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_MASK (0x80000000U) +#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_SHIFT (31U) +#define BCH_DEBUG1_TOG_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_TOG_DEBUG1_PREERASECHK_MASK) + + +/*! + * @} + */ /* end of group BCH_Register_Masks */ + + +/* BCH - Peripheral instance base addresses */ +/** Peripheral BCH base address */ +#define BCH_BASE (0x1808000u) +/** Peripheral BCH base pointer */ +#define BCH ((BCH_Type *)BCH_BASE) +/** Array initializer of BCH peripheral base addresses */ +#define BCH_BASE_ADDRS { BCH_BASE } +/** Array initializer of BCH peripheral base pointers */ +#define BCH_BASE_PTRS { BCH } +/** Interrupt vectors for the BCH peripheral type */ +#define BCH_IRQS { RAWNAND_BCH_IRQn } + +/*! + * @} + */ /* end of group BCH_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free Running Timer Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ + __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ + __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ + __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */ + __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ + uint8_t RESERVED_1[8]; + __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */ + __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */ + uint8_t RESERVED_2[48]; + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ + __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ + } MB[64]; + uint8_t RESERVED_3[1024]; + __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_4[96]; + __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +#define CAN_MCR_MAXMB_MASK (0x7FU) +#define CAN_MCR_MAXMB_SHIFT (0U) +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) +#define CAN_MCR_IDAM_MASK (0x300U) +#define CAN_MCR_IDAM_SHIFT (8U) +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) +#define CAN_MCR_AEN_MASK (0x1000U) +#define CAN_MCR_AEN_SHIFT (12U) +#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) +#define CAN_MCR_LPRIOEN_MASK (0x2000U) +#define CAN_MCR_LPRIOEN_SHIFT (13U) +#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) +#define CAN_MCR_IRMQ_MASK (0x10000U) +#define CAN_MCR_IRMQ_SHIFT (16U) +#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) +#define CAN_MCR_SRXDIS_MASK (0x20000U) +#define CAN_MCR_SRXDIS_SHIFT (17U) +#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) +#define CAN_MCR_WAKSRC_MASK (0x80000U) +#define CAN_MCR_WAKSRC_SHIFT (19U) +#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) +#define CAN_MCR_LPMACK_MASK (0x100000U) +#define CAN_MCR_LPMACK_SHIFT (20U) +#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) +#define CAN_MCR_WRNEN_MASK (0x200000U) +#define CAN_MCR_WRNEN_SHIFT (21U) +#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) +#define CAN_MCR_SLFWAK_MASK (0x400000U) +#define CAN_MCR_SLFWAK_SHIFT (22U) +#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) +#define CAN_MCR_SUPV_MASK (0x800000U) +#define CAN_MCR_SUPV_SHIFT (23U) +#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) +#define CAN_MCR_FRZACK_MASK (0x1000000U) +#define CAN_MCR_FRZACK_SHIFT (24U) +#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) +#define CAN_MCR_SOFTRST_MASK (0x2000000U) +#define CAN_MCR_SOFTRST_SHIFT (25U) +#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) +#define CAN_MCR_WAKMSK_MASK (0x4000000U) +#define CAN_MCR_WAKMSK_SHIFT (26U) +#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) +#define CAN_MCR_NOTRDY_MASK (0x8000000U) +#define CAN_MCR_NOTRDY_SHIFT (27U) +#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) +#define CAN_MCR_HALT_MASK (0x10000000U) +#define CAN_MCR_HALT_SHIFT (28U) +#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) +#define CAN_MCR_RFEN_MASK (0x20000000U) +#define CAN_MCR_RFEN_SHIFT (29U) +#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) +#define CAN_MCR_FRZ_MASK (0x40000000U) +#define CAN_MCR_FRZ_SHIFT (30U) +#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) +#define CAN_MCR_MDIS_MASK (0x80000000U) +#define CAN_MCR_MDIS_SHIFT (31U) +#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) + +/*! @name CTRL1 - Control 1 Register */ +#define CAN_CTRL1_PROPSEG_MASK (0x7U) +#define CAN_CTRL1_PROPSEG_SHIFT (0U) +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) +#define CAN_CTRL1_LOM_MASK (0x8U) +#define CAN_CTRL1_LOM_SHIFT (3U) +#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) +#define CAN_CTRL1_LBUF_MASK (0x10U) +#define CAN_CTRL1_LBUF_SHIFT (4U) +#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) +#define CAN_CTRL1_TSYN_MASK (0x20U) +#define CAN_CTRL1_TSYN_SHIFT (5U) +#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) +#define CAN_CTRL1_BOFFREC_MASK (0x40U) +#define CAN_CTRL1_BOFFREC_SHIFT (6U) +#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) +#define CAN_CTRL1_SMP_MASK (0x80U) +#define CAN_CTRL1_SMP_SHIFT (7U) +#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) +#define CAN_CTRL1_RWRNMSK_MASK (0x400U) +#define CAN_CTRL1_RWRNMSK_SHIFT (10U) +#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) +#define CAN_CTRL1_TWRNMSK_MASK (0x800U) +#define CAN_CTRL1_TWRNMSK_SHIFT (11U) +#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) +#define CAN_CTRL1_LPB_MASK (0x1000U) +#define CAN_CTRL1_LPB_SHIFT (12U) +#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) +#define CAN_CTRL1_ERRMSK_MASK (0x4000U) +#define CAN_CTRL1_ERRMSK_SHIFT (14U) +#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) +#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) +#define CAN_CTRL1_BOFFMSK_SHIFT (15U) +#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) +#define CAN_CTRL1_PSEG2_MASK (0x70000U) +#define CAN_CTRL1_PSEG2_SHIFT (16U) +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) +#define CAN_CTRL1_PSEG1_MASK (0x380000U) +#define CAN_CTRL1_PSEG1_SHIFT (19U) +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) +#define CAN_CTRL1_RJW_MASK (0xC00000U) +#define CAN_CTRL1_RJW_SHIFT (22U) +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) +#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) +#define CAN_CTRL1_PRESDIV_SHIFT (24U) +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) + +/*! @name TIMER - Free Running Timer Register */ +#define CAN_TIMER_TIMER_MASK (0xFFFFU) +#define CAN_TIMER_TIMER_SHIFT (0U) +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) + +/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) +#define CAN_RXMGMASK_MG_SHIFT (0U) +#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) + +/*! @name RX14MASK - Rx Buffer 14 Mask Register */ +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) +#define CAN_RX14MASK_RX14M_SHIFT (0U) +#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) + +/*! @name RX15MASK - Rx Buffer 15 Mask Register */ +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) +#define CAN_RX15MASK_RX15M_SHIFT (0U) +#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) + +/*! @name ECR - Error Counter Register */ +#define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU) +#define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U) +#define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK) +#define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U) +#define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U) +#define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK) + +/*! @name ESR1 - Error and Status 1 Register */ +#define CAN_ESR1_WAKINT_MASK (0x1U) +#define CAN_ESR1_WAKINT_SHIFT (0U) +#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) +#define CAN_ESR1_ERRINT_MASK (0x2U) +#define CAN_ESR1_ERRINT_SHIFT (1U) +#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) +#define CAN_ESR1_BOFFINT_MASK (0x4U) +#define CAN_ESR1_BOFFINT_SHIFT (2U) +#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) +#define CAN_ESR1_RX_MASK (0x8U) +#define CAN_ESR1_RX_SHIFT (3U) +#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) +#define CAN_ESR1_FLTCONF_MASK (0x30U) +#define CAN_ESR1_FLTCONF_SHIFT (4U) +#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) +#define CAN_ESR1_TX_MASK (0x40U) +#define CAN_ESR1_TX_SHIFT (6U) +#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) +#define CAN_ESR1_IDLE_MASK (0x80U) +#define CAN_ESR1_IDLE_SHIFT (7U) +#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) +#define CAN_ESR1_RXWRN_MASK (0x100U) +#define CAN_ESR1_RXWRN_SHIFT (8U) +#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) +#define CAN_ESR1_TXWRN_MASK (0x200U) +#define CAN_ESR1_TXWRN_SHIFT (9U) +#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) +#define CAN_ESR1_STFERR_MASK (0x400U) +#define CAN_ESR1_STFERR_SHIFT (10U) +#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) +#define CAN_ESR1_FRMERR_MASK (0x800U) +#define CAN_ESR1_FRMERR_SHIFT (11U) +#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) +#define CAN_ESR1_CRCERR_MASK (0x1000U) +#define CAN_ESR1_CRCERR_SHIFT (12U) +#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) +#define CAN_ESR1_ACKERR_MASK (0x2000U) +#define CAN_ESR1_ACKERR_SHIFT (13U) +#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) +#define CAN_ESR1_BIT0ERR_MASK (0x4000U) +#define CAN_ESR1_BIT0ERR_SHIFT (14U) +#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) +#define CAN_ESR1_BIT1ERR_MASK (0x8000U) +#define CAN_ESR1_BIT1ERR_SHIFT (15U) +#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) +#define CAN_ESR1_RWRNINT_MASK (0x10000U) +#define CAN_ESR1_RWRNINT_SHIFT (16U) +#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) +#define CAN_ESR1_TWRNINT_MASK (0x20000U) +#define CAN_ESR1_TWRNINT_SHIFT (17U) +#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) +#define CAN_ESR1_SYNCH_MASK (0x40000U) +#define CAN_ESR1_SYNCH_SHIFT (18U) +#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) + +/*! @name IMASK2 - Interrupt Masks 2 Register */ +#define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU) +#define CAN_IMASK2_BUFHM_SHIFT (0U) +#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK) + +/*! @name IMASK1 - Interrupt Masks 1 Register */ +#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUFLM_SHIFT (0U) +#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) + +/*! @name IFLAG2 - Interrupt Flags 2 Register */ +#define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU) +#define CAN_IFLAG2_BUFHI_SHIFT (0U) +#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK) + +/*! @name IFLAG1 - Interrupt Flags 1 Register */ +#define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU) +#define CAN_IFLAG1_BUF4TO0I_SHIFT (0U) +#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK) +#define CAN_IFLAG1_BUF5I_MASK (0x20U) +#define CAN_IFLAG1_BUF5I_SHIFT (5U) +#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) +#define CAN_IFLAG1_BUF6I_MASK (0x40U) +#define CAN_IFLAG1_BUF6I_SHIFT (6U) +#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) +#define CAN_IFLAG1_BUF7I_MASK (0x80U) +#define CAN_IFLAG1_BUF7I_SHIFT (7U) +#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) + +/*! @name CTRL2 - Control 2 Register */ +#define CAN_CTRL2_EACEN_MASK (0x10000U) +#define CAN_CTRL2_EACEN_SHIFT (16U) +#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) +#define CAN_CTRL2_RRS_MASK (0x20000U) +#define CAN_CTRL2_RRS_SHIFT (17U) +#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) +#define CAN_CTRL2_MRP_MASK (0x40000U) +#define CAN_CTRL2_MRP_SHIFT (18U) +#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) +#define CAN_CTRL2_TASD_MASK (0xF80000U) +#define CAN_CTRL2_TASD_SHIFT (19U) +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) +#define CAN_CTRL2_RFFN_MASK (0xF000000U) +#define CAN_CTRL2_RFFN_SHIFT (24U) +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) +#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) +#define CAN_CTRL2_WRMFRZ_SHIFT (28U) +#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) + +/*! @name ESR2 - Error and Status 2 Register */ +#define CAN_ESR2_IMB_MASK (0x2000U) +#define CAN_ESR2_IMB_SHIFT (13U) +#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) +#define CAN_ESR2_VPS_MASK (0x4000U) +#define CAN_ESR2_VPS_SHIFT (14U) +#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) +#define CAN_ESR2_LPTM_MASK (0x7F0000U) +#define CAN_ESR2_LPTM_SHIFT (16U) +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) + +/*! @name CRCR - CRC Register */ +#define CAN_CRCR_TXCRC_MASK (0x7FFFU) +#define CAN_CRCR_TXCRC_SHIFT (0U) +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) +#define CAN_CRCR_MBCRC_MASK (0x7F0000U) +#define CAN_CRCR_MBCRC_SHIFT (16U) +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) + +/*! @name RXFGMASK - Rx FIFO Global Mask Register */ +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) +#define CAN_RXFGMASK_FGM_SHIFT (0U) +#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) + +/*! @name RXFIR - Rx FIFO Information Register */ +#define CAN_RXFIR_IDHIT_MASK (0x1FFU) +#define CAN_RXFIR_IDHIT_SHIFT (0U) +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) + +/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */ +#define CAN_CS_TIME_STAMP_MASK (0xFFFFU) +#define CAN_CS_TIME_STAMP_SHIFT (0U) +#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) +#define CAN_CS_DLC_MASK (0xF0000U) +#define CAN_CS_DLC_SHIFT (16U) +#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) +#define CAN_CS_RTR_MASK (0x100000U) +#define CAN_CS_RTR_SHIFT (20U) +#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) +#define CAN_CS_IDE_MASK (0x200000U) +#define CAN_CS_IDE_SHIFT (21U) +#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) +#define CAN_CS_SRR_MASK (0x400000U) +#define CAN_CS_SRR_SHIFT (22U) +#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) +#define CAN_CS_CODE_MASK (0xF000000U) +#define CAN_CS_CODE_SHIFT (24U) +#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT (64U) + +/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */ +#define CAN_ID_EXT_MASK (0x3FFFFU) +#define CAN_ID_EXT_SHIFT (0U) +#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) +#define CAN_ID_STD_MASK (0x1FFC0000U) +#define CAN_ID_STD_SHIFT (18U) +#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) +#define CAN_ID_PRIO_MASK (0xE0000000U) +#define CAN_ID_PRIO_SHIFT (29U) +#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT (64U) + +/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */ +#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) +#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) +#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) +#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) +#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) +#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) +#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) +#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) + +/* The count of CAN_WORD0 */ +#define CAN_WORD0_COUNT (64U) + +/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */ +#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) +#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) +#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) +#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) +#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) +#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) +#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) +#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) + +/* The count of CAN_WORD1 */ +#define CAN_WORD1_COUNT (64U) + +/*! @name RXIMR - Rx Individual Mask Registers */ +#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) +#define CAN_RXIMR_MI_SHIFT (0U) +#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) + +/* The count of CAN_RXIMR */ +#define CAN_RXIMR_COUNT (64U) + +/*! @name GFWR - Glitch Filter Width Registers */ +#define CAN_GFWR_GFWR_MASK (0xFFU) +#define CAN_GFWR_GFWR_SHIFT (0U) +#define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK) + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN1 base address */ +#define CAN1_BASE (0x2090000u) +/** Peripheral CAN1 base pointer */ +#define CAN1 ((CAN_Type *)CAN1_BASE) +/** Peripheral CAN2 base address */ +#define CAN2_BASE (0x2094000u) +/** Peripheral CAN2 base pointer */ +#define CAN2 ((CAN_Type *)CAN2_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn } +/* Backward compatibility */ +#define CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASK +#define CAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFT +#define CAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x) +#define CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASK +#define CAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFT +#define CAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x) + + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer + * @{ + */ + +/** CCM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */ + __IO uint32_t CCDR; /**< CCM Control Divider Register, offset: 0x4 */ + __I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */ + __IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */ + __IO uint32_t CACRR; /**< CCM Arm Clock Root Register, offset: 0x10 */ + __IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */ + __IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */ + __IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */ + __IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */ + __IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */ + __IO uint32_t CS1CDR; /**< CCM SAI1 Clock Divider Register, offset: 0x28 */ + __IO uint32_t CS2CDR; /**< CCM SAI2 Clock Divider Register, offset: 0x2C */ + __IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */ + __IO uint32_t CHSCCDR; /**< CCM HSC Clock Divider Register, offset: 0x34 */ + __IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */ + __IO uint32_t CSCDR3; /**< CCM Serial Clock Divider Register 3, offset: 0x3C */ + uint8_t RESERVED_0[8]; + __I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */ + uint8_t RESERVED_1[8]; + __IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */ + __IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */ + __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ + __IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */ + __IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */ + __IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */ + __IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */ + __IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */ + __IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */ + __IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */ + __IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */ + __IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */ + uint8_t RESERVED_2[4]; + __IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */ +} CCM_Type; + +/* ---------------------------------------------------------------------------- + -- CCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Masks CCM Register Masks + * @{ + */ + +/*! @name CCR - CCM Control Register */ +#define CCM_CCR_OSCNT_MASK (0x7FU) +#define CCM_CCR_OSCNT_SHIFT (0U) +#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK) +#define CCM_CCR_COSC_EN_MASK (0x1000U) +#define CCM_CCR_COSC_EN_SHIFT (12U) +#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK) +#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U) +#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U) +#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK) +#define CCM_CCR_RBC_EN_MASK (0x8000000U) +#define CCM_CCR_RBC_EN_SHIFT (27U) +#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK) + +/*! @name CCDR - CCM Control Divider Register */ +#define CCM_CCDR_MMDC_CH1_MASK_MASK (0x10000U) +#define CCM_CCDR_MMDC_CH1_MASK_SHIFT (16U) +#define CCM_CCDR_MMDC_CH1_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCDR_MMDC_CH1_MASK_SHIFT)) & CCM_CCDR_MMDC_CH1_MASK_MASK) +#define CCM_CCDR_MMDC_CH0_MASK_MASK (0x20000U) +#define CCM_CCDR_MMDC_CH0_MASK_SHIFT (17U) +#define CCM_CCDR_MMDC_CH0_MASK(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCDR_MMDC_CH0_MASK_SHIFT)) & CCM_CCDR_MMDC_CH0_MASK_MASK) + +/*! @name CSR - CCM Status Register */ +#define CCM_CSR_REF_EN_B_MASK (0x1U) +#define CCM_CSR_REF_EN_B_SHIFT (0U) +#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK) +#define CCM_CSR_COSC_READY_MASK (0x20U) +#define CCM_CSR_COSC_READY_SHIFT (5U) +#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK) + +/*! @name CCSR - CCM Clock Switcher Register */ +#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U) +#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U) +#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK) +#define CCM_CCSR_PLL1_SW_CLK_SEL_MASK (0x4U) +#define CCM_CCSR_PLL1_SW_CLK_SEL_SHIFT (2U) +#define CCM_CCSR_PLL1_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL1_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL1_SW_CLK_SEL_MASK) +#define CCM_CCSR_SECONDARY_CLK_SEL_MASK (0x8U) +#define CCM_CCSR_SECONDARY_CLK_SEL_SHIFT (3U) +#define CCM_CCSR_SECONDARY_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_SECONDARY_CLK_SEL_SHIFT)) & CCM_CCSR_SECONDARY_CLK_SEL_MASK) +#define CCM_CCSR_STEP_SEL_MASK (0x100U) +#define CCM_CCSR_STEP_SEL_SHIFT (8U) +#define CCM_CCSR_STEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_STEP_SEL_SHIFT)) & CCM_CCSR_STEP_SEL_MASK) + +/*! @name CACRR - CCM Arm Clock Root Register */ +#define CCM_CACRR_ARM_PODF_MASK (0x7U) +#define CCM_CACRR_ARM_PODF_SHIFT (0U) +#define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK) + +/*! @name CBCDR - CCM Bus Clock Divider Register */ +#define CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7U) +#define CCM_CBCDR_PERIPH2_CLK2_PODF_SHIFT (0U) +#define CCM_CBCDR_PERIPH2_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH2_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) +#define CCM_CBCDR_FABRIC_MMDC_PODF_MASK (0x38U) +#define CCM_CBCDR_FABRIC_MMDC_PODF_SHIFT (3U) +#define CCM_CBCDR_FABRIC_MMDC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_FABRIC_MMDC_PODF_SHIFT)) & CCM_CBCDR_FABRIC_MMDC_PODF_MASK) +#define CCM_CBCDR_AXI_SEL_MASK (0x40U) +#define CCM_CBCDR_AXI_SEL_SHIFT (6U) +#define CCM_CBCDR_AXI_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AXI_SEL_SHIFT)) & CCM_CBCDR_AXI_SEL_MASK) +#define CCM_CBCDR_AXI_ALT_SEL_MASK (0x80U) +#define CCM_CBCDR_AXI_ALT_SEL_SHIFT (7U) +#define CCM_CBCDR_AXI_ALT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AXI_ALT_SEL_SHIFT)) & CCM_CBCDR_AXI_ALT_SEL_MASK) +#define CCM_CBCDR_IPG_PODF_MASK (0x300U) +#define CCM_CBCDR_IPG_PODF_SHIFT (8U) +#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK) +#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U) +#define CCM_CBCDR_AHB_PODF_SHIFT (10U) +#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK) +#define CCM_CBCDR_AXI_PODF_MASK (0x70000U) +#define CCM_CBCDR_AXI_PODF_SHIFT (16U) +#define CCM_CBCDR_AXI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AXI_PODF_SHIFT)) & CCM_CBCDR_AXI_PODF_MASK) +#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U) +#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U) +#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK) +#define CCM_CBCDR_PERIPH2_CLK_SEL_MASK (0x4000000U) +#define CCM_CBCDR_PERIPH2_CLK_SEL_SHIFT (26U) +#define CCM_CBCDR_PERIPH2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH2_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH2_CLK_SEL_MASK) +#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U) +#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U) +#define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) + +/*! @name CBCMR - CCM Bus Clock Multiplexer Register */ +#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U) +#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U) +#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) +#define CCM_CBCMR_PERIPH2_CLK2_SEL_MASK (0x100000U) +#define CCM_CBCMR_PERIPH2_CLK2_SEL_SHIFT (20U) +#define CCM_CBCMR_PERIPH2_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH2_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH2_CLK2_SEL_MASK) +#define CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x600000U) +#define CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT (21U) +#define CCM_CBCMR_PRE_PERIPH2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH2_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) +#define CCM_CBCMR_LCDIF1_PODF_MASK (0x3800000U) +#define CCM_CBCMR_LCDIF1_PODF_SHIFT (23U) +#define CCM_CBCMR_LCDIF1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF1_PODF_SHIFT)) & CCM_CBCMR_LCDIF1_PODF_MASK) + +/*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */ +#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU) +#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U) +#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK) +#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U) +#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U) +#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) +#define CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x380U) +#define CCM_CSCMR1_QSPI1_CLK_SEL_SHIFT (7U) +#define CCM_CSCMR1_QSPI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_QSPI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_QSPI1_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U) +#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U) +#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U) +#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U) +#define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U) +#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U) +#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK) +#define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U) +#define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U) +#define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK) +#define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U) +#define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U) +#define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK) +#define CCM_CSCMR1_BCH_CLK_SEL_MASK (0x40000U) +#define CCM_CSCMR1_BCH_CLK_SEL_SHIFT (18U) +#define CCM_CSCMR1_BCH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_BCH_CLK_SEL_SHIFT)) & CCM_CSCMR1_BCH_CLK_SEL_MASK) +#define CCM_CSCMR1_GPMI_CLK_SEL_MASK (0x80000U) +#define CCM_CSCMR1_GPMI_CLK_SEL_SHIFT (19U) +#define CCM_CSCMR1_GPMI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_GPMI_CLK_SEL_SHIFT)) & CCM_CSCMR1_GPMI_CLK_SEL_MASK) +#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF_MASK (0x3800000U) +#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF_SHIFT (23U) +#define CCM_CSCMR1_ACLK_EIM_SLOW_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_ACLK_EIM_SLOW_PODF_SHIFT)) & CCM_CSCMR1_ACLK_EIM_SLOW_PODF_MASK) +#define CCM_CSCMR1_QSPI1_PODF_MASK (0x1C000000U) +#define CCM_CSCMR1_QSPI1_PODF_SHIFT (26U) +#define CCM_CSCMR1_QSPI1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_QSPI1_PODF_SHIFT)) & CCM_CSCMR1_QSPI1_PODF_MASK) +#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL_MASK (0x60000000U) +#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL_SHIFT (29U) +#define CCM_CSCMR1_ACLK_EIM_SLOW_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_ACLK_EIM_SLOW_SEL_SHIFT)) & CCM_CSCMR1_ACLK_EIM_SLOW_SEL_MASK) + +/*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */ +#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU) +#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U) +#define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK) +#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U) +#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U) +#define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK) +#define CCM_CSCMR2_LDB_DI0_DIV_MASK (0x400U) +#define CCM_CSCMR2_LDB_DI0_DIV_SHIFT (10U) +#define CCM_CSCMR2_LDB_DI0_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_LDB_DI0_DIV_SHIFT)) & CCM_CSCMR2_LDB_DI0_DIV_MASK) +#define CCM_CSCMR2_LDB_DI1_DIV_MASK (0x800U) +#define CCM_CSCMR2_LDB_DI1_DIV_SHIFT (11U) +#define CCM_CSCMR2_LDB_DI1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_LDB_DI1_DIV_SHIFT)) & CCM_CSCMR2_LDB_DI1_DIV_MASK) +#define CCM_CSCMR2_ESAI_CLK_SEL_MASK (0x180000U) +#define CCM_CSCMR2_ESAI_CLK_SEL_SHIFT (19U) +#define CCM_CSCMR2_ESAI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_ESAI_CLK_SEL_SHIFT)) & CCM_CSCMR2_ESAI_CLK_SEL_MASK) +#define CCM_CSCMR2_VID_CLK_SEL_MASK (0xE00000U) +#define CCM_CSCMR2_VID_CLK_SEL_SHIFT (21U) +#define CCM_CSCMR2_VID_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_VID_CLK_SEL_SHIFT)) & CCM_CSCMR2_VID_CLK_SEL_MASK) +#define CCM_CSCMR2_VID_CLK_PRE_PODF_MASK (0x3000000U) +#define CCM_CSCMR2_VID_CLK_PRE_PODF_SHIFT (24U) +#define CCM_CSCMR2_VID_CLK_PRE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_VID_CLK_PRE_PODF_SHIFT)) & CCM_CSCMR2_VID_CLK_PRE_PODF_MASK) +#define CCM_CSCMR2_VID_CLK_PODF_MASK (0x1C000000U) +#define CCM_CSCMR2_VID_CLK_PODF_SHIFT (26U) +#define CCM_CSCMR2_VID_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_VID_CLK_PODF_SHIFT)) & CCM_CSCMR2_VID_CLK_PODF_MASK) + +/*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */ +#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU) +#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U) +#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK) +#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U) +#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U) +#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK) +#define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U) +#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U) +#define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK) +#define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U) +#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U) +#define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK) +#define CCM_CSCDR1_BCH_PODF_MASK (0x380000U) +#define CCM_CSCDR1_BCH_PODF_SHIFT (19U) +#define CCM_CSCDR1_BCH_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_BCH_PODF_SHIFT)) & CCM_CSCDR1_BCH_PODF_MASK) +#define CCM_CSCDR1_GPMI_PODF_MASK (0x1C00000U) +#define CCM_CSCDR1_GPMI_PODF_SHIFT (22U) +#define CCM_CSCDR1_GPMI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_GPMI_PODF_SHIFT)) & CCM_CSCDR1_GPMI_PODF_MASK) + +/*! @name CS1CDR - CCM SAI1 Clock Divider Register */ +#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU) +#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U) +#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK) +#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U) +#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U) +#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK) +#define CCM_CS1CDR_ESAI_CLK_PRED_MASK (0xE00U) +#define CCM_CS1CDR_ESAI_CLK_PRED_SHIFT (9U) +#define CCM_CS1CDR_ESAI_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_ESAI_CLK_PRED_SHIFT)) & CCM_CS1CDR_ESAI_CLK_PRED_MASK) +#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U) +#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U) +#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK) +#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U) +#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U) +#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK) +#define CCM_CS1CDR_ESAI_CLK_PODF_MASK (0xE000000U) +#define CCM_CS1CDR_ESAI_CLK_PODF_SHIFT (25U) +#define CCM_CS1CDR_ESAI_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_ESAI_CLK_PODF_SHIFT)) & CCM_CS1CDR_ESAI_CLK_PODF_MASK) + +/*! @name CS2CDR - CCM SAI2 Clock Divider Register */ +#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU) +#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U) +#define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK) +#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U) +#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U) +#define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK) +#define CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0xE00U) +#define CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT (9U) +#define CCM_CS2CDR_LDB_DI0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_LDB_DI0_CLK_SEL_SHIFT)) & CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK) +#define CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x38000U) +#define CCM_CS2CDR_ENFC_CLK_SEL_SHIFT (15U) +#define CCM_CS2CDR_ENFC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_ENFC_CLK_SEL_SHIFT)) & CCM_CS2CDR_ENFC_CLK_SEL_MASK) +#define CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x1C0000U) +#define CCM_CS2CDR_ENFC_CLK_PRED_SHIFT (18U) +#define CCM_CS2CDR_ENFC_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_ENFC_CLK_PRED_SHIFT)) & CCM_CS2CDR_ENFC_CLK_PRED_MASK) +#define CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x7E00000U) +#define CCM_CS2CDR_ENFC_CLK_PODF_SHIFT (21U) +#define CCM_CS2CDR_ENFC_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_ENFC_CLK_PODF_SHIFT)) & CCM_CS2CDR_ENFC_CLK_PODF_MASK) + +/*! @name CDCDR - CCM D1 Clock Divider Register */ +#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U) +#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U) +#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK) +#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U) +#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U) +#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK) +#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U) +#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U) +#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK) + +/*! @name CHSCCDR - CCM HSC Clock Divider Register */ +#define CCM_CHSCCDR_EPDC_CLK_SEL_MASK (0xE00U) +#define CCM_CHSCCDR_EPDC_CLK_SEL_SHIFT (9U) +#define CCM_CHSCCDR_EPDC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CHSCCDR_EPDC_CLK_SEL_SHIFT)) & CCM_CHSCCDR_EPDC_CLK_SEL_MASK) +#define CCM_CHSCCDR_EPDC_PODF_MASK (0x7000U) +#define CCM_CHSCCDR_EPDC_PODF_SHIFT (12U) +#define CCM_CHSCCDR_EPDC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CHSCCDR_EPDC_PODF_SHIFT)) & CCM_CHSCCDR_EPDC_PODF_MASK) +#define CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x38000U) +#define CCM_CHSCCDR_EPDC_PRE_CLK_SEL_SHIFT (15U) +#define CCM_CHSCCDR_EPDC_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CHSCCDR_EPDC_PRE_CLK_SEL_SHIFT)) & CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK) + +/*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */ +#define CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0xE00U) +#define CCM_CSCDR2_LCDIF1_CLK_SEL_SHIFT (9U) +#define CCM_CSCDR2_LCDIF1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF1_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) +#define CCM_CSCDR2_LCDIF1_PRED_MASK (0x7000U) +#define CCM_CSCDR2_LCDIF1_PRED_SHIFT (12U) +#define CCM_CSCDR2_LCDIF1_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF1_PRED_SHIFT)) & CCM_CSCDR2_LCDIF1_PRED_MASK) +#define CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_MASK (0x38000U) +#define CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_SHIFT (15U) +#define CCM_CSCDR2_LCDIF1_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF1_PRE_CLK_SEL_MASK) +#define CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x40000U) +#define CCM_CSCDR2_ECSPI_CLK_SEL_SHIFT (18U) +#define CCM_CSCDR2_ECSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_ECSPI_CLK_SEL_SHIFT)) & CCM_CSCDR2_ECSPI_CLK_SEL_MASK) +#define CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x1F80000U) +#define CCM_CSCDR2_ECSPI_CLK_PODF_SHIFT (19U) +#define CCM_CSCDR2_ECSPI_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_ECSPI_CLK_PODF_SHIFT)) & CCM_CSCDR2_ECSPI_CLK_PODF_MASK) + +/*! @name CSCDR3 - CCM Serial Clock Divider Register 3 */ +#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U) +#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U) +#define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK) +#define CCM_CSCDR3_CSI_PODF_MASK (0x3800U) +#define CCM_CSCDR3_CSI_PODF_SHIFT (11U) +#define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK) + +/*! @name CDHIPR - CCM Divider Handshake In-Process Register */ +#define CCM_CDHIPR_AXI_PODF_BUSY_MASK (0x1U) +#define CCM_CDHIPR_AXI_PODF_BUSY_SHIFT (0U) +#define CCM_CDHIPR_AXI_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AXI_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AXI_PODF_BUSY_MASK) +#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U) +#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U) +#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK) +#define CCM_CDHIPR_MMDC_PODF_BUSY_MASK (0x4U) +#define CCM_CDHIPR_MMDC_PODF_BUSY_SHIFT (2U) +#define CCM_CDHIPR_MMDC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_MMDC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_MMDC_PODF_BUSY_MASK) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK) +#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U) +#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U) +#define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK) + +/*! @name CLPCR - CCM Low Power Control Register */ +#define CCM_CLPCR_LPM_MASK (0x3U) +#define CCM_CLPCR_LPM_SHIFT (0U) +#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK) +#define CCM_CLPCR_SBYOS_MASK (0x40U) +#define CCM_CLPCR_SBYOS_SHIFT (6U) +#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK) +#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U) +#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U) +#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK) +#define CCM_CLPCR_VSTBY_MASK (0x100U) +#define CCM_CLPCR_VSTBY_SHIFT (8U) +#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK) +#define CCM_CLPCR_STBY_COUNT_MASK (0x600U) +#define CCM_CLPCR_STBY_COUNT_SHIFT (9U) +#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK) +#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U) +#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U) +#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK) +#define CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS_MASK (0x80000U) +#define CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS_SHIFT (19U) +#define CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS_SHIFT)) & CCM_CLPCR_BYPASS_MMDC_CH0_LPM_HS_MASK) +#define CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS_MASK (0x200000U) +#define CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS_SHIFT (21U) +#define CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS_SHIFT)) & CCM_CLPCR_BYPASS_MMDC_CH1_LPM_HS_MASK) +#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U) +#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U) +#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK) +#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U) +#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U) +#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK) +#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U) +#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U) +#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK) + +/*! @name CISR - CCM Interrupt Status Register */ +#define CCM_CISR_LRF_PLL_MASK (0x1U) +#define CCM_CISR_LRF_PLL_SHIFT (0U) +#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK) +#define CCM_CISR_COSC_READY_MASK (0x40U) +#define CCM_CISR_COSC_READY_SHIFT (6U) +#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK) +#define CCM_CISR_AXI_PODF_LOADED_MASK (0x20000U) +#define CCM_CISR_AXI_PODF_LOADED_SHIFT (17U) +#define CCM_CISR_AXI_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AXI_PODF_LOADED_SHIFT)) & CCM_CISR_AXI_PODF_LOADED_MASK) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK) +#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U) +#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U) +#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK) +#define CCM_CISR_MMDC_PODF_LOADED_MASK (0x200000U) +#define CCM_CISR_MMDC_PODF_LOADED_SHIFT (21U) +#define CCM_CISR_MMDC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_MMDC_PODF_LOADED_SHIFT)) & CCM_CISR_MMDC_PODF_LOADED_MASK) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK) +#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U) +#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U) +#define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK) + +/*! @name CIMR - CCM Interrupt Mask Register */ +#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U) +#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U) +#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK) +#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U) +#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U) +#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK) +#define CCM_CIMR_MASK_AXI_PODF_LOADED_MASK (0x20000U) +#define CCM_CIMR_MASK_AXI_PODF_LOADED_SHIFT (17U) +#define CCM_CIMR_MASK_AXI_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AXI_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AXI_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK) +#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U) +#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U) +#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_MMDC_PODF_LOADED_MASK (0x200000U) +#define CCM_CIMR_MASK_MMDC_PODF_LOADED_SHIFT (21U) +#define CCM_CIMR_MASK_MMDC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_MMDC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_MMDC_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK) +#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U) +#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U) +#define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK) + +/*! @name CCOSR - CCM Clock Output Source Register */ +#define CCM_CCOSR_CLKO_SEL_MASK (0xFU) +#define CCM_CCOSR_CLKO_SEL_SHIFT (0U) +#define CCM_CCOSR_CLKO_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO_SEL_SHIFT)) & CCM_CCOSR_CLKO_SEL_MASK) +#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U) +#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U) +#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK) +#define CCM_CCOSR_CLKO1_EN_MASK (0x80U) +#define CCM_CCOSR_CLKO1_EN_SHIFT (7U) +#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK) +#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U) +#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U) +#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK) +#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U) +#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U) +#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK) +#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U) +#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U) +#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK) +#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U) +#define CCM_CCOSR_CLKO2_EN_SHIFT (24U) +#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK) + +/*! @name CGPR - CCM General Purpose Register */ +#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U) +#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U) +#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK) +#define CCM_CGPR_MMDC_EXT_CLK_DIS_MASK (0x4U) +#define CCM_CGPR_MMDC_EXT_CLK_DIS_SHIFT (2U) +#define CCM_CGPR_MMDC_EXT_CLK_DIS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_MMDC_EXT_CLK_DIS_SHIFT)) & CCM_CGPR_MMDC_EXT_CLK_DIS_MASK) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK) +#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U) +#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U) +#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK) +#define CCM_CGPR_FPL_MASK (0x10000U) +#define CCM_CGPR_FPL_SHIFT (16U) +#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK) +#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U) +#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U) +#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK) + +/*! @name CCGR0 - CCM Clock Gating Register 0 */ +#define CCM_CCGR0_CG0_MASK (0x3U) +#define CCM_CCGR0_CG0_SHIFT (0U) +#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK) +#define CCM_CCGR0_CG1_MASK (0xCU) +#define CCM_CCGR0_CG1_SHIFT (2U) +#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK) +#define CCM_CCGR0_CG2_MASK (0x30U) +#define CCM_CCGR0_CG2_SHIFT (4U) +#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK) +#define CCM_CCGR0_CG3_MASK (0xC0U) +#define CCM_CCGR0_CG3_SHIFT (6U) +#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK) +#define CCM_CCGR0_CG4_MASK (0x300U) +#define CCM_CCGR0_CG4_SHIFT (8U) +#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK) +#define CCM_CCGR0_CG5_MASK (0xC00U) +#define CCM_CCGR0_CG5_SHIFT (10U) +#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK) +#define CCM_CCGR0_CG6_MASK (0x3000U) +#define CCM_CCGR0_CG6_SHIFT (12U) +#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK) +#define CCM_CCGR0_CG7_MASK (0xC000U) +#define CCM_CCGR0_CG7_SHIFT (14U) +#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK) +#define CCM_CCGR0_CG8_MASK (0x30000U) +#define CCM_CCGR0_CG8_SHIFT (16U) +#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK) +#define CCM_CCGR0_CG9_MASK (0xC0000U) +#define CCM_CCGR0_CG9_SHIFT (18U) +#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK) +#define CCM_CCGR0_CG10_MASK (0x300000U) +#define CCM_CCGR0_CG10_SHIFT (20U) +#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK) +#define CCM_CCGR0_CG11_MASK (0xC00000U) +#define CCM_CCGR0_CG11_SHIFT (22U) +#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK) +#define CCM_CCGR0_CG12_MASK (0x3000000U) +#define CCM_CCGR0_CG12_SHIFT (24U) +#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK) +#define CCM_CCGR0_CG13_MASK (0xC000000U) +#define CCM_CCGR0_CG13_SHIFT (26U) +#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK) +#define CCM_CCGR0_CG14_MASK (0x30000000U) +#define CCM_CCGR0_CG14_SHIFT (28U) +#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK) +#define CCM_CCGR0_CG15_MASK (0xC0000000U) +#define CCM_CCGR0_CG15_SHIFT (30U) +#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK) + +/*! @name CCGR1 - CCM Clock Gating Register 1 */ +#define CCM_CCGR1_CG0_MASK (0x3U) +#define CCM_CCGR1_CG0_SHIFT (0U) +#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK) +#define CCM_CCGR1_CG1_MASK (0xCU) +#define CCM_CCGR1_CG1_SHIFT (2U) +#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK) +#define CCM_CCGR1_CG2_MASK (0x30U) +#define CCM_CCGR1_CG2_SHIFT (4U) +#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK) +#define CCM_CCGR1_CG3_MASK (0xC0U) +#define CCM_CCGR1_CG3_SHIFT (6U) +#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK) +#define CCM_CCGR1_CG4_MASK (0x300U) +#define CCM_CCGR1_CG4_SHIFT (8U) +#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK) +#define CCM_CCGR1_CG5_MASK (0xC00U) +#define CCM_CCGR1_CG5_SHIFT (10U) +#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK) +#define CCM_CCGR1_CG6_MASK (0x3000U) +#define CCM_CCGR1_CG6_SHIFT (12U) +#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK) +#define CCM_CCGR1_CG7_MASK (0xC000U) +#define CCM_CCGR1_CG7_SHIFT (14U) +#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK) +#define CCM_CCGR1_CG8_MASK (0x30000U) +#define CCM_CCGR1_CG8_SHIFT (16U) +#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK) +#define CCM_CCGR1_CG9_MASK (0xC0000U) +#define CCM_CCGR1_CG9_SHIFT (18U) +#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK) +#define CCM_CCGR1_CG10_MASK (0x300000U) +#define CCM_CCGR1_CG10_SHIFT (20U) +#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK) +#define CCM_CCGR1_CG11_MASK (0xC00000U) +#define CCM_CCGR1_CG11_SHIFT (22U) +#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK) +#define CCM_CCGR1_CG12_MASK (0x3000000U) +#define CCM_CCGR1_CG12_SHIFT (24U) +#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK) +#define CCM_CCGR1_CG13_MASK (0xC000000U) +#define CCM_CCGR1_CG13_SHIFT (26U) +#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK) +#define CCM_CCGR1_CG14_MASK (0x30000000U) +#define CCM_CCGR1_CG14_SHIFT (28U) +#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK) +#define CCM_CCGR1_CG15_MASK (0xC0000000U) +#define CCM_CCGR1_CG15_SHIFT (30U) +#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK) + +/*! @name CCGR2 - CCM Clock Gating Register 2 */ +#define CCM_CCGR2_CG0_MASK (0x3U) +#define CCM_CCGR2_CG0_SHIFT (0U) +#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK) +#define CCM_CCGR2_CG1_MASK (0xCU) +#define CCM_CCGR2_CG1_SHIFT (2U) +#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK) +#define CCM_CCGR2_CG2_MASK (0x30U) +#define CCM_CCGR2_CG2_SHIFT (4U) +#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK) +#define CCM_CCGR2_CG3_MASK (0xC0U) +#define CCM_CCGR2_CG3_SHIFT (6U) +#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK) +#define CCM_CCGR2_CG4_MASK (0x300U) +#define CCM_CCGR2_CG4_SHIFT (8U) +#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK) +#define CCM_CCGR2_CG5_MASK (0xC00U) +#define CCM_CCGR2_CG5_SHIFT (10U) +#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK) +#define CCM_CCGR2_CG6_MASK (0x3000U) +#define CCM_CCGR2_CG6_SHIFT (12U) +#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK) +#define CCM_CCGR2_CG7_MASK (0xC000U) +#define CCM_CCGR2_CG7_SHIFT (14U) +#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK) +#define CCM_CCGR2_CG8_MASK (0x30000U) +#define CCM_CCGR2_CG8_SHIFT (16U) +#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK) +#define CCM_CCGR2_CG9_MASK (0xC0000U) +#define CCM_CCGR2_CG9_SHIFT (18U) +#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK) +#define CCM_CCGR2_CG10_MASK (0x300000U) +#define CCM_CCGR2_CG10_SHIFT (20U) +#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK) +#define CCM_CCGR2_CG11_MASK (0xC00000U) +#define CCM_CCGR2_CG11_SHIFT (22U) +#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK) +#define CCM_CCGR2_CG12_MASK (0x3000000U) +#define CCM_CCGR2_CG12_SHIFT (24U) +#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK) +#define CCM_CCGR2_CG13_MASK (0xC000000U) +#define CCM_CCGR2_CG13_SHIFT (26U) +#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK) +#define CCM_CCGR2_CG14_MASK (0x30000000U) +#define CCM_CCGR2_CG14_SHIFT (28U) +#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK) +#define CCM_CCGR2_CG15_MASK (0xC0000000U) +#define CCM_CCGR2_CG15_SHIFT (30U) +#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK) + +/*! @name CCGR3 - CCM Clock Gating Register 3 */ +#define CCM_CCGR3_CG0_MASK (0x3U) +#define CCM_CCGR3_CG0_SHIFT (0U) +#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK) +#define CCM_CCGR3_CG1_MASK (0xCU) +#define CCM_CCGR3_CG1_SHIFT (2U) +#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK) +#define CCM_CCGR3_CG2_MASK (0x30U) +#define CCM_CCGR3_CG2_SHIFT (4U) +#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK) +#define CCM_CCGR3_CG3_MASK (0xC0U) +#define CCM_CCGR3_CG3_SHIFT (6U) +#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK) +#define CCM_CCGR3_CG4_MASK (0x300U) +#define CCM_CCGR3_CG4_SHIFT (8U) +#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK) +#define CCM_CCGR3_CG5_MASK (0xC00U) +#define CCM_CCGR3_CG5_SHIFT (10U) +#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK) +#define CCM_CCGR3_CG6_MASK (0x3000U) +#define CCM_CCGR3_CG6_SHIFT (12U) +#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK) +#define CCM_CCGR3_CG7_MASK (0xC000U) +#define CCM_CCGR3_CG7_SHIFT (14U) +#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK) +#define CCM_CCGR3_CG8_MASK (0x30000U) +#define CCM_CCGR3_CG8_SHIFT (16U) +#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK) +#define CCM_CCGR3_CG9_MASK (0xC0000U) +#define CCM_CCGR3_CG9_SHIFT (18U) +#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK) +#define CCM_CCGR3_CG10_MASK (0x300000U) +#define CCM_CCGR3_CG10_SHIFT (20U) +#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK) +#define CCM_CCGR3_CG11_MASK (0xC00000U) +#define CCM_CCGR3_CG11_SHIFT (22U) +#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK) +#define CCM_CCGR3_CG12_MASK (0x3000000U) +#define CCM_CCGR3_CG12_SHIFT (24U) +#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK) +#define CCM_CCGR3_CG13_MASK (0xC000000U) +#define CCM_CCGR3_CG13_SHIFT (26U) +#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK) +#define CCM_CCGR3_CG14_MASK (0x30000000U) +#define CCM_CCGR3_CG14_SHIFT (28U) +#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK) +#define CCM_CCGR3_CG15_MASK (0xC0000000U) +#define CCM_CCGR3_CG15_SHIFT (30U) +#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK) + +/*! @name CCGR4 - CCM Clock Gating Register 4 */ +#define CCM_CCGR4_CG0_MASK (0x3U) +#define CCM_CCGR4_CG0_SHIFT (0U) +#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK) +#define CCM_CCGR4_CG1_MASK (0xCU) +#define CCM_CCGR4_CG1_SHIFT (2U) +#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK) +#define CCM_CCGR4_CG2_MASK (0x30U) +#define CCM_CCGR4_CG2_SHIFT (4U) +#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK) +#define CCM_CCGR4_CG3_MASK (0xC0U) +#define CCM_CCGR4_CG3_SHIFT (6U) +#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK) +#define CCM_CCGR4_CG4_MASK (0x300U) +#define CCM_CCGR4_CG4_SHIFT (8U) +#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK) +#define CCM_CCGR4_CG5_MASK (0xC00U) +#define CCM_CCGR4_CG5_SHIFT (10U) +#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK) +#define CCM_CCGR4_CG6_MASK (0x3000U) +#define CCM_CCGR4_CG6_SHIFT (12U) +#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK) +#define CCM_CCGR4_CG7_MASK (0xC000U) +#define CCM_CCGR4_CG7_SHIFT (14U) +#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK) +#define CCM_CCGR4_CG8_MASK (0x30000U) +#define CCM_CCGR4_CG8_SHIFT (16U) +#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK) +#define CCM_CCGR4_CG9_MASK (0xC0000U) +#define CCM_CCGR4_CG9_SHIFT (18U) +#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK) +#define CCM_CCGR4_CG10_MASK (0x300000U) +#define CCM_CCGR4_CG10_SHIFT (20U) +#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK) +#define CCM_CCGR4_CG11_MASK (0xC00000U) +#define CCM_CCGR4_CG11_SHIFT (22U) +#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK) +#define CCM_CCGR4_CG12_MASK (0x3000000U) +#define CCM_CCGR4_CG12_SHIFT (24U) +#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK) +#define CCM_CCGR4_CG13_MASK (0xC000000U) +#define CCM_CCGR4_CG13_SHIFT (26U) +#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK) +#define CCM_CCGR4_CG14_MASK (0x30000000U) +#define CCM_CCGR4_CG14_SHIFT (28U) +#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK) +#define CCM_CCGR4_CG15_MASK (0xC0000000U) +#define CCM_CCGR4_CG15_SHIFT (30U) +#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK) + +/*! @name CCGR5 - CCM Clock Gating Register 5 */ +#define CCM_CCGR5_CG0_MASK (0x3U) +#define CCM_CCGR5_CG0_SHIFT (0U) +#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK) +#define CCM_CCGR5_CG1_MASK (0xCU) +#define CCM_CCGR5_CG1_SHIFT (2U) +#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK) +#define CCM_CCGR5_CG2_MASK (0x30U) +#define CCM_CCGR5_CG2_SHIFT (4U) +#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK) +#define CCM_CCGR5_CG3_MASK (0xC0U) +#define CCM_CCGR5_CG3_SHIFT (6U) +#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK) +#define CCM_CCGR5_CG4_MASK (0x300U) +#define CCM_CCGR5_CG4_SHIFT (8U) +#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK) +#define CCM_CCGR5_CG5_MASK (0xC00U) +#define CCM_CCGR5_CG5_SHIFT (10U) +#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK) +#define CCM_CCGR5_CG6_MASK (0x3000U) +#define CCM_CCGR5_CG6_SHIFT (12U) +#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK) +#define CCM_CCGR5_CG7_MASK (0xC000U) +#define CCM_CCGR5_CG7_SHIFT (14U) +#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK) +#define CCM_CCGR5_CG8_MASK (0x30000U) +#define CCM_CCGR5_CG8_SHIFT (16U) +#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK) +#define CCM_CCGR5_CG9_MASK (0xC0000U) +#define CCM_CCGR5_CG9_SHIFT (18U) +#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK) +#define CCM_CCGR5_CG10_MASK (0x300000U) +#define CCM_CCGR5_CG10_SHIFT (20U) +#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK) +#define CCM_CCGR5_CG11_MASK (0xC00000U) +#define CCM_CCGR5_CG11_SHIFT (22U) +#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK) +#define CCM_CCGR5_CG12_MASK (0x3000000U) +#define CCM_CCGR5_CG12_SHIFT (24U) +#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK) +#define CCM_CCGR5_CG13_MASK (0xC000000U) +#define CCM_CCGR5_CG13_SHIFT (26U) +#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK) +#define CCM_CCGR5_CG14_MASK (0x30000000U) +#define CCM_CCGR5_CG14_SHIFT (28U) +#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK) +#define CCM_CCGR5_CG15_MASK (0xC0000000U) +#define CCM_CCGR5_CG15_SHIFT (30U) +#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK) + +/*! @name CCGR6 - CCM Clock Gating Register 6 */ +#define CCM_CCGR6_CG0_MASK (0x3U) +#define CCM_CCGR6_CG0_SHIFT (0U) +#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK) +#define CCM_CCGR6_CG1_MASK (0xCU) +#define CCM_CCGR6_CG1_SHIFT (2U) +#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK) +#define CCM_CCGR6_CG2_MASK (0x30U) +#define CCM_CCGR6_CG2_SHIFT (4U) +#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK) +#define CCM_CCGR6_CG3_MASK (0xC0U) +#define CCM_CCGR6_CG3_SHIFT (6U) +#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK) +#define CCM_CCGR6_CG4_MASK (0x300U) +#define CCM_CCGR6_CG4_SHIFT (8U) +#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK) +#define CCM_CCGR6_CG5_MASK (0xC00U) +#define CCM_CCGR6_CG5_SHIFT (10U) +#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK) +#define CCM_CCGR6_CG6_MASK (0x3000U) +#define CCM_CCGR6_CG6_SHIFT (12U) +#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK) +#define CCM_CCGR6_CG7_MASK (0xC000U) +#define CCM_CCGR6_CG7_SHIFT (14U) +#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK) +#define CCM_CCGR6_CG8_MASK (0x30000U) +#define CCM_CCGR6_CG8_SHIFT (16U) +#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK) +#define CCM_CCGR6_CG9_MASK (0xC0000U) +#define CCM_CCGR6_CG9_SHIFT (18U) +#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK) +#define CCM_CCGR6_CG10_MASK (0x300000U) +#define CCM_CCGR6_CG10_SHIFT (20U) +#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK) +#define CCM_CCGR6_CG11_MASK (0xC00000U) +#define CCM_CCGR6_CG11_SHIFT (22U) +#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK) +#define CCM_CCGR6_CG12_MASK (0x3000000U) +#define CCM_CCGR6_CG12_SHIFT (24U) +#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK) +#define CCM_CCGR6_CG13_MASK (0xC000000U) +#define CCM_CCGR6_CG13_SHIFT (26U) +#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK) +#define CCM_CCGR6_CG14_MASK (0x30000000U) +#define CCM_CCGR6_CG14_SHIFT (28U) +#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK) +#define CCM_CCGR6_CG15_MASK (0xC0000000U) +#define CCM_CCGR6_CG15_SHIFT (30U) +#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK) + +/*! @name CMEOR - CCM Module Enable Overide Register */ +#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U) +#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U) +#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK) +#define CCM_CMEOR_MOD_EN_OV_EPIT_MASK (0x40U) +#define CCM_CMEOR_MOD_EN_OV_EPIT_SHIFT (6U) +#define CCM_CMEOR_MOD_EN_OV_EPIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_EPIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_EPIT_MASK) +#define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U) +#define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U) +#define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK) + + +/*! + * @} + */ /* end of group CCM_Register_Masks */ + + +/* CCM - Peripheral instance base addresses */ +/** Peripheral CCM base address */ +#define CCM_BASE (0x20C4000u) +/** Peripheral CCM base pointer */ +#define CCM ((CCM_Type *)CCM_BASE) +/** Array initializer of CCM peripheral base addresses */ +#define CCM_BASE_ADDRS { CCM_BASE } +/** Array initializer of CCM peripheral base pointers */ +#define CCM_BASE_PTRS { CCM } +/** Interrupt vectors for the CCM peripheral type */ +#define CCM_IRQS { CCM_IRQ1_IRQn, CCM_IRQ2_IRQn } + +/*! + * @} + */ /* end of group CCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer + * @{ + */ + +/** CCM_ANALOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t PLL_ARM; /**< Analog ARM PLL control Register, offset: 0x0 */ + __IO uint32_t PLL_ARM_SET; /**< Analog ARM PLL control Register, offset: 0x4 */ + __IO uint32_t PLL_ARM_CLR; /**< Analog ARM PLL control Register, offset: 0x8 */ + __IO uint32_t PLL_ARM_TOG; /**< Analog ARM PLL control Register, offset: 0xC */ + __IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */ + __IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */ + __IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */ + __IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */ + __IO uint32_t PLL_USB2; /**< Analog USB2 480MHz PLL Control Register, offset: 0x20 */ + __IO uint32_t PLL_USB2_SET; /**< Analog USB2 480MHz PLL Control Register, offset: 0x24 */ + __IO uint32_t PLL_USB2_CLR; /**< Analog USB2 480MHz PLL Control Register, offset: 0x28 */ + __IO uint32_t PLL_USB2_TOG; /**< Analog USB2 480MHz PLL Control Register, offset: 0x2C */ + __IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */ + __IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */ + __IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */ + __IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */ + __IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PLL_SYS_NUM; /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PLL_SYS_DENOM; /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */ + uint8_t RESERVED_2[12]; + __IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */ + __IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */ + __IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */ + __IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */ + __IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */ + uint8_t RESERVED_3[12]; + __IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */ + uint8_t RESERVED_4[12]; + __IO uint32_t PLL_VIDEO; /**< Analog Video PLL control Register, offset: 0xA0 */ + __IO uint32_t PLL_VIDEO_SET; /**< Analog Video PLL control Register, offset: 0xA4 */ + __IO uint32_t PLL_VIDEO_CLR; /**< Analog Video PLL control Register, offset: 0xA8 */ + __IO uint32_t PLL_VIDEO_TOG; /**< Analog Video PLL control Register, offset: 0xAC */ + __IO uint32_t PLL_VIDEO_NUM; /**< Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0 */ + uint8_t RESERVED_5[12]; + __IO uint32_t PLL_VIDEO_DENOM; /**< Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0 */ + uint8_t RESERVED_6[28]; + __IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */ + __IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */ + __IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */ + __IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */ + __IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */ + __IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */ + __IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */ + __IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */ + __IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */ + __IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */ + __IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */ + __IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */ + uint8_t RESERVED_7[64]; + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ + __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ + __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ + __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ + __IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */ + __IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */ + __IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */ + __IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */ +} CCM_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks + * @{ + */ + +/*! @name PLL_ARM - Analog ARM PLL control Register */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK) + +/*! @name PLL_ARM_SET - Analog ARM PLL control Register */ +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK) + +/*! @name PLL_ARM_CLR - Analog ARM PLL control Register */ +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK) + +/*! @name PLL_ARM_TOG - Analog ARM PLL control Register */ +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK) + +/*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK) + +/*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK) + +/*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK) + +/*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK) + +/*! @name PLL_USB2 - Analog USB2 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK) + +/*! @name PLL_USB2_SET - Analog USB2 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK) + +/*! @name PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK) + +/*! @name PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register */ +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK) + +/*! @name PLL_SYS - Analog System PLL Control Register */ +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK) + +/*! @name PLL_SYS_SET - Analog System PLL Control Register */ +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK) + +/*! @name PLL_SYS_CLR - Analog System PLL Control Register */ +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK) + +/*! @name PLL_SYS_TOG - Analog System PLL Control Register */ +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK) + +/*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */ +#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU) +#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U) +#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK) + +/*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK) + +/*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK) + +/*! @name PLL_AUDIO - Analog Audio PLL control Register */ +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) + +/*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */ +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK) + +/*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */ +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK) + +/*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */ +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK) + +/*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) + +/*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) + +/*! @name PLL_VIDEO - Analog Video PLL control Register */ +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) + +/*! @name PLL_VIDEO_SET - Analog Video PLL control Register */ +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK) + +/*! @name PLL_VIDEO_CLR - Analog Video PLL control Register */ +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK) + +/*! @name PLL_VIDEO_TOG - Analog Video PLL control Register */ +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK) + +/*! @name PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) + +/*! @name PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register */ +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) + +/*! @name PLL_ENET - Analog ENET PLL Control Register */ +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT (2U) +#define CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK (0x80000U) +#define CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT (19U) +#define CCM_ANALOG_PLL_ENET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_125M_MASK) +#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK) + +/*! @name PLL_ENET_SET - Analog ENET PLL Control Register */ +#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET0_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT (2U) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK (0x80000U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT (19U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_125M_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK) + +/*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */ +#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET0_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT (2U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK (0x80000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT (19U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_125M_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK) + +/*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */ +#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET0_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT (2U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET1_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U) +#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK (0x80000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT (19U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_125M_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_125M_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK) + +/*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK) + +/*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK) + +/*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK) + +/*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK) + +/*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK) + +/*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK) + +/*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK) + +/*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK) + +/*! @name MISC0 - Miscellaneous Register 0 */ +#define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK) +#define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK) +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT (31U) +#define CCM_ANALOG_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_VID_PLL_PREDIV_MASK) + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK) +#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) +#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) +#define CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_SET_VID_PLL_PREDIV_MASK) + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK) +#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) +#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) +#define CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_CLR_VID_PLL_PREDIV_MASK) + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U) +#define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK) +#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) +#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) +#define CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & CCM_ANALOG_MISC0_TOG_VID_PLL_PREDIV_MASK) + +/*! @name MISC1 - Miscellaneous Register 1 */ +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK) + +/*! @name MISC1_SET - Miscellaneous Register 1 */ +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK) + +/*! @name MISC1_CLR - Miscellaneous Register 1 */ +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK) + +/*! @name MISC1_TOG - Miscellaneous Register 1 */ +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK) + +/*! @name MISC2 - Miscellaneous Register 2 */ +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) + +/*! @name MISC2_SET - Miscellaneous Register 2 */ +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_SET_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK) + +/*! @name MISC2_CLR - Miscellaneous Register 2 */ +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK) + +/*! @name MISC2_TOG - Miscellaneous Register 2 */ +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK (0x80U) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT (7U) +#define CCM_ANALOG_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK) + + +/*! + * @} + */ /* end of group CCM_ANALOG_Register_Masks */ + + +/* CCM_ANALOG - Peripheral instance base addresses */ +/** Peripheral CCM_ANALOG base address */ +#define CCM_ANALOG_BASE (0x20C8000u) +/** Peripheral CCM_ANALOG base pointer */ +#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE) +/** Array initializer of CCM_ANALOG peripheral base addresses */ +#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE } +/** Array initializer of CCM_ANALOG peripheral base pointers */ +#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG } + +/*! + * @} + */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CSI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer + * @{ + */ + +/** CSI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSICR1; /**< CSI Control Register 1, offset: 0x0 */ + __IO uint32_t CSICR2; /**< CSI Control Register 2, offset: 0x4 */ + __IO uint32_t CSICR3; /**< CSI Control Register 3, offset: 0x8 */ + __I uint32_t CSISTATFIFO; /**< CSI Statistic FIFO Register, offset: 0xC */ + __I uint32_t CSIRFIFO; /**< CSI RX FIFO Register, offset: 0x10 */ + __IO uint32_t CSIRXCNT; /**< CSI RX Count Register, offset: 0x14 */ + __IO uint32_t CSISR; /**< CSI Status Register, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t CSIDMASA_STATFIFO; /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */ + __IO uint32_t CSIDMATS_STATFIFO; /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */ + __IO uint32_t CSIDMASA_FB1; /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */ + __IO uint32_t CSIDMASA_FB2; /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */ + __IO uint32_t CSIFBUF_PARA; /**< CSI Frame Buffer Parameter Register, offset: 0x30 */ + __IO uint32_t CSIIMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */ + uint8_t RESERVED_1[16]; + __IO uint32_t CSICR18; /**< CSI Control Register 18, offset: 0x48 */ + __IO uint32_t CSICR19; /**< CSI Control Register 19, offset: 0x4C */ +} CSI_Type; + +/* ---------------------------------------------------------------------------- + -- CSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Register_Masks CSI Register Masks + * @{ + */ + +/*! @name CSICR1 - CSI Control Register 1 */ +#define CSI_CSICR1_PIXEL_BIT_MASK (0x1U) +#define CSI_CSICR1_PIXEL_BIT_SHIFT (0U) +#define CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK) +#define CSI_CSICR1_REDGE_MASK (0x2U) +#define CSI_CSICR1_REDGE_SHIFT (1U) +#define CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK) +#define CSI_CSICR1_INV_PCLK_MASK (0x4U) +#define CSI_CSICR1_INV_PCLK_SHIFT (2U) +#define CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK) +#define CSI_CSICR1_INV_DATA_MASK (0x8U) +#define CSI_CSICR1_INV_DATA_SHIFT (3U) +#define CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK) +#define CSI_CSICR1_GCLK_MODE_MASK (0x10U) +#define CSI_CSICR1_GCLK_MODE_SHIFT (4U) +#define CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK) +#define CSI_CSICR1_CLR_RXFIFO_MASK (0x20U) +#define CSI_CSICR1_CLR_RXFIFO_SHIFT (5U) +#define CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK) +#define CSI_CSICR1_CLR_STATFIFO_MASK (0x40U) +#define CSI_CSICR1_CLR_STATFIFO_SHIFT (6U) +#define CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK) +#define CSI_CSICR1_PACK_DIR_MASK (0x80U) +#define CSI_CSICR1_PACK_DIR_SHIFT (7U) +#define CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK) +#define CSI_CSICR1_FCC_MASK (0x100U) +#define CSI_CSICR1_FCC_SHIFT (8U) +#define CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK) +#define CSI_CSICR1_CCIR_EN_MASK (0x400U) +#define CSI_CSICR1_CCIR_EN_SHIFT (10U) +#define CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK) +#define CSI_CSICR1_HSYNC_POL_MASK (0x800U) +#define CSI_CSICR1_HSYNC_POL_SHIFT (11U) +#define CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK) +#define CSI_CSICR1_SOF_INTEN_MASK (0x10000U) +#define CSI_CSICR1_SOF_INTEN_SHIFT (16U) +#define CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK) +#define CSI_CSICR1_SOF_POL_MASK (0x20000U) +#define CSI_CSICR1_SOF_POL_SHIFT (17U) +#define CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK) +#define CSI_CSICR1_RXFF_INTEN_MASK (0x40000U) +#define CSI_CSICR1_RXFF_INTEN_SHIFT (18U) +#define CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_STATFF_INTEN_MASK (0x200000U) +#define CSI_CSICR1_STATFF_INTEN_SHIFT (21U) +#define CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK) +#define CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U) +#define CSI_CSICR1_RF_OR_INTEN_SHIFT (24U) +#define CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK) +#define CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U) +#define CSI_CSICR1_SF_OR_INTEN_SHIFT (25U) +#define CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK) +#define CSI_CSICR1_COF_INT_EN_MASK (0x4000000U) +#define CSI_CSICR1_COF_INT_EN_SHIFT (26U) +#define CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK) +#define CSI_CSICR1_VIDEO_MODE_MASK (0x8000000U) +#define CSI_CSICR1_VIDEO_MODE_SHIFT (27U) +#define CSI_CSICR1_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_VIDEO_MODE_SHIFT)) & CSI_CSICR1_VIDEO_MODE_MASK) +#define CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U) +#define CSI_CSICR1_PrP_IF_EN_SHIFT (28U) +#define CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK) +#define CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U) +#define CSI_CSICR1_EOF_INT_EN_SHIFT (29U) +#define CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK) +#define CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U) +#define CSI_CSICR1_EXT_VSYNC_SHIFT (30U) +#define CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK) +#define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U) +#define CSI_CSICR1_SWAP16_EN_SHIFT (31U) +#define CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK) + +/*! @name CSICR2 - CSI Control Register 2 */ +#define CSI_CSICR2_HSC_MASK (0xFFU) +#define CSI_CSICR2_HSC_SHIFT (0U) +#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK) +#define CSI_CSICR2_VSC_MASK (0xFF00U) +#define CSI_CSICR2_VSC_SHIFT (8U) +#define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK) +#define CSI_CSICR2_LVRM_MASK (0x70000U) +#define CSI_CSICR2_LVRM_SHIFT (16U) +#define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK) +#define CSI_CSICR2_BTS_MASK (0x180000U) +#define CSI_CSICR2_BTS_SHIFT (19U) +#define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK) +#define CSI_CSICR2_SCE_MASK (0x800000U) +#define CSI_CSICR2_SCE_SHIFT (23U) +#define CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK) +#define CSI_CSICR2_AFS_MASK (0x3000000U) +#define CSI_CSICR2_AFS_SHIFT (24U) +#define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK) +#define CSI_CSICR2_DRM_MASK (0x4000000U) +#define CSI_CSICR2_DRM_SHIFT (26U) +#define CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK) + +/*! @name CSICR3 - CSI Control Register 3 */ +#define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U) +#define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U) +#define CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK) +#define CSI_CSICR3_ECC_INT_EN_MASK (0x2U) +#define CSI_CSICR3_ECC_INT_EN_SHIFT (1U) +#define CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK) +#define CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U) +#define CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U) +#define CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK) +#define CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U) +#define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U) +#define CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK) +#define CSI_CSICR3_RxFF_LEVEL_MASK (0x70U) +#define CSI_CSICR3_RxFF_LEVEL_SHIFT (4U) +#define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK) +#define CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U) +#define CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U) +#define CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK) +#define CSI_CSICR3_STATFF_LEVEL_MASK (0x700U) +#define CSI_CSICR3_STATFF_LEVEL_SHIFT (8U) +#define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK) +#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U) +#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U) +#define CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK) +#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U) +#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U) +#define CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK) +#define CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U) +#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U) +#define CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK) +#define CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U) +#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U) +#define CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK) +#define CSI_CSICR3_FRMCNT_RST_MASK (0x8000U) +#define CSI_CSICR3_FRMCNT_RST_SHIFT (15U) +#define CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK) +#define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U) +#define CSI_CSICR3_FRMCNT_SHIFT (16U) +#define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK) + +/*! @name CSISTATFIFO - CSI Statistic FIFO Register */ +#define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU) +#define CSI_CSISTATFIFO_STAT_SHIFT (0U) +#define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK) + +/*! @name CSIRFIFO - CSI RX FIFO Register */ +#define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU) +#define CSI_CSIRFIFO_IMAGE_SHIFT (0U) +#define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK) + +/*! @name CSIRXCNT - CSI RX Count Register */ +#define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU) +#define CSI_CSIRXCNT_RXCNT_SHIFT (0U) +#define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK) + +/*! @name CSISR - CSI Status Register */ +#define CSI_CSISR_DRDY_MASK (0x1U) +#define CSI_CSISR_DRDY_SHIFT (0U) +#define CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK) +#define CSI_CSISR_ECC_INT_MASK (0x2U) +#define CSI_CSISR_ECC_INT_SHIFT (1U) +#define CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK) +#define CSI_CSISR_HRESP_ERR_INT_MASK (0x80U) +#define CSI_CSISR_HRESP_ERR_INT_SHIFT (7U) +#define CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK) +#define CSI_CSISR_COF_INT_MASK (0x2000U) +#define CSI_CSISR_COF_INT_SHIFT (13U) +#define CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK) +#define CSI_CSISR_F1_INT_MASK (0x4000U) +#define CSI_CSISR_F1_INT_SHIFT (14U) +#define CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK) +#define CSI_CSISR_F2_INT_MASK (0x8000U) +#define CSI_CSISR_F2_INT_SHIFT (15U) +#define CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK) +#define CSI_CSISR_SOF_INT_MASK (0x10000U) +#define CSI_CSISR_SOF_INT_SHIFT (16U) +#define CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK) +#define CSI_CSISR_EOF_INT_MASK (0x20000U) +#define CSI_CSISR_EOF_INT_SHIFT (17U) +#define CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK) +#define CSI_CSISR_RxFF_INT_MASK (0x40000U) +#define CSI_CSISR_RxFF_INT_SHIFT (18U) +#define CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK) +#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U) +#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U) +#define CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK) +#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U) +#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U) +#define CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK) +#define CSI_CSISR_STATFF_INT_MASK (0x200000U) +#define CSI_CSISR_STATFF_INT_SHIFT (21U) +#define CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK) +#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U) +#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U) +#define CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK) +#define CSI_CSISR_RF_OR_INT_MASK (0x1000000U) +#define CSI_CSISR_RF_OR_INT_SHIFT (24U) +#define CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK) +#define CSI_CSISR_SF_OR_INT_MASK (0x2000000U) +#define CSI_CSISR_SF_OR_INT_SHIFT (25U) +#define CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK) +#define CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U) +#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U) +#define CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK) +#define CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U) +#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U) +#define CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK) + +/*! @name CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */ +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U) +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK) + +/*! @name CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */ +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU) +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U) +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK) + +/*! @name CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */ +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U) +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK) + +/*! @name CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */ +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU) +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U) +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK) + +/*! @name CSIFBUF_PARA - CSI Frame Buffer Parameter Register */ +#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU) +#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U) +#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK) + +/*! @name CSIIMAG_PARA - CSI Image Parameter Register */ +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU) +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U) +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK) + +/*! @name CSICR18 - CSI Control Register 18 */ +#define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U) +#define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U) +#define CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK) +#define CSI_CSICR18_PARALLEL24_EN_MASK (0x8U) +#define CSI_CSICR18_PARALLEL24_EN_SHIFT (3U) +#define CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK) +#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U) +#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U) +#define CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK) +#define CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U) +#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U) +#define CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK) +#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U) +#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U) +#define CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK) +#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U) +#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U) +#define CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK) +#define CSI_CSICR18_AHB_HPROT_MASK (0xF000U) +#define CSI_CSICR18_AHB_HPROT_SHIFT (12U) +#define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK) +#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK (0x30000U) +#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT (16U) +#define CSI_CSICR18_CSI_LCDIF_BUFFER_LINES(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_SHIFT)) & CSI_CSICR18_CSI_LCDIF_BUFFER_LINES_MASK) +#define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U) +#define CSI_CSICR18_MASK_OPTION_SHIFT (18U) +#define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK) +#define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U) +#define CSI_CSICR18_CSI_ENABLE_SHIFT (31U) +#define CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK) + +/*! @name CSICR19 - CSI Control Register 19 */ +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU) +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U) +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK) + + +/*! + * @} + */ /* end of group CSI_Register_Masks */ + + +/* CSI - Peripheral instance base addresses */ +/** Peripheral CSI base address */ +#define CSI_BASE (0x21C4000u) +/** Peripheral CSI base pointer */ +#define CSI ((CSI_Type *)CSI_BASE) +/** Array initializer of CSI peripheral base addresses */ +#define CSI_BASE_ADDRS { CSI_BASE } +/** Array initializer of CSI peripheral base pointers */ +#define CSI_BASE_PTRS { CSI } +/** Interrupt vectors for the CSI peripheral type */ +#define CSI_IRQS { CSI_IRQn } + +/*! + * @} + */ /* end of group CSI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DCP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCP_Peripheral_Access_Layer DCP Peripheral Access Layer + * @{ + */ + +/** DCP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DCP control register 0, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t STAT; /**< DCP status register, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CHANNELCTRL; /**< DCP channel control register, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CAPABILITY0; /**< DCP capability 0 register, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __I uint32_t CAPABILITY1; /**< DCP capability 1 register, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t CONTEXT; /**< DCP context buffer pointer, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t KEY; /**< DCP key index, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t KEYDATA; /**< DCP key data, offset: 0x70 */ + uint8_t RESERVED_7[12]; + __I uint32_t PACKET0; /**< DCP work packet 0 status register, offset: 0x80 */ + uint8_t RESERVED_8[12]; + __I uint32_t PACKET1; /**< DCP work packet 1 status register, offset: 0x90 */ + uint8_t RESERVED_9[12]; + __I uint32_t PACKET2; /**< DCP work packet 2 status register, offset: 0xA0 */ + uint8_t RESERVED_10[12]; + __I uint32_t PACKET3; /**< DCP work packet 3 status register, offset: 0xB0 */ + uint8_t RESERVED_11[12]; + __I uint32_t PACKET4; /**< DCP work packet 4 status register, offset: 0xC0 */ + uint8_t RESERVED_12[12]; + __I uint32_t PACKET5; /**< DCP work packet 5 status register, offset: 0xD0 */ + uint8_t RESERVED_13[12]; + __I uint32_t PACKET6; /**< DCP work packet 6 status register, offset: 0xE0 */ + uint8_t RESERVED_14[28]; + __IO uint32_t CH0CMDPTR; /**< DCP channel 0 command pointer address register, offset: 0x100 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CH0SEMA; /**< DCP channel 0 semaphore register, offset: 0x110 */ + uint8_t RESERVED_16[12]; + __IO uint32_t CH0STAT; /**< DCP channel 0 status register, offset: 0x120 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CH0OPTS; /**< DCP channel 0 options register, offset: 0x130 */ + uint8_t RESERVED_18[12]; + __IO uint32_t CH1CMDPTR; /**< DCP channel 1 command pointer address register, offset: 0x140 */ + uint8_t RESERVED_19[12]; + __IO uint32_t CH1SEMA; /**< DCP channel 1 semaphore register, offset: 0x150 */ + uint8_t RESERVED_20[12]; + __IO uint32_t CH1STAT; /**< DCP channel 1 status register, offset: 0x160 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CH1OPTS; /**< DCP channel 1 options register, offset: 0x170 */ + uint8_t RESERVED_22[12]; + __IO uint32_t CH2CMDPTR; /**< DCP channel 2 command pointer address register, offset: 0x180 */ + uint8_t RESERVED_23[12]; + __IO uint32_t CH2SEMA; /**< DCP channel 2 semaphore register, offset: 0x190 */ + uint8_t RESERVED_24[12]; + __IO uint32_t CH2STAT; /**< DCP channel 2 status register, offset: 0x1A0 */ + uint8_t RESERVED_25[12]; + __IO uint32_t CH2OPTS; /**< DCP channel 2 options register, offset: 0x1B0 */ + uint8_t RESERVED_26[12]; + __IO uint32_t CH3CMDPTR; /**< DCP channel 3 command pointer address register, offset: 0x1C0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t CH3SEMA; /**< DCP channel 3 semaphore register, offset: 0x1D0 */ + uint8_t RESERVED_28[12]; + __IO uint32_t CH3STAT; /**< DCP channel 3 status register, offset: 0x1E0 */ + uint8_t RESERVED_29[12]; + __IO uint32_t CH3OPTS; /**< DCP channel 3 options register, offset: 0x1F0 */ + uint8_t RESERVED_30[524]; + __IO uint32_t DBGSELECT; /**< DCP debug select register, offset: 0x400 */ + uint8_t RESERVED_31[12]; + __I uint32_t DBGDATA; /**< DCP debug data register, offset: 0x410 */ + uint8_t RESERVED_32[12]; + __IO uint32_t PAGETABLE; /**< DCP page table register, offset: 0x420 */ + uint8_t RESERVED_33[12]; + __I uint32_t VERSION; /**< DCP version register, offset: 0x430 */ +} DCP_Type; + +/* ---------------------------------------------------------------------------- + -- DCP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCP_Register_Masks DCP Register Masks + * @{ + */ + +/*! @name CTRL - DCP control register 0 */ +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK) +#define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U) +#define DCP_CTRL_PRESENT_SHA_SHIFT (28U) +#define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK) +#define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U) +#define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U) +#define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK) +#define DCP_CTRL_CLKGATE_MASK (0x40000000U) +#define DCP_CTRL_CLKGATE_SHIFT (30U) +#define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK) +#define DCP_CTRL_SFTRST_MASK (0x80000000U) +#define DCP_CTRL_SFTRST_SHIFT (31U) +#define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK) + +/*! @name STAT - DCP status register */ +#define DCP_STAT_IRQ_MASK (0xFU) +#define DCP_STAT_IRQ_SHIFT (0U) +#define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK) +#define DCP_STAT_RSVD_IRQ_MASK (0x100U) +#define DCP_STAT_RSVD_IRQ_SHIFT (8U) +#define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK) +#define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U) +#define DCP_STAT_READY_CHANNELS_SHIFT (16U) +#define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK) +#define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U) +#define DCP_STAT_CUR_CHANNEL_SHIFT (24U) +#define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK) +#define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U) +#define DCP_STAT_OTP_KEY_READY_SHIFT (28U) +#define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK) + +/*! @name CHANNELCTRL - DCP channel control register */ +#define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU) +#define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U) +#define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK) +#define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U) +#define DCP_CHANNELCTRL_RSVD_SHIFT (17U) +#define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK) + +/*! @name CAPABILITY0 - DCP capability 0 register */ +#define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU) +#define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U) +#define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK) +#define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U) +#define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U) +#define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK) +#define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U) +#define DCP_CAPABILITY0_RSVD_SHIFT (12U) +#define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK) +#define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U) +#define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U) +#define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK) + +/*! @name CAPABILITY1 - DCP capability 1 register */ +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU) +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U) +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK) +#define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U) +#define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U) +#define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK) + +/*! @name CONTEXT - DCP context buffer pointer */ +#define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CONTEXT_ADDR_SHIFT (0U) +#define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK) + +/*! @name KEY - DCP key index */ +#define DCP_KEY_SUBWORD_MASK (0x3U) +#define DCP_KEY_SUBWORD_SHIFT (0U) +#define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK) +#define DCP_KEY_RSVD_SUBWORD_MASK (0xCU) +#define DCP_KEY_RSVD_SUBWORD_SHIFT (2U) +#define DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK) +#define DCP_KEY_INDEX_MASK (0x30U) +#define DCP_KEY_INDEX_SHIFT (4U) +#define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK) +#define DCP_KEY_RSVD_INDEX_MASK (0xC0U) +#define DCP_KEY_RSVD_INDEX_SHIFT (6U) +#define DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK) +#define DCP_KEY_RSVD_MASK (0xFFFFFF00U) +#define DCP_KEY_RSVD_SHIFT (8U) +#define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK) + +/*! @name KEYDATA - DCP key data */ +#define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU) +#define DCP_KEYDATA_DATA_SHIFT (0U) +#define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK) + +/*! @name PACKET0 - DCP work packet 0 status register */ +#define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET0_ADDR_SHIFT (0U) +#define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK) + +/*! @name PACKET1 - DCP work packet 1 status register */ +#define DCP_PACKET1_INTERRUPT_MASK (0x1U) +#define DCP_PACKET1_INTERRUPT_SHIFT (0U) +#define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK) +#define DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U) +#define DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U) +#define DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK) +#define DCP_PACKET1_CHAIN_MASK (0x4U) +#define DCP_PACKET1_CHAIN_SHIFT (2U) +#define DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK) +#define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U) +#define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U) +#define DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK) +#define DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U) +#define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U) +#define DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK) +#define DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U) +#define DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U) +#define DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK) +#define DCP_PACKET1_ENABLE_HASH_MASK (0x40U) +#define DCP_PACKET1_ENABLE_HASH_SHIFT (6U) +#define DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK) +#define DCP_PACKET1_ENABLE_BLIT_MASK (0x80U) +#define DCP_PACKET1_ENABLE_BLIT_SHIFT (7U) +#define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK) +#define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U) +#define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U) +#define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK) +#define DCP_PACKET1_CIPHER_INIT_MASK (0x200U) +#define DCP_PACKET1_CIPHER_INIT_SHIFT (9U) +#define DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK) +#define DCP_PACKET1_OTP_KEY_MASK (0x400U) +#define DCP_PACKET1_OTP_KEY_SHIFT (10U) +#define DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK) +#define DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U) +#define DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U) +#define DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK) +#define DCP_PACKET1_HASH_INIT_MASK (0x1000U) +#define DCP_PACKET1_HASH_INIT_SHIFT (12U) +#define DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK) +#define DCP_PACKET1_HASH_TERM_MASK (0x2000U) +#define DCP_PACKET1_HASH_TERM_SHIFT (13U) +#define DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK) +#define DCP_PACKET1_CHECK_HASH_MASK (0x4000U) +#define DCP_PACKET1_CHECK_HASH_SHIFT (14U) +#define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK) +#define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U) +#define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U) +#define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK) +#define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U) +#define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U) +#define DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK) +#define DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U) +#define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U) +#define DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK) +#define DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U) +#define DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U) +#define DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK) +#define DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U) +#define DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U) +#define DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK) +#define DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U) +#define DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U) +#define DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK) +#define DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U) +#define DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U) +#define DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK) +#define DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U) +#define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U) +#define DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK) +#define DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U) +#define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U) +#define DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK) +#define DCP_PACKET1_TAG_MASK (0xFF000000U) +#define DCP_PACKET1_TAG_SHIFT (24U) +#define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK) + +/*! @name PACKET2 - DCP work packet 2 status register */ +#define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU) +#define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U) +#define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK) +#define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U) +#define DCP_PACKET2_CIPHER_MODE_SHIFT (4U) +#define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK) +#define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U) +#define DCP_PACKET2_KEY_SELECT_SHIFT (8U) +#define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK) +#define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U) +#define DCP_PACKET2_HASH_SELECT_SHIFT (16U) +#define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK) +#define DCP_PACKET2_RSVD_MASK (0xF00000U) +#define DCP_PACKET2_RSVD_SHIFT (20U) +#define DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK) +#define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U) +#define DCP_PACKET2_CIPHER_CFG_SHIFT (24U) +#define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK) + +/*! @name PACKET3 - DCP work packet 3 status register */ +#define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET3_ADDR_SHIFT (0U) +#define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK) + +/*! @name PACKET4 - DCP work packet 4 status register */ +#define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET4_ADDR_SHIFT (0U) +#define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK) + +/*! @name PACKET5 - DCP work packet 5 status register */ +#define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU) +#define DCP_PACKET5_COUNT_SHIFT (0U) +#define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK) + +/*! @name PACKET6 - DCP work packet 6 status register */ +#define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET6_ADDR_SHIFT (0U) +#define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK) + +/*! @name CH0CMDPTR - DCP channel 0 command pointer address register */ +#define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH0CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK) + +/*! @name CH0SEMA - DCP channel 0 semaphore register */ +#define DCP_CH0SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH0SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK) +#define DCP_CH0SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH0SEMA_VALUE_SHIFT (16U) +#define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK) + +/*! @name CH0STAT - DCP channel 0 status register */ +#define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK) +#define DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK) +#define DCP_CH0STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH0STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK) +#define DCP_CH0STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH0STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK) +#define DCP_CH0STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH0STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK) +#define DCP_CH0STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH0STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK) +#define DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH0STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK) +#define DCP_CH0STAT_TAG_MASK (0xFF000000U) +#define DCP_CH0STAT_TAG_SHIFT (24U) +#define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK) + +/*! @name CH0OPTS - DCP channel 0 options register */ +#define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH0OPTS_RSVD_SHIFT (16U) +#define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK) + +/*! @name CH1CMDPTR - DCP channel 1 command pointer address register */ +#define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH1CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK) + +/*! @name CH1SEMA - DCP channel 1 semaphore register */ +#define DCP_CH1SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH1SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK) +#define DCP_CH1SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH1SEMA_VALUE_SHIFT (16U) +#define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK) + +/*! @name CH1STAT - DCP channel 1 status register */ +#define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK) +#define DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK) +#define DCP_CH1STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH1STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK) +#define DCP_CH1STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH1STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK) +#define DCP_CH1STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH1STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK) +#define DCP_CH1STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH1STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK) +#define DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH1STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK) +#define DCP_CH1STAT_TAG_MASK (0xFF000000U) +#define DCP_CH1STAT_TAG_SHIFT (24U) +#define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK) + +/*! @name CH1OPTS - DCP channel 1 options register */ +#define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH1OPTS_RSVD_SHIFT (16U) +#define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK) + +/*! @name CH2CMDPTR - DCP channel 2 command pointer address register */ +#define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH2CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK) + +/*! @name CH2SEMA - DCP channel 2 semaphore register */ +#define DCP_CH2SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH2SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK) +#define DCP_CH2SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH2SEMA_VALUE_SHIFT (16U) +#define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK) + +/*! @name CH2STAT - DCP channel 2 status register */ +#define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK) +#define DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK) +#define DCP_CH2STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH2STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK) +#define DCP_CH2STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH2STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK) +#define DCP_CH2STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH2STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK) +#define DCP_CH2STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH2STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK) +#define DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH2STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK) +#define DCP_CH2STAT_TAG_MASK (0xFF000000U) +#define DCP_CH2STAT_TAG_SHIFT (24U) +#define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK) + +/*! @name CH2OPTS - DCP channel 2 options register */ +#define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH2OPTS_RSVD_SHIFT (16U) +#define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK) + +/*! @name CH3CMDPTR - DCP channel 3 command pointer address register */ +#define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH3CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK) + +/*! @name CH3SEMA - DCP channel 3 semaphore register */ +#define DCP_CH3SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH3SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK) +#define DCP_CH3SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH3SEMA_VALUE_SHIFT (16U) +#define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK) + +/*! @name CH3STAT - DCP channel 3 status register */ +#define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK) +#define DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK) +#define DCP_CH3STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH3STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK) +#define DCP_CH3STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH3STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK) +#define DCP_CH3STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH3STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK) +#define DCP_CH3STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH3STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK) +#define DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH3STAT_ERROR_CODE_SHIFT (16U) +#define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK) +#define DCP_CH3STAT_TAG_MASK (0xFF000000U) +#define DCP_CH3STAT_TAG_SHIFT (24U) +#define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK) + +/*! @name CH3OPTS - DCP channel 3 options register */ +#define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH3OPTS_RSVD_SHIFT (16U) +#define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK) + +/*! @name DBGSELECT - DCP debug select register */ +#define DCP_DBGSELECT_INDEX_MASK (0xFFU) +#define DCP_DBGSELECT_INDEX_SHIFT (0U) +#define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK) +#define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U) +#define DCP_DBGSELECT_RSVD_SHIFT (8U) +#define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK) + +/*! @name DBGDATA - DCP debug data register */ +#define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU) +#define DCP_DBGDATA_DATA_SHIFT (0U) +#define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK) + +/*! @name PAGETABLE - DCP page table register */ +#define DCP_PAGETABLE_ENABLE_MASK (0x1U) +#define DCP_PAGETABLE_ENABLE_SHIFT (0U) +#define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK) +#define DCP_PAGETABLE_FLUSH_MASK (0x2U) +#define DCP_PAGETABLE_FLUSH_SHIFT (1U) +#define DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK) +#define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU) +#define DCP_PAGETABLE_BASE_SHIFT (2U) +#define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK) + +/*! @name VERSION - DCP version register */ +#define DCP_VERSION_STEP_MASK (0xFFFFU) +#define DCP_VERSION_STEP_SHIFT (0U) +#define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK) +#define DCP_VERSION_MINOR_MASK (0xFF0000U) +#define DCP_VERSION_MINOR_SHIFT (16U) +#define DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK) +#define DCP_VERSION_MAJOR_MASK (0xFF000000U) +#define DCP_VERSION_MAJOR_SHIFT (24U) +#define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK) + + +/*! + * @} + */ /* end of group DCP_Register_Masks */ + + +/* DCP - Peripheral instance base addresses */ +/** Peripheral DCP base address */ +#define DCP_BASE (0x2280000u) +/** Peripheral DCP base pointer */ +#define DCP ((DCP_Type *)DCP_BASE) +/** Array initializer of DCP peripheral base addresses */ +#define DCP_BASE_ADDRS { DCP_BASE } +/** Array initializer of DCP peripheral base pointers */ +#define DCP_BASE_PTRS { DCP } +/** Interrupt vectors for the DCP peripheral type */ +#define DCP_IRQS { DCP_IRQ_IRQn } +#define DCP_VMI_IRQS { DCP_VMI_IRQ_IRQn } +#define DCP_SEC_IRQS { DCP_SEC_IRQ_IRQn } + +/*! + * @} + */ /* end of group DCP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ECSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSPI_Peripheral_Access_Layer ECSPI Peripheral Access Layer + * @{ + */ + +/** ECSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t RXDATA; /**< Receive Data Register, offset: 0x0 */ + __O uint32_t TXDATA; /**< Transmit Data Register, offset: 0x4 */ + __IO uint32_t CONREG; /**< Control Register, offset: 0x8 */ + __IO uint32_t CONFIGREG; /**< Config Register, offset: 0xC */ + __IO uint32_t INTREG; /**< Interrupt Control Register, offset: 0x10 */ + __IO uint32_t DMAREG; /**< DMA Control Register, offset: 0x14 */ + __IO uint32_t STATREG; /**< Status Register, offset: 0x18 */ + __IO uint32_t PERIODREG; /**< Sample Period Control Register, offset: 0x1C */ + __IO uint32_t TESTREG; /**< Test Control Register, offset: 0x20 */ + uint8_t RESERVED_0[28]; + __O uint32_t MSGDATA; /**< Message Data Register, offset: 0x40 */ +} ECSPI_Type; + +/* ---------------------------------------------------------------------------- + -- ECSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSPI_Register_Masks ECSPI Register Masks + * @{ + */ + +/*! @name RXDATA - Receive Data Register */ +#define ECSPI_RXDATA_ECSPI_RXDATA_MASK (0xFFFFFFFFU) +#define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT (0U) +#define ECSPI_RXDATA_ECSPI_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_RXDATA_ECSPI_RXDATA_SHIFT)) & ECSPI_RXDATA_ECSPI_RXDATA_MASK) + +/*! @name TXDATA - Transmit Data Register */ +#define ECSPI_TXDATA_ECSPI_TXDATA_MASK (0xFFFFFFFFU) +#define ECSPI_TXDATA_ECSPI_TXDATA_SHIFT (0U) +#define ECSPI_TXDATA_ECSPI_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TXDATA_ECSPI_TXDATA_SHIFT)) & ECSPI_TXDATA_ECSPI_TXDATA_MASK) + +/*! @name CONREG - Control Register */ +#define ECSPI_CONREG_EN_MASK (0x1U) +#define ECSPI_CONREG_EN_SHIFT (0U) +#define ECSPI_CONREG_EN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_EN_SHIFT)) & ECSPI_CONREG_EN_MASK) +#define ECSPI_CONREG_HT_MASK (0x2U) +#define ECSPI_CONREG_HT_SHIFT (1U) +#define ECSPI_CONREG_HT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_HT_SHIFT)) & ECSPI_CONREG_HT_MASK) +#define ECSPI_CONREG_XCH_MASK (0x4U) +#define ECSPI_CONREG_XCH_SHIFT (2U) +#define ECSPI_CONREG_XCH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_XCH_SHIFT)) & ECSPI_CONREG_XCH_MASK) +#define ECSPI_CONREG_SMC_MASK (0x8U) +#define ECSPI_CONREG_SMC_SHIFT (3U) +#define ECSPI_CONREG_SMC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_SMC_SHIFT)) & ECSPI_CONREG_SMC_MASK) +#define ECSPI_CONREG_CHANNEL_MODE_MASK (0xF0U) +#define ECSPI_CONREG_CHANNEL_MODE_SHIFT (4U) +#define ECSPI_CONREG_CHANNEL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_MODE_SHIFT)) & ECSPI_CONREG_CHANNEL_MODE_MASK) +#define ECSPI_CONREG_POST_DIVIDER_MASK (0xF00U) +#define ECSPI_CONREG_POST_DIVIDER_SHIFT (8U) +#define ECSPI_CONREG_POST_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_POST_DIVIDER_SHIFT)) & ECSPI_CONREG_POST_DIVIDER_MASK) +#define ECSPI_CONREG_PRE_DIVIDER_MASK (0xF000U) +#define ECSPI_CONREG_PRE_DIVIDER_SHIFT (12U) +#define ECSPI_CONREG_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_PRE_DIVIDER_SHIFT)) & ECSPI_CONREG_PRE_DIVIDER_MASK) +#define ECSPI_CONREG_DRCTL_MASK (0x30000U) +#define ECSPI_CONREG_DRCTL_SHIFT (16U) +#define ECSPI_CONREG_DRCTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_DRCTL_SHIFT)) & ECSPI_CONREG_DRCTL_MASK) +#define ECSPI_CONREG_CHANNEL_SELECT_MASK (0xC0000U) +#define ECSPI_CONREG_CHANNEL_SELECT_SHIFT (18U) +#define ECSPI_CONREG_CHANNEL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_SELECT_SHIFT)) & ECSPI_CONREG_CHANNEL_SELECT_MASK) +#define ECSPI_CONREG_BURST_LENGTH_MASK (0xFFF00000U) +#define ECSPI_CONREG_BURST_LENGTH_SHIFT (20U) +#define ECSPI_CONREG_BURST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_BURST_LENGTH_SHIFT)) & ECSPI_CONREG_BURST_LENGTH_MASK) + +/*! @name CONFIGREG - Config Register */ +#define ECSPI_CONFIGREG_SCLK_PHA_MASK (0xFU) +#define ECSPI_CONFIGREG_SCLK_PHA_SHIFT (0U) +#define ECSPI_CONFIGREG_SCLK_PHA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_PHA_SHIFT)) & ECSPI_CONFIGREG_SCLK_PHA_MASK) +#define ECSPI_CONFIGREG_SCLK_POL_MASK (0xF0U) +#define ECSPI_CONFIGREG_SCLK_POL_SHIFT (4U) +#define ECSPI_CONFIGREG_SCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_POL_SHIFT)) & ECSPI_CONFIGREG_SCLK_POL_MASK) +#define ECSPI_CONFIGREG_SS_CTL_MASK (0xF00U) +#define ECSPI_CONFIGREG_SS_CTL_SHIFT (8U) +#define ECSPI_CONFIGREG_SS_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_CTL_SHIFT)) & ECSPI_CONFIGREG_SS_CTL_MASK) +#define ECSPI_CONFIGREG_SS_POL_MASK (0xF000U) +#define ECSPI_CONFIGREG_SS_POL_SHIFT (12U) +#define ECSPI_CONFIGREG_SS_POL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_POL_SHIFT)) & ECSPI_CONFIGREG_SS_POL_MASK) +#define ECSPI_CONFIGREG_DATA_CTL_MASK (0xF0000U) +#define ECSPI_CONFIGREG_DATA_CTL_SHIFT (16U) +#define ECSPI_CONFIGREG_DATA_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_DATA_CTL_SHIFT)) & ECSPI_CONFIGREG_DATA_CTL_MASK) +#define ECSPI_CONFIGREG_SCLK_CTL_MASK (0xF00000U) +#define ECSPI_CONFIGREG_SCLK_CTL_SHIFT (20U) +#define ECSPI_CONFIGREG_SCLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_CTL_SHIFT)) & ECSPI_CONFIGREG_SCLK_CTL_MASK) +#define ECSPI_CONFIGREG_HT_LENGTH_MASK (0x1F000000U) +#define ECSPI_CONFIGREG_HT_LENGTH_SHIFT (24U) +#define ECSPI_CONFIGREG_HT_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_HT_LENGTH_SHIFT)) & ECSPI_CONFIGREG_HT_LENGTH_MASK) + +/*! @name INTREG - Interrupt Control Register */ +#define ECSPI_INTREG_TEEN_MASK (0x1U) +#define ECSPI_INTREG_TEEN_SHIFT (0U) +#define ECSPI_INTREG_TEEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TEEN_SHIFT)) & ECSPI_INTREG_TEEN_MASK) +#define ECSPI_INTREG_TDREN_MASK (0x2U) +#define ECSPI_INTREG_TDREN_SHIFT (1U) +#define ECSPI_INTREG_TDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TDREN_SHIFT)) & ECSPI_INTREG_TDREN_MASK) +#define ECSPI_INTREG_TFEN_MASK (0x4U) +#define ECSPI_INTREG_TFEN_SHIFT (2U) +#define ECSPI_INTREG_TFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TFEN_SHIFT)) & ECSPI_INTREG_TFEN_MASK) +#define ECSPI_INTREG_RREN_MASK (0x8U) +#define ECSPI_INTREG_RREN_SHIFT (3U) +#define ECSPI_INTREG_RREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RREN_SHIFT)) & ECSPI_INTREG_RREN_MASK) +#define ECSPI_INTREG_RDREN_MASK (0x10U) +#define ECSPI_INTREG_RDREN_SHIFT (4U) +#define ECSPI_INTREG_RDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RDREN_SHIFT)) & ECSPI_INTREG_RDREN_MASK) +#define ECSPI_INTREG_RFEN_MASK (0x20U) +#define ECSPI_INTREG_RFEN_SHIFT (5U) +#define ECSPI_INTREG_RFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RFEN_SHIFT)) & ECSPI_INTREG_RFEN_MASK) +#define ECSPI_INTREG_ROEN_MASK (0x40U) +#define ECSPI_INTREG_ROEN_SHIFT (6U) +#define ECSPI_INTREG_ROEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_ROEN_SHIFT)) & ECSPI_INTREG_ROEN_MASK) +#define ECSPI_INTREG_TCEN_MASK (0x80U) +#define ECSPI_INTREG_TCEN_SHIFT (7U) +#define ECSPI_INTREG_TCEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TCEN_SHIFT)) & ECSPI_INTREG_TCEN_MASK) + +/*! @name DMAREG - DMA Control Register */ +#define ECSPI_DMAREG_TX_THRESHOLD_MASK (0x3FU) +#define ECSPI_DMAREG_TX_THRESHOLD_SHIFT (0U) +#define ECSPI_DMAREG_TX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_TX_THRESHOLD_MASK) +#define ECSPI_DMAREG_TEDEN_MASK (0x80U) +#define ECSPI_DMAREG_TEDEN_SHIFT (7U) +#define ECSPI_DMAREG_TEDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TEDEN_SHIFT)) & ECSPI_DMAREG_TEDEN_MASK) +#define ECSPI_DMAREG_RX_THRESHOLD_MASK (0x3F0000U) +#define ECSPI_DMAREG_RX_THRESHOLD_SHIFT (16U) +#define ECSPI_DMAREG_RX_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_RX_THRESHOLD_MASK) +#define ECSPI_DMAREG_RXDEN_MASK (0x800000U) +#define ECSPI_DMAREG_RXDEN_SHIFT (23U) +#define ECSPI_DMAREG_RXDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXDEN_SHIFT)) & ECSPI_DMAREG_RXDEN_MASK) +#define ECSPI_DMAREG_RX_DMA_LENGTH_MASK (0x3F000000U) +#define ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT (24U) +#define ECSPI_DMAREG_RX_DMA_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT)) & ECSPI_DMAREG_RX_DMA_LENGTH_MASK) +#define ECSPI_DMAREG_RXTDEN_MASK (0x80000000U) +#define ECSPI_DMAREG_RXTDEN_SHIFT (31U) +#define ECSPI_DMAREG_RXTDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXTDEN_SHIFT)) & ECSPI_DMAREG_RXTDEN_MASK) + +/*! @name STATREG - Status Register */ +#define ECSPI_STATREG_TE_MASK (0x1U) +#define ECSPI_STATREG_TE_SHIFT (0U) +#define ECSPI_STATREG_TE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TE_SHIFT)) & ECSPI_STATREG_TE_MASK) +#define ECSPI_STATREG_TDR_MASK (0x2U) +#define ECSPI_STATREG_TDR_SHIFT (1U) +#define ECSPI_STATREG_TDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TDR_SHIFT)) & ECSPI_STATREG_TDR_MASK) +#define ECSPI_STATREG_TF_MASK (0x4U) +#define ECSPI_STATREG_TF_SHIFT (2U) +#define ECSPI_STATREG_TF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TF_SHIFT)) & ECSPI_STATREG_TF_MASK) +#define ECSPI_STATREG_RR_MASK (0x8U) +#define ECSPI_STATREG_RR_SHIFT (3U) +#define ECSPI_STATREG_RR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RR_SHIFT)) & ECSPI_STATREG_RR_MASK) +#define ECSPI_STATREG_RDR_MASK (0x10U) +#define ECSPI_STATREG_RDR_SHIFT (4U) +#define ECSPI_STATREG_RDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RDR_SHIFT)) & ECSPI_STATREG_RDR_MASK) +#define ECSPI_STATREG_RF_MASK (0x20U) +#define ECSPI_STATREG_RF_SHIFT (5U) +#define ECSPI_STATREG_RF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RF_SHIFT)) & ECSPI_STATREG_RF_MASK) +#define ECSPI_STATREG_RO_MASK (0x40U) +#define ECSPI_STATREG_RO_SHIFT (6U) +#define ECSPI_STATREG_RO(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RO_SHIFT)) & ECSPI_STATREG_RO_MASK) +#define ECSPI_STATREG_TC_MASK (0x80U) +#define ECSPI_STATREG_TC_SHIFT (7U) +#define ECSPI_STATREG_TC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TC_SHIFT)) & ECSPI_STATREG_TC_MASK) + +/*! @name PERIODREG - Sample Period Control Register */ +#define ECSPI_PERIODREG_SAMPLE_PERIOD_MASK (0x7FFFU) +#define ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT (0U) +#define ECSPI_PERIODREG_SAMPLE_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT)) & ECSPI_PERIODREG_SAMPLE_PERIOD_MASK) +#define ECSPI_PERIODREG_CSRC_MASK (0x8000U) +#define ECSPI_PERIODREG_CSRC_SHIFT (15U) +#define ECSPI_PERIODREG_CSRC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSRC_SHIFT)) & ECSPI_PERIODREG_CSRC_MASK) +#define ECSPI_PERIODREG_CSD_CTL_MASK (0x3F0000U) +#define ECSPI_PERIODREG_CSD_CTL_SHIFT (16U) +#define ECSPI_PERIODREG_CSD_CTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSD_CTL_SHIFT)) & ECSPI_PERIODREG_CSD_CTL_MASK) + +/*! @name TESTREG - Test Control Register */ +#define ECSPI_TESTREG_TXCNT_MASK (0x7FU) +#define ECSPI_TESTREG_TXCNT_SHIFT (0U) +#define ECSPI_TESTREG_TXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_TXCNT_SHIFT)) & ECSPI_TESTREG_TXCNT_MASK) +#define ECSPI_TESTREG_RXCNT_MASK (0x7F00U) +#define ECSPI_TESTREG_RXCNT_SHIFT (8U) +#define ECSPI_TESTREG_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_RXCNT_SHIFT)) & ECSPI_TESTREG_RXCNT_MASK) +#define ECSPI_TESTREG_LBC_MASK (0x80000000U) +#define ECSPI_TESTREG_LBC_SHIFT (31U) +#define ECSPI_TESTREG_LBC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_LBC_SHIFT)) & ECSPI_TESTREG_LBC_MASK) + +/*! @name MSGDATA - Message Data Register */ +#define ECSPI_MSGDATA_ECSPI_MSGDATA_MASK (0xFFFFFFFFU) +#define ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT (0U) +#define ECSPI_MSGDATA_ECSPI_MSGDATA(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT)) & ECSPI_MSGDATA_ECSPI_MSGDATA_MASK) + + +/*! + * @} + */ /* end of group ECSPI_Register_Masks */ + + +/* ECSPI - Peripheral instance base addresses */ +/** Peripheral ECSPI1 base address */ +#define ECSPI1_BASE (0x2008000u) +/** Peripheral ECSPI1 base pointer */ +#define ECSPI1 ((ECSPI_Type *)ECSPI1_BASE) +/** Peripheral ECSPI2 base address */ +#define ECSPI2_BASE (0x200C000u) +/** Peripheral ECSPI2 base pointer */ +#define ECSPI2 ((ECSPI_Type *)ECSPI2_BASE) +/** Peripheral ECSPI3 base address */ +#define ECSPI3_BASE (0x2010000u) +/** Peripheral ECSPI3 base pointer */ +#define ECSPI3 ((ECSPI_Type *)ECSPI3_BASE) +/** Peripheral ECSPI4 base address */ +#define ECSPI4_BASE (0x2014000u) +/** Peripheral ECSPI4 base pointer */ +#define ECSPI4 ((ECSPI_Type *)ECSPI4_BASE) +/** Array initializer of ECSPI peripheral base addresses */ +#define ECSPI_BASE_ADDRS { 0u, ECSPI1_BASE, ECSPI2_BASE, ECSPI3_BASE, ECSPI4_BASE } +/** Array initializer of ECSPI peripheral base pointers */ +#define ECSPI_BASE_PTRS { (ECSPI_Type *)0u, ECSPI1, ECSPI2, ECSPI3, ECSPI4 } +/** Interrupt vectors for the ECSPI peripheral type */ +#define ECSPI_IRQS { NotAvail_IRQn, eCSPI1_IRQn, eCSPI2_IRQn, eCSPI3_IRQn, eCSPI4_IRQn } + +/*! + * @} + */ /* end of group ECSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer + * @{ + */ + +/** EIM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CS0GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x0 */ + __IO uint32_t CS0GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x4 */ + __IO uint32_t CS0RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x8 */ + __IO uint32_t CS0RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0xC */ + __IO uint32_t CS0WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x10 */ + __IO uint32_t CS0WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x14 */ + __IO uint32_t CS1GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x18 */ + __IO uint32_t CS1GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x1C */ + __IO uint32_t CS1RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x20 */ + __IO uint32_t CS1RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x24 */ + __IO uint32_t CS1WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x28 */ + __IO uint32_t CS1WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x2C */ + __IO uint32_t CS2GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x30 */ + __IO uint32_t CS2GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x34 */ + __IO uint32_t CS2RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x38 */ + __IO uint32_t CS2RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x3C */ + __IO uint32_t CS2WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x40 */ + __IO uint32_t CS2WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x44 */ + __IO uint32_t CS3GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x48 */ + __IO uint32_t CS3GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x4C */ + __IO uint32_t CS3RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x50 */ + __IO uint32_t CS3RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x54 */ + __IO uint32_t CS3WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x58 */ + __IO uint32_t CS3WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x5C */ + __IO uint32_t CS4GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x60 */ + __IO uint32_t CS4GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x64 */ + __IO uint32_t CS4RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x68 */ + __IO uint32_t CS4RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x6C */ + __IO uint32_t CS4WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x70 */ + __IO uint32_t CS4WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x74 */ + __IO uint32_t CS5GCR1; /**< Chip Select n General Configuration Register 1, offset: 0x78 */ + __IO uint32_t CS5GCR2; /**< Chip Select n General Configuration Register 2, offset: 0x7C */ + __IO uint32_t CS5RCR1; /**< Chip Select n Read Configuration Register 1, offset: 0x80 */ + __IO uint32_t CS5RCR2; /**< Chip Select n Read Configuration Register 2, offset: 0x84 */ + __IO uint32_t CS5WCR1; /**< Chip Select n Write Configuration Register 1, offset: 0x88 */ + __IO uint32_t CS5WCR2; /**< Chip Select n Write Configuration Register 2, offset: 0x8C */ + __IO uint32_t WCR; /**< EIM Configuration Register, offset: 0x90 */ +} EIM_Type; + +/* ---------------------------------------------------------------------------- + -- EIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Register_Masks EIM Register Masks + * @{ + */ + +/*! @name CS0GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS0GCR1_CSEN_MASK (0x1U) +#define EIM_CS0GCR1_CSEN_SHIFT (0U) +#define EIM_CS0GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_CSEN_SHIFT)) & EIM_CS0GCR1_CSEN_MASK) +#define EIM_CS0GCR1_SWR_MASK (0x2U) +#define EIM_CS0GCR1_SWR_SHIFT (1U) +#define EIM_CS0GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_SWR_SHIFT)) & EIM_CS0GCR1_SWR_MASK) +#define EIM_CS0GCR1_SRD_MASK (0x4U) +#define EIM_CS0GCR1_SRD_SHIFT (2U) +#define EIM_CS0GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_SRD_SHIFT)) & EIM_CS0GCR1_SRD_MASK) +#define EIM_CS0GCR1_MUM_MASK (0x8U) +#define EIM_CS0GCR1_MUM_SHIFT (3U) +#define EIM_CS0GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_MUM_SHIFT)) & EIM_CS0GCR1_MUM_MASK) +#define EIM_CS0GCR1_WFL_MASK (0x10U) +#define EIM_CS0GCR1_WFL_SHIFT (4U) +#define EIM_CS0GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_WFL_SHIFT)) & EIM_CS0GCR1_WFL_MASK) +#define EIM_CS0GCR1_RFL_MASK (0x20U) +#define EIM_CS0GCR1_RFL_SHIFT (5U) +#define EIM_CS0GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_RFL_SHIFT)) & EIM_CS0GCR1_RFL_MASK) +#define EIM_CS0GCR1_CRE_MASK (0x40U) +#define EIM_CS0GCR1_CRE_SHIFT (6U) +#define EIM_CS0GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_CRE_SHIFT)) & EIM_CS0GCR1_CRE_MASK) +#define EIM_CS0GCR1_CREP_MASK (0x80U) +#define EIM_CS0GCR1_CREP_SHIFT (7U) +#define EIM_CS0GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_CREP_SHIFT)) & EIM_CS0GCR1_CREP_MASK) +#define EIM_CS0GCR1_BL_MASK (0x700U) +#define EIM_CS0GCR1_BL_SHIFT (8U) +#define EIM_CS0GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_BL_SHIFT)) & EIM_CS0GCR1_BL_MASK) +#define EIM_CS0GCR1_WC_MASK (0x800U) +#define EIM_CS0GCR1_WC_SHIFT (11U) +#define EIM_CS0GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_WC_SHIFT)) & EIM_CS0GCR1_WC_MASK) +#define EIM_CS0GCR1_BCD_MASK (0x3000U) +#define EIM_CS0GCR1_BCD_SHIFT (12U) +#define EIM_CS0GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_BCD_SHIFT)) & EIM_CS0GCR1_BCD_MASK) +#define EIM_CS0GCR1_BCS_MASK (0xC000U) +#define EIM_CS0GCR1_BCS_SHIFT (14U) +#define EIM_CS0GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_BCS_SHIFT)) & EIM_CS0GCR1_BCS_MASK) +#define EIM_CS0GCR1_DSZ_MASK (0x70000U) +#define EIM_CS0GCR1_DSZ_SHIFT (16U) +#define EIM_CS0GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_DSZ_SHIFT)) & EIM_CS0GCR1_DSZ_MASK) +#define EIM_CS0GCR1_SP_MASK (0x80000U) +#define EIM_CS0GCR1_SP_SHIFT (19U) +#define EIM_CS0GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_SP_SHIFT)) & EIM_CS0GCR1_SP_MASK) +#define EIM_CS0GCR1_CSREC_MASK (0x700000U) +#define EIM_CS0GCR1_CSREC_SHIFT (20U) +#define EIM_CS0GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_CSREC_SHIFT)) & EIM_CS0GCR1_CSREC_MASK) +#define EIM_CS0GCR1_AUS_MASK (0x800000U) +#define EIM_CS0GCR1_AUS_SHIFT (23U) +#define EIM_CS0GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_AUS_SHIFT)) & EIM_CS0GCR1_AUS_MASK) +#define EIM_CS0GCR1_GBC_MASK (0x7000000U) +#define EIM_CS0GCR1_GBC_SHIFT (24U) +#define EIM_CS0GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_GBC_SHIFT)) & EIM_CS0GCR1_GBC_MASK) +#define EIM_CS0GCR1_WP_MASK (0x8000000U) +#define EIM_CS0GCR1_WP_SHIFT (27U) +#define EIM_CS0GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_WP_SHIFT)) & EIM_CS0GCR1_WP_MASK) +#define EIM_CS0GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS0GCR1_PSZ_SHIFT (28U) +#define EIM_CS0GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR1_PSZ_SHIFT)) & EIM_CS0GCR1_PSZ_MASK) + +/*! @name CS0GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS0GCR2_ADH_MASK (0x3U) +#define EIM_CS0GCR2_ADH_SHIFT (0U) +#define EIM_CS0GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_ADH_SHIFT)) & EIM_CS0GCR2_ADH_MASK) +#define EIM_CS0GCR2_DAPS_MASK (0xF0U) +#define EIM_CS0GCR2_DAPS_SHIFT (4U) +#define EIM_CS0GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_DAPS_SHIFT)) & EIM_CS0GCR2_DAPS_MASK) +#define EIM_CS0GCR2_DAE_MASK (0x100U) +#define EIM_CS0GCR2_DAE_SHIFT (8U) +#define EIM_CS0GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_DAE_SHIFT)) & EIM_CS0GCR2_DAE_MASK) +#define EIM_CS0GCR2_DAP_MASK (0x200U) +#define EIM_CS0GCR2_DAP_SHIFT (9U) +#define EIM_CS0GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_DAP_SHIFT)) & EIM_CS0GCR2_DAP_MASK) +#define EIM_CS0GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS0GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS0GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS0GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS0RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS0RCR1_RCSN_MASK (0x7U) +#define EIM_CS0RCR1_RCSN_SHIFT (0U) +#define EIM_CS0RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RCSN_SHIFT)) & EIM_CS0RCR1_RCSN_MASK) +#define EIM_CS0RCR1_RCSA_MASK (0x70U) +#define EIM_CS0RCR1_RCSA_SHIFT (4U) +#define EIM_CS0RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RCSA_SHIFT)) & EIM_CS0RCR1_RCSA_MASK) +#define EIM_CS0RCR1_OEN_MASK (0x700U) +#define EIM_CS0RCR1_OEN_SHIFT (8U) +#define EIM_CS0RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_OEN_SHIFT)) & EIM_CS0RCR1_OEN_MASK) +#define EIM_CS0RCR1_OEA_MASK (0x7000U) +#define EIM_CS0RCR1_OEA_SHIFT (12U) +#define EIM_CS0RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_OEA_SHIFT)) & EIM_CS0RCR1_OEA_MASK) +#define EIM_CS0RCR1_RADVN_MASK (0x70000U) +#define EIM_CS0RCR1_RADVN_SHIFT (16U) +#define EIM_CS0RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RADVN_SHIFT)) & EIM_CS0RCR1_RADVN_MASK) +#define EIM_CS0RCR1_RAL_MASK (0x80000U) +#define EIM_CS0RCR1_RAL_SHIFT (19U) +#define EIM_CS0RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RAL_SHIFT)) & EIM_CS0RCR1_RAL_MASK) +#define EIM_CS0RCR1_RADVA_MASK (0x700000U) +#define EIM_CS0RCR1_RADVA_SHIFT (20U) +#define EIM_CS0RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RADVA_SHIFT)) & EIM_CS0RCR1_RADVA_MASK) +#define EIM_CS0RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS0RCR1_RWSC_SHIFT (24U) +#define EIM_CS0RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR1_RWSC_SHIFT)) & EIM_CS0RCR1_RWSC_MASK) + +/*! @name CS0RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS0RCR2_RBEN_MASK (0x7U) +#define EIM_CS0RCR2_RBEN_SHIFT (0U) +#define EIM_CS0RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_RBEN_SHIFT)) & EIM_CS0RCR2_RBEN_MASK) +#define EIM_CS0RCR2_RBE_MASK (0x8U) +#define EIM_CS0RCR2_RBE_SHIFT (3U) +#define EIM_CS0RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_RBE_SHIFT)) & EIM_CS0RCR2_RBE_MASK) +#define EIM_CS0RCR2_RBEA_MASK (0x70U) +#define EIM_CS0RCR2_RBEA_SHIFT (4U) +#define EIM_CS0RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_RBEA_SHIFT)) & EIM_CS0RCR2_RBEA_MASK) +#define EIM_CS0RCR2_RL_MASK (0x300U) +#define EIM_CS0RCR2_RL_SHIFT (8U) +#define EIM_CS0RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_RL_SHIFT)) & EIM_CS0RCR2_RL_MASK) +#define EIM_CS0RCR2_PAT_MASK (0x7000U) +#define EIM_CS0RCR2_PAT_SHIFT (12U) +#define EIM_CS0RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_PAT_SHIFT)) & EIM_CS0RCR2_PAT_MASK) +#define EIM_CS0RCR2_APR_MASK (0x8000U) +#define EIM_CS0RCR2_APR_SHIFT (15U) +#define EIM_CS0RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0RCR2_APR_SHIFT)) & EIM_CS0RCR2_APR_MASK) + +/*! @name CS0WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS0WCR1_WCSN_MASK (0x7U) +#define EIM_CS0WCR1_WCSN_SHIFT (0U) +#define EIM_CS0WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WCSN_SHIFT)) & EIM_CS0WCR1_WCSN_MASK) +#define EIM_CS0WCR1_WCSA_MASK (0x38U) +#define EIM_CS0WCR1_WCSA_SHIFT (3U) +#define EIM_CS0WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WCSA_SHIFT)) & EIM_CS0WCR1_WCSA_MASK) +#define EIM_CS0WCR1_WEN_MASK (0x1C0U) +#define EIM_CS0WCR1_WEN_SHIFT (6U) +#define EIM_CS0WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WEN_SHIFT)) & EIM_CS0WCR1_WEN_MASK) +#define EIM_CS0WCR1_WEA_MASK (0xE00U) +#define EIM_CS0WCR1_WEA_SHIFT (9U) +#define EIM_CS0WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WEA_SHIFT)) & EIM_CS0WCR1_WEA_MASK) +#define EIM_CS0WCR1_WBEN_MASK (0x7000U) +#define EIM_CS0WCR1_WBEN_SHIFT (12U) +#define EIM_CS0WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WBEN_SHIFT)) & EIM_CS0WCR1_WBEN_MASK) +#define EIM_CS0WCR1_WBEA_MASK (0x38000U) +#define EIM_CS0WCR1_WBEA_SHIFT (15U) +#define EIM_CS0WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WBEA_SHIFT)) & EIM_CS0WCR1_WBEA_MASK) +#define EIM_CS0WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS0WCR1_WADVN_SHIFT (18U) +#define EIM_CS0WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WADVN_SHIFT)) & EIM_CS0WCR1_WADVN_MASK) +#define EIM_CS0WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS0WCR1_WADVA_SHIFT (21U) +#define EIM_CS0WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WADVA_SHIFT)) & EIM_CS0WCR1_WADVA_MASK) +#define EIM_CS0WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS0WCR1_WWSC_SHIFT (24U) +#define EIM_CS0WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WWSC_SHIFT)) & EIM_CS0WCR1_WWSC_MASK) +#define EIM_CS0WCR1_WBED_MASK (0x40000000U) +#define EIM_CS0WCR1_WBED_SHIFT (30U) +#define EIM_CS0WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WBED_SHIFT)) & EIM_CS0WCR1_WBED_MASK) +#define EIM_CS0WCR1_WAL_MASK (0x80000000U) +#define EIM_CS0WCR1_WAL_SHIFT (31U) +#define EIM_CS0WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR1_WAL_SHIFT)) & EIM_CS0WCR1_WAL_MASK) + +/*! @name CS0WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS0WCR2_WBCDD_MASK (0x1U) +#define EIM_CS0WCR2_WBCDD_SHIFT (0U) +#define EIM_CS0WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS0WCR2_WBCDD_SHIFT)) & EIM_CS0WCR2_WBCDD_MASK) + +/*! @name CS1GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS1GCR1_CSEN_MASK (0x1U) +#define EIM_CS1GCR1_CSEN_SHIFT (0U) +#define EIM_CS1GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_CSEN_SHIFT)) & EIM_CS1GCR1_CSEN_MASK) +#define EIM_CS1GCR1_SWR_MASK (0x2U) +#define EIM_CS1GCR1_SWR_SHIFT (1U) +#define EIM_CS1GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_SWR_SHIFT)) & EIM_CS1GCR1_SWR_MASK) +#define EIM_CS1GCR1_SRD_MASK (0x4U) +#define EIM_CS1GCR1_SRD_SHIFT (2U) +#define EIM_CS1GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_SRD_SHIFT)) & EIM_CS1GCR1_SRD_MASK) +#define EIM_CS1GCR1_MUM_MASK (0x8U) +#define EIM_CS1GCR1_MUM_SHIFT (3U) +#define EIM_CS1GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_MUM_SHIFT)) & EIM_CS1GCR1_MUM_MASK) +#define EIM_CS1GCR1_WFL_MASK (0x10U) +#define EIM_CS1GCR1_WFL_SHIFT (4U) +#define EIM_CS1GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_WFL_SHIFT)) & EIM_CS1GCR1_WFL_MASK) +#define EIM_CS1GCR1_RFL_MASK (0x20U) +#define EIM_CS1GCR1_RFL_SHIFT (5U) +#define EIM_CS1GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_RFL_SHIFT)) & EIM_CS1GCR1_RFL_MASK) +#define EIM_CS1GCR1_CRE_MASK (0x40U) +#define EIM_CS1GCR1_CRE_SHIFT (6U) +#define EIM_CS1GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_CRE_SHIFT)) & EIM_CS1GCR1_CRE_MASK) +#define EIM_CS1GCR1_CREP_MASK (0x80U) +#define EIM_CS1GCR1_CREP_SHIFT (7U) +#define EIM_CS1GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_CREP_SHIFT)) & EIM_CS1GCR1_CREP_MASK) +#define EIM_CS1GCR1_BL_MASK (0x700U) +#define EIM_CS1GCR1_BL_SHIFT (8U) +#define EIM_CS1GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_BL_SHIFT)) & EIM_CS1GCR1_BL_MASK) +#define EIM_CS1GCR1_WC_MASK (0x800U) +#define EIM_CS1GCR1_WC_SHIFT (11U) +#define EIM_CS1GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_WC_SHIFT)) & EIM_CS1GCR1_WC_MASK) +#define EIM_CS1GCR1_BCD_MASK (0x3000U) +#define EIM_CS1GCR1_BCD_SHIFT (12U) +#define EIM_CS1GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_BCD_SHIFT)) & EIM_CS1GCR1_BCD_MASK) +#define EIM_CS1GCR1_BCS_MASK (0xC000U) +#define EIM_CS1GCR1_BCS_SHIFT (14U) +#define EIM_CS1GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_BCS_SHIFT)) & EIM_CS1GCR1_BCS_MASK) +#define EIM_CS1GCR1_DSZ_MASK (0x70000U) +#define EIM_CS1GCR1_DSZ_SHIFT (16U) +#define EIM_CS1GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_DSZ_SHIFT)) & EIM_CS1GCR1_DSZ_MASK) +#define EIM_CS1GCR1_SP_MASK (0x80000U) +#define EIM_CS1GCR1_SP_SHIFT (19U) +#define EIM_CS1GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_SP_SHIFT)) & EIM_CS1GCR1_SP_MASK) +#define EIM_CS1GCR1_CSREC_MASK (0x700000U) +#define EIM_CS1GCR1_CSREC_SHIFT (20U) +#define EIM_CS1GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_CSREC_SHIFT)) & EIM_CS1GCR1_CSREC_MASK) +#define EIM_CS1GCR1_AUS_MASK (0x800000U) +#define EIM_CS1GCR1_AUS_SHIFT (23U) +#define EIM_CS1GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_AUS_SHIFT)) & EIM_CS1GCR1_AUS_MASK) +#define EIM_CS1GCR1_GBC_MASK (0x7000000U) +#define EIM_CS1GCR1_GBC_SHIFT (24U) +#define EIM_CS1GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_GBC_SHIFT)) & EIM_CS1GCR1_GBC_MASK) +#define EIM_CS1GCR1_WP_MASK (0x8000000U) +#define EIM_CS1GCR1_WP_SHIFT (27U) +#define EIM_CS1GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_WP_SHIFT)) & EIM_CS1GCR1_WP_MASK) +#define EIM_CS1GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS1GCR1_PSZ_SHIFT (28U) +#define EIM_CS1GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR1_PSZ_SHIFT)) & EIM_CS1GCR1_PSZ_MASK) + +/*! @name CS1GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS1GCR2_ADH_MASK (0x3U) +#define EIM_CS1GCR2_ADH_SHIFT (0U) +#define EIM_CS1GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_ADH_SHIFT)) & EIM_CS1GCR2_ADH_MASK) +#define EIM_CS1GCR2_DAPS_MASK (0xF0U) +#define EIM_CS1GCR2_DAPS_SHIFT (4U) +#define EIM_CS1GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_DAPS_SHIFT)) & EIM_CS1GCR2_DAPS_MASK) +#define EIM_CS1GCR2_DAE_MASK (0x100U) +#define EIM_CS1GCR2_DAE_SHIFT (8U) +#define EIM_CS1GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_DAE_SHIFT)) & EIM_CS1GCR2_DAE_MASK) +#define EIM_CS1GCR2_DAP_MASK (0x200U) +#define EIM_CS1GCR2_DAP_SHIFT (9U) +#define EIM_CS1GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_DAP_SHIFT)) & EIM_CS1GCR2_DAP_MASK) +#define EIM_CS1GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS1GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS1GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS1GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS1RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS1RCR1_RCSN_MASK (0x7U) +#define EIM_CS1RCR1_RCSN_SHIFT (0U) +#define EIM_CS1RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RCSN_SHIFT)) & EIM_CS1RCR1_RCSN_MASK) +#define EIM_CS1RCR1_RCSA_MASK (0x70U) +#define EIM_CS1RCR1_RCSA_SHIFT (4U) +#define EIM_CS1RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RCSA_SHIFT)) & EIM_CS1RCR1_RCSA_MASK) +#define EIM_CS1RCR1_OEN_MASK (0x700U) +#define EIM_CS1RCR1_OEN_SHIFT (8U) +#define EIM_CS1RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_OEN_SHIFT)) & EIM_CS1RCR1_OEN_MASK) +#define EIM_CS1RCR1_OEA_MASK (0x7000U) +#define EIM_CS1RCR1_OEA_SHIFT (12U) +#define EIM_CS1RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_OEA_SHIFT)) & EIM_CS1RCR1_OEA_MASK) +#define EIM_CS1RCR1_RADVN_MASK (0x70000U) +#define EIM_CS1RCR1_RADVN_SHIFT (16U) +#define EIM_CS1RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RADVN_SHIFT)) & EIM_CS1RCR1_RADVN_MASK) +#define EIM_CS1RCR1_RAL_MASK (0x80000U) +#define EIM_CS1RCR1_RAL_SHIFT (19U) +#define EIM_CS1RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RAL_SHIFT)) & EIM_CS1RCR1_RAL_MASK) +#define EIM_CS1RCR1_RADVA_MASK (0x700000U) +#define EIM_CS1RCR1_RADVA_SHIFT (20U) +#define EIM_CS1RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RADVA_SHIFT)) & EIM_CS1RCR1_RADVA_MASK) +#define EIM_CS1RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS1RCR1_RWSC_SHIFT (24U) +#define EIM_CS1RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR1_RWSC_SHIFT)) & EIM_CS1RCR1_RWSC_MASK) + +/*! @name CS1RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS1RCR2_RBEN_MASK (0x7U) +#define EIM_CS1RCR2_RBEN_SHIFT (0U) +#define EIM_CS1RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_RBEN_SHIFT)) & EIM_CS1RCR2_RBEN_MASK) +#define EIM_CS1RCR2_RBE_MASK (0x8U) +#define EIM_CS1RCR2_RBE_SHIFT (3U) +#define EIM_CS1RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_RBE_SHIFT)) & EIM_CS1RCR2_RBE_MASK) +#define EIM_CS1RCR2_RBEA_MASK (0x70U) +#define EIM_CS1RCR2_RBEA_SHIFT (4U) +#define EIM_CS1RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_RBEA_SHIFT)) & EIM_CS1RCR2_RBEA_MASK) +#define EIM_CS1RCR2_RL_MASK (0x300U) +#define EIM_CS1RCR2_RL_SHIFT (8U) +#define EIM_CS1RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_RL_SHIFT)) & EIM_CS1RCR2_RL_MASK) +#define EIM_CS1RCR2_PAT_MASK (0x7000U) +#define EIM_CS1RCR2_PAT_SHIFT (12U) +#define EIM_CS1RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_PAT_SHIFT)) & EIM_CS1RCR2_PAT_MASK) +#define EIM_CS1RCR2_APR_MASK (0x8000U) +#define EIM_CS1RCR2_APR_SHIFT (15U) +#define EIM_CS1RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1RCR2_APR_SHIFT)) & EIM_CS1RCR2_APR_MASK) + +/*! @name CS1WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS1WCR1_WCSN_MASK (0x7U) +#define EIM_CS1WCR1_WCSN_SHIFT (0U) +#define EIM_CS1WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WCSN_SHIFT)) & EIM_CS1WCR1_WCSN_MASK) +#define EIM_CS1WCR1_WCSA_MASK (0x38U) +#define EIM_CS1WCR1_WCSA_SHIFT (3U) +#define EIM_CS1WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WCSA_SHIFT)) & EIM_CS1WCR1_WCSA_MASK) +#define EIM_CS1WCR1_WEN_MASK (0x1C0U) +#define EIM_CS1WCR1_WEN_SHIFT (6U) +#define EIM_CS1WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WEN_SHIFT)) & EIM_CS1WCR1_WEN_MASK) +#define EIM_CS1WCR1_WEA_MASK (0xE00U) +#define EIM_CS1WCR1_WEA_SHIFT (9U) +#define EIM_CS1WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WEA_SHIFT)) & EIM_CS1WCR1_WEA_MASK) +#define EIM_CS1WCR1_WBEN_MASK (0x7000U) +#define EIM_CS1WCR1_WBEN_SHIFT (12U) +#define EIM_CS1WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WBEN_SHIFT)) & EIM_CS1WCR1_WBEN_MASK) +#define EIM_CS1WCR1_WBEA_MASK (0x38000U) +#define EIM_CS1WCR1_WBEA_SHIFT (15U) +#define EIM_CS1WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WBEA_SHIFT)) & EIM_CS1WCR1_WBEA_MASK) +#define EIM_CS1WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS1WCR1_WADVN_SHIFT (18U) +#define EIM_CS1WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WADVN_SHIFT)) & EIM_CS1WCR1_WADVN_MASK) +#define EIM_CS1WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS1WCR1_WADVA_SHIFT (21U) +#define EIM_CS1WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WADVA_SHIFT)) & EIM_CS1WCR1_WADVA_MASK) +#define EIM_CS1WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS1WCR1_WWSC_SHIFT (24U) +#define EIM_CS1WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WWSC_SHIFT)) & EIM_CS1WCR1_WWSC_MASK) +#define EIM_CS1WCR1_WBED_MASK (0x40000000U) +#define EIM_CS1WCR1_WBED_SHIFT (30U) +#define EIM_CS1WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WBED_SHIFT)) & EIM_CS1WCR1_WBED_MASK) +#define EIM_CS1WCR1_WAL_MASK (0x80000000U) +#define EIM_CS1WCR1_WAL_SHIFT (31U) +#define EIM_CS1WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR1_WAL_SHIFT)) & EIM_CS1WCR1_WAL_MASK) + +/*! @name CS1WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS1WCR2_WBCDD_MASK (0x1U) +#define EIM_CS1WCR2_WBCDD_SHIFT (0U) +#define EIM_CS1WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS1WCR2_WBCDD_SHIFT)) & EIM_CS1WCR2_WBCDD_MASK) + +/*! @name CS2GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS2GCR1_CSEN_MASK (0x1U) +#define EIM_CS2GCR1_CSEN_SHIFT (0U) +#define EIM_CS2GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_CSEN_SHIFT)) & EIM_CS2GCR1_CSEN_MASK) +#define EIM_CS2GCR1_SWR_MASK (0x2U) +#define EIM_CS2GCR1_SWR_SHIFT (1U) +#define EIM_CS2GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_SWR_SHIFT)) & EIM_CS2GCR1_SWR_MASK) +#define EIM_CS2GCR1_SRD_MASK (0x4U) +#define EIM_CS2GCR1_SRD_SHIFT (2U) +#define EIM_CS2GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_SRD_SHIFT)) & EIM_CS2GCR1_SRD_MASK) +#define EIM_CS2GCR1_MUM_MASK (0x8U) +#define EIM_CS2GCR1_MUM_SHIFT (3U) +#define EIM_CS2GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_MUM_SHIFT)) & EIM_CS2GCR1_MUM_MASK) +#define EIM_CS2GCR1_WFL_MASK (0x10U) +#define EIM_CS2GCR1_WFL_SHIFT (4U) +#define EIM_CS2GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_WFL_SHIFT)) & EIM_CS2GCR1_WFL_MASK) +#define EIM_CS2GCR1_RFL_MASK (0x20U) +#define EIM_CS2GCR1_RFL_SHIFT (5U) +#define EIM_CS2GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_RFL_SHIFT)) & EIM_CS2GCR1_RFL_MASK) +#define EIM_CS2GCR1_CRE_MASK (0x40U) +#define EIM_CS2GCR1_CRE_SHIFT (6U) +#define EIM_CS2GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_CRE_SHIFT)) & EIM_CS2GCR1_CRE_MASK) +#define EIM_CS2GCR1_CREP_MASK (0x80U) +#define EIM_CS2GCR1_CREP_SHIFT (7U) +#define EIM_CS2GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_CREP_SHIFT)) & EIM_CS2GCR1_CREP_MASK) +#define EIM_CS2GCR1_BL_MASK (0x700U) +#define EIM_CS2GCR1_BL_SHIFT (8U) +#define EIM_CS2GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_BL_SHIFT)) & EIM_CS2GCR1_BL_MASK) +#define EIM_CS2GCR1_WC_MASK (0x800U) +#define EIM_CS2GCR1_WC_SHIFT (11U) +#define EIM_CS2GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_WC_SHIFT)) & EIM_CS2GCR1_WC_MASK) +#define EIM_CS2GCR1_BCD_MASK (0x3000U) +#define EIM_CS2GCR1_BCD_SHIFT (12U) +#define EIM_CS2GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_BCD_SHIFT)) & EIM_CS2GCR1_BCD_MASK) +#define EIM_CS2GCR1_BCS_MASK (0xC000U) +#define EIM_CS2GCR1_BCS_SHIFT (14U) +#define EIM_CS2GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_BCS_SHIFT)) & EIM_CS2GCR1_BCS_MASK) +#define EIM_CS2GCR1_DSZ_MASK (0x70000U) +#define EIM_CS2GCR1_DSZ_SHIFT (16U) +#define EIM_CS2GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_DSZ_SHIFT)) & EIM_CS2GCR1_DSZ_MASK) +#define EIM_CS2GCR1_SP_MASK (0x80000U) +#define EIM_CS2GCR1_SP_SHIFT (19U) +#define EIM_CS2GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_SP_SHIFT)) & EIM_CS2GCR1_SP_MASK) +#define EIM_CS2GCR1_CSREC_MASK (0x700000U) +#define EIM_CS2GCR1_CSREC_SHIFT (20U) +#define EIM_CS2GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_CSREC_SHIFT)) & EIM_CS2GCR1_CSREC_MASK) +#define EIM_CS2GCR1_AUS_MASK (0x800000U) +#define EIM_CS2GCR1_AUS_SHIFT (23U) +#define EIM_CS2GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_AUS_SHIFT)) & EIM_CS2GCR1_AUS_MASK) +#define EIM_CS2GCR1_GBC_MASK (0x7000000U) +#define EIM_CS2GCR1_GBC_SHIFT (24U) +#define EIM_CS2GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_GBC_SHIFT)) & EIM_CS2GCR1_GBC_MASK) +#define EIM_CS2GCR1_WP_MASK (0x8000000U) +#define EIM_CS2GCR1_WP_SHIFT (27U) +#define EIM_CS2GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_WP_SHIFT)) & EIM_CS2GCR1_WP_MASK) +#define EIM_CS2GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS2GCR1_PSZ_SHIFT (28U) +#define EIM_CS2GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR1_PSZ_SHIFT)) & EIM_CS2GCR1_PSZ_MASK) + +/*! @name CS2GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS2GCR2_ADH_MASK (0x3U) +#define EIM_CS2GCR2_ADH_SHIFT (0U) +#define EIM_CS2GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_ADH_SHIFT)) & EIM_CS2GCR2_ADH_MASK) +#define EIM_CS2GCR2_DAPS_MASK (0xF0U) +#define EIM_CS2GCR2_DAPS_SHIFT (4U) +#define EIM_CS2GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_DAPS_SHIFT)) & EIM_CS2GCR2_DAPS_MASK) +#define EIM_CS2GCR2_DAE_MASK (0x100U) +#define EIM_CS2GCR2_DAE_SHIFT (8U) +#define EIM_CS2GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_DAE_SHIFT)) & EIM_CS2GCR2_DAE_MASK) +#define EIM_CS2GCR2_DAP_MASK (0x200U) +#define EIM_CS2GCR2_DAP_SHIFT (9U) +#define EIM_CS2GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_DAP_SHIFT)) & EIM_CS2GCR2_DAP_MASK) +#define EIM_CS2GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS2GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS2GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS2GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS2RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS2RCR1_RCSN_MASK (0x7U) +#define EIM_CS2RCR1_RCSN_SHIFT (0U) +#define EIM_CS2RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RCSN_SHIFT)) & EIM_CS2RCR1_RCSN_MASK) +#define EIM_CS2RCR1_RCSA_MASK (0x70U) +#define EIM_CS2RCR1_RCSA_SHIFT (4U) +#define EIM_CS2RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RCSA_SHIFT)) & EIM_CS2RCR1_RCSA_MASK) +#define EIM_CS2RCR1_OEN_MASK (0x700U) +#define EIM_CS2RCR1_OEN_SHIFT (8U) +#define EIM_CS2RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_OEN_SHIFT)) & EIM_CS2RCR1_OEN_MASK) +#define EIM_CS2RCR1_OEA_MASK (0x7000U) +#define EIM_CS2RCR1_OEA_SHIFT (12U) +#define EIM_CS2RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_OEA_SHIFT)) & EIM_CS2RCR1_OEA_MASK) +#define EIM_CS2RCR1_RADVN_MASK (0x70000U) +#define EIM_CS2RCR1_RADVN_SHIFT (16U) +#define EIM_CS2RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RADVN_SHIFT)) & EIM_CS2RCR1_RADVN_MASK) +#define EIM_CS2RCR1_RAL_MASK (0x80000U) +#define EIM_CS2RCR1_RAL_SHIFT (19U) +#define EIM_CS2RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RAL_SHIFT)) & EIM_CS2RCR1_RAL_MASK) +#define EIM_CS2RCR1_RADVA_MASK (0x700000U) +#define EIM_CS2RCR1_RADVA_SHIFT (20U) +#define EIM_CS2RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RADVA_SHIFT)) & EIM_CS2RCR1_RADVA_MASK) +#define EIM_CS2RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS2RCR1_RWSC_SHIFT (24U) +#define EIM_CS2RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR1_RWSC_SHIFT)) & EIM_CS2RCR1_RWSC_MASK) + +/*! @name CS2RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS2RCR2_RBEN_MASK (0x7U) +#define EIM_CS2RCR2_RBEN_SHIFT (0U) +#define EIM_CS2RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_RBEN_SHIFT)) & EIM_CS2RCR2_RBEN_MASK) +#define EIM_CS2RCR2_RBE_MASK (0x8U) +#define EIM_CS2RCR2_RBE_SHIFT (3U) +#define EIM_CS2RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_RBE_SHIFT)) & EIM_CS2RCR2_RBE_MASK) +#define EIM_CS2RCR2_RBEA_MASK (0x70U) +#define EIM_CS2RCR2_RBEA_SHIFT (4U) +#define EIM_CS2RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_RBEA_SHIFT)) & EIM_CS2RCR2_RBEA_MASK) +#define EIM_CS2RCR2_RL_MASK (0x300U) +#define EIM_CS2RCR2_RL_SHIFT (8U) +#define EIM_CS2RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_RL_SHIFT)) & EIM_CS2RCR2_RL_MASK) +#define EIM_CS2RCR2_PAT_MASK (0x7000U) +#define EIM_CS2RCR2_PAT_SHIFT (12U) +#define EIM_CS2RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_PAT_SHIFT)) & EIM_CS2RCR2_PAT_MASK) +#define EIM_CS2RCR2_APR_MASK (0x8000U) +#define EIM_CS2RCR2_APR_SHIFT (15U) +#define EIM_CS2RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2RCR2_APR_SHIFT)) & EIM_CS2RCR2_APR_MASK) + +/*! @name CS2WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS2WCR1_WCSN_MASK (0x7U) +#define EIM_CS2WCR1_WCSN_SHIFT (0U) +#define EIM_CS2WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WCSN_SHIFT)) & EIM_CS2WCR1_WCSN_MASK) +#define EIM_CS2WCR1_WCSA_MASK (0x38U) +#define EIM_CS2WCR1_WCSA_SHIFT (3U) +#define EIM_CS2WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WCSA_SHIFT)) & EIM_CS2WCR1_WCSA_MASK) +#define EIM_CS2WCR1_WEN_MASK (0x1C0U) +#define EIM_CS2WCR1_WEN_SHIFT (6U) +#define EIM_CS2WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WEN_SHIFT)) & EIM_CS2WCR1_WEN_MASK) +#define EIM_CS2WCR1_WEA_MASK (0xE00U) +#define EIM_CS2WCR1_WEA_SHIFT (9U) +#define EIM_CS2WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WEA_SHIFT)) & EIM_CS2WCR1_WEA_MASK) +#define EIM_CS2WCR1_WBEN_MASK (0x7000U) +#define EIM_CS2WCR1_WBEN_SHIFT (12U) +#define EIM_CS2WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WBEN_SHIFT)) & EIM_CS2WCR1_WBEN_MASK) +#define EIM_CS2WCR1_WBEA_MASK (0x38000U) +#define EIM_CS2WCR1_WBEA_SHIFT (15U) +#define EIM_CS2WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WBEA_SHIFT)) & EIM_CS2WCR1_WBEA_MASK) +#define EIM_CS2WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS2WCR1_WADVN_SHIFT (18U) +#define EIM_CS2WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WADVN_SHIFT)) & EIM_CS2WCR1_WADVN_MASK) +#define EIM_CS2WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS2WCR1_WADVA_SHIFT (21U) +#define EIM_CS2WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WADVA_SHIFT)) & EIM_CS2WCR1_WADVA_MASK) +#define EIM_CS2WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS2WCR1_WWSC_SHIFT (24U) +#define EIM_CS2WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WWSC_SHIFT)) & EIM_CS2WCR1_WWSC_MASK) +#define EIM_CS2WCR1_WBED_MASK (0x40000000U) +#define EIM_CS2WCR1_WBED_SHIFT (30U) +#define EIM_CS2WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WBED_SHIFT)) & EIM_CS2WCR1_WBED_MASK) +#define EIM_CS2WCR1_WAL_MASK (0x80000000U) +#define EIM_CS2WCR1_WAL_SHIFT (31U) +#define EIM_CS2WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR1_WAL_SHIFT)) & EIM_CS2WCR1_WAL_MASK) + +/*! @name CS2WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS2WCR2_WBCDD_MASK (0x1U) +#define EIM_CS2WCR2_WBCDD_SHIFT (0U) +#define EIM_CS2WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS2WCR2_WBCDD_SHIFT)) & EIM_CS2WCR2_WBCDD_MASK) + +/*! @name CS3GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS3GCR1_CSEN_MASK (0x1U) +#define EIM_CS3GCR1_CSEN_SHIFT (0U) +#define EIM_CS3GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_CSEN_SHIFT)) & EIM_CS3GCR1_CSEN_MASK) +#define EIM_CS3GCR1_SWR_MASK (0x2U) +#define EIM_CS3GCR1_SWR_SHIFT (1U) +#define EIM_CS3GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_SWR_SHIFT)) & EIM_CS3GCR1_SWR_MASK) +#define EIM_CS3GCR1_SRD_MASK (0x4U) +#define EIM_CS3GCR1_SRD_SHIFT (2U) +#define EIM_CS3GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_SRD_SHIFT)) & EIM_CS3GCR1_SRD_MASK) +#define EIM_CS3GCR1_MUM_MASK (0x8U) +#define EIM_CS3GCR1_MUM_SHIFT (3U) +#define EIM_CS3GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_MUM_SHIFT)) & EIM_CS3GCR1_MUM_MASK) +#define EIM_CS3GCR1_WFL_MASK (0x10U) +#define EIM_CS3GCR1_WFL_SHIFT (4U) +#define EIM_CS3GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_WFL_SHIFT)) & EIM_CS3GCR1_WFL_MASK) +#define EIM_CS3GCR1_RFL_MASK (0x20U) +#define EIM_CS3GCR1_RFL_SHIFT (5U) +#define EIM_CS3GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_RFL_SHIFT)) & EIM_CS3GCR1_RFL_MASK) +#define EIM_CS3GCR1_CRE_MASK (0x40U) +#define EIM_CS3GCR1_CRE_SHIFT (6U) +#define EIM_CS3GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_CRE_SHIFT)) & EIM_CS3GCR1_CRE_MASK) +#define EIM_CS3GCR1_CREP_MASK (0x80U) +#define EIM_CS3GCR1_CREP_SHIFT (7U) +#define EIM_CS3GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_CREP_SHIFT)) & EIM_CS3GCR1_CREP_MASK) +#define EIM_CS3GCR1_BL_MASK (0x700U) +#define EIM_CS3GCR1_BL_SHIFT (8U) +#define EIM_CS3GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_BL_SHIFT)) & EIM_CS3GCR1_BL_MASK) +#define EIM_CS3GCR1_WC_MASK (0x800U) +#define EIM_CS3GCR1_WC_SHIFT (11U) +#define EIM_CS3GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_WC_SHIFT)) & EIM_CS3GCR1_WC_MASK) +#define EIM_CS3GCR1_BCD_MASK (0x3000U) +#define EIM_CS3GCR1_BCD_SHIFT (12U) +#define EIM_CS3GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_BCD_SHIFT)) & EIM_CS3GCR1_BCD_MASK) +#define EIM_CS3GCR1_BCS_MASK (0xC000U) +#define EIM_CS3GCR1_BCS_SHIFT (14U) +#define EIM_CS3GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_BCS_SHIFT)) & EIM_CS3GCR1_BCS_MASK) +#define EIM_CS3GCR1_DSZ_MASK (0x70000U) +#define EIM_CS3GCR1_DSZ_SHIFT (16U) +#define EIM_CS3GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_DSZ_SHIFT)) & EIM_CS3GCR1_DSZ_MASK) +#define EIM_CS3GCR1_SP_MASK (0x80000U) +#define EIM_CS3GCR1_SP_SHIFT (19U) +#define EIM_CS3GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_SP_SHIFT)) & EIM_CS3GCR1_SP_MASK) +#define EIM_CS3GCR1_CSREC_MASK (0x700000U) +#define EIM_CS3GCR1_CSREC_SHIFT (20U) +#define EIM_CS3GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_CSREC_SHIFT)) & EIM_CS3GCR1_CSREC_MASK) +#define EIM_CS3GCR1_AUS_MASK (0x800000U) +#define EIM_CS3GCR1_AUS_SHIFT (23U) +#define EIM_CS3GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_AUS_SHIFT)) & EIM_CS3GCR1_AUS_MASK) +#define EIM_CS3GCR1_GBC_MASK (0x7000000U) +#define EIM_CS3GCR1_GBC_SHIFT (24U) +#define EIM_CS3GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_GBC_SHIFT)) & EIM_CS3GCR1_GBC_MASK) +#define EIM_CS3GCR1_WP_MASK (0x8000000U) +#define EIM_CS3GCR1_WP_SHIFT (27U) +#define EIM_CS3GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_WP_SHIFT)) & EIM_CS3GCR1_WP_MASK) +#define EIM_CS3GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS3GCR1_PSZ_SHIFT (28U) +#define EIM_CS3GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR1_PSZ_SHIFT)) & EIM_CS3GCR1_PSZ_MASK) + +/*! @name CS3GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS3GCR2_ADH_MASK (0x3U) +#define EIM_CS3GCR2_ADH_SHIFT (0U) +#define EIM_CS3GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_ADH_SHIFT)) & EIM_CS3GCR2_ADH_MASK) +#define EIM_CS3GCR2_DAPS_MASK (0xF0U) +#define EIM_CS3GCR2_DAPS_SHIFT (4U) +#define EIM_CS3GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_DAPS_SHIFT)) & EIM_CS3GCR2_DAPS_MASK) +#define EIM_CS3GCR2_DAE_MASK (0x100U) +#define EIM_CS3GCR2_DAE_SHIFT (8U) +#define EIM_CS3GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_DAE_SHIFT)) & EIM_CS3GCR2_DAE_MASK) +#define EIM_CS3GCR2_DAP_MASK (0x200U) +#define EIM_CS3GCR2_DAP_SHIFT (9U) +#define EIM_CS3GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_DAP_SHIFT)) & EIM_CS3GCR2_DAP_MASK) +#define EIM_CS3GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS3GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS3GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS3GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS3RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS3RCR1_RCSN_MASK (0x7U) +#define EIM_CS3RCR1_RCSN_SHIFT (0U) +#define EIM_CS3RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RCSN_SHIFT)) & EIM_CS3RCR1_RCSN_MASK) +#define EIM_CS3RCR1_RCSA_MASK (0x70U) +#define EIM_CS3RCR1_RCSA_SHIFT (4U) +#define EIM_CS3RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RCSA_SHIFT)) & EIM_CS3RCR1_RCSA_MASK) +#define EIM_CS3RCR1_OEN_MASK (0x700U) +#define EIM_CS3RCR1_OEN_SHIFT (8U) +#define EIM_CS3RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_OEN_SHIFT)) & EIM_CS3RCR1_OEN_MASK) +#define EIM_CS3RCR1_OEA_MASK (0x7000U) +#define EIM_CS3RCR1_OEA_SHIFT (12U) +#define EIM_CS3RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_OEA_SHIFT)) & EIM_CS3RCR1_OEA_MASK) +#define EIM_CS3RCR1_RADVN_MASK (0x70000U) +#define EIM_CS3RCR1_RADVN_SHIFT (16U) +#define EIM_CS3RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RADVN_SHIFT)) & EIM_CS3RCR1_RADVN_MASK) +#define EIM_CS3RCR1_RAL_MASK (0x80000U) +#define EIM_CS3RCR1_RAL_SHIFT (19U) +#define EIM_CS3RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RAL_SHIFT)) & EIM_CS3RCR1_RAL_MASK) +#define EIM_CS3RCR1_RADVA_MASK (0x700000U) +#define EIM_CS3RCR1_RADVA_SHIFT (20U) +#define EIM_CS3RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RADVA_SHIFT)) & EIM_CS3RCR1_RADVA_MASK) +#define EIM_CS3RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS3RCR1_RWSC_SHIFT (24U) +#define EIM_CS3RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR1_RWSC_SHIFT)) & EIM_CS3RCR1_RWSC_MASK) + +/*! @name CS3RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS3RCR2_RBEN_MASK (0x7U) +#define EIM_CS3RCR2_RBEN_SHIFT (0U) +#define EIM_CS3RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_RBEN_SHIFT)) & EIM_CS3RCR2_RBEN_MASK) +#define EIM_CS3RCR2_RBE_MASK (0x8U) +#define EIM_CS3RCR2_RBE_SHIFT (3U) +#define EIM_CS3RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_RBE_SHIFT)) & EIM_CS3RCR2_RBE_MASK) +#define EIM_CS3RCR2_RBEA_MASK (0x70U) +#define EIM_CS3RCR2_RBEA_SHIFT (4U) +#define EIM_CS3RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_RBEA_SHIFT)) & EIM_CS3RCR2_RBEA_MASK) +#define EIM_CS3RCR2_RL_MASK (0x300U) +#define EIM_CS3RCR2_RL_SHIFT (8U) +#define EIM_CS3RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_RL_SHIFT)) & EIM_CS3RCR2_RL_MASK) +#define EIM_CS3RCR2_PAT_MASK (0x7000U) +#define EIM_CS3RCR2_PAT_SHIFT (12U) +#define EIM_CS3RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_PAT_SHIFT)) & EIM_CS3RCR2_PAT_MASK) +#define EIM_CS3RCR2_APR_MASK (0x8000U) +#define EIM_CS3RCR2_APR_SHIFT (15U) +#define EIM_CS3RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3RCR2_APR_SHIFT)) & EIM_CS3RCR2_APR_MASK) + +/*! @name CS3WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS3WCR1_WCSN_MASK (0x7U) +#define EIM_CS3WCR1_WCSN_SHIFT (0U) +#define EIM_CS3WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WCSN_SHIFT)) & EIM_CS3WCR1_WCSN_MASK) +#define EIM_CS3WCR1_WCSA_MASK (0x38U) +#define EIM_CS3WCR1_WCSA_SHIFT (3U) +#define EIM_CS3WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WCSA_SHIFT)) & EIM_CS3WCR1_WCSA_MASK) +#define EIM_CS3WCR1_WEN_MASK (0x1C0U) +#define EIM_CS3WCR1_WEN_SHIFT (6U) +#define EIM_CS3WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WEN_SHIFT)) & EIM_CS3WCR1_WEN_MASK) +#define EIM_CS3WCR1_WEA_MASK (0xE00U) +#define EIM_CS3WCR1_WEA_SHIFT (9U) +#define EIM_CS3WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WEA_SHIFT)) & EIM_CS3WCR1_WEA_MASK) +#define EIM_CS3WCR1_WBEN_MASK (0x7000U) +#define EIM_CS3WCR1_WBEN_SHIFT (12U) +#define EIM_CS3WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WBEN_SHIFT)) & EIM_CS3WCR1_WBEN_MASK) +#define EIM_CS3WCR1_WBEA_MASK (0x38000U) +#define EIM_CS3WCR1_WBEA_SHIFT (15U) +#define EIM_CS3WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WBEA_SHIFT)) & EIM_CS3WCR1_WBEA_MASK) +#define EIM_CS3WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS3WCR1_WADVN_SHIFT (18U) +#define EIM_CS3WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WADVN_SHIFT)) & EIM_CS3WCR1_WADVN_MASK) +#define EIM_CS3WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS3WCR1_WADVA_SHIFT (21U) +#define EIM_CS3WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WADVA_SHIFT)) & EIM_CS3WCR1_WADVA_MASK) +#define EIM_CS3WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS3WCR1_WWSC_SHIFT (24U) +#define EIM_CS3WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WWSC_SHIFT)) & EIM_CS3WCR1_WWSC_MASK) +#define EIM_CS3WCR1_WBED_MASK (0x40000000U) +#define EIM_CS3WCR1_WBED_SHIFT (30U) +#define EIM_CS3WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WBED_SHIFT)) & EIM_CS3WCR1_WBED_MASK) +#define EIM_CS3WCR1_WAL_MASK (0x80000000U) +#define EIM_CS3WCR1_WAL_SHIFT (31U) +#define EIM_CS3WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR1_WAL_SHIFT)) & EIM_CS3WCR1_WAL_MASK) + +/*! @name CS3WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS3WCR2_WBCDD_MASK (0x1U) +#define EIM_CS3WCR2_WBCDD_SHIFT (0U) +#define EIM_CS3WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS3WCR2_WBCDD_SHIFT)) & EIM_CS3WCR2_WBCDD_MASK) + +/*! @name CS4GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS4GCR1_CSEN_MASK (0x1U) +#define EIM_CS4GCR1_CSEN_SHIFT (0U) +#define EIM_CS4GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_CSEN_SHIFT)) & EIM_CS4GCR1_CSEN_MASK) +#define EIM_CS4GCR1_SWR_MASK (0x2U) +#define EIM_CS4GCR1_SWR_SHIFT (1U) +#define EIM_CS4GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_SWR_SHIFT)) & EIM_CS4GCR1_SWR_MASK) +#define EIM_CS4GCR1_SRD_MASK (0x4U) +#define EIM_CS4GCR1_SRD_SHIFT (2U) +#define EIM_CS4GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_SRD_SHIFT)) & EIM_CS4GCR1_SRD_MASK) +#define EIM_CS4GCR1_MUM_MASK (0x8U) +#define EIM_CS4GCR1_MUM_SHIFT (3U) +#define EIM_CS4GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_MUM_SHIFT)) & EIM_CS4GCR1_MUM_MASK) +#define EIM_CS4GCR1_WFL_MASK (0x10U) +#define EIM_CS4GCR1_WFL_SHIFT (4U) +#define EIM_CS4GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_WFL_SHIFT)) & EIM_CS4GCR1_WFL_MASK) +#define EIM_CS4GCR1_RFL_MASK (0x20U) +#define EIM_CS4GCR1_RFL_SHIFT (5U) +#define EIM_CS4GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_RFL_SHIFT)) & EIM_CS4GCR1_RFL_MASK) +#define EIM_CS4GCR1_CRE_MASK (0x40U) +#define EIM_CS4GCR1_CRE_SHIFT (6U) +#define EIM_CS4GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_CRE_SHIFT)) & EIM_CS4GCR1_CRE_MASK) +#define EIM_CS4GCR1_CREP_MASK (0x80U) +#define EIM_CS4GCR1_CREP_SHIFT (7U) +#define EIM_CS4GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_CREP_SHIFT)) & EIM_CS4GCR1_CREP_MASK) +#define EIM_CS4GCR1_BL_MASK (0x700U) +#define EIM_CS4GCR1_BL_SHIFT (8U) +#define EIM_CS4GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_BL_SHIFT)) & EIM_CS4GCR1_BL_MASK) +#define EIM_CS4GCR1_WC_MASK (0x800U) +#define EIM_CS4GCR1_WC_SHIFT (11U) +#define EIM_CS4GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_WC_SHIFT)) & EIM_CS4GCR1_WC_MASK) +#define EIM_CS4GCR1_BCD_MASK (0x3000U) +#define EIM_CS4GCR1_BCD_SHIFT (12U) +#define EIM_CS4GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_BCD_SHIFT)) & EIM_CS4GCR1_BCD_MASK) +#define EIM_CS4GCR1_BCS_MASK (0xC000U) +#define EIM_CS4GCR1_BCS_SHIFT (14U) +#define EIM_CS4GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_BCS_SHIFT)) & EIM_CS4GCR1_BCS_MASK) +#define EIM_CS4GCR1_DSZ_MASK (0x70000U) +#define EIM_CS4GCR1_DSZ_SHIFT (16U) +#define EIM_CS4GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_DSZ_SHIFT)) & EIM_CS4GCR1_DSZ_MASK) +#define EIM_CS4GCR1_SP_MASK (0x80000U) +#define EIM_CS4GCR1_SP_SHIFT (19U) +#define EIM_CS4GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_SP_SHIFT)) & EIM_CS4GCR1_SP_MASK) +#define EIM_CS4GCR1_CSREC_MASK (0x700000U) +#define EIM_CS4GCR1_CSREC_SHIFT (20U) +#define EIM_CS4GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_CSREC_SHIFT)) & EIM_CS4GCR1_CSREC_MASK) +#define EIM_CS4GCR1_AUS_MASK (0x800000U) +#define EIM_CS4GCR1_AUS_SHIFT (23U) +#define EIM_CS4GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_AUS_SHIFT)) & EIM_CS4GCR1_AUS_MASK) +#define EIM_CS4GCR1_GBC_MASK (0x7000000U) +#define EIM_CS4GCR1_GBC_SHIFT (24U) +#define EIM_CS4GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_GBC_SHIFT)) & EIM_CS4GCR1_GBC_MASK) +#define EIM_CS4GCR1_WP_MASK (0x8000000U) +#define EIM_CS4GCR1_WP_SHIFT (27U) +#define EIM_CS4GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_WP_SHIFT)) & EIM_CS4GCR1_WP_MASK) +#define EIM_CS4GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS4GCR1_PSZ_SHIFT (28U) +#define EIM_CS4GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR1_PSZ_SHIFT)) & EIM_CS4GCR1_PSZ_MASK) + +/*! @name CS4GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS4GCR2_ADH_MASK (0x3U) +#define EIM_CS4GCR2_ADH_SHIFT (0U) +#define EIM_CS4GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_ADH_SHIFT)) & EIM_CS4GCR2_ADH_MASK) +#define EIM_CS4GCR2_DAPS_MASK (0xF0U) +#define EIM_CS4GCR2_DAPS_SHIFT (4U) +#define EIM_CS4GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_DAPS_SHIFT)) & EIM_CS4GCR2_DAPS_MASK) +#define EIM_CS4GCR2_DAE_MASK (0x100U) +#define EIM_CS4GCR2_DAE_SHIFT (8U) +#define EIM_CS4GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_DAE_SHIFT)) & EIM_CS4GCR2_DAE_MASK) +#define EIM_CS4GCR2_DAP_MASK (0x200U) +#define EIM_CS4GCR2_DAP_SHIFT (9U) +#define EIM_CS4GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_DAP_SHIFT)) & EIM_CS4GCR2_DAP_MASK) +#define EIM_CS4GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS4GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS4GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS4GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS4RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS4RCR1_RCSN_MASK (0x7U) +#define EIM_CS4RCR1_RCSN_SHIFT (0U) +#define EIM_CS4RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RCSN_SHIFT)) & EIM_CS4RCR1_RCSN_MASK) +#define EIM_CS4RCR1_RCSA_MASK (0x70U) +#define EIM_CS4RCR1_RCSA_SHIFT (4U) +#define EIM_CS4RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RCSA_SHIFT)) & EIM_CS4RCR1_RCSA_MASK) +#define EIM_CS4RCR1_OEN_MASK (0x700U) +#define EIM_CS4RCR1_OEN_SHIFT (8U) +#define EIM_CS4RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_OEN_SHIFT)) & EIM_CS4RCR1_OEN_MASK) +#define EIM_CS4RCR1_OEA_MASK (0x7000U) +#define EIM_CS4RCR1_OEA_SHIFT (12U) +#define EIM_CS4RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_OEA_SHIFT)) & EIM_CS4RCR1_OEA_MASK) +#define EIM_CS4RCR1_RADVN_MASK (0x70000U) +#define EIM_CS4RCR1_RADVN_SHIFT (16U) +#define EIM_CS4RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RADVN_SHIFT)) & EIM_CS4RCR1_RADVN_MASK) +#define EIM_CS4RCR1_RAL_MASK (0x80000U) +#define EIM_CS4RCR1_RAL_SHIFT (19U) +#define EIM_CS4RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RAL_SHIFT)) & EIM_CS4RCR1_RAL_MASK) +#define EIM_CS4RCR1_RADVA_MASK (0x700000U) +#define EIM_CS4RCR1_RADVA_SHIFT (20U) +#define EIM_CS4RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RADVA_SHIFT)) & EIM_CS4RCR1_RADVA_MASK) +#define EIM_CS4RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS4RCR1_RWSC_SHIFT (24U) +#define EIM_CS4RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR1_RWSC_SHIFT)) & EIM_CS4RCR1_RWSC_MASK) + +/*! @name CS4RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS4RCR2_RBEN_MASK (0x7U) +#define EIM_CS4RCR2_RBEN_SHIFT (0U) +#define EIM_CS4RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_RBEN_SHIFT)) & EIM_CS4RCR2_RBEN_MASK) +#define EIM_CS4RCR2_RBE_MASK (0x8U) +#define EIM_CS4RCR2_RBE_SHIFT (3U) +#define EIM_CS4RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_RBE_SHIFT)) & EIM_CS4RCR2_RBE_MASK) +#define EIM_CS4RCR2_RBEA_MASK (0x70U) +#define EIM_CS4RCR2_RBEA_SHIFT (4U) +#define EIM_CS4RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_RBEA_SHIFT)) & EIM_CS4RCR2_RBEA_MASK) +#define EIM_CS4RCR2_RL_MASK (0x300U) +#define EIM_CS4RCR2_RL_SHIFT (8U) +#define EIM_CS4RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_RL_SHIFT)) & EIM_CS4RCR2_RL_MASK) +#define EIM_CS4RCR2_PAT_MASK (0x7000U) +#define EIM_CS4RCR2_PAT_SHIFT (12U) +#define EIM_CS4RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_PAT_SHIFT)) & EIM_CS4RCR2_PAT_MASK) +#define EIM_CS4RCR2_APR_MASK (0x8000U) +#define EIM_CS4RCR2_APR_SHIFT (15U) +#define EIM_CS4RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4RCR2_APR_SHIFT)) & EIM_CS4RCR2_APR_MASK) + +/*! @name CS4WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS4WCR1_WCSN_MASK (0x7U) +#define EIM_CS4WCR1_WCSN_SHIFT (0U) +#define EIM_CS4WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WCSN_SHIFT)) & EIM_CS4WCR1_WCSN_MASK) +#define EIM_CS4WCR1_WCSA_MASK (0x38U) +#define EIM_CS4WCR1_WCSA_SHIFT (3U) +#define EIM_CS4WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WCSA_SHIFT)) & EIM_CS4WCR1_WCSA_MASK) +#define EIM_CS4WCR1_WEN_MASK (0x1C0U) +#define EIM_CS4WCR1_WEN_SHIFT (6U) +#define EIM_CS4WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WEN_SHIFT)) & EIM_CS4WCR1_WEN_MASK) +#define EIM_CS4WCR1_WEA_MASK (0xE00U) +#define EIM_CS4WCR1_WEA_SHIFT (9U) +#define EIM_CS4WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WEA_SHIFT)) & EIM_CS4WCR1_WEA_MASK) +#define EIM_CS4WCR1_WBEN_MASK (0x7000U) +#define EIM_CS4WCR1_WBEN_SHIFT (12U) +#define EIM_CS4WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WBEN_SHIFT)) & EIM_CS4WCR1_WBEN_MASK) +#define EIM_CS4WCR1_WBEA_MASK (0x38000U) +#define EIM_CS4WCR1_WBEA_SHIFT (15U) +#define EIM_CS4WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WBEA_SHIFT)) & EIM_CS4WCR1_WBEA_MASK) +#define EIM_CS4WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS4WCR1_WADVN_SHIFT (18U) +#define EIM_CS4WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WADVN_SHIFT)) & EIM_CS4WCR1_WADVN_MASK) +#define EIM_CS4WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS4WCR1_WADVA_SHIFT (21U) +#define EIM_CS4WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WADVA_SHIFT)) & EIM_CS4WCR1_WADVA_MASK) +#define EIM_CS4WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS4WCR1_WWSC_SHIFT (24U) +#define EIM_CS4WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WWSC_SHIFT)) & EIM_CS4WCR1_WWSC_MASK) +#define EIM_CS4WCR1_WBED_MASK (0x40000000U) +#define EIM_CS4WCR1_WBED_SHIFT (30U) +#define EIM_CS4WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WBED_SHIFT)) & EIM_CS4WCR1_WBED_MASK) +#define EIM_CS4WCR1_WAL_MASK (0x80000000U) +#define EIM_CS4WCR1_WAL_SHIFT (31U) +#define EIM_CS4WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR1_WAL_SHIFT)) & EIM_CS4WCR1_WAL_MASK) + +/*! @name CS4WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS4WCR2_WBCDD_MASK (0x1U) +#define EIM_CS4WCR2_WBCDD_SHIFT (0U) +#define EIM_CS4WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS4WCR2_WBCDD_SHIFT)) & EIM_CS4WCR2_WBCDD_MASK) + +/*! @name CS5GCR1 - Chip Select n General Configuration Register 1 */ +#define EIM_CS5GCR1_CSEN_MASK (0x1U) +#define EIM_CS5GCR1_CSEN_SHIFT (0U) +#define EIM_CS5GCR1_CSEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_CSEN_SHIFT)) & EIM_CS5GCR1_CSEN_MASK) +#define EIM_CS5GCR1_SWR_MASK (0x2U) +#define EIM_CS5GCR1_SWR_SHIFT (1U) +#define EIM_CS5GCR1_SWR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_SWR_SHIFT)) & EIM_CS5GCR1_SWR_MASK) +#define EIM_CS5GCR1_SRD_MASK (0x4U) +#define EIM_CS5GCR1_SRD_SHIFT (2U) +#define EIM_CS5GCR1_SRD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_SRD_SHIFT)) & EIM_CS5GCR1_SRD_MASK) +#define EIM_CS5GCR1_MUM_MASK (0x8U) +#define EIM_CS5GCR1_MUM_SHIFT (3U) +#define EIM_CS5GCR1_MUM(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_MUM_SHIFT)) & EIM_CS5GCR1_MUM_MASK) +#define EIM_CS5GCR1_WFL_MASK (0x10U) +#define EIM_CS5GCR1_WFL_SHIFT (4U) +#define EIM_CS5GCR1_WFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_WFL_SHIFT)) & EIM_CS5GCR1_WFL_MASK) +#define EIM_CS5GCR1_RFL_MASK (0x20U) +#define EIM_CS5GCR1_RFL_SHIFT (5U) +#define EIM_CS5GCR1_RFL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_RFL_SHIFT)) & EIM_CS5GCR1_RFL_MASK) +#define EIM_CS5GCR1_CRE_MASK (0x40U) +#define EIM_CS5GCR1_CRE_SHIFT (6U) +#define EIM_CS5GCR1_CRE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_CRE_SHIFT)) & EIM_CS5GCR1_CRE_MASK) +#define EIM_CS5GCR1_CREP_MASK (0x80U) +#define EIM_CS5GCR1_CREP_SHIFT (7U) +#define EIM_CS5GCR1_CREP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_CREP_SHIFT)) & EIM_CS5GCR1_CREP_MASK) +#define EIM_CS5GCR1_BL_MASK (0x700U) +#define EIM_CS5GCR1_BL_SHIFT (8U) +#define EIM_CS5GCR1_BL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_BL_SHIFT)) & EIM_CS5GCR1_BL_MASK) +#define EIM_CS5GCR1_WC_MASK (0x800U) +#define EIM_CS5GCR1_WC_SHIFT (11U) +#define EIM_CS5GCR1_WC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_WC_SHIFT)) & EIM_CS5GCR1_WC_MASK) +#define EIM_CS5GCR1_BCD_MASK (0x3000U) +#define EIM_CS5GCR1_BCD_SHIFT (12U) +#define EIM_CS5GCR1_BCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_BCD_SHIFT)) & EIM_CS5GCR1_BCD_MASK) +#define EIM_CS5GCR1_BCS_MASK (0xC000U) +#define EIM_CS5GCR1_BCS_SHIFT (14U) +#define EIM_CS5GCR1_BCS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_BCS_SHIFT)) & EIM_CS5GCR1_BCS_MASK) +#define EIM_CS5GCR1_DSZ_MASK (0x70000U) +#define EIM_CS5GCR1_DSZ_SHIFT (16U) +#define EIM_CS5GCR1_DSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_DSZ_SHIFT)) & EIM_CS5GCR1_DSZ_MASK) +#define EIM_CS5GCR1_SP_MASK (0x80000U) +#define EIM_CS5GCR1_SP_SHIFT (19U) +#define EIM_CS5GCR1_SP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_SP_SHIFT)) & EIM_CS5GCR1_SP_MASK) +#define EIM_CS5GCR1_CSREC_MASK (0x700000U) +#define EIM_CS5GCR1_CSREC_SHIFT (20U) +#define EIM_CS5GCR1_CSREC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_CSREC_SHIFT)) & EIM_CS5GCR1_CSREC_MASK) +#define EIM_CS5GCR1_AUS_MASK (0x800000U) +#define EIM_CS5GCR1_AUS_SHIFT (23U) +#define EIM_CS5GCR1_AUS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_AUS_SHIFT)) & EIM_CS5GCR1_AUS_MASK) +#define EIM_CS5GCR1_GBC_MASK (0x7000000U) +#define EIM_CS5GCR1_GBC_SHIFT (24U) +#define EIM_CS5GCR1_GBC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_GBC_SHIFT)) & EIM_CS5GCR1_GBC_MASK) +#define EIM_CS5GCR1_WP_MASK (0x8000000U) +#define EIM_CS5GCR1_WP_SHIFT (27U) +#define EIM_CS5GCR1_WP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_WP_SHIFT)) & EIM_CS5GCR1_WP_MASK) +#define EIM_CS5GCR1_PSZ_MASK (0xF0000000U) +#define EIM_CS5GCR1_PSZ_SHIFT (28U) +#define EIM_CS5GCR1_PSZ(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR1_PSZ_SHIFT)) & EIM_CS5GCR1_PSZ_MASK) + +/*! @name CS5GCR2 - Chip Select n General Configuration Register 2 */ +#define EIM_CS5GCR2_ADH_MASK (0x3U) +#define EIM_CS5GCR2_ADH_SHIFT (0U) +#define EIM_CS5GCR2_ADH(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_ADH_SHIFT)) & EIM_CS5GCR2_ADH_MASK) +#define EIM_CS5GCR2_DAPS_MASK (0xF0U) +#define EIM_CS5GCR2_DAPS_SHIFT (4U) +#define EIM_CS5GCR2_DAPS(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_DAPS_SHIFT)) & EIM_CS5GCR2_DAPS_MASK) +#define EIM_CS5GCR2_DAE_MASK (0x100U) +#define EIM_CS5GCR2_DAE_SHIFT (8U) +#define EIM_CS5GCR2_DAE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_DAE_SHIFT)) & EIM_CS5GCR2_DAE_MASK) +#define EIM_CS5GCR2_DAP_MASK (0x200U) +#define EIM_CS5GCR2_DAP_SHIFT (9U) +#define EIM_CS5GCR2_DAP(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_DAP_SHIFT)) & EIM_CS5GCR2_DAP_MASK) +#define EIM_CS5GCR2_MUX16_BYP_GRANT_MASK (0x1000U) +#define EIM_CS5GCR2_MUX16_BYP_GRANT_SHIFT (12U) +#define EIM_CS5GCR2_MUX16_BYP_GRANT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5GCR2_MUX16_BYP_GRANT_SHIFT)) & EIM_CS5GCR2_MUX16_BYP_GRANT_MASK) + +/*! @name CS5RCR1 - Chip Select n Read Configuration Register 1 */ +#define EIM_CS5RCR1_RCSN_MASK (0x7U) +#define EIM_CS5RCR1_RCSN_SHIFT (0U) +#define EIM_CS5RCR1_RCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RCSN_SHIFT)) & EIM_CS5RCR1_RCSN_MASK) +#define EIM_CS5RCR1_RCSA_MASK (0x70U) +#define EIM_CS5RCR1_RCSA_SHIFT (4U) +#define EIM_CS5RCR1_RCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RCSA_SHIFT)) & EIM_CS5RCR1_RCSA_MASK) +#define EIM_CS5RCR1_OEN_MASK (0x700U) +#define EIM_CS5RCR1_OEN_SHIFT (8U) +#define EIM_CS5RCR1_OEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_OEN_SHIFT)) & EIM_CS5RCR1_OEN_MASK) +#define EIM_CS5RCR1_OEA_MASK (0x7000U) +#define EIM_CS5RCR1_OEA_SHIFT (12U) +#define EIM_CS5RCR1_OEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_OEA_SHIFT)) & EIM_CS5RCR1_OEA_MASK) +#define EIM_CS5RCR1_RADVN_MASK (0x70000U) +#define EIM_CS5RCR1_RADVN_SHIFT (16U) +#define EIM_CS5RCR1_RADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RADVN_SHIFT)) & EIM_CS5RCR1_RADVN_MASK) +#define EIM_CS5RCR1_RAL_MASK (0x80000U) +#define EIM_CS5RCR1_RAL_SHIFT (19U) +#define EIM_CS5RCR1_RAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RAL_SHIFT)) & EIM_CS5RCR1_RAL_MASK) +#define EIM_CS5RCR1_RADVA_MASK (0x700000U) +#define EIM_CS5RCR1_RADVA_SHIFT (20U) +#define EIM_CS5RCR1_RADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RADVA_SHIFT)) & EIM_CS5RCR1_RADVA_MASK) +#define EIM_CS5RCR1_RWSC_MASK (0x3F000000U) +#define EIM_CS5RCR1_RWSC_SHIFT (24U) +#define EIM_CS5RCR1_RWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR1_RWSC_SHIFT)) & EIM_CS5RCR1_RWSC_MASK) + +/*! @name CS5RCR2 - Chip Select n Read Configuration Register 2 */ +#define EIM_CS5RCR2_RBEN_MASK (0x7U) +#define EIM_CS5RCR2_RBEN_SHIFT (0U) +#define EIM_CS5RCR2_RBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_RBEN_SHIFT)) & EIM_CS5RCR2_RBEN_MASK) +#define EIM_CS5RCR2_RBE_MASK (0x8U) +#define EIM_CS5RCR2_RBE_SHIFT (3U) +#define EIM_CS5RCR2_RBE(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_RBE_SHIFT)) & EIM_CS5RCR2_RBE_MASK) +#define EIM_CS5RCR2_RBEA_MASK (0x70U) +#define EIM_CS5RCR2_RBEA_SHIFT (4U) +#define EIM_CS5RCR2_RBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_RBEA_SHIFT)) & EIM_CS5RCR2_RBEA_MASK) +#define EIM_CS5RCR2_RL_MASK (0x300U) +#define EIM_CS5RCR2_RL_SHIFT (8U) +#define EIM_CS5RCR2_RL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_RL_SHIFT)) & EIM_CS5RCR2_RL_MASK) +#define EIM_CS5RCR2_PAT_MASK (0x7000U) +#define EIM_CS5RCR2_PAT_SHIFT (12U) +#define EIM_CS5RCR2_PAT(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_PAT_SHIFT)) & EIM_CS5RCR2_PAT_MASK) +#define EIM_CS5RCR2_APR_MASK (0x8000U) +#define EIM_CS5RCR2_APR_SHIFT (15U) +#define EIM_CS5RCR2_APR(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5RCR2_APR_SHIFT)) & EIM_CS5RCR2_APR_MASK) + +/*! @name CS5WCR1 - Chip Select n Write Configuration Register 1 */ +#define EIM_CS5WCR1_WCSN_MASK (0x7U) +#define EIM_CS5WCR1_WCSN_SHIFT (0U) +#define EIM_CS5WCR1_WCSN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WCSN_SHIFT)) & EIM_CS5WCR1_WCSN_MASK) +#define EIM_CS5WCR1_WCSA_MASK (0x38U) +#define EIM_CS5WCR1_WCSA_SHIFT (3U) +#define EIM_CS5WCR1_WCSA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WCSA_SHIFT)) & EIM_CS5WCR1_WCSA_MASK) +#define EIM_CS5WCR1_WEN_MASK (0x1C0U) +#define EIM_CS5WCR1_WEN_SHIFT (6U) +#define EIM_CS5WCR1_WEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WEN_SHIFT)) & EIM_CS5WCR1_WEN_MASK) +#define EIM_CS5WCR1_WEA_MASK (0xE00U) +#define EIM_CS5WCR1_WEA_SHIFT (9U) +#define EIM_CS5WCR1_WEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WEA_SHIFT)) & EIM_CS5WCR1_WEA_MASK) +#define EIM_CS5WCR1_WBEN_MASK (0x7000U) +#define EIM_CS5WCR1_WBEN_SHIFT (12U) +#define EIM_CS5WCR1_WBEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WBEN_SHIFT)) & EIM_CS5WCR1_WBEN_MASK) +#define EIM_CS5WCR1_WBEA_MASK (0x38000U) +#define EIM_CS5WCR1_WBEA_SHIFT (15U) +#define EIM_CS5WCR1_WBEA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WBEA_SHIFT)) & EIM_CS5WCR1_WBEA_MASK) +#define EIM_CS5WCR1_WADVN_MASK (0x1C0000U) +#define EIM_CS5WCR1_WADVN_SHIFT (18U) +#define EIM_CS5WCR1_WADVN(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WADVN_SHIFT)) & EIM_CS5WCR1_WADVN_MASK) +#define EIM_CS5WCR1_WADVA_MASK (0xE00000U) +#define EIM_CS5WCR1_WADVA_SHIFT (21U) +#define EIM_CS5WCR1_WADVA(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WADVA_SHIFT)) & EIM_CS5WCR1_WADVA_MASK) +#define EIM_CS5WCR1_WWSC_MASK (0x3F000000U) +#define EIM_CS5WCR1_WWSC_SHIFT (24U) +#define EIM_CS5WCR1_WWSC(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WWSC_SHIFT)) & EIM_CS5WCR1_WWSC_MASK) +#define EIM_CS5WCR1_WBED_MASK (0x40000000U) +#define EIM_CS5WCR1_WBED_SHIFT (30U) +#define EIM_CS5WCR1_WBED(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WBED_SHIFT)) & EIM_CS5WCR1_WBED_MASK) +#define EIM_CS5WCR1_WAL_MASK (0x80000000U) +#define EIM_CS5WCR1_WAL_SHIFT (31U) +#define EIM_CS5WCR1_WAL(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR1_WAL_SHIFT)) & EIM_CS5WCR1_WAL_MASK) + +/*! @name CS5WCR2 - Chip Select n Write Configuration Register 2 */ +#define EIM_CS5WCR2_WBCDD_MASK (0x1U) +#define EIM_CS5WCR2_WBCDD_SHIFT (0U) +#define EIM_CS5WCR2_WBCDD(x) (((uint32_t)(((uint32_t)(x)) << EIM_CS5WCR2_WBCDD_SHIFT)) & EIM_CS5WCR2_WBCDD_MASK) + +/*! @name WCR - EIM Configuration Register */ +#define EIM_WCR_BCM_MASK (0x1U) +#define EIM_WCR_BCM_SHIFT (0U) +#define EIM_WCR_BCM(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_BCM_SHIFT)) & EIM_WCR_BCM_MASK) +#define EIM_WCR_GBCD_MASK (0x6U) +#define EIM_WCR_GBCD_SHIFT (1U) +#define EIM_WCR_GBCD(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_GBCD_SHIFT)) & EIM_WCR_GBCD_MASK) +#define EIM_WCR_CONT_BCLK_SEL_MASK (0x8U) +#define EIM_WCR_CONT_BCLK_SEL_SHIFT (3U) +#define EIM_WCR_CONT_BCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_CONT_BCLK_SEL_SHIFT)) & EIM_WCR_CONT_BCLK_SEL_MASK) +#define EIM_WCR_INTEN_MASK (0x10U) +#define EIM_WCR_INTEN_SHIFT (4U) +#define EIM_WCR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_INTEN_SHIFT)) & EIM_WCR_INTEN_MASK) +#define EIM_WCR_INTPOL_MASK (0x20U) +#define EIM_WCR_INTPOL_SHIFT (5U) +#define EIM_WCR_INTPOL(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_INTPOL_SHIFT)) & EIM_WCR_INTPOL_MASK) +#define EIM_WCR_WDOG_EN_MASK (0x100U) +#define EIM_WCR_WDOG_EN_SHIFT (8U) +#define EIM_WCR_WDOG_EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_WDOG_EN_SHIFT)) & EIM_WCR_WDOG_EN_MASK) +#define EIM_WCR_WDOG_LIMIT_MASK (0x600U) +#define EIM_WCR_WDOG_LIMIT_SHIFT (9U) +#define EIM_WCR_WDOG_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_WDOG_LIMIT_SHIFT)) & EIM_WCR_WDOG_LIMIT_MASK) +#define EIM_WCR_FRUN_ACLK_EN_MASK (0x800U) +#define EIM_WCR_FRUN_ACLK_EN_SHIFT (11U) +#define EIM_WCR_FRUN_ACLK_EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_WCR_FRUN_ACLK_EN_SHIFT)) & EIM_WCR_FRUN_ACLK_EN_MASK) + + +/*! + * @} + */ /* end of group EIM_Register_Masks */ + + +/* EIM - Peripheral instance base addresses */ +/** Peripheral EIM base address */ +#define EIM_BASE (0x21B8000u) +/** Peripheral EIM base pointer */ +#define EIM ((EIM_Type *)EIM_BASE) +/** Array initializer of EIM peripheral base addresses */ +#define EIM_BASE_ADDRS { EIM_BASE } +/** Array initializer of EIM peripheral base pointers */ +#define EIM_BASE_PTRS { EIM } +/** Interrupt vectors for the EIM peripheral type */ +#define EIM_IRQS { WEIM_IRQn } + +/*! + * @} + */ /* end of group EIM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENET Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer + * @{ + */ + +/** ENET - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ + __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */ + __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */ + uint8_t RESERVED_2[12]; + __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ + uint8_t RESERVED_3[24]; + __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ + __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ + uint8_t RESERVED_4[28]; + __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ + uint8_t RESERVED_5[28]; + __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ + uint8_t RESERVED_6[60]; + __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ + uint8_t RESERVED_7[28]; + __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ + __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ + __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ + __IO uint32_t TXIC; /**< Transmit Interrupt Coalescing Register, offset: 0xF0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t RXIC; /**< Receive Interrupt Coalescing Register, offset: 0x100 */ + uint8_t RESERVED_9[20]; + __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ + __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ + __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ + __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ + uint8_t RESERVED_10[28]; + __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ + uint8_t RESERVED_11[56]; + __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */ + __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */ + __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */ + uint8_t RESERVED_12[4]; + __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ + __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ + __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ + __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ + __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ + __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ + __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ + __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ + __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ + __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ + uint8_t RESERVED_14[56]; + __I uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */ + __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ + __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ + __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ + __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ + __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ + __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ + __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ + __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ + __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ + __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ + __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ + __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ + __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ + __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ + __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ + __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ + __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ + __I uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */ + __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ + __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ + __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ + __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ + __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ + __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ + __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ + __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ + __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */ + __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ + __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ + uint8_t RESERVED_15[12]; + __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ + __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ + __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ + __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ + __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ + __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ + __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ + __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ + __I uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */ + __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ + __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ + __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ + __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ + __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ + __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ + __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ + __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ + __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ + __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ + __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ + __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ + __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ + __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ + __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ + uint8_t RESERVED_16[284]; + __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ + __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ + __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ + __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ + __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ + __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ + __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ + uint8_t RESERVED_17[488]; + __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ + struct { /* offset: 0x608, array step: 0x8 */ + __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ + __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ + } CHANNEL[4]; +} ENET_Type; + +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/*! @name EIR - Interrupt Event Register */ +#define ENET_EIR_TS_TIMER_MASK (0x8000U) +#define ENET_EIR_TS_TIMER_SHIFT (15U) +#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) +#define ENET_EIR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIR_TS_AVAIL_SHIFT (16U) +#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) +#define ENET_EIR_WAKEUP_MASK (0x20000U) +#define ENET_EIR_WAKEUP_SHIFT (17U) +#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) +#define ENET_EIR_PLR_MASK (0x40000U) +#define ENET_EIR_PLR_SHIFT (18U) +#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) +#define ENET_EIR_UN_MASK (0x80000U) +#define ENET_EIR_UN_SHIFT (19U) +#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) +#define ENET_EIR_RL_MASK (0x100000U) +#define ENET_EIR_RL_SHIFT (20U) +#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) +#define ENET_EIR_LC_MASK (0x200000U) +#define ENET_EIR_LC_SHIFT (21U) +#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) +#define ENET_EIR_EBERR_MASK (0x400000U) +#define ENET_EIR_EBERR_SHIFT (22U) +#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) +#define ENET_EIR_MII_MASK (0x800000U) +#define ENET_EIR_MII_SHIFT (23U) +#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) +#define ENET_EIR_RXB_MASK (0x1000000U) +#define ENET_EIR_RXB_SHIFT (24U) +#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) +#define ENET_EIR_RXF_MASK (0x2000000U) +#define ENET_EIR_RXF_SHIFT (25U) +#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) +#define ENET_EIR_TXB_MASK (0x4000000U) +#define ENET_EIR_TXB_SHIFT (26U) +#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) +#define ENET_EIR_TXF_MASK (0x8000000U) +#define ENET_EIR_TXF_SHIFT (27U) +#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) +#define ENET_EIR_GRA_MASK (0x10000000U) +#define ENET_EIR_GRA_SHIFT (28U) +#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) +#define ENET_EIR_BABT_MASK (0x20000000U) +#define ENET_EIR_BABT_SHIFT (29U) +#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) +#define ENET_EIR_BABR_MASK (0x40000000U) +#define ENET_EIR_BABR_SHIFT (30U) +#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) + +/*! @name EIMR - Interrupt Mask Register */ +#define ENET_EIMR_TS_TIMER_MASK (0x8000U) +#define ENET_EIMR_TS_TIMER_SHIFT (15U) +#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) +#define ENET_EIMR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIMR_TS_AVAIL_SHIFT (16U) +#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) +#define ENET_EIMR_WAKEUP_MASK (0x20000U) +#define ENET_EIMR_WAKEUP_SHIFT (17U) +#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) +#define ENET_EIMR_PLR_MASK (0x40000U) +#define ENET_EIMR_PLR_SHIFT (18U) +#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) +#define ENET_EIMR_UN_MASK (0x80000U) +#define ENET_EIMR_UN_SHIFT (19U) +#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) +#define ENET_EIMR_RL_MASK (0x100000U) +#define ENET_EIMR_RL_SHIFT (20U) +#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) +#define ENET_EIMR_LC_MASK (0x200000U) +#define ENET_EIMR_LC_SHIFT (21U) +#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) +#define ENET_EIMR_EBERR_MASK (0x400000U) +#define ENET_EIMR_EBERR_SHIFT (22U) +#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) +#define ENET_EIMR_MII_MASK (0x800000U) +#define ENET_EIMR_MII_SHIFT (23U) +#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) +#define ENET_EIMR_RXB_MASK (0x1000000U) +#define ENET_EIMR_RXB_SHIFT (24U) +#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) +#define ENET_EIMR_RXF_MASK (0x2000000U) +#define ENET_EIMR_RXF_SHIFT (25U) +#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) +#define ENET_EIMR_TXB_MASK (0x4000000U) +#define ENET_EIMR_TXB_SHIFT (26U) +#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) +#define ENET_EIMR_TXF_MASK (0x8000000U) +#define ENET_EIMR_TXF_SHIFT (27U) +#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) +#define ENET_EIMR_GRA_MASK (0x10000000U) +#define ENET_EIMR_GRA_SHIFT (28U) +#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) +#define ENET_EIMR_BABT_MASK (0x20000000U) +#define ENET_EIMR_BABT_SHIFT (29U) +#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) +#define ENET_EIMR_BABR_MASK (0x40000000U) +#define ENET_EIMR_BABR_SHIFT (30U) +#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) + +/*! @name RDAR - Receive Descriptor Active Register */ +#define ENET_RDAR_RDAR_MASK (0x1000000U) +#define ENET_RDAR_RDAR_SHIFT (24U) +#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) + +/*! @name TDAR - Transmit Descriptor Active Register */ +#define ENET_TDAR_TDAR_MASK (0x1000000U) +#define ENET_TDAR_TDAR_SHIFT (24U) +#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) + +/*! @name ECR - Ethernet Control Register */ +#define ENET_ECR_RESET_MASK (0x1U) +#define ENET_ECR_RESET_SHIFT (0U) +#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) +#define ENET_ECR_ETHEREN_MASK (0x2U) +#define ENET_ECR_ETHEREN_SHIFT (1U) +#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) +#define ENET_ECR_MAGICEN_MASK (0x4U) +#define ENET_ECR_MAGICEN_SHIFT (2U) +#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) +#define ENET_ECR_SLEEP_MASK (0x8U) +#define ENET_ECR_SLEEP_SHIFT (3U) +#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) +#define ENET_ECR_EN1588_MASK (0x10U) +#define ENET_ECR_EN1588_SHIFT (4U) +#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) +#define ENET_ECR_DBGEN_MASK (0x40U) +#define ENET_ECR_DBGEN_SHIFT (6U) +#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) +#define ENET_ECR_DBSWP_MASK (0x100U) +#define ENET_ECR_DBSWP_SHIFT (8U) +#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) + +/*! @name MMFR - MII Management Frame Register */ +#define ENET_MMFR_DATA_MASK (0xFFFFU) +#define ENET_MMFR_DATA_SHIFT (0U) +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) +#define ENET_MMFR_TA_MASK (0x30000U) +#define ENET_MMFR_TA_SHIFT (16U) +#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) +#define ENET_MMFR_RA_MASK (0x7C0000U) +#define ENET_MMFR_RA_SHIFT (18U) +#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) +#define ENET_MMFR_PA_MASK (0xF800000U) +#define ENET_MMFR_PA_SHIFT (23U) +#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) +#define ENET_MMFR_OP_MASK (0x30000000U) +#define ENET_MMFR_OP_SHIFT (28U) +#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) +#define ENET_MMFR_ST_MASK (0xC0000000U) +#define ENET_MMFR_ST_SHIFT (30U) +#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) + +/*! @name MSCR - MII Speed Control Register */ +#define ENET_MSCR_MII_SPEED_MASK (0x7EU) +#define ENET_MSCR_MII_SPEED_SHIFT (1U) +#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) +#define ENET_MSCR_DIS_PRE_MASK (0x80U) +#define ENET_MSCR_DIS_PRE_SHIFT (7U) +#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) +#define ENET_MSCR_HOLDTIME_MASK (0x700U) +#define ENET_MSCR_HOLDTIME_SHIFT (8U) +#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) + +/*! @name MIBC - MIB Control Register */ +#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) +#define ENET_MIBC_MIB_CLEAR_SHIFT (29U) +#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) +#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) +#define ENET_MIBC_MIB_IDLE_SHIFT (30U) +#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) +#define ENET_MIBC_MIB_DIS_MASK (0x80000000U) +#define ENET_MIBC_MIB_DIS_SHIFT (31U) +#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) + +/*! @name RCR - Receive Control Register */ +#define ENET_RCR_LOOP_MASK (0x1U) +#define ENET_RCR_LOOP_SHIFT (0U) +#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) +#define ENET_RCR_DRT_MASK (0x2U) +#define ENET_RCR_DRT_SHIFT (1U) +#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) +#define ENET_RCR_MII_MODE_MASK (0x4U) +#define ENET_RCR_MII_MODE_SHIFT (2U) +#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) +#define ENET_RCR_PROM_MASK (0x8U) +#define ENET_RCR_PROM_SHIFT (3U) +#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) +#define ENET_RCR_BC_REJ_MASK (0x10U) +#define ENET_RCR_BC_REJ_SHIFT (4U) +#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) +#define ENET_RCR_FCE_MASK (0x20U) +#define ENET_RCR_FCE_SHIFT (5U) +#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) +#define ENET_RCR_RMII_MODE_MASK (0x100U) +#define ENET_RCR_RMII_MODE_SHIFT (8U) +#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) +#define ENET_RCR_RMII_10T_MASK (0x200U) +#define ENET_RCR_RMII_10T_SHIFT (9U) +#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) +#define ENET_RCR_PADEN_MASK (0x1000U) +#define ENET_RCR_PADEN_SHIFT (12U) +#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) +#define ENET_RCR_PAUFWD_MASK (0x2000U) +#define ENET_RCR_PAUFWD_SHIFT (13U) +#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) +#define ENET_RCR_CRCFWD_MASK (0x4000U) +#define ENET_RCR_CRCFWD_SHIFT (14U) +#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) +#define ENET_RCR_CFEN_MASK (0x8000U) +#define ENET_RCR_CFEN_SHIFT (15U) +#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) +#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) +#define ENET_RCR_MAX_FL_SHIFT (16U) +#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) +#define ENET_RCR_NLC_MASK (0x40000000U) +#define ENET_RCR_NLC_SHIFT (30U) +#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) +#define ENET_RCR_GRS_MASK (0x80000000U) +#define ENET_RCR_GRS_SHIFT (31U) +#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) + +/*! @name TCR - Transmit Control Register */ +#define ENET_TCR_GTS_MASK (0x1U) +#define ENET_TCR_GTS_SHIFT (0U) +#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) +#define ENET_TCR_FDEN_MASK (0x4U) +#define ENET_TCR_FDEN_SHIFT (2U) +#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) +#define ENET_TCR_TFC_PAUSE_MASK (0x8U) +#define ENET_TCR_TFC_PAUSE_SHIFT (3U) +#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) +#define ENET_TCR_RFC_PAUSE_MASK (0x10U) +#define ENET_TCR_RFC_PAUSE_SHIFT (4U) +#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) +#define ENET_TCR_ADDSEL_MASK (0xE0U) +#define ENET_TCR_ADDSEL_SHIFT (5U) +#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) +#define ENET_TCR_ADDINS_MASK (0x100U) +#define ENET_TCR_ADDINS_SHIFT (8U) +#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) +#define ENET_TCR_CRCFWD_MASK (0x200U) +#define ENET_TCR_CRCFWD_SHIFT (9U) +#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) + +/*! @name PALR - Physical Address Lower Register */ +#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) +#define ENET_PALR_PADDR1_SHIFT (0U) +#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) + +/*! @name PAUR - Physical Address Upper Register */ +#define ENET_PAUR_TYPE_MASK (0xFFFFU) +#define ENET_PAUR_TYPE_SHIFT (0U) +#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) +#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) +#define ENET_PAUR_PADDR2_SHIFT (16U) +#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) + +/*! @name OPD - Opcode/Pause Duration Register */ +#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) +#define ENET_OPD_PAUSE_DUR_SHIFT (0U) +#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) +#define ENET_OPD_OPCODE_MASK (0xFFFF0000U) +#define ENET_OPD_OPCODE_SHIFT (16U) +#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) + +/*! @name TXIC - Transmit Interrupt Coalescing Register */ +#define ENET_TXIC_ICTT_MASK (0xFFFFU) +#define ENET_TXIC_ICTT_SHIFT (0U) +#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) +#define ENET_TXIC_ICFT_MASK (0xFF00000U) +#define ENET_TXIC_ICFT_SHIFT (20U) +#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) +#define ENET_TXIC_ICCS_MASK (0x40000000U) +#define ENET_TXIC_ICCS_SHIFT (30U) +#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) +#define ENET_TXIC_ICEN_MASK (0x80000000U) +#define ENET_TXIC_ICEN_SHIFT (31U) +#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) + +/*! @name RXIC - Receive Interrupt Coalescing Register */ +#define ENET_RXIC_ICTT_MASK (0xFFFFU) +#define ENET_RXIC_ICTT_SHIFT (0U) +#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) +#define ENET_RXIC_ICFT_MASK (0xFF00000U) +#define ENET_RXIC_ICFT_SHIFT (20U) +#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) +#define ENET_RXIC_ICCS_MASK (0x40000000U) +#define ENET_RXIC_ICCS_SHIFT (30U) +#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) +#define ENET_RXIC_ICEN_MASK (0x80000000U) +#define ENET_RXIC_ICEN_SHIFT (31U) +#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) + +/*! @name IAUR - Descriptor Individual Upper Address Register */ +#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) +#define ENET_IAUR_IADDR1_SHIFT (0U) +#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) + +/*! @name IALR - Descriptor Individual Lower Address Register */ +#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) +#define ENET_IALR_IADDR2_SHIFT (0U) +#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) + +/*! @name GAUR - Descriptor Group Upper Address Register */ +#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) +#define ENET_GAUR_GADDR1_SHIFT (0U) +#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) + +/*! @name GALR - Descriptor Group Lower Address Register */ +#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) +#define ENET_GALR_GADDR2_SHIFT (0U) +#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) + +/*! @name TFWR - Transmit FIFO Watermark Register */ +#define ENET_TFWR_TFWR_MASK (0x3FU) +#define ENET_TFWR_TFWR_SHIFT (0U) +#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) +#define ENET_TFWR_STRFWD_MASK (0x100U) +#define ENET_TFWR_STRFWD_SHIFT (8U) +#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) + +/*! @name RDSR - Receive Descriptor Ring Start Register */ +#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) +#define ENET_RDSR_R_DES_START_SHIFT (3U) +#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) + +/*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */ +#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) +#define ENET_TDSR_X_DES_START_SHIFT (3U) +#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) + +/*! @name MRBR - Maximum Receive Buffer Size Register */ +#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) +#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) +#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) + +/*! @name RSFL - Receive FIFO Section Full Threshold */ +#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU) +#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) +#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) + +/*! @name RSEM - Receive FIFO Section Empty Threshold */ +#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU) +#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) +#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) +#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) +#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) +#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) + +/*! @name RAEM - Receive FIFO Almost Empty Threshold */ +#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU) +#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) +#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) + +/*! @name RAFL - Receive FIFO Almost Full Threshold */ +#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU) +#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) +#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) + +/*! @name TSEM - Transmit FIFO Section Empty Threshold */ +#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU) +#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) +#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) + +/*! @name TAEM - Transmit FIFO Almost Empty Threshold */ +#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU) +#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) +#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) + +/*! @name TAFL - Transmit FIFO Almost Full Threshold */ +#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU) +#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) +#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) + +/*! @name TIPG - Transmit Inter-Packet Gap */ +#define ENET_TIPG_IPG_MASK (0x1FU) +#define ENET_TIPG_IPG_SHIFT (0U) +#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) + +/*! @name FTRL - Frame Truncation Length */ +#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) +#define ENET_FTRL_TRUNC_FL_SHIFT (0U) +#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) + +/*! @name TACC - Transmit Accelerator Function Configuration */ +#define ENET_TACC_SHIFT16_MASK (0x1U) +#define ENET_TACC_SHIFT16_SHIFT (0U) +#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) +#define ENET_TACC_IPCHK_MASK (0x8U) +#define ENET_TACC_IPCHK_SHIFT (3U) +#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) +#define ENET_TACC_PROCHK_MASK (0x10U) +#define ENET_TACC_PROCHK_SHIFT (4U) +#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) + +/*! @name RACC - Receive Accelerator Function Configuration */ +#define ENET_RACC_PADREM_MASK (0x1U) +#define ENET_RACC_PADREM_SHIFT (0U) +#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) +#define ENET_RACC_IPDIS_MASK (0x2U) +#define ENET_RACC_IPDIS_SHIFT (1U) +#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) +#define ENET_RACC_PRODIS_MASK (0x4U) +#define ENET_RACC_PRODIS_SHIFT (2U) +#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) +#define ENET_RACC_LINEDIS_MASK (0x40U) +#define ENET_RACC_LINEDIS_SHIFT (6U) +#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) +#define ENET_RACC_SHIFT16_MASK (0x80U) +#define ENET_RACC_SHIFT16_SHIFT (7U) +#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) + +/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ +#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) + +/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ +#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) + +/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ +#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) + +/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) + +/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ +#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) + +/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ +#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) + +/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) + +/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ +#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) + +/*! @name RMON_T_COL - Tx Collision Count Statistic Register */ +#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) + +/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ +#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) + +/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ +#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) + +/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ +#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) + +/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ +#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) + +/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ +#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) + +/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ +#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) + +/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ +#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) + +/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ +#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) +#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) +#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) + +/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ +#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) + +/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ +#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) + +/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ +#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) + +/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ +#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) +#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) + +/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ +#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) + +/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ +#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) + +/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ +#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) + +/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ +#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) + +/*! @name IEEE_T_SQE - Reserved Statistic Register */ +#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) +#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) + +/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ +#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) + +/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ +#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) + +/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ +#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) + +/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ +#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) + +/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ +#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) + +/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ +#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) +#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) + +/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ +#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) + +/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ +#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) + +/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) +#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) + +/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ +#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_JAB_COUNT_SHIFT (0U) +#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) + +/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ +#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P64_COUNT_SHIFT (0U) +#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) + +/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ +#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) +#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) + +/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ +#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) +#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) + +/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ +#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) +#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) + +/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ +#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) +#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) + +/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ +#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) +#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) + +/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ +#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) +#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) + +/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ +#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) +#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) + +/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ +#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) +#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) + +/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ +#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) + +/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ +#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) + +/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ +#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) +#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) + +/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ +#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) + +/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ +#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) + +/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ +#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) + +/*! @name ATCR - Adjustable Timer Control Register */ +#define ENET_ATCR_EN_MASK (0x1U) +#define ENET_ATCR_EN_SHIFT (0U) +#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) +#define ENET_ATCR_OFFEN_MASK (0x4U) +#define ENET_ATCR_OFFEN_SHIFT (2U) +#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) +#define ENET_ATCR_OFFRST_MASK (0x8U) +#define ENET_ATCR_OFFRST_SHIFT (3U) +#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) +#define ENET_ATCR_PEREN_MASK (0x10U) +#define ENET_ATCR_PEREN_SHIFT (4U) +#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) +#define ENET_ATCR_PINPER_MASK (0x80U) +#define ENET_ATCR_PINPER_SHIFT (7U) +#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) +#define ENET_ATCR_RESTART_MASK (0x200U) +#define ENET_ATCR_RESTART_SHIFT (9U) +#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) +#define ENET_ATCR_CAPTURE_MASK (0x800U) +#define ENET_ATCR_CAPTURE_SHIFT (11U) +#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) +#define ENET_ATCR_SLAVE_MASK (0x2000U) +#define ENET_ATCR_SLAVE_SHIFT (13U) +#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) + +/*! @name ATVR - Timer Value Register */ +#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) +#define ENET_ATVR_ATIME_SHIFT (0U) +#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) + +/*! @name ATOFF - Timer Offset Register */ +#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) +#define ENET_ATOFF_OFFSET_SHIFT (0U) +#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) + +/*! @name ATPER - Timer Period Register */ +#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) +#define ENET_ATPER_PERIOD_SHIFT (0U) +#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) + +/*! @name ATCOR - Timer Correction Register */ +#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) +#define ENET_ATCOR_COR_SHIFT (0U) +#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) + +/*! @name ATINC - Time-Stamping Clock Period Register */ +#define ENET_ATINC_INC_MASK (0x7FU) +#define ENET_ATINC_INC_SHIFT (0U) +#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) +#define ENET_ATINC_INC_CORR_MASK (0x7F00U) +#define ENET_ATINC_INC_CORR_SHIFT (8U) +#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) + +/*! @name ATSTMP - Timestamp of Last Transmitted Frame */ +#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) +#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) +#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) + +/*! @name TGSR - Timer Global Status Register */ +#define ENET_TGSR_TF0_MASK (0x1U) +#define ENET_TGSR_TF0_SHIFT (0U) +#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) +#define ENET_TGSR_TF1_MASK (0x2U) +#define ENET_TGSR_TF1_SHIFT (1U) +#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) +#define ENET_TGSR_TF2_MASK (0x4U) +#define ENET_TGSR_TF2_SHIFT (2U) +#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) +#define ENET_TGSR_TF3_MASK (0x8U) +#define ENET_TGSR_TF3_SHIFT (3U) +#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) + +/*! @name TCSR - Timer Control Status Register */ +#define ENET_TCSR_TDRE_MASK (0x1U) +#define ENET_TCSR_TDRE_SHIFT (0U) +#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) +#define ENET_TCSR_TMODE_MASK (0x3CU) +#define ENET_TCSR_TMODE_SHIFT (2U) +#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) +#define ENET_TCSR_TIE_MASK (0x40U) +#define ENET_TCSR_TIE_SHIFT (6U) +#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) +#define ENET_TCSR_TF_MASK (0x80U) +#define ENET_TCSR_TF_SHIFT (7U) +#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) +#define ENET_TCSR_TPWC_MASK (0xF800U) +#define ENET_TCSR_TPWC_SHIFT (11U) +#define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK) + +/* The count of ENET_TCSR */ +#define ENET_TCSR_COUNT (4U) + +/*! @name TCCR - Timer Compare Capture Register */ +#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) +#define ENET_TCCR_TCC_SHIFT (0U) +#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) + +/* The count of ENET_TCCR */ +#define ENET_TCCR_COUNT (4U) + + +/*! + * @} + */ /* end of group ENET_Register_Masks */ + + +/* ENET - Peripheral instance base addresses */ +/** Peripheral ENET1 base address */ +#define ENET1_BASE (0x2188000u) +/** Peripheral ENET1 base pointer */ +#define ENET1 ((ENET_Type *)ENET1_BASE) +/** Peripheral ENET2 base address */ +#define ENET2_BASE (0x20B4000u) +/** Peripheral ENET2 base pointer */ +#define ENET2 ((ENET_Type *)ENET2_BASE) +/** Array initializer of ENET peripheral base addresses */ +#define ENET_BASE_ADDRS { 0u, ENET1_BASE, ENET2_BASE } +/** Array initializer of ENET peripheral base pointers */ +#define ENET_BASE_PTRS { (ENET_Type *)0u, ENET1, ENET2 } +/** Interrupt vectors for the ENET peripheral type */ +#define ENET_Transmit_IRQS { NotAvail_IRQn, ENET1_IRQn, ENET2_IRQn } +#define ENET_Receive_IRQS { NotAvail_IRQn, ENET1_IRQn, ENET2_IRQn } +#define ENET_Error_IRQS { NotAvail_IRQn, ENET1_IRQn, ENET2_IRQn } +#define ENET_1588_Timer_IRQS { NotAvail_IRQn, ENET1_IRQn, ENET2_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + + +/*! + * @} + */ /* end of group ENET_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EPIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EPIT_Peripheral_Access_Layer EPIT Peripheral Access Layer + * @{ + */ + +/** EPIT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control register, offset: 0x0 */ + __IO uint32_t SR; /**< Status register, offset: 0x4 */ + __IO uint32_t LR; /**< Load register, offset: 0x8 */ + __IO uint32_t CMPR; /**< Compare register, offset: 0xC */ + __I uint32_t CNR; /**< Counter register, offset: 0x10 */ +} EPIT_Type; + +/* ---------------------------------------------------------------------------- + -- EPIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EPIT_Register_Masks EPIT Register Masks + * @{ + */ + +/*! @name CR - Control register */ +#define EPIT_CR_EN_MASK (0x1U) +#define EPIT_CR_EN_SHIFT (0U) +#define EPIT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_EN_SHIFT)) & EPIT_CR_EN_MASK) +#define EPIT_CR_ENMOD_MASK (0x2U) +#define EPIT_CR_ENMOD_SHIFT (1U) +#define EPIT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_ENMOD_SHIFT)) & EPIT_CR_ENMOD_MASK) +#define EPIT_CR_OCIEN_MASK (0x4U) +#define EPIT_CR_OCIEN_SHIFT (2U) +#define EPIT_CR_OCIEN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_OCIEN_SHIFT)) & EPIT_CR_OCIEN_MASK) +#define EPIT_CR_RLD_MASK (0x8U) +#define EPIT_CR_RLD_SHIFT (3U) +#define EPIT_CR_RLD(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_RLD_SHIFT)) & EPIT_CR_RLD_MASK) +#define EPIT_CR_PRESCALAR_MASK (0xFFF0U) +#define EPIT_CR_PRESCALAR_SHIFT (4U) +#define EPIT_CR_PRESCALAR(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_PRESCALAR_SHIFT)) & EPIT_CR_PRESCALAR_MASK) +#define EPIT_CR_SWR_MASK (0x10000U) +#define EPIT_CR_SWR_SHIFT (16U) +#define EPIT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_SWR_SHIFT)) & EPIT_CR_SWR_MASK) +#define EPIT_CR_IOVW_MASK (0x20000U) +#define EPIT_CR_IOVW_SHIFT (17U) +#define EPIT_CR_IOVW(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_IOVW_SHIFT)) & EPIT_CR_IOVW_MASK) +#define EPIT_CR_DBGEN_MASK (0x40000U) +#define EPIT_CR_DBGEN_SHIFT (18U) +#define EPIT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_DBGEN_SHIFT)) & EPIT_CR_DBGEN_MASK) +#define EPIT_CR_WAITEN_MASK (0x80000U) +#define EPIT_CR_WAITEN_SHIFT (19U) +#define EPIT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_WAITEN_SHIFT)) & EPIT_CR_WAITEN_MASK) +#define EPIT_CR_STOPEN_MASK (0x200000U) +#define EPIT_CR_STOPEN_SHIFT (21U) +#define EPIT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_STOPEN_SHIFT)) & EPIT_CR_STOPEN_MASK) +#define EPIT_CR_OM_MASK (0xC00000U) +#define EPIT_CR_OM_SHIFT (22U) +#define EPIT_CR_OM(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_OM_SHIFT)) & EPIT_CR_OM_MASK) +#define EPIT_CR_CLKSRC_MASK (0x3000000U) +#define EPIT_CR_CLKSRC_SHIFT (24U) +#define EPIT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CR_CLKSRC_SHIFT)) & EPIT_CR_CLKSRC_MASK) + +/*! @name SR - Status register */ +#define EPIT_SR_OCIF_MASK (0x1U) +#define EPIT_SR_OCIF_SHIFT (0U) +#define EPIT_SR_OCIF(x) (((uint32_t)(((uint32_t)(x)) << EPIT_SR_OCIF_SHIFT)) & EPIT_SR_OCIF_MASK) + +/*! @name LR - Load register */ +#define EPIT_LR_LOAD_MASK (0xFFFFFFFFU) +#define EPIT_LR_LOAD_SHIFT (0U) +#define EPIT_LR_LOAD(x) (((uint32_t)(((uint32_t)(x)) << EPIT_LR_LOAD_SHIFT)) & EPIT_LR_LOAD_MASK) + +/*! @name CMPR - Compare register */ +#define EPIT_CMPR_COMPARE_MASK (0xFFFFFFFFU) +#define EPIT_CMPR_COMPARE_SHIFT (0U) +#define EPIT_CMPR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CMPR_COMPARE_SHIFT)) & EPIT_CMPR_COMPARE_MASK) + +/*! @name CNR - Counter register */ +#define EPIT_CNR_COUNT_MASK (0xFFFFFFFFU) +#define EPIT_CNR_COUNT_SHIFT (0U) +#define EPIT_CNR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << EPIT_CNR_COUNT_SHIFT)) & EPIT_CNR_COUNT_MASK) + + +/*! + * @} + */ /* end of group EPIT_Register_Masks */ + + +/* EPIT - Peripheral instance base addresses */ +/** Peripheral EPIT1 base address */ +#define EPIT1_BASE (0x20D0000u) +/** Peripheral EPIT1 base pointer */ +#define EPIT1 ((EPIT_Type *)EPIT1_BASE) +/** Peripheral EPIT2 base address */ +#define EPIT2_BASE (0x20D4000u) +/** Peripheral EPIT2 base pointer */ +#define EPIT2 ((EPIT_Type *)EPIT2_BASE) +/** Array initializer of EPIT peripheral base addresses */ +#define EPIT_BASE_ADDRS { 0u, EPIT1_BASE, EPIT2_BASE } +/** Array initializer of EPIT peripheral base pointers */ +#define EPIT_BASE_PTRS { (EPIT_Type *)0u, EPIT1, EPIT2 } +/** Interrupt vectors for the EPIT peripheral type */ +#define EPIT_IRQS { NotAvail_IRQn, EPIT1_IRQn, EPIT2_IRQn } + +/*! + * @} + */ /* end of group EPIT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ESAI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ESAI_Peripheral_Access_Layer ESAI Peripheral Access Layer + * @{ + */ + +/** ESAI - Register Layout Typedef */ +typedef struct { + __O uint32_t ETDR; /**< ESAI Transmit Data Register, offset: 0x0 */ + __I uint32_t ERDR; /**< ESAI Receive Data Register, offset: 0x4 */ + __IO uint32_t ECR; /**< ESAI Control Register, offset: 0x8 */ + __I uint32_t ESR; /**< ESAI Status Register, offset: 0xC */ + __IO uint32_t TFCR; /**< Transmit FIFO Configuration Register, offset: 0x10 */ + __I uint32_t TFSR; /**< Transmit FIFO Status Register, offset: 0x14 */ + __IO uint32_t RFCR; /**< Receive FIFO Configuration Register, offset: 0x18 */ + __I uint32_t RFSR; /**< Receive FIFO Status Register, offset: 0x1C */ + uint8_t RESERVED_0[96]; + __IO uint32_t TX[6]; /**< Transmit Data Register n, array offset: 0x80, array step: 0x4 */ + __IO uint32_t TSR; /**< ESAI Transmit Slot Register, offset: 0x98 */ + uint8_t RESERVED_1[4]; + __I uint32_t RX[4]; /**< Receive Data Register n, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_2[28]; + __I uint32_t SAISR; /**< Serial Audio Interface Status Register, offset: 0xCC */ + __IO uint32_t SAICR; /**< Serial Audio Interface Control Register, offset: 0xD0 */ + __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xD4 */ + __IO uint32_t TCCR; /**< Transmit Clock Control Register, offset: 0xD8 */ + __IO uint32_t RCR; /**< Receive Control Register, offset: 0xDC */ + __IO uint32_t RCCR; /**< Receive Clock Control Register, offset: 0xE0 */ + __IO uint32_t TSMA; /**< Transmit Slot Mask Register A, offset: 0xE4 */ + __IO uint32_t TSMB; /**< Transmit Slot Mask Register B, offset: 0xE8 */ + __IO uint32_t RSMA; /**< Receive Slot Mask Register A, offset: 0xEC */ + __IO uint32_t RSMB; /**< Receive Slot Mask Register B, offset: 0xF0 */ + uint8_t RESERVED_3[4]; + __IO uint32_t PRRC; /**< Port C Direction Register, offset: 0xF8 */ + __IO uint32_t PCRC; /**< Port C Control Register, offset: 0xFC */ +} ESAI_Type; + +/* ---------------------------------------------------------------------------- + -- ESAI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ESAI_Register_Masks ESAI Register Masks + * @{ + */ + +/*! @name ETDR - ESAI Transmit Data Register */ +#define ESAI_ETDR_ETDR_MASK (0xFFFFFFFFU) +#define ESAI_ETDR_ETDR_SHIFT (0U) +#define ESAI_ETDR_ETDR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ETDR_ETDR_SHIFT)) & ESAI_ETDR_ETDR_MASK) + +/*! @name ERDR - ESAI Receive Data Register */ +#define ESAI_ERDR_ERDR_MASK (0xFFFFFFFFU) +#define ESAI_ERDR_ERDR_SHIFT (0U) +#define ESAI_ERDR_ERDR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ERDR_ERDR_SHIFT)) & ESAI_ERDR_ERDR_MASK) + +/*! @name ECR - ESAI Control Register */ +#define ESAI_ECR_ESAIEN_MASK (0x1U) +#define ESAI_ECR_ESAIEN_SHIFT (0U) +#define ESAI_ECR_ESAIEN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ESAIEN_SHIFT)) & ESAI_ECR_ESAIEN_MASK) +#define ESAI_ECR_ERST_MASK (0x2U) +#define ESAI_ECR_ERST_SHIFT (1U) +#define ESAI_ECR_ERST(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERST_SHIFT)) & ESAI_ECR_ERST_MASK) +#define ESAI_ECR_ERO_MASK (0x10000U) +#define ESAI_ECR_ERO_SHIFT (16U) +#define ESAI_ECR_ERO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERO_SHIFT)) & ESAI_ECR_ERO_MASK) +#define ESAI_ECR_ERI_MASK (0x20000U) +#define ESAI_ECR_ERI_SHIFT (17U) +#define ESAI_ECR_ERI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERI_SHIFT)) & ESAI_ECR_ERI_MASK) +#define ESAI_ECR_ETO_MASK (0x40000U) +#define ESAI_ECR_ETO_SHIFT (18U) +#define ESAI_ECR_ETO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ETO_SHIFT)) & ESAI_ECR_ETO_MASK) +#define ESAI_ECR_ETI_MASK (0x80000U) +#define ESAI_ECR_ETI_SHIFT (19U) +#define ESAI_ECR_ETI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ETI_SHIFT)) & ESAI_ECR_ETI_MASK) + +/*! @name ESR - ESAI Status Register */ +#define ESAI_ESR_RD_MASK (0x1U) +#define ESAI_ESR_RD_SHIFT (0U) +#define ESAI_ESR_RD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RD_SHIFT)) & ESAI_ESR_RD_MASK) +#define ESAI_ESR_RED_MASK (0x2U) +#define ESAI_ESR_RED_SHIFT (1U) +#define ESAI_ESR_RED(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RED_SHIFT)) & ESAI_ESR_RED_MASK) +#define ESAI_ESR_RDE_MASK (0x4U) +#define ESAI_ESR_RDE_SHIFT (2U) +#define ESAI_ESR_RDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RDE_SHIFT)) & ESAI_ESR_RDE_MASK) +#define ESAI_ESR_RLS_MASK (0x8U) +#define ESAI_ESR_RLS_SHIFT (3U) +#define ESAI_ESR_RLS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RLS_SHIFT)) & ESAI_ESR_RLS_MASK) +#define ESAI_ESR_TD_MASK (0x10U) +#define ESAI_ESR_TD_SHIFT (4U) +#define ESAI_ESR_TD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TD_SHIFT)) & ESAI_ESR_TD_MASK) +#define ESAI_ESR_TED_MASK (0x20U) +#define ESAI_ESR_TED_SHIFT (5U) +#define ESAI_ESR_TED(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TED_SHIFT)) & ESAI_ESR_TED_MASK) +#define ESAI_ESR_TDE_MASK (0x40U) +#define ESAI_ESR_TDE_SHIFT (6U) +#define ESAI_ESR_TDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TDE_SHIFT)) & ESAI_ESR_TDE_MASK) +#define ESAI_ESR_TLS_MASK (0x80U) +#define ESAI_ESR_TLS_SHIFT (7U) +#define ESAI_ESR_TLS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TLS_SHIFT)) & ESAI_ESR_TLS_MASK) +#define ESAI_ESR_TFE_MASK (0x100U) +#define ESAI_ESR_TFE_SHIFT (8U) +#define ESAI_ESR_TFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TFE_SHIFT)) & ESAI_ESR_TFE_MASK) +#define ESAI_ESR_RFF_MASK (0x200U) +#define ESAI_ESR_RFF_SHIFT (9U) +#define ESAI_ESR_RFF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RFF_SHIFT)) & ESAI_ESR_RFF_MASK) +#define ESAI_ESR_TINIT_MASK (0x400U) +#define ESAI_ESR_TINIT_SHIFT (10U) +#define ESAI_ESR_TINIT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TINIT_SHIFT)) & ESAI_ESR_TINIT_MASK) + +/*! @name TFCR - Transmit FIFO Configuration Register */ +#define ESAI_TFCR_TFE_MASK (0x1U) +#define ESAI_TFCR_TFE_SHIFT (0U) +#define ESAI_TFCR_TFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFE_SHIFT)) & ESAI_TFCR_TFE_MASK) +#define ESAI_TFCR_TFR_MASK (0x2U) +#define ESAI_TFCR_TFR_SHIFT (1U) +#define ESAI_TFCR_TFR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFR_SHIFT)) & ESAI_TFCR_TFR_MASK) +#define ESAI_TFCR_TE0_MASK (0x4U) +#define ESAI_TFCR_TE0_SHIFT (2U) +#define ESAI_TFCR_TE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE0_SHIFT)) & ESAI_TFCR_TE0_MASK) +#define ESAI_TFCR_TE1_MASK (0x8U) +#define ESAI_TFCR_TE1_SHIFT (3U) +#define ESAI_TFCR_TE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE1_SHIFT)) & ESAI_TFCR_TE1_MASK) +#define ESAI_TFCR_TE2_MASK (0x10U) +#define ESAI_TFCR_TE2_SHIFT (4U) +#define ESAI_TFCR_TE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE2_SHIFT)) & ESAI_TFCR_TE2_MASK) +#define ESAI_TFCR_TE3_MASK (0x20U) +#define ESAI_TFCR_TE3_SHIFT (5U) +#define ESAI_TFCR_TE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE3_SHIFT)) & ESAI_TFCR_TE3_MASK) +#define ESAI_TFCR_TE4_MASK (0x40U) +#define ESAI_TFCR_TE4_SHIFT (6U) +#define ESAI_TFCR_TE4(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE4_SHIFT)) & ESAI_TFCR_TE4_MASK) +#define ESAI_TFCR_TE5_MASK (0x80U) +#define ESAI_TFCR_TE5_SHIFT (7U) +#define ESAI_TFCR_TE5(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE5_SHIFT)) & ESAI_TFCR_TE5_MASK) +#define ESAI_TFCR_TFWM_MASK (0xFF00U) +#define ESAI_TFCR_TFWM_SHIFT (8U) +#define ESAI_TFCR_TFWM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFWM_SHIFT)) & ESAI_TFCR_TFWM_MASK) +#define ESAI_TFCR_TWA_MASK (0x70000U) +#define ESAI_TFCR_TWA_SHIFT (16U) +#define ESAI_TFCR_TWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TWA_SHIFT)) & ESAI_TFCR_TWA_MASK) +#define ESAI_TFCR_TIEN_MASK (0x80000U) +#define ESAI_TFCR_TIEN_SHIFT (19U) +#define ESAI_TFCR_TIEN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TIEN_SHIFT)) & ESAI_TFCR_TIEN_MASK) +#define ESAI_TFCR_TAENB_MASK (0x100000U) +#define ESAI_TFCR_TAENB_SHIFT (20U) +#define ESAI_TFCR_TAENB(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TAENB_SHIFT)) & ESAI_TFCR_TAENB_MASK) +#define ESAI_TFCR_TFIN_MASK (0x200000U) +#define ESAI_TFCR_TFIN_SHIFT (21U) +#define ESAI_TFCR_TFIN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFIN_SHIFT)) & ESAI_TFCR_TFIN_MASK) + +/*! @name TFSR - Transmit FIFO Status Register */ +#define ESAI_TFSR_TFCNT_MASK (0xFFU) +#define ESAI_TFSR_TFCNT_SHIFT (0U) +#define ESAI_TFSR_TFCNT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_TFCNT_SHIFT)) & ESAI_TFSR_TFCNT_MASK) +#define ESAI_TFSR_NTFI_MASK (0x700U) +#define ESAI_TFSR_NTFI_SHIFT (8U) +#define ESAI_TFSR_NTFI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_NTFI_SHIFT)) & ESAI_TFSR_NTFI_MASK) +#define ESAI_TFSR_NTFO_MASK (0x7000U) +#define ESAI_TFSR_NTFO_SHIFT (12U) +#define ESAI_TFSR_NTFO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_NTFO_SHIFT)) & ESAI_TFSR_NTFO_MASK) + +/*! @name RFCR - Receive FIFO Configuration Register */ +#define ESAI_RFCR_RFE_MASK (0x1U) +#define ESAI_RFCR_RFE_SHIFT (0U) +#define ESAI_RFCR_RFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFE_SHIFT)) & ESAI_RFCR_RFE_MASK) +#define ESAI_RFCR_RFR_MASK (0x2U) +#define ESAI_RFCR_RFR_SHIFT (1U) +#define ESAI_RFCR_RFR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFR_SHIFT)) & ESAI_RFCR_RFR_MASK) +#define ESAI_RFCR_RE0_MASK (0x4U) +#define ESAI_RFCR_RE0_SHIFT (2U) +#define ESAI_RFCR_RE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE0_SHIFT)) & ESAI_RFCR_RE0_MASK) +#define ESAI_RFCR_RE1_MASK (0x8U) +#define ESAI_RFCR_RE1_SHIFT (3U) +#define ESAI_RFCR_RE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE1_SHIFT)) & ESAI_RFCR_RE1_MASK) +#define ESAI_RFCR_RE2_MASK (0x10U) +#define ESAI_RFCR_RE2_SHIFT (4U) +#define ESAI_RFCR_RE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE2_SHIFT)) & ESAI_RFCR_RE2_MASK) +#define ESAI_RFCR_RE3_MASK (0x20U) +#define ESAI_RFCR_RE3_SHIFT (5U) +#define ESAI_RFCR_RE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE3_SHIFT)) & ESAI_RFCR_RE3_MASK) +#define ESAI_RFCR_RFWM_MASK (0xFF00U) +#define ESAI_RFCR_RFWM_SHIFT (8U) +#define ESAI_RFCR_RFWM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFWM_SHIFT)) & ESAI_RFCR_RFWM_MASK) +#define ESAI_RFCR_RWA_MASK (0x70000U) +#define ESAI_RFCR_RWA_SHIFT (16U) +#define ESAI_RFCR_RWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RWA_SHIFT)) & ESAI_RFCR_RWA_MASK) +#define ESAI_RFCR_REXT_MASK (0x80000U) +#define ESAI_RFCR_REXT_SHIFT (19U) +#define ESAI_RFCR_REXT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_REXT_SHIFT)) & ESAI_RFCR_REXT_MASK) +#define ESAI_RFCR_RAENB_MASK (0x100000U) +#define ESAI_RFCR_RAENB_SHIFT (20U) +#define ESAI_RFCR_RAENB(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RAENB_SHIFT)) & ESAI_RFCR_RAENB_MASK) +#define ESAI_RFCR_RFIN_MASK (0x200000U) +#define ESAI_RFCR_RFIN_SHIFT (21U) +#define ESAI_RFCR_RFIN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFIN_SHIFT)) & ESAI_RFCR_RFIN_MASK) + +/*! @name RFSR - Receive FIFO Status Register */ +#define ESAI_RFSR_RFCNT_MASK (0xFFU) +#define ESAI_RFSR_RFCNT_SHIFT (0U) +#define ESAI_RFSR_RFCNT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_RFCNT_SHIFT)) & ESAI_RFSR_RFCNT_MASK) +#define ESAI_RFSR_NRFO_MASK (0x300U) +#define ESAI_RFSR_NRFO_SHIFT (8U) +#define ESAI_RFSR_NRFO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_NRFO_SHIFT)) & ESAI_RFSR_NRFO_MASK) +#define ESAI_RFSR_NRFI_MASK (0x3000U) +#define ESAI_RFSR_NRFI_SHIFT (12U) +#define ESAI_RFSR_NRFI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_NRFI_SHIFT)) & ESAI_RFSR_NRFI_MASK) + +/*! @name TX - Transmit Data Register n */ +#define ESAI_TX_TXn_MASK (0xFFFFFFU) +#define ESAI_TX_TXn_SHIFT (0U) +#define ESAI_TX_TXn(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TX_TXn_SHIFT)) & ESAI_TX_TXn_MASK) + +/* The count of ESAI_TX */ +#define ESAI_TX_COUNT (6U) + +/*! @name TSR - ESAI Transmit Slot Register */ +#define ESAI_TSR_TSR_MASK (0xFFFFFFU) +#define ESAI_TSR_TSR_SHIFT (0U) +#define ESAI_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TSR_TSR_SHIFT)) & ESAI_TSR_TSR_MASK) + +/*! @name RX - Receive Data Register n */ +#define ESAI_RX_RXn_MASK (0xFFFFFFU) +#define ESAI_RX_RXn_SHIFT (0U) +#define ESAI_RX_RXn(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RX_RXn_SHIFT)) & ESAI_RX_RXn_MASK) + +/* The count of ESAI_RX */ +#define ESAI_RX_COUNT (4U) + +/*! @name SAISR - Serial Audio Interface Status Register */ +#define ESAI_SAISR_IF0_MASK (0x1U) +#define ESAI_SAISR_IF0_SHIFT (0U) +#define ESAI_SAISR_IF0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF0_SHIFT)) & ESAI_SAISR_IF0_MASK) +#define ESAI_SAISR_IF1_MASK (0x2U) +#define ESAI_SAISR_IF1_SHIFT (1U) +#define ESAI_SAISR_IF1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF1_SHIFT)) & ESAI_SAISR_IF1_MASK) +#define ESAI_SAISR_IF2_MASK (0x4U) +#define ESAI_SAISR_IF2_SHIFT (2U) +#define ESAI_SAISR_IF2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF2_SHIFT)) & ESAI_SAISR_IF2_MASK) +#define ESAI_SAISR_RFS_MASK (0x40U) +#define ESAI_SAISR_RFS_SHIFT (6U) +#define ESAI_SAISR_RFS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RFS_SHIFT)) & ESAI_SAISR_RFS_MASK) +#define ESAI_SAISR_ROE_MASK (0x80U) +#define ESAI_SAISR_ROE_SHIFT (7U) +#define ESAI_SAISR_ROE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_ROE_SHIFT)) & ESAI_SAISR_ROE_MASK) +#define ESAI_SAISR_RDF_MASK (0x100U) +#define ESAI_SAISR_RDF_SHIFT (8U) +#define ESAI_SAISR_RDF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RDF_SHIFT)) & ESAI_SAISR_RDF_MASK) +#define ESAI_SAISR_REDF_MASK (0x200U) +#define ESAI_SAISR_REDF_SHIFT (9U) +#define ESAI_SAISR_REDF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_REDF_SHIFT)) & ESAI_SAISR_REDF_MASK) +#define ESAI_SAISR_RODF_MASK (0x400U) +#define ESAI_SAISR_RODF_SHIFT (10U) +#define ESAI_SAISR_RODF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RODF_SHIFT)) & ESAI_SAISR_RODF_MASK) +#define ESAI_SAISR_TFS_MASK (0x2000U) +#define ESAI_SAISR_TFS_SHIFT (13U) +#define ESAI_SAISR_TFS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TFS_SHIFT)) & ESAI_SAISR_TFS_MASK) +#define ESAI_SAISR_TUE_MASK (0x4000U) +#define ESAI_SAISR_TUE_SHIFT (14U) +#define ESAI_SAISR_TUE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TUE_SHIFT)) & ESAI_SAISR_TUE_MASK) +#define ESAI_SAISR_TDE_MASK (0x8000U) +#define ESAI_SAISR_TDE_SHIFT (15U) +#define ESAI_SAISR_TDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TDE_SHIFT)) & ESAI_SAISR_TDE_MASK) +#define ESAI_SAISR_TEDE_MASK (0x10000U) +#define ESAI_SAISR_TEDE_SHIFT (16U) +#define ESAI_SAISR_TEDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TEDE_SHIFT)) & ESAI_SAISR_TEDE_MASK) +#define ESAI_SAISR_TODFE_MASK (0x20000U) +#define ESAI_SAISR_TODFE_SHIFT (17U) +#define ESAI_SAISR_TODFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TODFE_SHIFT)) & ESAI_SAISR_TODFE_MASK) + +/*! @name SAICR - Serial Audio Interface Control Register */ +#define ESAI_SAICR_OF0_MASK (0x1U) +#define ESAI_SAICR_OF0_SHIFT (0U) +#define ESAI_SAICR_OF0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF0_SHIFT)) & ESAI_SAICR_OF0_MASK) +#define ESAI_SAICR_OF1_MASK (0x2U) +#define ESAI_SAICR_OF1_SHIFT (1U) +#define ESAI_SAICR_OF1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF1_SHIFT)) & ESAI_SAICR_OF1_MASK) +#define ESAI_SAICR_OF2_MASK (0x4U) +#define ESAI_SAICR_OF2_SHIFT (2U) +#define ESAI_SAICR_OF2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF2_SHIFT)) & ESAI_SAICR_OF2_MASK) +#define ESAI_SAICR_SYN_MASK (0x40U) +#define ESAI_SAICR_SYN_SHIFT (6U) +#define ESAI_SAICR_SYN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_SYN_SHIFT)) & ESAI_SAICR_SYN_MASK) +#define ESAI_SAICR_TEBE_MASK (0x80U) +#define ESAI_SAICR_TEBE_SHIFT (7U) +#define ESAI_SAICR_TEBE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_TEBE_SHIFT)) & ESAI_SAICR_TEBE_MASK) +#define ESAI_SAICR_ALC_MASK (0x100U) +#define ESAI_SAICR_ALC_SHIFT (8U) +#define ESAI_SAICR_ALC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_ALC_SHIFT)) & ESAI_SAICR_ALC_MASK) + +/*! @name TCR - Transmit Control Register */ +#define ESAI_TCR_TE0_MASK (0x1U) +#define ESAI_TCR_TE0_SHIFT (0U) +#define ESAI_TCR_TE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE0_SHIFT)) & ESAI_TCR_TE0_MASK) +#define ESAI_TCR_TE1_MASK (0x2U) +#define ESAI_TCR_TE1_SHIFT (1U) +#define ESAI_TCR_TE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE1_SHIFT)) & ESAI_TCR_TE1_MASK) +#define ESAI_TCR_TE2_MASK (0x4U) +#define ESAI_TCR_TE2_SHIFT (2U) +#define ESAI_TCR_TE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE2_SHIFT)) & ESAI_TCR_TE2_MASK) +#define ESAI_TCR_TE3_MASK (0x8U) +#define ESAI_TCR_TE3_SHIFT (3U) +#define ESAI_TCR_TE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE3_SHIFT)) & ESAI_TCR_TE3_MASK) +#define ESAI_TCR_TE4_MASK (0x10U) +#define ESAI_TCR_TE4_SHIFT (4U) +#define ESAI_TCR_TE4(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE4_SHIFT)) & ESAI_TCR_TE4_MASK) +#define ESAI_TCR_TE5_MASK (0x20U) +#define ESAI_TCR_TE5_SHIFT (5U) +#define ESAI_TCR_TE5(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE5_SHIFT)) & ESAI_TCR_TE5_MASK) +#define ESAI_TCR_TSHFD_MASK (0x40U) +#define ESAI_TCR_TSHFD_SHIFT (6U) +#define ESAI_TCR_TSHFD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TSHFD_SHIFT)) & ESAI_TCR_TSHFD_MASK) +#define ESAI_TCR_TWA_MASK (0x80U) +#define ESAI_TCR_TWA_SHIFT (7U) +#define ESAI_TCR_TWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TWA_SHIFT)) & ESAI_TCR_TWA_MASK) +#define ESAI_TCR_TMOD_MASK (0x300U) +#define ESAI_TCR_TMOD_SHIFT (8U) +#define ESAI_TCR_TMOD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TMOD_SHIFT)) & ESAI_TCR_TMOD_MASK) +#define ESAI_TCR_TSWS_MASK (0x7C00U) +#define ESAI_TCR_TSWS_SHIFT (10U) +#define ESAI_TCR_TSWS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TSWS_SHIFT)) & ESAI_TCR_TSWS_MASK) +#define ESAI_TCR_TFSL_MASK (0x8000U) +#define ESAI_TCR_TFSL_SHIFT (15U) +#define ESAI_TCR_TFSL(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TFSL_SHIFT)) & ESAI_TCR_TFSL_MASK) +#define ESAI_TCR_TFSR_MASK (0x10000U) +#define ESAI_TCR_TFSR_SHIFT (16U) +#define ESAI_TCR_TFSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TFSR_SHIFT)) & ESAI_TCR_TFSR_MASK) +#define ESAI_TCR_PADC_MASK (0x20000U) +#define ESAI_TCR_PADC_SHIFT (17U) +#define ESAI_TCR_PADC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_PADC_SHIFT)) & ESAI_TCR_PADC_MASK) +#define ESAI_TCR_TPR_MASK (0x80000U) +#define ESAI_TCR_TPR_SHIFT (19U) +#define ESAI_TCR_TPR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TPR_SHIFT)) & ESAI_TCR_TPR_MASK) +#define ESAI_TCR_TEIE_MASK (0x100000U) +#define ESAI_TCR_TEIE_SHIFT (20U) +#define ESAI_TCR_TEIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TEIE_SHIFT)) & ESAI_TCR_TEIE_MASK) +#define ESAI_TCR_TEDIE_MASK (0x200000U) +#define ESAI_TCR_TEDIE_SHIFT (21U) +#define ESAI_TCR_TEDIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TEDIE_SHIFT)) & ESAI_TCR_TEDIE_MASK) +#define ESAI_TCR_TIE_MASK (0x400000U) +#define ESAI_TCR_TIE_SHIFT (22U) +#define ESAI_TCR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TIE_SHIFT)) & ESAI_TCR_TIE_MASK) +#define ESAI_TCR_TLIE_MASK (0x800000U) +#define ESAI_TCR_TLIE_SHIFT (23U) +#define ESAI_TCR_TLIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TLIE_SHIFT)) & ESAI_TCR_TLIE_MASK) + +/*! @name TCCR - Transmit Clock Control Register */ +#define ESAI_TCCR_TPM_MASK (0xFFU) +#define ESAI_TCCR_TPM_SHIFT (0U) +#define ESAI_TCCR_TPM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TPM_SHIFT)) & ESAI_TCCR_TPM_MASK) +#define ESAI_TCCR_TPSR_MASK (0x100U) +#define ESAI_TCCR_TPSR_SHIFT (8U) +#define ESAI_TCCR_TPSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TPSR_SHIFT)) & ESAI_TCCR_TPSR_MASK) +#define ESAI_TCCR_TDC_MASK (0x3E00U) +#define ESAI_TCCR_TDC_SHIFT (9U) +#define ESAI_TCCR_TDC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TDC_SHIFT)) & ESAI_TCCR_TDC_MASK) +#define ESAI_TCCR_TFP_MASK (0x3C000U) +#define ESAI_TCCR_TFP_SHIFT (14U) +#define ESAI_TCCR_TFP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFP_SHIFT)) & ESAI_TCCR_TFP_MASK) +#define ESAI_TCCR_TCKP_MASK (0x40000U) +#define ESAI_TCCR_TCKP_SHIFT (18U) +#define ESAI_TCCR_TCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TCKP_SHIFT)) & ESAI_TCCR_TCKP_MASK) +#define ESAI_TCCR_TFSP_MASK (0x80000U) +#define ESAI_TCCR_TFSP_SHIFT (19U) +#define ESAI_TCCR_TFSP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFSP_SHIFT)) & ESAI_TCCR_TFSP_MASK) +#define ESAI_TCCR_THCKP_MASK (0x100000U) +#define ESAI_TCCR_THCKP_SHIFT (20U) +#define ESAI_TCCR_THCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_THCKP_SHIFT)) & ESAI_TCCR_THCKP_MASK) +#define ESAI_TCCR_TCKD_MASK (0x200000U) +#define ESAI_TCCR_TCKD_SHIFT (21U) +#define ESAI_TCCR_TCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TCKD_SHIFT)) & ESAI_TCCR_TCKD_MASK) +#define ESAI_TCCR_TFSD_MASK (0x400000U) +#define ESAI_TCCR_TFSD_SHIFT (22U) +#define ESAI_TCCR_TFSD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFSD_SHIFT)) & ESAI_TCCR_TFSD_MASK) +#define ESAI_TCCR_THCKD_MASK (0x800000U) +#define ESAI_TCCR_THCKD_SHIFT (23U) +#define ESAI_TCCR_THCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_THCKD_SHIFT)) & ESAI_TCCR_THCKD_MASK) + +/*! @name RCR - Receive Control Register */ +#define ESAI_RCR_RE0_MASK (0x1U) +#define ESAI_RCR_RE0_SHIFT (0U) +#define ESAI_RCR_RE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE0_SHIFT)) & ESAI_RCR_RE0_MASK) +#define ESAI_RCR_RE1_MASK (0x2U) +#define ESAI_RCR_RE1_SHIFT (1U) +#define ESAI_RCR_RE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE1_SHIFT)) & ESAI_RCR_RE1_MASK) +#define ESAI_RCR_RE2_MASK (0x4U) +#define ESAI_RCR_RE2_SHIFT (2U) +#define ESAI_RCR_RE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE2_SHIFT)) & ESAI_RCR_RE2_MASK) +#define ESAI_RCR_RE3_MASK (0x8U) +#define ESAI_RCR_RE3_SHIFT (3U) +#define ESAI_RCR_RE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE3_SHIFT)) & ESAI_RCR_RE3_MASK) +#define ESAI_RCR_RSHFD_MASK (0x40U) +#define ESAI_RCR_RSHFD_SHIFT (6U) +#define ESAI_RCR_RSHFD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RSHFD_SHIFT)) & ESAI_RCR_RSHFD_MASK) +#define ESAI_RCR_RWA_MASK (0x80U) +#define ESAI_RCR_RWA_SHIFT (7U) +#define ESAI_RCR_RWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RWA_SHIFT)) & ESAI_RCR_RWA_MASK) +#define ESAI_RCR_RMOD_MASK (0x300U) +#define ESAI_RCR_RMOD_SHIFT (8U) +#define ESAI_RCR_RMOD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RMOD_SHIFT)) & ESAI_RCR_RMOD_MASK) +#define ESAI_RCR_RSWS_MASK (0x7C00U) +#define ESAI_RCR_RSWS_SHIFT (10U) +#define ESAI_RCR_RSWS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RSWS_SHIFT)) & ESAI_RCR_RSWS_MASK) +#define ESAI_RCR_RFSL_MASK (0x8000U) +#define ESAI_RCR_RFSL_SHIFT (15U) +#define ESAI_RCR_RFSL(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RFSL_SHIFT)) & ESAI_RCR_RFSL_MASK) +#define ESAI_RCR_RFSR_MASK (0x10000U) +#define ESAI_RCR_RFSR_SHIFT (16U) +#define ESAI_RCR_RFSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RFSR_SHIFT)) & ESAI_RCR_RFSR_MASK) +#define ESAI_RCR_RPR_MASK (0x80000U) +#define ESAI_RCR_RPR_SHIFT (19U) +#define ESAI_RCR_RPR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RPR_SHIFT)) & ESAI_RCR_RPR_MASK) +#define ESAI_RCR_REIE_MASK (0x100000U) +#define ESAI_RCR_REIE_SHIFT (20U) +#define ESAI_RCR_REIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_REIE_SHIFT)) & ESAI_RCR_REIE_MASK) +#define ESAI_RCR_REDIE_MASK (0x200000U) +#define ESAI_RCR_REDIE_SHIFT (21U) +#define ESAI_RCR_REDIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_REDIE_SHIFT)) & ESAI_RCR_REDIE_MASK) +#define ESAI_RCR_RIE_MASK (0x400000U) +#define ESAI_RCR_RIE_SHIFT (22U) +#define ESAI_RCR_RIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RIE_SHIFT)) & ESAI_RCR_RIE_MASK) +#define ESAI_RCR_RLIE_MASK (0x800000U) +#define ESAI_RCR_RLIE_SHIFT (23U) +#define ESAI_RCR_RLIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RLIE_SHIFT)) & ESAI_RCR_RLIE_MASK) + +/*! @name RCCR - Receive Clock Control Register */ +#define ESAI_RCCR_RPM_MASK (0xFFU) +#define ESAI_RCCR_RPM_SHIFT (0U) +#define ESAI_RCCR_RPM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RPM_SHIFT)) & ESAI_RCCR_RPM_MASK) +#define ESAI_RCCR_RPSR_MASK (0x100U) +#define ESAI_RCCR_RPSR_SHIFT (8U) +#define ESAI_RCCR_RPSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RPSR_SHIFT)) & ESAI_RCCR_RPSR_MASK) +#define ESAI_RCCR_RDC_MASK (0x3E00U) +#define ESAI_RCCR_RDC_SHIFT (9U) +#define ESAI_RCCR_RDC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RDC_SHIFT)) & ESAI_RCCR_RDC_MASK) +#define ESAI_RCCR_RFP_MASK (0x3C000U) +#define ESAI_RCCR_RFP_SHIFT (14U) +#define ESAI_RCCR_RFP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFP_SHIFT)) & ESAI_RCCR_RFP_MASK) +#define ESAI_RCCR_RCKP_MASK (0x40000U) +#define ESAI_RCCR_RCKP_SHIFT (18U) +#define ESAI_RCCR_RCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RCKP_SHIFT)) & ESAI_RCCR_RCKP_MASK) +#define ESAI_RCCR_RFSP_MASK (0x80000U) +#define ESAI_RCCR_RFSP_SHIFT (19U) +#define ESAI_RCCR_RFSP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFSP_SHIFT)) & ESAI_RCCR_RFSP_MASK) +#define ESAI_RCCR_RHCKP_MASK (0x100000U) +#define ESAI_RCCR_RHCKP_SHIFT (20U) +#define ESAI_RCCR_RHCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RHCKP_SHIFT)) & ESAI_RCCR_RHCKP_MASK) +#define ESAI_RCCR_RCKD_MASK (0x200000U) +#define ESAI_RCCR_RCKD_SHIFT (21U) +#define ESAI_RCCR_RCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RCKD_SHIFT)) & ESAI_RCCR_RCKD_MASK) +#define ESAI_RCCR_RFSD_MASK (0x400000U) +#define ESAI_RCCR_RFSD_SHIFT (22U) +#define ESAI_RCCR_RFSD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFSD_SHIFT)) & ESAI_RCCR_RFSD_MASK) +#define ESAI_RCCR_RHCKD_MASK (0x800000U) +#define ESAI_RCCR_RHCKD_SHIFT (23U) +#define ESAI_RCCR_RHCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RHCKD_SHIFT)) & ESAI_RCCR_RHCKD_MASK) + +/*! @name TSMA - Transmit Slot Mask Register A */ +#define ESAI_TSMA_TS_MASK (0xFFFFU) +#define ESAI_TSMA_TS_SHIFT (0U) +#define ESAI_TSMA_TS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TSMA_TS_SHIFT)) & ESAI_TSMA_TS_MASK) + +/*! @name TSMB - Transmit Slot Mask Register B */ +#define ESAI_TSMB_TS_MASK (0xFFFFU) +#define ESAI_TSMB_TS_SHIFT (0U) +#define ESAI_TSMB_TS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TSMB_TS_SHIFT)) & ESAI_TSMB_TS_MASK) + +/*! @name RSMA - Receive Slot Mask Register A */ +#define ESAI_RSMA_RS_MASK (0xFFFFU) +#define ESAI_RSMA_RS_SHIFT (0U) +#define ESAI_RSMA_RS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RSMA_RS_SHIFT)) & ESAI_RSMA_RS_MASK) + +/*! @name RSMB - Receive Slot Mask Register B */ +#define ESAI_RSMB_RS_MASK (0xFFFFU) +#define ESAI_RSMB_RS_SHIFT (0U) +#define ESAI_RSMB_RS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RSMB_RS_SHIFT)) & ESAI_RSMB_RS_MASK) + +/*! @name PRRC - Port C Direction Register */ +#define ESAI_PRRC_PDC_MASK (0xFFFU) +#define ESAI_PRRC_PDC_SHIFT (0U) +#define ESAI_PRRC_PDC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_PRRC_PDC_SHIFT)) & ESAI_PRRC_PDC_MASK) + +/*! @name PCRC - Port C Control Register */ +#define ESAI_PCRC_PC_MASK (0xFFFU) +#define ESAI_PCRC_PC_SHIFT (0U) +#define ESAI_PCRC_PC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_PCRC_PC_SHIFT)) & ESAI_PCRC_PC_MASK) + + +/*! + * @} + */ /* end of group ESAI_Register_Masks */ + + +/* ESAI - Peripheral instance base addresses */ +/** Peripheral ESAI base address */ +#define ESAI_BASE (0x2024000u) +/** Peripheral ESAI base pointer */ +#define ESAI ((ESAI_Type *)ESAI_BASE) +/** Array initializer of ESAI peripheral base addresses */ +#define ESAI_BASE_ADDRS { ESAI_BASE } +/** Array initializer of ESAI peripheral base pointers */ +#define ESAI_BASE_PTRS { ESAI } +/** Interrupt vectors for the ESAI peripheral type */ +#define ESAI_IRQS { ESAI_IRQn } + +/*! + * @} + */ /* end of group ESAI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer + * @{ + */ + +/** GPC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CNTR; /**< GPC Interface control register, offset: 0x0 */ + __IO uint32_t PGR; /**< GPC Power Gating Register, offset: 0x4 */ + __IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register 4, array offset: 0x8, array step: 0x4 */ + __I uint32_t ISR[4]; /**< IRQ status resister 1..IRQ status resister 4, array offset: 0x18, array step: 0x4 */ +} GPC_Type; + +/* ---------------------------------------------------------------------------- + -- GPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Register_Masks GPC Register Masks + * @{ + */ + +/*! @name CNTR - GPC Interface control register */ +#define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U) +#define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U) +#define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK) +#define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U) +#define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U) +#define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK) +#define GPC_CNTR_DISPLAY_PDN_REQ_MASK (0x10U) +#define GPC_CNTR_DISPLAY_PDN_REQ_SHIFT (4U) +#define GPC_CNTR_DISPLAY_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_DISPLAY_PDN_REQ_SHIFT)) & GPC_CNTR_DISPLAY_PDN_REQ_MASK) +#define GPC_CNTR_DISPLAY_PUP_REQ_MASK (0x20U) +#define GPC_CNTR_DISPLAY_PUP_REQ_SHIFT (5U) +#define GPC_CNTR_DISPLAY_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_DISPLAY_PUP_REQ_SHIFT)) & GPC_CNTR_DISPLAY_PUP_REQ_MASK) +#define GPC_CNTR_VADC_ANALOG_OFF_MASK (0x20000U) +#define GPC_CNTR_VADC_ANALOG_OFF_SHIFT (17U) +#define GPC_CNTR_VADC_ANALOG_OFF(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_VADC_ANALOG_OFF_SHIFT)) & GPC_CNTR_VADC_ANALOG_OFF_MASK) +#define GPC_CNTR_VADC_EXT_PWD_N_MASK (0x40000U) +#define GPC_CNTR_VADC_EXT_PWD_N_SHIFT (18U) +#define GPC_CNTR_VADC_EXT_PWD_N(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_VADC_EXT_PWD_N_SHIFT)) & GPC_CNTR_VADC_EXT_PWD_N_MASK) +#define GPC_CNTR_GPCIRQM_MASK (0x200000U) +#define GPC_CNTR_GPCIRQM_SHIFT (21U) +#define GPC_CNTR_GPCIRQM(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_GPCIRQM_SHIFT)) & GPC_CNTR_GPCIRQM_MASK) +#define GPC_CNTR_L2_PGE_MASK (0x400000U) +#define GPC_CNTR_L2_PGE_SHIFT (22U) +#define GPC_CNTR_L2_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_L2_PGE_SHIFT)) & GPC_CNTR_L2_PGE_MASK) + +/*! @name PGR - GPC Power Gating Register */ +#define GPC_PGR_DRCIC_MASK (0x60000000U) +#define GPC_PGR_DRCIC_SHIFT (29U) +#define GPC_PGR_DRCIC(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGR_DRCIC_SHIFT)) & GPC_PGR_DRCIC_MASK) + +/*! @name IMR - IRQ masking register 1..IRQ masking register 4 */ +#define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR1_SHIFT (0U) +#define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK) +#define GPC_IMR_IMR2_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR2_SHIFT (0U) +#define GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK) +#define GPC_IMR_IMR3_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR3_SHIFT (0U) +#define GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK) +#define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR4_SHIFT (0U) +#define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK) + +/* The count of GPC_IMR */ +#define GPC_IMR_COUNT (4U) + +/*! @name ISR - IRQ status resister 1..IRQ status resister 4 */ +#define GPC_ISR_ISR1_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR1_SHIFT (0U) +#define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK) +#define GPC_ISR_ISR2_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR2_SHIFT (0U) +#define GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK) +#define GPC_ISR_ISR3_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR3_SHIFT (0U) +#define GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK) +#define GPC_ISR_ISR4_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR4_SHIFT (0U) +#define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK) + +/* The count of GPC_ISR */ +#define GPC_ISR_COUNT (4U) + + +/*! + * @} + */ /* end of group GPC_Register_Masks */ + + +/* GPC - Peripheral instance base addresses */ +/** Peripheral GPC base address */ +#define GPC_BASE (0x20DC000u) +/** Peripheral GPC base pointer */ +#define GPC ((GPC_Type *)GPC_BASE) +/** Array initializer of GPC peripheral base addresses */ +#define GPC_BASE_ADDRS { GPC_BASE } +/** Array initializer of GPC peripheral base pointers */ +#define GPC_BASE_PTRS { GPC } +/** Interrupt vectors for the GPC peripheral type */ +#define GPC_IRQS { GPC_IRQn } + +/*! + * @} + */ /* end of group GPC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ + __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */ + __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */ + __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */ + __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */ + __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ + __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ + __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name DR - GPIO data register */ +#define GPIO_DR_DR_MASK (0xFFFFFFFFU) +#define GPIO_DR_DR_SHIFT (0U) +#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) + +/*! @name GDIR - GPIO direction register */ +#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) +#define GPIO_GDIR_GDIR_SHIFT (0U) +#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) + +/*! @name PSR - GPIO pad status register */ +#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) +#define GPIO_PSR_PSR_SHIFT (0U) +#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) + +/*! @name ICR1 - GPIO interrupt configuration register1 */ +#define GPIO_ICR1_ICR0_MASK (0x3U) +#define GPIO_ICR1_ICR0_SHIFT (0U) +#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) +#define GPIO_ICR1_ICR1_MASK (0xCU) +#define GPIO_ICR1_ICR1_SHIFT (2U) +#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) +#define GPIO_ICR1_ICR2_MASK (0x30U) +#define GPIO_ICR1_ICR2_SHIFT (4U) +#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) +#define GPIO_ICR1_ICR3_MASK (0xC0U) +#define GPIO_ICR1_ICR3_SHIFT (6U) +#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) +#define GPIO_ICR1_ICR4_MASK (0x300U) +#define GPIO_ICR1_ICR4_SHIFT (8U) +#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) +#define GPIO_ICR1_ICR5_MASK (0xC00U) +#define GPIO_ICR1_ICR5_SHIFT (10U) +#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) +#define GPIO_ICR1_ICR6_MASK (0x3000U) +#define GPIO_ICR1_ICR6_SHIFT (12U) +#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) +#define GPIO_ICR1_ICR7_MASK (0xC000U) +#define GPIO_ICR1_ICR7_SHIFT (14U) +#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) +#define GPIO_ICR1_ICR8_MASK (0x30000U) +#define GPIO_ICR1_ICR8_SHIFT (16U) +#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) +#define GPIO_ICR1_ICR9_MASK (0xC0000U) +#define GPIO_ICR1_ICR9_SHIFT (18U) +#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) +#define GPIO_ICR1_ICR10_MASK (0x300000U) +#define GPIO_ICR1_ICR10_SHIFT (20U) +#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) +#define GPIO_ICR1_ICR11_MASK (0xC00000U) +#define GPIO_ICR1_ICR11_SHIFT (22U) +#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) +#define GPIO_ICR1_ICR12_MASK (0x3000000U) +#define GPIO_ICR1_ICR12_SHIFT (24U) +#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) +#define GPIO_ICR1_ICR13_MASK (0xC000000U) +#define GPIO_ICR1_ICR13_SHIFT (26U) +#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) +#define GPIO_ICR1_ICR14_MASK (0x30000000U) +#define GPIO_ICR1_ICR14_SHIFT (28U) +#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) +#define GPIO_ICR1_ICR15_MASK (0xC0000000U) +#define GPIO_ICR1_ICR15_SHIFT (30U) +#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) + +/*! @name ICR2 - GPIO interrupt configuration register2 */ +#define GPIO_ICR2_ICR16_MASK (0x3U) +#define GPIO_ICR2_ICR16_SHIFT (0U) +#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) +#define GPIO_ICR2_ICR17_MASK (0xCU) +#define GPIO_ICR2_ICR17_SHIFT (2U) +#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) +#define GPIO_ICR2_ICR18_MASK (0x30U) +#define GPIO_ICR2_ICR18_SHIFT (4U) +#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) +#define GPIO_ICR2_ICR19_MASK (0xC0U) +#define GPIO_ICR2_ICR19_SHIFT (6U) +#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) +#define GPIO_ICR2_ICR20_MASK (0x300U) +#define GPIO_ICR2_ICR20_SHIFT (8U) +#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) +#define GPIO_ICR2_ICR21_MASK (0xC00U) +#define GPIO_ICR2_ICR21_SHIFT (10U) +#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) +#define GPIO_ICR2_ICR22_MASK (0x3000U) +#define GPIO_ICR2_ICR22_SHIFT (12U) +#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) +#define GPIO_ICR2_ICR23_MASK (0xC000U) +#define GPIO_ICR2_ICR23_SHIFT (14U) +#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) +#define GPIO_ICR2_ICR24_MASK (0x30000U) +#define GPIO_ICR2_ICR24_SHIFT (16U) +#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) +#define GPIO_ICR2_ICR25_MASK (0xC0000U) +#define GPIO_ICR2_ICR25_SHIFT (18U) +#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) +#define GPIO_ICR2_ICR26_MASK (0x300000U) +#define GPIO_ICR2_ICR26_SHIFT (20U) +#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) +#define GPIO_ICR2_ICR27_MASK (0xC00000U) +#define GPIO_ICR2_ICR27_SHIFT (22U) +#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) +#define GPIO_ICR2_ICR28_MASK (0x3000000U) +#define GPIO_ICR2_ICR28_SHIFT (24U) +#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) +#define GPIO_ICR2_ICR29_MASK (0xC000000U) +#define GPIO_ICR2_ICR29_SHIFT (26U) +#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) +#define GPIO_ICR2_ICR30_MASK (0x30000000U) +#define GPIO_ICR2_ICR30_SHIFT (28U) +#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) +#define GPIO_ICR2_ICR31_MASK (0xC0000000U) +#define GPIO_ICR2_ICR31_SHIFT (30U) +#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) + +/*! @name IMR - GPIO interrupt mask register */ +#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) +#define GPIO_IMR_IMR_SHIFT (0U) +#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) + +/*! @name ISR - GPIO interrupt status register */ +#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) +#define GPIO_ISR_ISR_SHIFT (0U) +#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) + +/*! @name EDGE_SEL - GPIO edge select register */ +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x209C000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x20A0000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x20A4000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x20A8000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Peripheral GPIO5 base address */ +#define GPIO5_BASE (0x20AC000u) +/** Peripheral GPIO5 base pointer */ +#define GPIO5 ((GPIO_Type *)GPIO5_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } +#define GPIO_COMBINED_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_0_15_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_0_15_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_0_15_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_0_15_IRQn, GPIO5_Combined_16_31_IRQn } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPMI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer + * @{ + */ + +/** GPMI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< GPMI Control Register 0 Description, offset: 0x0 */ + __IO uint32_t CTRL0_SET; /**< GPMI Control Register 0 Description, offset: 0x4 */ + __IO uint32_t CTRL0_CLR; /**< GPMI Control Register 0 Description, offset: 0x8 */ + __IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset: 0xC */ + __IO uint32_t COMPARE; /**< GPMI Compare Register Description, offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t ECCCTRL; /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */ + __IO uint32_t ECCCTRL_SET; /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */ + __IO uint32_t ECCCTRL_CLR; /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */ + __IO uint32_t ECCCTRL_TOG; /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */ + __IO uint32_t ECCCOUNT; /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PAYLOAD; /**< GPMI Payload Address Register Description, offset: 0x40 */ + uint8_t RESERVED_2[12]; + __IO uint32_t AUXILIARY; /**< GPMI Auxiliary Address Register Description, offset: 0x50 */ + uint8_t RESERVED_3[12]; + __IO uint32_t CTRL1; /**< GPMI Control Register 1 Description, offset: 0x60 */ + __IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset: 0x64 */ + __IO uint32_t CTRL1_CLR; /**< GPMI Control Register 1 Description, offset: 0x68 */ + __IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset: 0x6C */ + __IO uint32_t TIMING0; /**< GPMI Timing Register 0 Description, offset: 0x70 */ + uint8_t RESERVED_4[12]; + __IO uint32_t TIMING1; /**< GPMI Timing Register 1 Description, offset: 0x80 */ + uint8_t RESERVED_5[12]; + __IO uint32_t TIMING2; /**< GPMI Timing Register 2 Description, offset: 0x90 */ + uint8_t RESERVED_6[12]; + __IO uint32_t DATA; /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */ + uint8_t RESERVED_7[12]; + __I uint32_t STAT; /**< GPMI Status Register Description, offset: 0xB0 */ + uint8_t RESERVED_8[12]; + __I uint32_t DEBUGr; /**< GPMI Debug Information Register Description, offset: 0xC0 */ + uint8_t RESERVED_9[12]; + __I uint32_t VERSION; /**< GPMI Version Register Description, offset: 0xD0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t DEBUG2; /**< GPMI Debug2 Information Register Description, offset: 0xE0 */ + uint8_t RESERVED_11[12]; + __I uint32_t DEBUG3; /**< GPMI Debug3 Information Register Description, offset: 0xF0 */ + uint8_t RESERVED_12[12]; + __IO uint32_t READ_DDR_DLL_CTRL; /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */ + uint8_t RESERVED_13[12]; + __IO uint32_t WRITE_DDR_DLL_CTRL; /**< GPMI Double Rate Write DLL Control Register Description, offset: 0x110 */ + uint8_t RESERVED_14[12]; + __I uint32_t READ_DDR_DLL_STS; /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */ + uint8_t RESERVED_15[12]; + __I uint32_t WRITE_DDR_DLL_STS; /**< GPMI Double Rate Write DLL Status Register Description, offset: 0x130 */ +} GPMI_Type; + +/* ---------------------------------------------------------------------------- + -- GPMI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPMI_Register_Masks GPMI Register Masks + * @{ + */ + +/*! @name CTRL0 - GPMI Control Register 0 Description */ +#define GPMI_CTRL0_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_XFER_COUNT_SHIFT)) & GPMI_CTRL0_XFER_COUNT_MASK) +#define GPMI_CTRL0_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT (16U) +#define GPMI_CTRL0_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_ADDRESS_INCREMENT_MASK) +#define GPMI_CTRL0_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_SHIFT)) & GPMI_CTRL0_ADDRESS_MASK) +#define GPMI_CTRL0_CS_MASK (0x700000U) +#define GPMI_CTRL0_CS_SHIFT (20U) +#define GPMI_CTRL0_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CS_SHIFT)) & GPMI_CTRL0_CS_MASK) +#define GPMI_CTRL0_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_WORD_LENGTH_SHIFT (23U) +#define GPMI_CTRL0_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_WORD_LENGTH_MASK) +#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_COMMAND_MODE_SHIFT (24U) +#define GPMI_CTRL0_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_COMMAND_MODE_MASK) +#define GPMI_CTRL0_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_UDMA_SHIFT (26U) +#define GPMI_CTRL0_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_UDMA_SHIFT)) & GPMI_CTRL0_UDMA_MASK) +#define GPMI_CTRL0_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_LOCK_CS_SHIFT)) & GPMI_CTRL0_LOCK_CS_MASK) +#define GPMI_CTRL0_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_DEV_IRQ_EN_MASK) +#define GPMI_CTRL0_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_RUN_SHIFT (29U) +#define GPMI_CTRL0_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_RUN_SHIFT)) & GPMI_CTRL0_RUN_MASK) +#define GPMI_CTRL0_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLKGATE_SHIFT)) & GPMI_CTRL0_CLKGATE_MASK) +#define GPMI_CTRL0_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SFTRST_SHIFT)) & GPMI_CTRL0_SFTRST_MASK) + +/*! @name CTRL0_SET - GPMI Control Register 0 Description */ +#define GPMI_CTRL0_SET_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_SET_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_SET_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_XFER_COUNT_SHIFT)) & GPMI_CTRL0_SET_XFER_COUNT_MASK) +#define GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT (16U) +#define GPMI_CTRL0_SET_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK) +#define GPMI_CTRL0_SET_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_SET_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_SET_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_MASK) +#define GPMI_CTRL0_SET_CS_MASK (0x700000U) +#define GPMI_CTRL0_SET_CS_SHIFT (20U) +#define GPMI_CTRL0_SET_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CS_SHIFT)) & GPMI_CTRL0_SET_CS_MASK) +#define GPMI_CTRL0_SET_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_SET_WORD_LENGTH_SHIFT (23U) +#define GPMI_CTRL0_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_SET_WORD_LENGTH_MASK) +#define GPMI_CTRL0_SET_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_SET_COMMAND_MODE_SHIFT (24U) +#define GPMI_CTRL0_SET_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_SET_COMMAND_MODE_MASK) +#define GPMI_CTRL0_SET_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_SET_UDMA_SHIFT (26U) +#define GPMI_CTRL0_SET_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_UDMA_SHIFT)) & GPMI_CTRL0_SET_UDMA_MASK) +#define GPMI_CTRL0_SET_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_SET_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_SET_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_LOCK_CS_SHIFT)) & GPMI_CTRL0_SET_LOCK_CS_MASK) +#define GPMI_CTRL0_SET_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_SET_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_SET_DEV_IRQ_EN_MASK) +#define GPMI_CTRL0_SET_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_SET_RUN_SHIFT (29U) +#define GPMI_CTRL0_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_RUN_SHIFT)) & GPMI_CTRL0_SET_RUN_MASK) +#define GPMI_CTRL0_SET_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_SET_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CLKGATE_SHIFT)) & GPMI_CTRL0_SET_CLKGATE_MASK) +#define GPMI_CTRL0_SET_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_SET_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_SFTRST_SHIFT)) & GPMI_CTRL0_SET_SFTRST_MASK) + +/*! @name CTRL0_CLR - GPMI Control Register 0 Description */ +#define GPMI_CTRL0_CLR_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_CLR_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_CLR_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_XFER_COUNT_SHIFT)) & GPMI_CTRL0_CLR_XFER_COUNT_MASK) +#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT (16U) +#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK) +#define GPMI_CTRL0_CLR_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_CLR_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_CLR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_MASK) +#define GPMI_CTRL0_CLR_CS_MASK (0x700000U) +#define GPMI_CTRL0_CLR_CS_SHIFT (20U) +#define GPMI_CTRL0_CLR_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CS_SHIFT)) & GPMI_CTRL0_CLR_CS_MASK) +#define GPMI_CTRL0_CLR_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT (23U) +#define GPMI_CTRL0_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_CLR_WORD_LENGTH_MASK) +#define GPMI_CTRL0_CLR_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT (24U) +#define GPMI_CTRL0_CLR_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_CLR_COMMAND_MODE_MASK) +#define GPMI_CTRL0_CLR_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_CLR_UDMA_SHIFT (26U) +#define GPMI_CTRL0_CLR_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_UDMA_SHIFT)) & GPMI_CTRL0_CLR_UDMA_MASK) +#define GPMI_CTRL0_CLR_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_CLR_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_CLR_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_LOCK_CS_SHIFT)) & GPMI_CTRL0_CLR_LOCK_CS_MASK) +#define GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_CLR_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK) +#define GPMI_CTRL0_CLR_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_CLR_RUN_SHIFT (29U) +#define GPMI_CTRL0_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_RUN_SHIFT)) & GPMI_CTRL0_CLR_RUN_MASK) +#define GPMI_CTRL0_CLR_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_CLR_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CLKGATE_SHIFT)) & GPMI_CTRL0_CLR_CLKGATE_MASK) +#define GPMI_CTRL0_CLR_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_CLR_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_SFTRST_SHIFT)) & GPMI_CTRL0_CLR_SFTRST_MASK) + +/*! @name CTRL0_TOG - GPMI Control Register 0 Description */ +#define GPMI_CTRL0_TOG_XFER_COUNT_MASK (0xFFFFU) +#define GPMI_CTRL0_TOG_XFER_COUNT_SHIFT (0U) +#define GPMI_CTRL0_TOG_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_XFER_COUNT_SHIFT)) & GPMI_CTRL0_TOG_XFER_COUNT_MASK) +#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK (0x10000U) +#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT (16U) +#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK) +#define GPMI_CTRL0_TOG_ADDRESS_MASK (0xE0000U) +#define GPMI_CTRL0_TOG_ADDRESS_SHIFT (17U) +#define GPMI_CTRL0_TOG_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_MASK) +#define GPMI_CTRL0_TOG_CS_MASK (0x700000U) +#define GPMI_CTRL0_TOG_CS_SHIFT (20U) +#define GPMI_CTRL0_TOG_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CS_SHIFT)) & GPMI_CTRL0_TOG_CS_MASK) +#define GPMI_CTRL0_TOG_WORD_LENGTH_MASK (0x800000U) +#define GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT (23U) +#define GPMI_CTRL0_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_TOG_WORD_LENGTH_MASK) +#define GPMI_CTRL0_TOG_COMMAND_MODE_MASK (0x3000000U) +#define GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT (24U) +#define GPMI_CTRL0_TOG_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_TOG_COMMAND_MODE_MASK) +#define GPMI_CTRL0_TOG_UDMA_MASK (0x4000000U) +#define GPMI_CTRL0_TOG_UDMA_SHIFT (26U) +#define GPMI_CTRL0_TOG_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_UDMA_SHIFT)) & GPMI_CTRL0_TOG_UDMA_MASK) +#define GPMI_CTRL0_TOG_LOCK_CS_MASK (0x8000000U) +#define GPMI_CTRL0_TOG_LOCK_CS_SHIFT (27U) +#define GPMI_CTRL0_TOG_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_LOCK_CS_SHIFT)) & GPMI_CTRL0_TOG_LOCK_CS_MASK) +#define GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK (0x10000000U) +#define GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT (28U) +#define GPMI_CTRL0_TOG_DEV_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK) +#define GPMI_CTRL0_TOG_RUN_MASK (0x20000000U) +#define GPMI_CTRL0_TOG_RUN_SHIFT (29U) +#define GPMI_CTRL0_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_RUN_SHIFT)) & GPMI_CTRL0_TOG_RUN_MASK) +#define GPMI_CTRL0_TOG_CLKGATE_MASK (0x40000000U) +#define GPMI_CTRL0_TOG_CLKGATE_SHIFT (30U) +#define GPMI_CTRL0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CLKGATE_SHIFT)) & GPMI_CTRL0_TOG_CLKGATE_MASK) +#define GPMI_CTRL0_TOG_SFTRST_MASK (0x80000000U) +#define GPMI_CTRL0_TOG_SFTRST_SHIFT (31U) +#define GPMI_CTRL0_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_SFTRST_SHIFT)) & GPMI_CTRL0_TOG_SFTRST_MASK) + +/*! @name COMPARE - GPMI Compare Register Description */ +#define GPMI_COMPARE_REFERENCE_MASK (0xFFFFU) +#define GPMI_COMPARE_REFERENCE_SHIFT (0U) +#define GPMI_COMPARE_REFERENCE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_REFERENCE_SHIFT)) & GPMI_COMPARE_REFERENCE_MASK) +#define GPMI_COMPARE_MASK_MASK (0xFFFF0000U) +#define GPMI_COMPARE_MASK_SHIFT (16U) +#define GPMI_COMPARE_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_MASK_SHIFT)) & GPMI_COMPARE_MASK_MASK) + +/*! @name ECCCTRL - GPMI Integrated ECC Control Register Description */ +#define GPMI_ECCCTRL_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_RSVD1_MASK (0xE00U) +#define GPMI_ECCCTRL_RSVD1_SHIFT (9U) +#define GPMI_ECCCTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD1_SHIFT)) & GPMI_ECCCTRL_RSVD1_MASK) +#define GPMI_ECCCTRL_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_ENABLE_ECC_MASK) +#define GPMI_ECCCTRL_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_ECC_CMD_MASK) +#define GPMI_ECCCTRL_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD2_SHIFT)) & GPMI_ECCCTRL_RSVD2_MASK) +#define GPMI_ECCCTRL_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_HANDLE_SHIFT)) & GPMI_ECCCTRL_HANDLE_MASK) + +/*! @name ECCCTRL_SET - GPMI Integrated ECC Control Register Description */ +#define GPMI_ECCCTRL_SET_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_SET_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_SET_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_SET_RSVD1_MASK (0xE00U) +#define GPMI_ECCCTRL_SET_RSVD1_SHIFT (9U) +#define GPMI_ECCCTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RSVD1_SHIFT)) & GPMI_ECCCTRL_SET_RSVD1_MASK) +#define GPMI_ECCCTRL_SET_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_SET_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_SET_ENABLE_ECC_MASK) +#define GPMI_ECCCTRL_SET_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_SET_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_SET_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_SET_ECC_CMD_MASK) +#define GPMI_ECCCTRL_SET_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_SET_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RSVD2_SHIFT)) & GPMI_ECCCTRL_SET_RSVD2_MASK) +#define GPMI_ECCCTRL_SET_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_SET_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_SET_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_HANDLE_SHIFT)) & GPMI_ECCCTRL_SET_HANDLE_MASK) + +/*! @name ECCCTRL_CLR - GPMI Integrated ECC Control Register Description */ +#define GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_CLR_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_CLR_RSVD1_MASK (0xE00U) +#define GPMI_ECCCTRL_CLR_RSVD1_SHIFT (9U) +#define GPMI_ECCCTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RSVD1_SHIFT)) & GPMI_ECCCTRL_CLR_RSVD1_MASK) +#define GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_CLR_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK) +#define GPMI_ECCCTRL_CLR_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_CLR_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_CLR_ECC_CMD_MASK) +#define GPMI_ECCCTRL_CLR_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_CLR_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RSVD2_SHIFT)) & GPMI_ECCCTRL_CLR_RSVD2_MASK) +#define GPMI_ECCCTRL_CLR_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_CLR_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_CLR_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_HANDLE_SHIFT)) & GPMI_ECCCTRL_CLR_HANDLE_MASK) + +/*! @name ECCCTRL_TOG - GPMI Integrated ECC Control Register Description */ +#define GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK (0x1FFU) +#define GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT (0U) +#define GPMI_ECCCTRL_TOG_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK) +#define GPMI_ECCCTRL_TOG_RSVD1_MASK (0xE00U) +#define GPMI_ECCCTRL_TOG_RSVD1_SHIFT (9U) +#define GPMI_ECCCTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RSVD1_SHIFT)) & GPMI_ECCCTRL_TOG_RSVD1_MASK) +#define GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK (0x1000U) +#define GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT (12U) +#define GPMI_ECCCTRL_TOG_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK) +#define GPMI_ECCCTRL_TOG_ECC_CMD_MASK (0x6000U) +#define GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT (13U) +#define GPMI_ECCCTRL_TOG_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_TOG_ECC_CMD_MASK) +#define GPMI_ECCCTRL_TOG_RSVD2_MASK (0x8000U) +#define GPMI_ECCCTRL_TOG_RSVD2_SHIFT (15U) +#define GPMI_ECCCTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RSVD2_SHIFT)) & GPMI_ECCCTRL_TOG_RSVD2_MASK) +#define GPMI_ECCCTRL_TOG_HANDLE_MASK (0xFFFF0000U) +#define GPMI_ECCCTRL_TOG_HANDLE_SHIFT (16U) +#define GPMI_ECCCTRL_TOG_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_HANDLE_SHIFT)) & GPMI_ECCCTRL_TOG_HANDLE_MASK) + +/*! @name ECCCOUNT - GPMI Integrated ECC Transfer Count Register Description */ +#define GPMI_ECCCOUNT_COUNT_MASK (0xFFFFU) +#define GPMI_ECCCOUNT_COUNT_SHIFT (0U) +#define GPMI_ECCCOUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_COUNT_SHIFT)) & GPMI_ECCCOUNT_COUNT_MASK) +#define GPMI_ECCCOUNT_RSVD2_MASK (0xFFFF0000U) +#define GPMI_ECCCOUNT_RSVD2_SHIFT (16U) +#define GPMI_ECCCOUNT_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_RSVD2_SHIFT)) & GPMI_ECCCOUNT_RSVD2_MASK) + +/*! @name PAYLOAD - GPMI Payload Address Register Description */ +#define GPMI_PAYLOAD_RSVD0_MASK (0x3U) +#define GPMI_PAYLOAD_RSVD0_SHIFT (0U) +#define GPMI_PAYLOAD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_RSVD0_SHIFT)) & GPMI_PAYLOAD_RSVD0_MASK) +#define GPMI_PAYLOAD_ADDRESS_MASK (0xFFFFFFFCU) +#define GPMI_PAYLOAD_ADDRESS_SHIFT (2U) +#define GPMI_PAYLOAD_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_ADDRESS_SHIFT)) & GPMI_PAYLOAD_ADDRESS_MASK) + +/*! @name AUXILIARY - GPMI Auxiliary Address Register Description */ +#define GPMI_AUXILIARY_RSVD0_MASK (0x3U) +#define GPMI_AUXILIARY_RSVD0_SHIFT (0U) +#define GPMI_AUXILIARY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_RSVD0_SHIFT)) & GPMI_AUXILIARY_RSVD0_MASK) +#define GPMI_AUXILIARY_ADDRESS_MASK (0xFFFFFFFCU) +#define GPMI_AUXILIARY_ADDRESS_SHIFT (2U) +#define GPMI_AUXILIARY_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_ADDRESS_SHIFT)) & GPMI_AUXILIARY_ADDRESS_MASK) + +/*! @name CTRL1 - GPMI Control Register 1 Description */ +#define GPMI_CTRL1_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_GPMI_MODE_SHIFT (0U) +#define GPMI_CTRL1_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_MODE_SHIFT)) & GPMI_CTRL1_GPMI_MODE_MASK) +#define GPMI_CTRL1_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CAMERA_MODE_MASK) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT (2U) +#define GPMI_CTRL1_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK) +#define GPMI_CTRL1_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_DEV_RESET_SHIFT (3U) +#define GPMI_CTRL1_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_RESET_SHIFT)) & GPMI_CTRL1_DEV_RESET_MASK) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK) +#define GPMI_CTRL1_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BURST_EN_SHIFT)) & GPMI_CTRL1_BURST_EN_MASK) +#define GPMI_CTRL1_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_MASK) +#define GPMI_CTRL1_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_IRQ_SHIFT)) & GPMI_CTRL1_DEV_IRQ_MASK) +#define GPMI_CTRL1_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_DMA2ECC_MODE_MASK) +#define GPMI_CTRL1_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RDN_DELAY_SHIFT)) & GPMI_CTRL1_RDN_DELAY_MASK) +#define GPMI_CTRL1_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_HALF_PERIOD_MASK) +#define GPMI_CTRL1_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_DLL_ENABLE_MASK) +#define GPMI_CTRL1_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BCH_MODE_SHIFT)) & GPMI_CTRL1_BCH_MODE_MASK) +#define GPMI_CTRL1_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_GANGED_RDYBUSY_MASK) +#define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK) +#define GPMI_CTRL1_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_TEST_TRIGGER_SHIFT (21U) +#define GPMI_CTRL1_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TEST_TRIGGER_MASK) +#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_DECOUPLE_CS_MASK) +#define GPMI_CTRL1_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SSYNCMODE_MASK) +#define GPMI_CTRL1_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_UPDATE_CS_SHIFT)) & GPMI_CTRL1_UPDATE_CS_MASK) +#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT (27U) +#define GPMI_CTRL1_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK) +#define GPMI_CTRL1_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOGGLE_MODE_MASK) +#define GPMI_CTRL1_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_WRITE_CLK_STOP_MASK) +#define GPMI_CTRL1_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SSYNC_CLK_STOP_MASK) +#define GPMI_CTRL1_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_DEV_CLK_STOP_MASK) + +/*! @name CTRL1_SET - GPMI Control Register 1 Description */ +#define GPMI_CTRL1_SET_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_SET_GPMI_MODE_SHIFT (0U) +#define GPMI_CTRL1_SET_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_MODE_SHIFT)) & GPMI_CTRL1_SET_GPMI_MODE_MASK) +#define GPMI_CTRL1_SET_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_SET_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_SET_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_SET_CAMERA_MODE_MASK) +#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT (2U) +#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK) +#define GPMI_CTRL1_SET_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_SET_DEV_RESET_SHIFT (3U) +#define GPMI_CTRL1_SET_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_RESET_SHIFT)) & GPMI_CTRL1_SET_DEV_RESET_MASK) +#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK) +#define GPMI_CTRL1_SET_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_SET_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_SET_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BURST_EN_SHIFT)) & GPMI_CTRL1_SET_BURST_EN_MASK) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK) +#define GPMI_CTRL1_SET_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_SET_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_SET_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_IRQ_SHIFT)) & GPMI_CTRL1_SET_DEV_IRQ_MASK) +#define GPMI_CTRL1_SET_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_SET_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_SET_DMA2ECC_MODE_MASK) +#define GPMI_CTRL1_SET_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_SET_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_SET_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_RDN_DELAY_SHIFT)) & GPMI_CTRL1_SET_RDN_DELAY_MASK) +#define GPMI_CTRL1_SET_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_SET_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_SET_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_SET_HALF_PERIOD_MASK) +#define GPMI_CTRL1_SET_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_SET_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_SET_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_SET_DLL_ENABLE_MASK) +#define GPMI_CTRL1_SET_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_SET_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_SET_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BCH_MODE_SHIFT)) & GPMI_CTRL1_SET_BCH_MODE_MASK) +#define GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_SET_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK) +#define GPMI_CTRL1_SET_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT (21U) +#define GPMI_CTRL1_SET_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_SET_TEST_TRIGGER_MASK) +#define GPMI_CTRL1_SET_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_SET_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_SET_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_SET_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_SET_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_SET_DECOUPLE_CS_MASK) +#define GPMI_CTRL1_SET_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_SET_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_SET_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SET_SSYNCMODE_MASK) +#define GPMI_CTRL1_SET_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_SET_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_SET_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_UPDATE_CS_SHIFT)) & GPMI_CTRL1_SET_UPDATE_CS_MASK) +#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT (27U) +#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK) +#define GPMI_CTRL1_SET_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_SET_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_SET_TOGGLE_MODE_MASK) +#define GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_SET_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK) +#define GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_SET_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK) +#define GPMI_CTRL1_SET_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_SET_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_DEV_CLK_STOP_MASK) + +/*! @name CTRL1_CLR - GPMI Control Register 1 Description */ +#define GPMI_CTRL1_CLR_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_CLR_GPMI_MODE_SHIFT (0U) +#define GPMI_CTRL1_CLR_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_MODE_SHIFT)) & GPMI_CTRL1_CLR_GPMI_MODE_MASK) +#define GPMI_CTRL1_CLR_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_CLR_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CLR_CAMERA_MODE_MASK) +#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT (2U) +#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK) +#define GPMI_CTRL1_CLR_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_CLR_DEV_RESET_SHIFT (3U) +#define GPMI_CTRL1_CLR_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_RESET_SHIFT)) & GPMI_CTRL1_CLR_DEV_RESET_MASK) +#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK) +#define GPMI_CTRL1_CLR_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_CLR_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_CLR_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BURST_EN_SHIFT)) & GPMI_CTRL1_CLR_BURST_EN_MASK) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK) +#define GPMI_CTRL1_CLR_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_CLR_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_CLR_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_IRQ_SHIFT)) & GPMI_CTRL1_CLR_DEV_IRQ_MASK) +#define GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_CLR_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK) +#define GPMI_CTRL1_CLR_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_CLR_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_CLR_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_RDN_DELAY_SHIFT)) & GPMI_CTRL1_CLR_RDN_DELAY_MASK) +#define GPMI_CTRL1_CLR_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_CLR_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_CLR_HALF_PERIOD_MASK) +#define GPMI_CTRL1_CLR_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_CLR_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_CLR_DLL_ENABLE_MASK) +#define GPMI_CTRL1_CLR_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_CLR_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_CLR_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BCH_MODE_SHIFT)) & GPMI_CTRL1_CLR_BCH_MODE_MASK) +#define GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_CLR_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK) +#define GPMI_CTRL1_CLR_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT (21U) +#define GPMI_CTRL1_CLR_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_CLR_TEST_TRIGGER_MASK) +#define GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_CLR_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_CLR_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_CLR_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_CLR_DECOUPLE_CS_MASK) +#define GPMI_CTRL1_CLR_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_CLR_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_CLR_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNCMODE_SHIFT)) & GPMI_CTRL1_CLR_SSYNCMODE_MASK) +#define GPMI_CTRL1_CLR_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_CLR_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_CLR_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_UPDATE_CS_SHIFT)) & GPMI_CTRL1_CLR_UPDATE_CS_MASK) +#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT (27U) +#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK) +#define GPMI_CTRL1_CLR_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_CLR_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_CLR_TOGGLE_MODE_MASK) +#define GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_CLR_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK) +#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK) +#define GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_CLR_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK) + +/*! @name CTRL1_TOG - GPMI Control Register 1 Description */ +#define GPMI_CTRL1_TOG_GPMI_MODE_MASK (0x1U) +#define GPMI_CTRL1_TOG_GPMI_MODE_SHIFT (0U) +#define GPMI_CTRL1_TOG_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_MODE_SHIFT)) & GPMI_CTRL1_TOG_GPMI_MODE_MASK) +#define GPMI_CTRL1_TOG_CAMERA_MODE_MASK (0x2U) +#define GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT (1U) +#define GPMI_CTRL1_TOG_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_TOG_CAMERA_MODE_MASK) +#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK (0x4U) +#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT (2U) +#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK) +#define GPMI_CTRL1_TOG_DEV_RESET_MASK (0x8U) +#define GPMI_CTRL1_TOG_DEV_RESET_SHIFT (3U) +#define GPMI_CTRL1_TOG_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_RESET_SHIFT)) & GPMI_CTRL1_TOG_DEV_RESET_MASK) +#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK) +#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK (0x80U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT (7U) +#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK) +#define GPMI_CTRL1_TOG_BURST_EN_MASK (0x100U) +#define GPMI_CTRL1_TOG_BURST_EN_SHIFT (8U) +#define GPMI_CTRL1_TOG_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BURST_EN_SHIFT)) & GPMI_CTRL1_TOG_BURST_EN_MASK) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK (0x200U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT (9U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK) +#define GPMI_CTRL1_TOG_DEV_IRQ_MASK (0x400U) +#define GPMI_CTRL1_TOG_DEV_IRQ_SHIFT (10U) +#define GPMI_CTRL1_TOG_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_IRQ_SHIFT)) & GPMI_CTRL1_TOG_DEV_IRQ_MASK) +#define GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK (0x800U) +#define GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT (11U) +#define GPMI_CTRL1_TOG_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK) +#define GPMI_CTRL1_TOG_RDN_DELAY_MASK (0xF000U) +#define GPMI_CTRL1_TOG_RDN_DELAY_SHIFT (12U) +#define GPMI_CTRL1_TOG_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_RDN_DELAY_SHIFT)) & GPMI_CTRL1_TOG_RDN_DELAY_MASK) +#define GPMI_CTRL1_TOG_HALF_PERIOD_MASK (0x10000U) +#define GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT (16U) +#define GPMI_CTRL1_TOG_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_TOG_HALF_PERIOD_MASK) +#define GPMI_CTRL1_TOG_DLL_ENABLE_MASK (0x20000U) +#define GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT (17U) +#define GPMI_CTRL1_TOG_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_TOG_DLL_ENABLE_MASK) +#define GPMI_CTRL1_TOG_BCH_MODE_MASK (0x40000U) +#define GPMI_CTRL1_TOG_BCH_MODE_SHIFT (18U) +#define GPMI_CTRL1_TOG_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BCH_MODE_SHIFT)) & GPMI_CTRL1_TOG_BCH_MODE_MASK) +#define GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK (0x80000U) +#define GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT (19U) +#define GPMI_CTRL1_TOG_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK (0x100000U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT (20U) +#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK) +#define GPMI_CTRL1_TOG_TEST_TRIGGER_MASK (0x200000U) +#define GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT (21U) +#define GPMI_CTRL1_TOG_TEST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TOG_TEST_TRIGGER_MASK) +#define GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK (0xC00000U) +#define GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT (22U) +#define GPMI_CTRL1_TOG_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK) +#define GPMI_CTRL1_TOG_DECOUPLE_CS_MASK (0x1000000U) +#define GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT (24U) +#define GPMI_CTRL1_TOG_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_TOG_DECOUPLE_CS_MASK) +#define GPMI_CTRL1_TOG_SSYNCMODE_MASK (0x2000000U) +#define GPMI_CTRL1_TOG_SSYNCMODE_SHIFT (25U) +#define GPMI_CTRL1_TOG_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNCMODE_SHIFT)) & GPMI_CTRL1_TOG_SSYNCMODE_MASK) +#define GPMI_CTRL1_TOG_UPDATE_CS_MASK (0x4000000U) +#define GPMI_CTRL1_TOG_UPDATE_CS_SHIFT (26U) +#define GPMI_CTRL1_TOG_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_UPDATE_CS_SHIFT)) & GPMI_CTRL1_TOG_UPDATE_CS_MASK) +#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK (0x8000000U) +#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT (27U) +#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK) +#define GPMI_CTRL1_TOG_TOGGLE_MODE_MASK (0x10000000U) +#define GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT (28U) +#define GPMI_CTRL1_TOG_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOG_TOGGLE_MODE_MASK) +#define GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK (0x20000000U) +#define GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT (29U) +#define GPMI_CTRL1_TOG_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK) +#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK (0x40000000U) +#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT (30U) +#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK) +#define GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK (0x80000000U) +#define GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT (31U) +#define GPMI_CTRL1_TOG_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK) + +/*! @name TIMING0 - GPMI Timing Register 0 Description */ +#define GPMI_TIMING0_DATA_SETUP_MASK (0xFFU) +#define GPMI_TIMING0_DATA_SETUP_SHIFT (0U) +#define GPMI_TIMING0_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_SETUP_SHIFT)) & GPMI_TIMING0_DATA_SETUP_MASK) +#define GPMI_TIMING0_DATA_HOLD_MASK (0xFF00U) +#define GPMI_TIMING0_DATA_HOLD_SHIFT (8U) +#define GPMI_TIMING0_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_HOLD_SHIFT)) & GPMI_TIMING0_DATA_HOLD_MASK) +#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xFF0000U) +#define GPMI_TIMING0_ADDRESS_SETUP_SHIFT (16U) +#define GPMI_TIMING0_ADDRESS_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_ADDRESS_SETUP_SHIFT)) & GPMI_TIMING0_ADDRESS_SETUP_MASK) +#define GPMI_TIMING0_RSVD1_MASK (0xFF000000U) +#define GPMI_TIMING0_RSVD1_SHIFT (24U) +#define GPMI_TIMING0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_RSVD1_SHIFT)) & GPMI_TIMING0_RSVD1_MASK) + +/*! @name TIMING1 - GPMI Timing Register 1 Description */ +#define GPMI_TIMING1_RSVD1_MASK (0xFFFFU) +#define GPMI_TIMING1_RSVD1_SHIFT (0U) +#define GPMI_TIMING1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_RSVD1_SHIFT)) & GPMI_TIMING1_RSVD1_MASK) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xFFFF0000U) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT (16U) +#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT)) & GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK) + +/*! @name TIMING2 - GPMI Timing Register 2 Description */ +#define GPMI_TIMING2_DATA_PAUSE_MASK (0xFU) +#define GPMI_TIMING2_DATA_PAUSE_SHIFT (0U) +#define GPMI_TIMING2_DATA_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_DATA_PAUSE_SHIFT)) & GPMI_TIMING2_DATA_PAUSE_MASK) +#define GPMI_TIMING2_CMDADD_PAUSE_MASK (0xF0U) +#define GPMI_TIMING2_CMDADD_PAUSE_SHIFT (4U) +#define GPMI_TIMING2_CMDADD_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CMDADD_PAUSE_SHIFT)) & GPMI_TIMING2_CMDADD_PAUSE_MASK) +#define GPMI_TIMING2_POSTAMBLE_DELAY_MASK (0xF00U) +#define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT (8U) +#define GPMI_TIMING2_POSTAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_POSTAMBLE_DELAY_MASK) +#define GPMI_TIMING2_PREAMBLE_DELAY_MASK (0xF000U) +#define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT (12U) +#define GPMI_TIMING2_PREAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_PREAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_PREAMBLE_DELAY_MASK) +#define GPMI_TIMING2_CE_DELAY_MASK (0x1F0000U) +#define GPMI_TIMING2_CE_DELAY_SHIFT (16U) +#define GPMI_TIMING2_CE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CE_DELAY_SHIFT)) & GPMI_TIMING2_CE_DELAY_MASK) +#define GPMI_TIMING2_RSVD0_MASK (0xE00000U) +#define GPMI_TIMING2_RSVD0_SHIFT (21U) +#define GPMI_TIMING2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_RSVD0_SHIFT)) & GPMI_TIMING2_RSVD0_MASK) +#define GPMI_TIMING2_READ_LATENCY_MASK (0x7000000U) +#define GPMI_TIMING2_READ_LATENCY_SHIFT (24U) +#define GPMI_TIMING2_READ_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_READ_LATENCY_SHIFT)) & GPMI_TIMING2_READ_LATENCY_MASK) +#define GPMI_TIMING2_TCR_MASK (0x18000000U) +#define GPMI_TIMING2_TCR_SHIFT (27U) +#define GPMI_TIMING2_TCR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TCR_SHIFT)) & GPMI_TIMING2_TCR_MASK) +#define GPMI_TIMING2_TRPSTH_MASK (0xE0000000U) +#define GPMI_TIMING2_TRPSTH_SHIFT (29U) +#define GPMI_TIMING2_TRPSTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TRPSTH_SHIFT)) & GPMI_TIMING2_TRPSTH_MASK) + +/*! @name DATA - GPMI DMA Data Transfer Register Description */ +#define GPMI_DATA_DATA_MASK (0xFFFFFFFFU) +#define GPMI_DATA_DATA_SHIFT (0U) +#define GPMI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DATA_DATA_SHIFT)) & GPMI_DATA_DATA_MASK) + +/*! @name STAT - GPMI Status Register Description */ +#define GPMI_STAT_PRESENT_MASK (0x1U) +#define GPMI_STAT_PRESENT_SHIFT (0U) +#define GPMI_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_PRESENT_SHIFT)) & GPMI_STAT_PRESENT_MASK) +#define GPMI_STAT_FIFO_FULL_MASK (0x2U) +#define GPMI_STAT_FIFO_FULL_SHIFT (1U) +#define GPMI_STAT_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_FULL_SHIFT)) & GPMI_STAT_FIFO_FULL_MASK) +#define GPMI_STAT_FIFO_EMPTY_MASK (0x4U) +#define GPMI_STAT_FIFO_EMPTY_SHIFT (2U) +#define GPMI_STAT_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_EMPTY_SHIFT)) & GPMI_STAT_FIFO_EMPTY_MASK) +#define GPMI_STAT_INVALID_BUFFER_MASK_MASK (0x8U) +#define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT (3U) +#define GPMI_STAT_INVALID_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_INVALID_BUFFER_MASK_SHIFT)) & GPMI_STAT_INVALID_BUFFER_MASK_MASK) +#define GPMI_STAT_ATA_IRQ_MASK (0x10U) +#define GPMI_STAT_ATA_IRQ_SHIFT (4U) +#define GPMI_STAT_ATA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_ATA_IRQ_SHIFT)) & GPMI_STAT_ATA_IRQ_MASK) +#define GPMI_STAT_RSVD1_MASK (0xE0U) +#define GPMI_STAT_RSVD1_SHIFT (5U) +#define GPMI_STAT_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RSVD1_SHIFT)) & GPMI_STAT_RSVD1_MASK) +#define GPMI_STAT_DEV0_ERROR_MASK (0x100U) +#define GPMI_STAT_DEV0_ERROR_SHIFT (8U) +#define GPMI_STAT_DEV0_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV0_ERROR_SHIFT)) & GPMI_STAT_DEV0_ERROR_MASK) +#define GPMI_STAT_DEV1_ERROR_MASK (0x200U) +#define GPMI_STAT_DEV1_ERROR_SHIFT (9U) +#define GPMI_STAT_DEV1_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV1_ERROR_SHIFT)) & GPMI_STAT_DEV1_ERROR_MASK) +#define GPMI_STAT_DEV2_ERROR_MASK (0x400U) +#define GPMI_STAT_DEV2_ERROR_SHIFT (10U) +#define GPMI_STAT_DEV2_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV2_ERROR_SHIFT)) & GPMI_STAT_DEV2_ERROR_MASK) +#define GPMI_STAT_DEV3_ERROR_MASK (0x800U) +#define GPMI_STAT_DEV3_ERROR_SHIFT (11U) +#define GPMI_STAT_DEV3_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV3_ERROR_SHIFT)) & GPMI_STAT_DEV3_ERROR_MASK) +#define GPMI_STAT_DEV4_ERROR_MASK (0x1000U) +#define GPMI_STAT_DEV4_ERROR_SHIFT (12U) +#define GPMI_STAT_DEV4_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV4_ERROR_SHIFT)) & GPMI_STAT_DEV4_ERROR_MASK) +#define GPMI_STAT_DEV5_ERROR_MASK (0x2000U) +#define GPMI_STAT_DEV5_ERROR_SHIFT (13U) +#define GPMI_STAT_DEV5_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV5_ERROR_SHIFT)) & GPMI_STAT_DEV5_ERROR_MASK) +#define GPMI_STAT_DEV6_ERROR_MASK (0x4000U) +#define GPMI_STAT_DEV6_ERROR_SHIFT (14U) +#define GPMI_STAT_DEV6_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV6_ERROR_SHIFT)) & GPMI_STAT_DEV6_ERROR_MASK) +#define GPMI_STAT_DEV7_ERROR_MASK (0x8000U) +#define GPMI_STAT_DEV7_ERROR_SHIFT (15U) +#define GPMI_STAT_DEV7_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV7_ERROR_SHIFT)) & GPMI_STAT_DEV7_ERROR_MASK) +#define GPMI_STAT_RDY_TIMEOUT_MASK (0xFF0000U) +#define GPMI_STAT_RDY_TIMEOUT_SHIFT (16U) +#define GPMI_STAT_RDY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RDY_TIMEOUT_SHIFT)) & GPMI_STAT_RDY_TIMEOUT_MASK) +#define GPMI_STAT_READY_BUSY_MASK (0xFF000000U) +#define GPMI_STAT_READY_BUSY_SHIFT (24U) +#define GPMI_STAT_READY_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_READY_BUSY_SHIFT)) & GPMI_STAT_READY_BUSY_MASK) + +/*! @name DEBUG - GPMI Debug Information Register Description */ +#define GPMI_DEBUG_CMD_END_MASK (0xFFU) +#define GPMI_DEBUG_CMD_END_SHIFT (0U) +#define GPMI_DEBUG_CMD_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_CMD_END_SHIFT)) & GPMI_DEBUG_CMD_END_MASK) +#define GPMI_DEBUG_DMAREQ_MASK (0xFF00U) +#define GPMI_DEBUG_DMAREQ_SHIFT (8U) +#define GPMI_DEBUG_DMAREQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMAREQ_SHIFT)) & GPMI_DEBUG_DMAREQ_MASK) +#define GPMI_DEBUG_DMA_SENSE_MASK (0xFF0000U) +#define GPMI_DEBUG_DMA_SENSE_SHIFT (16U) +#define GPMI_DEBUG_DMA_SENSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMA_SENSE_SHIFT)) & GPMI_DEBUG_DMA_SENSE_MASK) +#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xFF000000U) +#define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT (24U) +#define GPMI_DEBUG_WAIT_FOR_READY_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT)) & GPMI_DEBUG_WAIT_FOR_READY_END_MASK) + +/*! @name VERSION - GPMI Version Register Description */ +#define GPMI_VERSION_STEP_MASK (0xFFFFU) +#define GPMI_VERSION_STEP_SHIFT (0U) +#define GPMI_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_STEP_SHIFT)) & GPMI_VERSION_STEP_MASK) +#define GPMI_VERSION_MINOR_MASK (0xFF0000U) +#define GPMI_VERSION_MINOR_SHIFT (16U) +#define GPMI_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MINOR_SHIFT)) & GPMI_VERSION_MINOR_MASK) +#define GPMI_VERSION_MAJOR_MASK (0xFF000000U) +#define GPMI_VERSION_MAJOR_SHIFT (24U) +#define GPMI_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MAJOR_SHIFT)) & GPMI_VERSION_MAJOR_MASK) + +/*! @name DEBUG2 - GPMI Debug2 Information Register Description */ +#define GPMI_DEBUG2_RDN_TAP_MASK (0x3FU) +#define GPMI_DEBUG2_RDN_TAP_SHIFT (0U) +#define GPMI_DEBUG2_RDN_TAP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RDN_TAP_SHIFT)) & GPMI_DEBUG2_RDN_TAP_MASK) +#define GPMI_DEBUG2_UPDATE_WINDOW_MASK (0x40U) +#define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT (6U) +#define GPMI_DEBUG2_UPDATE_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UPDATE_WINDOW_SHIFT)) & GPMI_DEBUG2_UPDATE_WINDOW_MASK) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK (0x80U) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT (7U) +#define GPMI_DEBUG2_VIEW_DELAYED_RDN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT)) & GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK) +#define GPMI_DEBUG2_SYND2GPMI_READY_MASK (0x100U) +#define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT (8U) +#define GPMI_DEBUG2_SYND2GPMI_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_READY_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_READY_MASK) +#define GPMI_DEBUG2_SYND2GPMI_VALID_MASK (0x200U) +#define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT (9U) +#define GPMI_DEBUG2_SYND2GPMI_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_VALID_MASK) +#define GPMI_DEBUG2_GPMI2SYND_READY_MASK (0x400U) +#define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT (10U) +#define GPMI_DEBUG2_GPMI2SYND_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_READY_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_READY_MASK) +#define GPMI_DEBUG2_GPMI2SYND_VALID_MASK (0x800U) +#define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT (11U) +#define GPMI_DEBUG2_GPMI2SYND_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_VALID_MASK) +#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xF000U) +#define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT (12U) +#define GPMI_DEBUG2_SYND2GPMI_BE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_BE_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_BE_MASK) +#define GPMI_DEBUG2_MAIN_STATE_MASK (0xF0000U) +#define GPMI_DEBUG2_MAIN_STATE_SHIFT (16U) +#define GPMI_DEBUG2_MAIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_MAIN_STATE_SHIFT)) & GPMI_DEBUG2_MAIN_STATE_MASK) +#define GPMI_DEBUG2_PIN_STATE_MASK (0x700000U) +#define GPMI_DEBUG2_PIN_STATE_SHIFT (20U) +#define GPMI_DEBUG2_PIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_PIN_STATE_SHIFT)) & GPMI_DEBUG2_PIN_STATE_MASK) +#define GPMI_DEBUG2_BUSY_MASK (0x800000U) +#define GPMI_DEBUG2_BUSY_SHIFT (23U) +#define GPMI_DEBUG2_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_BUSY_SHIFT)) & GPMI_DEBUG2_BUSY_MASK) +#define GPMI_DEBUG2_UDMA_STATE_MASK (0xF000000U) +#define GPMI_DEBUG2_UDMA_STATE_SHIFT (24U) +#define GPMI_DEBUG2_UDMA_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UDMA_STATE_SHIFT)) & GPMI_DEBUG2_UDMA_STATE_MASK) +#define GPMI_DEBUG2_RSVD1_MASK (0xF0000000U) +#define GPMI_DEBUG2_RSVD1_SHIFT (28U) +#define GPMI_DEBUG2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RSVD1_SHIFT)) & GPMI_DEBUG2_RSVD1_MASK) + +/*! @name DEBUG3 - GPMI Debug3 Information Register Description */ +#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK (0xFFFFU) +#define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT (0U) +#define GPMI_DEBUG3_DEV_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_DEV_WORD_CNTR_MASK) +#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xFFFF0000U) +#define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT (16U) +#define GPMI_DEBUG3_APB_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_APB_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_APB_WORD_CNTR_MASK) + +/*! @name READ_DDR_DLL_CTRL - GPMI Double Rate Read DLL Control Register Description */ +#define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK (0x1U) +#define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT (0U) +#define GPMI_READ_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK) +#define GPMI_READ_DDR_DLL_CTRL_RESET_MASK (0x2U) +#define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT (1U) +#define GPMI_READ_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RESET_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) +#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK) +#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U) +#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U) +#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U) +#define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT (18U) +#define GPMI_READ_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK) +#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) + +/*! @name WRITE_DDR_DLL_CTRL - GPMI Double Rate Write DLL Control Register Description */ +#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK (0x1U) +#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT (0U) +#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK (0x2U) +#define GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT (1U) +#define GPMI_WRITE_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U) +#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U) +#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U) +#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT (18U) +#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK) + +/*! @name READ_DDR_DLL_STS - GPMI Double Rate Read DLL Status Register Description */ +#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK (0x1U) +#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT (0U) +#define GPMI_READ_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK) +#define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU) +#define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT (1U) +#define GPMI_READ_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK) +#define GPMI_READ_DDR_DLL_STS_RSVD0_MASK (0xFE00U) +#define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT (9U) +#define GPMI_READ_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD0_MASK) +#define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK (0x10000U) +#define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT (16U) +#define GPMI_READ_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK) +#define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U) +#define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT (17U) +#define GPMI_READ_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_SEL_MASK) +#define GPMI_READ_DDR_DLL_STS_RSVD1_MASK (0xFE000000U) +#define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT (25U) +#define GPMI_READ_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD1_MASK) + +/*! @name WRITE_DDR_DLL_STS - GPMI Double Rate Write DLL Status Register Description */ +#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK (0x1U) +#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT (0U) +#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK) +#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU) +#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT (1U) +#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK) +#define GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK (0xFE00U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT (9U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK) +#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK (0x10000U) +#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT (16U) +#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK) +#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U) +#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT (17U) +#define GPMI_WRITE_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK) +#define GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK (0xFE000000U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT (25U) +#define GPMI_WRITE_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK) + + +/*! + * @} + */ /* end of group GPMI_Register_Masks */ + + +/* GPMI - Peripheral instance base addresses */ +/** Peripheral GPMI base address */ +#define GPMI_BASE (0x1806000u) +/** Peripheral GPMI base pointer */ +#define GPMI ((GPMI_Type *)GPMI_BASE) +/** Array initializer of GPMI peripheral base addresses */ +#define GPMI_BASE_ADDRS { GPMI_BASE } +/** Array initializer of GPMI peripheral base pointers */ +#define GPMI_BASE_PTRS { GPMI } +/** Interrupt vectors for the GPMI peripheral type */ +#define GPMI_IRQS { RAWNAND_GPMI_IRQn } + +/*! + * @} + */ /* end of group GPMI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer + * @{ + */ + +/** GPT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */ + __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */ + __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */ + __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */ + __IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */ + __I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */ + __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */ +} GPT_Type; + +/* ---------------------------------------------------------------------------- + -- GPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Register_Masks GPT Register Masks + * @{ + */ + +/*! @name CR - GPT Control Register */ +#define GPT_CR_EN_MASK (0x1U) +#define GPT_CR_EN_SHIFT (0U) +#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) +#define GPT_CR_ENMOD_MASK (0x2U) +#define GPT_CR_ENMOD_SHIFT (1U) +#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) +#define GPT_CR_DBGEN_MASK (0x4U) +#define GPT_CR_DBGEN_SHIFT (2U) +#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) +#define GPT_CR_WAITEN_MASK (0x8U) +#define GPT_CR_WAITEN_SHIFT (3U) +#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) +#define GPT_CR_DOZEEN_MASK (0x10U) +#define GPT_CR_DOZEEN_SHIFT (4U) +#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) +#define GPT_CR_STOPEN_MASK (0x20U) +#define GPT_CR_STOPEN_SHIFT (5U) +#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) +#define GPT_CR_CLKSRC_MASK (0x1C0U) +#define GPT_CR_CLKSRC_SHIFT (6U) +#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) +#define GPT_CR_FRR_MASK (0x200U) +#define GPT_CR_FRR_SHIFT (9U) +#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) +#define GPT_CR_EN_24M_MASK (0x400U) +#define GPT_CR_EN_24M_SHIFT (10U) +#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) +#define GPT_CR_SWR_MASK (0x8000U) +#define GPT_CR_SWR_SHIFT (15U) +#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) +#define GPT_CR_IM1_MASK (0x30000U) +#define GPT_CR_IM1_SHIFT (16U) +#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) +#define GPT_CR_IM2_MASK (0xC0000U) +#define GPT_CR_IM2_SHIFT (18U) +#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) +#define GPT_CR_OM1_MASK (0x700000U) +#define GPT_CR_OM1_SHIFT (20U) +#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) +#define GPT_CR_OM2_MASK (0x3800000U) +#define GPT_CR_OM2_SHIFT (23U) +#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) +#define GPT_CR_OM3_MASK (0x1C000000U) +#define GPT_CR_OM3_SHIFT (26U) +#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) +#define GPT_CR_FO1_MASK (0x20000000U) +#define GPT_CR_FO1_SHIFT (29U) +#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) +#define GPT_CR_FO2_MASK (0x40000000U) +#define GPT_CR_FO2_SHIFT (30U) +#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) +#define GPT_CR_FO3_MASK (0x80000000U) +#define GPT_CR_FO3_SHIFT (31U) +#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) + +/*! @name PR - GPT Prescaler Register */ +#define GPT_PR_PRESCALER_MASK (0xFFFU) +#define GPT_PR_PRESCALER_SHIFT (0U) +#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) +#define GPT_PR_PRESCALER24M_MASK (0xF000U) +#define GPT_PR_PRESCALER24M_SHIFT (12U) +#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) + +/*! @name SR - GPT Status Register */ +#define GPT_SR_OF1_MASK (0x1U) +#define GPT_SR_OF1_SHIFT (0U) +#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) +#define GPT_SR_OF2_MASK (0x2U) +#define GPT_SR_OF2_SHIFT (1U) +#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) +#define GPT_SR_OF3_MASK (0x4U) +#define GPT_SR_OF3_SHIFT (2U) +#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) +#define GPT_SR_IF1_MASK (0x8U) +#define GPT_SR_IF1_SHIFT (3U) +#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) +#define GPT_SR_IF2_MASK (0x10U) +#define GPT_SR_IF2_SHIFT (4U) +#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) +#define GPT_SR_ROV_MASK (0x20U) +#define GPT_SR_ROV_SHIFT (5U) +#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) + +/*! @name IR - GPT Interrupt Register */ +#define GPT_IR_OF1IE_MASK (0x1U) +#define GPT_IR_OF1IE_SHIFT (0U) +#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) +#define GPT_IR_OF2IE_MASK (0x2U) +#define GPT_IR_OF2IE_SHIFT (1U) +#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) +#define GPT_IR_OF3IE_MASK (0x4U) +#define GPT_IR_OF3IE_SHIFT (2U) +#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) +#define GPT_IR_IF1IE_MASK (0x8U) +#define GPT_IR_IF1IE_SHIFT (3U) +#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) +#define GPT_IR_IF2IE_MASK (0x10U) +#define GPT_IR_IF2IE_SHIFT (4U) +#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) +#define GPT_IR_ROVIE_MASK (0x20U) +#define GPT_IR_ROVIE_SHIFT (5U) +#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) + +/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */ +#define GPT_OCR_COMP_MASK (0xFFFFFFFFU) +#define GPT_OCR_COMP_SHIFT (0U) +#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) + +/* The count of GPT_OCR */ +#define GPT_OCR_COUNT (3U) + +/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */ +#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) +#define GPT_ICR_CAPT_SHIFT (0U) +#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) + +/* The count of GPT_ICR */ +#define GPT_ICR_COUNT (2U) + +/*! @name CNT - GPT Counter Register */ +#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) +#define GPT_CNT_COUNT_SHIFT (0U) +#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) + + +/*! + * @} + */ /* end of group GPT_Register_Masks */ + + +/* GPT - Peripheral instance base addresses */ +/** Peripheral GPT1 base address */ +#define GPT1_BASE (0x2098000u) +/** Peripheral GPT1 base pointer */ +#define GPT1 ((GPT_Type *)GPT1_BASE) +/** Peripheral GPT2 base address */ +#define GPT2_BASE (0x20E8000u) +/** Peripheral GPT2 base pointer */ +#define GPT2 ((GPT_Type *)GPT2_BASE) +/** Array initializer of GPT peripheral base addresses */ +#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE } +/** Array initializer of GPT peripheral base pointers */ +#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 } +/** Interrupt vectors for the GPT peripheral type */ +#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn } + +/*! + * @} + */ /* end of group GPT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + __IO uint16_t IADR; /**< I2C Address Register, offset: 0x0 */ + uint8_t RESERVED_0[2]; + __IO uint16_t IFDR; /**< I2C Frequency Divider Register, offset: 0x4 */ + uint8_t RESERVED_1[2]; + __IO uint16_t I2CR; /**< I2C Control Register, offset: 0x8 */ + uint8_t RESERVED_2[2]; + __IO uint16_t I2SR; /**< I2C Status Register, offset: 0xC */ + uint8_t RESERVED_3[2]; + __IO uint16_t I2DR; /**< I2C Data I/O Register, offset: 0x10 */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name IADR - I2C Address Register */ +#define I2C_IADR_ADR_MASK (0xFEU) +#define I2C_IADR_ADR_SHIFT (1U) +#define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x)) << I2C_IADR_ADR_SHIFT)) & I2C_IADR_ADR_MASK) + +/*! @name IFDR - I2C Frequency Divider Register */ +#define I2C_IFDR_IC_MASK (0x3FU) +#define I2C_IFDR_IC_SHIFT (0U) +#define I2C_IFDR_IC(x) (((uint16_t)(((uint16_t)(x)) << I2C_IFDR_IC_SHIFT)) & I2C_IFDR_IC_MASK) + +/*! @name I2CR - I2C Control Register */ +#define I2C_I2CR_RSTA_MASK (0x4U) +#define I2C_I2CR_RSTA_SHIFT (2U) +#define I2C_I2CR_RSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_RSTA_SHIFT)) & I2C_I2CR_RSTA_MASK) +#define I2C_I2CR_TXAK_MASK (0x8U) +#define I2C_I2CR_TXAK_SHIFT (3U) +#define I2C_I2CR_TXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_TXAK_SHIFT)) & I2C_I2CR_TXAK_MASK) +#define I2C_I2CR_MTX_MASK (0x10U) +#define I2C_I2CR_MTX_SHIFT (4U) +#define I2C_I2CR_MTX(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MTX_SHIFT)) & I2C_I2CR_MTX_MASK) +#define I2C_I2CR_MSTA_MASK (0x20U) +#define I2C_I2CR_MSTA_SHIFT (5U) +#define I2C_I2CR_MSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MSTA_SHIFT)) & I2C_I2CR_MSTA_MASK) +#define I2C_I2CR_IIEN_MASK (0x40U) +#define I2C_I2CR_IIEN_SHIFT (6U) +#define I2C_I2CR_IIEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IIEN_SHIFT)) & I2C_I2CR_IIEN_MASK) +#define I2C_I2CR_IEN_MASK (0x80U) +#define I2C_I2CR_IEN_SHIFT (7U) +#define I2C_I2CR_IEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IEN_SHIFT)) & I2C_I2CR_IEN_MASK) + +/*! @name I2SR - I2C Status Register */ +#define I2C_I2SR_RXAK_MASK (0x1U) +#define I2C_I2SR_RXAK_SHIFT (0U) +#define I2C_I2SR_RXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_RXAK_SHIFT)) & I2C_I2SR_RXAK_MASK) +#define I2C_I2SR_IIF_MASK (0x2U) +#define I2C_I2SR_IIF_SHIFT (1U) +#define I2C_I2SR_IIF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IIF_SHIFT)) & I2C_I2SR_IIF_MASK) +#define I2C_I2SR_SRW_MASK (0x4U) +#define I2C_I2SR_SRW_SHIFT (2U) +#define I2C_I2SR_SRW(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_SRW_SHIFT)) & I2C_I2SR_SRW_MASK) +#define I2C_I2SR_IAL_MASK (0x10U) +#define I2C_I2SR_IAL_SHIFT (4U) +#define I2C_I2SR_IAL(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAL_SHIFT)) & I2C_I2SR_IAL_MASK) +#define I2C_I2SR_IBB_MASK (0x20U) +#define I2C_I2SR_IBB_SHIFT (5U) +#define I2C_I2SR_IBB(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IBB_SHIFT)) & I2C_I2SR_IBB_MASK) +#define I2C_I2SR_IAAS_MASK (0x40U) +#define I2C_I2SR_IAAS_SHIFT (6U) +#define I2C_I2SR_IAAS(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAAS_SHIFT)) & I2C_I2SR_IAAS_MASK) +#define I2C_I2SR_ICF_MASK (0x80U) +#define I2C_I2SR_ICF_SHIFT (7U) +#define I2C_I2SR_ICF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_ICF_SHIFT)) & I2C_I2SR_ICF_MASK) + +/*! @name I2DR - I2C Data I/O Register */ +#define I2C_I2DR_DATA_MASK (0xFFU) +#define I2C_I2DR_DATA_SHIFT (0U) +#define I2C_I2DR_DATA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2DR_DATA_SHIFT)) & I2C_I2DR_DATA_MASK) + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +/** Peripheral I2C1 base address */ +#define I2C1_BASE (0x21A0000u) +/** Peripheral I2C1 base pointer */ +#define I2C1 ((I2C_Type *)I2C1_BASE) +/** Peripheral I2C2 base address */ +#define I2C2_BASE (0x21A4000u) +/** Peripheral I2C2 base pointer */ +#define I2C2 ((I2C_Type *)I2C2_BASE) +/** Peripheral I2C3 base address */ +#define I2C3_BASE (0x21A8000u) +/** Peripheral I2C3 base pointer */ +#define I2C3 ((I2C_Type *)I2C3_BASE) +/** Peripheral I2C4 base address */ +#define I2C4_BASE (0x21F8000u) +/** Peripheral I2C4 base pointer */ +#define I2C4 ((I2C_Type *)I2C4_BASE) +/** Array initializer of I2C peripheral base addresses */ +#define I2C_BASE_ADDRS { 0u, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE } +/** Array initializer of I2C peripheral base pointers */ +#define I2C_BASE_PTRS { (I2C_Type *)0u, I2C1, I2C2, I2C3, I2C4 } +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { NotAvail_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn, I2C4_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ + __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */ + __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ + __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ + __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ + __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ + uint8_t RESERVED_0[8]; + __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[28]; + __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_2[28]; + __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ + uint8_t RESERVED_3[28]; + __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ + __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */ + __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ + __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ + __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ + __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ + uint8_t RESERVED_4[8]; + __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_5[28]; + __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_6[28]; + __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name TCSR - SAI Transmit Control Register */ +#define I2S_TCSR_FRDE_MASK (0x1U) +#define I2S_TCSR_FRDE_SHIFT (0U) +#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) +#define I2S_TCSR_FWDE_MASK (0x2U) +#define I2S_TCSR_FWDE_SHIFT (1U) +#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) +#define I2S_TCSR_FRIE_MASK (0x100U) +#define I2S_TCSR_FRIE_SHIFT (8U) +#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) +#define I2S_TCSR_FWIE_MASK (0x200U) +#define I2S_TCSR_FWIE_SHIFT (9U) +#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) +#define I2S_TCSR_FEIE_MASK (0x400U) +#define I2S_TCSR_FEIE_SHIFT (10U) +#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) +#define I2S_TCSR_SEIE_MASK (0x800U) +#define I2S_TCSR_SEIE_SHIFT (11U) +#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) +#define I2S_TCSR_WSIE_MASK (0x1000U) +#define I2S_TCSR_WSIE_SHIFT (12U) +#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) +#define I2S_TCSR_FRF_MASK (0x10000U) +#define I2S_TCSR_FRF_SHIFT (16U) +#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) +#define I2S_TCSR_FWF_MASK (0x20000U) +#define I2S_TCSR_FWF_SHIFT (17U) +#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) +#define I2S_TCSR_FEF_MASK (0x40000U) +#define I2S_TCSR_FEF_SHIFT (18U) +#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) +#define I2S_TCSR_SEF_MASK (0x80000U) +#define I2S_TCSR_SEF_SHIFT (19U) +#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) +#define I2S_TCSR_WSF_MASK (0x100000U) +#define I2S_TCSR_WSF_SHIFT (20U) +#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) +#define I2S_TCSR_SR_MASK (0x1000000U) +#define I2S_TCSR_SR_SHIFT (24U) +#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) +#define I2S_TCSR_FR_MASK (0x2000000U) +#define I2S_TCSR_FR_SHIFT (25U) +#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) +#define I2S_TCSR_BCE_MASK (0x10000000U) +#define I2S_TCSR_BCE_SHIFT (28U) +#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) +#define I2S_TCSR_STOPE_MASK (0x40000000U) +#define I2S_TCSR_STOPE_SHIFT (30U) +#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) +#define I2S_TCSR_TE_MASK (0x80000000U) +#define I2S_TCSR_TE_SHIFT (31U) +#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) + +/*! @name TCR1 - SAI Transmit Configuration 1 Register */ +#define I2S_TCR1_TFW_MASK (0x1FU) +#define I2S_TCR1_TFW_SHIFT (0U) +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) + +/*! @name TCR2 - SAI Transmit Configuration 2 Register */ +#define I2S_TCR2_DIV_MASK (0xFFU) +#define I2S_TCR2_DIV_SHIFT (0U) +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) +#define I2S_TCR2_BCD_MASK (0x1000000U) +#define I2S_TCR2_BCD_SHIFT (24U) +#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) +#define I2S_TCR2_BCP_MASK (0x2000000U) +#define I2S_TCR2_BCP_SHIFT (25U) +#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) +#define I2S_TCR2_MSEL_MASK (0xC000000U) +#define I2S_TCR2_MSEL_SHIFT (26U) +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) +#define I2S_TCR2_BCI_MASK (0x10000000U) +#define I2S_TCR2_BCI_SHIFT (28U) +#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) +#define I2S_TCR2_BCS_MASK (0x20000000U) +#define I2S_TCR2_BCS_SHIFT (29U) +#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) +#define I2S_TCR2_SYNC_MASK (0xC0000000U) +#define I2S_TCR2_SYNC_SHIFT (30U) +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) + +/*! @name TCR3 - SAI Transmit Configuration 3 Register */ +#define I2S_TCR3_WDFL_MASK (0x1FU) +#define I2S_TCR3_WDFL_SHIFT (0U) +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) +#define I2S_TCR3_TCE_MASK (0x10000U) +#define I2S_TCR3_TCE_SHIFT (16U) +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) + +/*! @name TCR4 - SAI Transmit Configuration 4 Register */ +#define I2S_TCR4_FSD_MASK (0x1U) +#define I2S_TCR4_FSD_SHIFT (0U) +#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) +#define I2S_TCR4_FSP_MASK (0x2U) +#define I2S_TCR4_FSP_SHIFT (1U) +#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) +#define I2S_TCR4_FSE_MASK (0x8U) +#define I2S_TCR4_FSE_SHIFT (3U) +#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) +#define I2S_TCR4_MF_MASK (0x10U) +#define I2S_TCR4_MF_SHIFT (4U) +#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) +#define I2S_TCR4_SYWD_MASK (0x1F00U) +#define I2S_TCR4_SYWD_SHIFT (8U) +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) +#define I2S_TCR4_FRSZ_MASK (0x1F0000U) +#define I2S_TCR4_FRSZ_SHIFT (16U) +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) + +/*! @name TCR5 - SAI Transmit Configuration 5 Register */ +#define I2S_TCR5_FBT_MASK (0x1F00U) +#define I2S_TCR5_FBT_SHIFT (8U) +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) +#define I2S_TCR5_W0W_MASK (0x1F0000U) +#define I2S_TCR5_W0W_SHIFT (16U) +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) +#define I2S_TCR5_WNW_MASK (0x1F000000U) +#define I2S_TCR5_WNW_SHIFT (24U) +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) + +/*! @name TDR - SAI Transmit Data Register */ +#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) +#define I2S_TDR_TDR_SHIFT (0U) +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) + +/* The count of I2S_TDR */ +#define I2S_TDR_COUNT (1U) + +/*! @name TFR - SAI Transmit FIFO Register */ +#define I2S_TFR_RFP_MASK (0x3FU) +#define I2S_TFR_RFP_SHIFT (0U) +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) +#define I2S_TFR_WFP_MASK (0x3F0000U) +#define I2S_TFR_WFP_SHIFT (16U) +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) + +/* The count of I2S_TFR */ +#define I2S_TFR_COUNT (1U) + +/*! @name TMR - SAI Transmit Mask Register */ +#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) +#define I2S_TMR_TWM_SHIFT (0U) +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) + +/*! @name RCSR - SAI Receive Control Register */ +#define I2S_RCSR_FRDE_MASK (0x1U) +#define I2S_RCSR_FRDE_SHIFT (0U) +#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) +#define I2S_RCSR_FWDE_MASK (0x2U) +#define I2S_RCSR_FWDE_SHIFT (1U) +#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) +#define I2S_RCSR_FRIE_MASK (0x100U) +#define I2S_RCSR_FRIE_SHIFT (8U) +#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) +#define I2S_RCSR_FWIE_MASK (0x200U) +#define I2S_RCSR_FWIE_SHIFT (9U) +#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) +#define I2S_RCSR_FEIE_MASK (0x400U) +#define I2S_RCSR_FEIE_SHIFT (10U) +#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) +#define I2S_RCSR_SEIE_MASK (0x800U) +#define I2S_RCSR_SEIE_SHIFT (11U) +#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) +#define I2S_RCSR_WSIE_MASK (0x1000U) +#define I2S_RCSR_WSIE_SHIFT (12U) +#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) +#define I2S_RCSR_FRF_MASK (0x10000U) +#define I2S_RCSR_FRF_SHIFT (16U) +#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) +#define I2S_RCSR_FWF_MASK (0x20000U) +#define I2S_RCSR_FWF_SHIFT (17U) +#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) +#define I2S_RCSR_FEF_MASK (0x40000U) +#define I2S_RCSR_FEF_SHIFT (18U) +#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) +#define I2S_RCSR_SEF_MASK (0x80000U) +#define I2S_RCSR_SEF_SHIFT (19U) +#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) +#define I2S_RCSR_WSF_MASK (0x100000U) +#define I2S_RCSR_WSF_SHIFT (20U) +#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) +#define I2S_RCSR_SR_MASK (0x1000000U) +#define I2S_RCSR_SR_SHIFT (24U) +#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) +#define I2S_RCSR_FR_MASK (0x2000000U) +#define I2S_RCSR_FR_SHIFT (25U) +#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) +#define I2S_RCSR_BCE_MASK (0x10000000U) +#define I2S_RCSR_BCE_SHIFT (28U) +#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) +#define I2S_RCSR_STOPE_MASK (0x40000000U) +#define I2S_RCSR_STOPE_SHIFT (30U) +#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) +#define I2S_RCSR_RE_MASK (0x80000000U) +#define I2S_RCSR_RE_SHIFT (31U) +#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) + +/*! @name RCR1 - SAI Receive Configuration 1 Register */ +#define I2S_RCR1_RFW_MASK (0x1FU) +#define I2S_RCR1_RFW_SHIFT (0U) +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) + +/*! @name RCR2 - SAI Receive Configuration 2 Register */ +#define I2S_RCR2_DIV_MASK (0xFFU) +#define I2S_RCR2_DIV_SHIFT (0U) +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) +#define I2S_RCR2_BCD_MASK (0x1000000U) +#define I2S_RCR2_BCD_SHIFT (24U) +#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) +#define I2S_RCR2_BCP_MASK (0x2000000U) +#define I2S_RCR2_BCP_SHIFT (25U) +#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) +#define I2S_RCR2_MSEL_MASK (0xC000000U) +#define I2S_RCR2_MSEL_SHIFT (26U) +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) +#define I2S_RCR2_BCI_MASK (0x10000000U) +#define I2S_RCR2_BCI_SHIFT (28U) +#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) +#define I2S_RCR2_BCS_MASK (0x20000000U) +#define I2S_RCR2_BCS_SHIFT (29U) +#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) +#define I2S_RCR2_SYNC_MASK (0xC0000000U) +#define I2S_RCR2_SYNC_SHIFT (30U) +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) + +/*! @name RCR3 - SAI Receive Configuration 3 Register */ +#define I2S_RCR3_WDFL_MASK (0x1FU) +#define I2S_RCR3_WDFL_SHIFT (0U) +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) +#define I2S_RCR3_RCE_MASK (0x10000U) +#define I2S_RCR3_RCE_SHIFT (16U) +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) + +/*! @name RCR4 - SAI Receive Configuration 4 Register */ +#define I2S_RCR4_FSD_MASK (0x1U) +#define I2S_RCR4_FSD_SHIFT (0U) +#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) +#define I2S_RCR4_FSP_MASK (0x2U) +#define I2S_RCR4_FSP_SHIFT (1U) +#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) +#define I2S_RCR4_FSE_MASK (0x8U) +#define I2S_RCR4_FSE_SHIFT (3U) +#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) +#define I2S_RCR4_MF_MASK (0x10U) +#define I2S_RCR4_MF_SHIFT (4U) +#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) +#define I2S_RCR4_SYWD_MASK (0x1F00U) +#define I2S_RCR4_SYWD_SHIFT (8U) +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) +#define I2S_RCR4_FRSZ_MASK (0x1F0000U) +#define I2S_RCR4_FRSZ_SHIFT (16U) +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) + +/*! @name RCR5 - SAI Receive Configuration 5 Register */ +#define I2S_RCR5_FBT_MASK (0x1F00U) +#define I2S_RCR5_FBT_SHIFT (8U) +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) +#define I2S_RCR5_W0W_MASK (0x1F0000U) +#define I2S_RCR5_W0W_SHIFT (16U) +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) +#define I2S_RCR5_WNW_MASK (0x1F000000U) +#define I2S_RCR5_WNW_SHIFT (24U) +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) + +/*! @name RDR - SAI Receive Data Register */ +#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) +#define I2S_RDR_RDR_SHIFT (0U) +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) + +/* The count of I2S_RDR */ +#define I2S_RDR_COUNT (1U) + +/*! @name RFR - SAI Receive FIFO Register */ +#define I2S_RFR_RFP_MASK (0x3FU) +#define I2S_RFR_RFP_SHIFT (0U) +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) +#define I2S_RFR_WFP_MASK (0x3F0000U) +#define I2S_RFR_WFP_SHIFT (16U) +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) + +/* The count of I2S_RFR */ +#define I2S_RFR_COUNT (1U) + +/*! @name RMR - SAI Receive Mask Register */ +#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) +#define I2S_RMR_RWM_SHIFT (0U) +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral I2S1 base address */ +#define I2S1_BASE (0x2028000u) +/** Peripheral I2S1 base pointer */ +#define I2S1 ((I2S_Type *)I2S1_BASE) +/** Peripheral I2S2 base address */ +#define I2S2_BASE (0x202C000u) +/** Peripheral I2S2 base pointer */ +#define I2S2 ((I2S_Type *)I2S2_BASE) +/** Peripheral I2S3 base address */ +#define I2S3_BASE (0x2030000u) +/** Peripheral I2S3 base pointer */ +#define I2S3 ((I2S_Type *)I2S3_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { 0u, I2S1_BASE, I2S2_BASE, I2S3_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { (I2S_Type *)0u, I2S1, I2S2, I2S3 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn } +#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer + * @{ + */ + +/** IOMUXC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[68]; + __IO uint32_t SW_MUX_CTL_PAD[112]; /**< SW_MUX_CTL_PAD_JTAG_MOD SW MUX Control Register..SW_MUX_CTL_PAD_CSI_DATA07 SW MUX Control Register, array offset: 0x44, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_PAD_DDR[34]; /**< SW_PAD_CTL_PAD_DRAM_ADDR00 SW PAD Control Register..SW_PAD_CTL_PAD_DRAM_RESET SW PAD Control Register, array offset: 0x204, array step: 0x4 */ + uint8_t RESERVED_1[68]; + __IO uint32_t SW_PAD_CTL_PAD[112]; /**< SW_PAD_CTL_PAD_JTAG_MOD SW PAD Control Register..SW_PAD_CTL_PAD_CSI_DATA07 SW PAD Control Register, array offset: 0x2D0, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_GRP[10]; /**< SW_PAD_CTL_GRP_ADDDS SW GRP Register..SW_PAD_CTL_GRP_DDR_TYPE SW GRP Register, array offset: 0x490, array step: 0x4 */ + __IO uint32_t SELECT_INPUT[122]; /**< USB_OTG1_ID_SELECT_INPUT DAISY Register..USDHC2_WP_SELECT_INPUT DAISY Register, array offset: 0x4B8, array step: 0x4 */ +} IOMUXC_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_JTAG_MOD SW MUX Control Register..SW_MUX_CTL_PAD_CSI_DATA07 SW MUX Control Register */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) +#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) +#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) + +/* The count of IOMUXC_SW_MUX_CTL_PAD */ +#define IOMUXC_SW_MUX_CTL_PAD_COUNT (112U) + +/*! @name SW_PAD_CTL_PAD_DDR - SW_PAD_CTL_PAD_DRAM_ADDR00 SW PAD Control Register..SW_PAD_CTL_PAD_DRAM_RESET SW PAD Control Register */ +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DSE_SHIFT (3U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_ODT_MASK (0x700U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_ODT_SHIFT (8U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_ODT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_ODT_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_ODT_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PKE_SHIFT (12U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_PKE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUE_SHIFT (13U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_PUE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUS_MASK (0xC000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUS_SHIFT (14U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_PUS_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_HYS_SHIFT (16U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_HYS_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT_MASK (0x20000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT_SHIFT (17U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_INPUT_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL_MASK (0xC0000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL_SHIFT (18U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DDR_SEL_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_MASK (0x300000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_SHIFT (20U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN_MASK (0x3000000U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN_SHIFT (24U) +#define IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DDR_DO_TRIM_PADN_MASK) + +/* The count of IOMUXC_SW_PAD_CTL_PAD_DDR */ +#define IOMUXC_SW_PAD_CTL_PAD_DDR_COUNT (34U) + +/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_JTAG_MOD SW PAD Control Register..SW_PAD_CTL_PAD_CSI_DATA07 SW PAD Control Register */ +#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U) +#define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U) +#define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U) +#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U) +#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U) +#define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U) +#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U) +#define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U) +#define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U) +#define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK) + +/* The count of IOMUXC_SW_PAD_CTL_PAD */ +#define IOMUXC_SW_PAD_CTL_PAD_COUNT (112U) + +/*! @name SW_PAD_CTL_GRP - SW_PAD_CTL_GRP_ADDDS SW GRP Register..SW_PAD_CTL_GRP_DDR_TYPE SW GRP Register */ +#define IOMUXC_SW_PAD_CTL_GRP_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_GRP_DSE_SHIFT (3U) +#define IOMUXC_SW_PAD_CTL_GRP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_GRP_PKE_SHIFT (12U) +#define IOMUXC_SW_PAD_CTL_GRP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_PKE_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_GRP_PUE_SHIFT (13U) +#define IOMUXC_SW_PAD_CTL_GRP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_PUE_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_GRP_HYS_SHIFT (16U) +#define IOMUXC_SW_PAD_CTL_GRP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_HYS_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT_MASK (0x20000U) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT_SHIFT (17U) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_DDR_INPUT_MASK) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_SEL_MASK (0xC0000U) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_SEL_SHIFT (18U) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_GRP_DDR_SEL_SHIFT)) & IOMUXC_SW_PAD_CTL_GRP_DDR_SEL_MASK) + +/* The count of IOMUXC_SW_PAD_CTL_GRP */ +#define IOMUXC_SW_PAD_CTL_GRP_COUNT (10U) + +/*! @name SELECT_INPUT - USB_OTG1_ID_SELECT_INPUT DAISY Register..USDHC2_WP_SELECT_INPUT DAISY Register */ +#define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ +#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) +#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ + +/* The count of IOMUXC_SELECT_INPUT */ +#define IOMUXC_SELECT_INPUT_COUNT (122U) + + +/*! + * @} + */ /* end of group IOMUXC_Register_Masks */ + + +/* IOMUXC - Peripheral instance base addresses */ +/** Peripheral IOMUXC base address */ +#define IOMUXC_BASE (0x20E0000u) +/** Peripheral IOMUXC base pointer */ +#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) +/** Array initializer of IOMUXC peripheral base addresses */ +#define IOMUXC_BASE_ADDRS { IOMUXC_BASE } +/** Array initializer of IOMUXC peripheral base pointers */ +#define IOMUXC_BASE_PTRS { IOMUXC } + +/*! + * @} + */ /* end of group IOMUXC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_GPR - Register Layout Typedef */ +typedef struct { + __IO uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ + __IO uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ + __IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ + __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ + __IO uint32_t GPR4; /**< GPR4 General Purpose Register, offset: 0x10 */ + __IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 */ + uint8_t RESERVED_0[12]; + __I uint32_t GPR9; /**< GPR9 General Purpose Register, offset: 0x24 */ + __IO uint32_t GPR10; /**< GPR10 General Purpose Register, offset: 0x28 */ + uint8_t RESERVED_1[12]; + __IO uint32_t GPR14; /**< GPR14 General Purpose Register, offset: 0x38 */ +} IOMUXC_GPR_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks + * @{ + */ + +/*! @name GPR0 - GPR0 General Purpose Register */ +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK (0x1U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT (0U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK (0x2U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT (1U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK (0x4U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT (2U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK (0x8U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT (3U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK (0x10U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT (4U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK (0x20U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT (5U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK (0x40U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT (6U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_MASK (0x80U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_SHIFT (7U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_MASK (0x100U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_SHIFT (8U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_MASK (0x200U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_SHIFT (9U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_MASK (0x400U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_SHIFT (10U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_MASK (0x800U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_SHIFT (11U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_MASK (0x1000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_SHIFT (12U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_MASK (0x2000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_SHIFT (13U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_MASK (0x4000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_SHIFT (14U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_MASK (0x8000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_SHIFT (15U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_MASK (0x10000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_SHIFT (16U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_MASK (0x20000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_SHIFT (17U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_MASK (0x40000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_SHIFT (18U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_MASK (0x80000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_SHIFT (19U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_MASK (0x100000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_SHIFT (20U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_MASK (0x200000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_SHIFT (21U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_MASK) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_MASK (0x400000U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_SHIFT (22U) +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_SHIFT)) & IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_MASK) + +/*! @name GPR1 - GPR1 General Purpose Register */ +#define IOMUXC_GPR_GPR1_ACT_CS0_MASK (0x1U) +#define IOMUXC_GPR_GPR1_ACT_CS0_SHIFT (0U) +#define IOMUXC_GPR_GPR1_ACT_CS0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ACT_CS0_SHIFT)) & IOMUXC_GPR_GPR1_ACT_CS0_MASK) +#define IOMUXC_GPR_GPR1_ADDRS0_MASK (0x6U) +#define IOMUXC_GPR_GPR1_ADDRS0_SHIFT (1U) +#define IOMUXC_GPR_GPR1_ADDRS0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADDRS0_SHIFT)) & IOMUXC_GPR_GPR1_ADDRS0_MASK) +#define IOMUXC_GPR_GPR1_ACT_CS1_MASK (0x8U) +#define IOMUXC_GPR_GPR1_ACT_CS1_SHIFT (3U) +#define IOMUXC_GPR_GPR1_ACT_CS1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ACT_CS1_SHIFT)) & IOMUXC_GPR_GPR1_ACT_CS1_MASK) +#define IOMUXC_GPR_GPR1_ADDRS1_MASK (0x30U) +#define IOMUXC_GPR_GPR1_ADDRS1_SHIFT (4U) +#define IOMUXC_GPR_GPR1_ADDRS1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADDRS1_SHIFT)) & IOMUXC_GPR_GPR1_ADDRS1_MASK) +#define IOMUXC_GPR_GPR1_ACT_CS2_MASK (0x40U) +#define IOMUXC_GPR_GPR1_ACT_CS2_SHIFT (6U) +#define IOMUXC_GPR_GPR1_ACT_CS2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ACT_CS2_SHIFT)) & IOMUXC_GPR_GPR1_ACT_CS2_MASK) +#define IOMUXC_GPR_GPR1_ADDRS2_MASK (0x180U) +#define IOMUXC_GPR_GPR1_ADDRS2_SHIFT (7U) +#define IOMUXC_GPR_GPR1_ADDRS2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADDRS2_SHIFT)) & IOMUXC_GPR_GPR1_ADDRS2_MASK) +#define IOMUXC_GPR_GPR1_ACT_CS3_MASK (0x200U) +#define IOMUXC_GPR_GPR1_ACT_CS3_SHIFT (9U) +#define IOMUXC_GPR_GPR1_ACT_CS3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ACT_CS3_SHIFT)) & IOMUXC_GPR_GPR1_ACT_CS3_MASK) +#define IOMUXC_GPR_GPR1_ADDRS3_MASK (0xC00U) +#define IOMUXC_GPR_GPR1_ADDRS3_SHIFT (10U) +#define IOMUXC_GPR_GPR1_ADDRS3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADDRS3_SHIFT)) & IOMUXC_GPR_GPR1_ADDRS3_MASK) +#define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U) +#define IOMUXC_GPR_GPR1_GINT_SHIFT (12U) +#define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK) +#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK (0x4000U) +#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT (14U) +#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK) +#define IOMUXC_GPR_GPR1_ADD_DS_MASK (0x10000U) +#define IOMUXC_GPR_GPR1_ADD_DS_SHIFT (16U) +#define IOMUXC_GPR_GPR1_ADD_DS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ADD_DS_SHIFT)) & IOMUXC_GPR_GPR1_ADD_DS_MASK) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK (0x40000U) +#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT (18U) +#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U) +#define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U) +#define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK) +#define IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_MASK (0x800000U) +#define IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_SHIFT (23U) +#define IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_SHIFT)) & IOMUXC_GPR_GPR1_TZASC1_BOOT_LOCK_MASK) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN_MASK (0x1000000U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN_SHIFT (24U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR1_ARMA7_CLK_APB_DBG_EN_MASK) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN_MASK (0x2000000U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN_SHIFT (25U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN_SHIFT)) & IOMUXC_GPR_GPR1_ARMA7_CLK_ATB_EN_MASK) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN_MASK (0x4000000U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN_SHIFT (26U) +#define IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN_SHIFT)) & IOMUXC_GPR_GPR1_ARMA7_CLK_AHB_EN_MASK) + +/*! @name GPR2 - GPR2 General Purpose Register */ +#define IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_MASK (0x1U) +#define IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_SHIFT (0U) +#define IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_PXP_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_MASK (0x2U) +#define IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_SHIFT (1U) +#define IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_SHIFT)) & IOMUXC_GPR_GPR2_PXP_MEM_SHUTDOWN_MASK) +#define IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_MASK (0x4U) +#define IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_SHIFT (2U) +#define IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_PXP_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_MASK (0x8U) +#define IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_SHIFT (3U) +#define IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_PXP_MEM_LIGHTSLEEP_MASK) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_MASK (0x10U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_SHIFT (4U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF1_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_MASK (0x20U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_SHIFT (5U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF1_MEM_SHUTDOWN_MASK) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_MASK (0x40U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_SHIFT (6U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF1_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_MASK (0x80U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_SHIFT (7U) +#define IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF1_MEM_LIGHTSLEEP_MASK) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_MASK (0x100U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_SHIFT (8U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF2_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_MASK (0x200U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_SHIFT (9U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF2_MEM_SHUTDOWN_MASK) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_MASK (0x400U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_SHIFT (10U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF2_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_MASK (0x800U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_SHIFT (11U) +#define IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_LCDIF2_MEM_LIGHTSLEEP_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_MASK (0x2000U) +#define IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_SHIFT (13U) +#define IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_SHUTDOWN_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_MASK (0x8000U) +#define IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_SHIFT (15U) +#define IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_LIGHTSLEEP_MASK) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U) +#define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK) +#define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U) +#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U) +#define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK) +#define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_MASK (0x8000000U) +#define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_SHIFT (27U) +#define IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_RESET_BYPASS_MASK) +#define IOMUXC_GPR_GPR2_DRAM_RESET_MASK (0x10000000U) +#define IOMUXC_GPR_GPR2_DRAM_RESET_SHIFT (28U) +#define IOMUXC_GPR_GPR2_DRAM_RESET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_RESET_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_RESET_MASK) +#define IOMUXC_GPR_GPR2_DRAM_CKE0_MASK (0x20000000U) +#define IOMUXC_GPR_GPR2_DRAM_CKE0_SHIFT (29U) +#define IOMUXC_GPR_GPR2_DRAM_CKE0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_CKE0_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_CKE0_MASK) +#define IOMUXC_GPR_GPR2_DRAM_CKE1_MASK (0x40000000U) +#define IOMUXC_GPR_GPR2_DRAM_CKE1_SHIFT (30U) +#define IOMUXC_GPR_GPR2_DRAM_CKE1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_CKE1_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_CKE1_MASK) +#define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_MASK (0x80000000U) +#define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_SHIFT (31U) +#define IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_SHIFT)) & IOMUXC_GPR_GPR2_DRAM_CKE_BYPASS_MASK) + +/*! @name GPR3 - GPR3 General Purpose Register */ +#define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU) +#define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U) +#define IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK) +#define IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_MASK (0x2000U) +#define IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_SHIFT (13U) +#define IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_SHIFT)) & IOMUXC_GPR_GPR3_CORE_DBG_ACK_EN_MASK) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK) + +/*! @name GPR4 - GPR4 General Purpose Register */ +#define IOMUXC_GPR_GPR4_SDMA_STOP_REQ_MASK (0x1U) +#define IOMUXC_GPR_GPR4_SDMA_STOP_REQ_SHIFT (0U) +#define IOMUXC_GPR_GPR4_SDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SDMA_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_ENET1_STOP_REQ_MASK (0x8U) +#define IOMUXC_GPR_GPR4_ENET1_STOP_REQ_SHIFT (3U) +#define IOMUXC_GPR_GPR4_ENET1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK (0x10U) +#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT (4U) +#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN_MASK (0x100U) +#define IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN_SHIFT (8U) +#define IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR4_ENET_IPG_CLK_S_EN_MASK) +#define IOMUXC_GPR_GPR4_SDMA_STOP_ACK_MASK (0x10000U) +#define IOMUXC_GPR_GPR4_SDMA_STOP_ACK_SHIFT (16U) +#define IOMUXC_GPR_GPR4_SDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SDMA_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_ENET1_STOP_ACK_MASK (0x80000U) +#define IOMUXC_GPR_GPR4_ENET1_STOP_ACK_SHIFT (19U) +#define IOMUXC_GPR_GPR4_ENET1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK (0x100000U) +#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT (20U) +#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_ARM_WFI_MASK (0x40000000U) +#define IOMUXC_GPR_GPR4_ARM_WFI_SHIFT (30U) +#define IOMUXC_GPR_GPR4_ARM_WFI(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ARM_WFI_SHIFT)) & IOMUXC_GPR_GPR4_ARM_WFI_MASK) +#define IOMUXC_GPR_GPR4_ARM_WFE_MASK (0x80000000U) +#define IOMUXC_GPR_GPR4_ARM_WFE_SHIFT (31U) +#define IOMUXC_GPR_GPR4_ARM_WFE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ARM_WFE_SHIFT)) & IOMUXC_GPR_GPR4_ARM_WFE_MASK) + +/*! @name GPR5 - GPR5 General Purpose Register */ +#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U) +#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U) +#define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK) +#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U) +#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U) +#define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI_MASK (0x300U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI_SHIFT (8U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI_SHIFT)) & IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_CSI_MASK) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF_MASK (0x3000U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF_SHIFT (12U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF_SHIFT)) & IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_LCDIF_MASK) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_MASK (0x30000U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_SHIFT (16U) +#define IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_SHIFT)) & IOMUXC_GPR_GPR5_LCDIF_HANDSHAKE_PXP_MASK) +#define IOMUXC_GPR_GPR5_WDOG3_MASK_MASK (0x100000U) +#define IOMUXC_GPR_GPR5_WDOG3_MASK_SHIFT (20U) +#define IOMUXC_GPR_GPR5_WDOG3_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG3_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG3_MASK_MASK) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK (0x1000000U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT (24U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK) +#define IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_MASK (0x2000000U) +#define IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_SHIFT (25U) +#define IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1_EVENT3IN_SEL_MASK) +#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK (0x4000000U) +#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT (26U) +#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_MASK (0x40000000U) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_SHIFT (30U) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_SHIFT)) & IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT1_MASK) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_MASK (0x80000000U) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_SHIFT (31U) +#define IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_SHIFT)) & IOMUXC_GPR_GPR5_REF_1M_CLK_EPIT2_MASK) + +/*! @name GPR9 - GPR9 General Purpose Register */ +#define IOMUXC_GPR_GPR9_TZASC1_BYP_MASK (0x1U) +#define IOMUXC_GPR_GPR9_TZASC1_BYP_SHIFT (0U) +#define IOMUXC_GPR_GPR9_TZASC1_BYP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_TZASC1_BYP_SHIFT)) & IOMUXC_GPR_GPR9_TZASC1_BYP_MASK) + +/*! @name GPR10 - GPR10 General Purpose Register */ +#define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x1U) +#define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (0U) +#define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK) +#define IOMUXC_GPR_GPR10_DBG_CLK_EN_MASK (0x2U) +#define IOMUXC_GPR_GPR10_DBG_CLK_EN_SHIFT (1U) +#define IOMUXC_GPR_GPR10_DBG_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_CLK_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_CLK_EN_MASK) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x400U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (10U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xF800U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (11U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK) + +/*! @name GPR14 - GPR14 General Purpose Register */ +#define IOMUXC_GPR_GPR14_GPR_MASK (0xFFFFFFFCU) +#define IOMUXC_GPR_GPR14_GPR_SHIFT (2U) +#define IOMUXC_GPR_GPR14_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_GPR_SHIFT)) & IOMUXC_GPR_GPR14_GPR_MASK) + + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Masks */ + + +/* IOMUXC_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_GPR base address */ +#define IOMUXC_GPR_BASE (0x20E4000u) +/** Peripheral IOMUXC_GPR base pointer */ +#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) +/** Array initializer of IOMUXC_GPR peripheral base addresses */ +#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE } +/** Array initializer of IOMUXC_GPR peripheral base pointers */ +#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR } + +/*! + * @} + */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_Peripheral_Access_Layer IOMUXC_SNVS Peripheral Access Layer + * @{ + */ + +/** IOMUXC_SNVS - Register Layout Typedef */ +typedef struct { + __IO uint32_t SW_MUX_CTL_PAD[12]; /**< SW_MUX_CTL_PAD_BOOT_MODE0 SW MUX Control Register..SW_MUX_CTL_PAD_SNVS_TAMPER9 SW MUX Control Register, array offset: 0x0, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_PAD[17]; /**< SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register..SW_PAD_CTL_PAD_SNVS_TAMPER9 SW PAD Control Register, array offset: 0x30, array step: 0x4 */ +} IOMUXC_SNVS_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_Register_Masks IOMUXC_SNVS Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_BOOT_MODE0 SW MUX Control Register..SW_MUX_CTL_PAD_SNVS_TAMPER9 SW MUX Control Register */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_MUX_MODE_MASK) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_SION_MASK (0x10U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_SION_SHIFT (4U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_SION_MASK) + +/* The count of IOMUXC_SNVS_SW_MUX_CTL_PAD */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_COUNT (12U) + +/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register..SW_PAD_CTL_PAD_SNVS_TAMPER9 SW PAD Control Register */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE_SHIFT (0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE_SHIFT (3U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED_SHIFT (6U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE_SHIFT (11U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE_SHIFT (12U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE_SHIFT (13U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS_SHIFT (14U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS_SHIFT (16U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_HYS_MASK) + +/* The count of IOMUXC_SNVS_SW_PAD_CTL_PAD */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_COUNT (17U) + + +/*! + * @} + */ /* end of group IOMUXC_SNVS_Register_Masks */ + + +/* IOMUXC_SNVS - Peripheral instance base addresses */ +/** Peripheral IOMUXC_SNVS base address */ +#define IOMUXC_SNVS_BASE (0x2290000u) +/** Peripheral IOMUXC_SNVS base pointer */ +#define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE) +/** Array initializer of IOMUXC_SNVS peripheral base addresses */ +#define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE } +/** Array initializer of IOMUXC_SNVS peripheral base pointers */ +#define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS } + +/*! + * @} + */ /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- KPP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer + * @{ + */ + +/** KPP - Register Layout Typedef */ +typedef struct { + __IO uint16_t KPCR; /**< Keypad Control Register, offset: 0x0 */ + __IO uint16_t KPSR; /**< Keypad Status Register, offset: 0x2 */ + __IO uint16_t KDDR; /**< Keypad Data Direction Register, offset: 0x4 */ + __IO uint16_t KPDR; /**< Keypad Data Register, offset: 0x6 */ +} KPP_Type; + +/* ---------------------------------------------------------------------------- + -- KPP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Register_Masks KPP Register Masks + * @{ + */ + +/*! @name KPCR - Keypad Control Register */ +#define KPP_KPCR_KRE_MASK (0xFFU) +#define KPP_KPCR_KRE_SHIFT (0U) +#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK) +#define KPP_KPCR_KCO_MASK (0xFF00U) +#define KPP_KPCR_KCO_SHIFT (8U) +#define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK) + +/*! @name KPSR - Keypad Status Register */ +#define KPP_KPSR_KPKD_MASK (0x1U) +#define KPP_KPSR_KPKD_SHIFT (0U) +#define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK) +#define KPP_KPSR_KPKR_MASK (0x2U) +#define KPP_KPSR_KPKR_SHIFT (1U) +#define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK) +#define KPP_KPSR_KDSC_MASK (0x4U) +#define KPP_KPSR_KDSC_SHIFT (2U) +#define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK) +#define KPP_KPSR_KRSS_MASK (0x8U) +#define KPP_KPSR_KRSS_SHIFT (3U) +#define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK) +#define KPP_KPSR_KDIE_MASK (0x100U) +#define KPP_KPSR_KDIE_SHIFT (8U) +#define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK) +#define KPP_KPSR_KRIE_MASK (0x200U) +#define KPP_KPSR_KRIE_SHIFT (9U) +#define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK) + +/*! @name KDDR - Keypad Data Direction Register */ +#define KPP_KDDR_KRDD_MASK (0xFFU) +#define KPP_KDDR_KRDD_SHIFT (0U) +#define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK) +#define KPP_KDDR_KCDD_MASK (0xFF00U) +#define KPP_KDDR_KCDD_SHIFT (8U) +#define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK) + +/*! @name KPDR - Keypad Data Register */ +#define KPP_KPDR_KRD_MASK (0xFFU) +#define KPP_KPDR_KRD_SHIFT (0U) +#define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK) +#define KPP_KPDR_KCD_MASK (0xFF00U) +#define KPP_KPDR_KCD_SHIFT (8U) +#define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) + + +/*! + * @} + */ /* end of group KPP_Register_Masks */ + + +/* KPP - Peripheral instance base addresses */ +/** Peripheral KPP base address */ +#define KPP_BASE (0x20B8000u) +/** Peripheral KPP base pointer */ +#define KPP ((KPP_Type *)KPP_BASE) +/** Array initializer of KPP peripheral base addresses */ +#define KPP_BASE_ADDRS { KPP_BASE } +/** Array initializer of KPP peripheral base pointers */ +#define KPP_BASE_PTRS { KPP } +/** Interrupt vectors for the KPP peripheral type */ +#define KPP_IRQS { KPP_IRQn } + +/*! + * @} + */ /* end of group KPP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LCDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer + * @{ + */ + +/** LCDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< eLCDIF General Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< eLCDIF General Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< eLCDIF General Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< eLCDIF General Control Register, offset: 0xC */ + __IO uint32_t CTRL1; /**< eLCDIF General Control1 Register, offset: 0x10 */ + __IO uint32_t CTRL1_SET; /**< eLCDIF General Control1 Register, offset: 0x14 */ + __IO uint32_t CTRL1_CLR; /**< eLCDIF General Control1 Register, offset: 0x18 */ + __IO uint32_t CTRL1_TOG; /**< eLCDIF General Control1 Register, offset: 0x1C */ + __IO uint32_t CTRL2; /**< eLCDIF General Control2 Register, offset: 0x20 */ + __IO uint32_t CTRL2_SET; /**< eLCDIF General Control2 Register, offset: 0x24 */ + __IO uint32_t CTRL2_CLR; /**< eLCDIF General Control2 Register, offset: 0x28 */ + __IO uint32_t CTRL2_TOG; /**< eLCDIF General Control2 Register, offset: 0x2C */ + __IO uint32_t TRANSFER_COUNT; /**< eLCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t TIMING; /**< LCD Interface Timing Register, offset: 0x60 */ + uint8_t RESERVED_3[12]; + __IO uint32_t VDCTRL0; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ + __IO uint32_t VDCTRL0_SET; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ + __IO uint32_t VDCTRL0_CLR; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ + __IO uint32_t VDCTRL0_TOG; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ + __IO uint32_t VDCTRL1; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ + uint8_t RESERVED_4[12]; + __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */ + uint8_t RESERVED_5[12]; + __IO uint32_t VDCTRL3; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ + uint8_t RESERVED_6[12]; + __IO uint32_t VDCTRL4; /**< eLCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ + uint8_t RESERVED_7[12]; + __IO uint32_t DVICTRL0; /**< Digital Video Interface Control0 Register, offset: 0xC0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t DVICTRL1; /**< Digital Video Interface Control1 Register, offset: 0xD0 */ + uint8_t RESERVED_9[12]; + __IO uint32_t DVICTRL2; /**< Digital Video Interface Control2 Register, offset: 0xE0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t DVICTRL3; /**< Digital Video Interface Control3 Register, offset: 0xF0 */ + uint8_t RESERVED_11[12]; + __IO uint32_t DVICTRL4; /**< Digital Video Interface Control4 Register, offset: 0x100 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CSC_COEFF0; /**< RGB to YCbCr 4:2:2 CSC Coefficient0 Register, offset: 0x110 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CSC_COEFF1; /**< RGB to YCbCr 4:2:2 CSC Coefficient1 Register, offset: 0x120 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CSC_COEFF2; /**< RGB to YCbCr 4:2:2 CSC Coefficent2 Register, offset: 0x130 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CSC_COEFF3; /**< RGB to YCbCr 4:2:2 CSC Coefficient3 Register, offset: 0x140 */ + uint8_t RESERVED_16[12]; + __IO uint32_t CSC_COEFF4; /**< RGB to YCbCr 4:2:2 CSC Coefficient4 Register, offset: 0x150 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CSC_OFFSET; /**< RGB to YCbCr 4:2:2 CSC Offset Register, offset: 0x160 */ + uint8_t RESERVED_18[12]; + __IO uint32_t CSC_LIMIT; /**< RGB to YCbCr 4:2:2 CSC Limit Register, offset: 0x170 */ + uint8_t RESERVED_19[12]; + __IO uint32_t DATA; /**< LCD Interface Data Register, offset: 0x180 */ + uint8_t RESERVED_20[12]; + __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */ + uint8_t RESERVED_22[12]; + __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ + uint8_t RESERVED_23[76]; + __IO uint32_t THRES; /**< eLCDIF Threshold Register, offset: 0x200 */ + uint8_t RESERVED_24[12]; + __IO uint32_t AS_CTRL; /**< eLCDIF AS Buffer Control Register, offset: 0x210 */ + uint8_t RESERVED_25[12]; + __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x220 */ + uint8_t RESERVED_26[12]; + __IO uint32_t AS_NEXT_BUF; /**< , offset: 0x230 */ + uint8_t RESERVED_27[12]; + __IO uint32_t AS_CLRKEYLOW; /**< eLCDIF Overlay Color Key Low, offset: 0x240 */ + uint8_t RESERVED_28[12]; + __IO uint32_t AS_CLRKEYHIGH; /**< eLCDIF Overlay Color Key High, offset: 0x250 */ + uint8_t RESERVED_29[12]; + __IO uint32_t SYNC_DELAY; /**< LCD working insync mode with CSI for VSYNC delay, offset: 0x260 */ +} LCDIF_Type; + +/* ---------------------------------------------------------------------------- + -- LCDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Register_Masks LCDIF Register Masks + * @{ + */ + +/*! @name CTRL - eLCDIF General Control Register */ +#define LCDIF_CTRL_RUN_MASK (0x1U) +#define LCDIF_CTRL_RUN_SHIFT (0U) +#define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK) +#define LCDIF_CTRL_MASTER_MASK (0x20U) +#define LCDIF_CTRL_MASTER_SHIFT (5U) +#define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK) +#define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_DATA_SELECT_SHIFT (16U) +#define LCDIF_CTRL_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SELECT_SHIFT)) & LCDIF_CTRL_DATA_SELECT_MASK) +#define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_VSYNC_MODE_MASK) +#define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DVI_MODE_SHIFT)) & LCDIF_CTRL_DVI_MODE_MASK) +#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK) +#define LCDIF_CTRL_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_READ_WRITEB_SHIFT)) & LCDIF_CTRL_READ_WRITEB_MASK) +#define LCDIF_CTRL_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_YCBCR422_INPUT_MASK) +#define LCDIF_CTRL_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK) +#define LCDIF_CTRL_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) + +/*! @name CTRL_SET - eLCDIF General Control Register */ +#define LCDIF_CTRL_SET_RUN_MASK (0x1U) +#define LCDIF_CTRL_SET_RUN_SHIFT (0U) +#define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK) +#define LCDIF_CTRL_SET_MASTER_MASK (0x20U) +#define LCDIF_CTRL_SET_MASTER_SHIFT (5U) +#define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK) +#define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_SET_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_SET_DATA_SELECT_SHIFT (16U) +#define LCDIF_CTRL_SET_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SELECT_SHIFT)) & LCDIF_CTRL_SET_DATA_SELECT_MASK) +#define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_SET_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_SET_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_SET_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_SET_VSYNC_MODE_MASK) +#define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_SET_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_SET_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_SET_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DVI_MODE_SHIFT)) & LCDIF_CTRL_SET_DVI_MODE_MASK) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK) +#define LCDIF_CTRL_SET_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_SET_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_SET_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_READ_WRITEB_SHIFT)) & LCDIF_CTRL_SET_READ_WRITEB_MASK) +#define LCDIF_CTRL_SET_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_SET_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_SET_YCBCR422_INPUT_MASK) +#define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK) +#define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_SET_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) + +/*! @name CTRL_CLR - eLCDIF General Control Register */ +#define LCDIF_CTRL_CLR_RUN_MASK (0x1U) +#define LCDIF_CTRL_CLR_RUN_SHIFT (0U) +#define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK) +#define LCDIF_CTRL_CLR_MASTER_MASK (0x20U) +#define LCDIF_CTRL_CLR_MASTER_SHIFT (5U) +#define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK) +#define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_CLR_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_CLR_DATA_SELECT_SHIFT (16U) +#define LCDIF_CTRL_CLR_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SELECT_SHIFT)) & LCDIF_CTRL_CLR_DATA_SELECT_MASK) +#define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_CLR_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_CLR_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_CLR_VSYNC_MODE_MASK) +#define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_CLR_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_CLR_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_CLR_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DVI_MODE_SHIFT)) & LCDIF_CTRL_CLR_DVI_MODE_MASK) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK) +#define LCDIF_CTRL_CLR_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_CLR_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_CLR_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_READ_WRITEB_SHIFT)) & LCDIF_CTRL_CLR_READ_WRITEB_MASK) +#define LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_CLR_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK) +#define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK) +#define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) + +/*! @name CTRL_TOG - eLCDIF General Control Register */ +#define LCDIF_CTRL_TOG_RUN_MASK (0x1U) +#define LCDIF_CTRL_TOG_RUN_SHIFT (0U) +#define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U) +#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK) +#define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U) +#define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U) +#define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK) +#define LCDIF_CTRL_TOG_MASTER_MASK (0x20U) +#define LCDIF_CTRL_TOG_MASTER_SHIFT (5U) +#define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U) +#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK) +#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK (0x80U) +#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT (7U) +#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK) +#define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U) +#define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U) +#define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U) +#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U) +#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U) +#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_CTRL_TOG_DATA_SELECT_MASK (0x10000U) +#define LCDIF_CTRL_TOG_DATA_SELECT_SHIFT (16U) +#define LCDIF_CTRL_TOG_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SELECT_SHIFT)) & LCDIF_CTRL_TOG_DATA_SELECT_MASK) +#define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U) +#define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U) +#define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK) +#define LCDIF_CTRL_TOG_VSYNC_MODE_MASK (0x40000U) +#define LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT (18U) +#define LCDIF_CTRL_TOG_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_TOG_VSYNC_MODE_MASK) +#define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U) +#define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U) +#define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK) +#define LCDIF_CTRL_TOG_DVI_MODE_MASK (0x100000U) +#define LCDIF_CTRL_TOG_DVI_MODE_SHIFT (20U) +#define LCDIF_CTRL_TOG_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DVI_MODE_SHIFT)) & LCDIF_CTRL_TOG_DVI_MODE_MASK) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U) +#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U) +#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK) +#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) +#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) +#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK) +#define LCDIF_CTRL_TOG_READ_WRITEB_MASK (0x10000000U) +#define LCDIF_CTRL_TOG_READ_WRITEB_SHIFT (28U) +#define LCDIF_CTRL_TOG_READ_WRITEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_READ_WRITEB_SHIFT)) & LCDIF_CTRL_TOG_READ_WRITEB_MASK) +#define LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK (0x20000000U) +#define LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT (29U) +#define LCDIF_CTRL_TOG_YCBCR422_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK) +#define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U) +#define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK) +#define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) +#define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) + +/*! @name CTRL1 - eLCDIF General Control1 Register */ +#define LCDIF_CTRL1_RESET_MASK (0x1U) +#define LCDIF_CTRL1_RESET_SHIFT (0U) +#define LCDIF_CTRL1_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RESET_SHIFT)) & LCDIF_CTRL1_RESET_MASK) +#define LCDIF_CTRL1_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_MODE86_SHIFT (1U) +#define LCDIF_CTRL1_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_MODE86_SHIFT)) & LCDIF_CTRL1_MODE86_MASK) +#define LCDIF_CTRL1_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_BUSY_ENABLE_SHIFT (2U) +#define LCDIF_CTRL1_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_BUSY_ENABLE_MASK) +#define LCDIF_CTRL1_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK) +#define LCDIF_CTRL1_RSRVD1_MASK (0xF0000000U) +#define LCDIF_CTRL1_RSRVD1_SHIFT (28U) +#define LCDIF_CTRL1_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD1_SHIFT)) & LCDIF_CTRL1_RSRVD1_MASK) + +/*! @name CTRL1_SET - eLCDIF General Control1 Register */ +#define LCDIF_CTRL1_SET_RESET_MASK (0x1U) +#define LCDIF_CTRL1_SET_RESET_SHIFT (0U) +#define LCDIF_CTRL1_SET_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RESET_SHIFT)) & LCDIF_CTRL1_SET_RESET_MASK) +#define LCDIF_CTRL1_SET_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_SET_MODE86_SHIFT (1U) +#define LCDIF_CTRL1_SET_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_MODE86_SHIFT)) & LCDIF_CTRL1_SET_MODE86_MASK) +#define LCDIF_CTRL1_SET_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT (2U) +#define LCDIF_CTRL1_SET_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_SET_BUSY_ENABLE_MASK) +#define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK) +#define LCDIF_CTRL1_SET_RSRVD1_MASK (0xF0000000U) +#define LCDIF_CTRL1_SET_RSRVD1_SHIFT (28U) +#define LCDIF_CTRL1_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD1_SHIFT)) & LCDIF_CTRL1_SET_RSRVD1_MASK) + +/*! @name CTRL1_CLR - eLCDIF General Control1 Register */ +#define LCDIF_CTRL1_CLR_RESET_MASK (0x1U) +#define LCDIF_CTRL1_CLR_RESET_SHIFT (0U) +#define LCDIF_CTRL1_CLR_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RESET_SHIFT)) & LCDIF_CTRL1_CLR_RESET_MASK) +#define LCDIF_CTRL1_CLR_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_CLR_MODE86_SHIFT (1U) +#define LCDIF_CTRL1_CLR_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_MODE86_SHIFT)) & LCDIF_CTRL1_CLR_MODE86_MASK) +#define LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT (2U) +#define LCDIF_CTRL1_CLR_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK) +#define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK) +#define LCDIF_CTRL1_CLR_RSRVD1_MASK (0xF0000000U) +#define LCDIF_CTRL1_CLR_RSRVD1_SHIFT (28U) +#define LCDIF_CTRL1_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD1_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD1_MASK) + +/*! @name CTRL1_TOG - eLCDIF General Control1 Register */ +#define LCDIF_CTRL1_TOG_RESET_MASK (0x1U) +#define LCDIF_CTRL1_TOG_RESET_SHIFT (0U) +#define LCDIF_CTRL1_TOG_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RESET_SHIFT)) & LCDIF_CTRL1_TOG_RESET_MASK) +#define LCDIF_CTRL1_TOG_MODE86_MASK (0x2U) +#define LCDIF_CTRL1_TOG_MODE86_SHIFT (1U) +#define LCDIF_CTRL1_TOG_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_MODE86_SHIFT)) & LCDIF_CTRL1_TOG_MODE86_MASK) +#define LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK (0x4U) +#define LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT (2U) +#define LCDIF_CTRL1_TOG_BUSY_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK) +#define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U) +#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) +#define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U) +#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) +#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U) +#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U) +#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U) +#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) +#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U) +#define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) +#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U) +#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U) +#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U) +#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK) +#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK (0x8000000U) +#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT (27U) +#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK) +#define LCDIF_CTRL1_TOG_RSRVD1_MASK (0xF0000000U) +#define LCDIF_CTRL1_TOG_RSRVD1_SHIFT (28U) +#define LCDIF_CTRL1_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD1_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD1_MASK) + +/*! @name CTRL2 - eLCDIF General Control2 Register */ +#define LCDIF_CTRL2_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD1_SHIFT)) & LCDIF_CTRL2_RSRVD1_MASK) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) +#define LCDIF_CTRL2_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_READ_PACK_DIR_MASK) +#define LCDIF_CTRL2_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD2_SHIFT)) & LCDIF_CTRL2_RSRVD2_MASK) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK) +#define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) + +/*! @name CTRL2_SET - eLCDIF General Control2 Register */ +#define LCDIF_CTRL2_SET_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) +#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_SET_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_SET_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD1_SHIFT)) & LCDIF_CTRL2_SET_RSRVD1_MASK) +#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK) +#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) +#define LCDIF_CTRL2_SET_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_SET_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_SET_READ_PACK_DIR_MASK) +#define LCDIF_CTRL2_SET_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_SET_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD2_SHIFT)) & LCDIF_CTRL2_SET_RSRVD2_MASK) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK) +#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) + +/*! @name CTRL2_CLR - eLCDIF General Control2 Register */ +#define LCDIF_CTRL2_CLR_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) +#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_CLR_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_CLR_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD1_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD1_MASK) +#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK) +#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) +#define LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_CLR_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK) +#define LCDIF_CTRL2_CLR_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_CLR_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD2_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD2_MASK) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK) +#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) + +/*! @name CTRL2_TOG - eLCDIF General Control2 Register */ +#define LCDIF_CTRL2_TOG_RSRVD0_MASK (0x1U) +#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) +#define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) +#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK (0xEU) +#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT (1U) +#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK) +#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U) +#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U) +#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK) +#define LCDIF_CTRL2_TOG_RSRVD1_MASK (0x80U) +#define LCDIF_CTRL2_TOG_RSRVD1_SHIFT (7U) +#define LCDIF_CTRL2_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD1_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD1_MASK) +#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK (0x100U) +#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT (8U) +#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK) +#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U) +#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U) +#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK) +#define LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK (0x400U) +#define LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT (10U) +#define LCDIF_CTRL2_TOG_READ_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK) +#define LCDIF_CTRL2_TOG_RSRVD2_MASK (0x800U) +#define LCDIF_CTRL2_TOG_RSRVD2_SHIFT (11U) +#define LCDIF_CTRL2_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD2_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD2_MASK) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U) +#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U) +#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U) +#define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U) +#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) +#define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U) +#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U) +#define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK) +#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U) +#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U) +#define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U) +#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) +#define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) +#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) +#define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) + +/*! @name TRANSFER_COUNT - eLCDIF Horizontal and Vertical Valid Data Count Register */ +#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU) +#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) +#define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) +#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U) +#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) +#define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) + +/*! @name CUR_BUF - LCD Interface Current Buffer Address Register */ +#define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_CUR_BUF_ADDR_SHIFT (0U) +#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) + +/*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */ +#define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_NEXT_BUF_ADDR_SHIFT (0U) +#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) + +/*! @name TIMING - LCD Interface Timing Register */ +#define LCDIF_TIMING_DATA_SETUP_MASK (0xFFU) +#define LCDIF_TIMING_DATA_SETUP_SHIFT (0U) +#define LCDIF_TIMING_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_SETUP_SHIFT)) & LCDIF_TIMING_DATA_SETUP_MASK) +#define LCDIF_TIMING_DATA_HOLD_MASK (0xFF00U) +#define LCDIF_TIMING_DATA_HOLD_SHIFT (8U) +#define LCDIF_TIMING_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_HOLD_SHIFT)) & LCDIF_TIMING_DATA_HOLD_MASK) +#define LCDIF_TIMING_CMD_SETUP_MASK (0xFF0000U) +#define LCDIF_TIMING_CMD_SETUP_SHIFT (16U) +#define LCDIF_TIMING_CMD_SETUP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_SETUP_SHIFT)) & LCDIF_TIMING_CMD_SETUP_MASK) +#define LCDIF_TIMING_CMD_HOLD_MASK (0xFF000000U) +#define LCDIF_TIMING_CMD_HOLD_SHIFT (24U) +#define LCDIF_TIMING_CMD_HOLD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_HOLD_SHIFT)) & LCDIF_TIMING_CMD_HOLD_MASK) + +/*! @name VDCTRL0 - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK) +#define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT (29U) +#define LCDIF_VDCTRL0_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK) +#define LCDIF_VDCTRL0_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) + +/*! @name VDCTRL0_SET - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK) +#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT (29U) +#define LCDIF_VDCTRL0_SET_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK) +#define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) + +/*! @name VDCTRL0_CLR - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT (29U) +#define LCDIF_VDCTRL0_CLR_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK) +#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) + +/*! @name VDCTRL0_TOG - eLCDIF VSYNC Mode and Dotclk Mode Control Register0 */ +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U) +#define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U) +#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK) +#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U) +#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U) +#define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U) +#define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U) +#define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U) +#define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U) +#define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U) +#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK) +#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK (0x20000000U) +#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT (29U) +#define LCDIF_VDCTRL0_TOG_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK) +#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xC0000000U) +#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (30U) +#define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) + +/*! @name VDCTRL1 - eLCDIF VSYNC Mode and Dotclk Mode Control Register1 */ +#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU) +#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) +#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) + +/*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */ +#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU) +#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) +#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) + +/*! @name VDCTRL3 - eLCDIF VSYNC Mode and Dotclk Mode Control Register3 */ +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U) +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) +#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U) +#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U) +#define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U) +#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK) +#define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) +#define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) +#define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) + +/*! @name VDCTRL4 - eLCDIF VSYNC Mode and Dotclk Mode Control Register4 */ +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U) +#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK) +#define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U) +#define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U) +#define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) + +/*! @name DVICTRL0 - Digital Video Interface Control0 Register */ +#define LCDIF_DVICTRL0_H_BLANKING_CNT_MASK (0xFFFU) +#define LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT (0U) +#define LCDIF_DVICTRL0_H_BLANKING_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT)) & LCDIF_DVICTRL0_H_BLANKING_CNT_MASK) +#define LCDIF_DVICTRL0_RSRVD0_MASK (0xF000U) +#define LCDIF_DVICTRL0_RSRVD0_SHIFT (12U) +#define LCDIF_DVICTRL0_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD0_SHIFT)) & LCDIF_DVICTRL0_RSRVD0_MASK) +#define LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK (0xFFF0000U) +#define LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT (16U) +#define LCDIF_DVICTRL0_H_ACTIVE_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT)) & LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK) +#define LCDIF_DVICTRL0_RSRVD1_MASK (0xF0000000U) +#define LCDIF_DVICTRL0_RSRVD1_SHIFT (28U) +#define LCDIF_DVICTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD1_SHIFT)) & LCDIF_DVICTRL0_RSRVD1_MASK) + +/*! @name DVICTRL1 - Digital Video Interface Control1 Register */ +#define LCDIF_DVICTRL1_F2_START_LINE_MASK (0x3FFU) +#define LCDIF_DVICTRL1_F2_START_LINE_SHIFT (0U) +#define LCDIF_DVICTRL1_F2_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F2_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F2_START_LINE_MASK) +#define LCDIF_DVICTRL1_F1_END_LINE_MASK (0xFFC00U) +#define LCDIF_DVICTRL1_F1_END_LINE_SHIFT (10U) +#define LCDIF_DVICTRL1_F1_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_END_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_END_LINE_MASK) +#define LCDIF_DVICTRL1_F1_START_LINE_MASK (0x3FF00000U) +#define LCDIF_DVICTRL1_F1_START_LINE_SHIFT (20U) +#define LCDIF_DVICTRL1_F1_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_START_LINE_MASK) +#define LCDIF_DVICTRL1_RSRVD0_MASK (0xC0000000U) +#define LCDIF_DVICTRL1_RSRVD0_SHIFT (30U) +#define LCDIF_DVICTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_RSRVD0_SHIFT)) & LCDIF_DVICTRL1_RSRVD0_MASK) + +/*! @name DVICTRL2 - Digital Video Interface Control2 Register */ +#define LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK (0x3FFU) +#define LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT (0U) +#define LCDIF_DVICTRL2_V1_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK) +#define LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK (0xFFC00U) +#define LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT (10U) +#define LCDIF_DVICTRL2_V1_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK) +#define LCDIF_DVICTRL2_F2_END_LINE_MASK (0x3FF00000U) +#define LCDIF_DVICTRL2_F2_END_LINE_SHIFT (20U) +#define LCDIF_DVICTRL2_F2_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_F2_END_LINE_SHIFT)) & LCDIF_DVICTRL2_F2_END_LINE_MASK) +#define LCDIF_DVICTRL2_RSRVD0_MASK (0xC0000000U) +#define LCDIF_DVICTRL2_RSRVD0_SHIFT (30U) +#define LCDIF_DVICTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_RSRVD0_SHIFT)) & LCDIF_DVICTRL2_RSRVD0_MASK) + +/*! @name DVICTRL3 - Digital Video Interface Control3 Register */ +#define LCDIF_DVICTRL3_V_LINES_CNT_MASK (0x3FFU) +#define LCDIF_DVICTRL3_V_LINES_CNT_SHIFT (0U) +#define LCDIF_DVICTRL3_V_LINES_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V_LINES_CNT_SHIFT)) & LCDIF_DVICTRL3_V_LINES_CNT_MASK) +#define LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK (0xFFC00U) +#define LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT (10U) +#define LCDIF_DVICTRL3_V2_BLANK_END_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK) +#define LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK (0x3FF00000U) +#define LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT (20U) +#define LCDIF_DVICTRL3_V2_BLANK_START_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK) +#define LCDIF_DVICTRL3_RSRVD0_MASK (0xC0000000U) +#define LCDIF_DVICTRL3_RSRVD0_SHIFT (30U) +#define LCDIF_DVICTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_RSRVD0_SHIFT)) & LCDIF_DVICTRL3_RSRVD0_MASK) + +/*! @name DVICTRL4 - Digital Video Interface Control4 Register */ +#define LCDIF_DVICTRL4_H_FILL_CNT_MASK (0xFFU) +#define LCDIF_DVICTRL4_H_FILL_CNT_SHIFT (0U) +#define LCDIF_DVICTRL4_H_FILL_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_H_FILL_CNT_SHIFT)) & LCDIF_DVICTRL4_H_FILL_CNT_MASK) +#define LCDIF_DVICTRL4_CR_FILL_VALUE_MASK (0xFF00U) +#define LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT (8U) +#define LCDIF_DVICTRL4_CR_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CR_FILL_VALUE_MASK) +#define LCDIF_DVICTRL4_CB_FILL_VALUE_MASK (0xFF0000U) +#define LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT (16U) +#define LCDIF_DVICTRL4_CB_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CB_FILL_VALUE_MASK) +#define LCDIF_DVICTRL4_Y_FILL_VALUE_MASK (0xFF000000U) +#define LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT (24U) +#define LCDIF_DVICTRL4_Y_FILL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_Y_FILL_VALUE_MASK) + +/*! @name CSC_COEFF0 - RGB to YCbCr 4:2:2 CSC Coefficient0 Register */ +#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK (0x3U) +#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT (0U) +#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT)) & LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK) +#define LCDIF_CSC_COEFF0_RSRVD0_MASK (0xFFFCU) +#define LCDIF_CSC_COEFF0_RSRVD0_SHIFT (2U) +#define LCDIF_CSC_COEFF0_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD0_MASK) +#define LCDIF_CSC_COEFF0_C0_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF0_C0_SHIFT (16U) +#define LCDIF_CSC_COEFF0_C0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_C0_SHIFT)) & LCDIF_CSC_COEFF0_C0_MASK) +#define LCDIF_CSC_COEFF0_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF0_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD1_MASK) + +/*! @name CSC_COEFF1 - RGB to YCbCr 4:2:2 CSC Coefficient1 Register */ +#define LCDIF_CSC_COEFF1_C1_MASK (0x3FFU) +#define LCDIF_CSC_COEFF1_C1_SHIFT (0U) +#define LCDIF_CSC_COEFF1_C1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C1_SHIFT)) & LCDIF_CSC_COEFF1_C1_MASK) +#define LCDIF_CSC_COEFF1_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF1_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD0_MASK) +#define LCDIF_CSC_COEFF1_C2_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF1_C2_SHIFT (16U) +#define LCDIF_CSC_COEFF1_C2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C2_SHIFT)) & LCDIF_CSC_COEFF1_C2_MASK) +#define LCDIF_CSC_COEFF1_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF1_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF1_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD1_MASK) + +/*! @name CSC_COEFF2 - RGB to YCbCr 4:2:2 CSC Coefficent2 Register */ +#define LCDIF_CSC_COEFF2_C3_MASK (0x3FFU) +#define LCDIF_CSC_COEFF2_C3_SHIFT (0U) +#define LCDIF_CSC_COEFF2_C3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C3_SHIFT)) & LCDIF_CSC_COEFF2_C3_MASK) +#define LCDIF_CSC_COEFF2_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF2_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD0_MASK) +#define LCDIF_CSC_COEFF2_C4_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF2_C4_SHIFT (16U) +#define LCDIF_CSC_COEFF2_C4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C4_SHIFT)) & LCDIF_CSC_COEFF2_C4_MASK) +#define LCDIF_CSC_COEFF2_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF2_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD1_MASK) + +/*! @name CSC_COEFF3 - RGB to YCbCr 4:2:2 CSC Coefficient3 Register */ +#define LCDIF_CSC_COEFF3_C5_MASK (0x3FFU) +#define LCDIF_CSC_COEFF3_C5_SHIFT (0U) +#define LCDIF_CSC_COEFF3_C5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C5_SHIFT)) & LCDIF_CSC_COEFF3_C5_MASK) +#define LCDIF_CSC_COEFF3_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF3_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD0_MASK) +#define LCDIF_CSC_COEFF3_C6_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF3_C6_SHIFT (16U) +#define LCDIF_CSC_COEFF3_C6(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C6_SHIFT)) & LCDIF_CSC_COEFF3_C6_MASK) +#define LCDIF_CSC_COEFF3_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF3_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF3_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD1_MASK) + +/*! @name CSC_COEFF4 - RGB to YCbCr 4:2:2 CSC Coefficient4 Register */ +#define LCDIF_CSC_COEFF4_C7_MASK (0x3FFU) +#define LCDIF_CSC_COEFF4_C7_SHIFT (0U) +#define LCDIF_CSC_COEFF4_C7(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C7_SHIFT)) & LCDIF_CSC_COEFF4_C7_MASK) +#define LCDIF_CSC_COEFF4_RSRVD0_MASK (0xFC00U) +#define LCDIF_CSC_COEFF4_RSRVD0_SHIFT (10U) +#define LCDIF_CSC_COEFF4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD0_MASK) +#define LCDIF_CSC_COEFF4_C8_MASK (0x3FF0000U) +#define LCDIF_CSC_COEFF4_C8_SHIFT (16U) +#define LCDIF_CSC_COEFF4_C8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C8_SHIFT)) & LCDIF_CSC_COEFF4_C8_MASK) +#define LCDIF_CSC_COEFF4_RSRVD1_MASK (0xFC000000U) +#define LCDIF_CSC_COEFF4_RSRVD1_SHIFT (26U) +#define LCDIF_CSC_COEFF4_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD1_MASK) + +/*! @name CSC_OFFSET - RGB to YCbCr 4:2:2 CSC Offset Register */ +#define LCDIF_CSC_OFFSET_Y_OFFSET_MASK (0x1FFU) +#define LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT (0U) +#define LCDIF_CSC_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_Y_OFFSET_MASK) +#define LCDIF_CSC_OFFSET_RSRVD0_MASK (0xFE00U) +#define LCDIF_CSC_OFFSET_RSRVD0_SHIFT (9U) +#define LCDIF_CSC_OFFSET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD0_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD0_MASK) +#define LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK (0x1FF0000U) +#define LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT (16U) +#define LCDIF_CSC_OFFSET_CBCR_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK) +#define LCDIF_CSC_OFFSET_RSRVD1_MASK (0xFE000000U) +#define LCDIF_CSC_OFFSET_RSRVD1_SHIFT (25U) +#define LCDIF_CSC_OFFSET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD1_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD1_MASK) + +/*! @name CSC_LIMIT - RGB to YCbCr 4:2:2 CSC Limit Register */ +#define LCDIF_CSC_LIMIT_Y_MAX_MASK (0xFFU) +#define LCDIF_CSC_LIMIT_Y_MAX_SHIFT (0U) +#define LCDIF_CSC_LIMIT_Y_MAX(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MAX_SHIFT)) & LCDIF_CSC_LIMIT_Y_MAX_MASK) +#define LCDIF_CSC_LIMIT_Y_MIN_MASK (0xFF00U) +#define LCDIF_CSC_LIMIT_Y_MIN_SHIFT (8U) +#define LCDIF_CSC_LIMIT_Y_MIN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MIN_SHIFT)) & LCDIF_CSC_LIMIT_Y_MIN_MASK) +#define LCDIF_CSC_LIMIT_CBCR_MAX_MASK (0xFF0000U) +#define LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT (16U) +#define LCDIF_CSC_LIMIT_CBCR_MAX(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MAX_MASK) +#define LCDIF_CSC_LIMIT_CBCR_MIN_MASK (0xFF000000U) +#define LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT (24U) +#define LCDIF_CSC_LIMIT_CBCR_MIN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MIN_MASK) + +/*! @name DATA - LCD Interface Data Register */ +#define LCDIF_DATA_DATA_ZERO_MASK (0xFFU) +#define LCDIF_DATA_DATA_ZERO_SHIFT (0U) +#define LCDIF_DATA_DATA_ZERO(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ZERO_SHIFT)) & LCDIF_DATA_DATA_ZERO_MASK) +#define LCDIF_DATA_DATA_ONE_MASK (0xFF00U) +#define LCDIF_DATA_DATA_ONE_SHIFT (8U) +#define LCDIF_DATA_DATA_ONE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ONE_SHIFT)) & LCDIF_DATA_DATA_ONE_MASK) +#define LCDIF_DATA_DATA_TWO_MASK (0xFF0000U) +#define LCDIF_DATA_DATA_TWO_SHIFT (16U) +#define LCDIF_DATA_DATA_TWO(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_TWO_SHIFT)) & LCDIF_DATA_DATA_TWO_MASK) +#define LCDIF_DATA_DATA_THREE_MASK (0xFF000000U) +#define LCDIF_DATA_DATA_THREE_SHIFT (24U) +#define LCDIF_DATA_DATA_THREE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_THREE_SHIFT)) & LCDIF_DATA_DATA_THREE_MASK) + +/*! @name BM_ERROR_STAT - Bus Master Error Status Register */ +#define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) +#define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) + +/*! @name CRC_STAT - CRC Status Register */ +#define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU) +#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) +#define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) + +/*! @name STAT - LCD Interface Status Register */ +#define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU) +#define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) +#define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) +#define LCDIF_STAT_RSRVD0_MASK (0xFFFE00U) +#define LCDIF_STAT_RSRVD0_SHIFT (9U) +#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK) +#define LCDIF_STAT_DVI_CURRENT_FIELD_MASK (0x1000000U) +#define LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT (24U) +#define LCDIF_STAT_DVI_CURRENT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT)) & LCDIF_STAT_DVI_CURRENT_FIELD_MASK) +#define LCDIF_STAT_BUSY_MASK (0x2000000U) +#define LCDIF_STAT_BUSY_SHIFT (25U) +#define LCDIF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_BUSY_SHIFT)) & LCDIF_STAT_BUSY_MASK) +#define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U) +#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U) +#define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK) +#define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U) +#define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U) +#define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK) +#define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U) +#define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U) +#define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK) +#define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U) +#define LCDIF_STAT_LFIFO_FULL_SHIFT (29U) +#define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK) +#define LCDIF_STAT_PRESENT_MASK (0x80000000U) +#define LCDIF_STAT_PRESENT_SHIFT (31U) +#define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) + +/*! @name THRES - eLCDIF Threshold Register */ +#define LCDIF_THRES_PANIC_MASK (0x1FFU) +#define LCDIF_THRES_PANIC_SHIFT (0U) +#define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK) +#define LCDIF_THRES_RSRVD1_MASK (0xFE00U) +#define LCDIF_THRES_RSRVD1_SHIFT (9U) +#define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK) +#define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U) +#define LCDIF_THRES_FASTCLOCK_SHIFT (16U) +#define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK) +#define LCDIF_THRES_RSRVD2_MASK (0xFE000000U) +#define LCDIF_THRES_RSRVD2_SHIFT (25U) +#define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK) + +/*! @name AS_CTRL - eLCDIF AS Buffer Control Register */ +#define LCDIF_AS_CTRL_AS_ENABLE_MASK (0x1U) +#define LCDIF_AS_CTRL_AS_ENABLE_SHIFT (0U) +#define LCDIF_AS_CTRL_AS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_AS_ENABLE_SHIFT)) & LCDIF_AS_CTRL_AS_ENABLE_MASK) +#define LCDIF_AS_CTRL_ALPHA_CTRL_MASK (0x6U) +#define LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT (1U) +#define LCDIF_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT)) & LCDIF_AS_CTRL_ALPHA_CTRL_MASK) +#define LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) +#define LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) +#define LCDIF_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK) +#define LCDIF_AS_CTRL_FORMAT_MASK (0xF0U) +#define LCDIF_AS_CTRL_FORMAT_SHIFT (4U) +#define LCDIF_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_FORMAT_SHIFT)) & LCDIF_AS_CTRL_FORMAT_MASK) +#define LCDIF_AS_CTRL_ALPHA_MASK (0xFF00U) +#define LCDIF_AS_CTRL_ALPHA_SHIFT (8U) +#define LCDIF_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_SHIFT)) & LCDIF_AS_CTRL_ALPHA_MASK) +#define LCDIF_AS_CTRL_ROP_MASK (0xF0000U) +#define LCDIF_AS_CTRL_ROP_SHIFT (16U) +#define LCDIF_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ROP_SHIFT)) & LCDIF_AS_CTRL_ROP_MASK) +#define LCDIF_AS_CTRL_ALPHA_INVERT_MASK (0x100000U) +#define LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT (20U) +#define LCDIF_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT)) & LCDIF_AS_CTRL_ALPHA_INVERT_MASK) +#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK (0x600000U) +#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT (21U) +#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK) +#define LCDIF_AS_CTRL_PS_DISABLE_MASK (0x800000U) +#define LCDIF_AS_CTRL_PS_DISABLE_SHIFT (23U) +#define LCDIF_AS_CTRL_PS_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_PS_DISABLE_SHIFT)) & LCDIF_AS_CTRL_PS_DISABLE_MASK) +#define LCDIF_AS_CTRL_RVDS1_MASK (0x7000000U) +#define LCDIF_AS_CTRL_RVDS1_SHIFT (24U) +#define LCDIF_AS_CTRL_RVDS1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_RVDS1_SHIFT)) & LCDIF_AS_CTRL_RVDS1_MASK) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK (0x8000000U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT (27U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK (0x10000000U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT (28U) +#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK) +#define LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK (0x20000000U) +#define LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT (29U) +#define LCDIF_AS_CTRL_CSI_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK) +#define LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK (0x40000000U) +#define LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT (30U) +#define LCDIF_AS_CTRL_CSI_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK) +#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK (0x80000000U) +#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT (31U) +#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK) + +/*! @name AS_BUF - Alpha Surface Buffer Pointer */ +#define LCDIF_AS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_AS_BUF_ADDR_SHIFT (0U) +#define LCDIF_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_BUF_ADDR_SHIFT)) & LCDIF_AS_BUF_ADDR_MASK) + +/*! @name AS_NEXT_BUF - */ +#define LCDIF_AS_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define LCDIF_AS_NEXT_BUF_ADDR_SHIFT (0U) +#define LCDIF_AS_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_NEXT_BUF_ADDR_SHIFT)) & LCDIF_AS_NEXT_BUF_ADDR_MASK) + +/*! @name AS_CLRKEYLOW - eLCDIF Overlay Color Key Low */ +#define LCDIF_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) +#define LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT (0U) +#define LCDIF_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYLOW_PIXEL_MASK) +#define LCDIF_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) +#define LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT (24U) +#define LCDIF_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYLOW_RSVD1_MASK) + +/*! @name AS_CLRKEYHIGH - eLCDIF Overlay Color Key High */ +#define LCDIF_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) +#define LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT (0U) +#define LCDIF_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYHIGH_PIXEL_MASK) +#define LCDIF_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) +#define LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT (24U) +#define LCDIF_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYHIGH_RSVD1_MASK) + +/*! @name SYNC_DELAY - LCD working insync mode with CSI for VSYNC delay */ +#define LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK (0xFFFFU) +#define LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT (0U) +#define LCDIF_SYNC_DELAY_H_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK) +#define LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK (0xFFFF0000U) +#define LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT (16U) +#define LCDIF_SYNC_DELAY_V_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK) + + +/*! + * @} + */ /* end of group LCDIF_Register_Masks */ + + +/* LCDIF - Peripheral instance base addresses */ +/** Peripheral LCDIF base address */ +#define LCDIF_BASE (0x21C8000u) +/** Peripheral LCDIF base pointer */ +#define LCDIF ((LCDIF_Type *)LCDIF_BASE) +/** Array initializer of LCDIF peripheral base addresses */ +#define LCDIF_BASE_ADDRS { LCDIF_BASE } +/** Array initializer of LCDIF peripheral base pointers */ +#define LCDIF_BASE_PTRS { LCDIF } + +/*! + * @} + */ /* end of group LCDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MMDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MMDC_Peripheral_Access_Layer MMDC Peripheral Access Layer + * @{ + */ + +/** MMDC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MDCTL; /**< MMDC Core Control Register, offset: 0x0 */ + __IO uint32_t MDPDC; /**< MMDC Core Power Down Control Register, offset: 0x4 */ + __IO uint32_t MDOTC; /**< MMDC Core ODT Timing Control Register, offset: 0x8 */ + __IO uint32_t MDCFG0; /**< MMDC Core Timing Configuration Register 0, offset: 0xC */ + __IO uint32_t MDCFG1; /**< MMDC Core Timing Configuration Register 1, offset: 0x10 */ + __IO uint32_t MDCFG2; /**< MMDC Core Timing Configuration Register 2, offset: 0x14 */ + __IO uint32_t MDMISC; /**< MMDC Core Miscellaneous Register, offset: 0x18 */ + __IO uint32_t MDSCR; /**< MMDC Core Special Command Register, offset: 0x1C */ + __IO uint32_t MDREF; /**< MMDC Core Refresh Control Register, offset: 0x20 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MDRWD; /**< MMDC Core Read/Write Command Delay Register, offset: 0x2C */ + __IO uint32_t MDOR; /**< MMDC Core Out of Reset Delays Register, offset: 0x30 */ + __I uint32_t MDMRR; /**< MMDC Core MRR Data Register, offset: 0x34 */ + __IO uint32_t MDCFG3LP; /**< MMDC Core Timing Configuration Register 3, offset: 0x38 */ + __IO uint32_t MDMR4; /**< MMDC Core MR4 Derating Register, offset: 0x3C */ + __IO uint32_t MDASP; /**< MMDC Core Address Space Partition Register, offset: 0x40 */ + uint8_t RESERVED_1[956]; + __IO uint32_t MAARCR; /**< MMDC Core AXI Reordering Control Register, offset: 0x400 */ + __IO uint32_t MAPSR; /**< MMDC Core Power Saving Control and Status Register, offset: 0x404 */ + __IO uint32_t MAEXIDR0; /**< MMDC Core Exclusive ID Monitor Register0, offset: 0x408 */ + __IO uint32_t MAEXIDR1; /**< MMDC Core Exclusive ID Monitor Register1, offset: 0x40C */ + __IO uint32_t MADPCR0; /**< MMDC Core Debug and Profiling Control Register 0, offset: 0x410 */ + __IO uint32_t MADPCR1; /**< MMDC Core Debug and Profiling Control Register 1, offset: 0x414 */ + __I uint32_t MADPSR0; /**< MMDC Core Debug and Profiling Status Register 0, offset: 0x418 */ + __I uint32_t MADPSR1; /**< MMDC Core Debug and Profiling Status Register 1, offset: 0x41C */ + __I uint32_t MADPSR2; /**< MMDC Core Debug and Profiling Status Register 2, offset: 0x420 */ + __I uint32_t MADPSR3; /**< MMDC Core Debug and Profiling Status Register 3, offset: 0x424 */ + __I uint32_t MADPSR4; /**< MMDC Core Debug and Profiling Status Register 4, offset: 0x428 */ + __I uint32_t MADPSR5; /**< MMDC Core Debug and Profiling Status Register 5, offset: 0x42C */ + __I uint32_t MASBS0; /**< MMDC Core Step By Step Address Register, offset: 0x430 */ + __I uint32_t MASBS1; /**< MMDC Core Step By Step Address Attributes Register, offset: 0x434 */ + uint8_t RESERVED_2[8]; + __IO uint32_t MAGENP; /**< MMDC Core General Purpose Register, offset: 0x440 */ + uint8_t RESERVED_3[956]; + __IO uint32_t MPZQHWCTRL; /**< MMDC PHY ZQ HW control register, offset: 0x800 */ + __IO uint32_t MPZQSWCTRL; /**< MMDC PHY ZQ SW control register, offset: 0x804 */ + __IO uint32_t MPWLGCR; /**< MMDC PHY Write Leveling Configuration and Error Status Register, offset: 0x808 */ + __IO uint32_t MPWLDECTRL0; /**< MMDC PHY Write Leveling Delay Control Register 0, offset: 0x80C */ + __IO uint32_t MPWLDECTRL1; /**< MMDC PHY Write Leveling Delay Control Register 1, offset: 0x810 */ + __I uint32_t MPWLDLST; /**< MMDC PHY Write Leveling delay-line Status Register, offset: 0x814 */ + __IO uint32_t MPODTCTRL; /**< MMDC PHY ODT control register, offset: 0x818 */ + __IO uint32_t MPRDDQBY0DL; /**< MMDC PHY Read DQ Byte0 Delay Register, offset: 0x81C */ + __IO uint32_t MPRDDQBY1DL; /**< MMDC PHY Read DQ Byte1 Delay Register, offset: 0x820 */ + uint8_t RESERVED_4[8]; + __IO uint32_t MPWRDQBY0DL; /**< MMDC PHY Write DQ Byte0 Delay Register, offset: 0x82C */ + __IO uint32_t MPWRDQBY1DL; /**< MMDC PHY Write DQ Byte1 Delay Register, offset: 0x830 */ + __IO uint32_t MPWRDQBY2DL; /**< MMDC PHY Write DQ Byte2 Delay Register, offset: 0x834 */ + __IO uint32_t MPWRDQBY3DL; /**< MMDC PHY Write DQ Byte3 Delay Register, offset: 0x838 */ + __IO uint32_t MPDGCTRL0; /**< MMDC PHY Read DQS Gating Control Register 0, offset: 0x83C */ + uint8_t RESERVED_5[4]; + __I uint32_t MPDGDLST0; /**< MMDC PHY Read DQS Gating delay-line Status Register, offset: 0x844 */ + __IO uint32_t MPRDDLCTL; /**< MMDC PHY Read delay-lines Configuration Register, offset: 0x848 */ + __I uint32_t MPRDDLST; /**< MMDC PHY Read delay-lines Status Register, offset: 0x84C */ + __IO uint32_t MPWRDLCTL; /**< MMDC PHY Write delay-lines Configuration Register, offset: 0x850 */ + __I uint32_t MPWRDLST; /**< MMDC PHY Write delay-lines Status Register, offset: 0x854 */ + __IO uint32_t MPSDCTRL; /**< MMDC PHY CK Control Register, offset: 0x858 */ + __IO uint32_t MPZQLP2CTL; /**< MMDC ZQ LPDDR2 HW Control Register, offset: 0x85C */ + __IO uint32_t MPRDDLHWCTL; /**< MMDC PHY Read Delay HW Calibration Control Register, offset: 0x860 */ + __IO uint32_t MPWRDLHWCTL; /**< MMDC PHY Write Delay HW Calibration Control Register, offset: 0x864 */ + __I uint32_t MPRDDLHWST0; /**< MMDC PHY Read Delay HW Calibration Status Register 0, offset: 0x868 */ + uint8_t RESERVED_6[4]; + __I uint32_t MPWRDLHWST0; /**< MMDC PHY Write Delay HW Calibration Status Register 0, offset: 0x870 */ + uint8_t RESERVED_7[4]; + __I uint32_t MPWLHWERR; /**< MMDC PHY Write Leveling HW Error Register, offset: 0x878 */ + __I uint32_t MPDGHWST0; /**< MMDC PHY Read DQS Gating HW Status Register 0, offset: 0x87C */ + __I uint32_t MPDGHWST1; /**< MMDC PHY Read DQS Gating HW Status Register 1, offset: 0x880 */ + uint8_t RESERVED_8[8]; + __IO uint32_t MPPDCMPR1; /**< MMDC PHY Pre-defined Compare Register 1, offset: 0x88C */ + __IO uint32_t MPPDCMPR2; /**< MMDC PHY Pre-defined Compare and CA delay-line Configuration Register, offset: 0x890 */ + __IO uint32_t MPSWDAR0; /**< MMDC PHY SW Dummy Access Register, offset: 0x894 */ + __I uint32_t MPSWDRDR0; /**< MMDC PHY SW Dummy Read Data Register 0, offset: 0x898 */ + __I uint32_t MPSWDRDR1; /**< MMDC PHY SW Dummy Read Data Register 1, offset: 0x89C */ + __I uint32_t MPSWDRDR2; /**< MMDC PHY SW Dummy Read Data Register 2, offset: 0x8A0 */ + __I uint32_t MPSWDRDR3; /**< MMDC PHY SW Dummy Read Data Register 3, offset: 0x8A4 */ + __I uint32_t MPSWDRDR4; /**< MMDC PHY SW Dummy Read Data Register 4, offset: 0x8A8 */ + __I uint32_t MPSWDRDR5; /**< MMDC PHY SW Dummy Read Data Register 5, offset: 0x8AC */ + __I uint32_t MPSWDRDR6; /**< MMDC PHY SW Dummy Read Data Register 6, offset: 0x8B0 */ + __I uint32_t MPSWDRDR7; /**< MMDC PHY SW Dummy Read Data Register 7, offset: 0x8B4 */ + __IO uint32_t MPMUR0; /**< MMDC PHY Measure Unit Register, offset: 0x8B8 */ + __IO uint32_t MPWRCADL; /**< MMDC Write CA delay-line controller, offset: 0x8BC */ + __IO uint32_t MPDCCR; /**< MMDC Duty Cycle Control Register, offset: 0x8C0 */ +} MMDC_Type; + +/* ---------------------------------------------------------------------------- + -- MMDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MMDC_Register_Masks MMDC Register Masks + * @{ + */ + +/*! @name MDCTL - MMDC Core Control Register */ +#define MMDC_MDCTL_DSIZ_MASK (0x30000U) +#define MMDC_MDCTL_DSIZ_SHIFT (16U) +#define MMDC_MDCTL_DSIZ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_DSIZ_SHIFT)) & MMDC_MDCTL_DSIZ_MASK) +#define MMDC_MDCTL_BL_MASK (0x80000U) +#define MMDC_MDCTL_BL_SHIFT (19U) +#define MMDC_MDCTL_BL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_BL_SHIFT)) & MMDC_MDCTL_BL_MASK) +#define MMDC_MDCTL_COL_MASK (0x700000U) +#define MMDC_MDCTL_COL_SHIFT (20U) +#define MMDC_MDCTL_COL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_COL_SHIFT)) & MMDC_MDCTL_COL_MASK) +#define MMDC_MDCTL_ROW_MASK (0x7000000U) +#define MMDC_MDCTL_ROW_SHIFT (24U) +#define MMDC_MDCTL_ROW(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_ROW_SHIFT)) & MMDC_MDCTL_ROW_MASK) +#define MMDC_MDCTL_SDE_1_MASK (0x40000000U) +#define MMDC_MDCTL_SDE_1_SHIFT (30U) +#define MMDC_MDCTL_SDE_1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_SDE_1_SHIFT)) & MMDC_MDCTL_SDE_1_MASK) +#define MMDC_MDCTL_SDE_0_MASK (0x80000000U) +#define MMDC_MDCTL_SDE_0_SHIFT (31U) +#define MMDC_MDCTL_SDE_0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCTL_SDE_0_SHIFT)) & MMDC_MDCTL_SDE_0_MASK) + +/*! @name MDPDC - MMDC Core Power Down Control Register */ +#define MMDC_MDPDC_TCKSRE_MASK (0x7U) +#define MMDC_MDPDC_TCKSRE_SHIFT (0U) +#define MMDC_MDPDC_TCKSRE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_TCKSRE_SHIFT)) & MMDC_MDPDC_TCKSRE_MASK) +#define MMDC_MDPDC_TCKSRX_MASK (0x38U) +#define MMDC_MDPDC_TCKSRX_SHIFT (3U) +#define MMDC_MDPDC_TCKSRX(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_TCKSRX_SHIFT)) & MMDC_MDPDC_TCKSRX_MASK) +#define MMDC_MDPDC_BOTH_CS_PD_MASK (0x40U) +#define MMDC_MDPDC_BOTH_CS_PD_SHIFT (6U) +#define MMDC_MDPDC_BOTH_CS_PD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_BOTH_CS_PD_SHIFT)) & MMDC_MDPDC_BOTH_CS_PD_MASK) +#define MMDC_MDPDC_SLOW_PD_MASK (0x80U) +#define MMDC_MDPDC_SLOW_PD_SHIFT (7U) +#define MMDC_MDPDC_SLOW_PD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_SLOW_PD_SHIFT)) & MMDC_MDPDC_SLOW_PD_MASK) +#define MMDC_MDPDC_PWDT_0_MASK (0xF00U) +#define MMDC_MDPDC_PWDT_0_SHIFT (8U) +#define MMDC_MDPDC_PWDT_0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PWDT_0_SHIFT)) & MMDC_MDPDC_PWDT_0_MASK) +#define MMDC_MDPDC_PWDT_1_MASK (0xF000U) +#define MMDC_MDPDC_PWDT_1_SHIFT (12U) +#define MMDC_MDPDC_PWDT_1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PWDT_1_SHIFT)) & MMDC_MDPDC_PWDT_1_MASK) +#define MMDC_MDPDC_TCKE_MASK (0x70000U) +#define MMDC_MDPDC_TCKE_SHIFT (16U) +#define MMDC_MDPDC_TCKE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_TCKE_SHIFT)) & MMDC_MDPDC_TCKE_MASK) +#define MMDC_MDPDC_PRCT_0_MASK (0x7000000U) +#define MMDC_MDPDC_PRCT_0_SHIFT (24U) +#define MMDC_MDPDC_PRCT_0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PRCT_0_SHIFT)) & MMDC_MDPDC_PRCT_0_MASK) +#define MMDC_MDPDC_PRCT_1_MASK (0x70000000U) +#define MMDC_MDPDC_PRCT_1_SHIFT (28U) +#define MMDC_MDPDC_PRCT_1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDPDC_PRCT_1_SHIFT)) & MMDC_MDPDC_PRCT_1_MASK) + +/*! @name MDOTC - MMDC Core ODT Timing Control Register */ +#define MMDC_MDOTC_TODT_IDLE_OFF_MASK (0x1F0U) +#define MMDC_MDOTC_TODT_IDLE_OFF_SHIFT (4U) +#define MMDC_MDOTC_TODT_IDLE_OFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TODT_IDLE_OFF_SHIFT)) & MMDC_MDOTC_TODT_IDLE_OFF_MASK) +#define MMDC_MDOTC_TODTLON_MASK (0x7000U) +#define MMDC_MDOTC_TODTLON_SHIFT (12U) +#define MMDC_MDOTC_TODTLON(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TODTLON_SHIFT)) & MMDC_MDOTC_TODTLON_MASK) +#define MMDC_MDOTC_TAXPD_MASK (0xF0000U) +#define MMDC_MDOTC_TAXPD_SHIFT (16U) +#define MMDC_MDOTC_TAXPD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TAXPD_SHIFT)) & MMDC_MDOTC_TAXPD_MASK) +#define MMDC_MDOTC_TANPD_MASK (0xF00000U) +#define MMDC_MDOTC_TANPD_SHIFT (20U) +#define MMDC_MDOTC_TANPD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TANPD_SHIFT)) & MMDC_MDOTC_TANPD_MASK) +#define MMDC_MDOTC_TAONPD_MASK (0x7000000U) +#define MMDC_MDOTC_TAONPD_SHIFT (24U) +#define MMDC_MDOTC_TAONPD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TAONPD_SHIFT)) & MMDC_MDOTC_TAONPD_MASK) +#define MMDC_MDOTC_TAOFPD_MASK (0x38000000U) +#define MMDC_MDOTC_TAOFPD_SHIFT (27U) +#define MMDC_MDOTC_TAOFPD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOTC_TAOFPD_SHIFT)) & MMDC_MDOTC_TAOFPD_MASK) + +/*! @name MDCFG0 - MMDC Core Timing Configuration Register 0 */ +#define MMDC_MDCFG0_TCL_MASK (0xFU) +#define MMDC_MDCFG0_TCL_SHIFT (0U) +#define MMDC_MDCFG0_TCL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TCL_SHIFT)) & MMDC_MDCFG0_TCL_MASK) +#define MMDC_MDCFG0_TFAW_MASK (0x1F0U) +#define MMDC_MDCFG0_TFAW_SHIFT (4U) +#define MMDC_MDCFG0_TFAW(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TFAW_SHIFT)) & MMDC_MDCFG0_TFAW_MASK) +#define MMDC_MDCFG0_TXPDLL_MASK (0x1E00U) +#define MMDC_MDCFG0_TXPDLL_SHIFT (9U) +#define MMDC_MDCFG0_TXPDLL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TXPDLL_SHIFT)) & MMDC_MDCFG0_TXPDLL_MASK) +#define MMDC_MDCFG0_TXP_MASK (0xE000U) +#define MMDC_MDCFG0_TXP_SHIFT (13U) +#define MMDC_MDCFG0_TXP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TXP_SHIFT)) & MMDC_MDCFG0_TXP_MASK) +#define MMDC_MDCFG0_TXS_MASK (0xFF0000U) +#define MMDC_MDCFG0_TXS_SHIFT (16U) +#define MMDC_MDCFG0_TXS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TXS_SHIFT)) & MMDC_MDCFG0_TXS_MASK) +#define MMDC_MDCFG0_TRFC_MASK (0xFF000000U) +#define MMDC_MDCFG0_TRFC_SHIFT (24U) +#define MMDC_MDCFG0_TRFC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG0_TRFC_SHIFT)) & MMDC_MDCFG0_TRFC_MASK) + +/*! @name MDCFG1 - MMDC Core Timing Configuration Register 1 */ +#define MMDC_MDCFG1_TCWL_MASK (0x7U) +#define MMDC_MDCFG1_TCWL_SHIFT (0U) +#define MMDC_MDCFG1_TCWL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TCWL_SHIFT)) & MMDC_MDCFG1_TCWL_MASK) +#define MMDC_MDCFG1_TMRD_MASK (0x1E0U) +#define MMDC_MDCFG1_TMRD_SHIFT (5U) +#define MMDC_MDCFG1_TMRD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TMRD_SHIFT)) & MMDC_MDCFG1_TMRD_MASK) +#define MMDC_MDCFG1_TWR_MASK (0xE00U) +#define MMDC_MDCFG1_TWR_SHIFT (9U) +#define MMDC_MDCFG1_TWR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TWR_SHIFT)) & MMDC_MDCFG1_TWR_MASK) +#define MMDC_MDCFG1_TRPA_MASK (0x8000U) +#define MMDC_MDCFG1_TRPA_SHIFT (15U) +#define MMDC_MDCFG1_TRPA(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRPA_SHIFT)) & MMDC_MDCFG1_TRPA_MASK) +#define MMDC_MDCFG1_TRAS_MASK (0x1F0000U) +#define MMDC_MDCFG1_TRAS_SHIFT (16U) +#define MMDC_MDCFG1_TRAS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRAS_SHIFT)) & MMDC_MDCFG1_TRAS_MASK) +#define MMDC_MDCFG1_TRC_MASK (0x3E00000U) +#define MMDC_MDCFG1_TRC_SHIFT (21U) +#define MMDC_MDCFG1_TRC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRC_SHIFT)) & MMDC_MDCFG1_TRC_MASK) +#define MMDC_MDCFG1_TRP_MASK (0x1C000000U) +#define MMDC_MDCFG1_TRP_SHIFT (26U) +#define MMDC_MDCFG1_TRP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRP_SHIFT)) & MMDC_MDCFG1_TRP_MASK) +#define MMDC_MDCFG1_TRCD_MASK (0xE0000000U) +#define MMDC_MDCFG1_TRCD_SHIFT (29U) +#define MMDC_MDCFG1_TRCD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG1_TRCD_SHIFT)) & MMDC_MDCFG1_TRCD_MASK) + +/*! @name MDCFG2 - MMDC Core Timing Configuration Register 2 */ +#define MMDC_MDCFG2_TRRD_MASK (0x7U) +#define MMDC_MDCFG2_TRRD_SHIFT (0U) +#define MMDC_MDCFG2_TRRD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_TRRD_SHIFT)) & MMDC_MDCFG2_TRRD_MASK) +#define MMDC_MDCFG2_TWTR_MASK (0x38U) +#define MMDC_MDCFG2_TWTR_SHIFT (3U) +#define MMDC_MDCFG2_TWTR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_TWTR_SHIFT)) & MMDC_MDCFG2_TWTR_MASK) +#define MMDC_MDCFG2_TRTP_MASK (0x1C0U) +#define MMDC_MDCFG2_TRTP_SHIFT (6U) +#define MMDC_MDCFG2_TRTP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_TRTP_SHIFT)) & MMDC_MDCFG2_TRTP_MASK) +#define MMDC_MDCFG2_TDLLK_MASK (0x1FF0000U) +#define MMDC_MDCFG2_TDLLK_SHIFT (16U) +#define MMDC_MDCFG2_TDLLK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG2_TDLLK_SHIFT)) & MMDC_MDCFG2_TDLLK_MASK) + +/*! @name MDMISC - MMDC Core Miscellaneous Register */ +#define MMDC_MDMISC_RST_MASK (0x2U) +#define MMDC_MDMISC_RST_SHIFT (1U) +#define MMDC_MDMISC_RST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_RST_SHIFT)) & MMDC_MDMISC_RST_MASK) +#define MMDC_MDMISC_DDR_TYPE_MASK (0x18U) +#define MMDC_MDMISC_DDR_TYPE_SHIFT (3U) +#define MMDC_MDMISC_DDR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_DDR_TYPE_SHIFT)) & MMDC_MDMISC_DDR_TYPE_MASK) +#define MMDC_MDMISC_DDR_4_BANK_MASK (0x20U) +#define MMDC_MDMISC_DDR_4_BANK_SHIFT (5U) +#define MMDC_MDMISC_DDR_4_BANK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_DDR_4_BANK_SHIFT)) & MMDC_MDMISC_DDR_4_BANK_MASK) +#define MMDC_MDMISC_RALAT_MASK (0x1C0U) +#define MMDC_MDMISC_RALAT_SHIFT (6U) +#define MMDC_MDMISC_RALAT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_RALAT_SHIFT)) & MMDC_MDMISC_RALAT_MASK) +#define MMDC_MDMISC_MIF3_MODE_MASK (0x600U) +#define MMDC_MDMISC_MIF3_MODE_SHIFT (9U) +#define MMDC_MDMISC_MIF3_MODE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_MIF3_MODE_SHIFT)) & MMDC_MDMISC_MIF3_MODE_MASK) +#define MMDC_MDMISC_LPDDR2_S2_MASK (0x800U) +#define MMDC_MDMISC_LPDDR2_S2_SHIFT (11U) +#define MMDC_MDMISC_LPDDR2_S2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_LPDDR2_S2_SHIFT)) & MMDC_MDMISC_LPDDR2_S2_MASK) +#define MMDC_MDMISC_BI_ON_MASK (0x1000U) +#define MMDC_MDMISC_BI_ON_SHIFT (12U) +#define MMDC_MDMISC_BI_ON(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_BI_ON_SHIFT)) & MMDC_MDMISC_BI_ON_MASK) +#define MMDC_MDMISC_WALAT_MASK (0x30000U) +#define MMDC_MDMISC_WALAT_SHIFT (16U) +#define MMDC_MDMISC_WALAT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_WALAT_SHIFT)) & MMDC_MDMISC_WALAT_MASK) +#define MMDC_MDMISC_LHD_MASK (0x40000U) +#define MMDC_MDMISC_LHD_SHIFT (18U) +#define MMDC_MDMISC_LHD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_LHD_SHIFT)) & MMDC_MDMISC_LHD_MASK) +#define MMDC_MDMISC_ADDR_MIRROR_MASK (0x80000U) +#define MMDC_MDMISC_ADDR_MIRROR_SHIFT (19U) +#define MMDC_MDMISC_ADDR_MIRROR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_ADDR_MIRROR_SHIFT)) & MMDC_MDMISC_ADDR_MIRROR_MASK) +#define MMDC_MDMISC_CALIB_PER_CS_MASK (0x100000U) +#define MMDC_MDMISC_CALIB_PER_CS_SHIFT (20U) +#define MMDC_MDMISC_CALIB_PER_CS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CALIB_PER_CS_SHIFT)) & MMDC_MDMISC_CALIB_PER_CS_MASK) +#define MMDC_MDMISC_CK1_GATING_MASK (0x200000U) +#define MMDC_MDMISC_CK1_GATING_SHIFT (21U) +#define MMDC_MDMISC_CK1_GATING(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CK1_GATING_SHIFT)) & MMDC_MDMISC_CK1_GATING_MASK) +#define MMDC_MDMISC_CS1_RDY_MASK (0x40000000U) +#define MMDC_MDMISC_CS1_RDY_SHIFT (30U) +#define MMDC_MDMISC_CS1_RDY(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CS1_RDY_SHIFT)) & MMDC_MDMISC_CS1_RDY_MASK) +#define MMDC_MDMISC_CS0_RDY_MASK (0x80000000U) +#define MMDC_MDMISC_CS0_RDY_SHIFT (31U) +#define MMDC_MDMISC_CS0_RDY(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMISC_CS0_RDY_SHIFT)) & MMDC_MDMISC_CS0_RDY_MASK) + +/*! @name MDSCR - MMDC Core Special Command Register */ +#define MMDC_MDSCR_CMD_BA_MASK (0x7U) +#define MMDC_MDSCR_CMD_BA_SHIFT (0U) +#define MMDC_MDSCR_CMD_BA(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_BA_SHIFT)) & MMDC_MDSCR_CMD_BA_MASK) +#define MMDC_MDSCR_CMD_CS_MASK (0x8U) +#define MMDC_MDSCR_CMD_CS_SHIFT (3U) +#define MMDC_MDSCR_CMD_CS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_CS_SHIFT)) & MMDC_MDSCR_CMD_CS_MASK) +#define MMDC_MDSCR_CMD_MASK (0x70U) +#define MMDC_MDSCR_CMD_SHIFT (4U) +#define MMDC_MDSCR_CMD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_SHIFT)) & MMDC_MDSCR_CMD_MASK) +#define MMDC_MDSCR_WL_EN_MASK (0x200U) +#define MMDC_MDSCR_WL_EN_SHIFT (9U) +#define MMDC_MDSCR_WL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_WL_EN_SHIFT)) & MMDC_MDSCR_WL_EN_MASK) +#define MMDC_MDSCR_MRR_READ_DATA_VALID_MASK (0x400U) +#define MMDC_MDSCR_MRR_READ_DATA_VALID_SHIFT (10U) +#define MMDC_MDSCR_MRR_READ_DATA_VALID(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_MRR_READ_DATA_VALID_SHIFT)) & MMDC_MDSCR_MRR_READ_DATA_VALID_MASK) +#define MMDC_MDSCR_CON_ACK_MASK (0x4000U) +#define MMDC_MDSCR_CON_ACK_SHIFT (14U) +#define MMDC_MDSCR_CON_ACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CON_ACK_SHIFT)) & MMDC_MDSCR_CON_ACK_MASK) +#define MMDC_MDSCR_CON_REQ_MASK (0x8000U) +#define MMDC_MDSCR_CON_REQ_SHIFT (15U) +#define MMDC_MDSCR_CON_REQ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CON_REQ_SHIFT)) & MMDC_MDSCR_CON_REQ_MASK) +#define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_MASK (0xFF0000U) +#define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_SHIFT (16U) +#define MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_SHIFT)) & MMDC_MDSCR_CMD_ADDR_LSB_MR_ADDR_MASK) +#define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_MASK (0xFF000000U) +#define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_SHIFT (24U) +#define MMDC_MDSCR_CMD_ADDR_MSB_MR_OP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_SHIFT)) & MMDC_MDSCR_CMD_ADDR_MSB_MR_OP_MASK) + +/*! @name MDREF - MMDC Core Refresh Control Register */ +#define MMDC_MDREF_START_REF_MASK (0x1U) +#define MMDC_MDREF_START_REF_SHIFT (0U) +#define MMDC_MDREF_START_REF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_START_REF_SHIFT)) & MMDC_MDREF_START_REF_MASK) +#define MMDC_MDREF_REFR_MASK (0x3800U) +#define MMDC_MDREF_REFR_SHIFT (11U) +#define MMDC_MDREF_REFR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_REFR_SHIFT)) & MMDC_MDREF_REFR_MASK) +#define MMDC_MDREF_REF_SEL_MASK (0xC000U) +#define MMDC_MDREF_REF_SEL_SHIFT (14U) +#define MMDC_MDREF_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_REF_SEL_SHIFT)) & MMDC_MDREF_REF_SEL_MASK) +#define MMDC_MDREF_REF_CNT_MASK (0xFFFF0000U) +#define MMDC_MDREF_REF_CNT_SHIFT (16U) +#define MMDC_MDREF_REF_CNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDREF_REF_CNT_SHIFT)) & MMDC_MDREF_REF_CNT_MASK) + +/*! @name MDRWD - MMDC Core Read/Write Command Delay Register */ +#define MMDC_MDRWD_RTR_DIFF_MASK (0x7U) +#define MMDC_MDRWD_RTR_DIFF_SHIFT (0U) +#define MMDC_MDRWD_RTR_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_RTR_DIFF_SHIFT)) & MMDC_MDRWD_RTR_DIFF_MASK) +#define MMDC_MDRWD_RTW_DIFF_MASK (0x38U) +#define MMDC_MDRWD_RTW_DIFF_SHIFT (3U) +#define MMDC_MDRWD_RTW_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_RTW_DIFF_SHIFT)) & MMDC_MDRWD_RTW_DIFF_MASK) +#define MMDC_MDRWD_WTW_DIFF_MASK (0x1C0U) +#define MMDC_MDRWD_WTW_DIFF_SHIFT (6U) +#define MMDC_MDRWD_WTW_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_WTW_DIFF_SHIFT)) & MMDC_MDRWD_WTW_DIFF_MASK) +#define MMDC_MDRWD_WTR_DIFF_MASK (0xE00U) +#define MMDC_MDRWD_WTR_DIFF_SHIFT (9U) +#define MMDC_MDRWD_WTR_DIFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_WTR_DIFF_SHIFT)) & MMDC_MDRWD_WTR_DIFF_MASK) +#define MMDC_MDRWD_RTW_SAME_MASK (0x7000U) +#define MMDC_MDRWD_RTW_SAME_SHIFT (12U) +#define MMDC_MDRWD_RTW_SAME(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_RTW_SAME_SHIFT)) & MMDC_MDRWD_RTW_SAME_MASK) +#define MMDC_MDRWD_TDAI_MASK (0x1FFF0000U) +#define MMDC_MDRWD_TDAI_SHIFT (16U) +#define MMDC_MDRWD_TDAI(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDRWD_TDAI_SHIFT)) & MMDC_MDRWD_TDAI_MASK) + +/*! @name MDOR - MMDC Core Out of Reset Delays Register */ +#define MMDC_MDOR_RST_TO_CKE_MASK (0x3FU) +#define MMDC_MDOR_RST_TO_CKE_SHIFT (0U) +#define MMDC_MDOR_RST_TO_CKE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOR_RST_TO_CKE_SHIFT)) & MMDC_MDOR_RST_TO_CKE_MASK) +#define MMDC_MDOR_SDE_TO_RST_MASK (0x3F00U) +#define MMDC_MDOR_SDE_TO_RST_SHIFT (8U) +#define MMDC_MDOR_SDE_TO_RST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOR_SDE_TO_RST_SHIFT)) & MMDC_MDOR_SDE_TO_RST_MASK) +#define MMDC_MDOR_TXPR_MASK (0xFF0000U) +#define MMDC_MDOR_TXPR_SHIFT (16U) +#define MMDC_MDOR_TXPR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDOR_TXPR_SHIFT)) & MMDC_MDOR_TXPR_MASK) + +/*! @name MDMRR - MMDC Core MRR Data Register */ +#define MMDC_MDMRR_MRR_READ_DATA0_MASK (0xFFU) +#define MMDC_MDMRR_MRR_READ_DATA0_SHIFT (0U) +#define MMDC_MDMRR_MRR_READ_DATA0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMRR_MRR_READ_DATA0_SHIFT)) & MMDC_MDMRR_MRR_READ_DATA0_MASK) +#define MMDC_MDMRR_MRR_READ_DATA1_MASK (0xFF00U) +#define MMDC_MDMRR_MRR_READ_DATA1_SHIFT (8U) +#define MMDC_MDMRR_MRR_READ_DATA1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMRR_MRR_READ_DATA1_SHIFT)) & MMDC_MDMRR_MRR_READ_DATA1_MASK) + +/*! @name MDCFG3LP - MMDC Core Timing Configuration Register 3 */ +#define MMDC_MDCFG3LP_TRPAB_LP_MASK (0xFU) +#define MMDC_MDCFG3LP_TRPAB_LP_SHIFT (0U) +#define MMDC_MDCFG3LP_TRPAB_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_TRPAB_LP_SHIFT)) & MMDC_MDCFG3LP_TRPAB_LP_MASK) +#define MMDC_MDCFG3LP_TRPPB_LP_MASK (0xF0U) +#define MMDC_MDCFG3LP_TRPPB_LP_SHIFT (4U) +#define MMDC_MDCFG3LP_TRPPB_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_TRPPB_LP_SHIFT)) & MMDC_MDCFG3LP_TRPPB_LP_MASK) +#define MMDC_MDCFG3LP_TRCD_LP_MASK (0xF00U) +#define MMDC_MDCFG3LP_TRCD_LP_SHIFT (8U) +#define MMDC_MDCFG3LP_TRCD_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_TRCD_LP_SHIFT)) & MMDC_MDCFG3LP_TRCD_LP_MASK) +#define MMDC_MDCFG3LP_RC_LP_MASK (0x3F0000U) +#define MMDC_MDCFG3LP_RC_LP_SHIFT (16U) +#define MMDC_MDCFG3LP_RC_LP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDCFG3LP_RC_LP_SHIFT)) & MMDC_MDCFG3LP_RC_LP_MASK) + +/*! @name MDMR4 - MMDC Core MR4 Derating Register */ +#define MMDC_MDMR4_UPDATE_DE_REQ_MASK (0x1U) +#define MMDC_MDMR4_UPDATE_DE_REQ_SHIFT (0U) +#define MMDC_MDMR4_UPDATE_DE_REQ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_UPDATE_DE_REQ_SHIFT)) & MMDC_MDMR4_UPDATE_DE_REQ_MASK) +#define MMDC_MDMR4_UPDATE_DE_ACK_MASK (0x2U) +#define MMDC_MDMR4_UPDATE_DE_ACK_SHIFT (1U) +#define MMDC_MDMR4_UPDATE_DE_ACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_UPDATE_DE_ACK_SHIFT)) & MMDC_MDMR4_UPDATE_DE_ACK_MASK) +#define MMDC_MDMR4_TRCD_DE_MASK (0x10U) +#define MMDC_MDMR4_TRCD_DE_SHIFT (4U) +#define MMDC_MDMR4_TRCD_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRCD_DE_SHIFT)) & MMDC_MDMR4_TRCD_DE_MASK) +#define MMDC_MDMR4_TRC_DE_MASK (0x20U) +#define MMDC_MDMR4_TRC_DE_SHIFT (5U) +#define MMDC_MDMR4_TRC_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRC_DE_SHIFT)) & MMDC_MDMR4_TRC_DE_MASK) +#define MMDC_MDMR4_TRAS_DE_MASK (0x40U) +#define MMDC_MDMR4_TRAS_DE_SHIFT (6U) +#define MMDC_MDMR4_TRAS_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRAS_DE_SHIFT)) & MMDC_MDMR4_TRAS_DE_MASK) +#define MMDC_MDMR4_TRP_DE_MASK (0x80U) +#define MMDC_MDMR4_TRP_DE_SHIFT (7U) +#define MMDC_MDMR4_TRP_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRP_DE_SHIFT)) & MMDC_MDMR4_TRP_DE_MASK) +#define MMDC_MDMR4_TRRD_DE_MASK (0x100U) +#define MMDC_MDMR4_TRRD_DE_SHIFT (8U) +#define MMDC_MDMR4_TRRD_DE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDMR4_TRRD_DE_SHIFT)) & MMDC_MDMR4_TRRD_DE_MASK) + +/*! @name MDASP - MMDC Core Address Space Partition Register */ +#define MMDC_MDASP_CS0_END_MASK (0x7FU) +#define MMDC_MDASP_CS0_END_SHIFT (0U) +#define MMDC_MDASP_CS0_END(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MDASP_CS0_END_SHIFT)) & MMDC_MDASP_CS0_END_MASK) + +/*! @name MAARCR - MMDC Core AXI Reordering Control Register */ +#define MMDC_MAARCR_ARCR_GUARD_MASK (0xFU) +#define MMDC_MAARCR_ARCR_GUARD_SHIFT (0U) +#define MMDC_MAARCR_ARCR_GUARD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_GUARD_SHIFT)) & MMDC_MAARCR_ARCR_GUARD_MASK) +#define MMDC_MAARCR_ARCR_DYN_MAX_MASK (0xF0U) +#define MMDC_MAARCR_ARCR_DYN_MAX_SHIFT (4U) +#define MMDC_MAARCR_ARCR_DYN_MAX(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_DYN_MAX_SHIFT)) & MMDC_MAARCR_ARCR_DYN_MAX_MASK) +#define MMDC_MAARCR_ARCR_DYN_JMP_MASK (0xF00U) +#define MMDC_MAARCR_ARCR_DYN_JMP_SHIFT (8U) +#define MMDC_MAARCR_ARCR_DYN_JMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_DYN_JMP_SHIFT)) & MMDC_MAARCR_ARCR_DYN_JMP_MASK) +#define MMDC_MAARCR_ARCR_ACC_HIT_MASK (0x70000U) +#define MMDC_MAARCR_ARCR_ACC_HIT_SHIFT (16U) +#define MMDC_MAARCR_ARCR_ACC_HIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_ACC_HIT_SHIFT)) & MMDC_MAARCR_ARCR_ACC_HIT_MASK) +#define MMDC_MAARCR_ARCR_PAG_HIT_MASK (0x700000U) +#define MMDC_MAARCR_ARCR_PAG_HIT_SHIFT (20U) +#define MMDC_MAARCR_ARCR_PAG_HIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_PAG_HIT_SHIFT)) & MMDC_MAARCR_ARCR_PAG_HIT_MASK) +#define MMDC_MAARCR_ARCR_RCH_EN_MASK (0x1000000U) +#define MMDC_MAARCR_ARCR_RCH_EN_SHIFT (24U) +#define MMDC_MAARCR_ARCR_RCH_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_RCH_EN_SHIFT)) & MMDC_MAARCR_ARCR_RCH_EN_MASK) +#define MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK (0x10000000U) +#define MMDC_MAARCR_ARCR_EXC_ERR_EN_SHIFT (28U) +#define MMDC_MAARCR_ARCR_EXC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_EXC_ERR_EN_SHIFT)) & MMDC_MAARCR_ARCR_EXC_ERR_EN_MASK) +#define MMDC_MAARCR_ARCR_SEC_ERR_EN_MASK (0x40000000U) +#define MMDC_MAARCR_ARCR_SEC_ERR_EN_SHIFT (30U) +#define MMDC_MAARCR_ARCR_SEC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_SEC_ERR_EN_SHIFT)) & MMDC_MAARCR_ARCR_SEC_ERR_EN_MASK) +#define MMDC_MAARCR_ARCR_SEC_ERR_LOCK_MASK (0x80000000U) +#define MMDC_MAARCR_ARCR_SEC_ERR_LOCK_SHIFT (31U) +#define MMDC_MAARCR_ARCR_SEC_ERR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAARCR_ARCR_SEC_ERR_LOCK_SHIFT)) & MMDC_MAARCR_ARCR_SEC_ERR_LOCK_MASK) + +/*! @name MAPSR - MMDC Core Power Saving Control and Status Register */ +#define MMDC_MAPSR_PSD_MASK (0x1U) +#define MMDC_MAPSR_PSD_SHIFT (0U) +#define MMDC_MAPSR_PSD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_PSD_SHIFT)) & MMDC_MAPSR_PSD_MASK) +#define MMDC_MAPSR_PSS_MASK (0x10U) +#define MMDC_MAPSR_PSS_SHIFT (4U) +#define MMDC_MAPSR_PSS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_PSS_SHIFT)) & MMDC_MAPSR_PSS_MASK) +#define MMDC_MAPSR_RIS_MASK (0x20U) +#define MMDC_MAPSR_RIS_SHIFT (5U) +#define MMDC_MAPSR_RIS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_RIS_SHIFT)) & MMDC_MAPSR_RIS_MASK) +#define MMDC_MAPSR_WIS_MASK (0x40U) +#define MMDC_MAPSR_WIS_SHIFT (6U) +#define MMDC_MAPSR_WIS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_WIS_SHIFT)) & MMDC_MAPSR_WIS_MASK) +#define MMDC_MAPSR_PST_MASK (0xFF00U) +#define MMDC_MAPSR_PST_SHIFT (8U) +#define MMDC_MAPSR_PST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_PST_SHIFT)) & MMDC_MAPSR_PST_MASK) +#define MMDC_MAPSR_LPMD_MASK (0x100000U) +#define MMDC_MAPSR_LPMD_SHIFT (20U) +#define MMDC_MAPSR_LPMD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_LPMD_SHIFT)) & MMDC_MAPSR_LPMD_MASK) +#define MMDC_MAPSR_DVFS_MASK (0x200000U) +#define MMDC_MAPSR_DVFS_SHIFT (21U) +#define MMDC_MAPSR_DVFS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_DVFS_SHIFT)) & MMDC_MAPSR_DVFS_MASK) +#define MMDC_MAPSR_LPACK_MASK (0x1000000U) +#define MMDC_MAPSR_LPACK_SHIFT (24U) +#define MMDC_MAPSR_LPACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_LPACK_SHIFT)) & MMDC_MAPSR_LPACK_MASK) +#define MMDC_MAPSR_DVACK_MASK (0x2000000U) +#define MMDC_MAPSR_DVACK_SHIFT (25U) +#define MMDC_MAPSR_DVACK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAPSR_DVACK_SHIFT)) & MMDC_MAPSR_DVACK_MASK) + +/*! @name MAEXIDR0 - MMDC Core Exclusive ID Monitor Register0 */ +#define MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK (0xFFFFU) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR0_SHIFT (0U) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR0_EXC_ID_MONITOR0_SHIFT)) & MMDC_MAEXIDR0_EXC_ID_MONITOR0_MASK) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK (0xFFFF0000U) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR1_SHIFT (16U) +#define MMDC_MAEXIDR0_EXC_ID_MONITOR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR0_EXC_ID_MONITOR1_SHIFT)) & MMDC_MAEXIDR0_EXC_ID_MONITOR1_MASK) + +/*! @name MAEXIDR1 - MMDC Core Exclusive ID Monitor Register1 */ +#define MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK (0xFFFFU) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR2_SHIFT (0U) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR1_EXC_ID_MONITOR2_SHIFT)) & MMDC_MAEXIDR1_EXC_ID_MONITOR2_MASK) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK (0xFFFF0000U) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR3_SHIFT (16U) +#define MMDC_MAEXIDR1_EXC_ID_MONITOR3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAEXIDR1_EXC_ID_MONITOR3_SHIFT)) & MMDC_MAEXIDR1_EXC_ID_MONITOR3_MASK) + +/*! @name MADPCR0 - MMDC Core Debug and Profiling Control Register 0 */ +#define MMDC_MADPCR0_DBG_EN_MASK (0x1U) +#define MMDC_MADPCR0_DBG_EN_SHIFT (0U) +#define MMDC_MADPCR0_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_DBG_EN_SHIFT)) & MMDC_MADPCR0_DBG_EN_MASK) +#define MMDC_MADPCR0_DBG_RST_MASK (0x2U) +#define MMDC_MADPCR0_DBG_RST_SHIFT (1U) +#define MMDC_MADPCR0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_DBG_RST_SHIFT)) & MMDC_MADPCR0_DBG_RST_MASK) +#define MMDC_MADPCR0_PRF_FRZ_MASK (0x4U) +#define MMDC_MADPCR0_PRF_FRZ_SHIFT (2U) +#define MMDC_MADPCR0_PRF_FRZ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_PRF_FRZ_SHIFT)) & MMDC_MADPCR0_PRF_FRZ_MASK) +#define MMDC_MADPCR0_CYC_OVF_MASK (0x8U) +#define MMDC_MADPCR0_CYC_OVF_SHIFT (3U) +#define MMDC_MADPCR0_CYC_OVF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_CYC_OVF_SHIFT)) & MMDC_MADPCR0_CYC_OVF_MASK) +#define MMDC_MADPCR0_SBS_EN_MASK (0x100U) +#define MMDC_MADPCR0_SBS_EN_SHIFT (8U) +#define MMDC_MADPCR0_SBS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_SBS_EN_SHIFT)) & MMDC_MADPCR0_SBS_EN_MASK) +#define MMDC_MADPCR0_SBS_MASK (0x200U) +#define MMDC_MADPCR0_SBS_SHIFT (9U) +#define MMDC_MADPCR0_SBS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR0_SBS_SHIFT)) & MMDC_MADPCR0_SBS_MASK) + +/*! @name MADPCR1 - MMDC Core Debug and Profiling Control Register 1 */ +#define MMDC_MADPCR1_PRF_AXI_ID_MASK (0xFFFFU) +#define MMDC_MADPCR1_PRF_AXI_ID_SHIFT (0U) +#define MMDC_MADPCR1_PRF_AXI_ID(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR1_PRF_AXI_ID_SHIFT)) & MMDC_MADPCR1_PRF_AXI_ID_MASK) +#define MMDC_MADPCR1_PRF_AXI_IDMASK_MASK (0xFFFF0000U) +#define MMDC_MADPCR1_PRF_AXI_IDMASK_SHIFT (16U) +#define MMDC_MADPCR1_PRF_AXI_IDMASK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPCR1_PRF_AXI_IDMASK_SHIFT)) & MMDC_MADPCR1_PRF_AXI_IDMASK_MASK) + +/*! @name MADPSR0 - MMDC Core Debug and Profiling Status Register 0 */ +#define MMDC_MADPSR0_CYC_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR0_CYC_COUNT_SHIFT (0U) +#define MMDC_MADPSR0_CYC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR0_CYC_COUNT_SHIFT)) & MMDC_MADPSR0_CYC_COUNT_MASK) + +/*! @name MADPSR1 - MMDC Core Debug and Profiling Status Register 1 */ +#define MMDC_MADPSR1_BUSY_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR1_BUSY_COUNT_SHIFT (0U) +#define MMDC_MADPSR1_BUSY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR1_BUSY_COUNT_SHIFT)) & MMDC_MADPSR1_BUSY_COUNT_MASK) + +/*! @name MADPSR2 - MMDC Core Debug and Profiling Status Register 2 */ +#define MMDC_MADPSR2_RD_ACC_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR2_RD_ACC_COUNT_SHIFT (0U) +#define MMDC_MADPSR2_RD_ACC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR2_RD_ACC_COUNT_SHIFT)) & MMDC_MADPSR2_RD_ACC_COUNT_MASK) + +/*! @name MADPSR3 - MMDC Core Debug and Profiling Status Register 3 */ +#define MMDC_MADPSR3_WR_ACC_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR3_WR_ACC_COUNT_SHIFT (0U) +#define MMDC_MADPSR3_WR_ACC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR3_WR_ACC_COUNT_SHIFT)) & MMDC_MADPSR3_WR_ACC_COUNT_MASK) + +/*! @name MADPSR4 - MMDC Core Debug and Profiling Status Register 4 */ +#define MMDC_MADPSR4_RD_BYTES_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR4_RD_BYTES_COUNT_SHIFT (0U) +#define MMDC_MADPSR4_RD_BYTES_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR4_RD_BYTES_COUNT_SHIFT)) & MMDC_MADPSR4_RD_BYTES_COUNT_MASK) + +/*! @name MADPSR5 - MMDC Core Debug and Profiling Status Register 5 */ +#define MMDC_MADPSR5_WR_BYTES_COUNT_MASK (0xFFFFFFFFU) +#define MMDC_MADPSR5_WR_BYTES_COUNT_SHIFT (0U) +#define MMDC_MADPSR5_WR_BYTES_COUNT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MADPSR5_WR_BYTES_COUNT_SHIFT)) & MMDC_MADPSR5_WR_BYTES_COUNT_MASK) + +/*! @name MASBS0 - MMDC Core Step By Step Address Register */ +#define MMDC_MASBS0_SBS_ADDR_MASK (0xFFFFFFFFU) +#define MMDC_MASBS0_SBS_ADDR_SHIFT (0U) +#define MMDC_MASBS0_SBS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS0_SBS_ADDR_SHIFT)) & MMDC_MASBS0_SBS_ADDR_MASK) + +/*! @name MASBS1 - MMDC Core Step By Step Address Attributes Register */ +#define MMDC_MASBS1_SBS_VLD_MASK (0x1U) +#define MMDC_MASBS1_SBS_VLD_SHIFT (0U) +#define MMDC_MASBS1_SBS_VLD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_VLD_SHIFT)) & MMDC_MASBS1_SBS_VLD_MASK) +#define MMDC_MASBS1_SBS_TYPE_MASK (0x2U) +#define MMDC_MASBS1_SBS_TYPE_SHIFT (1U) +#define MMDC_MASBS1_SBS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_TYPE_SHIFT)) & MMDC_MASBS1_SBS_TYPE_MASK) +#define MMDC_MASBS1_SBS_LOCK_MASK (0xCU) +#define MMDC_MASBS1_SBS_LOCK_SHIFT (2U) +#define MMDC_MASBS1_SBS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_LOCK_SHIFT)) & MMDC_MASBS1_SBS_LOCK_MASK) +#define MMDC_MASBS1_SBS_PROT_MASK (0x70U) +#define MMDC_MASBS1_SBS_PROT_SHIFT (4U) +#define MMDC_MASBS1_SBS_PROT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_PROT_SHIFT)) & MMDC_MASBS1_SBS_PROT_MASK) +#define MMDC_MASBS1_SBS_SIZE_MASK (0x380U) +#define MMDC_MASBS1_SBS_SIZE_SHIFT (7U) +#define MMDC_MASBS1_SBS_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_SIZE_SHIFT)) & MMDC_MASBS1_SBS_SIZE_MASK) +#define MMDC_MASBS1_SBS_BURST_MASK (0xC00U) +#define MMDC_MASBS1_SBS_BURST_SHIFT (10U) +#define MMDC_MASBS1_SBS_BURST(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_BURST_SHIFT)) & MMDC_MASBS1_SBS_BURST_MASK) +#define MMDC_MASBS1_SBS_BUFF_MASK (0x1000U) +#define MMDC_MASBS1_SBS_BUFF_SHIFT (12U) +#define MMDC_MASBS1_SBS_BUFF(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_BUFF_SHIFT)) & MMDC_MASBS1_SBS_BUFF_MASK) +#define MMDC_MASBS1_SBS_LEN_MASK (0xE000U) +#define MMDC_MASBS1_SBS_LEN_SHIFT (13U) +#define MMDC_MASBS1_SBS_LEN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_LEN_SHIFT)) & MMDC_MASBS1_SBS_LEN_MASK) +#define MMDC_MASBS1_SBS_AXI_ID_MASK (0xFFFF0000U) +#define MMDC_MASBS1_SBS_AXI_ID_SHIFT (16U) +#define MMDC_MASBS1_SBS_AXI_ID(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MASBS1_SBS_AXI_ID_SHIFT)) & MMDC_MASBS1_SBS_AXI_ID_MASK) + +/*! @name MAGENP - MMDC Core General Purpose Register */ +#define MMDC_MAGENP_GP31_GP0_MASK (0xFFFFFFFFU) +#define MMDC_MAGENP_GP31_GP0_SHIFT (0U) +#define MMDC_MAGENP_GP31_GP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MAGENP_GP31_GP0_SHIFT)) & MMDC_MAGENP_GP31_GP0_MASK) + +/*! @name MPZQHWCTRL - MMDC PHY ZQ HW control register */ +#define MMDC_MPZQHWCTRL_ZQ_MODE_MASK (0x3U) +#define MMDC_MPZQHWCTRL_ZQ_MODE_SHIFT (0U) +#define MMDC_MPZQHWCTRL_ZQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_MODE_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_MODE_MASK) +#define MMDC_MPZQHWCTRL_ZQ_HW_PER_MASK (0x3CU) +#define MMDC_MPZQHWCTRL_ZQ_HW_PER_SHIFT (2U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PER(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_PER_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_PER_MASK) +#define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_MASK (0x7C0U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_SHIFT (6U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PU_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_PU_RES_MASK) +#define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_MASK (0xF800U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_SHIFT (11U) +#define MMDC_MPZQHWCTRL_ZQ_HW_PD_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_PD_RES_MASK) +#define MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK (0x10000U) +#define MMDC_MPZQHWCTRL_ZQ_HW_FOR_SHIFT (16U) +#define MMDC_MPZQHWCTRL_ZQ_HW_FOR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_HW_FOR_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_HW_FOR_MASK) +#define MMDC_MPZQHWCTRL_TZQ_INIT_MASK (0xE0000U) +#define MMDC_MPZQHWCTRL_TZQ_INIT_SHIFT (17U) +#define MMDC_MPZQHWCTRL_TZQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_TZQ_INIT_SHIFT)) & MMDC_MPZQHWCTRL_TZQ_INIT_MASK) +#define MMDC_MPZQHWCTRL_TZQ_OPER_MASK (0x700000U) +#define MMDC_MPZQHWCTRL_TZQ_OPER_SHIFT (20U) +#define MMDC_MPZQHWCTRL_TZQ_OPER(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_TZQ_OPER_SHIFT)) & MMDC_MPZQHWCTRL_TZQ_OPER_MASK) +#define MMDC_MPZQHWCTRL_TZQ_CS_MASK (0x3800000U) +#define MMDC_MPZQHWCTRL_TZQ_CS_SHIFT (23U) +#define MMDC_MPZQHWCTRL_TZQ_CS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_TZQ_CS_SHIFT)) & MMDC_MPZQHWCTRL_TZQ_CS_MASK) +#define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_MASK (0xF8000000U) +#define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_SHIFT (27U) +#define MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_SHIFT)) & MMDC_MPZQHWCTRL_ZQ_EARLY_COMPARATOR_EN_TIMER_MASK) + +/*! @name MPZQSWCTRL - MMDC PHY ZQ SW control register */ +#define MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK (0x1U) +#define MMDC_MPZQSWCTRL_ZQ_SW_FOR_SHIFT (0U) +#define MMDC_MPZQSWCTRL_ZQ_SW_FOR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_FOR_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_FOR_MASK) +#define MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK (0x2U) +#define MMDC_MPZQSWCTRL_ZQ_SW_RES_SHIFT (1U) +#define MMDC_MPZQSWCTRL_ZQ_SW_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_RES_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_RES_MASK) +#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK (0x7CU) +#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_SHIFT (2U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_PU_VAL_MASK) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK (0xF80U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_SHIFT (7U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_PD_VAL_MASK) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK (0x1000U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD_SHIFT (12U) +#define MMDC_MPZQSWCTRL_ZQ_SW_PD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_SW_PD_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_SW_PD_MASK) +#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK (0x2000U) +#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_SHIFT (13U) +#define MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_SHIFT)) & MMDC_MPZQSWCTRL_USE_ZQ_SW_VAL_MASK) +#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK (0x30000U) +#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_SHIFT (16U) +#define MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_SHIFT)) & MMDC_MPZQSWCTRL_ZQ_CMP_OUT_SMP_MASK) + +/*! @name MPWLGCR - MMDC PHY Write Leveling Configuration and Error Status Register */ +#define MMDC_MPWLGCR_HW_WL_EN_MASK (0x1U) +#define MMDC_MPWLGCR_HW_WL_EN_SHIFT (0U) +#define MMDC_MPWLGCR_HW_WL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_HW_WL_EN_SHIFT)) & MMDC_MPWLGCR_HW_WL_EN_MASK) +#define MMDC_MPWLGCR_SW_WL_EN_MASK (0x2U) +#define MMDC_MPWLGCR_SW_WL_EN_SHIFT (1U) +#define MMDC_MPWLGCR_SW_WL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_SW_WL_EN_SHIFT)) & MMDC_MPWLGCR_SW_WL_EN_MASK) +#define MMDC_MPWLGCR_SW_WL_CNT_EN_MASK (0x4U) +#define MMDC_MPWLGCR_SW_WL_CNT_EN_SHIFT (2U) +#define MMDC_MPWLGCR_SW_WL_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_SW_WL_CNT_EN_SHIFT)) & MMDC_MPWLGCR_SW_WL_CNT_EN_MASK) +#define MMDC_MPWLGCR_WL_SW_RES0_MASK (0x10U) +#define MMDC_MPWLGCR_WL_SW_RES0_SHIFT (4U) +#define MMDC_MPWLGCR_WL_SW_RES0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_WL_SW_RES0_SHIFT)) & MMDC_MPWLGCR_WL_SW_RES0_MASK) +#define MMDC_MPWLGCR_WL_SW_RES1_MASK (0x20U) +#define MMDC_MPWLGCR_WL_SW_RES1_SHIFT (5U) +#define MMDC_MPWLGCR_WL_SW_RES1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_WL_SW_RES1_SHIFT)) & MMDC_MPWLGCR_WL_SW_RES1_MASK) +#define MMDC_MPWLGCR_WL_HW_ERR0_MASK (0x100U) +#define MMDC_MPWLGCR_WL_HW_ERR0_SHIFT (8U) +#define MMDC_MPWLGCR_WL_HW_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_WL_HW_ERR0_SHIFT)) & MMDC_MPWLGCR_WL_HW_ERR0_MASK) +#define MMDC_MPWLGCR_WL_HW_ERR1_MASK (0x200U) +#define MMDC_MPWLGCR_WL_HW_ERR1_SHIFT (9U) +#define MMDC_MPWLGCR_WL_HW_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLGCR_WL_HW_ERR1_SHIFT)) & MMDC_MPWLGCR_WL_HW_ERR1_MASK) + +/*! @name MPWLDECTRL0 - MMDC PHY Write Leveling Delay Control Register 0 */ +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_MASK (0x7FU) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_SHIFT (0U) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_SHIFT)) & MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET0_MASK) +#define MMDC_MPWLDECTRL0_WL_HC_DEL0_MASK (0x100U) +#define MMDC_MPWLDECTRL0_WL_HC_DEL0_SHIFT (8U) +#define MMDC_MPWLDECTRL0_WL_HC_DEL0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_HC_DEL0_SHIFT)) & MMDC_MPWLDECTRL0_WL_HC_DEL0_MASK) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL0_MASK (0x600U) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL0_SHIFT (9U) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_CYC_DEL0_SHIFT)) & MMDC_MPWLDECTRL0_WL_CYC_DEL0_MASK) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_MASK (0x7F0000U) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_SHIFT (16U) +#define MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_SHIFT)) & MMDC_MPWLDECTRL0_WL_DL_ABS_OFFSET1_MASK) +#define MMDC_MPWLDECTRL0_WL_HC_DEL1_MASK (0x1000000U) +#define MMDC_MPWLDECTRL0_WL_HC_DEL1_SHIFT (24U) +#define MMDC_MPWLDECTRL0_WL_HC_DEL1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_HC_DEL1_SHIFT)) & MMDC_MPWLDECTRL0_WL_HC_DEL1_MASK) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL1_MASK (0x6000000U) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL1_SHIFT (25U) +#define MMDC_MPWLDECTRL0_WL_CYC_DEL1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL0_WL_CYC_DEL1_SHIFT)) & MMDC_MPWLDECTRL0_WL_CYC_DEL1_MASK) + +/*! @name MPWLDECTRL1 - MMDC PHY Write Leveling Delay Control Register 1 */ +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_MASK (0x7FU) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_SHIFT (0U) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_SHIFT)) & MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET2_MASK) +#define MMDC_MPWLDECTRL1_WL_HC_DEL2_MASK (0x100U) +#define MMDC_MPWLDECTRL1_WL_HC_DEL2_SHIFT (8U) +#define MMDC_MPWLDECTRL1_WL_HC_DEL2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_HC_DEL2_SHIFT)) & MMDC_MPWLDECTRL1_WL_HC_DEL2_MASK) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL2_MASK (0x600U) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL2_SHIFT (9U) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_CYC_DEL2_SHIFT)) & MMDC_MPWLDECTRL1_WL_CYC_DEL2_MASK) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_MASK (0x7F0000U) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_SHIFT (16U) +#define MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_SHIFT)) & MMDC_MPWLDECTRL1_WL_DL_ABS_OFFSET3_MASK) +#define MMDC_MPWLDECTRL1_WL_HC_DEL3_MASK (0x1000000U) +#define MMDC_MPWLDECTRL1_WL_HC_DEL3_SHIFT (24U) +#define MMDC_MPWLDECTRL1_WL_HC_DEL3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_HC_DEL3_SHIFT)) & MMDC_MPWLDECTRL1_WL_HC_DEL3_MASK) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL3_MASK (0x6000000U) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL3_SHIFT (25U) +#define MMDC_MPWLDECTRL1_WL_CYC_DEL3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDECTRL1_WL_CYC_DEL3_SHIFT)) & MMDC_MPWLDECTRL1_WL_CYC_DEL3_MASK) + +/*! @name MPWLDLST - MMDC PHY Write Leveling delay-line Status Register */ +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM0_MASK (0x7FU) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM0_SHIFT (0U) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDLST_WL_DL_UNIT_NUM0_SHIFT)) & MMDC_MPWLDLST_WL_DL_UNIT_NUM0_MASK) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM1_MASK (0x7F00U) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM1_SHIFT (8U) +#define MMDC_MPWLDLST_WL_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLDLST_WL_DL_UNIT_NUM1_SHIFT)) & MMDC_MPWLDLST_WL_DL_UNIT_NUM1_MASK) + +/*! @name MPODTCTRL - MMDC PHY ODT control register */ +#define MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK (0x1U) +#define MMDC_MPODTCTRL_ODT_WR_PAS_EN_SHIFT (0U) +#define MMDC_MPODTCTRL_ODT_WR_PAS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT_WR_PAS_EN_SHIFT)) & MMDC_MPODTCTRL_ODT_WR_PAS_EN_MASK) +#define MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK (0x2U) +#define MMDC_MPODTCTRL_ODT_WR_ACT_EN_SHIFT (1U) +#define MMDC_MPODTCTRL_ODT_WR_ACT_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT_WR_ACT_EN_SHIFT)) & MMDC_MPODTCTRL_ODT_WR_ACT_EN_MASK) +#define MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK (0x4U) +#define MMDC_MPODTCTRL_ODT_RD_PAS_EN_SHIFT (2U) +#define MMDC_MPODTCTRL_ODT_RD_PAS_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT_RD_PAS_EN_SHIFT)) & MMDC_MPODTCTRL_ODT_RD_PAS_EN_MASK) +#define MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK (0x8U) +#define MMDC_MPODTCTRL_ODT_RD_ACT_EN_SHIFT (3U) +#define MMDC_MPODTCTRL_ODT_RD_ACT_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT_RD_ACT_EN_SHIFT)) & MMDC_MPODTCTRL_ODT_RD_ACT_EN_MASK) +#define MMDC_MPODTCTRL_ODT0_INT_RES_MASK (0x70U) +#define MMDC_MPODTCTRL_ODT0_INT_RES_SHIFT (4U) +#define MMDC_MPODTCTRL_ODT0_INT_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT0_INT_RES_SHIFT)) & MMDC_MPODTCTRL_ODT0_INT_RES_MASK) +#define MMDC_MPODTCTRL_ODT1_INT_RES_MASK (0x700U) +#define MMDC_MPODTCTRL_ODT1_INT_RES_SHIFT (8U) +#define MMDC_MPODTCTRL_ODT1_INT_RES(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPODTCTRL_ODT1_INT_RES_SHIFT)) & MMDC_MPODTCTRL_ODT1_INT_RES_MASK) + +/*! @name MPRDDQBY0DL - MMDC PHY Read DQ Byte0 Delay Register */ +#define MMDC_MPRDDQBY0DL_RD_DQ0_DEL_MASK (0x7U) +#define MMDC_MPRDDQBY0DL_RD_DQ0_DEL_SHIFT (0U) +#define MMDC_MPRDDQBY0DL_RD_DQ0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ0_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ0_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ1_DEL_MASK (0x70U) +#define MMDC_MPRDDQBY0DL_RD_DQ1_DEL_SHIFT (4U) +#define MMDC_MPRDDQBY0DL_RD_DQ1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ1_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ1_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ2_DEL_MASK (0x700U) +#define MMDC_MPRDDQBY0DL_RD_DQ2_DEL_SHIFT (8U) +#define MMDC_MPRDDQBY0DL_RD_DQ2_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ2_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ2_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ3_DEL_MASK (0x7000U) +#define MMDC_MPRDDQBY0DL_RD_DQ3_DEL_SHIFT (12U) +#define MMDC_MPRDDQBY0DL_RD_DQ3_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ3_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ3_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ4_DEL_MASK (0x70000U) +#define MMDC_MPRDDQBY0DL_RD_DQ4_DEL_SHIFT (16U) +#define MMDC_MPRDDQBY0DL_RD_DQ4_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ4_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ4_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ5_DEL_MASK (0x700000U) +#define MMDC_MPRDDQBY0DL_RD_DQ5_DEL_SHIFT (20U) +#define MMDC_MPRDDQBY0DL_RD_DQ5_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ5_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ5_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ6_DEL_MASK (0x7000000U) +#define MMDC_MPRDDQBY0DL_RD_DQ6_DEL_SHIFT (24U) +#define MMDC_MPRDDQBY0DL_RD_DQ6_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ6_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ6_DEL_MASK) +#define MMDC_MPRDDQBY0DL_RD_DQ7_DEL_MASK (0x70000000U) +#define MMDC_MPRDDQBY0DL_RD_DQ7_DEL_SHIFT (28U) +#define MMDC_MPRDDQBY0DL_RD_DQ7_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY0DL_RD_DQ7_DEL_SHIFT)) & MMDC_MPRDDQBY0DL_RD_DQ7_DEL_MASK) + +/*! @name MPRDDQBY1DL - MMDC PHY Read DQ Byte1 Delay Register */ +#define MMDC_MPRDDQBY1DL_RD_DQ8_DEL_MASK (0x7U) +#define MMDC_MPRDDQBY1DL_RD_DQ8_DEL_SHIFT (0U) +#define MMDC_MPRDDQBY1DL_RD_DQ8_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ8_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ8_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ9_DEL_MASK (0x70U) +#define MMDC_MPRDDQBY1DL_RD_DQ9_DEL_SHIFT (4U) +#define MMDC_MPRDDQBY1DL_RD_DQ9_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ9_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ9_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ10_DEL_MASK (0x700U) +#define MMDC_MPRDDQBY1DL_RD_DQ10_DEL_SHIFT (8U) +#define MMDC_MPRDDQBY1DL_RD_DQ10_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ10_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ10_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ11_DEL_MASK (0x7000U) +#define MMDC_MPRDDQBY1DL_RD_DQ11_DEL_SHIFT (12U) +#define MMDC_MPRDDQBY1DL_RD_DQ11_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ11_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ11_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ12_DEL_MASK (0x70000U) +#define MMDC_MPRDDQBY1DL_RD_DQ12_DEL_SHIFT (16U) +#define MMDC_MPRDDQBY1DL_RD_DQ12_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ12_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ12_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ13_DEL_MASK (0x700000U) +#define MMDC_MPRDDQBY1DL_RD_DQ13_DEL_SHIFT (20U) +#define MMDC_MPRDDQBY1DL_RD_DQ13_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ13_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ13_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ14_DEL_MASK (0x7000000U) +#define MMDC_MPRDDQBY1DL_RD_DQ14_DEL_SHIFT (24U) +#define MMDC_MPRDDQBY1DL_RD_DQ14_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ14_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ14_DEL_MASK) +#define MMDC_MPRDDQBY1DL_RD_DQ15_DEL_MASK (0x70000000U) +#define MMDC_MPRDDQBY1DL_RD_DQ15_DEL_SHIFT (28U) +#define MMDC_MPRDDQBY1DL_RD_DQ15_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDQBY1DL_RD_DQ15_DEL_SHIFT)) & MMDC_MPRDDQBY1DL_RD_DQ15_DEL_MASK) + +/*! @name MPWRDQBY0DL - MMDC PHY Write DQ Byte0 Delay Register */ +#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK (0x3U) +#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL_SHIFT (0U) +#define MMDC_MPWRDQBY0DL_WR_DQ0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ0_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ0_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK (0x30U) +#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL_SHIFT (4U) +#define MMDC_MPWRDQBY0DL_WR_DQ1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ1_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ1_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK (0x300U) +#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL_SHIFT (8U) +#define MMDC_MPWRDQBY0DL_WR_DQ2_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ2_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ2_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK (0x3000U) +#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL_SHIFT (12U) +#define MMDC_MPWRDQBY0DL_WR_DQ3_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ3_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ3_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK (0x30000U) +#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL_SHIFT (16U) +#define MMDC_MPWRDQBY0DL_WR_DQ4_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ4_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ4_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK (0x300000U) +#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL_SHIFT (20U) +#define MMDC_MPWRDQBY0DL_WR_DQ5_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ5_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ5_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK (0x3000000U) +#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL_SHIFT (24U) +#define MMDC_MPWRDQBY0DL_WR_DQ6_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ6_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ6_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK (0x30000000U) +#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL_SHIFT (28U) +#define MMDC_MPWRDQBY0DL_WR_DQ7_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DQ7_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DQ7_DEL_MASK) +#define MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK (0xC0000000U) +#define MMDC_MPWRDQBY0DL_WR_DM0_DEL_SHIFT (30U) +#define MMDC_MPWRDQBY0DL_WR_DM0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY0DL_WR_DM0_DEL_SHIFT)) & MMDC_MPWRDQBY0DL_WR_DM0_DEL_MASK) + +/*! @name MPWRDQBY1DL - MMDC PHY Write DQ Byte1 Delay Register */ +#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK (0x3U) +#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL_SHIFT (0U) +#define MMDC_MPWRDQBY1DL_WR_DQ8_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ8_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ8_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK (0x30U) +#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL_SHIFT (4U) +#define MMDC_MPWRDQBY1DL_WR_DQ9_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ9_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ9_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK (0x300U) +#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL_SHIFT (8U) +#define MMDC_MPWRDQBY1DL_WR_DQ10_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ10_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ10_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK (0x3000U) +#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL_SHIFT (12U) +#define MMDC_MPWRDQBY1DL_WR_DQ11_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ11_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ11_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK (0x30000U) +#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL_SHIFT (16U) +#define MMDC_MPWRDQBY1DL_WR_DQ12_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ12_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ12_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK (0x300000U) +#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL_SHIFT (20U) +#define MMDC_MPWRDQBY1DL_WR_DQ13_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ13_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ13_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK (0x3000000U) +#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL_SHIFT (24U) +#define MMDC_MPWRDQBY1DL_WR_DQ14_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ14_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ14_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK (0x30000000U) +#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL_SHIFT (28U) +#define MMDC_MPWRDQBY1DL_WR_DQ15_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DQ15_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DQ15_DEL_MASK) +#define MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK (0xC0000000U) +#define MMDC_MPWRDQBY1DL_WR_DM1_DEL_SHIFT (30U) +#define MMDC_MPWRDQBY1DL_WR_DM1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY1DL_WR_DM1_DEL_SHIFT)) & MMDC_MPWRDQBY1DL_WR_DM1_DEL_MASK) + +/*! @name MPWRDQBY2DL - MMDC PHY Write DQ Byte2 Delay Register */ +#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK (0x3U) +#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL_SHIFT (0U) +#define MMDC_MPWRDQBY2DL_WR_DQ16_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ16_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ16_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK (0x30U) +#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL_SHIFT (4U) +#define MMDC_MPWRDQBY2DL_WR_DQ17_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ17_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ17_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK (0x300U) +#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL_SHIFT (8U) +#define MMDC_MPWRDQBY2DL_WR_DQ18_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ18_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ18_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK (0x3000U) +#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL_SHIFT (12U) +#define MMDC_MPWRDQBY2DL_WR_DQ19_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ19_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ19_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK (0x30000U) +#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL_SHIFT (16U) +#define MMDC_MPWRDQBY2DL_WR_DQ20_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ20_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ20_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK (0x300000U) +#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL_SHIFT (20U) +#define MMDC_MPWRDQBY2DL_WR_DQ21_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ21_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ21_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK (0x3000000U) +#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL_SHIFT (24U) +#define MMDC_MPWRDQBY2DL_WR_DQ22_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ22_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ22_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK (0x30000000U) +#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL_SHIFT (28U) +#define MMDC_MPWRDQBY2DL_WR_DQ23_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DQ23_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DQ23_DEL_MASK) +#define MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK (0xC0000000U) +#define MMDC_MPWRDQBY2DL_WR_DM2_DEL_SHIFT (30U) +#define MMDC_MPWRDQBY2DL_WR_DM2_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY2DL_WR_DM2_DEL_SHIFT)) & MMDC_MPWRDQBY2DL_WR_DM2_DEL_MASK) + +/*! @name MPWRDQBY3DL - MMDC PHY Write DQ Byte3 Delay Register */ +#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK (0x3U) +#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_SHIFT (0U) +#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ24_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK (0x30U) +#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_SHIFT (4U) +#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ25_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK (0x300U) +#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL_SHIFT (8U) +#define MMDC_MPWRDQBY3DL_WR_DQ26_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ26_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ26_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK (0x3000U) +#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL_SHIFT (12U) +#define MMDC_MPWRDQBY3DL_WR_DQ27_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ27_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ27_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK (0x30000U) +#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL_SHIFT (16U) +#define MMDC_MPWRDQBY3DL_WR_DQ28_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ28_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ28_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK (0x300000U) +#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL_SHIFT (20U) +#define MMDC_MPWRDQBY3DL_WR_DQ29_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ29_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ29_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK (0x3000000U) +#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL_SHIFT (24U) +#define MMDC_MPWRDQBY3DL_WR_DQ30_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ30_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ30_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK (0x30000000U) +#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL_SHIFT (28U) +#define MMDC_MPWRDQBY3DL_WR_DQ31_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DQ31_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DQ31_DEL_MASK) +#define MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK (0xC0000000U) +#define MMDC_MPWRDQBY3DL_WR_DM3_DEL_SHIFT (30U) +#define MMDC_MPWRDQBY3DL_WR_DM3_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDQBY3DL_WR_DM3_DEL_SHIFT)) & MMDC_MPWRDQBY3DL_WR_DM3_DEL_MASK) + +/*! @name MPDGCTRL0 - MMDC PHY Read DQS Gating Control Register 0 */ +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_MASK (0x7FU) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_SHIFT (0U) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_SHIFT)) & MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET0_MASK) +#define MMDC_MPDGCTRL0_DG_HC_DEL0_MASK (0xF00U) +#define MMDC_MPDGCTRL0_DG_HC_DEL0_SHIFT (8U) +#define MMDC_MPDGCTRL0_DG_HC_DEL0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_HC_DEL0_SHIFT)) & MMDC_MPDGCTRL0_DG_HC_DEL0_MASK) +#define MMDC_MPDGCTRL0_HW_DG_ERR_MASK (0x1000U) +#define MMDC_MPDGCTRL0_HW_DG_ERR_SHIFT (12U) +#define MMDC_MPDGCTRL0_HW_DG_ERR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_HW_DG_ERR_SHIFT)) & MMDC_MPDGCTRL0_HW_DG_ERR_MASK) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_MASK (0x7F0000U) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_SHIFT (16U) +#define MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_SHIFT)) & MMDC_MPDGCTRL0_DG_DL_ABS_OFFSET1_MASK) +#define MMDC_MPDGCTRL0_DG_EXT_UP_MASK (0x800000U) +#define MMDC_MPDGCTRL0_DG_EXT_UP_SHIFT (23U) +#define MMDC_MPDGCTRL0_DG_EXT_UP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_EXT_UP_SHIFT)) & MMDC_MPDGCTRL0_DG_EXT_UP_MASK) +#define MMDC_MPDGCTRL0_DG_HC_DEL1_MASK (0xF000000U) +#define MMDC_MPDGCTRL0_DG_HC_DEL1_SHIFT (24U) +#define MMDC_MPDGCTRL0_DG_HC_DEL1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_HC_DEL1_SHIFT)) & MMDC_MPDGCTRL0_DG_HC_DEL1_MASK) +#define MMDC_MPDGCTRL0_HW_DG_EN_MASK (0x10000000U) +#define MMDC_MPDGCTRL0_HW_DG_EN_SHIFT (28U) +#define MMDC_MPDGCTRL0_HW_DG_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_HW_DG_EN_SHIFT)) & MMDC_MPDGCTRL0_HW_DG_EN_MASK) +#define MMDC_MPDGCTRL0_DG_DIS_MASK (0x20000000U) +#define MMDC_MPDGCTRL0_DG_DIS_SHIFT (29U) +#define MMDC_MPDGCTRL0_DG_DIS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_DIS_SHIFT)) & MMDC_MPDGCTRL0_DG_DIS_MASK) +#define MMDC_MPDGCTRL0_DG_CMP_CYC_MASK (0x40000000U) +#define MMDC_MPDGCTRL0_DG_CMP_CYC_SHIFT (30U) +#define MMDC_MPDGCTRL0_DG_CMP_CYC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_DG_CMP_CYC_SHIFT)) & MMDC_MPDGCTRL0_DG_CMP_CYC_MASK) +#define MMDC_MPDGCTRL0_RST_RD_FIFO_MASK (0x80000000U) +#define MMDC_MPDGCTRL0_RST_RD_FIFO_SHIFT (31U) +#define MMDC_MPDGCTRL0_RST_RD_FIFO(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGCTRL0_RST_RD_FIFO_SHIFT)) & MMDC_MPDGCTRL0_RST_RD_FIFO_MASK) + +/*! @name MPDGDLST0 - MMDC PHY Read DQS Gating delay-line Status Register */ +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_MASK (0x7FU) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_SHIFT (0U) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_SHIFT)) & MMDC_MPDGDLST0_DG_DL_UNIT_NUM0_MASK) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_MASK (0x7F00U) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_SHIFT (8U) +#define MMDC_MPDGDLST0_DG_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_SHIFT)) & MMDC_MPDGDLST0_DG_DL_UNIT_NUM1_MASK) + +/*! @name MPRDDLCTL - MMDC PHY Read delay-lines Configuration Register */ +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK (0x7FU) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_SHIFT (0U) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_SHIFT)) & MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET0_MASK) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK (0x7F00U) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_SHIFT (8U) +#define MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_SHIFT)) & MMDC_MPRDDLCTL_RD_DL_ABS_OFFSET1_MASK) + +/*! @name MPRDDLST - MMDC PHY Read delay-lines Status Register */ +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM0_MASK (0x7FU) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM0_SHIFT (0U) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLST_RD_DL_UNIT_NUM0_SHIFT)) & MMDC_MPRDDLST_RD_DL_UNIT_NUM0_MASK) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM1_MASK (0x7F00U) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM1_SHIFT (8U) +#define MMDC_MPRDDLST_RD_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLST_RD_DL_UNIT_NUM1_SHIFT)) & MMDC_MPRDDLST_RD_DL_UNIT_NUM1_MASK) + +/*! @name MPWRDLCTL - MMDC PHY Write delay-lines Configuration Register */ +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK (0x7FU) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_SHIFT (0U) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_SHIFT)) & MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET0_MASK) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK (0x7F00U) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_SHIFT (8U) +#define MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_SHIFT)) & MMDC_MPWRDLCTL_WR_DL_ABS_OFFSET1_MASK) + +/*! @name MPWRDLST - MMDC PHY Write delay-lines Status Register */ +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM0_MASK (0x7FU) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM0_SHIFT (0U) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLST_WR_DL_UNIT_NUM0_SHIFT)) & MMDC_MPWRDLST_WR_DL_UNIT_NUM0_MASK) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM1_MASK (0x7F00U) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM1_SHIFT (8U) +#define MMDC_MPWRDLST_WR_DL_UNIT_NUM1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLST_WR_DL_UNIT_NUM1_SHIFT)) & MMDC_MPWRDLST_WR_DL_UNIT_NUM1_MASK) + +/*! @name MPSDCTRL - MMDC PHY CK Control Register */ +#define MMDC_MPSDCTRL_SDCLK0_DEL_MASK (0x300U) +#define MMDC_MPSDCTRL_SDCLK0_DEL_SHIFT (8U) +#define MMDC_MPSDCTRL_SDCLK0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSDCTRL_SDCLK0_DEL_SHIFT)) & MMDC_MPSDCTRL_SDCLK0_DEL_MASK) +#define MMDC_MPSDCTRL_SDCLK1_DEL_MASK (0xC00U) +#define MMDC_MPSDCTRL_SDCLK1_DEL_SHIFT (10U) +#define MMDC_MPSDCTRL_SDCLK1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSDCTRL_SDCLK1_DEL_SHIFT)) & MMDC_MPSDCTRL_SDCLK1_DEL_MASK) + +/*! @name MPZQLP2CTL - MMDC ZQ LPDDR2 HW Control Register */ +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK (0x1FFU) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_SHIFT (0U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_SHIFT)) & MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQINIT_MASK) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK (0xFF0000U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_SHIFT (16U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_SHIFT)) & MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCL_MASK) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK (0x7F000000U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_SHIFT (24U) +#define MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_SHIFT)) & MMDC_MPZQLP2CTL_ZQ_LP2_HW_ZQCS_MASK) + +/*! @name MPRDDLHWCTL - MMDC PHY Read Delay HW Calibration Control Register */ +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_MASK (0x1U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_SHIFT (0U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_ERR0_MASK) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_MASK (0x2U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_SHIFT (1U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_ERR1_MASK) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK (0x10U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN_SHIFT (4U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_EN_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_EN_MASK) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK (0x20U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_SHIFT (5U) +#define MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_SHIFT)) & MMDC_MPRDDLHWCTL_HW_RD_DL_CMP_CYC_MASK) + +/*! @name MPWRDLHWCTL - MMDC PHY Write Delay HW Calibration Control Register */ +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_MASK (0x1U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_SHIFT (0U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_ERR0_MASK) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_MASK (0x2U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_SHIFT (1U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_ERR1_MASK) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK (0x10U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN_SHIFT (4U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_EN_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_EN_MASK) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK (0x20U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_SHIFT (5U) +#define MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_SHIFT)) & MMDC_MPWRDLHWCTL_HW_WR_DL_CMP_CYC_MASK) + +/*! @name MPRDDLHWST0 - MMDC PHY Read Delay HW Calibration Status Register 0 */ +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_MASK (0x7FU) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_SHIFT (0U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_LOW0_MASK) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP0_MASK (0x7F00U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP0_SHIFT (8U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_UP0_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_UP0_MASK) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_MASK (0x7F0000U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_SHIFT (16U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_LOW1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_LOW1_MASK) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP1_MASK (0x7F000000U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP1_SHIFT (24U) +#define MMDC_MPRDDLHWST0_HW_RD_DL_UP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPRDDLHWST0_HW_RD_DL_UP1_SHIFT)) & MMDC_MPRDDLHWST0_HW_RD_DL_UP1_MASK) + +/*! @name MPWRDLHWST0 - MMDC PHY Write Delay HW Calibration Status Register 0 */ +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_MASK (0x7FU) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_SHIFT (0U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_LOW0_MASK) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP0_MASK (0x7F00U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP0_SHIFT (8U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_UP0_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_UP0_MASK) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_MASK (0x7F0000U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_SHIFT (16U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_LOW1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_LOW1_MASK) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP1_MASK (0x7F000000U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP1_SHIFT (24U) +#define MMDC_MPWRDLHWST0_HW_WR_DL_UP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRDLHWST0_HW_WR_DL_UP1_SHIFT)) & MMDC_MPWRDLHWST0_HW_WR_DL_UP1_MASK) + +/*! @name MPWLHWERR - MMDC PHY Write Leveling HW Error Register */ +#define MMDC_MPWLHWERR_HW_WL0_DQ_MASK (0xFFU) +#define MMDC_MPWLHWERR_HW_WL0_DQ_SHIFT (0U) +#define MMDC_MPWLHWERR_HW_WL0_DQ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLHWERR_HW_WL0_DQ_SHIFT)) & MMDC_MPWLHWERR_HW_WL0_DQ_MASK) +#define MMDC_MPWLHWERR_HW_WL1_DQ_MASK (0xFF00U) +#define MMDC_MPWLHWERR_HW_WL1_DQ_SHIFT (8U) +#define MMDC_MPWLHWERR_HW_WL1_DQ(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWLHWERR_HW_WL1_DQ_SHIFT)) & MMDC_MPWLHWERR_HW_WL1_DQ_MASK) + +/*! @name MPDGHWST0 - MMDC PHY Read DQS Gating HW Status Register 0 */ +#define MMDC_MPDGHWST0_HW_DG_LOW0_MASK (0x7FFU) +#define MMDC_MPDGHWST0_HW_DG_LOW0_SHIFT (0U) +#define MMDC_MPDGHWST0_HW_DG_LOW0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGHWST0_HW_DG_LOW0_SHIFT)) & MMDC_MPDGHWST0_HW_DG_LOW0_MASK) +#define MMDC_MPDGHWST0_HW_DG_UP0_MASK (0x7FF0000U) +#define MMDC_MPDGHWST0_HW_DG_UP0_SHIFT (16U) +#define MMDC_MPDGHWST0_HW_DG_UP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGHWST0_HW_DG_UP0_SHIFT)) & MMDC_MPDGHWST0_HW_DG_UP0_MASK) + +/*! @name MPDGHWST1 - MMDC PHY Read DQS Gating HW Status Register 1 */ +#define MMDC_MPDGHWST1_HW_DG_LOW1_MASK (0x7FFU) +#define MMDC_MPDGHWST1_HW_DG_LOW1_SHIFT (0U) +#define MMDC_MPDGHWST1_HW_DG_LOW1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGHWST1_HW_DG_LOW1_SHIFT)) & MMDC_MPDGHWST1_HW_DG_LOW1_MASK) +#define MMDC_MPDGHWST1_HW_DG_UP1_MASK (0x7FF0000U) +#define MMDC_MPDGHWST1_HW_DG_UP1_SHIFT (16U) +#define MMDC_MPDGHWST1_HW_DG_UP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDGHWST1_HW_DG_UP1_SHIFT)) & MMDC_MPDGHWST1_HW_DG_UP1_MASK) + +/*! @name MPPDCMPR1 - MMDC PHY Pre-defined Compare Register 1 */ +#define MMDC_MPPDCMPR1_PDV1_MASK (0xFFFFU) +#define MMDC_MPPDCMPR1_PDV1_SHIFT (0U) +#define MMDC_MPPDCMPR1_PDV1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR1_PDV1_SHIFT)) & MMDC_MPPDCMPR1_PDV1_MASK) +#define MMDC_MPPDCMPR1_PDV2_MASK (0xFFFF0000U) +#define MMDC_MPPDCMPR1_PDV2_SHIFT (16U) +#define MMDC_MPPDCMPR1_PDV2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR1_PDV2_SHIFT)) & MMDC_MPPDCMPR1_PDV2_MASK) + +/*! @name MPPDCMPR2 - MMDC PHY Pre-defined Compare and CA delay-line Configuration Register */ +#define MMDC_MPPDCMPR2_MPR_CMP_MASK (0x1U) +#define MMDC_MPPDCMPR2_MPR_CMP_SHIFT (0U) +#define MMDC_MPPDCMPR2_MPR_CMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_MPR_CMP_SHIFT)) & MMDC_MPPDCMPR2_MPR_CMP_MASK) +#define MMDC_MPPDCMPR2_MPR_FULL_CMP_MASK (0x2U) +#define MMDC_MPPDCMPR2_MPR_FULL_CMP_SHIFT (1U) +#define MMDC_MPPDCMPR2_MPR_FULL_CMP(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_MPR_FULL_CMP_SHIFT)) & MMDC_MPPDCMPR2_MPR_FULL_CMP_MASK) +#define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_MASK (0x4U) +#define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_SHIFT (2U) +#define MMDC_MPPDCMPR2_READ_LEVEL_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_SHIFT)) & MMDC_MPPDCMPR2_READ_LEVEL_PATTERN_MASK) +#define MMDC_MPPDCMPR2_ZQ_OFFSET_EN_MASK (0x8U) +#define MMDC_MPPDCMPR2_ZQ_OFFSET_EN_SHIFT (3U) +#define MMDC_MPPDCMPR2_ZQ_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_ZQ_OFFSET_EN_SHIFT)) & MMDC_MPPDCMPR2_ZQ_OFFSET_EN_MASK) +#define MMDC_MPPDCMPR2_ZQ_PD_OFFSET_MASK (0xF0U) +#define MMDC_MPPDCMPR2_ZQ_PD_OFFSET_SHIFT (4U) +#define MMDC_MPPDCMPR2_ZQ_PD_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_ZQ_PD_OFFSET_SHIFT)) & MMDC_MPPDCMPR2_ZQ_PD_OFFSET_MASK) +#define MMDC_MPPDCMPR2_ZQ_PU_OFFSET_MASK (0xF00U) +#define MMDC_MPPDCMPR2_ZQ_PU_OFFSET_SHIFT (8U) +#define MMDC_MPPDCMPR2_ZQ_PU_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_ZQ_PU_OFFSET_SHIFT)) & MMDC_MPPDCMPR2_ZQ_PU_OFFSET_MASK) +#define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_MASK (0x7F0000U) +#define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_SHIFT (16U) +#define MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_SHIFT)) & MMDC_MPPDCMPR2_CA_DL_ABS_OFFSET_MASK) +#define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_MASK (0x7F000000U) +#define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_SHIFT (24U) +#define MMDC_MPPDCMPR2_PHY_CA_DL_UNIT(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_SHIFT)) & MMDC_MPPDCMPR2_PHY_CA_DL_UNIT_MASK) + +/*! @name MPSWDAR0 - MMDC PHY SW Dummy Access Register */ +#define MMDC_MPSWDAR0_SW_DUMMY_WR_MASK (0x1U) +#define MMDC_MPSWDAR0_SW_DUMMY_WR_SHIFT (0U) +#define MMDC_MPSWDAR0_SW_DUMMY_WR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUMMY_WR_SHIFT)) & MMDC_MPSWDAR0_SW_DUMMY_WR_MASK) +#define MMDC_MPSWDAR0_SW_DUMMY_RD_MASK (0x2U) +#define MMDC_MPSWDAR0_SW_DUMMY_RD_SHIFT (1U) +#define MMDC_MPSWDAR0_SW_DUMMY_RD(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUMMY_RD_SHIFT)) & MMDC_MPSWDAR0_SW_DUMMY_RD_MASK) +#define MMDC_MPSWDAR0_SW_DUM_CMP0_MASK (0x4U) +#define MMDC_MPSWDAR0_SW_DUM_CMP0_SHIFT (2U) +#define MMDC_MPSWDAR0_SW_DUM_CMP0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUM_CMP0_SHIFT)) & MMDC_MPSWDAR0_SW_DUM_CMP0_MASK) +#define MMDC_MPSWDAR0_SW_DUM_CMP1_MASK (0x8U) +#define MMDC_MPSWDAR0_SW_DUM_CMP1_SHIFT (3U) +#define MMDC_MPSWDAR0_SW_DUM_CMP1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDAR0_SW_DUM_CMP1_SHIFT)) & MMDC_MPSWDAR0_SW_DUM_CMP1_MASK) + +/*! @name MPSWDRDR0 - MMDC PHY SW Dummy Read Data Register 0 */ +#define MMDC_MPSWDRDR0_DUM_RD0_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR0_DUM_RD0_SHIFT (0U) +#define MMDC_MPSWDRDR0_DUM_RD0(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR0_DUM_RD0_SHIFT)) & MMDC_MPSWDRDR0_DUM_RD0_MASK) + +/*! @name MPSWDRDR1 - MMDC PHY SW Dummy Read Data Register 1 */ +#define MMDC_MPSWDRDR1_DUM_RD1_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR1_DUM_RD1_SHIFT (0U) +#define MMDC_MPSWDRDR1_DUM_RD1(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR1_DUM_RD1_SHIFT)) & MMDC_MPSWDRDR1_DUM_RD1_MASK) + +/*! @name MPSWDRDR2 - MMDC PHY SW Dummy Read Data Register 2 */ +#define MMDC_MPSWDRDR2_DUM_RD2_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR2_DUM_RD2_SHIFT (0U) +#define MMDC_MPSWDRDR2_DUM_RD2(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR2_DUM_RD2_SHIFT)) & MMDC_MPSWDRDR2_DUM_RD2_MASK) + +/*! @name MPSWDRDR3 - MMDC PHY SW Dummy Read Data Register 3 */ +#define MMDC_MPSWDRDR3_DUM_RD3_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR3_DUM_RD3_SHIFT (0U) +#define MMDC_MPSWDRDR3_DUM_RD3(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR3_DUM_RD3_SHIFT)) & MMDC_MPSWDRDR3_DUM_RD3_MASK) + +/*! @name MPSWDRDR4 - MMDC PHY SW Dummy Read Data Register 4 */ +#define MMDC_MPSWDRDR4_DUM_RD4_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR4_DUM_RD4_SHIFT (0U) +#define MMDC_MPSWDRDR4_DUM_RD4(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR4_DUM_RD4_SHIFT)) & MMDC_MPSWDRDR4_DUM_RD4_MASK) + +/*! @name MPSWDRDR5 - MMDC PHY SW Dummy Read Data Register 5 */ +#define MMDC_MPSWDRDR5_DUM_RD5_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR5_DUM_RD5_SHIFT (0U) +#define MMDC_MPSWDRDR5_DUM_RD5(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR5_DUM_RD5_SHIFT)) & MMDC_MPSWDRDR5_DUM_RD5_MASK) + +/*! @name MPSWDRDR6 - MMDC PHY SW Dummy Read Data Register 6 */ +#define MMDC_MPSWDRDR6_DUM_RD6_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR6_DUM_RD6_SHIFT (0U) +#define MMDC_MPSWDRDR6_DUM_RD6(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR6_DUM_RD6_SHIFT)) & MMDC_MPSWDRDR6_DUM_RD6_MASK) + +/*! @name MPSWDRDR7 - MMDC PHY SW Dummy Read Data Register 7 */ +#define MMDC_MPSWDRDR7_DUM_RD7_MASK (0xFFFFFFFFU) +#define MMDC_MPSWDRDR7_DUM_RD7_SHIFT (0U) +#define MMDC_MPSWDRDR7_DUM_RD7(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPSWDRDR7_DUM_RD7_SHIFT)) & MMDC_MPSWDRDR7_DUM_RD7_MASK) + +/*! @name MPMUR0 - MMDC PHY Measure Unit Register */ +#define MMDC_MPMUR0_MU_BYP_VAL_MASK (0x3FFU) +#define MMDC_MPMUR0_MU_BYP_VAL_SHIFT (0U) +#define MMDC_MPMUR0_MU_BYP_VAL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_MU_BYP_VAL_SHIFT)) & MMDC_MPMUR0_MU_BYP_VAL_MASK) +#define MMDC_MPMUR0_MU_BYP_EN_MASK (0x400U) +#define MMDC_MPMUR0_MU_BYP_EN_SHIFT (10U) +#define MMDC_MPMUR0_MU_BYP_EN(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_MU_BYP_EN_SHIFT)) & MMDC_MPMUR0_MU_BYP_EN_MASK) +#define MMDC_MPMUR0_FRC_MSR_MASK (0x800U) +#define MMDC_MPMUR0_FRC_MSR_SHIFT (11U) +#define MMDC_MPMUR0_FRC_MSR(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_FRC_MSR_SHIFT)) & MMDC_MPMUR0_FRC_MSR_MASK) +#define MMDC_MPMUR0_MU_UNIT_DEL_NUM_MASK (0x3FF0000U) +#define MMDC_MPMUR0_MU_UNIT_DEL_NUM_SHIFT (16U) +#define MMDC_MPMUR0_MU_UNIT_DEL_NUM(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPMUR0_MU_UNIT_DEL_NUM_SHIFT)) & MMDC_MPMUR0_MU_UNIT_DEL_NUM_MASK) + +/*! @name MPWRCADL - MMDC Write CA delay-line controller */ +#define MMDC_MPWRCADL_WR_CA0_DEL_MASK (0x3U) +#define MMDC_MPWRCADL_WR_CA0_DEL_SHIFT (0U) +#define MMDC_MPWRCADL_WR_CA0_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA0_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA0_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA1_DEL_MASK (0xCU) +#define MMDC_MPWRCADL_WR_CA1_DEL_SHIFT (2U) +#define MMDC_MPWRCADL_WR_CA1_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA1_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA1_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA2_DEL_MASK (0x30U) +#define MMDC_MPWRCADL_WR_CA2_DEL_SHIFT (4U) +#define MMDC_MPWRCADL_WR_CA2_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA2_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA2_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA3_DEL_MASK (0xC0U) +#define MMDC_MPWRCADL_WR_CA3_DEL_SHIFT (6U) +#define MMDC_MPWRCADL_WR_CA3_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA3_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA3_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA4_DEL_MASK (0x300U) +#define MMDC_MPWRCADL_WR_CA4_DEL_SHIFT (8U) +#define MMDC_MPWRCADL_WR_CA4_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA4_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA4_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA5_DEL_MASK (0xC00U) +#define MMDC_MPWRCADL_WR_CA5_DEL_SHIFT (10U) +#define MMDC_MPWRCADL_WR_CA5_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA5_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA5_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA6_DEL_MASK (0x3000U) +#define MMDC_MPWRCADL_WR_CA6_DEL_SHIFT (12U) +#define MMDC_MPWRCADL_WR_CA6_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA6_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA6_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA7_DEL_MASK (0xC000U) +#define MMDC_MPWRCADL_WR_CA7_DEL_SHIFT (14U) +#define MMDC_MPWRCADL_WR_CA7_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA7_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA7_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA8_DEL_MASK (0x30000U) +#define MMDC_MPWRCADL_WR_CA8_DEL_SHIFT (16U) +#define MMDC_MPWRCADL_WR_CA8_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA8_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA8_DEL_MASK) +#define MMDC_MPWRCADL_WR_CA9_DEL_MASK (0xC0000U) +#define MMDC_MPWRCADL_WR_CA9_DEL_SHIFT (18U) +#define MMDC_MPWRCADL_WR_CA9_DEL(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPWRCADL_WR_CA9_DEL_SHIFT)) & MMDC_MPWRCADL_WR_CA9_DEL_MASK) + +/*! @name MPDCCR - MMDC Duty Cycle Control Register */ +#define MMDC_MPDCCR_WR_DQS0_FT_DCC_MASK (0x7U) +#define MMDC_MPDCCR_WR_DQS0_FT_DCC_SHIFT (0U) +#define MMDC_MPDCCR_WR_DQS0_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_WR_DQS0_FT_DCC_SHIFT)) & MMDC_MPDCCR_WR_DQS0_FT_DCC_MASK) +#define MMDC_MPDCCR_WR_DQS1_FT_DCC_MASK (0x38U) +#define MMDC_MPDCCR_WR_DQS1_FT_DCC_SHIFT (3U) +#define MMDC_MPDCCR_WR_DQS1_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_WR_DQS1_FT_DCC_SHIFT)) & MMDC_MPDCCR_WR_DQS1_FT_DCC_MASK) +#define MMDC_MPDCCR_CK_FT0_DCC_MASK (0x7000U) +#define MMDC_MPDCCR_CK_FT0_DCC_SHIFT (12U) +#define MMDC_MPDCCR_CK_FT0_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_CK_FT0_DCC_SHIFT)) & MMDC_MPDCCR_CK_FT0_DCC_MASK) +#define MMDC_MPDCCR_CK_FT1_DCC_MASK (0x70000U) +#define MMDC_MPDCCR_CK_FT1_DCC_SHIFT (16U) +#define MMDC_MPDCCR_CK_FT1_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_CK_FT1_DCC_SHIFT)) & MMDC_MPDCCR_CK_FT1_DCC_MASK) +#define MMDC_MPDCCR_RD_DQS0_FT_DCC_MASK (0x380000U) +#define MMDC_MPDCCR_RD_DQS0_FT_DCC_SHIFT (19U) +#define MMDC_MPDCCR_RD_DQS0_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_RD_DQS0_FT_DCC_SHIFT)) & MMDC_MPDCCR_RD_DQS0_FT_DCC_MASK) +#define MMDC_MPDCCR_RD_DQS1_FT_DCC_MASK (0x1C00000U) +#define MMDC_MPDCCR_RD_DQS1_FT_DCC_SHIFT (22U) +#define MMDC_MPDCCR_RD_DQS1_FT_DCC(x) (((uint32_t)(((uint32_t)(x)) << MMDC_MPDCCR_RD_DQS1_FT_DCC_SHIFT)) & MMDC_MPDCCR_RD_DQS1_FT_DCC_MASK) + + +/*! + * @} + */ /* end of group MMDC_Register_Masks */ + + +/* MMDC - Peripheral instance base addresses */ +/** Peripheral MMDC base address */ +#define MMDC_BASE (0x21B0000u) +/** Peripheral MMDC base pointer */ +#define MMDC ((MMDC_Type *)MMDC_BASE) +/** Array initializer of MMDC peripheral base addresses */ +#define MMDC_BASE_ADDRS { MMDC_BASE } +/** Array initializer of MMDC peripheral base pointers */ +#define MMDC_BASE_PTRS { MMDC } +/* MMDC max frequency (MHz). */ +#define MMDC_MAX_FREQUENCY (400) +/* MMDC device start address. */ +#define MMDC_DEVICE_START_ADDRESS (0x80000000U) + + +/*! + * @} + */ /* end of group MMDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OCOTP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer + * @{ + */ + +/** OCOTP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< OTP Controller Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */ + __IO uint32_t TIMING; /**< OTP Controller Timing Register, offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DATA; /**< OTP Controller Write Data Register, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t READ_CTRL; /**< OTP Controller Read Control Register, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t READ_FUSE_DATA; /**< OTP Controller Read Fuse Data Register, offset: 0x40 */ + uint8_t RESERVED_3[12]; + __IO uint32_t SW_STICKY; /**< Sticky bit Register, offset: 0x50 */ + uint8_t RESERVED_4[12]; + __IO uint32_t SCS; /**< Software Controllable Signals Register, offset: 0x60 */ + __IO uint32_t SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */ + __IO uint32_t SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */ + __IO uint32_t SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */ + __IO uint32_t CRC_ADDR; /**< OTP Controller CRC Test Address, offset: 0x70 */ + uint8_t RESERVED_5[12]; + __IO uint32_t CRC_VALUE; /**< OTP Controller CRC Value Register, offset: 0x80 */ + uint8_t RESERVED_6[12]; + __I uint32_t VERSION; /**< OTP Controller Version Register, offset: 0x90 */ + uint8_t RESERVED_7[108]; + __IO uint32_t TIMING2; /**< OTP Controller Timing Register 2, offset: 0x100 */ + uint8_t RESERVED_8[764]; + __IO uint32_t LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */ + uint8_t RESERVED_9[12]; + __IO uint32_t CFG0; /**< Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CFG1; /**< Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420 */ + uint8_t RESERVED_11[12]; + __IO uint32_t CFG2; /**< Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.), offset: 0x430 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CFG3; /**< Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.), offset: 0x440 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CFG4; /**< Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CFG5; /**< Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CFG6; /**< Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.), offset: 0x470 */ + uint8_t RESERVED_16[12]; + __IO uint32_t MEM0; /**< Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480 */ + uint8_t RESERVED_17[12]; + __IO uint32_t MEM1; /**< Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490 */ + uint8_t RESERVED_18[12]; + __IO uint32_t MEM2; /**< Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0 */ + uint8_t RESERVED_19[12]; + __IO uint32_t MEM3; /**< Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0 */ + uint8_t RESERVED_20[12]; + __IO uint32_t MEM4; /**< Value of OTP Bank1 Word4 (Memory Related Info.), offset: 0x4C0 */ + uint8_t RESERVED_21[12]; + __IO uint32_t ANA0; /**< Value of OTP Bank1 Word5 (Memory Related Info.), offset: 0x4D0 */ + uint8_t RESERVED_22[12]; + __IO uint32_t ANA1; /**< Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.), offset: 0x4E0 */ + uint8_t RESERVED_23[12]; + __IO uint32_t ANA2; /**< Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.), offset: 0x4F0 */ + uint8_t RESERVED_24[12]; + __IO uint32_t OTPMK0; /**< Value of OTP Bank2 Word0 (OTPMK Key), offset: 0x500 */ + uint8_t RESERVED_25[12]; + __IO uint32_t OTPMK1; /**< Value of OTP Bank2 Word1 (OTPMK Key), offset: 0x510 */ + uint8_t RESERVED_26[12]; + __IO uint32_t OTPMK2; /**< Value of OTP Bank2 Word2 (OTPMK Key), offset: 0x520 */ + uint8_t RESERVED_27[12]; + __IO uint32_t OTPMK3; /**< Value of OTP Bank2 Word3 (OTPMK Key), offset: 0x530 */ + uint8_t RESERVED_28[12]; + __IO uint32_t OTPMK4; /**< Value of OTP Bank2 Word4 (OTPMK Key), offset: 0x540 */ + uint8_t RESERVED_29[12]; + __IO uint32_t OTPMK5; /**< Value of OTP Bank2 Word5 (OTPMK Key), offset: 0x550 */ + uint8_t RESERVED_30[12]; + __IO uint32_t OTPMK6; /**< Value of OTP Bank2 Word6 (OTPMK Key), offset: 0x560 */ + uint8_t RESERVED_31[12]; + __IO uint32_t OTPMK7; /**< Value of OTP Bank2 Word7 (OTPMK Key), offset: 0x570 */ + uint8_t RESERVED_32[12]; + __IO uint32_t SRK0; /**< Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580 */ + uint8_t RESERVED_33[12]; + __IO uint32_t SRK1; /**< Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590 */ + uint8_t RESERVED_34[12]; + __IO uint32_t SRK2; /**< Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0 */ + uint8_t RESERVED_35[12]; + __IO uint32_t SRK3; /**< Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0 */ + uint8_t RESERVED_36[12]; + __IO uint32_t SRK4; /**< Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0 */ + uint8_t RESERVED_37[12]; + __IO uint32_t SRK5; /**< Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0 */ + uint8_t RESERVED_38[12]; + __IO uint32_t SRK6; /**< Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0 */ + uint8_t RESERVED_39[12]; + __IO uint32_t SRK7; /**< Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0 */ + uint8_t RESERVED_40[12]; + __IO uint32_t SJC_RESP0; /**< Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600 */ + uint8_t RESERVED_41[12]; + __IO uint32_t SJC_RESP1; /**< Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610 */ + uint8_t RESERVED_42[12]; + __IO uint32_t MAC0; /**< Value of OTP Bank4 Word2 (MAC Address), offset: 0x620 */ + uint8_t RESERVED_43[12]; + __IO uint32_t MAC1; /**< Value of OTP Bank4 Word3 (MAC Address), offset: 0x630 */ + uint8_t RESERVED_44[12]; + __IO uint32_t MAC; /**< Value of OTP Bank4 Word4 (MAC Address) (OCOTP_RESERVED), offset: 0x640 */ + uint8_t RESERVED_45[12]; + __IO uint32_t CRC; /**< Value of OTP Bank4 Word5 (CRC Key), offset: 0x650 */ + uint8_t RESERVED_46[12]; + __IO uint32_t GP1; /**< Value of OTP Bank4 Word6 (General Purpose Customer Defined Info), offset: 0x660 */ + uint8_t RESERVED_47[12]; + __IO uint32_t GP2; /**< Value of OTP Bank4 Word7 (General Purpose Customer Defined Info), offset: 0x670 */ + uint8_t RESERVED_48[12]; + __IO uint32_t SW_GP0; /**< Value of OTP Bank5 Word0 (SW GP), offset: 0x680 */ + uint8_t RESERVED_49[12]; + __IO uint32_t SW_GP1; /**< Value of OTP Bank5 Word1 (SW GP), offset: 0x690 */ + uint8_t RESERVED_50[12]; + __IO uint32_t SW_GP2; /**< Value of OTP Bank5 Word2 (SW GP), offset: 0x6A0 */ + uint8_t RESERVED_51[12]; + __IO uint32_t SW_GP3; /**< Value of OTP Bank5 Word3 (SW GP), offset: 0x6B0 */ + uint8_t RESERVED_52[12]; + __IO uint32_t SW_GP4; /**< Value of OTP Bank5 Word4 (SW GP), offset: 0x6C0 */ + uint8_t RESERVED_53[12]; + __IO uint32_t MISC_CONF; /**< Value of OTP Bank5 Word5 (Misc Conf), offset: 0x6D0 */ + uint8_t RESERVED_54[12]; + __IO uint32_t FIELD_RETURN; /**< Value of OTP Bank5 Word6 (Field Return), offset: 0x6E0 */ + uint8_t RESERVED_55[12]; + __IO uint32_t SRK_REVOKE; /**< Value of OTP Bank5 Word7 (SRK Revoke), offset: 0x6F0 */ + uint8_t RESERVED_56[268]; + __IO uint32_t ROM_PATCH0; /**< Value of OTP Bank6 Word0 (ROM Patch), offset: 0x800 */ + uint8_t RESERVED_57[12]; + __IO uint32_t ROM_PATCH1; /**< Value of OTP Bank6 Word1 (ROM Patch), offset: 0x810 */ + uint8_t RESERVED_58[12]; + __IO uint32_t ROM_PATCH2; /**< Value of OTP Bank6 Word2 (ROM Patch), offset: 0x820 */ + uint8_t RESERVED_59[12]; + __IO uint32_t ROM_PATCH3; /**< Value of OTP Bank6 Word3 (ROM Patch), offset: 0x830 */ + uint8_t RESERVED_60[12]; + __IO uint32_t ROM_PATCH4; /**< Value of OTP Bank6 Word4 (ROM Patch), offset: 0x840 */ + uint8_t RESERVED_61[12]; + __IO uint32_t ROM_PATCH5; /**< Value of OTP Bank6 Word5 (ROM Patch), offset: 0x850 */ + uint8_t RESERVED_62[12]; + __IO uint32_t ROM_PATCH6; /**< Value of OTP Bank6 Word6 (ROM Patch), offset: 0x860 */ + uint8_t RESERVED_63[12]; + __IO uint32_t ROM_PATCH7; /**< Value of OTP Bank6 Word7 (ROM Patch), offset: 0x870 */ + uint8_t RESERVED_64[12]; + __IO uint32_t GP3_0; /**< Value of OTP Bank7 Word0 (General Purpose Customer Defined Info), offset: 0x880 */ + uint8_t RESERVED_65[12]; + __IO uint32_t GP3_1; /**< Value of OTP Bank7 Word1 (General Purpose Customer Defined Info), offset: 0x890 */ + uint8_t RESERVED_66[12]; + __IO uint32_t GP3_2; /**< Value of OTP Bank7 Word2 (General Purpose Customer Defined Info), offset: 0x8A0 */ + uint8_t RESERVED_67[12]; + __IO uint32_t GP3_3; /**< Value of OTP Bank7 Word3 (General Purpose Customer Defined Info), offset: 0x8B0 */ + uint8_t RESERVED_68[12]; + __IO uint32_t GP3_4; /**< Value of OTP Bank8 Word4 (General Purpose Customer Defined Info), offset: 0x8C0 */ + uint8_t RESERVED_69[12]; + __IO uint32_t GP4_0; /**< Value of OTP Bank7 Word5 (General Purpose Customer Defined Info), offset: 0x8D0 */ + uint8_t RESERVED_70[12]; + __IO uint32_t GP4_1; /**< Value of OTP Bank7 Word6 (General Purpose Customer Defined Info), offset: 0x8E0 */ + uint8_t RESERVED_71[12]; + __IO uint32_t GP4_2; /**< Value of OTP Bank7 Word7 (General Purpose Customer Defined Info), offset: 0x8F0 */ +} OCOTP_Type; + +/* ---------------------------------------------------------------------------- + -- OCOTP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Register_Masks OCOTP Register Masks + * @{ + */ + +/*! @name CTRL - OTP Controller Control Register */ +#define OCOTP_CTRL_ADDR_MASK (0x7FU) +#define OCOTP_CTRL_ADDR_SHIFT (0U) +#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK) +#define OCOTP_CTRL_RSVD0_MASK (0x80U) +#define OCOTP_CTRL_RSVD0_SHIFT (7U) +#define OCOTP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RSVD0_SHIFT)) & OCOTP_CTRL_RSVD0_MASK) +#define OCOTP_CTRL_BUSY_MASK (0x100U) +#define OCOTP_CTRL_BUSY_SHIFT (8U) +#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK) +#define OCOTP_CTRL_ERROR_MASK (0x200U) +#define OCOTP_CTRL_ERROR_SHIFT (9U) +#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK) +#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CRC_TEST_SHIFT)) & OCOTP_CTRL_CRC_TEST_MASK) +#define OCOTP_CTRL_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CRC_FAIL_SHIFT)) & OCOTP_CTRL_CRC_FAIL_MASK) +#define OCOTP_CTRL_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RSVD1_SHIFT)) & OCOTP_CTRL_RSVD1_MASK) +#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK) + +/*! @name CTRL_SET - OTP Controller Control Register */ +#define OCOTP_CTRL_SET_ADDR_MASK (0x7FU) +#define OCOTP_CTRL_SET_ADDR_SHIFT (0U) +#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK) +#define OCOTP_CTRL_SET_RSVD0_MASK (0x80U) +#define OCOTP_CTRL_SET_RSVD0_SHIFT (7U) +#define OCOTP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RSVD0_SHIFT)) & OCOTP_CTRL_SET_RSVD0_MASK) +#define OCOTP_CTRL_SET_BUSY_MASK (0x100U) +#define OCOTP_CTRL_SET_BUSY_SHIFT (8U) +#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK) +#define OCOTP_CTRL_SET_ERROR_MASK (0x200U) +#define OCOTP_CTRL_SET_ERROR_SHIFT (9U) +#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_SET_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_SET_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_SET_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_CRC_TEST_SHIFT)) & OCOTP_CTRL_SET_CRC_TEST_MASK) +#define OCOTP_CTRL_SET_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_SET_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_SET_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_CRC_FAIL_SHIFT)) & OCOTP_CTRL_SET_CRC_FAIL_MASK) +#define OCOTP_CTRL_SET_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_SET_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RSVD1_SHIFT)) & OCOTP_CTRL_SET_RSVD1_MASK) +#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK) + +/*! @name CTRL_CLR - OTP Controller Control Register */ +#define OCOTP_CTRL_CLR_ADDR_MASK (0x7FU) +#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U) +#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK) +#define OCOTP_CTRL_CLR_RSVD0_MASK (0x80U) +#define OCOTP_CTRL_CLR_RSVD0_SHIFT (7U) +#define OCOTP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RSVD0_SHIFT)) & OCOTP_CTRL_CLR_RSVD0_MASK) +#define OCOTP_CTRL_CLR_BUSY_MASK (0x100U) +#define OCOTP_CTRL_CLR_BUSY_SHIFT (8U) +#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK) +#define OCOTP_CTRL_CLR_ERROR_MASK (0x200U) +#define OCOTP_CTRL_CLR_ERROR_SHIFT (9U) +#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_CLR_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_CLR_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_CLR_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_CRC_TEST_SHIFT)) & OCOTP_CTRL_CLR_CRC_TEST_MASK) +#define OCOTP_CTRL_CLR_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_CLR_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_CLR_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_CRC_FAIL_SHIFT)) & OCOTP_CTRL_CLR_CRC_FAIL_MASK) +#define OCOTP_CTRL_CLR_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_CLR_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RSVD1_SHIFT)) & OCOTP_CTRL_CLR_RSVD1_MASK) +#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK) + +/*! @name CTRL_TOG - OTP Controller Control Register */ +#define OCOTP_CTRL_TOG_ADDR_MASK (0x7FU) +#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U) +#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK) +#define OCOTP_CTRL_TOG_RSVD0_MASK (0x80U) +#define OCOTP_CTRL_TOG_RSVD0_SHIFT (7U) +#define OCOTP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RSVD0_SHIFT)) & OCOTP_CTRL_TOG_RSVD0_MASK) +#define OCOTP_CTRL_TOG_BUSY_MASK (0x100U) +#define OCOTP_CTRL_TOG_BUSY_SHIFT (8U) +#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK) +#define OCOTP_CTRL_TOG_ERROR_MASK (0x200U) +#define OCOTP_CTRL_TOG_ERROR_SHIFT (9U) +#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_TOG_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_TOG_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_TOG_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_CRC_TEST_SHIFT)) & OCOTP_CTRL_TOG_CRC_TEST_MASK) +#define OCOTP_CTRL_TOG_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_TOG_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_TOG_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_CRC_FAIL_SHIFT)) & OCOTP_CTRL_TOG_CRC_FAIL_MASK) +#define OCOTP_CTRL_TOG_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_TOG_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RSVD1_SHIFT)) & OCOTP_CTRL_TOG_RSVD1_MASK) +#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK) + +/*! @name TIMING - OTP Controller Timing Register */ +#define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU) +#define OCOTP_TIMING_STROBE_PROG_SHIFT (0U) +#define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK) +#define OCOTP_TIMING_RELAX_MASK (0xF000U) +#define OCOTP_TIMING_RELAX_SHIFT (12U) +#define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK) +#define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U) +#define OCOTP_TIMING_STROBE_READ_SHIFT (16U) +#define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK) +#define OCOTP_TIMING_WAIT_MASK (0xFC00000U) +#define OCOTP_TIMING_WAIT_SHIFT (22U) +#define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK) +#define OCOTP_TIMING_RSRVD0_MASK (0xF0000000U) +#define OCOTP_TIMING_RSRVD0_SHIFT (28U) +#define OCOTP_TIMING_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RSRVD0_SHIFT)) & OCOTP_TIMING_RSRVD0_MASK) + +/*! @name DATA - OTP Controller Write Data Register */ +#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_DATA_DATA_SHIFT (0U) +#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK) + +/*! @name READ_CTRL - OTP Controller Read Control Register */ +#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) +#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) +#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK) +#define OCOTP_READ_CTRL_RSVD0_MASK (0xFFFFFFFEU) +#define OCOTP_READ_CTRL_RSVD0_SHIFT (1U) +#define OCOTP_READ_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_RSVD0_SHIFT)) & OCOTP_READ_CTRL_RSVD0_MASK) + +/*! @name READ_FUSE_DATA - OTP Controller Read Fuse Data Register */ +#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) +#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK) + +/*! @name SW_STICKY - Sticky bit Register */ +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK) +#define OCOTP_SW_STICKY_RSVD0_MASK (0xFFFFFFE0U) +#define OCOTP_SW_STICKY_RSVD0_SHIFT (5U) +#define OCOTP_SW_STICKY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_RSVD0_SHIFT)) & OCOTP_SW_STICKY_RSVD0_MASK) + +/*! @name SCS - Software Controllable Signals Register */ +#define OCOTP_SCS_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK) +#define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SPARE_SHIFT (1U) +#define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK) +#define OCOTP_SCS_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_LOCK_SHIFT (31U) +#define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK) + +/*! @name SCS_SET - Software Controllable Signals Register */ +#define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK) +#define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SET_SPARE_SHIFT (1U) +#define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK) +#define OCOTP_SCS_SET_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_SET_LOCK_SHIFT (31U) +#define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK) + +/*! @name SCS_CLR - Software Controllable Signals Register */ +#define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK) +#define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_CLR_SPARE_SHIFT (1U) +#define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK) +#define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_CLR_LOCK_SHIFT (31U) +#define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK) + +/*! @name SCS_TOG - Software Controllable Signals Register */ +#define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK) +#define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_TOG_SPARE_SHIFT (1U) +#define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK) +#define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_TOG_LOCK_SHIFT (31U) +#define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK) + +/*! @name CRC_ADDR - OTP Controller CRC Test Address */ +#define OCOTP_CRC_ADDR_DATA_START_ADDR_MASK (0xFFU) +#define OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT (0U) +#define OCOTP_CRC_ADDR_DATA_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT)) & OCOTP_CRC_ADDR_DATA_START_ADDR_MASK) +#define OCOTP_CRC_ADDR_DATA_END_ADDR_MASK (0xFF00U) +#define OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT (8U) +#define OCOTP_CRC_ADDR_DATA_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT)) & OCOTP_CRC_ADDR_DATA_END_ADDR_MASK) +#define OCOTP_CRC_ADDR_CRC_ADDR_MASK (0x70000U) +#define OCOTP_CRC_ADDR_CRC_ADDR_SHIFT (16U) +#define OCOTP_CRC_ADDR_CRC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_CRC_ADDR_SHIFT)) & OCOTP_CRC_ADDR_CRC_ADDR_MASK) +#define OCOTP_CRC_ADDR_OTPMK_CRC_MASK (0x80000U) +#define OCOTP_CRC_ADDR_OTPMK_CRC_SHIFT (19U) +#define OCOTP_CRC_ADDR_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_OTPMK_CRC_SHIFT)) & OCOTP_CRC_ADDR_OTPMK_CRC_MASK) +#define OCOTP_CRC_ADDR_RSVD0_MASK (0xFFF00000U) +#define OCOTP_CRC_ADDR_RSVD0_SHIFT (20U) +#define OCOTP_CRC_ADDR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_RSVD0_SHIFT)) & OCOTP_CRC_ADDR_RSVD0_MASK) + +/*! @name CRC_VALUE - OTP Controller CRC Value Register */ +#define OCOTP_CRC_VALUE_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_CRC_VALUE_DATA_SHIFT (0U) +#define OCOTP_CRC_VALUE_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_VALUE_DATA_SHIFT)) & OCOTP_CRC_VALUE_DATA_MASK) + +/*! @name VERSION - OTP Controller Version Register */ +#define OCOTP_VERSION_STEP_MASK (0xFFFFU) +#define OCOTP_VERSION_STEP_SHIFT (0U) +#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK) +#define OCOTP_VERSION_MINOR_MASK (0xFF0000U) +#define OCOTP_VERSION_MINOR_SHIFT (16U) +#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK) +#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U) +#define OCOTP_VERSION_MAJOR_SHIFT (24U) +#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK) + +/*! @name TIMING2 - OTP Controller Timing Register 2 */ +#define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU) +#define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U) +#define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK) +#define OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U) +#define OCOTP_TIMING2_RELAX_READ_SHIFT (16U) +#define OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK) +#define OCOTP_TIMING2_RELAX1_MASK (0x1FC00000U) +#define OCOTP_TIMING2_RELAX1_SHIFT (22U) +#define OCOTP_TIMING2_RELAX1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX1_SHIFT)) & OCOTP_TIMING2_RELAX1_MASK) + +/*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */ +#define OCOTP_LOCK_TESTER_MASK (0x3U) +#define OCOTP_LOCK_TESTER_SHIFT (0U) +#define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK) +#define OCOTP_LOCK_BOOT_CFG_MASK (0xCU) +#define OCOTP_LOCK_BOOT_CFG_SHIFT (2U) +#define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK) +#define OCOTP_LOCK_MEM_TRIM_MASK (0x30U) +#define OCOTP_LOCK_MEM_TRIM_SHIFT (4U) +#define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK) +#define OCOTP_LOCK_SJC_RESP_MASK (0x40U) +#define OCOTP_LOCK_SJC_RESP_SHIFT (6U) +#define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK) +#define OCOTP_LOCK_RSVD0_MASK (0x80U) +#define OCOTP_LOCK_RSVD0_SHIFT (7U) +#define OCOTP_LOCK_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_RSVD0_SHIFT)) & OCOTP_LOCK_RSVD0_MASK) +#define OCOTP_LOCK_MAC_ADDR_MASK (0x300U) +#define OCOTP_LOCK_MAC_ADDR_SHIFT (8U) +#define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK) +#define OCOTP_LOCK_GP1_MASK (0xC00U) +#define OCOTP_LOCK_GP1_SHIFT (10U) +#define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK) +#define OCOTP_LOCK_GP2_MASK (0x3000U) +#define OCOTP_LOCK_GP2_SHIFT (12U) +#define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK) +#define OCOTP_LOCK_SRK_MASK (0x4000U) +#define OCOTP_LOCK_SRK_SHIFT (14U) +#define OCOTP_LOCK_SRK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SRK_SHIFT)) & OCOTP_LOCK_SRK_MASK) +#define OCOTP_LOCK_GP3_MASK (0x8000U) +#define OCOTP_LOCK_GP3_SHIFT (15U) +#define OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK) +#define OCOTP_LOCK_SW_GP_MASK (0x10000U) +#define OCOTP_LOCK_SW_GP_SHIFT (16U) +#define OCOTP_LOCK_SW_GP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP_SHIFT)) & OCOTP_LOCK_SW_GP_MASK) +#define OCOTP_LOCK_OTPMK_MASK (0x20000U) +#define OCOTP_LOCK_OTPMK_SHIFT (17U) +#define OCOTP_LOCK_OTPMK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_SHIFT)) & OCOTP_LOCK_OTPMK_MASK) +#define OCOTP_LOCK_ANALOG_MASK (0xC0000U) +#define OCOTP_LOCK_ANALOG_SHIFT (18U) +#define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK) +#define OCOTP_LOCK_OTPMK_CRC_MASK (0x100000U) +#define OCOTP_LOCK_OTPMK_CRC_SHIFT (20U) +#define OCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK) +#define OCOTP_LOCK_ROM_PATCH_MASK (0x200000U) +#define OCOTP_LOCK_ROM_PATCH_SHIFT (21U) +#define OCOTP_LOCK_ROM_PATCH(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ROM_PATCH_SHIFT)) & OCOTP_LOCK_ROM_PATCH_MASK) +#define OCOTP_LOCK_MISC_CONF_MASK (0x400000U) +#define OCOTP_LOCK_MISC_CONF_SHIFT (22U) +#define OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK) +#define OCOTP_LOCK_GP4_MASK (0x800000U) +#define OCOTP_LOCK_GP4_SHIFT (23U) +#define OCOTP_LOCK_GP4(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP4_SHIFT)) & OCOTP_LOCK_GP4_MASK) +#define OCOTP_LOCK_PIN_MASK (0x2000000U) +#define OCOTP_LOCK_PIN_SHIFT (25U) +#define OCOTP_LOCK_PIN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_PIN_SHIFT)) & OCOTP_LOCK_PIN_MASK) +#define OCOTP_LOCK_GP4_RLOCK_MASK (0x40000000U) +#define OCOTP_LOCK_GP4_RLOCK_SHIFT (30U) +#define OCOTP_LOCK_GP4_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP4_RLOCK_SHIFT)) & OCOTP_LOCK_GP4_RLOCK_MASK) +#define OCOTP_LOCK_GP3_RLOCK_MASK (0x80000000U) +#define OCOTP_LOCK_GP3_RLOCK_SHIFT (31U) +#define OCOTP_LOCK_GP3_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_RLOCK_SHIFT)) & OCOTP_LOCK_GP3_RLOCK_MASK) + +/*! @name CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG0_BITS_SHIFT (0U) +#define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK) + +/*! @name CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG1_BITS_SHIFT (0U) +#define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK) + +/*! @name CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG2_BITS_SHIFT (0U) +#define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK) + +/*! @name CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG3_BITS_SHIFT (0U) +#define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK) + +/*! @name CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG4_BITS_SHIFT (0U) +#define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK) + +/*! @name CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG5_BITS_SHIFT (0U) +#define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK) + +/*! @name CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) */ +#define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG6_BITS_SHIFT (0U) +#define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK) + +/*! @name MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) */ +#define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM0_BITS_SHIFT (0U) +#define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK) + +/*! @name MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) */ +#define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM1_BITS_SHIFT (0U) +#define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK) + +/*! @name MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) */ +#define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM2_BITS_SHIFT (0U) +#define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK) + +/*! @name MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) */ +#define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM3_BITS_SHIFT (0U) +#define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK) + +/*! @name MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) */ +#define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM4_BITS_SHIFT (0U) +#define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK) + +/*! @name ANA0 - Value of OTP Bank1 Word5 (Memory Related Info.) */ +#define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA0_BITS_SHIFT (0U) +#define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK) + +/*! @name ANA1 - Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.) */ +#define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA1_BITS_SHIFT (0U) +#define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK) + +/*! @name ANA2 - Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) */ +#define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA2_BITS_SHIFT (0U) +#define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK) + +/*! @name OTPMK0 - Value of OTP Bank2 Word0 (OTPMK Key) */ +#define OCOTP_OTPMK0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK0_BITS_SHIFT (0U) +#define OCOTP_OTPMK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK0_BITS_SHIFT)) & OCOTP_OTPMK0_BITS_MASK) + +/*! @name OTPMK1 - Value of OTP Bank2 Word1 (OTPMK Key) */ +#define OCOTP_OTPMK1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK1_BITS_SHIFT (0U) +#define OCOTP_OTPMK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK1_BITS_SHIFT)) & OCOTP_OTPMK1_BITS_MASK) + +/*! @name OTPMK2 - Value of OTP Bank2 Word2 (OTPMK Key) */ +#define OCOTP_OTPMK2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK2_BITS_SHIFT (0U) +#define OCOTP_OTPMK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK2_BITS_SHIFT)) & OCOTP_OTPMK2_BITS_MASK) + +/*! @name OTPMK3 - Value of OTP Bank2 Word3 (OTPMK Key) */ +#define OCOTP_OTPMK3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK3_BITS_SHIFT (0U) +#define OCOTP_OTPMK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK3_BITS_SHIFT)) & OCOTP_OTPMK3_BITS_MASK) + +/*! @name OTPMK4 - Value of OTP Bank2 Word4 (OTPMK Key) */ +#define OCOTP_OTPMK4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK4_BITS_SHIFT (0U) +#define OCOTP_OTPMK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK4_BITS_SHIFT)) & OCOTP_OTPMK4_BITS_MASK) + +/*! @name OTPMK5 - Value of OTP Bank2 Word5 (OTPMK Key) */ +#define OCOTP_OTPMK5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK5_BITS_SHIFT (0U) +#define OCOTP_OTPMK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK5_BITS_SHIFT)) & OCOTP_OTPMK5_BITS_MASK) + +/*! @name OTPMK6 - Value of OTP Bank2 Word6 (OTPMK Key) */ +#define OCOTP_OTPMK6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK6_BITS_SHIFT (0U) +#define OCOTP_OTPMK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK6_BITS_SHIFT)) & OCOTP_OTPMK6_BITS_MASK) + +/*! @name OTPMK7 - Value of OTP Bank2 Word7 (OTPMK Key) */ +#define OCOTP_OTPMK7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK7_BITS_SHIFT (0U) +#define OCOTP_OTPMK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK7_BITS_SHIFT)) & OCOTP_OTPMK7_BITS_MASK) + +/*! @name SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) */ +#define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK0_BITS_SHIFT (0U) +#define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK) + +/*! @name SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) */ +#define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK1_BITS_SHIFT (0U) +#define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK) + +/*! @name SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) */ +#define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK2_BITS_SHIFT (0U) +#define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK) + +/*! @name SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) */ +#define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK3_BITS_SHIFT (0U) +#define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK) + +/*! @name SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) */ +#define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK4_BITS_SHIFT (0U) +#define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK) + +/*! @name SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) */ +#define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK5_BITS_SHIFT (0U) +#define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK) + +/*! @name SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) */ +#define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK6_BITS_SHIFT (0U) +#define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK) + +/*! @name SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) */ +#define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK7_BITS_SHIFT (0U) +#define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK) + +/*! @name SJC_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) */ +#define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP0_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK) + +/*! @name SJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) */ +#define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP1_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK) + +/*! @name MAC0 - Value of OTP Bank4 Word2 (MAC Address) */ +#define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC0_BITS_SHIFT (0U) +#define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK) + +/*! @name MAC1 - Value of OTP Bank4 Word3 (MAC Address) */ +#define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC1_BITS_SHIFT (0U) +#define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK) + +/*! @name MAC - Value of OTP Bank4 Word4 (MAC Address) (OCOTP_RESERVED) */ +#define OCOTP_MAC_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC_BITS_SHIFT (0U) +#define OCOTP_MAC_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC_BITS_SHIFT)) & OCOTP_MAC_BITS_MASK) + +/*! @name CRC - Value of OTP Bank4 Word5 (CRC Key) */ +#define OCOTP_CRC_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CRC_BITS_SHIFT (0U) +#define OCOTP_CRC_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_BITS_SHIFT)) & OCOTP_CRC_BITS_MASK) + +/*! @name GP1 - Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) */ +#define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP1_BITS_SHIFT (0U) +#define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK) + +/*! @name GP2 - Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) */ +#define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP2_BITS_SHIFT (0U) +#define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK) + +/*! @name SW_GP0 - Value of OTP Bank5 Word0 (SW GP) */ +#define OCOTP_SW_GP0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP0_BITS_SHIFT (0U) +#define OCOTP_SW_GP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP0_BITS_SHIFT)) & OCOTP_SW_GP0_BITS_MASK) + +/*! @name SW_GP1 - Value of OTP Bank5 Word1 (SW GP) */ +#define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP1_BITS_SHIFT (0U) +#define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK) + +/*! @name SW_GP2 - Value of OTP Bank5 Word2 (SW GP) */ +#define OCOTP_SW_GP2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP2_BITS_SHIFT (0U) +#define OCOTP_SW_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP2_BITS_SHIFT)) & OCOTP_SW_GP2_BITS_MASK) + +/*! @name SW_GP3 - Value of OTP Bank5 Word3 (SW GP) */ +#define OCOTP_SW_GP3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP3_BITS_SHIFT (0U) +#define OCOTP_SW_GP3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP3_BITS_SHIFT)) & OCOTP_SW_GP3_BITS_MASK) + +/*! @name SW_GP4 - Value of OTP Bank5 Word4 (SW GP) */ +#define OCOTP_SW_GP4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP4_BITS_SHIFT (0U) +#define OCOTP_SW_GP4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP4_BITS_SHIFT)) & OCOTP_SW_GP4_BITS_MASK) + +/*! @name MISC_CONF - Value of OTP Bank5 Word5 (Misc Conf) */ +#define OCOTP_MISC_CONF_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MISC_CONF_BITS_SHIFT (0U) +#define OCOTP_MISC_CONF_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF_BITS_SHIFT)) & OCOTP_MISC_CONF_BITS_MASK) + +/*! @name FIELD_RETURN - Value of OTP Bank5 Word6 (Field Return) */ +#define OCOTP_FIELD_RETURN_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_FIELD_RETURN_BITS_SHIFT (0U) +#define OCOTP_FIELD_RETURN_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FIELD_RETURN_BITS_SHIFT)) & OCOTP_FIELD_RETURN_BITS_MASK) + +/*! @name SRK_REVOKE - Value of OTP Bank5 Word7 (SRK Revoke) */ +#define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK_REVOKE_BITS_SHIFT (0U) +#define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK) + +/*! @name ROM_PATCH0 - Value of OTP Bank6 Word0 (ROM Patch) */ +#define OCOTP_ROM_PATCH0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH0_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH0_BITS_SHIFT)) & OCOTP_ROM_PATCH0_BITS_MASK) + +/*! @name ROM_PATCH1 - Value of OTP Bank6 Word1 (ROM Patch) */ +#define OCOTP_ROM_PATCH1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH1_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH1_BITS_SHIFT)) & OCOTP_ROM_PATCH1_BITS_MASK) + +/*! @name ROM_PATCH2 - Value of OTP Bank6 Word2 (ROM Patch) */ +#define OCOTP_ROM_PATCH2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH2_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH2_BITS_SHIFT)) & OCOTP_ROM_PATCH2_BITS_MASK) + +/*! @name ROM_PATCH3 - Value of OTP Bank6 Word3 (ROM Patch) */ +#define OCOTP_ROM_PATCH3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH3_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH3_BITS_SHIFT)) & OCOTP_ROM_PATCH3_BITS_MASK) + +/*! @name ROM_PATCH4 - Value of OTP Bank6 Word4 (ROM Patch) */ +#define OCOTP_ROM_PATCH4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH4_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH4_BITS_SHIFT)) & OCOTP_ROM_PATCH4_BITS_MASK) + +/*! @name ROM_PATCH5 - Value of OTP Bank6 Word5 (ROM Patch) */ +#define OCOTP_ROM_PATCH5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH5_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH5_BITS_SHIFT)) & OCOTP_ROM_PATCH5_BITS_MASK) + +/*! @name ROM_PATCH6 - Value of OTP Bank6 Word6 (ROM Patch) */ +#define OCOTP_ROM_PATCH6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH6_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH6_BITS_SHIFT)) & OCOTP_ROM_PATCH6_BITS_MASK) + +/*! @name ROM_PATCH7 - Value of OTP Bank6 Word7 (ROM Patch) */ +#define OCOTP_ROM_PATCH7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH7_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH7_BITS_SHIFT)) & OCOTP_ROM_PATCH7_BITS_MASK) + +/*! @name GP3_0 - Value of OTP Bank7 Word0 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_0_BITS_SHIFT (0U) +#define OCOTP_GP3_0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_0_BITS_SHIFT)) & OCOTP_GP3_0_BITS_MASK) + +/*! @name GP3_1 - Value of OTP Bank7 Word1 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_1_BITS_SHIFT (0U) +#define OCOTP_GP3_1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_1_BITS_SHIFT)) & OCOTP_GP3_1_BITS_MASK) + +/*! @name GP3_2 - Value of OTP Bank7 Word2 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_2_BITS_SHIFT (0U) +#define OCOTP_GP3_2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_2_BITS_SHIFT)) & OCOTP_GP3_2_BITS_MASK) + +/*! @name GP3_3 - Value of OTP Bank7 Word3 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_3_BITS_SHIFT (0U) +#define OCOTP_GP3_3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_3_BITS_SHIFT)) & OCOTP_GP3_3_BITS_MASK) + +/*! @name GP3_4 - Value of OTP Bank8 Word4 (General Purpose Customer Defined Info) */ +#define OCOTP_GP3_4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP3_4_BITS_SHIFT (0U) +#define OCOTP_GP3_4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP3_4_BITS_SHIFT)) & OCOTP_GP3_4_BITS_MASK) + +/*! @name GP4_0 - Value of OTP Bank7 Word5 (General Purpose Customer Defined Info) */ +#define OCOTP_GP4_0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP4_0_BITS_SHIFT (0U) +#define OCOTP_GP4_0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP4_0_BITS_SHIFT)) & OCOTP_GP4_0_BITS_MASK) + +/*! @name GP4_1 - Value of OTP Bank7 Word6 (General Purpose Customer Defined Info) */ +#define OCOTP_GP4_1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP4_1_BITS_SHIFT (0U) +#define OCOTP_GP4_1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP4_1_BITS_SHIFT)) & OCOTP_GP4_1_BITS_MASK) + +/*! @name GP4_2 - Value of OTP Bank7 Word7 (General Purpose Customer Defined Info) */ +#define OCOTP_GP4_2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP4_2_BITS_SHIFT (0U) +#define OCOTP_GP4_2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP4_2_BITS_SHIFT)) & OCOTP_GP4_2_BITS_MASK) + + +/*! + * @} + */ /* end of group OCOTP_Register_Masks */ + + +/* OCOTP - Peripheral instance base addresses */ +/** Peripheral OCOTP base address */ +#define OCOTP_BASE (0x21BC000u) +/** Peripheral OCOTP base pointer */ +#define OCOTP ((OCOTP_Type *)OCOTP_BASE) +/** Array initializer of OCOTP peripheral base addresses */ +#define OCOTP_BASE_ADDRS { OCOTP_BASE } +/** Array initializer of OCOTP peripheral base pointers */ +#define OCOTP_BASE_PTRS { OCOTP } + +/*! + * @} + */ /* end of group OCOTP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PGC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Peripheral_Access_Layer PGC Peripheral Access Layer + * @{ + */ + +/** PGC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MEGA_CTRL; /**< PGC Mega Control Register, offset: 0x0 */ + __IO uint32_t MEGA_PUPSCR; /**< PGC Mega Power Up Sequence Control Register, offset: 0x4 */ + __IO uint32_t MEGA_PDNSCR; /**< PGC Mega Pull Down Sequence Control Register, offset: 0x8 */ + __IO uint32_t MEGA_SR; /**< PGC Mega Power Gating Controller Status Register, offset: 0xC */ + uint8_t RESERVED_0[112]; + __IO uint32_t CPU_CTRL; /**< PGC CPU Control Register, offset: 0x80 */ + __IO uint32_t CPU_PUPSCR; /**< PGC CPU Power Up Sequence Control Register, offset: 0x84 */ + __IO uint32_t CPU_PDNSCR; /**< PGC CPU Pull Down Sequence Control Register, offset: 0x88 */ + __IO uint32_t CPU_SR; /**< PGC CPU Power Gating Controller Status Register, offset: 0x8C */ +} PGC_Type; + +/* ---------------------------------------------------------------------------- + -- PGC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Register_Masks PGC Register Masks + * @{ + */ + +/*! @name MEGA_CTRL - PGC Mega Control Register */ +#define PGC_MEGA_CTRL_PCR_MASK (0x1U) +#define PGC_MEGA_CTRL_PCR_SHIFT (0U) +#define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK) + +/*! @name MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register */ +#define PGC_MEGA_PUPSCR_SW_MASK (0x3FU) +#define PGC_MEGA_PUPSCR_SW_SHIFT (0U) +#define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK) +#define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U) +#define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U) +#define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK) + +/*! @name MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register */ +#define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU) +#define PGC_MEGA_PDNSCR_ISO_SHIFT (0U) +#define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK) +#define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U) +#define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U) +#define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK) + +/*! @name MEGA_SR - PGC Mega Power Gating Controller Status Register */ +#define PGC_MEGA_SR_PSR_MASK (0x1U) +#define PGC_MEGA_SR_PSR_SHIFT (0U) +#define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK) + +/*! @name CPU_CTRL - PGC CPU Control Register */ +#define PGC_CPU_CTRL_PCR_MASK (0x1U) +#define PGC_CPU_CTRL_PCR_SHIFT (0U) +#define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK) + +/*! @name CPU_PUPSCR - PGC CPU Power Up Sequence Control Register */ +#define PGC_CPU_PUPSCR_SW_MASK (0x3FU) +#define PGC_CPU_PUPSCR_SW_SHIFT (0U) +#define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK) +#define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) +#define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U) +#define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK) + +/*! @name CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register */ +#define PGC_CPU_PDNSCR_ISO_MASK (0x3FU) +#define PGC_CPU_PDNSCR_ISO_SHIFT (0U) +#define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK) +#define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) +#define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U) +#define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK) + +/*! @name CPU_SR - PGC CPU Power Gating Controller Status Register */ +#define PGC_CPU_SR_PSR_MASK (0x1U) +#define PGC_CPU_SR_PSR_SHIFT (0U) +#define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK) + + +/*! + * @} + */ /* end of group PGC_Register_Masks */ + + +/* PGC - Peripheral instance base addresses */ +/** Peripheral PGC base address */ +#define PGC_BASE (0x20DC220u) +/** Peripheral PGC base pointer */ +#define PGC ((PGC_Type *)PGC_BASE) +/** Array initializer of PGC peripheral base addresses */ +#define PGC_BASE_ADDRS { PGC_BASE } +/** Array initializer of PGC peripheral base pointers */ +#define PGC_BASE_PTRS { PGC } + +/*! + * @} + */ /* end of group PGC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer + * @{ + */ + +/** PMU - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG_1P1; /**< Regulator 1P1 Register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __IO uint32_t REG_CORE; /**< Digital Regulator Core Register, offset: 0x30 */ + uint8_t RESERVED_3[300]; + __IO uint32_t LOWPWR_CTRL; /**< Low Power Control Register, offset: 0x160 */ + __IO uint32_t LOWPWR_CTRL_SET; /**< Low Power Control Register, offset: 0x164 */ + __IO uint32_t LOWPWR_CTRL_CLR; /**< Low Power Control Register, offset: 0x168 */ + __IO uint32_t LOWPWR_CTRL_TOG; /**< Low Power Control Register, offset: 0x16C */ +} PMU_Type; + +/* ---------------------------------------------------------------------------- + -- PMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Register_Masks PMU Register Masks + * @{ + */ + +/*! @name REG_1P1 - Regulator 1P1 Register */ +#define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK) +#define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK) +#define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK) +#define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U) +#define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) + +/*! @name REG_3P0 - Regulator 3P0 Register */ +#define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK) +#define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK) +#define PMU_REG_3P0_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_VBUS_SEL_SHIFT (7U) +#define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK) +#define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK) +#define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK) + +/*! @name REG_2P5 - Regulator 2P5 Register */ +#define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK) +#define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK) +#define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U) +#define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK) +#define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK) + +/*! @name REG_CORE - Digital Regulator Core Register */ +#define PMU_REG_CORE_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_REG0_TARG_SHIFT (0U) +#define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK) +#define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_REG2_TARG_SHIFT (18U) +#define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK) +#define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_RAMP_RATE_SHIFT (27U) +#define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK) +#define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK) + +/*! @name LOWPWR_CTRL - Low Power Control Register */ +#define PMU_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U) +#define PMU_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U) +#define PMU_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & PMU_LOWPWR_CTRL_RC_OSC_EN_MASK) +#define PMU_LOWPWR_CTRL_RC_OSC_PROG_MASK (0xEU) +#define PMU_LOWPWR_CTRL_RC_OSC_PROG_SHIFT (1U) +#define PMU_LOWPWR_CTRL_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_RC_OSC_PROG_SHIFT)) & PMU_LOWPWR_CTRL_RC_OSC_PROG_MASK) +#define PMU_LOWPWR_CTRL_OSC_SEL_MASK (0x10U) +#define PMU_LOWPWR_CTRL_OSC_SEL_SHIFT (4U) +#define PMU_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_OSC_SEL_SHIFT)) & PMU_LOWPWR_CTRL_OSC_SEL_MASK) +#define PMU_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) +#define PMU_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U) +#define PMU_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & PMU_LOWPWR_CTRL_LPBG_SEL_MASK) +#define PMU_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U) +#define PMU_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U) +#define PMU_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & PMU_LOWPWR_CTRL_LPBG_TEST_MASK) +#define PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U) +#define PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U) +#define PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK) +#define PMU_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U) +#define PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U) +#define PMU_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_L1_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U) +#define PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U) +#define PMU_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_L2_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U) +#define PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U) +#define PMU_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U) +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U) +#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & PMU_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & PMU_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & PMU_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) +#define PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U) +#define PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U) +#define PMU_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK) + +/*! @name LOWPWR_CTRL_SET - Low Power Control Register */ +#define PMU_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & PMU_LOWPWR_CTRL_SET_RC_OSC_EN_MASK) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK (0xEU) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT (1U) +#define PMU_LOWPWR_CTRL_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_SHIFT)) & PMU_LOWPWR_CTRL_SET_RC_OSC_PROG_MASK) +#define PMU_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U) +#define PMU_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U) +#define PMU_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & PMU_LOWPWR_CTRL_SET_OSC_SEL_MASK) +#define PMU_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U) +#define PMU_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U) +#define PMU_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & PMU_LOWPWR_CTRL_SET_LPBG_SEL_MASK) +#define PMU_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U) +#define PMU_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U) +#define PMU_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & PMU_LOWPWR_CTRL_SET_LPBG_TEST_MASK) +#define PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U) +#define PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U) +#define PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & PMU_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK) +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U) +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U) +#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U) +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U) +#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U) +#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U) +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U) +#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & PMU_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & PMU_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK) +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U) +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U) +#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK) + +/*! @name LOWPWR_CTRL_CLR - Low Power Control Register */ +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & PMU_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK (0xEU) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT (1U) +#define PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_SHIFT)) & PMU_LOWPWR_CTRL_CLR_RC_OSC_PROG_MASK) +#define PMU_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U) +#define PMU_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U) +#define PMU_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & PMU_LOWPWR_CTRL_CLR_OSC_SEL_MASK) +#define PMU_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U) +#define PMU_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U) +#define PMU_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & PMU_LOWPWR_CTRL_CLR_LPBG_SEL_MASK) +#define PMU_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U) +#define PMU_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U) +#define PMU_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & PMU_LOWPWR_CTRL_CLR_LPBG_TEST_MASK) +#define PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U) +#define PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U) +#define PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & PMU_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK) +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U) +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U) +#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U) +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U) +#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U) +#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U) +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U) +#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & PMU_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK) +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U) +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U) +#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK) + +/*! @name LOWPWR_CTRL_TOG - Low Power Control Register */ +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & PMU_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK (0xEU) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT (1U) +#define PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_SHIFT)) & PMU_LOWPWR_CTRL_TOG_RC_OSC_PROG_MASK) +#define PMU_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U) +#define PMU_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U) +#define PMU_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & PMU_LOWPWR_CTRL_TOG_OSC_SEL_MASK) +#define PMU_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U) +#define PMU_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U) +#define PMU_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & PMU_LOWPWR_CTRL_TOG_LPBG_SEL_MASK) +#define PMU_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U) +#define PMU_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U) +#define PMU_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & PMU_LOWPWR_CTRL_TOG_LPBG_TEST_MASK) +#define PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U) +#define PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U) +#define PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & PMU_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK) +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U) +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U) +#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U) +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U) +#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U) +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U) +#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U) +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U) +#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK) +#define PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U) +#define PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & PMU_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK) +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U) +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U) +#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK) + + +/*! + * @} + */ /* end of group PMU_Register_Masks */ + + +/* PMU - Peripheral instance base addresses */ +/** Peripheral PMU base address */ +#define PMU_BASE (0x20C8110u) +/** Peripheral PMU base pointer */ +#define PMU ((PMU_Type *)PMU_BASE) +/** Array initializer of PMU peripheral base addresses */ +#define PMU_BASE_ADDRS { PMU_BASE } +/** Array initializer of PMU peripheral base pointers */ +#define PMU_BASE_PTRS { PMU } +/** Interrupt vectors for the PMU peripheral type */ +#define PMU_IRQS { PMU_IRQ1_IRQn, PMU_IRQ2_IRQn } + +/*! + * @} + */ /* end of group PMU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer + * @{ + */ + +/** PWM - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWMCR; /**< PWM Control Register, offset: 0x0 */ + __IO uint32_t PWMSR; /**< PWM Status Register, offset: 0x4 */ + __IO uint32_t PWMIR; /**< PWM Interrupt Register, offset: 0x8 */ + __IO uint32_t PWMSAR; /**< PWM Sample Register, offset: 0xC */ + __IO uint32_t PWMPR; /**< PWM Period Register, offset: 0x10 */ + __I uint32_t PWMCNR; /**< PWM Counter Register, offset: 0x14 */ +} PWM_Type; + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/*! @name PWMCR - PWM Control Register */ +#define PWM_PWMCR_EN_MASK (0x1U) +#define PWM_PWMCR_EN_SHIFT (0U) +#define PWM_PWMCR_EN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_EN_SHIFT)) & PWM_PWMCR_EN_MASK) +#define PWM_PWMCR_REPEAT_MASK (0x6U) +#define PWM_PWMCR_REPEAT_SHIFT (1U) +#define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_REPEAT_SHIFT)) & PWM_PWMCR_REPEAT_MASK) +#define PWM_PWMCR_SWR_MASK (0x8U) +#define PWM_PWMCR_SWR_SHIFT (3U) +#define PWM_PWMCR_SWR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_SWR_SHIFT)) & PWM_PWMCR_SWR_MASK) +#define PWM_PWMCR_PRESCALER_MASK (0xFFF0U) +#define PWM_PWMCR_PRESCALER_SHIFT (4U) +#define PWM_PWMCR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_PRESCALER_SHIFT)) & PWM_PWMCR_PRESCALER_MASK) +#define PWM_PWMCR_CLKSRC_MASK (0x30000U) +#define PWM_PWMCR_CLKSRC_SHIFT (16U) +#define PWM_PWMCR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_CLKSRC_SHIFT)) & PWM_PWMCR_CLKSRC_MASK) +#define PWM_PWMCR_POUTC_MASK (0xC0000U) +#define PWM_PWMCR_POUTC_SHIFT (18U) +#define PWM_PWMCR_POUTC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_POUTC_SHIFT)) & PWM_PWMCR_POUTC_MASK) +#define PWM_PWMCR_HCTR_MASK (0x100000U) +#define PWM_PWMCR_HCTR_SHIFT (20U) +#define PWM_PWMCR_HCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_HCTR_SHIFT)) & PWM_PWMCR_HCTR_MASK) +#define PWM_PWMCR_BCTR_MASK (0x200000U) +#define PWM_PWMCR_BCTR_SHIFT (21U) +#define PWM_PWMCR_BCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_BCTR_SHIFT)) & PWM_PWMCR_BCTR_MASK) +#define PWM_PWMCR_DBGEN_MASK (0x400000U) +#define PWM_PWMCR_DBGEN_SHIFT (22U) +#define PWM_PWMCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DBGEN_SHIFT)) & PWM_PWMCR_DBGEN_MASK) +#define PWM_PWMCR_WAITEN_MASK (0x800000U) +#define PWM_PWMCR_WAITEN_SHIFT (23U) +#define PWM_PWMCR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_WAITEN_SHIFT)) & PWM_PWMCR_WAITEN_MASK) +#define PWM_PWMCR_DOZEN_MASK (0x1000000U) +#define PWM_PWMCR_DOZEN_SHIFT (24U) +#define PWM_PWMCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DOZEN_SHIFT)) & PWM_PWMCR_DOZEN_MASK) +#define PWM_PWMCR_STOPEN_MASK (0x2000000U) +#define PWM_PWMCR_STOPEN_SHIFT (25U) +#define PWM_PWMCR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_STOPEN_SHIFT)) & PWM_PWMCR_STOPEN_MASK) +#define PWM_PWMCR_FWM_MASK (0xC000000U) +#define PWM_PWMCR_FWM_SHIFT (26U) +#define PWM_PWMCR_FWM(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_FWM_SHIFT)) & PWM_PWMCR_FWM_MASK) + +/*! @name PWMSR - PWM Status Register */ +#define PWM_PWMSR_FIFOAV_MASK (0x7U) +#define PWM_PWMSR_FIFOAV_SHIFT (0U) +#define PWM_PWMSR_FIFOAV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FIFOAV_SHIFT)) & PWM_PWMSR_FIFOAV_MASK) +#define PWM_PWMSR_FE_MASK (0x8U) +#define PWM_PWMSR_FE_SHIFT (3U) +#define PWM_PWMSR_FE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FE_SHIFT)) & PWM_PWMSR_FE_MASK) +#define PWM_PWMSR_ROV_MASK (0x10U) +#define PWM_PWMSR_ROV_SHIFT (4U) +#define PWM_PWMSR_ROV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_ROV_SHIFT)) & PWM_PWMSR_ROV_MASK) +#define PWM_PWMSR_CMP_MASK (0x20U) +#define PWM_PWMSR_CMP_SHIFT (5U) +#define PWM_PWMSR_CMP(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_CMP_SHIFT)) & PWM_PWMSR_CMP_MASK) +#define PWM_PWMSR_FWE_MASK (0x40U) +#define PWM_PWMSR_FWE_SHIFT (6U) +#define PWM_PWMSR_FWE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FWE_SHIFT)) & PWM_PWMSR_FWE_MASK) + +/*! @name PWMIR - PWM Interrupt Register */ +#define PWM_PWMIR_FIE_MASK (0x1U) +#define PWM_PWMIR_FIE_SHIFT (0U) +#define PWM_PWMIR_FIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_FIE_SHIFT)) & PWM_PWMIR_FIE_MASK) +#define PWM_PWMIR_RIE_MASK (0x2U) +#define PWM_PWMIR_RIE_SHIFT (1U) +#define PWM_PWMIR_RIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_RIE_SHIFT)) & PWM_PWMIR_RIE_MASK) +#define PWM_PWMIR_CIE_MASK (0x4U) +#define PWM_PWMIR_CIE_SHIFT (2U) +#define PWM_PWMIR_CIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_CIE_SHIFT)) & PWM_PWMIR_CIE_MASK) + +/*! @name PWMSAR - PWM Sample Register */ +#define PWM_PWMSAR_SAMPLE_MASK (0xFFFFU) +#define PWM_PWMSAR_SAMPLE_SHIFT (0U) +#define PWM_PWMSAR_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSAR_SAMPLE_SHIFT)) & PWM_PWMSAR_SAMPLE_MASK) + +/*! @name PWMPR - PWM Period Register */ +#define PWM_PWMPR_PERIOD_MASK (0xFFFFU) +#define PWM_PWMPR_PERIOD_SHIFT (0U) +#define PWM_PWMPR_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMPR_PERIOD_SHIFT)) & PWM_PWMPR_PERIOD_MASK) + +/*! @name PWMCNR - PWM Counter Register */ +#define PWM_PWMCNR_COUNT_MASK (0xFFFFU) +#define PWM_PWMCNR_COUNT_SHIFT (0U) +#define PWM_PWMCNR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCNR_COUNT_SHIFT)) & PWM_PWMCNR_COUNT_MASK) + + +/*! + * @} + */ /* end of group PWM_Register_Masks */ + + +/* PWM - Peripheral instance base addresses */ +/** Peripheral PWM1 base address */ +#define PWM1_BASE (0x2080000u) +/** Peripheral PWM1 base pointer */ +#define PWM1 ((PWM_Type *)PWM1_BASE) +/** Peripheral PWM2 base address */ +#define PWM2_BASE (0x2084000u) +/** Peripheral PWM2 base pointer */ +#define PWM2 ((PWM_Type *)PWM2_BASE) +/** Peripheral PWM3 base address */ +#define PWM3_BASE (0x2088000u) +/** Peripheral PWM3 base pointer */ +#define PWM3 ((PWM_Type *)PWM3_BASE) +/** Peripheral PWM4 base address */ +#define PWM4_BASE (0x208C000u) +/** Peripheral PWM4 base pointer */ +#define PWM4 ((PWM_Type *)PWM4_BASE) +/** Peripheral PWM5 base address */ +#define PWM5_BASE (0x20F0000u) +/** Peripheral PWM5 base pointer */ +#define PWM5 ((PWM_Type *)PWM5_BASE) +/** Peripheral PWM6 base address */ +#define PWM6_BASE (0x20F4000u) +/** Peripheral PWM6 base pointer */ +#define PWM6 ((PWM_Type *)PWM6_BASE) +/** Peripheral PWM7 base address */ +#define PWM7_BASE (0x20F8000u) +/** Peripheral PWM7 base pointer */ +#define PWM7 ((PWM_Type *)PWM7_BASE) +/** Peripheral PWM8 base address */ +#define PWM8_BASE (0x20FC000u) +/** Peripheral PWM8 base pointer */ +#define PWM8 ((PWM_Type *)PWM8_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE, PWM5_BASE, PWM6_BASE, PWM7_BASE, PWM8_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_IRQS { NotAvail_IRQn, PWM1_IRQn, PWM2_IRQn, PWM3_IRQn, PWM4_IRQn, PWM5_IRQn, PWM6_IRQn, PWM7_IRQn, PWM8_IRQn } + +/*! + * @} + */ /* end of group PWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PXP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer + * @{ + */ + +/** PXP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control Register 0, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< Control Register 0, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< Control Register 0, offset: 0xC */ + __IO uint32_t STAT; /**< Status Register, offset: 0x10 */ + __IO uint32_t STAT_SET; /**< Status Register, offset: 0x14 */ + __IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */ + __IO uint32_t STAT_TOG; /**< Status Register, offset: 0x1C */ + __IO uint32_t OUT_CTRL; /**< Output Buffer Control Register, offset: 0x20 */ + __IO uint32_t OUT_CTRL_SET; /**< Output Buffer Control Register, offset: 0x24 */ + __IO uint32_t OUT_CTRL_CLR; /**< Output Buffer Control Register, offset: 0x28 */ + __IO uint32_t OUT_CTRL_TOG; /**< Output Buffer Control Register, offset: 0x2C */ + __IO uint32_t OUT_BUF; /**< Output Frame Buffer Pointer, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __IO uint32_t OUT_BUF2; /**< Output Frame Buffer Pointer #2, offset: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t OUT_PITCH; /**< Output Buffer Pitch, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t OUT_LRC; /**< Output Surface Lower Right Coordinate, offset: 0x60 */ + uint8_t RESERVED_3[12]; + __IO uint32_t OUT_PS_ULC; /**< Processed Surface Upper Left Coordinate, offset: 0x70 */ + uint8_t RESERVED_4[12]; + __IO uint32_t OUT_PS_LRC; /**< Processed Surface Lower Right Coordinate, offset: 0x80 */ + uint8_t RESERVED_5[12]; + __IO uint32_t OUT_AS_ULC; /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */ + uint8_t RESERVED_6[12]; + __IO uint32_t OUT_AS_LRC; /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */ + uint8_t RESERVED_7[12]; + __IO uint32_t PS_CTRL; /**< Processed Surface (PS) Control Register, offset: 0xB0 */ + __IO uint32_t PS_CTRL_SET; /**< Processed Surface (PS) Control Register, offset: 0xB4 */ + __IO uint32_t PS_CTRL_CLR; /**< Processed Surface (PS) Control Register, offset: 0xB8 */ + __IO uint32_t PS_CTRL_TOG; /**< Processed Surface (PS) Control Register, offset: 0xBC */ + __IO uint32_t PS_BUF; /**< PS Input Buffer Address, offset: 0xC0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t PS_UBUF; /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */ + uint8_t RESERVED_9[12]; + __IO uint32_t PS_VBUF; /**< PS V/Cr Input Buffer Address, offset: 0xE0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t PS_PITCH; /**< Processed Surface Pitch, offset: 0xF0 */ + uint8_t RESERVED_11[12]; + __IO uint32_t PS_BACKGROUND_0; /**< PS Background Color, offset: 0x100 */ + uint8_t RESERVED_12[12]; + __IO uint32_t PS_SCALE; /**< PS Scale Factor Register, offset: 0x110 */ + uint8_t RESERVED_13[12]; + __IO uint32_t PS_OFFSET; /**< PS Scale Offset Register, offset: 0x120 */ + uint8_t RESERVED_14[12]; + __IO uint32_t PS_CLRKEYLOW_0; /**< PS Color Key Low, offset: 0x130 */ + uint8_t RESERVED_15[12]; + __IO uint32_t PS_CLRKEYHIGH_0; /**< PS Color Key High, offset: 0x140 */ + uint8_t RESERVED_16[12]; + __IO uint32_t AS_CTRL; /**< Alpha Surface Control, offset: 0x150 */ + uint8_t RESERVED_17[12]; + __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x160 */ + uint8_t RESERVED_18[12]; + __IO uint32_t AS_PITCH; /**< Alpha Surface Pitch, offset: 0x170 */ + uint8_t RESERVED_19[12]; + __IO uint32_t AS_CLRKEYLOW_0; /**< Overlay Color Key Low, offset: 0x180 */ + uint8_t RESERVED_20[12]; + __IO uint32_t AS_CLRKEYHIGH_0; /**< Overlay Color Key High, offset: 0x190 */ + uint8_t RESERVED_21[12]; + __IO uint32_t CSC1_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */ + uint8_t RESERVED_22[12]; + __IO uint32_t CSC1_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */ + uint8_t RESERVED_23[12]; + __IO uint32_t CSC1_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */ + uint8_t RESERVED_24[12]; + __IO uint32_t CSC2_CTRL; /**< Color Space Conversion Control Register., offset: 0x1D0 */ + uint8_t RESERVED_25[12]; + __IO uint32_t CSC2_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1E0 */ + uint8_t RESERVED_26[12]; + __IO uint32_t CSC2_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1F0 */ + uint8_t RESERVED_27[12]; + __IO uint32_t CSC2_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x200 */ + uint8_t RESERVED_28[12]; + __IO uint32_t CSC2_COEF3; /**< Color Space Conversion Coefficient Register 3, offset: 0x210 */ + uint8_t RESERVED_29[12]; + __IO uint32_t CSC2_COEF4; /**< Color Space Conversion Coefficient Register 4, offset: 0x220 */ + uint8_t RESERVED_30[12]; + __IO uint32_t CSC2_COEF5; /**< Color Space Conversion Coefficient Register 5, offset: 0x230 */ + uint8_t RESERVED_31[12]; + __IO uint32_t LUT_CTRL; /**< Lookup Table Control Register., offset: 0x240 */ + uint8_t RESERVED_32[12]; + __IO uint32_t LUT_ADDR; /**< Lookup Table Control Register., offset: 0x250 */ + uint8_t RESERVED_33[12]; + __IO uint32_t LUT_DATA; /**< Lookup Table Data Register., offset: 0x260 */ + uint8_t RESERVED_34[12]; + __IO uint32_t LUT_EXTMEM; /**< Lookup Table External Memory Address Register., offset: 0x270 */ + uint8_t RESERVED_35[12]; + __IO uint32_t CFA; /**< Color Filter Array Register., offset: 0x280 */ + uint8_t RESERVED_36[12]; + __IO uint32_t ALPHA_A_CTRL; /**< PXP Alpha Engine A Control Register., offset: 0x290 */ + uint8_t RESERVED_37[44]; + __IO uint32_t PS_BACKGROUND_1; /**< PS Background Color 1, offset: 0x2C0 */ + uint8_t RESERVED_38[12]; + __IO uint32_t PS_CLRKEYLOW_1; /**< PS Color Key Low 1, offset: 0x2D0 */ + uint8_t RESERVED_39[12]; + __IO uint32_t PS_CLRKEYHIGH_1; /**< PS Color Key High 1, offset: 0x2E0 */ + uint8_t RESERVED_40[12]; + __IO uint32_t AS_CLRKEYLOW_1; /**< Overlay Color Key Low, offset: 0x2F0 */ + uint8_t RESERVED_41[12]; + __IO uint32_t AS_CLRKEYHIGH_1; /**< Overlay Color Key High, offset: 0x300 */ + uint8_t RESERVED_42[12]; + __IO uint32_t CTRL2; /**< Control Register 2, offset: 0x310 */ + __IO uint32_t CTRL2_SET; /**< Control Register 2, offset: 0x314 */ + __IO uint32_t CTRL2_CLR; /**< Control Register 2, offset: 0x318 */ + __IO uint32_t CTRL2_TOG; /**< Control Register 2, offset: 0x31C */ + __IO uint32_t POWER_REG0; /**< PXP Power Control Register., offset: 0x320 */ + uint8_t RESERVED_43[12]; + __IO uint32_t POWER_REG1; /**< PXP Power Control Register 1., offset: 0x330 */ + uint8_t RESERVED_44[12]; + __IO uint32_t DATA_PATH_CTRL0; /**< This register helps decide the data path gthrough the PXP., offset: 0x340 */ + __IO uint32_t DATA_PATH_CTRL0_SET; /**< This register helps decide the data path gthrough the PXP., offset: 0x344 */ + __IO uint32_t DATA_PATH_CTRL0_CLR; /**< This register helps decide the data path gthrough the PXP., offset: 0x348 */ + __IO uint32_t DATA_PATH_CTRL0_TOG; /**< This register helps decide the data path gthrough the PXP., offset: 0x34C */ + __IO uint32_t DATA_PATH_CTRL1; /**< This register helps decide the data path gthrough the PXP., offset: 0x350 */ + __IO uint32_t DATA_PATH_CTRL1_SET; /**< This register helps decide the data path gthrough the PXP., offset: 0x354 */ + __IO uint32_t DATA_PATH_CTRL1_CLR; /**< This register helps decide the data path gthrough the PXP., offset: 0x358 */ + __IO uint32_t DATA_PATH_CTRL1_TOG; /**< This register helps decide the data path gthrough the PXP., offset: 0x35C */ + __IO uint32_t INIT_MEM_CTRL; /**< Initialize memory buffer control Register, offset: 0x360 */ + __IO uint32_t INIT_MEM_CTRL_SET; /**< Initialize memory buffer control Register, offset: 0x364 */ + __IO uint32_t INIT_MEM_CTRL_CLR; /**< Initialize memory buffer control Register, offset: 0x368 */ + __IO uint32_t INIT_MEM_CTRL_TOG; /**< Initialize memory buffer control Register, offset: 0x36C */ + __IO uint32_t INIT_MEM_DATA; /**< Write data Register, offset: 0x370 */ + uint8_t RESERVED_45[12]; + __IO uint32_t INIT_MEM_DATA_HIGH; /**< Write data Register, offset: 0x380 */ + uint8_t RESERVED_46[12]; + __IO uint32_t IRQ_MASK; /**< PXP IRQ Mask Register, offset: 0x390 */ + __IO uint32_t IRQ_MASK_SET; /**< PXP IRQ Mask Register, offset: 0x394 */ + __IO uint32_t IRQ_MASK_CLR; /**< PXP IRQ Mask Register, offset: 0x398 */ + __IO uint32_t IRQ_MASK_TOG; /**< PXP IRQ Mask Register, offset: 0x39C */ + __IO uint32_t IRQ; /**< PXP Interrupt Register, offset: 0x3A0 */ + __IO uint32_t IRQ_SET; /**< PXP Interrupt Register, offset: 0x3A4 */ + __IO uint32_t IRQ_CLR; /**< PXP Interrupt Register, offset: 0x3A8 */ + __IO uint32_t IRQ_TOG; /**< PXP Interrupt Register, offset: 0x3AC */ + __IO uint32_t NEXT_EN; /**< PXP NEXT Buffer Enable select Register, offset: 0x3B0 */ + __IO uint32_t NEXT_EN_SET; /**< PXP NEXT Buffer Enable select Register, offset: 0x3B4 */ + __IO uint32_t NEXT_EN_CLR; /**< PXP NEXT Buffer Enable select Register, offset: 0x3B8 */ + __IO uint32_t NEXT_EN_TOG; /**< PXP NEXT Buffer Enable select Register, offset: 0x3BC */ + uint8_t RESERVED_47[64]; + __IO uint32_t NEXT; /**< Next Frame Pointer, offset: 0x400 */ + uint8_t RESERVED_48[12]; + __IO uint32_t DEBUGCTRL; /**< Debug Control Register, offset: 0x410 */ + uint8_t RESERVED_49[12]; + __I uint32_t DEBUGr; /**< Debug Register, offset: 0x420 */ + uint8_t RESERVED_50[12]; + __I uint32_t VERSION; /**< Version Register, offset: 0x430 */ + uint8_t RESERVED_51[1484]; + __IO uint32_t DITHER_STORE_SIZE_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0xA00 */ + uint8_t RESERVED_52[1788]; + __IO uint32_t WFB_FETCH_CTRL; /**< Fetch engine Control for WFE B Register, offset: 0x1100 */ + __IO uint32_t WFB_FETCH_CTRL_SET; /**< Fetch engine Control for WFE B Register, offset: 0x1104 */ + __IO uint32_t WFB_FETCH_CTRL_CLR; /**< Fetch engine Control for WFE B Register, offset: 0x1108 */ + __IO uint32_t WFB_FETCH_CTRL_TOG; /**< Fetch engine Control for WFE B Register, offset: 0x110C */ + __IO uint32_t WFB_FETCH_BUF1_ADDR; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1110 */ + uint8_t RESERVED_53[12]; + __IO uint32_t WFB_FETCH_BUF1_PITCH; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1120 */ + uint8_t RESERVED_54[12]; + __IO uint32_t WFB_FETCH_BUF1_SIZE; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1130 */ + uint8_t RESERVED_55[12]; + __IO uint32_t WFB_FETCH_BUF2_ADDR; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1140 */ + uint8_t RESERVED_56[12]; + __IO uint32_t WFB_FETCH_BUF2_PITCH; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1150 */ + uint8_t RESERVED_57[12]; + __IO uint32_t WFB_FETCH_BUF2_SIZE; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1160 */ + uint8_t RESERVED_58[12]; + __IO uint32_t WFB_ARRAY_PIXEL0_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1170 */ + uint8_t RESERVED_59[12]; + __IO uint32_t WFB_ARRAY_PIXEL1_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1180 */ + uint8_t RESERVED_60[12]; + __IO uint32_t WFB_ARRAY_PIXEL2_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1190 */ + uint8_t RESERVED_61[12]; + __IO uint32_t WFB_ARRAY_PIXEL3_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11A0 */ + uint8_t RESERVED_62[12]; + __IO uint32_t WFB_ARRAY_PIXEL4_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11B0 */ + uint8_t RESERVED_63[12]; + __IO uint32_t WFB_ARRAY_PIXEL5_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11C0 */ + uint8_t RESERVED_64[12]; + __IO uint32_t WFB_ARRAY_PIXEL6_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11D0 */ + uint8_t RESERVED_65[12]; + __IO uint32_t WFB_ARRAY_PIXEL7_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11E0 */ + uint8_t RESERVED_66[12]; + __IO uint32_t WFB_ARRAY_FLAG0_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x11F0 */ + uint8_t RESERVED_67[12]; + __IO uint32_t WFB_ARRAY_FLAG1_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1200 */ + uint8_t RESERVED_68[12]; + __IO uint32_t WFB_ARRAY_FLAG2_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1210 */ + uint8_t RESERVED_69[12]; + __IO uint32_t WFB_ARRAY_FLAG3_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1220 */ + uint8_t RESERVED_70[12]; + __IO uint32_t WFB_ARRAY_FLAG4_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1230 */ + uint8_t RESERVED_71[12]; + __IO uint32_t WFB_ARRAY_FLAG5_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1240 */ + uint8_t RESERVED_72[12]; + __IO uint32_t WFB_ARRAY_FLAG6_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1250 */ + uint8_t RESERVED_73[12]; + __IO uint32_t WFB_ARRAY_FLAG7_MASK; /**< This register defines the control bits for the pxp wfb fetch sub-block., offset: 0x1260 */ + uint8_t RESERVED_74[12]; + __IO uint32_t WFB_FETCH_BUF1_CORD; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x1270 */ + uint8_t RESERVED_75[12]; + __IO uint32_t WFB_FETCH_BUF2_CORD; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x1280 */ + uint8_t RESERVED_76[12]; + __IO uint32_t WFB_ARRAY_FLAG8_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x1290 */ + uint8_t RESERVED_77[12]; + __IO uint32_t WFB_ARRAY_FLAG9_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12A0 */ + uint8_t RESERVED_78[12]; + __IO uint32_t WFB_ARRAY_FLAG10_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12B0 */ + uint8_t RESERVED_79[12]; + __IO uint32_t WFB_ARRAY_FLAG11_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12C0 */ + uint8_t RESERVED_80[12]; + __IO uint32_t WFB_ARRAY_FLAG12_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12D0 */ + uint8_t RESERVED_81[12]; + __IO uint32_t WFB_ARRAY_FLAG13_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12E0 */ + uint8_t RESERVED_82[12]; + __IO uint32_t WFB_ARRAY_FLAG14_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x12F0 */ + uint8_t RESERVED_83[12]; + __IO uint32_t WFB_ARRAY_FLAG15_MASK; /**< This register defines the control bits for the pxp wfa fetch sub-block., offset: 0x1300 */ + uint8_t RESERVED_84[12]; + __IO uint32_t WFB_ARRAY_REG0; /**< This register defines software define pixels for wfb fetch sub-block., offset: 0x1310 */ + uint8_t RESERVED_85[12]; + __IO uint32_t WFB_ARRAY_REG1; /**< This register defines software define pixels for wfb fetch sub-block., offset: 0x1320 */ + uint8_t RESERVED_86[12]; + __IO uint32_t WFB_ARRAY_REG2; /**< This register defines software define pixels for wfb fetch sub-block., offset: 0x1330 */ + uint8_t RESERVED_87[12]; + __IO uint32_t WFE_B_STORE_CTRL_CH0; /**< Store engine Control Channel 0 Register, offset: 0x1340 */ + __IO uint32_t WFE_B_STORE_CTRL_CH0_SET; /**< Store engine Control Channel 0 Register, offset: 0x1344 */ + __IO uint32_t WFE_B_STORE_CTRL_CH0_CLR; /**< Store engine Control Channel 0 Register, offset: 0x1348 */ + __IO uint32_t WFE_B_STORE_CTRL_CH0_TOG; /**< Store engine Control Channel 0 Register, offset: 0x134C */ + __IO uint32_t WFE_B_STORE_CTRL_CH1; /**< Store engine Control Channel 1 Register, offset: 0x1350 */ + __IO uint32_t WFE_B_STORE_CTRL_CH1_SET; /**< Store engine Control Channel 1 Register, offset: 0x1354 */ + __IO uint32_t WFE_B_STORE_CTRL_CH1_CLR; /**< Store engine Control Channel 1 Register, offset: 0x1358 */ + __IO uint32_t WFE_B_STORE_CTRL_CH1_TOG; /**< Store engine Control Channel 1 Register, offset: 0x135C */ + __I uint32_t WFE_B_STORE_STATUS_CH0; /**< Store engine status Channel 0 Register, offset: 0x1360 */ + uint8_t RESERVED_88[12]; + __I uint32_t WFE_B_STORE_STATUS_CH1; /**< Store engine status Channel 1 Register, offset: 0x1370 */ + uint8_t RESERVED_89[12]; + __IO uint32_t WFE_B_STORE_SIZE_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1380 */ + uint8_t RESERVED_90[12]; + __IO uint32_t WFE_B_STORE_SIZE_CH1; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1390 */ + uint8_t RESERVED_91[12]; + __IO uint32_t WFE_B_STORE_PITCH; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13A0 */ + uint8_t RESERVED_92[12]; + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13B0 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0_SET; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13B4 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0_CLR; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13B8 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH0_TOG; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13BC */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13C0 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1_SET; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13C4 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1_CLR; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13C8 */ + __IO uint32_t WFE_B_STORE_SHIFT_CTRL_CH1_TOG; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x13CC */ + uint8_t RESERVED_93[64]; + __IO uint32_t WFE_B_STORE_ADDR_0_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1410 */ + uint8_t RESERVED_94[12]; + __IO uint32_t WFE_B_STORE_ADDR_1_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1420 */ + uint8_t RESERVED_95[12]; + __IO uint32_t WFE_B_STORE_FILL_DATA_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1430 */ + uint8_t RESERVED_96[12]; + __IO uint32_t WFE_B_STORE_ADDR_0_CH1; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1440 */ + uint8_t RESERVED_97[12]; + __IO uint32_t WFE_B_STORE_ADDR_1_CH1; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1450 */ + uint8_t RESERVED_98[12]; + __IO uint32_t WFE_B_STORE_D_MASK0_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1460 */ + uint8_t RESERVED_99[12]; + __IO uint32_t WFE_B_STORE_D_MASK0_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1470 */ + uint8_t RESERVED_100[12]; + __IO uint32_t WFE_B_STORE_D_MASK1_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1480 */ + uint8_t RESERVED_101[12]; + __IO uint32_t WFE_B_STORE_D_MASK1_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1490 */ + uint8_t RESERVED_102[12]; + __IO uint32_t WFE_B_STORE_D_MASK2_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14A0 */ + uint8_t RESERVED_103[12]; + __IO uint32_t WFE_B_STORE_D_MASK2_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14B0 */ + uint8_t RESERVED_104[12]; + __IO uint32_t WFE_B_STORE_D_MASK3_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14C0 */ + uint8_t RESERVED_105[12]; + __IO uint32_t WFE_B_STORE_D_MASK3_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14D0 */ + uint8_t RESERVED_106[12]; + __IO uint32_t WFE_B_STORE_D_MASK4_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14E0 */ + uint8_t RESERVED_107[12]; + __IO uint32_t WFE_B_STORE_D_MASK4_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x14F0 */ + uint8_t RESERVED_108[12]; + __IO uint32_t WFE_B_STORE_D_MASK5_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1500 */ + uint8_t RESERVED_109[12]; + __IO uint32_t WFE_B_STORE_D_MASK5_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1510 */ + uint8_t RESERVED_110[12]; + __IO uint32_t WFE_B_STORE_D_MASK6_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1520 */ + uint8_t RESERVED_111[12]; + __IO uint32_t WFE_B_STORE_D_MASK6_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1530 */ + uint8_t RESERVED_112[12]; + __IO uint32_t WFE_B_STORE_D_MASK7_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1540 */ + uint8_t RESERVED_113[12]; + __IO uint32_t WFE_B_STORE_D_MASK7_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1550 */ + uint8_t RESERVED_114[12]; + __IO uint32_t WFE_B_STORE_D_SHIFT_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1560 */ + uint8_t RESERVED_115[12]; + __IO uint32_t WFE_B_STORE_D_SHIFT_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1570 */ + uint8_t RESERVED_116[12]; + __IO uint32_t WFE_B_STORE_F_SHIFT_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1580 */ + uint8_t RESERVED_117[12]; + __IO uint32_t WFE_B_STORE_F_SHIFT_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x1590 */ + uint8_t RESERVED_118[12]; + __IO uint32_t WFE_B_STORE_F_MASK_L_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x15A0 */ + uint8_t RESERVED_119[12]; + __IO uint32_t WFE_B_STORE_F_MASK_H_CH0; /**< This register defines the control bits for the pxp store_engine sub-block., offset: 0x15B0 */ + uint8_t RESERVED_120[28]; + __IO uint32_t FETCH_WFE_B_DEBUG; /**< This register holds the debug bits for the prefetch engine for WFE B., offset: 0x15D0 */ + uint8_t RESERVED_121[156]; + __IO uint32_t DITHER_CTRL; /**< Dither Control Register 0, offset: 0x1670 */ + __IO uint32_t DITHER_CTRL_SET; /**< Dither Control Register 0, offset: 0x1674 */ + __IO uint32_t DITHER_CTRL_CLR; /**< Dither Control Register 0, offset: 0x1678 */ + __IO uint32_t DITHER_CTRL_TOG; /**< Dither Control Register 0, offset: 0x167C */ + __IO uint32_t DITHER_FINAL_LUT_DATA0; /**< Final stage lookup value Register, offset: 0x1680 */ + __IO uint32_t DITHER_FINAL_LUT_DATA0_SET; /**< Final stage lookup value Register, offset: 0x1684 */ + __IO uint32_t DITHER_FINAL_LUT_DATA0_CLR; /**< Final stage lookup value Register, offset: 0x1688 */ + __IO uint32_t DITHER_FINAL_LUT_DATA0_TOG; /**< Final stage lookup value Register, offset: 0x168C */ + __IO uint32_t DITHER_FINAL_LUT_DATA1; /**< Final stage lookup value Register, offset: 0x1690 */ + __IO uint32_t DITHER_FINAL_LUT_DATA1_SET; /**< Final stage lookup value Register, offset: 0x1694 */ + __IO uint32_t DITHER_FINAL_LUT_DATA1_CLR; /**< Final stage lookup value Register, offset: 0x1698 */ + __IO uint32_t DITHER_FINAL_LUT_DATA1_TOG; /**< Final stage lookup value Register, offset: 0x169C */ + __IO uint32_t DITHER_FINAL_LUT_DATA2; /**< Final stage lookup value Register, offset: 0x16A0 */ + __IO uint32_t DITHER_FINAL_LUT_DATA2_SET; /**< Final stage lookup value Register, offset: 0x16A4 */ + __IO uint32_t DITHER_FINAL_LUT_DATA2_CLR; /**< Final stage lookup value Register, offset: 0x16A8 */ + __IO uint32_t DITHER_FINAL_LUT_DATA2_TOG; /**< Final stage lookup value Register, offset: 0x16AC */ + __IO uint32_t DITHER_FINAL_LUT_DATA3; /**< Final stage lookup value Register, offset: 0x16B0 */ + __IO uint32_t DITHER_FINAL_LUT_DATA3_SET; /**< Final stage lookup value Register, offset: 0x16B4 */ + __IO uint32_t DITHER_FINAL_LUT_DATA3_CLR; /**< Final stage lookup value Register, offset: 0x16B8 */ + __IO uint32_t DITHER_FINAL_LUT_DATA3_TOG; /**< Final stage lookup value Register, offset: 0x16BC */ + uint8_t RESERVED_122[1600]; + __IO uint32_t WFE_B_CTRL; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D00 */ + __IO uint32_t WFE_B_CTRL_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D04 */ + __IO uint32_t WFE_B_CTRL_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D08 */ + __IO uint32_t WFE_B_CTRL_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D0C */ + __IO uint32_t WFE_B_DIMENSIONS; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D10 */ + uint8_t RESERVED_123[12]; + __IO uint32_t WFE_B_OFFSET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D20 */ + uint8_t RESERVED_124[12]; + __IO uint32_t WFE_B_SW_DATA_REGS; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D30 */ + uint8_t RESERVED_125[12]; + __IO uint32_t WFE_B_SW_FLAG_REGS; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D40 */ + uint8_t RESERVED_126[12]; + __IO uint32_t WFE_B_STAGE1_MUX0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D50 */ + __IO uint32_t WFE_B_STAGE1_MUX0_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D54 */ + __IO uint32_t WFE_B_STAGE1_MUX0_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D58 */ + __IO uint32_t WFE_B_STAGE1_MUX0_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D5C */ + __IO uint32_t WFE_B_STAGE1_MUX1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D60 */ + __IO uint32_t WFE_B_STAGE1_MUX1_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D64 */ + __IO uint32_t WFE_B_STAGE1_MUX1_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D68 */ + __IO uint32_t WFE_B_STAGE1_MUX1_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D6C */ + __IO uint32_t WFE_B_STAGE1_MUX2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D70 */ + __IO uint32_t WFE_B_STAGE1_MUX2_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D74 */ + __IO uint32_t WFE_B_STAGE1_MUX2_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D78 */ + __IO uint32_t WFE_B_STAGE1_MUX2_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D7C */ + __IO uint32_t WFE_B_STAGE1_MUX3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D80 */ + __IO uint32_t WFE_B_STAGE1_MUX3_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D84 */ + __IO uint32_t WFE_B_STAGE1_MUX3_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D88 */ + __IO uint32_t WFE_B_STAGE1_MUX3_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D8C */ + __IO uint32_t WFE_B_STAGE1_MUX4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D90 */ + __IO uint32_t WFE_B_STAGE1_MUX4_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D94 */ + __IO uint32_t WFE_B_STAGE1_MUX4_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D98 */ + __IO uint32_t WFE_B_STAGE1_MUX4_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1D9C */ + __IO uint32_t WFE_B_STAGE1_MUX5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DA0 */ + __IO uint32_t WFE_B_STAGE1_MUX5_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DA4 */ + __IO uint32_t WFE_B_STAGE1_MUX5_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DA8 */ + __IO uint32_t WFE_B_STAGE1_MUX5_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DAC */ + __IO uint32_t WFE_B_STAGE1_MUX6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DB0 */ + __IO uint32_t WFE_B_STAGE1_MUX6_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DB4 */ + __IO uint32_t WFE_B_STAGE1_MUX6_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DB8 */ + __IO uint32_t WFE_B_STAGE1_MUX6_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DBC */ + __IO uint32_t WFE_B_STAGE1_MUX7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DC0 */ + __IO uint32_t WFE_B_STAGE1_MUX7_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DC4 */ + __IO uint32_t WFE_B_STAGE1_MUX7_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DC8 */ + __IO uint32_t WFE_B_STAGE1_MUX7_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DCC */ + __IO uint32_t WFE_B_STAGE1_MUX8; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DD0 */ + __IO uint32_t WFE_B_STAGE1_MUX8_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DD4 */ + __IO uint32_t WFE_B_STAGE1_MUX8_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DD8 */ + __IO uint32_t WFE_B_STAGE1_MUX8_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DDC */ + __IO uint32_t WFE_B_STAGE2_MUX0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DE0 */ + __IO uint32_t WFE_B_STAGE2_MUX0_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DE4 */ + __IO uint32_t WFE_B_STAGE2_MUX0_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DE8 */ + __IO uint32_t WFE_B_STAGE2_MUX0_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DEC */ + __IO uint32_t WFE_B_STAGE2_MUX1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DF0 */ + __IO uint32_t WFE_B_STAGE2_MUX1_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DF4 */ + __IO uint32_t WFE_B_STAGE2_MUX1_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DF8 */ + __IO uint32_t WFE_B_STAGE2_MUX1_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1DFC */ + __IO uint32_t WFE_B_STAGE2_MUX2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E00 */ + __IO uint32_t WFE_B_STAGE2_MUX2_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E04 */ + __IO uint32_t WFE_B_STAGE2_MUX2_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E08 */ + __IO uint32_t WFE_B_STAGE2_MUX2_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E0C */ + __IO uint32_t WFE_B_STAGE2_MUX3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E10 */ + __IO uint32_t WFE_B_STAGE2_MUX3_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E14 */ + __IO uint32_t WFE_B_STAGE2_MUX3_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E18 */ + __IO uint32_t WFE_B_STAGE2_MUX3_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E1C */ + __IO uint32_t WFE_B_STAGE2_MUX4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E20 */ + __IO uint32_t WFE_B_STAGE2_MUX4_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E24 */ + __IO uint32_t WFE_B_STAGE2_MUX4_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E28 */ + __IO uint32_t WFE_B_STAGE2_MUX4_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E2C */ + __IO uint32_t WFE_B_STAGE2_MUX5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E30 */ + __IO uint32_t WFE_B_STAGE2_MUX5_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E34 */ + __IO uint32_t WFE_B_STAGE2_MUX5_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E38 */ + __IO uint32_t WFE_B_STAGE2_MUX5_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E3C */ + __IO uint32_t WFE_B_STAGE2_MUX6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E40 */ + __IO uint32_t WFE_B_STAGE2_MUX6_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E44 */ + __IO uint32_t WFE_B_STAGE2_MUX6_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E48 */ + __IO uint32_t WFE_B_STAGE2_MUX6_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E4C */ + __IO uint32_t WFE_B_STAGE2_MUX7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E50 */ + __IO uint32_t WFE_B_STAGE2_MUX7_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E54 */ + __IO uint32_t WFE_B_STAGE2_MUX7_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E58 */ + __IO uint32_t WFE_B_STAGE2_MUX7_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E5C */ + __IO uint32_t WFE_B_STAGE2_MUX8; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E60 */ + __IO uint32_t WFE_B_STAGE2_MUX8_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E64 */ + __IO uint32_t WFE_B_STAGE2_MUX8_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E68 */ + __IO uint32_t WFE_B_STAGE2_MUX8_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E6C */ + __IO uint32_t WFE_B_STAGE2_MUX9; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E70 */ + __IO uint32_t WFE_B_STAGE2_MUX9_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E74 */ + __IO uint32_t WFE_B_STAGE2_MUX9_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E78 */ + __IO uint32_t WFE_B_STAGE2_MUX9_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E7C */ + __IO uint32_t WFE_B_STAGE2_MUX10; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E80 */ + __IO uint32_t WFE_B_STAGE2_MUX10_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E84 */ + __IO uint32_t WFE_B_STAGE2_MUX10_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E88 */ + __IO uint32_t WFE_B_STAGE2_MUX10_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E8C */ + __IO uint32_t WFE_B_STAGE2_MUX11; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E90 */ + __IO uint32_t WFE_B_STAGE2_MUX11_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E94 */ + __IO uint32_t WFE_B_STAGE2_MUX11_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E98 */ + __IO uint32_t WFE_B_STAGE2_MUX11_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1E9C */ + __IO uint32_t WFE_B_STAGE2_MUX12; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EA0 */ + __IO uint32_t WFE_B_STAGE2_MUX12_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EA4 */ + __IO uint32_t WFE_B_STAGE2_MUX12_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EA8 */ + __IO uint32_t WFE_B_STAGE2_MUX12_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EAC */ + __IO uint32_t WFE_B_STAGE3_MUX0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EB0 */ + __IO uint32_t WFE_B_STAGE3_MUX0_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EB4 */ + __IO uint32_t WFE_B_STAGE3_MUX0_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EB8 */ + __IO uint32_t WFE_B_STAGE3_MUX0_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EBC */ + __IO uint32_t WFE_B_STAGE3_MUX1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EC0 */ + __IO uint32_t WFE_B_STAGE3_MUX1_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EC4 */ + __IO uint32_t WFE_B_STAGE3_MUX1_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EC8 */ + __IO uint32_t WFE_B_STAGE3_MUX1_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1ECC */ + __IO uint32_t WFE_B_STAGE3_MUX2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1ED0 */ + __IO uint32_t WFE_B_STAGE3_MUX2_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1ED4 */ + __IO uint32_t WFE_B_STAGE3_MUX2_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1ED8 */ + __IO uint32_t WFE_B_STAGE3_MUX2_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EDC */ + __IO uint32_t WFE_B_STAGE3_MUX3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EE0 */ + __IO uint32_t WFE_B_STAGE3_MUX3_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EE4 */ + __IO uint32_t WFE_B_STAGE3_MUX3_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EE8 */ + __IO uint32_t WFE_B_STAGE3_MUX3_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EEC */ + __IO uint32_t WFE_B_STAGE3_MUX4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EF0 */ + __IO uint32_t WFE_B_STAGE3_MUX4_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EF4 */ + __IO uint32_t WFE_B_STAGE3_MUX4_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EF8 */ + __IO uint32_t WFE_B_STAGE3_MUX4_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1EFC */ + __IO uint32_t WFE_B_STAGE3_MUX5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F00 */ + __IO uint32_t WFE_B_STAGE3_MUX5_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F04 */ + __IO uint32_t WFE_B_STAGE3_MUX5_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F08 */ + __IO uint32_t WFE_B_STAGE3_MUX5_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F0C */ + __IO uint32_t WFE_B_STAGE3_MUX6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F10 */ + __IO uint32_t WFE_B_STAGE3_MUX6_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F14 */ + __IO uint32_t WFE_B_STAGE3_MUX6_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F18 */ + __IO uint32_t WFE_B_STAGE3_MUX6_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F1C */ + __IO uint32_t WFE_B_STAGE3_MUX7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F20 */ + __IO uint32_t WFE_B_STAGE3_MUX7_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F24 */ + __IO uint32_t WFE_B_STAGE3_MUX7_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F28 */ + __IO uint32_t WFE_B_STAGE3_MUX7_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F2C */ + __IO uint32_t WFE_B_STAGE3_MUX8; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F30 */ + __IO uint32_t WFE_B_STAGE3_MUX8_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F34 */ + __IO uint32_t WFE_B_STAGE3_MUX8_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F38 */ + __IO uint32_t WFE_B_STAGE3_MUX8_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F3C */ + __IO uint32_t WFE_B_STAGE3_MUX9; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F40 */ + __IO uint32_t WFE_B_STAGE3_MUX9_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F44 */ + __IO uint32_t WFE_B_STAGE3_MUX9_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F48 */ + __IO uint32_t WFE_B_STAGE3_MUX9_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F4C */ + __IO uint32_t WFE_B_STAGE3_MUX10; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F50 */ + __IO uint32_t WFE_B_STAGE3_MUX10_SET; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F54 */ + __IO uint32_t WFE_B_STAGE3_MUX10_CLR; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F58 */ + __IO uint32_t WFE_B_STAGE3_MUX10_TOG; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F5C */ + __IO uint32_t WFE_B_STG1_5X8_OUT0_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F60 */ + uint8_t RESERVED_127[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F70 */ + uint8_t RESERVED_128[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F80 */ + uint8_t RESERVED_129[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1F90 */ + uint8_t RESERVED_130[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FA0 */ + uint8_t RESERVED_131[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FB0 */ + uint8_t RESERVED_132[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FC0 */ + uint8_t RESERVED_133[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT0_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FD0 */ + uint8_t RESERVED_134[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FE0 */ + uint8_t RESERVED_135[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x1FF0 */ + uint8_t RESERVED_136[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2000 */ + uint8_t RESERVED_137[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2010 */ + uint8_t RESERVED_138[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2020 */ + uint8_t RESERVED_139[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2030 */ + uint8_t RESERVED_140[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2040 */ + uint8_t RESERVED_141[12]; + __IO uint32_t WFE_B_STG1_5X8_OUT1_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2050 */ + uint8_t RESERVED_142[12]; + __IO uint32_t WFE_B_STAGE1_5X8_MASKS_0; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x8 LUT., offset: 0x2060 */ + uint8_t RESERVED_143[12]; + __IO uint32_t WFE_B_STG1_5X1_OUT0; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 1., offset: 0x2070 */ + uint8_t RESERVED_144[12]; + __IO uint32_t WFE_B_STG1_5X1_MASKS; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x1 LUT., offset: 0x2080 */ + uint8_t RESERVED_145[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2090 */ + uint8_t RESERVED_146[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20A0 */ + uint8_t RESERVED_147[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20B0 */ + uint8_t RESERVED_148[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20C0 */ + uint8_t RESERVED_149[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20D0 */ + uint8_t RESERVED_150[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20E0 */ + uint8_t RESERVED_151[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x20F0 */ + uint8_t RESERVED_152[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT0_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2100 */ + uint8_t RESERVED_153[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2110 */ + uint8_t RESERVED_154[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2120 */ + uint8_t RESERVED_155[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2130 */ + uint8_t RESERVED_156[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2140 */ + uint8_t RESERVED_157[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2150 */ + uint8_t RESERVED_158[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2160 */ + uint8_t RESERVED_159[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2170 */ + uint8_t RESERVED_160[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT1_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2180 */ + uint8_t RESERVED_161[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2190 */ + uint8_t RESERVED_162[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21A0 */ + uint8_t RESERVED_163[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21B0 */ + uint8_t RESERVED_164[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21C0 */ + uint8_t RESERVED_165[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21D0 */ + uint8_t RESERVED_166[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21E0 */ + uint8_t RESERVED_167[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x21F0 */ + uint8_t RESERVED_168[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT2_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2200 */ + uint8_t RESERVED_169[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2210 */ + uint8_t RESERVED_170[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2220 */ + uint8_t RESERVED_171[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2230 */ + uint8_t RESERVED_172[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2240 */ + uint8_t RESERVED_173[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2250 */ + uint8_t RESERVED_174[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2260 */ + uint8_t RESERVED_175[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2270 */ + uint8_t RESERVED_176[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT3_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2280 */ + uint8_t RESERVED_177[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2290 */ + uint8_t RESERVED_178[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22A0 */ + uint8_t RESERVED_179[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22B0 */ + uint8_t RESERVED_180[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22C0 */ + uint8_t RESERVED_181[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22D0 */ + uint8_t RESERVED_182[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22E0 */ + uint8_t RESERVED_183[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x22F0 */ + uint8_t RESERVED_184[12]; + __IO uint32_t WFE_B_STG1_8X1_OUT4_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 1., offset: 0x2300 */ + uint8_t RESERVED_185[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2310 */ + uint8_t RESERVED_186[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2320 */ + uint8_t RESERVED_187[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2330 */ + uint8_t RESERVED_188[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2340 */ + uint8_t RESERVED_189[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2350 */ + uint8_t RESERVED_190[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2360 */ + uint8_t RESERVED_191[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2370 */ + uint8_t RESERVED_192[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT0_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2380 */ + uint8_t RESERVED_193[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2390 */ + uint8_t RESERVED_194[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23A0 */ + uint8_t RESERVED_195[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23B0 */ + uint8_t RESERVED_196[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23C0 */ + uint8_t RESERVED_197[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23D0 */ + uint8_t RESERVED_198[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23E0 */ + uint8_t RESERVED_199[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x23F0 */ + uint8_t RESERVED_200[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT1_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2400 */ + uint8_t RESERVED_201[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2410 */ + uint8_t RESERVED_202[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2420 */ + uint8_t RESERVED_203[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2430 */ + uint8_t RESERVED_204[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2440 */ + uint8_t RESERVED_205[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2450 */ + uint8_t RESERVED_206[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2460 */ + uint8_t RESERVED_207[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2470 */ + uint8_t RESERVED_208[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT2_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2480 */ + uint8_t RESERVED_209[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_0; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2490 */ + uint8_t RESERVED_210[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_1; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24A0 */ + uint8_t RESERVED_211[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_2; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24B0 */ + uint8_t RESERVED_212[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_3; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24C0 */ + uint8_t RESERVED_213[28]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_4; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24E0 */ + uint8_t RESERVED_214[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_5; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x24F0 */ + uint8_t RESERVED_215[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_6; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2500 */ + uint8_t RESERVED_216[12]; + __IO uint32_t WFE_B_STG2_5X6_OUT3_7; /**< This register defines the control bits for the pxp wfe sub-block, offset: 0x2510 */ + uint8_t RESERVED_217[12]; + __IO uint32_t WFE_B_STAGE2_5X6_MASKS_0; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x6 LUT., offset: 0x2520 */ + uint8_t RESERVED_218[12]; + __IO uint32_t WFE_B_STAGE2_5X6_ADDR_0; /**< Each Address specifies the MUX position in the MUX array. There is one MUXADDR per 5x6 LUT., offset: 0x2530 */ + uint8_t RESERVED_219[12]; + __IO uint32_t WFE_B_STG2_5X1_OUT0; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 2., offset: 0x2540 */ + uint8_t RESERVED_220[12]; + __IO uint32_t WFE_B_STG2_5X1_OUT1; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 2., offset: 0x2550 */ + uint8_t RESERVED_221[12]; + __IO uint32_t WFE_B_STG2_5X1_OUT2; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 2., offset: 0x2560 */ + uint8_t RESERVED_222[12]; + __IO uint32_t WFE_B_STG2_5X1_OUT3; /**< This register defines the output values (new flag) for the 5x1 LUTs in stage 2., offset: 0x2570 */ + uint8_t RESERVED_223[12]; + __IO uint32_t WFE_B_STG2_5X1_MASKS; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x1 LUT., offset: 0x2580 */ + uint8_t RESERVED_224[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2590 */ + uint8_t RESERVED_225[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25A0 */ + uint8_t RESERVED_226[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25B0 */ + uint8_t RESERVED_227[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25C0 */ + uint8_t RESERVED_228[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25D0 */ + uint8_t RESERVED_229[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25E0 */ + uint8_t RESERVED_230[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x25F0 */ + uint8_t RESERVED_231[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT0_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2600 */ + uint8_t RESERVED_232[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2610 */ + uint8_t RESERVED_233[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2620 */ + uint8_t RESERVED_234[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2630 */ + uint8_t RESERVED_235[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2640 */ + uint8_t RESERVED_236[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2650 */ + uint8_t RESERVED_237[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2660 */ + uint8_t RESERVED_238[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2670 */ + uint8_t RESERVED_239[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT1_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2680 */ + uint8_t RESERVED_240[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2690 */ + uint8_t RESERVED_241[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26A0 */ + uint8_t RESERVED_242[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26B0 */ + uint8_t RESERVED_243[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26C0 */ + uint8_t RESERVED_244[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26D0 */ + uint8_t RESERVED_245[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26E0 */ + uint8_t RESERVED_246[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x26F0 */ + uint8_t RESERVED_247[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT2_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2700 */ + uint8_t RESERVED_248[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_0; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2710 */ + uint8_t RESERVED_249[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_1; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2720 */ + uint8_t RESERVED_250[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_2; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2730 */ + uint8_t RESERVED_251[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_3; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2740 */ + uint8_t RESERVED_252[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_4; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2750 */ + uint8_t RESERVED_253[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_5; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2760 */ + uint8_t RESERVED_254[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_6; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2770 */ + uint8_t RESERVED_255[12]; + __IO uint32_t WFE_B_STG3_F8X1_OUT3_7; /**< This register defines the output values (new flag) for the 8x1 LUTs in stage 3., offset: 0x2780 */ + uint8_t RESERVED_256[12]; + __IO uint32_t WFE_B_STG3_F8X1_MASKS; /**< Each set mask bit enables one of the corresponding flag input bits. There is one mask per 8x1 LUT., offset: 0x2790 */ + uint8_t RESERVED_257[268]; + __IO uint32_t ALU_B_CTRL; /**< This register defines the control bits for the pxp alu sub-block., offset: 0x28A0 */ + __IO uint32_t ALU_B_CTRL_SET; /**< This register defines the control bits for the pxp alu sub-block., offset: 0x28A4 */ + __IO uint32_t ALU_B_CTRL_CLR; /**< This register defines the control bits for the pxp alu sub-block., offset: 0x28A8 */ + __IO uint32_t ALU_B_CTRL_TOG; /**< This register defines the control bits for the pxp alu sub-block., offset: 0x28AC */ + __IO uint32_t ALU_B_BUF_SIZE; /**< This register defines the size of the buffer to be processed by the alu engine., offset: 0x28B0 */ + uint8_t RESERVED_258[12]; + __IO uint32_t ALU_B_INST_ENTRY; /**< This register defines the Entry Address for the Instruction Memory of the ALU., offset: 0x28C0 */ + uint8_t RESERVED_259[12]; + __IO uint32_t ALU_B_PARAM; /**< This register defines the parameter used by SW running on ALU., offset: 0x28D0 */ + uint8_t RESERVED_260[12]; + __IO uint32_t ALU_B_CONFIG; /**< This register defines the hw configuration options for the alu core., offset: 0x28E0 */ + uint8_t RESERVED_261[12]; + __IO uint32_t ALU_B_LUT_CONFIG; /**< This register defines the hw configuration options for the LUT, offset: 0x28F0 */ + __IO uint32_t ALU_B_LUT_CONFIG_SET; /**< This register defines the hw configuration options for the LUT, offset: 0x28F4 */ + __IO uint32_t ALU_B_LUT_CONFIG_CLR; /**< This register defines the hw configuration options for the LUT, offset: 0x28F8 */ + __IO uint32_t ALU_B_LUT_CONFIG_TOG; /**< This register defines the hw configuration options for the LUT, offset: 0x28FC */ + __IO uint32_t ALU_B_LUT_DATA0; /**< This register defines the lower 32-bit data for the LUT, offset: 0x2900 */ + uint8_t RESERVED_262[12]; + __IO uint32_t ALU_B_LUT_DATA1; /**< This register defines the higher 32-bit data for the LUT, offset: 0x2910 */ + uint8_t RESERVED_263[12]; + __IO uint32_t ALU_B_DBG; /**< This register is used for debugging alu block, offset: 0x2920 */ + uint8_t RESERVED_264[220]; + __IO uint32_t HIST_A_CTRL; /**< Histogram Control Register., offset: 0x2A00 */ + uint8_t RESERVED_265[12]; + __IO uint32_t HIST_A_MASK; /**< Histogram Pixel Mask Register., offset: 0x2A10 */ + uint8_t RESERVED_266[12]; + __IO uint32_t HIST_A_BUF_SIZE; /**< Histogram Pixel Buffer Size Register., offset: 0x2A20 */ + uint8_t RESERVED_267[12]; + __I uint32_t HIST_A_TOTAL_PIXEL; /**< Total Number of Pixels Used by Histogram Engine., offset: 0x2A30 */ + uint8_t RESERVED_268[12]; + __I uint32_t HIST_A_ACTIVE_AREA_X; /**< The X Coordinate Offset for Active Area., offset: 0x2A40 */ + uint8_t RESERVED_269[12]; + __I uint32_t HIST_A_ACTIVE_AREA_Y; /**< The Y Coordinate Offset for Active Area., offset: 0x2A50 */ + uint8_t RESERVED_270[12]; + __I uint32_t HIST_A_RAW_STAT0; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2A60 */ + uint8_t RESERVED_271[12]; + __I uint32_t HIST_A_RAW_STAT1; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2A70 */ + uint8_t RESERVED_272[12]; + __IO uint32_t HIST_B_CTRL; /**< Histogram Control Register., offset: 0x2A80 */ + uint8_t RESERVED_273[12]; + __IO uint32_t HIST_B_MASK; /**< Histogram Pixel Mask Register., offset: 0x2A90 */ + uint8_t RESERVED_274[12]; + __IO uint32_t HIST_B_BUF_SIZE; /**< Histogram Pixel Buffer Size Register., offset: 0x2AA0 */ + uint8_t RESERVED_275[12]; + __I uint32_t HIST_B_TOTAL_PIXEL; /**< Total Number of Pixels Used by Histogram Engine., offset: 0x2AB0 */ + uint8_t RESERVED_276[12]; + __I uint32_t HIST_B_ACTIVE_AREA_X; /**< The X Coordinate Offset for Active Area., offset: 0x2AC0 */ + uint8_t RESERVED_277[12]; + __I uint32_t HIST_B_ACTIVE_AREA_Y; /**< The Y Coordinate Offset for Active Area., offset: 0x2AD0 */ + uint8_t RESERVED_278[12]; + __I uint32_t HIST_B_RAW_STAT0; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2AE0 */ + uint8_t RESERVED_279[12]; + __I uint32_t HIST_B_RAW_STAT1; /**< Histogram Result Based on RAW Pixel Value., offset: 0x2AF0 */ + uint8_t RESERVED_280[12]; + __IO uint32_t HIST2_PARAM; /**< 2-level Histogram Parameter Register., offset: 0x2B00 */ + uint8_t RESERVED_281[12]; + __IO uint32_t HIST4_PARAM; /**< 4-level Histogram Parameter Register., offset: 0x2B10 */ + uint8_t RESERVED_282[12]; + __IO uint32_t HIST8_PARAM0; /**< 8-level Histogram Parameter 0 Register., offset: 0x2B20 */ + uint8_t RESERVED_283[12]; + __IO uint32_t HIST8_PARAM1; /**< 8-level Histogram Parameter 1 Register., offset: 0x2B30 */ + uint8_t RESERVED_284[12]; + __IO uint32_t HIST16_PARAM0; /**< 16-level Histogram Parameter 0 Register., offset: 0x2B40 */ + uint8_t RESERVED_285[12]; + __IO uint32_t HIST16_PARAM1; /**< 16-level Histogram Parameter 1 Register., offset: 0x2B50 */ + uint8_t RESERVED_286[12]; + __IO uint32_t HIST16_PARAM2; /**< 16-level Histogram Parameter 2 Register., offset: 0x2B60 */ + uint8_t RESERVED_287[12]; + __IO uint32_t HIST16_PARAM3; /**< 16-level Histogram Parameter 3 Register., offset: 0x2B70 */ + uint8_t RESERVED_288[12]; + __IO uint32_t HIST32_PARAM0; /**< 32-level Histogram Parameter 0 Register., offset: 0x2B80 */ + uint8_t RESERVED_289[12]; + __IO uint32_t HIST32_PARAM1; /**< 32-level Histogram Parameter 1 Register., offset: 0x2B90 */ + uint8_t RESERVED_290[12]; + __IO uint32_t HIST32_PARAM2; /**< 32-level Histogram Parameter 2 Register., offset: 0x2BA0 */ + uint8_t RESERVED_291[12]; + __IO uint32_t HIST32_PARAM3; /**< 32-level Histogram Parameter 3 Register., offset: 0x2BB0 */ + uint8_t RESERVED_292[12]; + __IO uint32_t HIST32_PARAM4; /**< 32-level Histogram Parameter 0 Register., offset: 0x2BC0 */ + uint8_t RESERVED_293[12]; + __IO uint32_t HIST32_PARAM5; /**< 32-level Histogram Parameter 1 Register., offset: 0x2BD0 */ + uint8_t RESERVED_294[12]; + __IO uint32_t HIST32_PARAM6; /**< 32-level Histogram Parameter 2 Register., offset: 0x2BE0 */ + uint8_t RESERVED_295[12]; + __IO uint32_t HIST32_PARAM7; /**< 32-level Histogram Parameter 3 Register., offset: 0x2BF0 */ + uint8_t RESERVED_296[252]; + __IO uint32_t HANDSHAKE_READY_MUX0; /**< This register defines the pxp subblock handshake signals ready mux on top level., offset: 0x2CF0 */ + uint8_t RESERVED_297[12]; + __IO uint32_t HANDSHAKE_READY_MUX1; /**< This register defines the pxp subblock handshake signals ready mux on top level., offset: 0x2D00 */ + uint8_t RESERVED_298[12]; + __IO uint32_t HANDSHAKE_DONE_MUX0; /**< This register defines the pxp subblock handshake signals done mux on top level., offset: 0x2D10 */ + uint8_t RESERVED_299[12]; + __IO uint32_t HANDSHAKE_DONE_MUX1; /**< This register defines the pxp subblock handshake signals done mux on top level., offset: 0x2D20 */ +} PXP_Type; + +/* ---------------------------------------------------------------------------- + -- PXP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Register_Masks PXP Register Masks + * @{ + */ + +/*! @name CTRL - Control Register 0 */ +#define PXP_CTRL_ENABLE_MASK (0x1U) +#define PXP_CTRL_ENABLE_SHIFT (0U) +#define PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK) +#define PXP_CTRL_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK) +#define PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK (0x8U) +#define PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT (3U) +#define PXP_CTRL_LUT_DMA_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK) +#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK) +#define PXP_CTRL_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +#define PXP_CTRL_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_HANDSHAKE_ABORT_SKIP_MASK) +#define PXP_CTRL_ROTATE0_MASK (0x300U) +#define PXP_CTRL_ROTATE0_SHIFT (8U) +#define PXP_CTRL_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE0_SHIFT)) & PXP_CTRL_ROTATE0_MASK) +#define PXP_CTRL_HFLIP0_MASK (0x400U) +#define PXP_CTRL_HFLIP0_SHIFT (10U) +#define PXP_CTRL_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP0_SHIFT)) & PXP_CTRL_HFLIP0_MASK) +#define PXP_CTRL_VFLIP0_MASK (0x800U) +#define PXP_CTRL_VFLIP0_SHIFT (11U) +#define PXP_CTRL_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP0_SHIFT)) & PXP_CTRL_VFLIP0_MASK) +#define PXP_CTRL_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_ROTATE1_SHIFT (12U) +#define PXP_CTRL_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE1_SHIFT)) & PXP_CTRL_ROTATE1_MASK) +#define PXP_CTRL_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_HFLIP1_SHIFT (14U) +#define PXP_CTRL_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP1_SHIFT)) & PXP_CTRL_HFLIP1_MASK) +#define PXP_CTRL_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_VFLIP1_SHIFT (15U) +#define PXP_CTRL_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP1_SHIFT)) & PXP_CTRL_VFLIP1_MASK) +#define PXP_CTRL_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_ENABLE_PS_AS_OUT_SHIFT (16U) +#define PXP_CTRL_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_ENABLE_PS_AS_OUT_MASK) +#define PXP_CTRL_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_DITHER_SHIFT)) & PXP_CTRL_ENABLE_DITHER_MASK) +#define PXP_CTRL_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_ENABLE_WFE_B_MASK) +#define PXP_CTRL_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK) +#define PXP_CTRL_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_CSC2_SHIFT)) & PXP_CTRL_ENABLE_CSC2_MASK) +#define PXP_CTRL_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LUT_SHIFT)) & PXP_CTRL_ENABLE_LUT_MASK) +#define PXP_CTRL_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_ENABLE_ROTATE0_MASK) +#define PXP_CTRL_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_ENABLE_ROTATE1_MASK) +#define PXP_CTRL_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK) +#define PXP_CTRL_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_CLKGATE_SHIFT (30U) +#define PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK) +#define PXP_CTRL_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_SFTRST_SHIFT (31U) +#define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK) + +/*! @name CTRL_SET - Control Register 0 */ +#define PXP_CTRL_SET_ENABLE_MASK (0x1U) +#define PXP_CTRL_SET_ENABLE_SHIFT (0U) +#define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK) +#define PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_MASK (0x8U) +#define PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_SHIFT (3U) +#define PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_LUT_DMA_IRQ_ENABLE_MASK) +#define PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD0_HANDSHAKE_MASK) +#define PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +#define PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_SET_HANDSHAKE_ABORT_SKIP_MASK) +#define PXP_CTRL_SET_ROTATE0_MASK (0x300U) +#define PXP_CTRL_SET_ROTATE0_SHIFT (8U) +#define PXP_CTRL_SET_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE0_SHIFT)) & PXP_CTRL_SET_ROTATE0_MASK) +#define PXP_CTRL_SET_HFLIP0_MASK (0x400U) +#define PXP_CTRL_SET_HFLIP0_SHIFT (10U) +#define PXP_CTRL_SET_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP0_SHIFT)) & PXP_CTRL_SET_HFLIP0_MASK) +#define PXP_CTRL_SET_VFLIP0_MASK (0x800U) +#define PXP_CTRL_SET_VFLIP0_SHIFT (11U) +#define PXP_CTRL_SET_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP0_SHIFT)) & PXP_CTRL_SET_VFLIP0_MASK) +#define PXP_CTRL_SET_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_SET_ROTATE1_SHIFT (12U) +#define PXP_CTRL_SET_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE1_SHIFT)) & PXP_CTRL_SET_ROTATE1_MASK) +#define PXP_CTRL_SET_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_SET_HFLIP1_SHIFT (14U) +#define PXP_CTRL_SET_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP1_SHIFT)) & PXP_CTRL_SET_HFLIP1_MASK) +#define PXP_CTRL_SET_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_SET_VFLIP1_SHIFT (15U) +#define PXP_CTRL_SET_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP1_SHIFT)) & PXP_CTRL_SET_VFLIP1_MASK) +#define PXP_CTRL_SET_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_SET_ENABLE_PS_AS_OUT_SHIFT (16U) +#define PXP_CTRL_SET_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_SET_ENABLE_PS_AS_OUT_MASK) +#define PXP_CTRL_SET_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL_SET_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL_SET_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_DITHER_SHIFT)) & PXP_CTRL_SET_ENABLE_DITHER_MASK) +#define PXP_CTRL_SET_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL_SET_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL_SET_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_SET_ENABLE_WFE_B_MASK) +#define PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK) +#define PXP_CTRL_SET_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_SET_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL_SET_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_CSC2_SHIFT)) & PXP_CTRL_SET_ENABLE_CSC2_MASK) +#define PXP_CTRL_SET_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL_SET_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL_SET_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LUT_SHIFT)) & PXP_CTRL_SET_ENABLE_LUT_MASK) +#define PXP_CTRL_SET_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_SET_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL_SET_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_SET_ENABLE_ROTATE0_MASK) +#define PXP_CTRL_SET_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_SET_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL_SET_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_SET_ENABLE_ROTATE1_MASK) +#define PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_SET_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK) +#define PXP_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_SET_CLKGATE_SHIFT (30U) +#define PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK) +#define PXP_CTRL_SET_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_SET_SFTRST_SHIFT (31U) +#define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK) + +/*! @name CTRL_CLR - Control Register 0 */ +#define PXP_CTRL_CLR_ENABLE_MASK (0x1U) +#define PXP_CTRL_CLR_ENABLE_SHIFT (0U) +#define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK) +#define PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_MASK (0x8U) +#define PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_SHIFT (3U) +#define PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_LUT_DMA_IRQ_ENABLE_MASK) +#define PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD0_HANDSHAKE_MASK) +#define PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +#define PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_CLR_HANDSHAKE_ABORT_SKIP_MASK) +#define PXP_CTRL_CLR_ROTATE0_MASK (0x300U) +#define PXP_CTRL_CLR_ROTATE0_SHIFT (8U) +#define PXP_CTRL_CLR_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE0_SHIFT)) & PXP_CTRL_CLR_ROTATE0_MASK) +#define PXP_CTRL_CLR_HFLIP0_MASK (0x400U) +#define PXP_CTRL_CLR_HFLIP0_SHIFT (10U) +#define PXP_CTRL_CLR_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP0_SHIFT)) & PXP_CTRL_CLR_HFLIP0_MASK) +#define PXP_CTRL_CLR_VFLIP0_MASK (0x800U) +#define PXP_CTRL_CLR_VFLIP0_SHIFT (11U) +#define PXP_CTRL_CLR_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP0_SHIFT)) & PXP_CTRL_CLR_VFLIP0_MASK) +#define PXP_CTRL_CLR_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_CLR_ROTATE1_SHIFT (12U) +#define PXP_CTRL_CLR_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE1_SHIFT)) & PXP_CTRL_CLR_ROTATE1_MASK) +#define PXP_CTRL_CLR_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_CLR_HFLIP1_SHIFT (14U) +#define PXP_CTRL_CLR_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP1_SHIFT)) & PXP_CTRL_CLR_HFLIP1_MASK) +#define PXP_CTRL_CLR_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_CLR_VFLIP1_SHIFT (15U) +#define PXP_CTRL_CLR_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP1_SHIFT)) & PXP_CTRL_CLR_VFLIP1_MASK) +#define PXP_CTRL_CLR_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_CLR_ENABLE_PS_AS_OUT_SHIFT (16U) +#define PXP_CTRL_CLR_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_CLR_ENABLE_PS_AS_OUT_MASK) +#define PXP_CTRL_CLR_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL_CLR_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL_CLR_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_DITHER_SHIFT)) & PXP_CTRL_CLR_ENABLE_DITHER_MASK) +#define PXP_CTRL_CLR_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL_CLR_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL_CLR_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_CLR_ENABLE_WFE_B_MASK) +#define PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK) +#define PXP_CTRL_CLR_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_CLR_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL_CLR_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_CSC2_SHIFT)) & PXP_CTRL_CLR_ENABLE_CSC2_MASK) +#define PXP_CTRL_CLR_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL_CLR_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL_CLR_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LUT_SHIFT)) & PXP_CTRL_CLR_ENABLE_LUT_MASK) +#define PXP_CTRL_CLR_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_CLR_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL_CLR_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_CLR_ENABLE_ROTATE0_MASK) +#define PXP_CTRL_CLR_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_CLR_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL_CLR_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_CLR_ENABLE_ROTATE1_MASK) +#define PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK) +#define PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_CLR_CLKGATE_SHIFT (30U) +#define PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK) +#define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_CLR_SFTRST_SHIFT (31U) +#define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK) + +/*! @name CTRL_TOG - Control Register 0 */ +#define PXP_CTRL_TOG_ENABLE_MASK (0x1U) +#define PXP_CTRL_TOG_ENABLE_SHIFT (0U) +#define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK) +#define PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U) +#define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U) +#define PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U) +#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK) +#define PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_MASK (0x8U) +#define PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_SHIFT (3U) +#define PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_LUT_DMA_IRQ_ENABLE_MASK) +#define PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_MASK (0x10U) +#define PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_SHIFT (4U) +#define PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD0_HANDSHAKE_MASK) +#define PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_MASK (0x20U) +#define PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_SHIFT (5U) +#define PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_SHIFT)) & PXP_CTRL_TOG_HANDSHAKE_ABORT_SKIP_MASK) +#define PXP_CTRL_TOG_ROTATE0_MASK (0x300U) +#define PXP_CTRL_TOG_ROTATE0_SHIFT (8U) +#define PXP_CTRL_TOG_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE0_SHIFT)) & PXP_CTRL_TOG_ROTATE0_MASK) +#define PXP_CTRL_TOG_HFLIP0_MASK (0x400U) +#define PXP_CTRL_TOG_HFLIP0_SHIFT (10U) +#define PXP_CTRL_TOG_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP0_SHIFT)) & PXP_CTRL_TOG_HFLIP0_MASK) +#define PXP_CTRL_TOG_VFLIP0_MASK (0x800U) +#define PXP_CTRL_TOG_VFLIP0_SHIFT (11U) +#define PXP_CTRL_TOG_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP0_SHIFT)) & PXP_CTRL_TOG_VFLIP0_MASK) +#define PXP_CTRL_TOG_ROTATE1_MASK (0x3000U) +#define PXP_CTRL_TOG_ROTATE1_SHIFT (12U) +#define PXP_CTRL_TOG_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE1_SHIFT)) & PXP_CTRL_TOG_ROTATE1_MASK) +#define PXP_CTRL_TOG_HFLIP1_MASK (0x4000U) +#define PXP_CTRL_TOG_HFLIP1_SHIFT (14U) +#define PXP_CTRL_TOG_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP1_SHIFT)) & PXP_CTRL_TOG_HFLIP1_MASK) +#define PXP_CTRL_TOG_VFLIP1_MASK (0x8000U) +#define PXP_CTRL_TOG_VFLIP1_SHIFT (15U) +#define PXP_CTRL_TOG_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP1_SHIFT)) & PXP_CTRL_TOG_VFLIP1_MASK) +#define PXP_CTRL_TOG_ENABLE_PS_AS_OUT_MASK (0x10000U) +#define PXP_CTRL_TOG_ENABLE_PS_AS_OUT_SHIFT (16U) +#define PXP_CTRL_TOG_ENABLE_PS_AS_OUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_PS_AS_OUT_SHIFT)) & PXP_CTRL_TOG_ENABLE_PS_AS_OUT_MASK) +#define PXP_CTRL_TOG_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL_TOG_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL_TOG_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_DITHER_SHIFT)) & PXP_CTRL_TOG_ENABLE_DITHER_MASK) +#define PXP_CTRL_TOG_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL_TOG_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL_TOG_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_WFE_B_SHIFT)) & PXP_CTRL_TOG_ENABLE_WFE_B_MASK) +#define PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK) +#define PXP_CTRL_TOG_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL_TOG_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL_TOG_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_CSC2_SHIFT)) & PXP_CTRL_TOG_ENABLE_CSC2_MASK) +#define PXP_CTRL_TOG_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL_TOG_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL_TOG_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LUT_SHIFT)) & PXP_CTRL_TOG_ENABLE_LUT_MASK) +#define PXP_CTRL_TOG_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL_TOG_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL_TOG_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL_TOG_ENABLE_ROTATE0_MASK) +#define PXP_CTRL_TOG_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL_TOG_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL_TOG_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL_TOG_ENABLE_ROTATE1_MASK) +#define PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U) +#define PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U) +#define PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK) +#define PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define PXP_CTRL_TOG_CLKGATE_SHIFT (30U) +#define PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK) +#define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define PXP_CTRL_TOG_SFTRST_SHIFT (31U) +#define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK) + +/*! @name STAT - Status Register */ +#define PXP_STAT_IRQ0_MASK (0x1U) +#define PXP_STAT_IRQ0_SHIFT (0U) +#define PXP_STAT_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ0_SHIFT)) & PXP_STAT_IRQ0_MASK) +#define PXP_STAT_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_AXI_WRITE_ERROR_0_SHIFT (1U) +#define PXP_STAT_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_0_MASK) +#define PXP_STAT_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_AXI_READ_ERROR_0_SHIFT (2U) +#define PXP_STAT_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_AXI_READ_ERROR_0_MASK) +#define PXP_STAT_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK) +#define PXP_STAT_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_AXI_ERROR_ID_0_SHIFT (4U) +#define PXP_STAT_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_AXI_ERROR_ID_0_MASK) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_AXI_WRITE_ERROR_1_SHIFT (9U) +#define PXP_STAT_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_1_MASK) +#define PXP_STAT_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_AXI_READ_ERROR_1_SHIFT (10U) +#define PXP_STAT_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_AXI_READ_ERROR_1_MASK) +#define PXP_STAT_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_AXI_ERROR_ID_1_SHIFT (12U) +#define PXP_STAT_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_AXI_ERROR_ID_1_MASK) +#define PXP_STAT_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_BLOCKY_SHIFT (16U) +#define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK) +#define PXP_STAT_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_BLOCKX_SHIFT (24U) +#define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK) + +/*! @name STAT_SET - Status Register */ +#define PXP_STAT_SET_IRQ0_MASK (0x1U) +#define PXP_STAT_SET_IRQ0_SHIFT (0U) +#define PXP_STAT_SET_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ0_SHIFT)) & PXP_STAT_SET_IRQ0_MASK) +#define PXP_STAT_SET_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_0_SHIFT (1U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_0_MASK) +#define PXP_STAT_SET_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_SET_AXI_READ_ERROR_0_SHIFT (2U) +#define PXP_STAT_SET_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_0_MASK) +#define PXP_STAT_SET_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_SET_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK) +#define PXP_STAT_SET_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_SET_AXI_ERROR_ID_0_SHIFT (4U) +#define PXP_STAT_SET_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_0_MASK) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_SET_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_1_SHIFT (9U) +#define PXP_STAT_SET_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_1_MASK) +#define PXP_STAT_SET_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_SET_AXI_READ_ERROR_1_SHIFT (10U) +#define PXP_STAT_SET_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_1_MASK) +#define PXP_STAT_SET_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_SET_AXI_ERROR_ID_1_SHIFT (12U) +#define PXP_STAT_SET_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_1_MASK) +#define PXP_STAT_SET_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_SET_BLOCKY_SHIFT (16U) +#define PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK) +#define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_SET_BLOCKX_SHIFT (24U) +#define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK) + +/*! @name STAT_CLR - Status Register */ +#define PXP_STAT_CLR_IRQ0_MASK (0x1U) +#define PXP_STAT_CLR_IRQ0_SHIFT (0U) +#define PXP_STAT_CLR_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ0_SHIFT)) & PXP_STAT_CLR_IRQ0_MASK) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_0_SHIFT (1U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_0_MASK) +#define PXP_STAT_CLR_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_CLR_AXI_READ_ERROR_0_SHIFT (2U) +#define PXP_STAT_CLR_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_0_MASK) +#define PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK) +#define PXP_STAT_CLR_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_CLR_AXI_ERROR_ID_0_SHIFT (4U) +#define PXP_STAT_CLR_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_0_MASK) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_1_SHIFT (9U) +#define PXP_STAT_CLR_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_1_MASK) +#define PXP_STAT_CLR_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_CLR_AXI_READ_ERROR_1_SHIFT (10U) +#define PXP_STAT_CLR_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_1_MASK) +#define PXP_STAT_CLR_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_CLR_AXI_ERROR_ID_1_SHIFT (12U) +#define PXP_STAT_CLR_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_1_MASK) +#define PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_CLR_BLOCKY_SHIFT (16U) +#define PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK) +#define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_CLR_BLOCKX_SHIFT (24U) +#define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK) + +/*! @name STAT_TOG - Status Register */ +#define PXP_STAT_TOG_IRQ0_MASK (0x1U) +#define PXP_STAT_TOG_IRQ0_SHIFT (0U) +#define PXP_STAT_TOG_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ0_SHIFT)) & PXP_STAT_TOG_IRQ0_MASK) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_0_MASK (0x2U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_0_SHIFT (1U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_0_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_0_MASK) +#define PXP_STAT_TOG_AXI_READ_ERROR_0_MASK (0x4U) +#define PXP_STAT_TOG_AXI_READ_ERROR_0_SHIFT (2U) +#define PXP_STAT_TOG_AXI_READ_ERROR_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_0_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_0_MASK) +#define PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U) +#define PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U) +#define PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK) +#define PXP_STAT_TOG_AXI_ERROR_ID_0_MASK (0xF0U) +#define PXP_STAT_TOG_AXI_ERROR_ID_0_SHIFT (4U) +#define PXP_STAT_TOG_AXI_ERROR_ID_0(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_0_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_0_MASK) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_1_MASK (0x200U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_1_SHIFT (9U) +#define PXP_STAT_TOG_AXI_WRITE_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_1_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_1_MASK) +#define PXP_STAT_TOG_AXI_READ_ERROR_1_MASK (0x400U) +#define PXP_STAT_TOG_AXI_READ_ERROR_1_SHIFT (10U) +#define PXP_STAT_TOG_AXI_READ_ERROR_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_1_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_1_MASK) +#define PXP_STAT_TOG_AXI_ERROR_ID_1_MASK (0xF000U) +#define PXP_STAT_TOG_AXI_ERROR_ID_1_SHIFT (12U) +#define PXP_STAT_TOG_AXI_ERROR_ID_1(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_1_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_1_MASK) +#define PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U) +#define PXP_STAT_TOG_BLOCKY_SHIFT (16U) +#define PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK) +#define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U) +#define PXP_STAT_TOG_BLOCKX_SHIFT (24U) +#define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK) + +/*! @name OUT_CTRL - Output Buffer Control Register */ +#define PXP_OUT_CTRL_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK) + +/*! @name OUT_CTRL_SET - Output Buffer Control Register */ +#define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK) + +/*! @name OUT_CTRL_CLR - Output Buffer Control Register */ +#define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK) + +/*! @name OUT_CTRL_TOG - Output Buffer Control Register */ +#define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU) +#define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U) +#define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U) +#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U) +#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK) +#define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U) +#define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U) +#define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK) + +/*! @name OUT_BUF - Output Frame Buffer Pointer */ +#define PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_OUT_BUF_ADDR_SHIFT (0U) +#define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK) + +/*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */ +#define PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU) +#define PXP_OUT_BUF2_ADDR_SHIFT (0U) +#define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK) + +/*! @name OUT_PITCH - Output Buffer Pitch */ +#define PXP_OUT_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_OUT_PITCH_PITCH_SHIFT (0U) +#define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK) + +/*! @name OUT_LRC - Output Surface Lower Right Coordinate */ +#define PXP_OUT_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_LRC_Y_SHIFT (0U) +#define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK) +#define PXP_OUT_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_LRC_X_SHIFT (16U) +#define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK) + +/*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */ +#define PXP_OUT_PS_ULC_Y_MASK (0x3FFFU) +#define PXP_OUT_PS_ULC_Y_SHIFT (0U) +#define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK) +#define PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U) +#define PXP_OUT_PS_ULC_X_SHIFT (16U) +#define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK) + +/*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */ +#define PXP_OUT_PS_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_PS_LRC_Y_SHIFT (0U) +#define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK) +#define PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_PS_LRC_X_SHIFT (16U) +#define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK) + +/*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */ +#define PXP_OUT_AS_ULC_Y_MASK (0x3FFFU) +#define PXP_OUT_AS_ULC_Y_SHIFT (0U) +#define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK) +#define PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U) +#define PXP_OUT_AS_ULC_X_SHIFT (16U) +#define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK) + +/*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */ +#define PXP_OUT_AS_LRC_Y_MASK (0x3FFFU) +#define PXP_OUT_AS_LRC_Y_SHIFT (0U) +#define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK) +#define PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U) +#define PXP_OUT_AS_LRC_X_SHIFT (16U) +#define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK) + +/*! @name PS_CTRL - Processed Surface (PS) Control Register */ +#define PXP_PS_CTRL_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK) +#define PXP_PS_CTRL_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_WB_SWAP_SHIFT (6U) +#define PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK) +#define PXP_PS_CTRL_DECY_MASK (0x300U) +#define PXP_PS_CTRL_DECY_SHIFT (8U) +#define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK) +#define PXP_PS_CTRL_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_DECX_SHIFT (10U) +#define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK) + +/*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */ +#define PXP_PS_CTRL_SET_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK) +#define PXP_PS_CTRL_SET_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_SET_WB_SWAP_SHIFT (6U) +#define PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK) +#define PXP_PS_CTRL_SET_DECY_MASK (0x300U) +#define PXP_PS_CTRL_SET_DECY_SHIFT (8U) +#define PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK) +#define PXP_PS_CTRL_SET_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_SET_DECX_SHIFT (10U) +#define PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK) + +/*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */ +#define PXP_PS_CTRL_CLR_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK) +#define PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (6U) +#define PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK) +#define PXP_PS_CTRL_CLR_DECY_MASK (0x300U) +#define PXP_PS_CTRL_CLR_DECY_SHIFT (8U) +#define PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK) +#define PXP_PS_CTRL_CLR_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_CLR_DECX_SHIFT (10U) +#define PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK) + +/*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */ +#define PXP_PS_CTRL_TOG_FORMAT_MASK (0x3FU) +#define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U) +#define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK) +#define PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x40U) +#define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (6U) +#define PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK) +#define PXP_PS_CTRL_TOG_DECY_MASK (0x300U) +#define PXP_PS_CTRL_TOG_DECY_SHIFT (8U) +#define PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK) +#define PXP_PS_CTRL_TOG_DECX_MASK (0xC00U) +#define PXP_PS_CTRL_TOG_DECX_SHIFT (10U) +#define PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK) + +/*! @name PS_BUF - PS Input Buffer Address */ +#define PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_BUF_ADDR_SHIFT (0U) +#define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK) + +/*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */ +#define PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_UBUF_ADDR_SHIFT (0U) +#define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK) + +/*! @name PS_VBUF - PS V/Cr Input Buffer Address */ +#define PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_PS_VBUF_ADDR_SHIFT (0U) +#define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK) + +/*! @name PS_PITCH - Processed Surface Pitch */ +#define PXP_PS_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_PS_PITCH_PITCH_SHIFT (0U) +#define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK) + +/*! @name PS_BACKGROUND_0 - PS Background Color */ +#define PXP_PS_BACKGROUND_0_COLOR_MASK (0xFFFFFFU) +#define PXP_PS_BACKGROUND_0_COLOR_SHIFT (0U) +#define PXP_PS_BACKGROUND_0_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_0_COLOR_SHIFT)) & PXP_PS_BACKGROUND_0_COLOR_MASK) + +/*! @name PS_SCALE - PS Scale Factor Register */ +#define PXP_PS_SCALE_XSCALE_MASK (0x7FFFU) +#define PXP_PS_SCALE_XSCALE_SHIFT (0U) +#define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK) +#define PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U) +#define PXP_PS_SCALE_YSCALE_SHIFT (16U) +#define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK) + +/*! @name PS_OFFSET - PS Scale Offset Register */ +#define PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU) +#define PXP_PS_OFFSET_XOFFSET_SHIFT (0U) +#define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK) +#define PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U) +#define PXP_PS_OFFSET_YOFFSET_SHIFT (16U) +#define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK) + +/*! @name PS_CLRKEYLOW_0 - PS Color Key Low */ +#define PXP_PS_CLRKEYLOW_0_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYLOW_0_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYLOW_0_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_0_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_0_PIXEL_MASK) + +/*! @name PS_CLRKEYHIGH_0 - PS Color Key High */ +#define PXP_PS_CLRKEYHIGH_0_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYHIGH_0_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYHIGH_0_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_0_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_0_PIXEL_MASK) + +/*! @name AS_CTRL - Alpha Surface Control */ +#define PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U) +#define PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U) +#define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK) +#define PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) +#define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) +#define PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK) +#define PXP_AS_CTRL_FORMAT_MASK (0xF0U) +#define PXP_AS_CTRL_FORMAT_SHIFT (4U) +#define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK) +#define PXP_AS_CTRL_ALPHA_MASK (0xFF00U) +#define PXP_AS_CTRL_ALPHA_SHIFT (8U) +#define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK) +#define PXP_AS_CTRL_ROP_MASK (0xF0000U) +#define PXP_AS_CTRL_ROP_SHIFT (16U) +#define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK) +#define PXP_AS_CTRL_ALPHA0_INVERT_MASK (0x100000U) +#define PXP_AS_CTRL_ALPHA0_INVERT_SHIFT (20U) +#define PXP_AS_CTRL_ALPHA0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA0_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA0_INVERT_MASK) +#define PXP_AS_CTRL_ALPHA1_INVERT_MASK (0x200000U) +#define PXP_AS_CTRL_ALPHA1_INVERT_SHIFT (21U) +#define PXP_AS_CTRL_ALPHA1_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA1_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA1_INVERT_MASK) + +/*! @name AS_BUF - Alpha Surface Buffer Pointer */ +#define PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_AS_BUF_ADDR_SHIFT (0U) +#define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK) + +/*! @name AS_PITCH - Alpha Surface Pitch */ +#define PXP_AS_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_AS_PITCH_PITCH_SHIFT (0U) +#define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK) + +/*! @name AS_CLRKEYLOW_0 - Overlay Color Key Low */ +#define PXP_AS_CLRKEYLOW_0_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYLOW_0_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYLOW_0_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_0_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_0_PIXEL_MASK) + +/*! @name AS_CLRKEYHIGH_0 - Overlay Color Key High */ +#define PXP_AS_CLRKEYHIGH_0_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYHIGH_0_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYHIGH_0_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_0_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_0_PIXEL_MASK) + +/*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */ +#define PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU) +#define PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U) +#define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK) +#define PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U) +#define PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U) +#define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK) +#define PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U) +#define PXP_CSC1_COEF0_C0_SHIFT (18U) +#define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK) +#define PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U) +#define PXP_CSC1_COEF0_BYPASS_SHIFT (30U) +#define PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK) +#define PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U) +#define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U) +#define PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK) + +/*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */ +#define PXP_CSC1_COEF1_C4_MASK (0x7FFU) +#define PXP_CSC1_COEF1_C4_SHIFT (0U) +#define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK) +#define PXP_CSC1_COEF1_C1_MASK (0x7FF0000U) +#define PXP_CSC1_COEF1_C1_SHIFT (16U) +#define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK) + +/*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */ +#define PXP_CSC1_COEF2_C3_MASK (0x7FFU) +#define PXP_CSC1_COEF2_C3_SHIFT (0U) +#define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK) +#define PXP_CSC1_COEF2_C2_MASK (0x7FF0000U) +#define PXP_CSC1_COEF2_C2_SHIFT (16U) +#define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK) + +/*! @name CSC2_CTRL - Color Space Conversion Control Register. */ +#define PXP_CSC2_CTRL_BYPASS_MASK (0x1U) +#define PXP_CSC2_CTRL_BYPASS_SHIFT (0U) +#define PXP_CSC2_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_CTRL_BYPASS_SHIFT)) & PXP_CSC2_CTRL_BYPASS_MASK) +#define PXP_CSC2_CTRL_CSC_MODE_MASK (0x6U) +#define PXP_CSC2_CTRL_CSC_MODE_SHIFT (1U) +#define PXP_CSC2_CTRL_CSC_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_CTRL_CSC_MODE_SHIFT)) & PXP_CSC2_CTRL_CSC_MODE_MASK) + +/*! @name CSC2_COEF0 - Color Space Conversion Coefficient Register 0 */ +#define PXP_CSC2_COEF0_A1_MASK (0x7FFU) +#define PXP_CSC2_COEF0_A1_SHIFT (0U) +#define PXP_CSC2_COEF0_A1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF0_A1_SHIFT)) & PXP_CSC2_COEF0_A1_MASK) +#define PXP_CSC2_COEF0_A2_MASK (0x7FF0000U) +#define PXP_CSC2_COEF0_A2_SHIFT (16U) +#define PXP_CSC2_COEF0_A2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF0_A2_SHIFT)) & PXP_CSC2_COEF0_A2_MASK) + +/*! @name CSC2_COEF1 - Color Space Conversion Coefficient Register 1 */ +#define PXP_CSC2_COEF1_A3_MASK (0x7FFU) +#define PXP_CSC2_COEF1_A3_SHIFT (0U) +#define PXP_CSC2_COEF1_A3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF1_A3_SHIFT)) & PXP_CSC2_COEF1_A3_MASK) +#define PXP_CSC2_COEF1_B1_MASK (0x7FF0000U) +#define PXP_CSC2_COEF1_B1_SHIFT (16U) +#define PXP_CSC2_COEF1_B1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF1_B1_SHIFT)) & PXP_CSC2_COEF1_B1_MASK) + +/*! @name CSC2_COEF2 - Color Space Conversion Coefficient Register 2 */ +#define PXP_CSC2_COEF2_B2_MASK (0x7FFU) +#define PXP_CSC2_COEF2_B2_SHIFT (0U) +#define PXP_CSC2_COEF2_B2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF2_B2_SHIFT)) & PXP_CSC2_COEF2_B2_MASK) +#define PXP_CSC2_COEF2_B3_MASK (0x7FF0000U) +#define PXP_CSC2_COEF2_B3_SHIFT (16U) +#define PXP_CSC2_COEF2_B3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF2_B3_SHIFT)) & PXP_CSC2_COEF2_B3_MASK) + +/*! @name CSC2_COEF3 - Color Space Conversion Coefficient Register 3 */ +#define PXP_CSC2_COEF3_C1_MASK (0x7FFU) +#define PXP_CSC2_COEF3_C1_SHIFT (0U) +#define PXP_CSC2_COEF3_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF3_C1_SHIFT)) & PXP_CSC2_COEF3_C1_MASK) +#define PXP_CSC2_COEF3_C2_MASK (0x7FF0000U) +#define PXP_CSC2_COEF3_C2_SHIFT (16U) +#define PXP_CSC2_COEF3_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF3_C2_SHIFT)) & PXP_CSC2_COEF3_C2_MASK) + +/*! @name CSC2_COEF4 - Color Space Conversion Coefficient Register 4 */ +#define PXP_CSC2_COEF4_C3_MASK (0x7FFU) +#define PXP_CSC2_COEF4_C3_SHIFT (0U) +#define PXP_CSC2_COEF4_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF4_C3_SHIFT)) & PXP_CSC2_COEF4_C3_MASK) +#define PXP_CSC2_COEF4_D1_MASK (0x1FF0000U) +#define PXP_CSC2_COEF4_D1_SHIFT (16U) +#define PXP_CSC2_COEF4_D1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF4_D1_SHIFT)) & PXP_CSC2_COEF4_D1_MASK) + +/*! @name CSC2_COEF5 - Color Space Conversion Coefficient Register 5 */ +#define PXP_CSC2_COEF5_D2_MASK (0x1FFU) +#define PXP_CSC2_COEF5_D2_SHIFT (0U) +#define PXP_CSC2_COEF5_D2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF5_D2_SHIFT)) & PXP_CSC2_COEF5_D2_MASK) +#define PXP_CSC2_COEF5_D3_MASK (0x1FF0000U) +#define PXP_CSC2_COEF5_D3_SHIFT (16U) +#define PXP_CSC2_COEF5_D3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC2_COEF5_D3_SHIFT)) & PXP_CSC2_COEF5_D3_MASK) + +/*! @name LUT_CTRL - Lookup Table Control Register. */ +#define PXP_LUT_CTRL_DMA_START_MASK (0x1U) +#define PXP_LUT_CTRL_DMA_START_SHIFT (0U) +#define PXP_LUT_CTRL_DMA_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_DMA_START_SHIFT)) & PXP_LUT_CTRL_DMA_START_MASK) +#define PXP_LUT_CTRL_INVALID_MASK (0x100U) +#define PXP_LUT_CTRL_INVALID_SHIFT (8U) +#define PXP_LUT_CTRL_INVALID(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_INVALID_SHIFT)) & PXP_LUT_CTRL_INVALID_MASK) +#define PXP_LUT_CTRL_LRU_UPD_MASK (0x200U) +#define PXP_LUT_CTRL_LRU_UPD_SHIFT (9U) +#define PXP_LUT_CTRL_LRU_UPD(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_LRU_UPD_SHIFT)) & PXP_LUT_CTRL_LRU_UPD_MASK) +#define PXP_LUT_CTRL_SEL_8KB_MASK (0x400U) +#define PXP_LUT_CTRL_SEL_8KB_SHIFT (10U) +#define PXP_LUT_CTRL_SEL_8KB(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_SEL_8KB_SHIFT)) & PXP_LUT_CTRL_SEL_8KB_MASK) +#define PXP_LUT_CTRL_OUT_MODE_MASK (0x30000U) +#define PXP_LUT_CTRL_OUT_MODE_SHIFT (16U) +#define PXP_LUT_CTRL_OUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_OUT_MODE_SHIFT)) & PXP_LUT_CTRL_OUT_MODE_MASK) +#define PXP_LUT_CTRL_LOOKUP_MODE_MASK (0x3000000U) +#define PXP_LUT_CTRL_LOOKUP_MODE_SHIFT (24U) +#define PXP_LUT_CTRL_LOOKUP_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_LOOKUP_MODE_SHIFT)) & PXP_LUT_CTRL_LOOKUP_MODE_MASK) +#define PXP_LUT_CTRL_BYPASS_MASK (0x80000000U) +#define PXP_LUT_CTRL_BYPASS_SHIFT (31U) +#define PXP_LUT_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_CTRL_BYPASS_SHIFT)) & PXP_LUT_CTRL_BYPASS_MASK) + +/*! @name LUT_ADDR - Lookup Table Control Register. */ +#define PXP_LUT_ADDR_ADDR_MASK (0x3FFFU) +#define PXP_LUT_ADDR_ADDR_SHIFT (0U) +#define PXP_LUT_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_ADDR_ADDR_SHIFT)) & PXP_LUT_ADDR_ADDR_MASK) +#define PXP_LUT_ADDR_NUM_BYTES_MASK (0x7FFF0000U) +#define PXP_LUT_ADDR_NUM_BYTES_SHIFT (16U) +#define PXP_LUT_ADDR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_ADDR_NUM_BYTES_SHIFT)) & PXP_LUT_ADDR_NUM_BYTES_MASK) + +/*! @name LUT_DATA - Lookup Table Data Register. */ +#define PXP_LUT_DATA_DATA_MASK (0xFFFFFFFFU) +#define PXP_LUT_DATA_DATA_SHIFT (0U) +#define PXP_LUT_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_DATA_DATA_SHIFT)) & PXP_LUT_DATA_DATA_MASK) + +/*! @name LUT_EXTMEM - Lookup Table External Memory Address Register. */ +#define PXP_LUT_EXTMEM_ADDR_MASK (0xFFFFFFFFU) +#define PXP_LUT_EXTMEM_ADDR_SHIFT (0U) +#define PXP_LUT_EXTMEM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_LUT_EXTMEM_ADDR_SHIFT)) & PXP_LUT_EXTMEM_ADDR_MASK) + +/*! @name CFA - Color Filter Array Register. */ +#define PXP_CFA_DATA_MASK (0xFFFFFFFFU) +#define PXP_CFA_DATA_SHIFT (0U) +#define PXP_CFA_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_CFA_DATA_SHIFT)) & PXP_CFA_DATA_MASK) + +/*! @name ALPHA_A_CTRL - PXP Alpha Engine A Control Register. */ +#define PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_MASK (0x1U) +#define PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_SHIFT (0U) +#define PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_SHIFT)) & PXP_ALPHA_A_CTRL_POTER_DUFF_ENABLE_MASK) +#define PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U) +#define PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U) +#define PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_S1_FACTOR_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_MASK (0x20U) +#define PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_SHIFT (5U) +#define PXP_ALPHA_A_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_ALPHA_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S0_COLOR_MODE_MASK (0x40U) +#define PXP_ALPHA_A_CTRL_S0_COLOR_MODE_SHIFT (6U) +#define PXP_ALPHA_A_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S0_COLOR_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U) +#define PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U) +#define PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_S0_FACTOR_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_MASK (0x1000U) +#define PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_SHIFT (12U) +#define PXP_ALPHA_A_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_ALPHA_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S1_COLOR_MODE_MASK (0x2000U) +#define PXP_ALPHA_A_CTRL_S1_COLOR_MODE_SHIFT (13U) +#define PXP_ALPHA_A_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_ALPHA_A_CTRL_S1_COLOR_MODE_MASK) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U) +#define PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_ALPHA_A_CTRL_S0_GLOBAL_ALPHA_MASK) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U) +#define PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_ALPHA_A_CTRL_S1_GLOBAL_ALPHA_MASK) + +/*! @name PS_BACKGROUND_1 - PS Background Color 1 */ +#define PXP_PS_BACKGROUND_1_COLOR_MASK (0xFFFFFFU) +#define PXP_PS_BACKGROUND_1_COLOR_SHIFT (0U) +#define PXP_PS_BACKGROUND_1_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_1_COLOR_SHIFT)) & PXP_PS_BACKGROUND_1_COLOR_MASK) + +/*! @name PS_CLRKEYLOW_1 - PS Color Key Low 1 */ +#define PXP_PS_CLRKEYLOW_1_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYLOW_1_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYLOW_1_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_1_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_1_PIXEL_MASK) + +/*! @name PS_CLRKEYHIGH_1 - PS Color Key High 1 */ +#define PXP_PS_CLRKEYHIGH_1_PIXEL_MASK (0xFFFFFFU) +#define PXP_PS_CLRKEYHIGH_1_PIXEL_SHIFT (0U) +#define PXP_PS_CLRKEYHIGH_1_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_1_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_1_PIXEL_MASK) + +/*! @name AS_CLRKEYLOW_1 - Overlay Color Key Low */ +#define PXP_AS_CLRKEYLOW_1_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYLOW_1_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYLOW_1_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_1_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_1_PIXEL_MASK) + +/*! @name AS_CLRKEYHIGH_1 - Overlay Color Key High */ +#define PXP_AS_CLRKEYHIGH_1_PIXEL_MASK (0xFFFFFFU) +#define PXP_AS_CLRKEYHIGH_1_PIXEL_SHIFT (0U) +#define PXP_AS_CLRKEYHIGH_1_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_1_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_1_PIXEL_MASK) + +/*! @name CTRL2 - Control Register 2 */ +#define PXP_CTRL2_ENABLE_MASK (0x1U) +#define PXP_CTRL2_ENABLE_SHIFT (0U) +#define PXP_CTRL2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_SHIFT)) & PXP_CTRL2_ENABLE_MASK) +#define PXP_CTRL2_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_ROTATE0_SHIFT (8U) +#define PXP_CTRL2_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ROTATE0_SHIFT)) & PXP_CTRL2_ROTATE0_MASK) +#define PXP_CTRL2_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_HFLIP0_SHIFT (10U) +#define PXP_CTRL2_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_HFLIP0_SHIFT)) & PXP_CTRL2_HFLIP0_MASK) +#define PXP_CTRL2_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_VFLIP0_SHIFT (11U) +#define PXP_CTRL2_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_VFLIP0_SHIFT)) & PXP_CTRL2_VFLIP0_MASK) +#define PXP_CTRL2_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_ROTATE1_SHIFT (12U) +#define PXP_CTRL2_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ROTATE1_SHIFT)) & PXP_CTRL2_ROTATE1_MASK) +#define PXP_CTRL2_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_HFLIP1_SHIFT (14U) +#define PXP_CTRL2_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_HFLIP1_SHIFT)) & PXP_CTRL2_HFLIP1_MASK) +#define PXP_CTRL2_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_VFLIP1_SHIFT (15U) +#define PXP_CTRL2_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_VFLIP1_SHIFT)) & PXP_CTRL2_VFLIP1_MASK) +#define PXP_CTRL2_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL2_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL2_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_ENABLE_DITHER_MASK) +#define PXP_CTRL2_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL2_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL2_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_ENABLE_WFE_B_MASK) +#define PXP_CTRL2_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL2_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_BLOCK_SIZE_MASK) +#define PXP_CTRL2_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL2_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_ENABLE_CSC2_MASK) +#define PXP_CTRL2_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL2_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL2_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_LUT_SHIFT)) & PXP_CTRL2_ENABLE_LUT_MASK) +#define PXP_CTRL2_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL2_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_ENABLE_ROTATE0_MASK) +#define PXP_CTRL2_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL2_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_ENABLE_ROTATE1_MASK) + +/*! @name CTRL2_SET - Control Register 2 */ +#define PXP_CTRL2_SET_ENABLE_MASK (0x1U) +#define PXP_CTRL2_SET_ENABLE_SHIFT (0U) +#define PXP_CTRL2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_SHIFT)) & PXP_CTRL2_SET_ENABLE_MASK) +#define PXP_CTRL2_SET_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_SET_ROTATE0_SHIFT (8U) +#define PXP_CTRL2_SET_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ROTATE0_SHIFT)) & PXP_CTRL2_SET_ROTATE0_MASK) +#define PXP_CTRL2_SET_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_SET_HFLIP0_SHIFT (10U) +#define PXP_CTRL2_SET_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_HFLIP0_SHIFT)) & PXP_CTRL2_SET_HFLIP0_MASK) +#define PXP_CTRL2_SET_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_SET_VFLIP0_SHIFT (11U) +#define PXP_CTRL2_SET_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_VFLIP0_SHIFT)) & PXP_CTRL2_SET_VFLIP0_MASK) +#define PXP_CTRL2_SET_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_SET_ROTATE1_SHIFT (12U) +#define PXP_CTRL2_SET_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ROTATE1_SHIFT)) & PXP_CTRL2_SET_ROTATE1_MASK) +#define PXP_CTRL2_SET_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_SET_HFLIP1_SHIFT (14U) +#define PXP_CTRL2_SET_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_HFLIP1_SHIFT)) & PXP_CTRL2_SET_HFLIP1_MASK) +#define PXP_CTRL2_SET_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_SET_VFLIP1_SHIFT (15U) +#define PXP_CTRL2_SET_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_VFLIP1_SHIFT)) & PXP_CTRL2_SET_VFLIP1_MASK) +#define PXP_CTRL2_SET_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL2_SET_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL2_SET_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_SET_ENABLE_DITHER_MASK) +#define PXP_CTRL2_SET_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL2_SET_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL2_SET_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_SET_ENABLE_WFE_B_MASK) +#define PXP_CTRL2_SET_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_SET_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL2_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_SET_BLOCK_SIZE_MASK) +#define PXP_CTRL2_SET_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_SET_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL2_SET_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_SET_ENABLE_CSC2_MASK) +#define PXP_CTRL2_SET_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL2_SET_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL2_SET_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_LUT_SHIFT)) & PXP_CTRL2_SET_ENABLE_LUT_MASK) +#define PXP_CTRL2_SET_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_SET_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL2_SET_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_SET_ENABLE_ROTATE0_MASK) +#define PXP_CTRL2_SET_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_SET_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL2_SET_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_SET_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_SET_ENABLE_ROTATE1_MASK) + +/*! @name CTRL2_CLR - Control Register 2 */ +#define PXP_CTRL2_CLR_ENABLE_MASK (0x1U) +#define PXP_CTRL2_CLR_ENABLE_SHIFT (0U) +#define PXP_CTRL2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_SHIFT)) & PXP_CTRL2_CLR_ENABLE_MASK) +#define PXP_CTRL2_CLR_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_CLR_ROTATE0_SHIFT (8U) +#define PXP_CTRL2_CLR_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ROTATE0_SHIFT)) & PXP_CTRL2_CLR_ROTATE0_MASK) +#define PXP_CTRL2_CLR_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_CLR_HFLIP0_SHIFT (10U) +#define PXP_CTRL2_CLR_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_HFLIP0_SHIFT)) & PXP_CTRL2_CLR_HFLIP0_MASK) +#define PXP_CTRL2_CLR_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_CLR_VFLIP0_SHIFT (11U) +#define PXP_CTRL2_CLR_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_VFLIP0_SHIFT)) & PXP_CTRL2_CLR_VFLIP0_MASK) +#define PXP_CTRL2_CLR_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_CLR_ROTATE1_SHIFT (12U) +#define PXP_CTRL2_CLR_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ROTATE1_SHIFT)) & PXP_CTRL2_CLR_ROTATE1_MASK) +#define PXP_CTRL2_CLR_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_CLR_HFLIP1_SHIFT (14U) +#define PXP_CTRL2_CLR_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_HFLIP1_SHIFT)) & PXP_CTRL2_CLR_HFLIP1_MASK) +#define PXP_CTRL2_CLR_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_CLR_VFLIP1_SHIFT (15U) +#define PXP_CTRL2_CLR_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_VFLIP1_SHIFT)) & PXP_CTRL2_CLR_VFLIP1_MASK) +#define PXP_CTRL2_CLR_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL2_CLR_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL2_CLR_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_CLR_ENABLE_DITHER_MASK) +#define PXP_CTRL2_CLR_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL2_CLR_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL2_CLR_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_CLR_ENABLE_WFE_B_MASK) +#define PXP_CTRL2_CLR_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_CLR_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL2_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_CLR_BLOCK_SIZE_MASK) +#define PXP_CTRL2_CLR_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_CLR_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL2_CLR_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_CLR_ENABLE_CSC2_MASK) +#define PXP_CTRL2_CLR_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL2_CLR_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL2_CLR_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_LUT_SHIFT)) & PXP_CTRL2_CLR_ENABLE_LUT_MASK) +#define PXP_CTRL2_CLR_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_CLR_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL2_CLR_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_CLR_ENABLE_ROTATE0_MASK) +#define PXP_CTRL2_CLR_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_CLR_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL2_CLR_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_CLR_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_CLR_ENABLE_ROTATE1_MASK) + +/*! @name CTRL2_TOG - Control Register 2 */ +#define PXP_CTRL2_TOG_ENABLE_MASK (0x1U) +#define PXP_CTRL2_TOG_ENABLE_SHIFT (0U) +#define PXP_CTRL2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_SHIFT)) & PXP_CTRL2_TOG_ENABLE_MASK) +#define PXP_CTRL2_TOG_ROTATE0_MASK (0x300U) +#define PXP_CTRL2_TOG_ROTATE0_SHIFT (8U) +#define PXP_CTRL2_TOG_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ROTATE0_SHIFT)) & PXP_CTRL2_TOG_ROTATE0_MASK) +#define PXP_CTRL2_TOG_HFLIP0_MASK (0x400U) +#define PXP_CTRL2_TOG_HFLIP0_SHIFT (10U) +#define PXP_CTRL2_TOG_HFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_HFLIP0_SHIFT)) & PXP_CTRL2_TOG_HFLIP0_MASK) +#define PXP_CTRL2_TOG_VFLIP0_MASK (0x800U) +#define PXP_CTRL2_TOG_VFLIP0_SHIFT (11U) +#define PXP_CTRL2_TOG_VFLIP0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_VFLIP0_SHIFT)) & PXP_CTRL2_TOG_VFLIP0_MASK) +#define PXP_CTRL2_TOG_ROTATE1_MASK (0x3000U) +#define PXP_CTRL2_TOG_ROTATE1_SHIFT (12U) +#define PXP_CTRL2_TOG_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ROTATE1_SHIFT)) & PXP_CTRL2_TOG_ROTATE1_MASK) +#define PXP_CTRL2_TOG_HFLIP1_MASK (0x4000U) +#define PXP_CTRL2_TOG_HFLIP1_SHIFT (14U) +#define PXP_CTRL2_TOG_HFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_HFLIP1_SHIFT)) & PXP_CTRL2_TOG_HFLIP1_MASK) +#define PXP_CTRL2_TOG_VFLIP1_MASK (0x8000U) +#define PXP_CTRL2_TOG_VFLIP1_SHIFT (15U) +#define PXP_CTRL2_TOG_VFLIP1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_VFLIP1_SHIFT)) & PXP_CTRL2_TOG_VFLIP1_MASK) +#define PXP_CTRL2_TOG_ENABLE_DITHER_MASK (0x20000U) +#define PXP_CTRL2_TOG_ENABLE_DITHER_SHIFT (17U) +#define PXP_CTRL2_TOG_ENABLE_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_DITHER_SHIFT)) & PXP_CTRL2_TOG_ENABLE_DITHER_MASK) +#define PXP_CTRL2_TOG_ENABLE_WFE_B_MASK (0x80000U) +#define PXP_CTRL2_TOG_ENABLE_WFE_B_SHIFT (19U) +#define PXP_CTRL2_TOG_ENABLE_WFE_B(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_WFE_B_SHIFT)) & PXP_CTRL2_TOG_ENABLE_WFE_B_MASK) +#define PXP_CTRL2_TOG_BLOCK_SIZE_MASK (0x800000U) +#define PXP_CTRL2_TOG_BLOCK_SIZE_SHIFT (23U) +#define PXP_CTRL2_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL2_TOG_BLOCK_SIZE_MASK) +#define PXP_CTRL2_TOG_ENABLE_CSC2_MASK (0x1000000U) +#define PXP_CTRL2_TOG_ENABLE_CSC2_SHIFT (24U) +#define PXP_CTRL2_TOG_ENABLE_CSC2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_CSC2_SHIFT)) & PXP_CTRL2_TOG_ENABLE_CSC2_MASK) +#define PXP_CTRL2_TOG_ENABLE_LUT_MASK (0x2000000U) +#define PXP_CTRL2_TOG_ENABLE_LUT_SHIFT (25U) +#define PXP_CTRL2_TOG_ENABLE_LUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_LUT_SHIFT)) & PXP_CTRL2_TOG_ENABLE_LUT_MASK) +#define PXP_CTRL2_TOG_ENABLE_ROTATE0_MASK (0x4000000U) +#define PXP_CTRL2_TOG_ENABLE_ROTATE0_SHIFT (26U) +#define PXP_CTRL2_TOG_ENABLE_ROTATE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_ROTATE0_SHIFT)) & PXP_CTRL2_TOG_ENABLE_ROTATE0_MASK) +#define PXP_CTRL2_TOG_ENABLE_ROTATE1_MASK (0x8000000U) +#define PXP_CTRL2_TOG_ENABLE_ROTATE1_SHIFT (27U) +#define PXP_CTRL2_TOG_ENABLE_ROTATE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL2_TOG_ENABLE_ROTATE1_SHIFT)) & PXP_CTRL2_TOG_ENABLE_ROTATE1_MASK) + +/*! @name POWER_REG0 - PXP Power Control Register. */ +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_MASK (0x7U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_SHIFT (0U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_SHIFT)) & PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANK0_MASK) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_MASK (0x38U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_SHIFT (3U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_SHIFT)) & PXP_POWER_REG0_LUT_LP_STATE_WAY0_BANKN_MASK) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_MASK (0x1C0U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_SHIFT (6U) +#define PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_SHIFT)) & PXP_POWER_REG0_LUT_LP_STATE_WAY1_BANKN_MASK) +#define PXP_POWER_REG0_ROT0_MEM_LP_STATE_MASK (0xE00U) +#define PXP_POWER_REG0_ROT0_MEM_LP_STATE_SHIFT (9U) +#define PXP_POWER_REG0_ROT0_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_ROT0_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG0_ROT0_MEM_LP_STATE_MASK) +#define PXP_POWER_REG0_CTRL_MASK (0xFFFFF000U) +#define PXP_POWER_REG0_CTRL_SHIFT (12U) +#define PXP_POWER_REG0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG0_CTRL_SHIFT)) & PXP_POWER_REG0_CTRL_MASK) + +/*! @name POWER_REG1 - PXP Power Control Register 1. */ +#define PXP_POWER_REG1_ROT1_MEM_LP_STATE_MASK (0x7U) +#define PXP_POWER_REG1_ROT1_MEM_LP_STATE_SHIFT (0U) +#define PXP_POWER_REG1_ROT1_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_ROT1_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_ROT1_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_MASK (0x38U) +#define PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_SHIFT (3U) +#define PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH0_LUT_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_MASK (0x1C0U) +#define PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_SHIFT (6U) +#define PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH0_ERR0_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_MASK (0xE00U) +#define PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_SHIFT (9U) +#define PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH0_ERR1_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_MASK (0x7000U) +#define PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_SHIFT (12U) +#define PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH1_LUT_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_MASK (0x38000U) +#define PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_SHIFT (15U) +#define PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_DITH2_LUT_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_ALU_A_MEM_LP_STATE_MASK (0x1C0000U) +#define PXP_POWER_REG1_ALU_A_MEM_LP_STATE_SHIFT (18U) +#define PXP_POWER_REG1_ALU_A_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_ALU_A_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_ALU_A_MEM_LP_STATE_MASK) +#define PXP_POWER_REG1_ALU_B_MEM_LP_STATE_MASK (0xE00000U) +#define PXP_POWER_REG1_ALU_B_MEM_LP_STATE_SHIFT (21U) +#define PXP_POWER_REG1_ALU_B_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_REG1_ALU_B_MEM_LP_STATE_SHIFT)) & PXP_POWER_REG1_ALU_B_MEM_LP_STATE_MASK) + +/*! @name DATA_PATH_CTRL0 - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_MUX0_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL0_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_MUX1_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL0_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX1_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_MUX3_SEL_SHIFT (6U) +#define PXP_DATA_PATH_CTRL0_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_MUX8_SEL_SHIFT (16U) +#define PXP_DATA_PATH_CTRL0_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX8_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_MUX9_SEL_SHIFT (18U) +#define PXP_DATA_PATH_CTRL0_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX9_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_MUX11_SEL_SHIFT (22U) +#define PXP_DATA_PATH_CTRL0_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX11_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_MUX12_SEL_SHIFT (24U) +#define PXP_DATA_PATH_CTRL0_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_MUX14_SEL_SHIFT (28U) +#define PXP_DATA_PATH_CTRL0_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_MUX14_SEL_MASK) + +/*! @name DATA_PATH_CTRL0_SET - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL0_SET_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX0_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL0_SET_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX1_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_SHIFT (6U) +#define PXP_DATA_PATH_CTRL0_SET_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX3_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_SHIFT (16U) +#define PXP_DATA_PATH_CTRL0_SET_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX8_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_SHIFT (18U) +#define PXP_DATA_PATH_CTRL0_SET_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX9_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_SHIFT (22U) +#define PXP_DATA_PATH_CTRL0_SET_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX11_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_SHIFT (24U) +#define PXP_DATA_PATH_CTRL0_SET_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX12_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_SHIFT (28U) +#define PXP_DATA_PATH_CTRL0_SET_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_SET_MUX14_SEL_MASK) + +/*! @name DATA_PATH_CTRL0_CLR - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX0_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX1_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_SHIFT (6U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX3_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_SHIFT (16U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX8_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_SHIFT (18U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX9_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_SHIFT (22U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX11_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_SHIFT (24U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX12_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_SHIFT (28U) +#define PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_CLR_MUX14_SEL_MASK) + +/*! @name DATA_PATH_CTRL0_TOG - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX0_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX1_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_MASK (0xC0U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_SHIFT (6U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX3_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_MASK (0x30000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_SHIFT (16U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX8_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_MASK (0xC0000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_SHIFT (18U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX9_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_MASK (0xC00000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_SHIFT (22U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX11_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_MASK (0x3000000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_SHIFT (24U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX12_SEL_MASK) +#define PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_MASK (0x30000000U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_SHIFT (28U) +#define PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_SHIFT)) & PXP_DATA_PATH_CTRL0_TOG_MUX14_SEL_MASK) + +/*! @name DATA_PATH_CTRL1 - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL1_MUX16_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL1_MUX16_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL1_MUX16_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_MUX16_SEL_MASK) +#define PXP_DATA_PATH_CTRL1_MUX17_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL1_MUX17_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL1_MUX17_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_MUX17_SEL_MASK) + +/*! @name DATA_PATH_CTRL1_SET - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL1_SET_MUX16_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_SET_MUX16_SEL_MASK) +#define PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL1_SET_MUX17_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_SET_MUX17_SEL_MASK) + +/*! @name DATA_PATH_CTRL1_CLR - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_CLR_MUX16_SEL_MASK) +#define PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_CLR_MUX17_SEL_MASK) + +/*! @name DATA_PATH_CTRL1_TOG - This register helps decide the data path gthrough the PXP. */ +#define PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_MASK (0x3U) +#define PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_SHIFT (0U) +#define PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_TOG_MUX16_SEL_MASK) +#define PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_MASK (0xCU) +#define PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_SHIFT (2U) +#define PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_SHIFT)) & PXP_DATA_PATH_CTRL1_TOG_MUX17_SEL_MASK) + +/*! @name INIT_MEM_CTRL - Initialize memory buffer control Register */ +#define PXP_INIT_MEM_CTRL_ADDR_MASK (0xFFFFU) +#define PXP_INIT_MEM_CTRL_ADDR_SHIFT (0U) +#define PXP_INIT_MEM_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_ADDR_MASK) +#define PXP_INIT_MEM_CTRL_SELECT_MASK (0x78000000U) +#define PXP_INIT_MEM_CTRL_SELECT_SHIFT (27U) +#define PXP_INIT_MEM_CTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_SELECT_MASK) +#define PXP_INIT_MEM_CTRL_START_MASK (0x80000000U) +#define PXP_INIT_MEM_CTRL_START_SHIFT (31U) +#define PXP_INIT_MEM_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_START_SHIFT)) & PXP_INIT_MEM_CTRL_START_MASK) + +/*! @name INIT_MEM_CTRL_SET - Initialize memory buffer control Register */ +#define PXP_INIT_MEM_CTRL_SET_ADDR_MASK (0xFFFFU) +#define PXP_INIT_MEM_CTRL_SET_ADDR_SHIFT (0U) +#define PXP_INIT_MEM_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SET_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_SET_ADDR_MASK) +#define PXP_INIT_MEM_CTRL_SET_SELECT_MASK (0x78000000U) +#define PXP_INIT_MEM_CTRL_SET_SELECT_SHIFT (27U) +#define PXP_INIT_MEM_CTRL_SET_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SET_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_SET_SELECT_MASK) +#define PXP_INIT_MEM_CTRL_SET_START_MASK (0x80000000U) +#define PXP_INIT_MEM_CTRL_SET_START_SHIFT (31U) +#define PXP_INIT_MEM_CTRL_SET_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_SET_START_SHIFT)) & PXP_INIT_MEM_CTRL_SET_START_MASK) + +/*! @name INIT_MEM_CTRL_CLR - Initialize memory buffer control Register */ +#define PXP_INIT_MEM_CTRL_CLR_ADDR_MASK (0xFFFFU) +#define PXP_INIT_MEM_CTRL_CLR_ADDR_SHIFT (0U) +#define PXP_INIT_MEM_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_CLR_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_CLR_ADDR_MASK) +#define PXP_INIT_MEM_CTRL_CLR_SELECT_MASK (0x78000000U) +#define PXP_INIT_MEM_CTRL_CLR_SELECT_SHIFT (27U) +#define PXP_INIT_MEM_CTRL_CLR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_CLR_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_CLR_SELECT_MASK) +#define PXP_INIT_MEM_CTRL_CLR_START_MASK (0x80000000U) +#define PXP_INIT_MEM_CTRL_CLR_START_SHIFT (31U) +#define PXP_INIT_MEM_CTRL_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_CLR_START_SHIFT)) & PXP_INIT_MEM_CTRL_CLR_START_MASK) + +/*! @name INIT_MEM_CTRL_TOG - Initialize memory buffer control Register */ +#define PXP_INIT_MEM_CTRL_TOG_ADDR_MASK (0xFFFFU) +#define PXP_INIT_MEM_CTRL_TOG_ADDR_SHIFT (0U) +#define PXP_INIT_MEM_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_TOG_ADDR_SHIFT)) & PXP_INIT_MEM_CTRL_TOG_ADDR_MASK) +#define PXP_INIT_MEM_CTRL_TOG_SELECT_MASK (0x78000000U) +#define PXP_INIT_MEM_CTRL_TOG_SELECT_SHIFT (27U) +#define PXP_INIT_MEM_CTRL_TOG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_TOG_SELECT_SHIFT)) & PXP_INIT_MEM_CTRL_TOG_SELECT_MASK) +#define PXP_INIT_MEM_CTRL_TOG_START_MASK (0x80000000U) +#define PXP_INIT_MEM_CTRL_TOG_START_SHIFT (31U) +#define PXP_INIT_MEM_CTRL_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_CTRL_TOG_START_SHIFT)) & PXP_INIT_MEM_CTRL_TOG_START_MASK) + +/*! @name INIT_MEM_DATA - Write data Register */ +#define PXP_INIT_MEM_DATA_DATA_MASK (0xFFFFFFFFU) +#define PXP_INIT_MEM_DATA_DATA_SHIFT (0U) +#define PXP_INIT_MEM_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_DATA_DATA_SHIFT)) & PXP_INIT_MEM_DATA_DATA_MASK) + +/*! @name INIT_MEM_DATA_HIGH - Write data Register */ +#define PXP_INIT_MEM_DATA_HIGH_DATA_MASK (0xFFFFFFFFU) +#define PXP_INIT_MEM_DATA_HIGH_DATA_SHIFT (0U) +#define PXP_INIT_MEM_DATA_HIGH_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_INIT_MEM_DATA_HIGH_DATA_SHIFT)) & PXP_INIT_MEM_DATA_HIGH_DATA_MASK) + +/*! @name IRQ_MASK - PXP IRQ Mask Register */ +#define PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U) +#define PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U) +#define PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U) +#define PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U) +#define PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_MASK (0x8000U) +#define PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_SHIFT (15U) +#define PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_MASK) + +/*! @name IRQ_MASK_SET - PXP IRQ Mask Register */ +#define PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U) +#define PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U) +#define PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_WFE_B_CH0_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U) +#define PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U) +#define PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_WFE_B_CH1_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_MASK (0x8000U) +#define PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_SHIFT (15U) +#define PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_SET_WFE_B_STORE_IRQ_EN_MASK) + +/*! @name IRQ_MASK_CLR - PXP IRQ Mask Register */ +#define PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U) +#define PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U) +#define PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_WFE_B_CH0_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U) +#define PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U) +#define PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_WFE_B_CH1_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_MASK (0x8000U) +#define PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_SHIFT (15U) +#define PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_CLR_WFE_B_STORE_IRQ_EN_MASK) + +/*! @name IRQ_MASK_TOG - PXP IRQ Mask Register */ +#define PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_MASK (0x400U) +#define PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_SHIFT (10U) +#define PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_WFE_B_CH0_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_MASK (0x800U) +#define PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_SHIFT (11U) +#define PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_WFE_B_CH1_STORE_IRQ_EN_MASK) +#define PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_MASK (0x8000U) +#define PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_SHIFT (15U) +#define PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_SHIFT)) & PXP_IRQ_MASK_TOG_WFE_B_STORE_IRQ_EN_MASK) + +/*! @name IRQ - PXP Interrupt Register */ +#define PXP_IRQ_WFE_B_CH0_STORE_IRQ_MASK (0x400U) +#define PXP_IRQ_WFE_B_CH0_STORE_IRQ_SHIFT (10U) +#define PXP_IRQ_WFE_B_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_WFE_B_CH0_STORE_IRQ_MASK) +#define PXP_IRQ_WFE_B_CH1_STORE_IRQ_MASK (0x800U) +#define PXP_IRQ_WFE_B_CH1_STORE_IRQ_SHIFT (11U) +#define PXP_IRQ_WFE_B_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_WFE_B_CH1_STORE_IRQ_MASK) +#define PXP_IRQ_WFE_B_STORE_IRQ_MASK (0x8000U) +#define PXP_IRQ_WFE_B_STORE_IRQ_SHIFT (15U) +#define PXP_IRQ_WFE_B_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_WFE_B_STORE_IRQ_MASK) + +/*! @name IRQ_SET - PXP Interrupt Register */ +#define PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_MASK (0x400U) +#define PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_SHIFT (10U) +#define PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_WFE_B_CH0_STORE_IRQ_MASK) +#define PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_MASK (0x800U) +#define PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_SHIFT (11U) +#define PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_WFE_B_CH1_STORE_IRQ_MASK) +#define PXP_IRQ_SET_WFE_B_STORE_IRQ_MASK (0x8000U) +#define PXP_IRQ_SET_WFE_B_STORE_IRQ_SHIFT (15U) +#define PXP_IRQ_SET_WFE_B_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_SET_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_SET_WFE_B_STORE_IRQ_MASK) + +/*! @name IRQ_CLR - PXP Interrupt Register */ +#define PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_MASK (0x400U) +#define PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_SHIFT (10U) +#define PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_WFE_B_CH0_STORE_IRQ_MASK) +#define PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_MASK (0x800U) +#define PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_SHIFT (11U) +#define PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_WFE_B_CH1_STORE_IRQ_MASK) +#define PXP_IRQ_CLR_WFE_B_STORE_IRQ_MASK (0x8000U) +#define PXP_IRQ_CLR_WFE_B_STORE_IRQ_SHIFT (15U) +#define PXP_IRQ_CLR_WFE_B_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_CLR_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_CLR_WFE_B_STORE_IRQ_MASK) + +/*! @name IRQ_TOG - PXP Interrupt Register */ +#define PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_MASK (0x400U) +#define PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_SHIFT (10U) +#define PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_WFE_B_CH0_STORE_IRQ_MASK) +#define PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_MASK (0x800U) +#define PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_SHIFT (11U) +#define PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_WFE_B_CH1_STORE_IRQ_MASK) +#define PXP_IRQ_TOG_WFE_B_STORE_IRQ_MASK (0x8000U) +#define PXP_IRQ_TOG_WFE_B_STORE_IRQ_SHIFT (15U) +#define PXP_IRQ_TOG_WFE_B_STORE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_IRQ_TOG_WFE_B_STORE_IRQ_SHIFT)) & PXP_IRQ_TOG_WFE_B_STORE_IRQ_MASK) + +/*! @name NEXT_EN - PXP NEXT Buffer Enable select Register */ +#define PXP_NEXT_EN_LEGACY_MASK (0x1U) +#define PXP_NEXT_EN_LEGACY_SHIFT (0U) +#define PXP_NEXT_EN_LEGACY(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_LEGACY_SHIFT)) & PXP_NEXT_EN_LEGACY_MASK) +#define PXP_NEXT_EN_WFEB_MASK (0x2U) +#define PXP_NEXT_EN_WFEB_SHIFT (1U) +#define PXP_NEXT_EN_WFEB(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_WFEB_SHIFT)) & PXP_NEXT_EN_WFEB_MASK) + +/*! @name NEXT_EN_SET - PXP NEXT Buffer Enable select Register */ +#define PXP_NEXT_EN_SET_LEGACY_MASK (0x1U) +#define PXP_NEXT_EN_SET_LEGACY_SHIFT (0U) +#define PXP_NEXT_EN_SET_LEGACY(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_SET_LEGACY_SHIFT)) & PXP_NEXT_EN_SET_LEGACY_MASK) +#define PXP_NEXT_EN_SET_WFEB_MASK (0x2U) +#define PXP_NEXT_EN_SET_WFEB_SHIFT (1U) +#define PXP_NEXT_EN_SET_WFEB(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_SET_WFEB_SHIFT)) & PXP_NEXT_EN_SET_WFEB_MASK) + +/*! @name NEXT_EN_CLR - PXP NEXT Buffer Enable select Register */ +#define PXP_NEXT_EN_CLR_LEGACY_MASK (0x1U) +#define PXP_NEXT_EN_CLR_LEGACY_SHIFT (0U) +#define PXP_NEXT_EN_CLR_LEGACY(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_CLR_LEGACY_SHIFT)) & PXP_NEXT_EN_CLR_LEGACY_MASK) +#define PXP_NEXT_EN_CLR_WFEB_MASK (0x2U) +#define PXP_NEXT_EN_CLR_WFEB_SHIFT (1U) +#define PXP_NEXT_EN_CLR_WFEB(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_CLR_WFEB_SHIFT)) & PXP_NEXT_EN_CLR_WFEB_MASK) + +/*! @name NEXT_EN_TOG - PXP NEXT Buffer Enable select Register */ +#define PXP_NEXT_EN_TOG_LEGACY_MASK (0x1U) +#define PXP_NEXT_EN_TOG_LEGACY_SHIFT (0U) +#define PXP_NEXT_EN_TOG_LEGACY(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_TOG_LEGACY_SHIFT)) & PXP_NEXT_EN_TOG_LEGACY_MASK) +#define PXP_NEXT_EN_TOG_WFEB_MASK (0x2U) +#define PXP_NEXT_EN_TOG_WFEB_SHIFT (1U) +#define PXP_NEXT_EN_TOG_WFEB(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_EN_TOG_WFEB_SHIFT)) & PXP_NEXT_EN_TOG_WFEB_MASK) + +/*! @name NEXT - Next Frame Pointer */ +#define PXP_NEXT_ENABLED_MASK (0x1U) +#define PXP_NEXT_ENABLED_SHIFT (0U) +#define PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK) +#define PXP_NEXT_POINTER_MASK (0xFFFFFFFCU) +#define PXP_NEXT_POINTER_SHIFT (2U) +#define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK) + +/*! @name DEBUGCTRL - Debug Control Register */ +#define PXP_DEBUGCTRL_SELECT_MASK (0xFFU) +#define PXP_DEBUGCTRL_SELECT_SHIFT (0U) +#define PXP_DEBUGCTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DEBUGCTRL_SELECT_SHIFT)) & PXP_DEBUGCTRL_SELECT_MASK) +#define PXP_DEBUGCTRL_LUT_CLR_STAT_CNT_MASK (0xF00U) +#define PXP_DEBUGCTRL_LUT_CLR_STAT_CNT_SHIFT (8U) +#define PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DEBUGCTRL_LUT_CLR_STAT_CNT_SHIFT)) & PXP_DEBUGCTRL_LUT_CLR_STAT_CNT_MASK) + +/*! @name DEBUG - Debug Register */ +#define PXP_DEBUG_DATA_MASK (0xFFFFFFFFU) +#define PXP_DEBUG_DATA_SHIFT (0U) +#define PXP_DEBUG_DATA(x) (((uint32_t)(((uint32_t)(x)) << PXP_DEBUG_DATA_SHIFT)) & PXP_DEBUG_DATA_MASK) + +/*! @name VERSION - Version Register */ +#define PXP_VERSION_STEP_MASK (0xFFFFU) +#define PXP_VERSION_STEP_SHIFT (0U) +#define PXP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << PXP_VERSION_STEP_SHIFT)) & PXP_VERSION_STEP_MASK) +#define PXP_VERSION_MINOR_MASK (0xFF0000U) +#define PXP_VERSION_MINOR_SHIFT (16U) +#define PXP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_VERSION_MINOR_SHIFT)) & PXP_VERSION_MINOR_MASK) +#define PXP_VERSION_MAJOR_MASK (0xFF000000U) +#define PXP_VERSION_MAJOR_SHIFT (24U) +#define PXP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_VERSION_MAJOR_SHIFT)) & PXP_VERSION_MAJOR_MASK) + +/*! @name DITHER_STORE_SIZE_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_MASK (0xFFFFU) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_SHIFT (0U) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_SHIFT)) & PXP_DITHER_STORE_SIZE_CH0_OUT_WIDTH_MASK) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_MASK (0xFFFF0000U) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT (16U) +#define PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT)) & PXP_DITHER_STORE_SIZE_CH0_OUT_HEIGHT_MASK) + +/*! @name WFB_FETCH_CTRL - Fetch engine Control for WFE B Register */ +#define PXP_WFB_FETCH_CTRL_BF1_EN_MASK (0x1U) +#define PXP_WFB_FETCH_CTRL_BF1_EN_SHIFT (0U) +#define PXP_WFB_FETCH_CTRL_BF1_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_EN_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_SRAM_IF_MASK (0x2U) +#define PXP_WFB_FETCH_CTRL_BF1_SRAM_IF_SHIFT (1U) +#define PXP_WFB_FETCH_CTRL_BF1_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_HSK_MODE_MASK (0x4U) +#define PXP_WFB_FETCH_CTRL_BF1_HSK_MODE_SHIFT (2U) +#define PXP_WFB_FETCH_CTRL_BF1_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE_MASK (0x8U) +#define PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE_SHIFT (3U) +#define PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_BURST_LEN_MASK (0x10U) +#define PXP_WFB_FETCH_CTRL_BF1_BURST_LEN_SHIFT (4U) +#define PXP_WFB_FETCH_CTRL_BF1_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE_MASK (0x20U) +#define PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE_SHIFT (5U) +#define PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_EN_MASK (0x100U) +#define PXP_WFB_FETCH_CTRL_BF2_EN_SHIFT (8U) +#define PXP_WFB_FETCH_CTRL_BF2_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_EN_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_SRAM_IF_MASK (0x200U) +#define PXP_WFB_FETCH_CTRL_BF2_SRAM_IF_SHIFT (9U) +#define PXP_WFB_FETCH_CTRL_BF2_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_HSK_MODE_MASK (0x400U) +#define PXP_WFB_FETCH_CTRL_BF2_HSK_MODE_SHIFT (10U) +#define PXP_WFB_FETCH_CTRL_BF2_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE_MASK (0x800U) +#define PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE_SHIFT (11U) +#define PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_BURST_LEN_MASK (0x1000U) +#define PXP_WFB_FETCH_CTRL_BF2_BURST_LEN_SHIFT (12U) +#define PXP_WFB_FETCH_CTRL_BF2_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE_MASK (0x2000U) +#define PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE_SHIFT (13U) +#define PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_BYTES_PP_MASK (0x30000U) +#define PXP_WFB_FETCH_CTRL_BF1_BYTES_PP_SHIFT (16U) +#define PXP_WFB_FETCH_CTRL_BF1_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_BF1_LINE_MODE_MASK (0xC0000U) +#define PXP_WFB_FETCH_CTRL_BF1_LINE_MODE_SHIFT (18U) +#define PXP_WFB_FETCH_CTRL_BF1_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF1_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF1_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_BYTES_PP_MASK (0x300000U) +#define PXP_WFB_FETCH_CTRL_BF2_BYTES_PP_SHIFT (20U) +#define PXP_WFB_FETCH_CTRL_BF2_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_BF2_LINE_MODE_MASK (0xC00000U) +#define PXP_WFB_FETCH_CTRL_BF2_LINE_MODE_SHIFT (22U) +#define PXP_WFB_FETCH_CTRL_BF2_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BF2_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_BF2_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_MASK (0x10000000U) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_SHIFT (28U) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_MASK (0x20000000U) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_SHIFT (29U) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN_MASK (0x40000000U) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN_SHIFT (30U) +#define PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_BUF1_DONE_IRQ_EN_MASK) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN_MASK (0x80000000U) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN_SHIFT (31U) +#define PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_BUF2_DONE_IRQ_EN_MASK) + +/*! @name WFB_FETCH_CTRL_SET - Fetch engine Control for WFE B Register */ +#define PXP_WFB_FETCH_CTRL_SET_BF1_EN_MASK (0x1U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_EN_SHIFT (0U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_EN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF_MASK (0x2U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF_SHIFT (1U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE_MASK (0x4U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE_SHIFT (2U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE_MASK (0x8U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE_SHIFT (3U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN_MASK (0x10U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN_SHIFT (4U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE_MASK (0x20U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE_SHIFT (5U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_EN_MASK (0x100U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_EN_SHIFT (8U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_EN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF_MASK (0x200U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF_SHIFT (9U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE_MASK (0x400U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE_SHIFT (10U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE_MASK (0x800U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE_SHIFT (11U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN_MASK (0x1000U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN_SHIFT (12U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE_MASK (0x2000U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE_SHIFT (13U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP_MASK (0x30000U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP_SHIFT (16U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE_MASK (0xC0000U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE_SHIFT (18U) +#define PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF1_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP_MASK (0x300000U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP_SHIFT (20U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE_MASK (0xC00000U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE_SHIFT (22U) +#define PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BF2_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_MASK (0x10000000U) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_SHIFT (28U) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_MASK (0x20000000U) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_SHIFT (29U) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_MASK (0x40000000U) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_SHIFT (30U) +#define PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BUF1_DONE_IRQ_EN_MASK) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_MASK (0x80000000U) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_SHIFT (31U) +#define PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_SET_BUF2_DONE_IRQ_EN_MASK) + +/*! @name WFB_FETCH_CTRL_CLR - Fetch engine Control for WFE B Register */ +#define PXP_WFB_FETCH_CTRL_CLR_BF1_EN_MASK (0x1U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_EN_SHIFT (0U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_EN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF_MASK (0x2U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF_SHIFT (1U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE_MASK (0x4U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE_SHIFT (2U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE_MASK (0x8U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE_SHIFT (3U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN_MASK (0x10U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN_SHIFT (4U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE_MASK (0x20U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE_SHIFT (5U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_EN_MASK (0x100U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_EN_SHIFT (8U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_EN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF_MASK (0x200U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF_SHIFT (9U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE_MASK (0x400U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE_SHIFT (10U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE_MASK (0x800U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE_SHIFT (11U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN_MASK (0x1000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN_SHIFT (12U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE_MASK (0x2000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE_SHIFT (13U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP_MASK (0x30000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP_SHIFT (16U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE_MASK (0xC0000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE_SHIFT (18U) +#define PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF1_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP_MASK (0x300000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP_SHIFT (20U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE_MASK (0xC00000U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE_SHIFT (22U) +#define PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BF2_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_MASK (0x10000000U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_SHIFT (28U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_MASK (0x20000000U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_SHIFT (29U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_MASK (0x40000000U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_SHIFT (30U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BUF1_DONE_IRQ_EN_MASK) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_MASK (0x80000000U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_SHIFT (31U) +#define PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_CLR_BUF2_DONE_IRQ_EN_MASK) + +/*! @name WFB_FETCH_CTRL_TOG - Fetch engine Control for WFE B Register */ +#define PXP_WFB_FETCH_CTRL_TOG_BF1_EN_MASK (0x1U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_EN_SHIFT (0U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_EN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF_MASK (0x2U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF_SHIFT (1U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE_MASK (0x4U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE_SHIFT (2U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE_MASK (0x8U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE_SHIFT (3U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN_MASK (0x10U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN_SHIFT (4U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE_MASK (0x20U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE_SHIFT (5U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_EN_MASK (0x100U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_EN_SHIFT (8U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_EN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF_MASK (0x200U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF_SHIFT (9U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_SRAM_IF_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE_MASK (0x400U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE_SHIFT (10U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_HSK_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE_MASK (0x800U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE_SHIFT (11U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_BYPASS_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN_MASK (0x1000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN_SHIFT (12U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_BURST_LEN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE_MASK (0x2000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE_SHIFT (13U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_BORDER_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP_MASK (0x30000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP_SHIFT (16U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE_MASK (0xC0000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE_SHIFT (18U) +#define PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF1_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP_MASK (0x300000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP_SHIFT (20U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_BYTES_PP_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE_MASK (0xC00000U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE_SHIFT (22U) +#define PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BF2_LINE_MODE_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_MASK (0x10000000U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_SHIFT (28U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_MASK (0x20000000U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_SHIFT (29U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_MASK (0x40000000U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_SHIFT (30U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BUF1_DONE_IRQ_EN_MASK) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_MASK (0x80000000U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_SHIFT (31U) +#define PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_SHIFT)) & PXP_WFB_FETCH_CTRL_TOG_BUF2_DONE_IRQ_EN_MASK) + +/*! @name WFB_FETCH_BUF1_ADDR - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR_SHIFT (0U) +#define PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR_SHIFT)) & PXP_WFB_FETCH_BUF1_ADDR_BUF_ADDR_MASK) + +/*! @name WFB_FETCH_BUF1_PITCH - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF1_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_WFB_FETCH_BUF1_PITCH_PITCH_SHIFT (0U) +#define PXP_WFB_FETCH_BUF1_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_PITCH_PITCH_SHIFT)) & PXP_WFB_FETCH_BUF1_PITCH_PITCH_MASK) + +/*! @name WFB_FETCH_BUF1_SIZE - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH_MASK (0xFFFFU) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH_SHIFT (0U) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH_SHIFT)) & PXP_WFB_FETCH_BUF1_SIZE_BUF_WIDTH_MASK) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT_MASK (0xFFFF0000U) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT_SHIFT (16U) +#define PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT_SHIFT)) & PXP_WFB_FETCH_BUF1_SIZE_BUF_HEIGHT_MASK) + +/*! @name WFB_FETCH_BUF2_ADDR - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR_SHIFT (0U) +#define PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR_SHIFT)) & PXP_WFB_FETCH_BUF2_ADDR_BUF_ADDR_MASK) + +/*! @name WFB_FETCH_BUF2_PITCH - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF2_PITCH_PITCH_MASK (0xFFFFU) +#define PXP_WFB_FETCH_BUF2_PITCH_PITCH_SHIFT (0U) +#define PXP_WFB_FETCH_BUF2_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_PITCH_PITCH_SHIFT)) & PXP_WFB_FETCH_BUF2_PITCH_PITCH_MASK) + +/*! @name WFB_FETCH_BUF2_SIZE - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH_MASK (0xFFFFU) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH_SHIFT (0U) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH_SHIFT)) & PXP_WFB_FETCH_BUF2_SIZE_BUF_WIDTH_MASK) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT_MASK (0xFFFF0000U) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT_SHIFT (16U) +#define PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT_SHIFT)) & PXP_WFB_FETCH_BUF2_SIZE_BUF_HEIGHT_MASK) + +/*! @name WFB_ARRAY_PIXEL0_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL0_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL1_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL1_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL2_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL2_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL3_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL3_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL4_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL4_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL5_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL5_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL6_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL6_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_PIXEL7_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_PIXEL7_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG0_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG0_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG0_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG0_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG0_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG0_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG0_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG1_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG1_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG1_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG1_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG1_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG1_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG1_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG2_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG2_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG2_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG2_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG2_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG2_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG2_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG3_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG3_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG3_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG3_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG3_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG3_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG3_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG4_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG4_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG4_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG4_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG4_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG4_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG4_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG5_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG5_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG5_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG5_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG5_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG5_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG5_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG6_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG6_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG6_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG6_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG6_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG6_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG6_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG7_MASK - This register defines the control bits for the pxp wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG7_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG7_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG7_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG7_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG7_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG7_MASK_BUF_SEL_MASK) + +/*! @name WFB_FETCH_BUF1_CORD - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_FETCH_BUF1_CORD_XCORD_MASK (0x3FFFU) +#define PXP_WFB_FETCH_BUF1_CORD_XCORD_SHIFT (0U) +#define PXP_WFB_FETCH_BUF1_CORD_XCORD(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_CORD_XCORD_SHIFT)) & PXP_WFB_FETCH_BUF1_CORD_XCORD_MASK) +#define PXP_WFB_FETCH_BUF1_CORD_YCORD_MASK (0x3FFF0000U) +#define PXP_WFB_FETCH_BUF1_CORD_YCORD_SHIFT (16U) +#define PXP_WFB_FETCH_BUF1_CORD_YCORD(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF1_CORD_YCORD_SHIFT)) & PXP_WFB_FETCH_BUF1_CORD_YCORD_MASK) + +/*! @name WFB_FETCH_BUF2_CORD - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_FETCH_BUF2_CORD_XCORD_MASK (0x3FFFU) +#define PXP_WFB_FETCH_BUF2_CORD_XCORD_SHIFT (0U) +#define PXP_WFB_FETCH_BUF2_CORD_XCORD(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_CORD_XCORD_SHIFT)) & PXP_WFB_FETCH_BUF2_CORD_XCORD_MASK) +#define PXP_WFB_FETCH_BUF2_CORD_YCORD_MASK (0x3FFF0000U) +#define PXP_WFB_FETCH_BUF2_CORD_YCORD_SHIFT (16U) +#define PXP_WFB_FETCH_BUF2_CORD_YCORD(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_FETCH_BUF2_CORD_YCORD_SHIFT)) & PXP_WFB_FETCH_BUF2_CORD_YCORD_MASK) + +/*! @name WFB_ARRAY_FLAG8_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG8_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG8_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG8_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG8_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG8_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG8_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG9_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG9_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG9_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG9_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG9_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG9_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG9_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG10_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG10_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG10_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG10_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG10_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG10_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG10_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG11_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG11_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG11_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG11_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG11_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG11_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG11_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG12_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG12_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG12_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG12_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG12_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG12_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG12_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG13_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG13_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG13_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG13_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG13_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG13_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG13_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG14_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG14_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG14_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG14_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG14_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG14_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG14_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_FLAG15_MASK - This register defines the control bits for the pxp wfa fetch sub-block. */ +#define PXP_WFB_ARRAY_FLAG15_MASK_L_OFS_MASK (0x1FU) +#define PXP_WFB_ARRAY_FLAG15_MASK_L_OFS_SHIFT (0U) +#define PXP_WFB_ARRAY_FLAG15_MASK_L_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_L_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_L_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_H_OFS_MASK (0x1F00U) +#define PXP_WFB_ARRAY_FLAG15_MASK_H_OFS_SHIFT (8U) +#define PXP_WFB_ARRAY_FLAG15_MASK_H_OFS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_H_OFS_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_H_OFS_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X_MASK (0x30000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X_SHIFT (16U) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_X_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y_MASK (0x300000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y_SHIFT (20U) +#define PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_OFFSET_Y_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X_MASK (0x1000000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X_SHIFT (24U) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_SIGN_X_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y_MASK (0x2000000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y_SHIFT (25U) +#define PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_SIGN_Y_MASK) +#define PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL_MASK (0x30000000U) +#define PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL_SHIFT (28U) +#define PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL_SHIFT)) & PXP_WFB_ARRAY_FLAG15_MASK_BUF_SEL_MASK) + +/*! @name WFB_ARRAY_REG0 - This register defines software define pixels for wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_REG0_SW_PIXLE0_MASK (0xFFU) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE0_SHIFT (0U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG0_SW_PIXLE0_SHIFT)) & PXP_WFB_ARRAY_REG0_SW_PIXLE0_MASK) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE1_MASK (0xFF00U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE1_SHIFT (8U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG0_SW_PIXLE1_SHIFT)) & PXP_WFB_ARRAY_REG0_SW_PIXLE1_MASK) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE2_MASK (0xFF0000U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE2_SHIFT (16U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG0_SW_PIXLE2_SHIFT)) & PXP_WFB_ARRAY_REG0_SW_PIXLE2_MASK) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE3_MASK (0xFF000000U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE3_SHIFT (24U) +#define PXP_WFB_ARRAY_REG0_SW_PIXLE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG0_SW_PIXLE3_SHIFT)) & PXP_WFB_ARRAY_REG0_SW_PIXLE3_MASK) + +/*! @name WFB_ARRAY_REG1 - This register defines software define pixels for wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_REG1_SW_PIXLE4_MASK (0xFFU) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE4_SHIFT (0U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG1_SW_PIXLE4_SHIFT)) & PXP_WFB_ARRAY_REG1_SW_PIXLE4_MASK) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE5_MASK (0xFF00U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE5_SHIFT (8U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG1_SW_PIXLE5_SHIFT)) & PXP_WFB_ARRAY_REG1_SW_PIXLE5_MASK) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE6_MASK (0xFF0000U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE6_SHIFT (16U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG1_SW_PIXLE6_SHIFT)) & PXP_WFB_ARRAY_REG1_SW_PIXLE6_MASK) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE7_MASK (0xFF000000U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE7_SHIFT (24U) +#define PXP_WFB_ARRAY_REG1_SW_PIXLE7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG1_SW_PIXLE7_SHIFT)) & PXP_WFB_ARRAY_REG1_SW_PIXLE7_MASK) + +/*! @name WFB_ARRAY_REG2 - This register defines software define pixels for wfb fetch sub-block. */ +#define PXP_WFB_ARRAY_REG2_SW_FLAG0_MASK (0x1U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG0_SHIFT (0U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG0_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG0_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG1_MASK (0x2U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG1_SHIFT (1U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG1_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG1_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG2_MASK (0x4U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG2_SHIFT (2U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG2_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG2_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG3_MASK (0x8U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG3_SHIFT (3U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG3_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG3_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG4_MASK (0x10U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG4_SHIFT (4U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG4_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG4_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG5_MASK (0x20U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG5_SHIFT (5U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG5_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG5_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG6_MASK (0x40U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG6_SHIFT (6U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG6_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG6_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG7_MASK (0x80U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG7_SHIFT (7U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG7_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG7_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG8_MASK (0x100U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG8_SHIFT (8U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG8_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG8_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG9_MASK (0x200U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG9_SHIFT (9U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG9_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG9_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG10_MASK (0x400U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG10_SHIFT (10U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG10_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG10_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG11_MASK (0x800U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG11_SHIFT (11U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG11_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG11_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG12_MASK (0x1000U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG12_SHIFT (12U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG12_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG12_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG13_MASK (0x2000U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG13_SHIFT (13U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG13_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG13_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG14_MASK (0x4000U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG14_SHIFT (14U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG14_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG14_MASK) +#define PXP_WFB_ARRAY_REG2_SW_FLAG15_MASK (0x8000U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG15_SHIFT (15U) +#define PXP_WFB_ARRAY_REG2_SW_FLAG15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFB_ARRAY_REG2_SW_FLAG15_SHIFT)) & PXP_WFB_ARRAY_REG2_SW_FLAG15_MASK) + +/*! @name WFE_B_STORE_CTRL_CH0 - Store engine Control Channel 0 Register */ +#define PXP_WFE_B_STORE_CTRL_CH0_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH0_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH0_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_MASK (0x800U) +#define PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT (11U) +#define PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_FILL_DATA_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_WR_NUM_BYTES_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK (0x1000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT (24U) +#define PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_COMBINE_2CHANNEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_MASK (0x80000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_SHIFT (31U) +#define PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_ARBIT_EN_MASK) + +/*! @name WFE_B_STORE_CTRL_CH0_SET - Store engine Control Channel 0 Register */ +#define PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_MASK (0x800U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_SHIFT (11U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_FILL_DATA_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_WR_NUM_BYTES_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK (0x1000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_SHIFT (24U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_MASK (0x80000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_SHIFT (31U) +#define PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_SET_ARBIT_EN_MASK) + +/*! @name WFE_B_STORE_CTRL_CH0_CLR - Store engine Control Channel 0 Register */ +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_MASK (0x800U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_SHIFT (11U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_FILL_DATA_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_WR_NUM_BYTES_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_MASK (0x1000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_SHIFT (24U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_COMBINE_2CHANNEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_MASK (0x80000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_SHIFT (31U) +#define PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_CLR_ARBIT_EN_MASK) + +/*! @name WFE_B_STORE_CTRL_CH0_TOG - Store engine Control Channel 0 Register */ +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_MASK (0x800U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_SHIFT (11U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_FILL_DATA_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_WR_NUM_BYTES_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_MASK (0x1000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_SHIFT (24U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_COMBINE_2CHANNEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_MASK (0x80000000U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_SHIFT (31U) +#define PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH0_TOG_ARBIT_EN_MASK) + +/*! @name WFE_B_STORE_CTRL_CH1 - Store engine Control Channel 1 Register */ +#define PXP_WFE_B_STORE_CTRL_CH1_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH1_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH1_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_WR_NUM_BYTES_MASK) + +/*! @name WFE_B_STORE_CTRL_CH1_SET - Store engine Control Channel 1 Register */ +#define PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_SET_WR_NUM_BYTES_MASK) + +/*! @name WFE_B_STORE_CTRL_CH1_CLR - Store engine Control Channel 1 Register */ +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_CLR_WR_NUM_BYTES_MASK) + +/*! @name WFE_B_STORE_CTRL_CH1_TOG - Store engine Control Channel 1 Register */ +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_MASK (0x1U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_SHIFT (0U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_CH_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_MASK (0x2U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_SHIFT (1U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_MASK (0x4U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_SHIFT (2U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_BLOCK_16_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_MASK (0x8U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT (3U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_HANDSHAKE_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_MASK (0x60U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_SHIFT (5U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_ARRAY_LINE_NUM_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_MASK (0x100U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_SHIFT (8U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_BYPASS_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_MASK (0x200U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_SHIFT (9U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_STORE_MEMORY_EN_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_MASK (0x400U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_SHIFT (10U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_PACK_IN_SEL_MASK) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_MASK (0x30000U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_SHIFT (16U) +#define PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_SHIFT)) & PXP_WFE_B_STORE_CTRL_CH1_TOG_WR_NUM_BYTES_MASK) + +/*! @name WFE_B_STORE_STATUS_CH0 - Store engine status Channel 0 Register */ +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT (0U) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_X_MASK) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT (16U) +#define PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH0_STORE_BLOCK_Y_MASK) + +/*! @name WFE_B_STORE_STATUS_CH1 - Store engine status Channel 1 Register */ +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT (0U) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_X_MASK) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT (16U) +#define PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_SHIFT)) & PXP_WFE_B_STORE_STATUS_CH1_STORE_BLOCK_Y_MASK) + +/*! @name WFE_B_STORE_SIZE_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_SHIFT (0U) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH0_OUT_WIDTH_MASK) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT (16U) +#define PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH0_OUT_HEIGHT_MASK) + +/*! @name WFE_B_STORE_SIZE_CH1 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_SHIFT (0U) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH1_OUT_WIDTH_MASK) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT (16U) +#define PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_SHIFT)) & PXP_WFE_B_STORE_SIZE_CH1_OUT_HEIGHT_MASK) + +/*! @name WFE_B_STORE_PITCH - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_MASK (0xFFFFU) +#define PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_SHIFT (0U) +#define PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_SHIFT)) & PXP_WFE_B_STORE_PITCH_CH0_OUT_PITCH_MASK) +#define PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_MASK (0xFFFF0000U) +#define PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_SHIFT (16U) +#define PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_SHIFT)) & PXP_WFE_B_STORE_PITCH_CH1_OUT_PITCH_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_OUT_YUV422_2P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK (0x80U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT (7U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SHIFT_BYPASS_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH0_SET - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_OUT_YUV422_2P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK (0x80U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT (7U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_SET_SHIFT_BYPASS_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH0_CLR - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_OUT_YUV422_2P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK (0x80U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT (7U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_CLR_SHIFT_BYPASS_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH0_TOG - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_OUT_YUV422_2P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK (0x80U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT (7U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH0_TOG_SHIFT_BYPASS_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH1 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_OUT_YUV422_2P_EN_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH1_SET - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_SET_OUT_YUV422_2P_EN_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH1_CLR - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_CLR_OUT_YUV422_2P_EN_MASK) + +/*! @name WFE_B_STORE_SHIFT_CTRL_CH1_TOG - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_MASK (0xCU) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_SHIFT (2U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUTPUT_ACTIVE_BPP_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_MASK (0x10U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_SHIFT (4U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_1P_EN_MASK) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_MASK (0x20U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_SHIFT (5U) +#define PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_SHIFT)) & PXP_WFE_B_STORE_SHIFT_CTRL_CH1_TOG_OUT_YUV422_2P_EN_MASK) + +/*! @name WFE_B_STORE_ADDR_0_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT (0U) +#define PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_SHIFT)) & PXP_WFE_B_STORE_ADDR_0_CH0_OUT_BASE_ADDR0_MASK) + +/*! @name WFE_B_STORE_ADDR_1_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT (0U) +#define PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_SHIFT)) & PXP_WFE_B_STORE_ADDR_1_CH0_OUT_BASE_ADDR1_MASK) + +/*! @name WFE_B_STORE_FILL_DATA_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_SHIFT)) & PXP_WFE_B_STORE_FILL_DATA_CH0_FILL_DATA_CH0_MASK) + +/*! @name WFE_B_STORE_ADDR_0_CH1 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT (0U) +#define PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_SHIFT)) & PXP_WFE_B_STORE_ADDR_0_CH1_OUT_BASE_ADDR0_MASK) + +/*! @name WFE_B_STORE_ADDR_1_CH1 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT (0U) +#define PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_SHIFT)) & PXP_WFE_B_STORE_ADDR_1_CH1_OUT_BASE_ADDR1_MASK) + +/*! @name WFE_B_STORE_D_MASK0_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK0_H_CH0_D_MASK0_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK0_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK0_L_CH0_D_MASK0_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK1_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK1_H_CH0_D_MASK1_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK1_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK1_L_CH0_D_MASK1_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK2_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK2_H_CH0_D_MASK2_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK2_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK2_L_CH0_D_MASK2_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK3_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK3_H_CH0_D_MASK3_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK3_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK3_L_CH0_D_MASK3_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK4_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK4_H_CH0_D_MASK4_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK4_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK4_L_CH0_D_MASK4_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK5_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK5_H_CH0_D_MASK5_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK5_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK5_L_CH0_D_MASK5_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK6_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK6_H_CH0_D_MASK6_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK6_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK6_L_CH0_D_MASK6_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK7_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK7_H_CH0_D_MASK7_H_CH0_MASK) + +/*! @name WFE_B_STORE_D_MASK7_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK (0xFFFFFFFFU) +#define PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_SHIFT)) & PXP_WFE_B_STORE_D_MASK7_L_CH0_D_MASK7_L_CH0_MASK) + +/*! @name WFE_B_STORE_D_SHIFT_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK (0x3FU) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT (0U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH0_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK (0x80U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT (7U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG0_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK (0x3F00U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT (8U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH1_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK (0x8000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT (15U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG1_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK (0x3F0000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT (16U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH2_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK (0x800000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT (23U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG2_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK (0x3F000000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT (24U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_WIDTH3_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK (0x80000000U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT (31U) +#define PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_L_CH0_D_SHIFT_FLAG3_MASK) + +/*! @name WFE_B_STORE_D_SHIFT_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK (0x3FU) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT (0U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH4_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK (0x80U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT (7U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG4_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK (0x3F00U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT (8U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH5_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK (0x8000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT (15U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG5_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK (0x3F0000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT (16U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH6_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK (0x800000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT (23U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG6_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK (0x3F000000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT (24U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_WIDTH7_MASK) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK (0x80000000U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT (31U) +#define PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_SHIFT)) & PXP_WFE_B_STORE_D_SHIFT_H_CH0_D_SHIFT_FLAG7_MASK) + +/*! @name WFE_B_STORE_F_SHIFT_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK (0x3FU) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT (0U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH0_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK (0x40U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT (6U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG0_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK (0x3F00U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT (8U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH1_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK (0x4000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT (14U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG1_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK (0x3F0000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT (16U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH2_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK (0x400000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT (22U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG2_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK (0x3F000000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT (24U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_WIDTH3_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK (0x40000000U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT (30U) +#define PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_L_CH0_F_SHIFT_FLAG3_MASK) + +/*! @name WFE_B_STORE_F_SHIFT_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK (0x3FU) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT (0U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH4_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK (0x40U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT (6U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG4_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK (0x3F00U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT (8U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH5_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK (0x4000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT (14U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG5_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK (0x3F0000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT (16U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH6_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK (0x400000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT (22U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG6_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK (0x3F000000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT (24U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_WIDTH7_MASK) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK (0x40000000U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT (30U) +#define PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_SHIFT)) & PXP_WFE_B_STORE_F_SHIFT_H_CH0_F_SHIFT_FLAG7_MASK) + +/*! @name WFE_B_STORE_F_MASK_L_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_MASK (0xFFU) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_SHIFT (0U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK0_MASK) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_MASK (0xFF00U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_SHIFT (8U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK1_MASK) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_MASK (0xFF0000U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_SHIFT (16U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK2_MASK) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_MASK (0xFF000000U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_SHIFT (24U) +#define PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_SHIFT)) & PXP_WFE_B_STORE_F_MASK_L_CH0_F_MASK3_MASK) + +/*! @name WFE_B_STORE_F_MASK_H_CH0 - This register defines the control bits for the pxp store_engine sub-block. */ +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_MASK (0xFFU) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_SHIFT (0U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK4_MASK) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_MASK (0xFF00U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_SHIFT (8U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK5_MASK) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_MASK (0xFF0000U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_SHIFT (16U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK6_MASK) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_MASK (0xFF000000U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_SHIFT (24U) +#define PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_SHIFT)) & PXP_WFE_B_STORE_F_MASK_H_CH0_F_MASK7_MASK) + +/*! @name FETCH_WFE_B_DEBUG - This register holds the debug bits for the prefetch engine for WFE B. */ +#define PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_MASK (0xFFFFFFU) +#define PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_SHIFT (0U) +#define PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_SHIFT)) & PXP_FETCH_WFE_B_DEBUG_DEBUG_VALUE_MASK) +#define PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_MASK (0xF000000U) +#define PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_SHIFT (24U) +#define PXP_FETCH_WFE_B_DEBUG_ITEM_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_SHIFT)) & PXP_FETCH_WFE_B_DEBUG_ITEM_SEL_MASK) +#define PXP_FETCH_WFE_B_DEBUG_BUF_SEL_MASK (0x10000000U) +#define PXP_FETCH_WFE_B_DEBUG_BUF_SEL_SHIFT (28U) +#define PXP_FETCH_WFE_B_DEBUG_BUF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_FETCH_WFE_B_DEBUG_BUF_SEL_SHIFT)) & PXP_FETCH_WFE_B_DEBUG_BUF_SEL_MASK) + +/*! @name DITHER_CTRL - Dither Control Register 0 */ +#define PXP_DITHER_CTRL_ENABLE0_MASK (0x1U) +#define PXP_DITHER_CTRL_ENABLE0_SHIFT (0U) +#define PXP_DITHER_CTRL_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_ENABLE0_MASK) +#define PXP_DITHER_CTRL_ENABLE1_MASK (0x2U) +#define PXP_DITHER_CTRL_ENABLE1_SHIFT (1U) +#define PXP_DITHER_CTRL_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_ENABLE1_MASK) +#define PXP_DITHER_CTRL_ENABLE2_MASK (0x4U) +#define PXP_DITHER_CTRL_ENABLE2_SHIFT (2U) +#define PXP_DITHER_CTRL_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_ENABLE2_MASK) +#define PXP_DITHER_CTRL_DITHER_MODE0_MASK (0x38U) +#define PXP_DITHER_CTRL_DITHER_MODE0_SHIFT (3U) +#define PXP_DITHER_CTRL_DITHER_MODE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_DITHER_MODE0_MASK) +#define PXP_DITHER_CTRL_DITHER_MODE1_MASK (0x1C0U) +#define PXP_DITHER_CTRL_DITHER_MODE1_SHIFT (6U) +#define PXP_DITHER_CTRL_DITHER_MODE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_DITHER_MODE1_MASK) +#define PXP_DITHER_CTRL_DITHER_MODE2_MASK (0xE00U) +#define PXP_DITHER_CTRL_DITHER_MODE2_SHIFT (9U) +#define PXP_DITHER_CTRL_DITHER_MODE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_DITHER_MODE2_MASK) +#define PXP_DITHER_CTRL_NUM_QUANT_BIT_MASK (0x7000U) +#define PXP_DITHER_CTRL_NUM_QUANT_BIT_SHIFT (12U) +#define PXP_DITHER_CTRL_NUM_QUANT_BIT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_NUM_QUANT_BIT_MASK) +#define PXP_DITHER_CTRL_LUT_MODE_MASK (0x18000U) +#define PXP_DITHER_CTRL_LUT_MODE_SHIFT (15U) +#define PXP_DITHER_CTRL_LUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_LUT_MODE_MASK) +#define PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_MASK (0x60000U) +#define PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_SHIFT (17U) +#define PXP_DITHER_CTRL_IDX_MATRIX0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_IDX_MATRIX0_SIZE_MASK) +#define PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_MASK (0x180000U) +#define PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_SHIFT (19U) +#define PXP_DITHER_CTRL_IDX_MATRIX1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_IDX_MATRIX1_SIZE_MASK) +#define PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_MASK (0x600000U) +#define PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_SHIFT (21U) +#define PXP_DITHER_CTRL_IDX_MATRIX2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_IDX_MATRIX2_SIZE_MASK) +#define PXP_DITHER_CTRL_FINAL_LUT_ENABLE_MASK (0x800000U) +#define PXP_DITHER_CTRL_FINAL_LUT_ENABLE_SHIFT (23U) +#define PXP_DITHER_CTRL_FINAL_LUT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_FINAL_LUT_ENABLE_MASK) +#define PXP_DITHER_CTRL_ORDERED_ROUND_MODE_MASK (0x1000000U) +#define PXP_DITHER_CTRL_ORDERED_ROUND_MODE_SHIFT (24U) +#define PXP_DITHER_CTRL_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_ORDERED_ROUND_MODE_MASK) +#define PXP_DITHER_CTRL_BUSY2_MASK (0x20000000U) +#define PXP_DITHER_CTRL_BUSY2_SHIFT (29U) +#define PXP_DITHER_CTRL_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_BUSY2_SHIFT)) & PXP_DITHER_CTRL_BUSY2_MASK) +#define PXP_DITHER_CTRL_BUSY1_MASK (0x40000000U) +#define PXP_DITHER_CTRL_BUSY1_SHIFT (30U) +#define PXP_DITHER_CTRL_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_BUSY1_SHIFT)) & PXP_DITHER_CTRL_BUSY1_MASK) +#define PXP_DITHER_CTRL_BUSY0_MASK (0x80000000U) +#define PXP_DITHER_CTRL_BUSY0_SHIFT (31U) +#define PXP_DITHER_CTRL_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_BUSY0_SHIFT)) & PXP_DITHER_CTRL_BUSY0_MASK) + +/*! @name DITHER_CTRL_SET - Dither Control Register 0 */ +#define PXP_DITHER_CTRL_SET_ENABLE0_MASK (0x1U) +#define PXP_DITHER_CTRL_SET_ENABLE0_SHIFT (0U) +#define PXP_DITHER_CTRL_SET_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_SET_ENABLE0_MASK) +#define PXP_DITHER_CTRL_SET_ENABLE1_MASK (0x2U) +#define PXP_DITHER_CTRL_SET_ENABLE1_SHIFT (1U) +#define PXP_DITHER_CTRL_SET_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_SET_ENABLE1_MASK) +#define PXP_DITHER_CTRL_SET_ENABLE2_MASK (0x4U) +#define PXP_DITHER_CTRL_SET_ENABLE2_SHIFT (2U) +#define PXP_DITHER_CTRL_SET_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_SET_ENABLE2_MASK) +#define PXP_DITHER_CTRL_SET_DITHER_MODE0_MASK (0x38U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE0_SHIFT (3U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_SET_DITHER_MODE0_MASK) +#define PXP_DITHER_CTRL_SET_DITHER_MODE1_MASK (0x1C0U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE1_SHIFT (6U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_SET_DITHER_MODE1_MASK) +#define PXP_DITHER_CTRL_SET_DITHER_MODE2_MASK (0xE00U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE2_SHIFT (9U) +#define PXP_DITHER_CTRL_SET_DITHER_MODE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_SET_DITHER_MODE2_MASK) +#define PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_MASK (0x7000U) +#define PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_SHIFT (12U) +#define PXP_DITHER_CTRL_SET_NUM_QUANT_BIT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_SET_NUM_QUANT_BIT_MASK) +#define PXP_DITHER_CTRL_SET_LUT_MODE_MASK (0x18000U) +#define PXP_DITHER_CTRL_SET_LUT_MODE_SHIFT (15U) +#define PXP_DITHER_CTRL_SET_LUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_SET_LUT_MODE_MASK) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_MASK (0x60000U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_SHIFT (17U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_SET_IDX_MATRIX0_SIZE_MASK) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_MASK (0x180000U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_SHIFT (19U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_SET_IDX_MATRIX1_SIZE_MASK) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_MASK (0x600000U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_SHIFT (21U) +#define PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_SET_IDX_MATRIX2_SIZE_MASK) +#define PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_MASK (0x800000U) +#define PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_SHIFT (23U) +#define PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_SET_FINAL_LUT_ENABLE_MASK) +#define PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_MASK (0x1000000U) +#define PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_SHIFT (24U) +#define PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_SET_ORDERED_ROUND_MODE_MASK) +#define PXP_DITHER_CTRL_SET_BUSY2_MASK (0x20000000U) +#define PXP_DITHER_CTRL_SET_BUSY2_SHIFT (29U) +#define PXP_DITHER_CTRL_SET_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_BUSY2_SHIFT)) & PXP_DITHER_CTRL_SET_BUSY2_MASK) +#define PXP_DITHER_CTRL_SET_BUSY1_MASK (0x40000000U) +#define PXP_DITHER_CTRL_SET_BUSY1_SHIFT (30U) +#define PXP_DITHER_CTRL_SET_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_BUSY1_SHIFT)) & PXP_DITHER_CTRL_SET_BUSY1_MASK) +#define PXP_DITHER_CTRL_SET_BUSY0_MASK (0x80000000U) +#define PXP_DITHER_CTRL_SET_BUSY0_SHIFT (31U) +#define PXP_DITHER_CTRL_SET_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_SET_BUSY0_SHIFT)) & PXP_DITHER_CTRL_SET_BUSY0_MASK) + +/*! @name DITHER_CTRL_CLR - Dither Control Register 0 */ +#define PXP_DITHER_CTRL_CLR_ENABLE0_MASK (0x1U) +#define PXP_DITHER_CTRL_CLR_ENABLE0_SHIFT (0U) +#define PXP_DITHER_CTRL_CLR_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_CLR_ENABLE0_MASK) +#define PXP_DITHER_CTRL_CLR_ENABLE1_MASK (0x2U) +#define PXP_DITHER_CTRL_CLR_ENABLE1_SHIFT (1U) +#define PXP_DITHER_CTRL_CLR_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_CLR_ENABLE1_MASK) +#define PXP_DITHER_CTRL_CLR_ENABLE2_MASK (0x4U) +#define PXP_DITHER_CTRL_CLR_ENABLE2_SHIFT (2U) +#define PXP_DITHER_CTRL_CLR_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_CLR_ENABLE2_MASK) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE0_MASK (0x38U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE0_SHIFT (3U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_CLR_DITHER_MODE0_MASK) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE1_MASK (0x1C0U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE1_SHIFT (6U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_CLR_DITHER_MODE1_MASK) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE2_MASK (0xE00U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE2_SHIFT (9U) +#define PXP_DITHER_CTRL_CLR_DITHER_MODE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_CLR_DITHER_MODE2_MASK) +#define PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_MASK (0x7000U) +#define PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_SHIFT (12U) +#define PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_CLR_NUM_QUANT_BIT_MASK) +#define PXP_DITHER_CTRL_CLR_LUT_MODE_MASK (0x18000U) +#define PXP_DITHER_CTRL_CLR_LUT_MODE_SHIFT (15U) +#define PXP_DITHER_CTRL_CLR_LUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_CLR_LUT_MODE_MASK) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_MASK (0x60000U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_SHIFT (17U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_CLR_IDX_MATRIX0_SIZE_MASK) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_MASK (0x180000U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_SHIFT (19U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_CLR_IDX_MATRIX1_SIZE_MASK) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_MASK (0x600000U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_SHIFT (21U) +#define PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_CLR_IDX_MATRIX2_SIZE_MASK) +#define PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_MASK (0x800000U) +#define PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_SHIFT (23U) +#define PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_CLR_FINAL_LUT_ENABLE_MASK) +#define PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_MASK (0x1000000U) +#define PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_SHIFT (24U) +#define PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_CLR_ORDERED_ROUND_MODE_MASK) +#define PXP_DITHER_CTRL_CLR_BUSY2_MASK (0x20000000U) +#define PXP_DITHER_CTRL_CLR_BUSY2_SHIFT (29U) +#define PXP_DITHER_CTRL_CLR_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_BUSY2_SHIFT)) & PXP_DITHER_CTRL_CLR_BUSY2_MASK) +#define PXP_DITHER_CTRL_CLR_BUSY1_MASK (0x40000000U) +#define PXP_DITHER_CTRL_CLR_BUSY1_SHIFT (30U) +#define PXP_DITHER_CTRL_CLR_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_BUSY1_SHIFT)) & PXP_DITHER_CTRL_CLR_BUSY1_MASK) +#define PXP_DITHER_CTRL_CLR_BUSY0_MASK (0x80000000U) +#define PXP_DITHER_CTRL_CLR_BUSY0_SHIFT (31U) +#define PXP_DITHER_CTRL_CLR_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_CLR_BUSY0_SHIFT)) & PXP_DITHER_CTRL_CLR_BUSY0_MASK) + +/*! @name DITHER_CTRL_TOG - Dither Control Register 0 */ +#define PXP_DITHER_CTRL_TOG_ENABLE0_MASK (0x1U) +#define PXP_DITHER_CTRL_TOG_ENABLE0_SHIFT (0U) +#define PXP_DITHER_CTRL_TOG_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ENABLE0_SHIFT)) & PXP_DITHER_CTRL_TOG_ENABLE0_MASK) +#define PXP_DITHER_CTRL_TOG_ENABLE1_MASK (0x2U) +#define PXP_DITHER_CTRL_TOG_ENABLE1_SHIFT (1U) +#define PXP_DITHER_CTRL_TOG_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ENABLE1_SHIFT)) & PXP_DITHER_CTRL_TOG_ENABLE1_MASK) +#define PXP_DITHER_CTRL_TOG_ENABLE2_MASK (0x4U) +#define PXP_DITHER_CTRL_TOG_ENABLE2_SHIFT (2U) +#define PXP_DITHER_CTRL_TOG_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ENABLE2_SHIFT)) & PXP_DITHER_CTRL_TOG_ENABLE2_MASK) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE0_MASK (0x38U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE0_SHIFT (3U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_DITHER_MODE0_SHIFT)) & PXP_DITHER_CTRL_TOG_DITHER_MODE0_MASK) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE1_MASK (0x1C0U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE1_SHIFT (6U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_DITHER_MODE1_SHIFT)) & PXP_DITHER_CTRL_TOG_DITHER_MODE1_MASK) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE2_MASK (0xE00U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE2_SHIFT (9U) +#define PXP_DITHER_CTRL_TOG_DITHER_MODE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_DITHER_MODE2_SHIFT)) & PXP_DITHER_CTRL_TOG_DITHER_MODE2_MASK) +#define PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_MASK (0x7000U) +#define PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_SHIFT (12U) +#define PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_SHIFT)) & PXP_DITHER_CTRL_TOG_NUM_QUANT_BIT_MASK) +#define PXP_DITHER_CTRL_TOG_LUT_MODE_MASK (0x18000U) +#define PXP_DITHER_CTRL_TOG_LUT_MODE_SHIFT (15U) +#define PXP_DITHER_CTRL_TOG_LUT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_LUT_MODE_SHIFT)) & PXP_DITHER_CTRL_TOG_LUT_MODE_MASK) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_MASK (0x60000U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_SHIFT (17U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_SHIFT)) & PXP_DITHER_CTRL_TOG_IDX_MATRIX0_SIZE_MASK) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_MASK (0x180000U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_SHIFT (19U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_SHIFT)) & PXP_DITHER_CTRL_TOG_IDX_MATRIX1_SIZE_MASK) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_MASK (0x600000U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_SHIFT (21U) +#define PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_SHIFT)) & PXP_DITHER_CTRL_TOG_IDX_MATRIX2_SIZE_MASK) +#define PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_MASK (0x800000U) +#define PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_SHIFT (23U) +#define PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_SHIFT)) & PXP_DITHER_CTRL_TOG_FINAL_LUT_ENABLE_MASK) +#define PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_MASK (0x1000000U) +#define PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_SHIFT (24U) +#define PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_SHIFT)) & PXP_DITHER_CTRL_TOG_ORDERED_ROUND_MODE_MASK) +#define PXP_DITHER_CTRL_TOG_BUSY2_MASK (0x20000000U) +#define PXP_DITHER_CTRL_TOG_BUSY2_SHIFT (29U) +#define PXP_DITHER_CTRL_TOG_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_BUSY2_SHIFT)) & PXP_DITHER_CTRL_TOG_BUSY2_MASK) +#define PXP_DITHER_CTRL_TOG_BUSY1_MASK (0x40000000U) +#define PXP_DITHER_CTRL_TOG_BUSY1_SHIFT (30U) +#define PXP_DITHER_CTRL_TOG_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_BUSY1_SHIFT)) & PXP_DITHER_CTRL_TOG_BUSY1_MASK) +#define PXP_DITHER_CTRL_TOG_BUSY0_MASK (0x80000000U) +#define PXP_DITHER_CTRL_TOG_BUSY0_SHIFT (31U) +#define PXP_DITHER_CTRL_TOG_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_CTRL_TOG_BUSY0_SHIFT)) & PXP_DITHER_CTRL_TOG_BUSY0_MASK) + +/*! @name DITHER_FINAL_LUT_DATA0 - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA0_DATA0_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA0_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA0_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA1_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA1_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA1_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA2_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA2_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA2_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA3_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA3_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA0_DATA3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_DATA3_MASK) + +/*! @name DITHER_FINAL_LUT_DATA0_SET - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA0_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA1_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA2_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_SET_DATA3_MASK) + +/*! @name DITHER_FINAL_LUT_DATA0_CLR - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA0_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA1_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA2_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_CLR_DATA3_MASK) + +/*! @name DITHER_FINAL_LUT_DATA0_TOG - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA0_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA1_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA2_MASK) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA0_TOG_DATA3_MASK) + +/*! @name DITHER_FINAL_LUT_DATA1 - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA1_DATA4_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA4_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA4_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA5_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA5_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA5_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA6_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA6_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA6_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA7_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA7_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA1_DATA7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_DATA7_MASK) + +/*! @name DITHER_FINAL_LUT_DATA1_SET - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA4_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA5_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA6_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_SET_DATA7_MASK) + +/*! @name DITHER_FINAL_LUT_DATA1_CLR - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA4_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA5_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA6_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_CLR_DATA7_MASK) + +/*! @name DITHER_FINAL_LUT_DATA1_TOG - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA4_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA5_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA6_MASK) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA1_TOG_DATA7_MASK) + +/*! @name DITHER_FINAL_LUT_DATA2 - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA2_DATA8_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA8_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA8(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA8_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA9_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA9_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA9(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA9_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA10_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA10_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA10_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA11_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA11_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA2_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_DATA11_MASK) + +/*! @name DITHER_FINAL_LUT_DATA2_SET - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA8_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA9_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA10_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_SET_DATA11_MASK) + +/*! @name DITHER_FINAL_LUT_DATA2_CLR - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA8_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA9_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA10_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_CLR_DATA11_MASK) + +/*! @name DITHER_FINAL_LUT_DATA2_TOG - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA8_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA9_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA10_MASK) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA2_TOG_DATA11_MASK) + +/*! @name DITHER_FINAL_LUT_DATA3 - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA3_DATA12_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA12_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA12_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA13_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA13_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA13_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA14_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA14_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA14_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA15_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA15_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA3_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_DATA15_MASK) + +/*! @name DITHER_FINAL_LUT_DATA3_SET - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA12_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA13_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA14_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_SET_DATA15_MASK) + +/*! @name DITHER_FINAL_LUT_DATA3_CLR - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA12_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA13_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA14_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_CLR_DATA15_MASK) + +/*! @name DITHER_FINAL_LUT_DATA3_TOG - Final stage lookup value Register */ +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_MASK (0xFFU) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_SHIFT (0U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA12_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_MASK (0xFF00U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_SHIFT (8U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA13_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_MASK (0xFF0000U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_SHIFT (16U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA14_MASK) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_MASK (0xFF000000U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_SHIFT (24U) +#define PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15(x) (((uint32_t)(((uint32_t)(x)) << PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_SHIFT)) & PXP_DITHER_FINAL_LUT_DATA3_TOG_DATA15_MASK) + +/*! @name WFE_B_CTRL - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_CTRL_ENABLE_MASK (0x1U) +#define PXP_WFE_B_CTRL_ENABLE_SHIFT (0U) +#define PXP_WFE_B_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_ENABLE_MASK) +#define PXP_WFE_B_CTRL_SW_RESET_MASK (0x4U) +#define PXP_WFE_B_CTRL_SW_RESET_SHIFT (2U) +#define PXP_WFE_B_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_SW_RESET_MASK) +#define PXP_WFE_B_CTRL_DONE_MASK (0x80000000U) +#define PXP_WFE_B_CTRL_DONE_SHIFT (31U) +#define PXP_WFE_B_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_DONE_SHIFT)) & PXP_WFE_B_CTRL_DONE_MASK) + +/*! @name WFE_B_CTRL_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_CTRL_SET_ENABLE_MASK (0x1U) +#define PXP_WFE_B_CTRL_SET_ENABLE_SHIFT (0U) +#define PXP_WFE_B_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SET_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_SET_ENABLE_MASK) +#define PXP_WFE_B_CTRL_SET_SW_RESET_MASK (0x4U) +#define PXP_WFE_B_CTRL_SET_SW_RESET_SHIFT (2U) +#define PXP_WFE_B_CTRL_SET_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SET_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_SET_SW_RESET_MASK) +#define PXP_WFE_B_CTRL_SET_DONE_MASK (0x80000000U) +#define PXP_WFE_B_CTRL_SET_DONE_SHIFT (31U) +#define PXP_WFE_B_CTRL_SET_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_SET_DONE_SHIFT)) & PXP_WFE_B_CTRL_SET_DONE_MASK) + +/*! @name WFE_B_CTRL_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_CTRL_CLR_ENABLE_MASK (0x1U) +#define PXP_WFE_B_CTRL_CLR_ENABLE_SHIFT (0U) +#define PXP_WFE_B_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_CLR_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_CLR_ENABLE_MASK) +#define PXP_WFE_B_CTRL_CLR_SW_RESET_MASK (0x4U) +#define PXP_WFE_B_CTRL_CLR_SW_RESET_SHIFT (2U) +#define PXP_WFE_B_CTRL_CLR_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_CLR_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_CLR_SW_RESET_MASK) +#define PXP_WFE_B_CTRL_CLR_DONE_MASK (0x80000000U) +#define PXP_WFE_B_CTRL_CLR_DONE_SHIFT (31U) +#define PXP_WFE_B_CTRL_CLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_CLR_DONE_SHIFT)) & PXP_WFE_B_CTRL_CLR_DONE_MASK) + +/*! @name WFE_B_CTRL_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_CTRL_TOG_ENABLE_MASK (0x1U) +#define PXP_WFE_B_CTRL_TOG_ENABLE_SHIFT (0U) +#define PXP_WFE_B_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_TOG_ENABLE_SHIFT)) & PXP_WFE_B_CTRL_TOG_ENABLE_MASK) +#define PXP_WFE_B_CTRL_TOG_SW_RESET_MASK (0x4U) +#define PXP_WFE_B_CTRL_TOG_SW_RESET_SHIFT (2U) +#define PXP_WFE_B_CTRL_TOG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_TOG_SW_RESET_SHIFT)) & PXP_WFE_B_CTRL_TOG_SW_RESET_MASK) +#define PXP_WFE_B_CTRL_TOG_DONE_MASK (0x80000000U) +#define PXP_WFE_B_CTRL_TOG_DONE_SHIFT (31U) +#define PXP_WFE_B_CTRL_TOG_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_CTRL_TOG_DONE_SHIFT)) & PXP_WFE_B_CTRL_TOG_DONE_MASK) + +/*! @name WFE_B_DIMENSIONS - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_DIMENSIONS_WIDTH_MASK (0xFFFU) +#define PXP_WFE_B_DIMENSIONS_WIDTH_SHIFT (0U) +#define PXP_WFE_B_DIMENSIONS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_DIMENSIONS_WIDTH_SHIFT)) & PXP_WFE_B_DIMENSIONS_WIDTH_MASK) +#define PXP_WFE_B_DIMENSIONS_HEIGHT_MASK (0xFFF0000U) +#define PXP_WFE_B_DIMENSIONS_HEIGHT_SHIFT (16U) +#define PXP_WFE_B_DIMENSIONS_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_DIMENSIONS_HEIGHT_SHIFT)) & PXP_WFE_B_DIMENSIONS_HEIGHT_MASK) + +/*! @name WFE_B_OFFSET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_OFFSET_X_OFFSET_MASK (0xFFFU) +#define PXP_WFE_B_OFFSET_X_OFFSET_SHIFT (0U) +#define PXP_WFE_B_OFFSET_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_OFFSET_X_OFFSET_SHIFT)) & PXP_WFE_B_OFFSET_X_OFFSET_MASK) +#define PXP_WFE_B_OFFSET_Y_OFFSET_MASK (0xFFF0000U) +#define PXP_WFE_B_OFFSET_Y_OFFSET_SHIFT (16U) +#define PXP_WFE_B_OFFSET_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_OFFSET_Y_OFFSET_SHIFT)) & PXP_WFE_B_OFFSET_Y_OFFSET_MASK) + +/*! @name WFE_B_SW_DATA_REGS - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_SW_DATA_REGS_VAL0_MASK (0xFFU) +#define PXP_WFE_B_SW_DATA_REGS_VAL0_SHIFT (0U) +#define PXP_WFE_B_SW_DATA_REGS_VAL0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL0_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL0_MASK) +#define PXP_WFE_B_SW_DATA_REGS_VAL1_MASK (0xFF00U) +#define PXP_WFE_B_SW_DATA_REGS_VAL1_SHIFT (8U) +#define PXP_WFE_B_SW_DATA_REGS_VAL1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL1_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL1_MASK) +#define PXP_WFE_B_SW_DATA_REGS_VAL2_MASK (0xFF0000U) +#define PXP_WFE_B_SW_DATA_REGS_VAL2_SHIFT (16U) +#define PXP_WFE_B_SW_DATA_REGS_VAL2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL2_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL2_MASK) +#define PXP_WFE_B_SW_DATA_REGS_VAL3_MASK (0xFF000000U) +#define PXP_WFE_B_SW_DATA_REGS_VAL3_SHIFT (24U) +#define PXP_WFE_B_SW_DATA_REGS_VAL3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_DATA_REGS_VAL3_SHIFT)) & PXP_WFE_B_SW_DATA_REGS_VAL3_MASK) + +/*! @name WFE_B_SW_FLAG_REGS - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_SW_FLAG_REGS_VAL0_MASK (0x1U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL0_SHIFT (0U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL0_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL0_MASK) +#define PXP_WFE_B_SW_FLAG_REGS_VAL1_MASK (0x2U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL1_SHIFT (1U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL1_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL1_MASK) +#define PXP_WFE_B_SW_FLAG_REGS_VAL2_MASK (0x4U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL2_SHIFT (2U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL2_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL2_MASK) +#define PXP_WFE_B_SW_FLAG_REGS_VAL3_MASK (0x8U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL3_SHIFT (3U) +#define PXP_WFE_B_SW_FLAG_REGS_VAL3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_SW_FLAG_REGS_VAL3_SHIFT)) & PXP_WFE_B_SW_FLAG_REGS_VAL3_MASK) + +/*! @name WFE_B_STAGE1_MUX0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX0_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX0_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX0_MASK) +#define PXP_WFE_B_STAGE1_MUX0_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX0_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX0_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX1_MASK) +#define PXP_WFE_B_STAGE1_MUX0_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX0_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX0_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX2_MASK) +#define PXP_WFE_B_STAGE1_MUX0_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX0_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX0_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_MUX3_MASK) + +/*! @name WFE_B_STAGE1_MUX0_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX0_MASK) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX1_MASK) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX2_MASK) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX0_SET_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_SET_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_SET_MUX3_MASK) + +/*! @name WFE_B_STAGE1_MUX0_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX0_MASK) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX1_MASK) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX2_MASK) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX0_CLR_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_CLR_MUX3_MASK) + +/*! @name WFE_B_STAGE1_MUX0_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX0_MASK) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX1_MASK) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX2_MASK) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX0_TOG_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_SHIFT)) & PXP_WFE_B_STAGE1_MUX0_TOG_MUX3_MASK) + +/*! @name WFE_B_STAGE1_MUX1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX1_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX1_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX1_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX4_MASK) +#define PXP_WFE_B_STAGE1_MUX1_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX1_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX1_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX5_MASK) +#define PXP_WFE_B_STAGE1_MUX1_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX1_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX1_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX6_MASK) +#define PXP_WFE_B_STAGE1_MUX1_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX1_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX1_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_MUX7_MASK) + +/*! @name WFE_B_STAGE1_MUX1_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX4_MASK) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX5_MASK) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX6_MASK) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX1_SET_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_SET_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_SET_MUX7_MASK) + +/*! @name WFE_B_STAGE1_MUX1_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX4_MASK) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX5_MASK) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX6_MASK) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX1_CLR_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_CLR_MUX7_MASK) + +/*! @name WFE_B_STAGE1_MUX1_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX4_MASK) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX5_MASK) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX6_MASK) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX1_TOG_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_SHIFT)) & PXP_WFE_B_STAGE1_MUX1_TOG_MUX7_MASK) + +/*! @name WFE_B_STAGE1_MUX2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX2_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX2_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX2_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX8_MASK) +#define PXP_WFE_B_STAGE1_MUX2_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX2_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX2_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX9_MASK) +#define PXP_WFE_B_STAGE1_MUX2_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX2_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX2_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX10_MASK) +#define PXP_WFE_B_STAGE1_MUX2_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX2_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX2_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_MUX11_MASK) + +/*! @name WFE_B_STAGE1_MUX2_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX8_MASK) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX9_MASK) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX10_MASK) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX2_SET_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_SET_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_SET_MUX11_MASK) + +/*! @name WFE_B_STAGE1_MUX2_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX8_MASK) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX9_MASK) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX10_MASK) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX2_CLR_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_CLR_MUX11_MASK) + +/*! @name WFE_B_STAGE1_MUX2_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX8_MASK) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX9_MASK) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX10_MASK) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX2_TOG_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_SHIFT)) & PXP_WFE_B_STAGE1_MUX2_TOG_MUX11_MASK) + +/*! @name WFE_B_STAGE1_MUX3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX3_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX3_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX3_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX12_MASK) +#define PXP_WFE_B_STAGE1_MUX3_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX3_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX3_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX13_MASK) +#define PXP_WFE_B_STAGE1_MUX3_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX3_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX3_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX14_MASK) +#define PXP_WFE_B_STAGE1_MUX3_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX3_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX3_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_MUX15_MASK) + +/*! @name WFE_B_STAGE1_MUX3_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX12_MASK) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX13_MASK) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX14_MASK) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX3_SET_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_SET_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_SET_MUX15_MASK) + +/*! @name WFE_B_STAGE1_MUX3_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX12_MASK) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX13_MASK) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX14_MASK) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX3_CLR_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_CLR_MUX15_MASK) + +/*! @name WFE_B_STAGE1_MUX3_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX12_MASK) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX13_MASK) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX14_MASK) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX3_TOG_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_SHIFT)) & PXP_WFE_B_STAGE1_MUX3_TOG_MUX15_MASK) + +/*! @name WFE_B_STAGE1_MUX4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX4_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX4_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX4_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX16_MASK) +#define PXP_WFE_B_STAGE1_MUX4_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX4_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX4_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX17_MASK) +#define PXP_WFE_B_STAGE1_MUX4_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX4_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX4_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX18_MASK) +#define PXP_WFE_B_STAGE1_MUX4_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX4_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX4_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_MUX19_MASK) + +/*! @name WFE_B_STAGE1_MUX4_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX16_MASK) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX17_MASK) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX18_MASK) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX4_SET_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_SET_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_SET_MUX19_MASK) + +/*! @name WFE_B_STAGE1_MUX4_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX16_MASK) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX17_MASK) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX18_MASK) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX4_CLR_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_CLR_MUX19_MASK) + +/*! @name WFE_B_STAGE1_MUX4_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX16_MASK) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX17_MASK) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX18_MASK) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX4_TOG_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_SHIFT)) & PXP_WFE_B_STAGE1_MUX4_TOG_MUX19_MASK) + +/*! @name WFE_B_STAGE1_MUX5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX5_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX5_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX5_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX20_MASK) +#define PXP_WFE_B_STAGE1_MUX5_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX5_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX5_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX21_MASK) +#define PXP_WFE_B_STAGE1_MUX5_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX5_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX5_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX22_MASK) +#define PXP_WFE_B_STAGE1_MUX5_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX5_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX5_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_MUX23_MASK) + +/*! @name WFE_B_STAGE1_MUX5_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX20_MASK) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX21_MASK) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX22_MASK) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX5_SET_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_SET_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_SET_MUX23_MASK) + +/*! @name WFE_B_STAGE1_MUX5_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX20_MASK) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX21_MASK) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX22_MASK) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX5_CLR_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_CLR_MUX23_MASK) + +/*! @name WFE_B_STAGE1_MUX5_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX20_MASK) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX21_MASK) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX22_MASK) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX5_TOG_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_SHIFT)) & PXP_WFE_B_STAGE1_MUX5_TOG_MUX23_MASK) + +/*! @name WFE_B_STAGE1_MUX6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX6_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX6_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX6_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX24_MASK) +#define PXP_WFE_B_STAGE1_MUX6_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX6_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX6_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX25_MASK) +#define PXP_WFE_B_STAGE1_MUX6_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX6_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX6_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX26_MASK) +#define PXP_WFE_B_STAGE1_MUX6_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX6_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX6_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_MUX27_MASK) + +/*! @name WFE_B_STAGE1_MUX6_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX24_MASK) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX25_MASK) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX26_MASK) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX6_SET_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_SET_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_SET_MUX27_MASK) + +/*! @name WFE_B_STAGE1_MUX6_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX24_MASK) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX25_MASK) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX26_MASK) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX6_CLR_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_CLR_MUX27_MASK) + +/*! @name WFE_B_STAGE1_MUX6_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX24_MASK) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX25_MASK) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX26_MASK) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX6_TOG_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_SHIFT)) & PXP_WFE_B_STAGE1_MUX6_TOG_MUX27_MASK) + +/*! @name WFE_B_STAGE1_MUX7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX7_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX7_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX7_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX28_MASK) +#define PXP_WFE_B_STAGE1_MUX7_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX7_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX7_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX29_MASK) +#define PXP_WFE_B_STAGE1_MUX7_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX7_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX7_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX30_MASK) +#define PXP_WFE_B_STAGE1_MUX7_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX7_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX7_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_MUX31_MASK) + +/*! @name WFE_B_STAGE1_MUX7_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX28_MASK) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX29_MASK) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX30_MASK) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX7_SET_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_SET_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_SET_MUX31_MASK) + +/*! @name WFE_B_STAGE1_MUX7_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX28_MASK) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX29_MASK) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX30_MASK) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX7_CLR_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_CLR_MUX31_MASK) + +/*! @name WFE_B_STAGE1_MUX7_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX28_MASK) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX29_MASK) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX30_MASK) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE1_MUX7_TOG_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_SHIFT)) & PXP_WFE_B_STAGE1_MUX7_TOG_MUX31_MASK) + +/*! @name WFE_B_STAGE1_MUX8 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX8_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX8_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX8_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_MUX32_MASK) + +/*! @name WFE_B_STAGE1_MUX8_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX8_SET_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX8_SET_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX8_SET_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_SET_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_SET_MUX32_MASK) + +/*! @name WFE_B_STAGE1_MUX8_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX8_CLR_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_CLR_MUX32_MASK) + +/*! @name WFE_B_STAGE1_MUX8_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE1_MUX8_TOG_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_SHIFT)) & PXP_WFE_B_STAGE1_MUX8_TOG_MUX32_MASK) + +/*! @name WFE_B_STAGE2_MUX0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX0_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX0_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX0_MASK) +#define PXP_WFE_B_STAGE2_MUX0_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX0_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX0_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX1_MASK) +#define PXP_WFE_B_STAGE2_MUX0_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX0_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX0_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX2_MASK) +#define PXP_WFE_B_STAGE2_MUX0_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX0_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX0_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_MUX3_MASK) + +/*! @name WFE_B_STAGE2_MUX0_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX0_MASK) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX1_MASK) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX2_MASK) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX0_SET_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_SET_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_SET_MUX3_MASK) + +/*! @name WFE_B_STAGE2_MUX0_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX0_MASK) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX1_MASK) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX2_MASK) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX0_CLR_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_CLR_MUX3_MASK) + +/*! @name WFE_B_STAGE2_MUX0_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX0_MASK) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX1_MASK) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX2_MASK) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX0_TOG_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_SHIFT)) & PXP_WFE_B_STAGE2_MUX0_TOG_MUX3_MASK) + +/*! @name WFE_B_STAGE2_MUX1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX1_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX1_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX1_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX4_MASK) +#define PXP_WFE_B_STAGE2_MUX1_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX1_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX1_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX5_MASK) +#define PXP_WFE_B_STAGE2_MUX1_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX1_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX1_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX6_MASK) +#define PXP_WFE_B_STAGE2_MUX1_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX1_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX1_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_MUX7_MASK) + +/*! @name WFE_B_STAGE2_MUX1_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX4_MASK) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX5_MASK) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX6_MASK) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX1_SET_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_SET_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_SET_MUX7_MASK) + +/*! @name WFE_B_STAGE2_MUX1_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX4_MASK) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX5_MASK) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX6_MASK) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX1_CLR_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_CLR_MUX7_MASK) + +/*! @name WFE_B_STAGE2_MUX1_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX4_MASK) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX5_MASK) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX6_MASK) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX1_TOG_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_SHIFT)) & PXP_WFE_B_STAGE2_MUX1_TOG_MUX7_MASK) + +/*! @name WFE_B_STAGE2_MUX2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX2_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX2_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX2_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX8_MASK) +#define PXP_WFE_B_STAGE2_MUX2_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX2_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX2_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX9_MASK) +#define PXP_WFE_B_STAGE2_MUX2_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX2_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX2_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX10_MASK) +#define PXP_WFE_B_STAGE2_MUX2_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX2_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX2_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_MUX11_MASK) + +/*! @name WFE_B_STAGE2_MUX2_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX8_MASK) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX9_MASK) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX10_MASK) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX2_SET_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_SET_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_SET_MUX11_MASK) + +/*! @name WFE_B_STAGE2_MUX2_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX8_MASK) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX9_MASK) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX10_MASK) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX2_CLR_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_CLR_MUX11_MASK) + +/*! @name WFE_B_STAGE2_MUX2_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX8_MASK) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX9_MASK) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX10_MASK) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX2_TOG_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_SHIFT)) & PXP_WFE_B_STAGE2_MUX2_TOG_MUX11_MASK) + +/*! @name WFE_B_STAGE2_MUX3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX3_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX3_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX3_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX12_MASK) +#define PXP_WFE_B_STAGE2_MUX3_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX3_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX3_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX13_MASK) +#define PXP_WFE_B_STAGE2_MUX3_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX3_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX3_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX14_MASK) +#define PXP_WFE_B_STAGE2_MUX3_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX3_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX3_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_MUX15_MASK) + +/*! @name WFE_B_STAGE2_MUX3_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX12_MASK) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX13_MASK) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX14_MASK) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX3_SET_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_SET_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_SET_MUX15_MASK) + +/*! @name WFE_B_STAGE2_MUX3_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX12_MASK) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX13_MASK) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX14_MASK) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX3_CLR_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_CLR_MUX15_MASK) + +/*! @name WFE_B_STAGE2_MUX3_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX12_MASK) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX13_MASK) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX14_MASK) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX3_TOG_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_SHIFT)) & PXP_WFE_B_STAGE2_MUX3_TOG_MUX15_MASK) + +/*! @name WFE_B_STAGE2_MUX4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX4_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX4_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX4_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX16_MASK) +#define PXP_WFE_B_STAGE2_MUX4_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX4_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX4_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX17_MASK) +#define PXP_WFE_B_STAGE2_MUX4_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX4_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX4_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX18_MASK) +#define PXP_WFE_B_STAGE2_MUX4_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX4_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX4_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_MUX19_MASK) + +/*! @name WFE_B_STAGE2_MUX4_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX16_MASK) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX17_MASK) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX18_MASK) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX4_SET_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_SET_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_SET_MUX19_MASK) + +/*! @name WFE_B_STAGE2_MUX4_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX16_MASK) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX17_MASK) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX18_MASK) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX4_CLR_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_CLR_MUX19_MASK) + +/*! @name WFE_B_STAGE2_MUX4_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX16_MASK) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX17_MASK) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX18_MASK) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX4_TOG_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_SHIFT)) & PXP_WFE_B_STAGE2_MUX4_TOG_MUX19_MASK) + +/*! @name WFE_B_STAGE2_MUX5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX5_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX5_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX5_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX20_MASK) +#define PXP_WFE_B_STAGE2_MUX5_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX5_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX5_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX21_MASK) +#define PXP_WFE_B_STAGE2_MUX5_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX5_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX5_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX22_MASK) +#define PXP_WFE_B_STAGE2_MUX5_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX5_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX5_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_MUX23_MASK) + +/*! @name WFE_B_STAGE2_MUX5_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX20_MASK) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX21_MASK) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX22_MASK) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX5_SET_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_SET_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_SET_MUX23_MASK) + +/*! @name WFE_B_STAGE2_MUX5_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX20_MASK) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX21_MASK) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX22_MASK) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX5_CLR_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_CLR_MUX23_MASK) + +/*! @name WFE_B_STAGE2_MUX5_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX20_MASK) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX21_MASK) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX22_MASK) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX5_TOG_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_SHIFT)) & PXP_WFE_B_STAGE2_MUX5_TOG_MUX23_MASK) + +/*! @name WFE_B_STAGE2_MUX6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX6_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX6_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX6_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX24_MASK) +#define PXP_WFE_B_STAGE2_MUX6_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX6_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX6_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX25_MASK) +#define PXP_WFE_B_STAGE2_MUX6_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX6_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX6_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX26_MASK) +#define PXP_WFE_B_STAGE2_MUX6_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX6_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX6_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_MUX27_MASK) + +/*! @name WFE_B_STAGE2_MUX6_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX24_MASK) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX25_MASK) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX26_MASK) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX6_SET_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_SET_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_SET_MUX27_MASK) + +/*! @name WFE_B_STAGE2_MUX6_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX24_MASK) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX25_MASK) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX26_MASK) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX6_CLR_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_CLR_MUX27_MASK) + +/*! @name WFE_B_STAGE2_MUX6_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX24_MASK) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX25_MASK) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX26_MASK) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX6_TOG_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_SHIFT)) & PXP_WFE_B_STAGE2_MUX6_TOG_MUX27_MASK) + +/*! @name WFE_B_STAGE2_MUX7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX7_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX7_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX7_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX28_MASK) +#define PXP_WFE_B_STAGE2_MUX7_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX7_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX7_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX29_MASK) +#define PXP_WFE_B_STAGE2_MUX7_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX7_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX7_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX30_MASK) +#define PXP_WFE_B_STAGE2_MUX7_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX7_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX7_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_MUX31_MASK) + +/*! @name WFE_B_STAGE2_MUX7_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX28_MASK) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX29_MASK) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX30_MASK) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX7_SET_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_SET_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_SET_MUX31_MASK) + +/*! @name WFE_B_STAGE2_MUX7_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX28_MASK) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX29_MASK) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX30_MASK) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX7_CLR_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_CLR_MUX31_MASK) + +/*! @name WFE_B_STAGE2_MUX7_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX28_MASK) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX29_MASK) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX30_MASK) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX7_TOG_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_SHIFT)) & PXP_WFE_B_STAGE2_MUX7_TOG_MUX31_MASK) + +/*! @name WFE_B_STAGE2_MUX8 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX8_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX8_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX8_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX32_MASK) +#define PXP_WFE_B_STAGE2_MUX8_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX8_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX8_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX33_MASK) +#define PXP_WFE_B_STAGE2_MUX8_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX8_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX8_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX34_MASK) +#define PXP_WFE_B_STAGE2_MUX8_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX8_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX8_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_MUX35_MASK) + +/*! @name WFE_B_STAGE2_MUX8_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX32_MASK) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX33_MASK) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX34_MASK) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX8_SET_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_SET_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_SET_MUX35_MASK) + +/*! @name WFE_B_STAGE2_MUX8_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX32_MASK) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX33_MASK) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX34_MASK) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX8_CLR_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_CLR_MUX35_MASK) + +/*! @name WFE_B_STAGE2_MUX8_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX32_MASK) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX33_MASK) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX34_MASK) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX8_TOG_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_SHIFT)) & PXP_WFE_B_STAGE2_MUX8_TOG_MUX35_MASK) + +/*! @name WFE_B_STAGE2_MUX9 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX9_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX9_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX9_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX36_MASK) +#define PXP_WFE_B_STAGE2_MUX9_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX9_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX9_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX37_MASK) +#define PXP_WFE_B_STAGE2_MUX9_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX9_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX9_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX38_MASK) +#define PXP_WFE_B_STAGE2_MUX9_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX9_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX9_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_MUX39_MASK) + +/*! @name WFE_B_STAGE2_MUX9_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX36_MASK) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX37_MASK) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX38_MASK) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX9_SET_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_SET_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_SET_MUX39_MASK) + +/*! @name WFE_B_STAGE2_MUX9_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX36_MASK) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX37_MASK) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX38_MASK) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX9_CLR_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_CLR_MUX39_MASK) + +/*! @name WFE_B_STAGE2_MUX9_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX36_MASK) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX37_MASK) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX38_MASK) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX9_TOG_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_SHIFT)) & PXP_WFE_B_STAGE2_MUX9_TOG_MUX39_MASK) + +/*! @name WFE_B_STAGE2_MUX10 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX10_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX10_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX10_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX40_MASK) +#define PXP_WFE_B_STAGE2_MUX10_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX10_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX10_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX41_MASK) +#define PXP_WFE_B_STAGE2_MUX10_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX10_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX10_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX42_MASK) +#define PXP_WFE_B_STAGE2_MUX10_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX10_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX10_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_MUX43_MASK) + +/*! @name WFE_B_STAGE2_MUX10_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX40_MASK) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX41_MASK) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX42_MASK) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX10_SET_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_SET_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_SET_MUX43_MASK) + +/*! @name WFE_B_STAGE2_MUX10_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX40_MASK) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX41_MASK) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX42_MASK) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX10_CLR_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_CLR_MUX43_MASK) + +/*! @name WFE_B_STAGE2_MUX10_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX40_MASK) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX41_MASK) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX42_MASK) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX10_TOG_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_SHIFT)) & PXP_WFE_B_STAGE2_MUX10_TOG_MUX43_MASK) + +/*! @name WFE_B_STAGE2_MUX11 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX11_MUX44_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX11_MUX44_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX11_MUX44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX44_MASK) +#define PXP_WFE_B_STAGE2_MUX11_MUX45_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX11_MUX45_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX11_MUX45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX45_MASK) +#define PXP_WFE_B_STAGE2_MUX11_MUX46_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX11_MUX46_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX11_MUX46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX46_MASK) +#define PXP_WFE_B_STAGE2_MUX11_MUX47_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX11_MUX47_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX11_MUX47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_MUX47_MASK) + +/*! @name WFE_B_STAGE2_MUX11_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX44_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX44_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX44_MASK) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX45_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX45_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX45_MASK) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX46_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX46_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX46_MASK) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX47_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX47_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX11_SET_MUX47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_SET_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_SET_MUX47_MASK) + +/*! @name WFE_B_STAGE2_MUX11_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX44_MASK) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX45_MASK) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX46_MASK) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX11_CLR_MUX47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_CLR_MUX47_MASK) + +/*! @name WFE_B_STAGE2_MUX11_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX44_MASK) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_SHIFT (8U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX45_MASK) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_SHIFT (16U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX46_MASK) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_SHIFT (24U) +#define PXP_WFE_B_STAGE2_MUX11_TOG_MUX47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_SHIFT)) & PXP_WFE_B_STAGE2_MUX11_TOG_MUX47_MASK) + +/*! @name WFE_B_STAGE2_MUX12 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX12_MUX48_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX12_MUX48_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX12_MUX48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_MUX48_MASK) + +/*! @name WFE_B_STAGE2_MUX12_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX12_SET_MUX48_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX12_SET_MUX48_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX12_SET_MUX48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_SET_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_SET_MUX48_MASK) + +/*! @name WFE_B_STAGE2_MUX12_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX12_CLR_MUX48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_CLR_MUX48_MASK) + +/*! @name WFE_B_STAGE2_MUX12_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_SHIFT (0U) +#define PXP_WFE_B_STAGE2_MUX12_TOG_MUX48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_SHIFT)) & PXP_WFE_B_STAGE2_MUX12_TOG_MUX48_MASK) + +/*! @name WFE_B_STAGE3_MUX0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX0_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX0_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX0_MASK) +#define PXP_WFE_B_STAGE3_MUX0_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX0_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX0_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX1_MASK) +#define PXP_WFE_B_STAGE3_MUX0_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX0_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX0_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX2_MASK) +#define PXP_WFE_B_STAGE3_MUX0_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX0_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX0_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_MUX3_MASK) + +/*! @name WFE_B_STAGE3_MUX0_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX0_MASK) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX1_MASK) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX2_MASK) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX0_SET_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_SET_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_SET_MUX3_MASK) + +/*! @name WFE_B_STAGE3_MUX0_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX0_MASK) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX1_MASK) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX2_MASK) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX0_CLR_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_CLR_MUX3_MASK) + +/*! @name WFE_B_STAGE3_MUX0_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX0_MASK) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX1_MASK) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX2_MASK) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX0_TOG_MUX3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_SHIFT)) & PXP_WFE_B_STAGE3_MUX0_TOG_MUX3_MASK) + +/*! @name WFE_B_STAGE3_MUX1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX1_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX1_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX1_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX4_MASK) +#define PXP_WFE_B_STAGE3_MUX1_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX1_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX1_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX5_MASK) +#define PXP_WFE_B_STAGE3_MUX1_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX1_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX1_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX6_MASK) +#define PXP_WFE_B_STAGE3_MUX1_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX1_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX1_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_MUX7_MASK) + +/*! @name WFE_B_STAGE3_MUX1_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX4_MASK) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX5_MASK) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX6_MASK) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX1_SET_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_SET_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_SET_MUX7_MASK) + +/*! @name WFE_B_STAGE3_MUX1_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX4_MASK) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX5_MASK) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX6_MASK) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX1_CLR_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_CLR_MUX7_MASK) + +/*! @name WFE_B_STAGE3_MUX1_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX4_MASK) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX5_MASK) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX6_MASK) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX1_TOG_MUX7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_SHIFT)) & PXP_WFE_B_STAGE3_MUX1_TOG_MUX7_MASK) + +/*! @name WFE_B_STAGE3_MUX2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX2_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX2_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX2_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX8_MASK) +#define PXP_WFE_B_STAGE3_MUX2_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX2_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX2_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX9_MASK) +#define PXP_WFE_B_STAGE3_MUX2_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX2_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX2_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX10_MASK) +#define PXP_WFE_B_STAGE3_MUX2_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX2_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX2_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_MUX11_MASK) + +/*! @name WFE_B_STAGE3_MUX2_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX8_MASK) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX9_MASK) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX10_MASK) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX2_SET_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_SET_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_SET_MUX11_MASK) + +/*! @name WFE_B_STAGE3_MUX2_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX8_MASK) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX9_MASK) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX10_MASK) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX2_CLR_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_CLR_MUX11_MASK) + +/*! @name WFE_B_STAGE3_MUX2_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX8_MASK) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX9_MASK) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX10_MASK) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX2_TOG_MUX11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_SHIFT)) & PXP_WFE_B_STAGE3_MUX2_TOG_MUX11_MASK) + +/*! @name WFE_B_STAGE3_MUX3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX3_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX3_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX3_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX12_MASK) +#define PXP_WFE_B_STAGE3_MUX3_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX3_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX3_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX13_MASK) +#define PXP_WFE_B_STAGE3_MUX3_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX3_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX3_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX14_MASK) +#define PXP_WFE_B_STAGE3_MUX3_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX3_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX3_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_MUX15_MASK) + +/*! @name WFE_B_STAGE3_MUX3_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX12_MASK) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX13_MASK) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX14_MASK) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX3_SET_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_SET_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_SET_MUX15_MASK) + +/*! @name WFE_B_STAGE3_MUX3_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX12_MASK) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX13_MASK) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX14_MASK) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX3_CLR_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_CLR_MUX15_MASK) + +/*! @name WFE_B_STAGE3_MUX3_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX12_MASK) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX13_MASK) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX14_MASK) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX3_TOG_MUX15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_SHIFT)) & PXP_WFE_B_STAGE3_MUX3_TOG_MUX15_MASK) + +/*! @name WFE_B_STAGE3_MUX4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX4_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX4_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX4_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX16_MASK) +#define PXP_WFE_B_STAGE3_MUX4_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX4_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX4_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX17_MASK) +#define PXP_WFE_B_STAGE3_MUX4_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX4_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX4_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX18_MASK) +#define PXP_WFE_B_STAGE3_MUX4_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX4_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX4_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_MUX19_MASK) + +/*! @name WFE_B_STAGE3_MUX4_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX16_MASK) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX17_MASK) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX18_MASK) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX4_SET_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_SET_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_SET_MUX19_MASK) + +/*! @name WFE_B_STAGE3_MUX4_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX16_MASK) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX17_MASK) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX18_MASK) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX4_CLR_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_CLR_MUX19_MASK) + +/*! @name WFE_B_STAGE3_MUX4_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX16_MASK) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX17_MASK) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX18_MASK) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX4_TOG_MUX19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_SHIFT)) & PXP_WFE_B_STAGE3_MUX4_TOG_MUX19_MASK) + +/*! @name WFE_B_STAGE3_MUX5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX5_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX5_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX5_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX20_MASK) +#define PXP_WFE_B_STAGE3_MUX5_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX5_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX5_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX21_MASK) +#define PXP_WFE_B_STAGE3_MUX5_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX5_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX5_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX22_MASK) +#define PXP_WFE_B_STAGE3_MUX5_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX5_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX5_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_MUX23_MASK) + +/*! @name WFE_B_STAGE3_MUX5_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX20_MASK) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX21_MASK) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX22_MASK) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX5_SET_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_SET_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_SET_MUX23_MASK) + +/*! @name WFE_B_STAGE3_MUX5_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX20_MASK) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX21_MASK) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX22_MASK) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX5_CLR_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_CLR_MUX23_MASK) + +/*! @name WFE_B_STAGE3_MUX5_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX20_MASK) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX21_MASK) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX22_MASK) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX5_TOG_MUX23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_SHIFT)) & PXP_WFE_B_STAGE3_MUX5_TOG_MUX23_MASK) + +/*! @name WFE_B_STAGE3_MUX6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX6_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX6_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX6_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX24_MASK) +#define PXP_WFE_B_STAGE3_MUX6_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX6_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX6_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX25_MASK) +#define PXP_WFE_B_STAGE3_MUX6_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX6_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX6_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX26_MASK) +#define PXP_WFE_B_STAGE3_MUX6_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX6_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX6_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_MUX27_MASK) + +/*! @name WFE_B_STAGE3_MUX6_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX24_MASK) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX25_MASK) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX26_MASK) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX6_SET_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_SET_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_SET_MUX27_MASK) + +/*! @name WFE_B_STAGE3_MUX6_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX24_MASK) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX25_MASK) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX26_MASK) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX6_CLR_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_CLR_MUX27_MASK) + +/*! @name WFE_B_STAGE3_MUX6_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX24_MASK) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX25_MASK) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX26_MASK) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX6_TOG_MUX27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_SHIFT)) & PXP_WFE_B_STAGE3_MUX6_TOG_MUX27_MASK) + +/*! @name WFE_B_STAGE3_MUX7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX7_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX7_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX7_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX28_MASK) +#define PXP_WFE_B_STAGE3_MUX7_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX7_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX7_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX29_MASK) +#define PXP_WFE_B_STAGE3_MUX7_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX7_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX7_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX30_MASK) +#define PXP_WFE_B_STAGE3_MUX7_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX7_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX7_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_MUX31_MASK) + +/*! @name WFE_B_STAGE3_MUX7_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX28_MASK) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX29_MASK) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX30_MASK) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX7_SET_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_SET_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_SET_MUX31_MASK) + +/*! @name WFE_B_STAGE3_MUX7_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX28_MASK) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX29_MASK) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX30_MASK) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX7_CLR_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_CLR_MUX31_MASK) + +/*! @name WFE_B_STAGE3_MUX7_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX28_MASK) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX29_MASK) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX30_MASK) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX7_TOG_MUX31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_SHIFT)) & PXP_WFE_B_STAGE3_MUX7_TOG_MUX31_MASK) + +/*! @name WFE_B_STAGE3_MUX8 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX8_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX8_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX8_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX32_MASK) +#define PXP_WFE_B_STAGE3_MUX8_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX8_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX8_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX33_MASK) +#define PXP_WFE_B_STAGE3_MUX8_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX8_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX8_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX34_MASK) +#define PXP_WFE_B_STAGE3_MUX8_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX8_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX8_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_MUX35_MASK) + +/*! @name WFE_B_STAGE3_MUX8_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX32_MASK) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX33_MASK) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX34_MASK) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX8_SET_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_SET_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_SET_MUX35_MASK) + +/*! @name WFE_B_STAGE3_MUX8_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX32_MASK) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX33_MASK) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX34_MASK) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX8_CLR_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_CLR_MUX35_MASK) + +/*! @name WFE_B_STAGE3_MUX8_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX32_MASK) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX33_MASK) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX34_MASK) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX8_TOG_MUX35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_SHIFT)) & PXP_WFE_B_STAGE3_MUX8_TOG_MUX35_MASK) + +/*! @name WFE_B_STAGE3_MUX9 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX9_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX9_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX9_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX36_MASK) +#define PXP_WFE_B_STAGE3_MUX9_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX9_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX9_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX37_MASK) +#define PXP_WFE_B_STAGE3_MUX9_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX9_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX9_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX38_MASK) +#define PXP_WFE_B_STAGE3_MUX9_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX9_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX9_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_MUX39_MASK) + +/*! @name WFE_B_STAGE3_MUX9_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX36_MASK) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX37_MASK) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX38_MASK) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX9_SET_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_SET_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_SET_MUX39_MASK) + +/*! @name WFE_B_STAGE3_MUX9_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX36_MASK) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX37_MASK) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX38_MASK) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX9_CLR_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_CLR_MUX39_MASK) + +/*! @name WFE_B_STAGE3_MUX9_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX36_MASK) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX37_MASK) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX38_MASK) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX9_TOG_MUX39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_SHIFT)) & PXP_WFE_B_STAGE3_MUX9_TOG_MUX39_MASK) + +/*! @name WFE_B_STAGE3_MUX10 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX10_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX10_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX10_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX40_MASK) +#define PXP_WFE_B_STAGE3_MUX10_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX10_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX10_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX41_MASK) +#define PXP_WFE_B_STAGE3_MUX10_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX10_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX10_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX42_MASK) +#define PXP_WFE_B_STAGE3_MUX10_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX10_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX10_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_MUX43_MASK) + +/*! @name WFE_B_STAGE3_MUX10_SET - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX40_MASK) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX41_MASK) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX42_MASK) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX10_SET_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_SET_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_SET_MUX43_MASK) + +/*! @name WFE_B_STAGE3_MUX10_CLR - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX40_MASK) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX41_MASK) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX42_MASK) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX10_CLR_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_CLR_MUX43_MASK) + +/*! @name WFE_B_STAGE3_MUX10_TOG - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_MASK (0x3FU) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_SHIFT (0U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX40_MASK) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_MASK (0x3F00U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_SHIFT (8U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX41_MASK) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_SHIFT (16U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX42_MASK) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_SHIFT (24U) +#define PXP_WFE_B_STAGE3_MUX10_TOG_MUX43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_SHIFT)) & PXP_WFE_B_STAGE3_MUX10_TOG_MUX43_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG1_5X8_OUT0_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT0_7_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG1_5X8_OUT1_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_MASK (0xFFU) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_MASK (0xFF00U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_MASK (0xFF0000U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_MASK (0xFF000000U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_5X8_OUT1_7_LUTOUT31_MASK) + +/*! @name WFE_B_STAGE1_5X8_MASKS_0 - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x8 LUT. */ +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_MASK (0x1FU) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_SHIFT (0U) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_SHIFT)) & PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK0_MASK) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_MASK (0x1F00U) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_SHIFT (8U) +#define PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_SHIFT)) & PXP_WFE_B_STAGE1_5X8_MASKS_0_MASK1_MASK) + +/*! @name WFE_B_STG1_5X1_OUT0 - This register defines the output values (new flag) for the 5x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_5X1_OUT0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_5X1_MASKS - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x1 LUT. */ +#define PXP_WFE_B_STG1_5X1_MASKS_MASK0_MASK (0x1FU) +#define PXP_WFE_B_STG1_5X1_MASKS_MASK0_SHIFT (0U) +#define PXP_WFE_B_STG1_5X1_MASKS_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_5X1_MASKS_MASK0_SHIFT)) & PXP_WFE_B_STG1_5X1_MASKS_MASK0_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT0_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT0_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT1_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT1_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT2_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT2_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT3_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT3_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG1_8X1_OUT4_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 1. */ +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG1_8X1_OUT4_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG2_5X6_OUT0_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT0_7_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG2_5X6_OUT1_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT1_7_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG2_5X6_OUT2_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT2_7_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_0 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_0_LUTOUT3_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_1 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_1_LUTOUT7_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_2 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_2_LUTOUT11_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_3 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_3_LUTOUT15_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_4 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_4_LUTOUT19_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_5 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_5_LUTOUT23_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_6 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_6_LUTOUT27_MASK) + +/*! @name WFE_B_STG2_5X6_OUT3_7 - This register defines the control bits for the pxp wfe sub-block */ +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_MASK (0x3FU) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_SHIFT (0U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_MASK (0x3F00U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_SHIFT (8U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_MASK (0x3F0000U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_SHIFT (16U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_MASK (0x3F000000U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_SHIFT (24U) +#define PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X6_OUT3_7_LUTOUT31_MASK) + +/*! @name WFE_B_STAGE2_5X6_MASKS_0 - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x6 LUT. */ +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_MASK (0x1FU) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK0_MASK) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_MASK (0x1F00U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK1_MASK) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_MASK (0x1F0000U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK2_MASK) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_MASK (0x1F000000U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_SHIFT)) & PXP_WFE_B_STAGE2_5X6_MASKS_0_MASK3_MASK) + +/*! @name WFE_B_STAGE2_5X6_ADDR_0 - Each Address specifies the MUX position in the MUX array. There is one MUXADDR per 5x6 LUT. */ +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_MASK (0x3FU) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_SHIFT (0U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR0_MASK) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_MASK (0x3F00U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_SHIFT (8U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR1_MASK) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_MASK (0x3F0000U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_SHIFT (16U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR2_MASK) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_MASK (0x3F000000U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_SHIFT (24U) +#define PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_SHIFT)) & PXP_WFE_B_STAGE2_5X6_ADDR_0_MUXADDR3_MASK) + +/*! @name WFE_B_STG2_5X1_OUT0 - This register defines the output values (new flag) for the 5x1 LUTs in stage 2. */ +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT3_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT7_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT11_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT15_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT19_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT23_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT27_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT0_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X1_OUT1 - This register defines the output values (new flag) for the 5x1 LUTs in stage 2. */ +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT3_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT7_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT11_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT15_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT19_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT23_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT27_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT1_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X1_OUT2 - This register defines the output values (new flag) for the 5x1 LUTs in stage 2. */ +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT3_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT7_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT11_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT15_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT19_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT23_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT27_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT2_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X1_OUT3 - This register defines the output values (new flag) for the 5x1 LUTs in stage 2. */ +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT0_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT1_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT2_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT3_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT4_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT5_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT6_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT7_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT8_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT9_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT10_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT11_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT12_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT13_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT14_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT15_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT16_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT17_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT18_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT19_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT20_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT21_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT22_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT23_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT24_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT25_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT26_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT27_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT28_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT29_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT30_MASK) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_SHIFT)) & PXP_WFE_B_STG2_5X1_OUT3_LUTOUT31_MASK) + +/*! @name WFE_B_STG2_5X1_MASKS - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 5x1 LUT. */ +#define PXP_WFE_B_STG2_5X1_MASKS_MASK0_MASK (0x1FU) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK0_SHIFT (0U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK0_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK0_MASK) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK1_MASK (0x1F00U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK1_SHIFT (8U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK1_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK1_MASK) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK2_MASK (0x1F0000U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK2_SHIFT (16U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK2_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK2_MASK) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK3_MASK (0x1F000000U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK3_SHIFT (24U) +#define PXP_WFE_B_STG2_5X1_MASKS_MASK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG2_5X1_MASKS_MASK3_SHIFT)) & PXP_WFE_B_STG2_5X1_MASKS_MASK3_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT0_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT0_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT1_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT1_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT2_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT2_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_0 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT0_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT1_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT2_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT3_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT4_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT5_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT6_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT7_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT8_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT9_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT10_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT11_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT12_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT13_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT14_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT15_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT16_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT17_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT18_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT19_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT20_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT21_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT22_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT23_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT24_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT25_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT26_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT27_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT28_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT29_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT30_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_0_LUTOUT31_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_1 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT32_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT33_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT34_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT35_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT36_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT37_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT38_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT39_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT40_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT41_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT42_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT43_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT44_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT45_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT46_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT47_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT48_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT49_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT50_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT51_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT52_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT53_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT54_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT55_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT56_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT57_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT58_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT59_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT60_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT61_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT62_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_1_LUTOUT63_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_2 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT64_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT65_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT66_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT67_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT68_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT69_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT70_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT71_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT72_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT73_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT74_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT75_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT76_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT77_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT78_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT79_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT80_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT81_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT82_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT83_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT84_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT85_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT86_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT87_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT88_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT89_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT90_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT91_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT92_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT93_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT94_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_2_LUTOUT95_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_3 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT96_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT97_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT98_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT99_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT100_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT101_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT102_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT103_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT104_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT105_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT106_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT107_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT108_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT109_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT110_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT111_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT112_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT113_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT114_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT115_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT116_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT117_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT118_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT119_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT120_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT121_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT122_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT123_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT124_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT125_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT126_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_3_LUTOUT127_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_4 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT128_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT129_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT130_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT131_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT132_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT133_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT134_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT135_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT136_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT137_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT138_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT139_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT140_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT141_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT142_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT143_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT144_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT145_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT146_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT147_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT148_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT149_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT150_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT151_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT152_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT153_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT154_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT155_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT156_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT157_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT158_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_4_LUTOUT159_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_5 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT160_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT161_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT162_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT163_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT164_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT165_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT166_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT167_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT168_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT169_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT170_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT171_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT172_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT173_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT174_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT175_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT176_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT177_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT178_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT179_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT180_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT181_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT182_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT183_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT184_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT185_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT186_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT187_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT188_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT189_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT190_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_5_LUTOUT191_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_6 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT192_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT193_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT194_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT195_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT196_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT197_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT198_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT199_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT200_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT201_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT202_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT203_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT204_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT205_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT206_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT207_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT208_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT209_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT210_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT211_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT212_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT213_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT214_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT215_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT216_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT217_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT218_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT219_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT220_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT221_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT222_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_6_LUTOUT223_MASK) + +/*! @name WFE_B_STG3_F8X1_OUT3_7 - This register defines the output values (new flag) for the 8x1 LUTs in stage 3. */ +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_MASK (0x1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT224_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_MASK (0x2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_SHIFT (1U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT225_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_MASK (0x4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_SHIFT (2U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT226_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_MASK (0x8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_SHIFT (3U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT227_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_MASK (0x10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_SHIFT (4U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT228_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_MASK (0x20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_SHIFT (5U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT229_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_MASK (0x40U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_SHIFT (6U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT230_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_MASK (0x80U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_SHIFT (7U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT231_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_MASK (0x100U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT232_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_MASK (0x200U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_SHIFT (9U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT233_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_MASK (0x400U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_SHIFT (10U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT234_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_MASK (0x800U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_SHIFT (11U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT235_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_MASK (0x1000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_SHIFT (12U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT236_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_MASK (0x2000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_SHIFT (13U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT237_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_MASK (0x4000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_SHIFT (14U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT238_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_MASK (0x8000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_SHIFT (15U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT239_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_MASK (0x10000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT240_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_MASK (0x20000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_SHIFT (17U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT241_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_MASK (0x40000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_SHIFT (18U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT242_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_MASK (0x80000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_SHIFT (19U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT243_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_MASK (0x100000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_SHIFT (20U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT244_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_MASK (0x200000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_SHIFT (21U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT245_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_MASK (0x400000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_SHIFT (22U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT246_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_MASK (0x800000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_SHIFT (23U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT247_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_MASK (0x1000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT248_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_MASK (0x2000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_SHIFT (25U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT249_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_MASK (0x4000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_SHIFT (26U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT250_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_MASK (0x8000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_SHIFT (27U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT251_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_MASK (0x10000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_SHIFT (28U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT252_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_MASK (0x20000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_SHIFT (29U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT253_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_MASK (0x40000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_SHIFT (30U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT254_MASK) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_MASK (0x80000000U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_SHIFT (31U) +#define PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_SHIFT)) & PXP_WFE_B_STG3_F8X1_OUT3_7_LUTOUT255_MASK) + +/*! @name WFE_B_STG3_F8X1_MASKS - Each set mask bit enables one of the corresponding flag input bits. There is one mask per 8x1 LUT. */ +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK0_MASK (0xFFU) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK0_SHIFT (0U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK0_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK0_MASK) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK1_MASK (0xFF00U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK1_SHIFT (8U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK1_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK1_MASK) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK2_MASK (0xFF0000U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK2_SHIFT (16U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK2_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK2_MASK) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK3_MASK (0xFF000000U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK3_SHIFT (24U) +#define PXP_WFE_B_STG3_F8X1_MASKS_MASK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_WFE_B_STG3_F8X1_MASKS_MASK3_SHIFT)) & PXP_WFE_B_STG3_F8X1_MASKS_MASK3_MASK) + +/*! @name ALU_B_CTRL - This register defines the control bits for the pxp alu sub-block. */ +#define PXP_ALU_B_CTRL_ENABLE_MASK (0x1U) +#define PXP_ALU_B_CTRL_ENABLE_SHIFT (0U) +#define PXP_ALU_B_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_ENABLE_MASK) +#define PXP_ALU_B_CTRL_START_MASK (0x10U) +#define PXP_ALU_B_CTRL_START_SHIFT (4U) +#define PXP_ALU_B_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_START_SHIFT)) & PXP_ALU_B_CTRL_START_MASK) +#define PXP_ALU_B_CTRL_SW_RESET_MASK (0x100U) +#define PXP_ALU_B_CTRL_SW_RESET_SHIFT (8U) +#define PXP_ALU_B_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_SW_RESET_MASK) +#define PXP_ALU_B_CTRL_BYPASS_MASK (0x1000U) +#define PXP_ALU_B_CTRL_BYPASS_SHIFT (12U) +#define PXP_ALU_B_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_BYPASS_MASK) +#define PXP_ALU_B_CTRL_DONE_IRQ_FLAG_MASK (0x10000U) +#define PXP_ALU_B_CTRL_DONE_IRQ_FLAG_SHIFT (16U) +#define PXP_ALU_B_CTRL_DONE_IRQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_DONE_IRQ_FLAG_MASK) +#define PXP_ALU_B_CTRL_DONE_IRQ_EN_MASK (0x100000U) +#define PXP_ALU_B_CTRL_DONE_IRQ_EN_SHIFT (20U) +#define PXP_ALU_B_CTRL_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_DONE_IRQ_EN_MASK) +#define PXP_ALU_B_CTRL_DONE_MASK (0x10000000U) +#define PXP_ALU_B_CTRL_DONE_SHIFT (28U) +#define PXP_ALU_B_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_DONE_SHIFT)) & PXP_ALU_B_CTRL_DONE_MASK) + +/*! @name ALU_B_CTRL_SET - This register defines the control bits for the pxp alu sub-block. */ +#define PXP_ALU_B_CTRL_SET_ENABLE_MASK (0x1U) +#define PXP_ALU_B_CTRL_SET_ENABLE_SHIFT (0U) +#define PXP_ALU_B_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_SET_ENABLE_MASK) +#define PXP_ALU_B_CTRL_SET_START_MASK (0x10U) +#define PXP_ALU_B_CTRL_SET_START_SHIFT (4U) +#define PXP_ALU_B_CTRL_SET_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_START_SHIFT)) & PXP_ALU_B_CTRL_SET_START_MASK) +#define PXP_ALU_B_CTRL_SET_SW_RESET_MASK (0x100U) +#define PXP_ALU_B_CTRL_SET_SW_RESET_SHIFT (8U) +#define PXP_ALU_B_CTRL_SET_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_SET_SW_RESET_MASK) +#define PXP_ALU_B_CTRL_SET_BYPASS_MASK (0x1000U) +#define PXP_ALU_B_CTRL_SET_BYPASS_SHIFT (12U) +#define PXP_ALU_B_CTRL_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_SET_BYPASS_MASK) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_MASK (0x10000U) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_SHIFT (16U) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_SET_DONE_IRQ_FLAG_MASK) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_MASK (0x100000U) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_SHIFT (20U) +#define PXP_ALU_B_CTRL_SET_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_SET_DONE_IRQ_EN_MASK) +#define PXP_ALU_B_CTRL_SET_DONE_MASK (0x10000000U) +#define PXP_ALU_B_CTRL_SET_DONE_SHIFT (28U) +#define PXP_ALU_B_CTRL_SET_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_SET_DONE_SHIFT)) & PXP_ALU_B_CTRL_SET_DONE_MASK) + +/*! @name ALU_B_CTRL_CLR - This register defines the control bits for the pxp alu sub-block. */ +#define PXP_ALU_B_CTRL_CLR_ENABLE_MASK (0x1U) +#define PXP_ALU_B_CTRL_CLR_ENABLE_SHIFT (0U) +#define PXP_ALU_B_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_CLR_ENABLE_MASK) +#define PXP_ALU_B_CTRL_CLR_START_MASK (0x10U) +#define PXP_ALU_B_CTRL_CLR_START_SHIFT (4U) +#define PXP_ALU_B_CTRL_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_START_SHIFT)) & PXP_ALU_B_CTRL_CLR_START_MASK) +#define PXP_ALU_B_CTRL_CLR_SW_RESET_MASK (0x100U) +#define PXP_ALU_B_CTRL_CLR_SW_RESET_SHIFT (8U) +#define PXP_ALU_B_CTRL_CLR_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_CLR_SW_RESET_MASK) +#define PXP_ALU_B_CTRL_CLR_BYPASS_MASK (0x1000U) +#define PXP_ALU_B_CTRL_CLR_BYPASS_SHIFT (12U) +#define PXP_ALU_B_CTRL_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_CLR_BYPASS_MASK) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_MASK (0x10000U) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_SHIFT (16U) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_CLR_DONE_IRQ_FLAG_MASK) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_MASK (0x100000U) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_SHIFT (20U) +#define PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_CLR_DONE_IRQ_EN_MASK) +#define PXP_ALU_B_CTRL_CLR_DONE_MASK (0x10000000U) +#define PXP_ALU_B_CTRL_CLR_DONE_SHIFT (28U) +#define PXP_ALU_B_CTRL_CLR_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_CLR_DONE_SHIFT)) & PXP_ALU_B_CTRL_CLR_DONE_MASK) + +/*! @name ALU_B_CTRL_TOG - This register defines the control bits for the pxp alu sub-block. */ +#define PXP_ALU_B_CTRL_TOG_ENABLE_MASK (0x1U) +#define PXP_ALU_B_CTRL_TOG_ENABLE_SHIFT (0U) +#define PXP_ALU_B_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_ENABLE_SHIFT)) & PXP_ALU_B_CTRL_TOG_ENABLE_MASK) +#define PXP_ALU_B_CTRL_TOG_START_MASK (0x10U) +#define PXP_ALU_B_CTRL_TOG_START_SHIFT (4U) +#define PXP_ALU_B_CTRL_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_START_SHIFT)) & PXP_ALU_B_CTRL_TOG_START_MASK) +#define PXP_ALU_B_CTRL_TOG_SW_RESET_MASK (0x100U) +#define PXP_ALU_B_CTRL_TOG_SW_RESET_SHIFT (8U) +#define PXP_ALU_B_CTRL_TOG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_SW_RESET_SHIFT)) & PXP_ALU_B_CTRL_TOG_SW_RESET_MASK) +#define PXP_ALU_B_CTRL_TOG_BYPASS_MASK (0x1000U) +#define PXP_ALU_B_CTRL_TOG_BYPASS_SHIFT (12U) +#define PXP_ALU_B_CTRL_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_BYPASS_SHIFT)) & PXP_ALU_B_CTRL_TOG_BYPASS_MASK) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_MASK (0x10000U) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_SHIFT (16U) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_SHIFT)) & PXP_ALU_B_CTRL_TOG_DONE_IRQ_FLAG_MASK) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_MASK (0x100000U) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_SHIFT (20U) +#define PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_SHIFT)) & PXP_ALU_B_CTRL_TOG_DONE_IRQ_EN_MASK) +#define PXP_ALU_B_CTRL_TOG_DONE_MASK (0x10000000U) +#define PXP_ALU_B_CTRL_TOG_DONE_SHIFT (28U) +#define PXP_ALU_B_CTRL_TOG_DONE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CTRL_TOG_DONE_SHIFT)) & PXP_ALU_B_CTRL_TOG_DONE_MASK) + +/*! @name ALU_B_BUF_SIZE - This register defines the size of the buffer to be processed by the alu engine. */ +#define PXP_ALU_B_BUF_SIZE_BUF_WIDTH_MASK (0xFFFU) +#define PXP_ALU_B_BUF_SIZE_BUF_WIDTH_SHIFT (0U) +#define PXP_ALU_B_BUF_SIZE_BUF_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_BUF_SIZE_BUF_WIDTH_SHIFT)) & PXP_ALU_B_BUF_SIZE_BUF_WIDTH_MASK) +#define PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_MASK (0xFFF0000U) +#define PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_SHIFT (16U) +#define PXP_ALU_B_BUF_SIZE_BUF_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_SHIFT)) & PXP_ALU_B_BUF_SIZE_BUF_HEIGHT_MASK) + +/*! @name ALU_B_INST_ENTRY - This register defines the Entry Address for the Instruction Memory of the ALU. */ +#define PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_MASK (0xFFFFU) +#define PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_SHIFT (0U) +#define PXP_ALU_B_INST_ENTRY_ENTRY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_SHIFT)) & PXP_ALU_B_INST_ENTRY_ENTRY_ADDR_MASK) + +/*! @name ALU_B_PARAM - This register defines the parameter used by SW running on ALU. */ +#define PXP_ALU_B_PARAM_PARAM0_MASK (0xFFU) +#define PXP_ALU_B_PARAM_PARAM0_SHIFT (0U) +#define PXP_ALU_B_PARAM_PARAM0(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_PARAM_PARAM0_SHIFT)) & PXP_ALU_B_PARAM_PARAM0_MASK) +#define PXP_ALU_B_PARAM_PARAM1_MASK (0xFF00U) +#define PXP_ALU_B_PARAM_PARAM1_SHIFT (8U) +#define PXP_ALU_B_PARAM_PARAM1(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_PARAM_PARAM1_SHIFT)) & PXP_ALU_B_PARAM_PARAM1_MASK) + +/*! @name ALU_B_CONFIG - This register defines the hw configuration options for the alu core. */ +#define PXP_ALU_B_CONFIG_BUF_ADDR_MASK (0xFFFFFFFFU) +#define PXP_ALU_B_CONFIG_BUF_ADDR_SHIFT (0U) +#define PXP_ALU_B_CONFIG_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_CONFIG_BUF_ADDR_SHIFT)) & PXP_ALU_B_CONFIG_BUF_ADDR_MASK) + +/*! @name ALU_B_LUT_CONFIG - This register defines the hw configuration options for the LUT */ +#define PXP_ALU_B_LUT_CONFIG_EN_MASK (0x1U) +#define PXP_ALU_B_LUT_CONFIG_EN_SHIFT (0U) +#define PXP_ALU_B_LUT_CONFIG_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_EN_MASK) +#define PXP_ALU_B_LUT_CONFIG_MODE_MASK (0x30U) +#define PXP_ALU_B_LUT_CONFIG_MODE_SHIFT (4U) +#define PXP_ALU_B_LUT_CONFIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_MODE_MASK) + +/*! @name ALU_B_LUT_CONFIG_SET - This register defines the hw configuration options for the LUT */ +#define PXP_ALU_B_LUT_CONFIG_SET_EN_MASK (0x1U) +#define PXP_ALU_B_LUT_CONFIG_SET_EN_SHIFT (0U) +#define PXP_ALU_B_LUT_CONFIG_SET_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_SET_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_SET_EN_MASK) +#define PXP_ALU_B_LUT_CONFIG_SET_MODE_MASK (0x30U) +#define PXP_ALU_B_LUT_CONFIG_SET_MODE_SHIFT (4U) +#define PXP_ALU_B_LUT_CONFIG_SET_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_SET_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_SET_MODE_MASK) + +/*! @name ALU_B_LUT_CONFIG_CLR - This register defines the hw configuration options for the LUT */ +#define PXP_ALU_B_LUT_CONFIG_CLR_EN_MASK (0x1U) +#define PXP_ALU_B_LUT_CONFIG_CLR_EN_SHIFT (0U) +#define PXP_ALU_B_LUT_CONFIG_CLR_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_CLR_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_CLR_EN_MASK) +#define PXP_ALU_B_LUT_CONFIG_CLR_MODE_MASK (0x30U) +#define PXP_ALU_B_LUT_CONFIG_CLR_MODE_SHIFT (4U) +#define PXP_ALU_B_LUT_CONFIG_CLR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_CLR_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_CLR_MODE_MASK) + +/*! @name ALU_B_LUT_CONFIG_TOG - This register defines the hw configuration options for the LUT */ +#define PXP_ALU_B_LUT_CONFIG_TOG_EN_MASK (0x1U) +#define PXP_ALU_B_LUT_CONFIG_TOG_EN_SHIFT (0U) +#define PXP_ALU_B_LUT_CONFIG_TOG_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_TOG_EN_SHIFT)) & PXP_ALU_B_LUT_CONFIG_TOG_EN_MASK) +#define PXP_ALU_B_LUT_CONFIG_TOG_MODE_MASK (0x30U) +#define PXP_ALU_B_LUT_CONFIG_TOG_MODE_SHIFT (4U) +#define PXP_ALU_B_LUT_CONFIG_TOG_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_CONFIG_TOG_MODE_SHIFT)) & PXP_ALU_B_LUT_CONFIG_TOG_MODE_MASK) + +/*! @name ALU_B_LUT_DATA0 - This register defines the lower 32-bit data for the LUT */ +#define PXP_ALU_B_LUT_DATA0_LUT_DATA_L_MASK (0xFFFFFFFFU) +#define PXP_ALU_B_LUT_DATA0_LUT_DATA_L_SHIFT (0U) +#define PXP_ALU_B_LUT_DATA0_LUT_DATA_L(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_DATA0_LUT_DATA_L_SHIFT)) & PXP_ALU_B_LUT_DATA0_LUT_DATA_L_MASK) + +/*! @name ALU_B_LUT_DATA1 - This register defines the higher 32-bit data for the LUT */ +#define PXP_ALU_B_LUT_DATA1_LUT_DATA_H_MASK (0xFFFFFFFFU) +#define PXP_ALU_B_LUT_DATA1_LUT_DATA_H_SHIFT (0U) +#define PXP_ALU_B_LUT_DATA1_LUT_DATA_H(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_LUT_DATA1_LUT_DATA_H_SHIFT)) & PXP_ALU_B_LUT_DATA1_LUT_DATA_H_MASK) + +/*! @name ALU_B_DBG - This register is used for debugging alu block */ +#define PXP_ALU_B_DBG_DEBUG_VALUE_MASK (0xFFFFFFU) +#define PXP_ALU_B_DBG_DEBUG_VALUE_SHIFT (0U) +#define PXP_ALU_B_DBG_DEBUG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_DBG_DEBUG_VALUE_SHIFT)) & PXP_ALU_B_DBG_DEBUG_VALUE_MASK) +#define PXP_ALU_B_DBG_DEBUG_SEL_MASK (0xFF000000U) +#define PXP_ALU_B_DBG_DEBUG_SEL_SHIFT (24U) +#define PXP_ALU_B_DBG_DEBUG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_ALU_B_DBG_DEBUG_SEL_SHIFT)) & PXP_ALU_B_DBG_DEBUG_SEL_MASK) + +/*! @name HIST_A_CTRL - Histogram Control Register. */ +#define PXP_HIST_A_CTRL_ENABLE_MASK (0x1U) +#define PXP_HIST_A_CTRL_ENABLE_SHIFT (0U) +#define PXP_HIST_A_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_ENABLE_SHIFT)) & PXP_HIST_A_CTRL_ENABLE_MASK) +#define PXP_HIST_A_CTRL_CLEAR_MASK (0x10U) +#define PXP_HIST_A_CTRL_CLEAR_SHIFT (4U) +#define PXP_HIST_A_CTRL_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_CLEAR_SHIFT)) & PXP_HIST_A_CTRL_CLEAR_MASK) +#define PXP_HIST_A_CTRL_STATUS_MASK (0x1F00U) +#define PXP_HIST_A_CTRL_STATUS_SHIFT (8U) +#define PXP_HIST_A_CTRL_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_STATUS_SHIFT)) & PXP_HIST_A_CTRL_STATUS_MASK) +#define PXP_HIST_A_CTRL_PIXEL_OFFSET_MASK (0x7F0000U) +#define PXP_HIST_A_CTRL_PIXEL_OFFSET_SHIFT (16U) +#define PXP_HIST_A_CTRL_PIXEL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_PIXEL_OFFSET_SHIFT)) & PXP_HIST_A_CTRL_PIXEL_OFFSET_MASK) +#define PXP_HIST_A_CTRL_PIXEL_WIDTH_MASK (0x7000000U) +#define PXP_HIST_A_CTRL_PIXEL_WIDTH_SHIFT (24U) +#define PXP_HIST_A_CTRL_PIXEL_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_CTRL_PIXEL_WIDTH_SHIFT)) & PXP_HIST_A_CTRL_PIXEL_WIDTH_MASK) + +/*! @name HIST_A_MASK - Histogram Pixel Mask Register. */ +#define PXP_HIST_A_MASK_MASK_EN_MASK (0x1U) +#define PXP_HIST_A_MASK_MASK_EN_SHIFT (0U) +#define PXP_HIST_A_MASK_MASK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_EN_SHIFT)) & PXP_HIST_A_MASK_MASK_EN_MASK) +#define PXP_HIST_A_MASK_MASK_MODE_MASK (0x30U) +#define PXP_HIST_A_MASK_MASK_MODE_SHIFT (4U) +#define PXP_HIST_A_MASK_MASK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_MODE_SHIFT)) & PXP_HIST_A_MASK_MASK_MODE_MASK) +#define PXP_HIST_A_MASK_MASK_OFFSET_MASK (0x1FC0U) +#define PXP_HIST_A_MASK_MASK_OFFSET_SHIFT (6U) +#define PXP_HIST_A_MASK_MASK_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_OFFSET_SHIFT)) & PXP_HIST_A_MASK_MASK_OFFSET_MASK) +#define PXP_HIST_A_MASK_MASK_WIDTH_MASK (0xE000U) +#define PXP_HIST_A_MASK_MASK_WIDTH_SHIFT (13U) +#define PXP_HIST_A_MASK_MASK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_WIDTH_SHIFT)) & PXP_HIST_A_MASK_MASK_WIDTH_MASK) +#define PXP_HIST_A_MASK_MASK_VALUE0_MASK (0xFF0000U) +#define PXP_HIST_A_MASK_MASK_VALUE0_SHIFT (16U) +#define PXP_HIST_A_MASK_MASK_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_VALUE0_SHIFT)) & PXP_HIST_A_MASK_MASK_VALUE0_MASK) +#define PXP_HIST_A_MASK_MASK_VALUE1_MASK (0xFF000000U) +#define PXP_HIST_A_MASK_MASK_VALUE1_SHIFT (24U) +#define PXP_HIST_A_MASK_MASK_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_MASK_MASK_VALUE1_SHIFT)) & PXP_HIST_A_MASK_MASK_VALUE1_MASK) + +/*! @name HIST_A_BUF_SIZE - Histogram Pixel Buffer Size Register. */ +#define PXP_HIST_A_BUF_SIZE_WIDTH_MASK (0xFFFU) +#define PXP_HIST_A_BUF_SIZE_WIDTH_SHIFT (0U) +#define PXP_HIST_A_BUF_SIZE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_BUF_SIZE_WIDTH_SHIFT)) & PXP_HIST_A_BUF_SIZE_WIDTH_MASK) +#define PXP_HIST_A_BUF_SIZE_HEIGHT_MASK (0xFFF0000U) +#define PXP_HIST_A_BUF_SIZE_HEIGHT_SHIFT (16U) +#define PXP_HIST_A_BUF_SIZE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_BUF_SIZE_HEIGHT_SHIFT)) & PXP_HIST_A_BUF_SIZE_HEIGHT_MASK) + +/*! @name HIST_A_TOTAL_PIXEL - Total Number of Pixels Used by Histogram Engine. */ +#define PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_MASK (0xFFFFFFU) +#define PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT (0U) +#define PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT)) & PXP_HIST_A_TOTAL_PIXEL_TOTAL_PIXEL_MASK) + +/*! @name HIST_A_ACTIVE_AREA_X - The X Coordinate Offset for Active Area. */ +#define PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_MASK (0xFFFU) +#define PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT (0U) +#define PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_X_MIN_X_OFFSET_MASK) +#define PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_MASK (0xFFF0000U) +#define PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT (16U) +#define PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_X_MAX_X_OFFSET_MASK) + +/*! @name HIST_A_ACTIVE_AREA_Y - The Y Coordinate Offset for Active Area. */ +#define PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK (0xFFFU) +#define PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT (0U) +#define PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK) +#define PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK (0xFFF0000U) +#define PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT (16U) +#define PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT)) & PXP_HIST_A_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK) + +/*! @name HIST_A_RAW_STAT0 - Histogram Result Based on RAW Pixel Value. */ +#define PXP_HIST_A_RAW_STAT0_STAT0_MASK (0xFFFFFFFFU) +#define PXP_HIST_A_RAW_STAT0_STAT0_SHIFT (0U) +#define PXP_HIST_A_RAW_STAT0_STAT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_RAW_STAT0_STAT0_SHIFT)) & PXP_HIST_A_RAW_STAT0_STAT0_MASK) + +/*! @name HIST_A_RAW_STAT1 - Histogram Result Based on RAW Pixel Value. */ +#define PXP_HIST_A_RAW_STAT1_STAT1_MASK (0xFFFFFFFFU) +#define PXP_HIST_A_RAW_STAT1_STAT1_SHIFT (0U) +#define PXP_HIST_A_RAW_STAT1_STAT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_A_RAW_STAT1_STAT1_SHIFT)) & PXP_HIST_A_RAW_STAT1_STAT1_MASK) + +/*! @name HIST_B_CTRL - Histogram Control Register. */ +#define PXP_HIST_B_CTRL_ENABLE_MASK (0x1U) +#define PXP_HIST_B_CTRL_ENABLE_SHIFT (0U) +#define PXP_HIST_B_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_ENABLE_SHIFT)) & PXP_HIST_B_CTRL_ENABLE_MASK) +#define PXP_HIST_B_CTRL_CLEAR_MASK (0x10U) +#define PXP_HIST_B_CTRL_CLEAR_SHIFT (4U) +#define PXP_HIST_B_CTRL_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_CLEAR_SHIFT)) & PXP_HIST_B_CTRL_CLEAR_MASK) +#define PXP_HIST_B_CTRL_STATUS_MASK (0x1F00U) +#define PXP_HIST_B_CTRL_STATUS_SHIFT (8U) +#define PXP_HIST_B_CTRL_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_STATUS_SHIFT)) & PXP_HIST_B_CTRL_STATUS_MASK) +#define PXP_HIST_B_CTRL_PIXEL_OFFSET_MASK (0x7F0000U) +#define PXP_HIST_B_CTRL_PIXEL_OFFSET_SHIFT (16U) +#define PXP_HIST_B_CTRL_PIXEL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_PIXEL_OFFSET_SHIFT)) & PXP_HIST_B_CTRL_PIXEL_OFFSET_MASK) +#define PXP_HIST_B_CTRL_PIXEL_WIDTH_MASK (0x7000000U) +#define PXP_HIST_B_CTRL_PIXEL_WIDTH_SHIFT (24U) +#define PXP_HIST_B_CTRL_PIXEL_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_CTRL_PIXEL_WIDTH_SHIFT)) & PXP_HIST_B_CTRL_PIXEL_WIDTH_MASK) + +/*! @name HIST_B_MASK - Histogram Pixel Mask Register. */ +#define PXP_HIST_B_MASK_MASK_EN_MASK (0x1U) +#define PXP_HIST_B_MASK_MASK_EN_SHIFT (0U) +#define PXP_HIST_B_MASK_MASK_EN(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_EN_SHIFT)) & PXP_HIST_B_MASK_MASK_EN_MASK) +#define PXP_HIST_B_MASK_MASK_MODE_MASK (0x30U) +#define PXP_HIST_B_MASK_MASK_MODE_SHIFT (4U) +#define PXP_HIST_B_MASK_MASK_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_MODE_SHIFT)) & PXP_HIST_B_MASK_MASK_MODE_MASK) +#define PXP_HIST_B_MASK_MASK_OFFSET_MASK (0x1FC0U) +#define PXP_HIST_B_MASK_MASK_OFFSET_SHIFT (6U) +#define PXP_HIST_B_MASK_MASK_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_OFFSET_SHIFT)) & PXP_HIST_B_MASK_MASK_OFFSET_MASK) +#define PXP_HIST_B_MASK_MASK_WIDTH_MASK (0xE000U) +#define PXP_HIST_B_MASK_MASK_WIDTH_SHIFT (13U) +#define PXP_HIST_B_MASK_MASK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_WIDTH_SHIFT)) & PXP_HIST_B_MASK_MASK_WIDTH_MASK) +#define PXP_HIST_B_MASK_MASK_VALUE0_MASK (0xFF0000U) +#define PXP_HIST_B_MASK_MASK_VALUE0_SHIFT (16U) +#define PXP_HIST_B_MASK_MASK_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_VALUE0_SHIFT)) & PXP_HIST_B_MASK_MASK_VALUE0_MASK) +#define PXP_HIST_B_MASK_MASK_VALUE1_MASK (0xFF000000U) +#define PXP_HIST_B_MASK_MASK_VALUE1_SHIFT (24U) +#define PXP_HIST_B_MASK_MASK_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_MASK_MASK_VALUE1_SHIFT)) & PXP_HIST_B_MASK_MASK_VALUE1_MASK) + +/*! @name HIST_B_BUF_SIZE - Histogram Pixel Buffer Size Register. */ +#define PXP_HIST_B_BUF_SIZE_WIDTH_MASK (0xFFFU) +#define PXP_HIST_B_BUF_SIZE_WIDTH_SHIFT (0U) +#define PXP_HIST_B_BUF_SIZE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_BUF_SIZE_WIDTH_SHIFT)) & PXP_HIST_B_BUF_SIZE_WIDTH_MASK) +#define PXP_HIST_B_BUF_SIZE_HEIGHT_MASK (0xFFF0000U) +#define PXP_HIST_B_BUF_SIZE_HEIGHT_SHIFT (16U) +#define PXP_HIST_B_BUF_SIZE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_BUF_SIZE_HEIGHT_SHIFT)) & PXP_HIST_B_BUF_SIZE_HEIGHT_MASK) + +/*! @name HIST_B_TOTAL_PIXEL - Total Number of Pixels Used by Histogram Engine. */ +#define PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_MASK (0xFFFFFFU) +#define PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT (0U) +#define PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_SHIFT)) & PXP_HIST_B_TOTAL_PIXEL_TOTAL_PIXEL_MASK) + +/*! @name HIST_B_ACTIVE_AREA_X - The X Coordinate Offset for Active Area. */ +#define PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_MASK (0xFFFU) +#define PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT (0U) +#define PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_X_MIN_X_OFFSET_MASK) +#define PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_MASK (0xFFF0000U) +#define PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT (16U) +#define PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_X_MAX_X_OFFSET_MASK) + +/*! @name HIST_B_ACTIVE_AREA_Y - The Y Coordinate Offset for Active Area. */ +#define PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK (0xFFFU) +#define PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT (0U) +#define PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_Y_MIN_Y_OFFSET_MASK) +#define PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK (0xFFF0000U) +#define PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT (16U) +#define PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_SHIFT)) & PXP_HIST_B_ACTIVE_AREA_Y_MAX_Y_OFFSET_MASK) + +/*! @name HIST_B_RAW_STAT0 - Histogram Result Based on RAW Pixel Value. */ +#define PXP_HIST_B_RAW_STAT0_STAT0_MASK (0xFFFFFFFFU) +#define PXP_HIST_B_RAW_STAT0_STAT0_SHIFT (0U) +#define PXP_HIST_B_RAW_STAT0_STAT0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_RAW_STAT0_STAT0_SHIFT)) & PXP_HIST_B_RAW_STAT0_STAT0_MASK) + +/*! @name HIST_B_RAW_STAT1 - Histogram Result Based on RAW Pixel Value. */ +#define PXP_HIST_B_RAW_STAT1_STAT1_MASK (0xFFFFFFFFU) +#define PXP_HIST_B_RAW_STAT1_STAT1_SHIFT (0U) +#define PXP_HIST_B_RAW_STAT1_STAT1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST_B_RAW_STAT1_STAT1_SHIFT)) & PXP_HIST_B_RAW_STAT1_STAT1_MASK) + +/*! @name HIST2_PARAM - 2-level Histogram Parameter Register. */ +#define PXP_HIST2_PARAM_VALUE0_MASK (0x3FU) +#define PXP_HIST2_PARAM_VALUE0_SHIFT (0U) +#define PXP_HIST2_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST2_PARAM_VALUE0_SHIFT)) & PXP_HIST2_PARAM_VALUE0_MASK) +#define PXP_HIST2_PARAM_VALUE1_MASK (0x3F00U) +#define PXP_HIST2_PARAM_VALUE1_SHIFT (8U) +#define PXP_HIST2_PARAM_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST2_PARAM_VALUE1_SHIFT)) & PXP_HIST2_PARAM_VALUE1_MASK) + +/*! @name HIST4_PARAM - 4-level Histogram Parameter Register. */ +#define PXP_HIST4_PARAM_VALUE0_MASK (0x3FU) +#define PXP_HIST4_PARAM_VALUE0_SHIFT (0U) +#define PXP_HIST4_PARAM_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE0_SHIFT)) & PXP_HIST4_PARAM_VALUE0_MASK) +#define PXP_HIST4_PARAM_VALUE1_MASK (0x3F00U) +#define PXP_HIST4_PARAM_VALUE1_SHIFT (8U) +#define PXP_HIST4_PARAM_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE1_SHIFT)) & PXP_HIST4_PARAM_VALUE1_MASK) +#define PXP_HIST4_PARAM_VALUE2_MASK (0x3F0000U) +#define PXP_HIST4_PARAM_VALUE2_SHIFT (16U) +#define PXP_HIST4_PARAM_VALUE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE2_SHIFT)) & PXP_HIST4_PARAM_VALUE2_MASK) +#define PXP_HIST4_PARAM_VALUE3_MASK (0x3F000000U) +#define PXP_HIST4_PARAM_VALUE3_SHIFT (24U) +#define PXP_HIST4_PARAM_VALUE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST4_PARAM_VALUE3_SHIFT)) & PXP_HIST4_PARAM_VALUE3_MASK) + +/*! @name HIST8_PARAM0 - 8-level Histogram Parameter 0 Register. */ +#define PXP_HIST8_PARAM0_VALUE0_MASK (0x3FU) +#define PXP_HIST8_PARAM0_VALUE0_SHIFT (0U) +#define PXP_HIST8_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE0_SHIFT)) & PXP_HIST8_PARAM0_VALUE0_MASK) +#define PXP_HIST8_PARAM0_VALUE1_MASK (0x3F00U) +#define PXP_HIST8_PARAM0_VALUE1_SHIFT (8U) +#define PXP_HIST8_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE1_SHIFT)) & PXP_HIST8_PARAM0_VALUE1_MASK) +#define PXP_HIST8_PARAM0_VALUE2_MASK (0x3F0000U) +#define PXP_HIST8_PARAM0_VALUE2_SHIFT (16U) +#define PXP_HIST8_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE2_SHIFT)) & PXP_HIST8_PARAM0_VALUE2_MASK) +#define PXP_HIST8_PARAM0_VALUE3_MASK (0x3F000000U) +#define PXP_HIST8_PARAM0_VALUE3_SHIFT (24U) +#define PXP_HIST8_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM0_VALUE3_SHIFT)) & PXP_HIST8_PARAM0_VALUE3_MASK) + +/*! @name HIST8_PARAM1 - 8-level Histogram Parameter 1 Register. */ +#define PXP_HIST8_PARAM1_VALUE4_MASK (0x3FU) +#define PXP_HIST8_PARAM1_VALUE4_SHIFT (0U) +#define PXP_HIST8_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE4_SHIFT)) & PXP_HIST8_PARAM1_VALUE4_MASK) +#define PXP_HIST8_PARAM1_VALUE5_MASK (0x3F00U) +#define PXP_HIST8_PARAM1_VALUE5_SHIFT (8U) +#define PXP_HIST8_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE5_SHIFT)) & PXP_HIST8_PARAM1_VALUE5_MASK) +#define PXP_HIST8_PARAM1_VALUE6_MASK (0x3F0000U) +#define PXP_HIST8_PARAM1_VALUE6_SHIFT (16U) +#define PXP_HIST8_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE6_SHIFT)) & PXP_HIST8_PARAM1_VALUE6_MASK) +#define PXP_HIST8_PARAM1_VALUE7_MASK (0x3F000000U) +#define PXP_HIST8_PARAM1_VALUE7_SHIFT (24U) +#define PXP_HIST8_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST8_PARAM1_VALUE7_SHIFT)) & PXP_HIST8_PARAM1_VALUE7_MASK) + +/*! @name HIST16_PARAM0 - 16-level Histogram Parameter 0 Register. */ +#define PXP_HIST16_PARAM0_VALUE0_MASK (0x3FU) +#define PXP_HIST16_PARAM0_VALUE0_SHIFT (0U) +#define PXP_HIST16_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE0_SHIFT)) & PXP_HIST16_PARAM0_VALUE0_MASK) +#define PXP_HIST16_PARAM0_VALUE1_MASK (0x3F00U) +#define PXP_HIST16_PARAM0_VALUE1_SHIFT (8U) +#define PXP_HIST16_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE1_SHIFT)) & PXP_HIST16_PARAM0_VALUE1_MASK) +#define PXP_HIST16_PARAM0_VALUE2_MASK (0x3F0000U) +#define PXP_HIST16_PARAM0_VALUE2_SHIFT (16U) +#define PXP_HIST16_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE2_SHIFT)) & PXP_HIST16_PARAM0_VALUE2_MASK) +#define PXP_HIST16_PARAM0_VALUE3_MASK (0x3F000000U) +#define PXP_HIST16_PARAM0_VALUE3_SHIFT (24U) +#define PXP_HIST16_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM0_VALUE3_SHIFT)) & PXP_HIST16_PARAM0_VALUE3_MASK) + +/*! @name HIST16_PARAM1 - 16-level Histogram Parameter 1 Register. */ +#define PXP_HIST16_PARAM1_VALUE4_MASK (0x3FU) +#define PXP_HIST16_PARAM1_VALUE4_SHIFT (0U) +#define PXP_HIST16_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE4_SHIFT)) & PXP_HIST16_PARAM1_VALUE4_MASK) +#define PXP_HIST16_PARAM1_VALUE5_MASK (0x3F00U) +#define PXP_HIST16_PARAM1_VALUE5_SHIFT (8U) +#define PXP_HIST16_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE5_SHIFT)) & PXP_HIST16_PARAM1_VALUE5_MASK) +#define PXP_HIST16_PARAM1_VALUE6_MASK (0x3F0000U) +#define PXP_HIST16_PARAM1_VALUE6_SHIFT (16U) +#define PXP_HIST16_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE6_SHIFT)) & PXP_HIST16_PARAM1_VALUE6_MASK) +#define PXP_HIST16_PARAM1_VALUE7_MASK (0x3F000000U) +#define PXP_HIST16_PARAM1_VALUE7_SHIFT (24U) +#define PXP_HIST16_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM1_VALUE7_SHIFT)) & PXP_HIST16_PARAM1_VALUE7_MASK) + +/*! @name HIST16_PARAM2 - 16-level Histogram Parameter 2 Register. */ +#define PXP_HIST16_PARAM2_VALUE8_MASK (0x3FU) +#define PXP_HIST16_PARAM2_VALUE8_SHIFT (0U) +#define PXP_HIST16_PARAM2_VALUE8(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE8_SHIFT)) & PXP_HIST16_PARAM2_VALUE8_MASK) +#define PXP_HIST16_PARAM2_VALUE9_MASK (0x3F00U) +#define PXP_HIST16_PARAM2_VALUE9_SHIFT (8U) +#define PXP_HIST16_PARAM2_VALUE9(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE9_SHIFT)) & PXP_HIST16_PARAM2_VALUE9_MASK) +#define PXP_HIST16_PARAM2_VALUE10_MASK (0x3F0000U) +#define PXP_HIST16_PARAM2_VALUE10_SHIFT (16U) +#define PXP_HIST16_PARAM2_VALUE10(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE10_SHIFT)) & PXP_HIST16_PARAM2_VALUE10_MASK) +#define PXP_HIST16_PARAM2_VALUE11_MASK (0x3F000000U) +#define PXP_HIST16_PARAM2_VALUE11_SHIFT (24U) +#define PXP_HIST16_PARAM2_VALUE11(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM2_VALUE11_SHIFT)) & PXP_HIST16_PARAM2_VALUE11_MASK) + +/*! @name HIST16_PARAM3 - 16-level Histogram Parameter 3 Register. */ +#define PXP_HIST16_PARAM3_VALUE12_MASK (0x3FU) +#define PXP_HIST16_PARAM3_VALUE12_SHIFT (0U) +#define PXP_HIST16_PARAM3_VALUE12(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE12_SHIFT)) & PXP_HIST16_PARAM3_VALUE12_MASK) +#define PXP_HIST16_PARAM3_VALUE13_MASK (0x3F00U) +#define PXP_HIST16_PARAM3_VALUE13_SHIFT (8U) +#define PXP_HIST16_PARAM3_VALUE13(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE13_SHIFT)) & PXP_HIST16_PARAM3_VALUE13_MASK) +#define PXP_HIST16_PARAM3_VALUE14_MASK (0x3F0000U) +#define PXP_HIST16_PARAM3_VALUE14_SHIFT (16U) +#define PXP_HIST16_PARAM3_VALUE14(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE14_SHIFT)) & PXP_HIST16_PARAM3_VALUE14_MASK) +#define PXP_HIST16_PARAM3_VALUE15_MASK (0x3F000000U) +#define PXP_HIST16_PARAM3_VALUE15_SHIFT (24U) +#define PXP_HIST16_PARAM3_VALUE15(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST16_PARAM3_VALUE15_SHIFT)) & PXP_HIST16_PARAM3_VALUE15_MASK) + +/*! @name HIST32_PARAM0 - 32-level Histogram Parameter 0 Register. */ +#define PXP_HIST32_PARAM0_VALUE0_MASK (0x3FU) +#define PXP_HIST32_PARAM0_VALUE0_SHIFT (0U) +#define PXP_HIST32_PARAM0_VALUE0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE0_SHIFT)) & PXP_HIST32_PARAM0_VALUE0_MASK) +#define PXP_HIST32_PARAM0_VALUE1_MASK (0x3F00U) +#define PXP_HIST32_PARAM0_VALUE1_SHIFT (8U) +#define PXP_HIST32_PARAM0_VALUE1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE1_SHIFT)) & PXP_HIST32_PARAM0_VALUE1_MASK) +#define PXP_HIST32_PARAM0_VALUE2_MASK (0x3F0000U) +#define PXP_HIST32_PARAM0_VALUE2_SHIFT (16U) +#define PXP_HIST32_PARAM0_VALUE2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE2_SHIFT)) & PXP_HIST32_PARAM0_VALUE2_MASK) +#define PXP_HIST32_PARAM0_VALUE3_MASK (0x3F000000U) +#define PXP_HIST32_PARAM0_VALUE3_SHIFT (24U) +#define PXP_HIST32_PARAM0_VALUE3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM0_VALUE3_SHIFT)) & PXP_HIST32_PARAM0_VALUE3_MASK) + +/*! @name HIST32_PARAM1 - 32-level Histogram Parameter 1 Register. */ +#define PXP_HIST32_PARAM1_VALUE4_MASK (0x3FU) +#define PXP_HIST32_PARAM1_VALUE4_SHIFT (0U) +#define PXP_HIST32_PARAM1_VALUE4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE4_SHIFT)) & PXP_HIST32_PARAM1_VALUE4_MASK) +#define PXP_HIST32_PARAM1_VALUE5_MASK (0x3F00U) +#define PXP_HIST32_PARAM1_VALUE5_SHIFT (8U) +#define PXP_HIST32_PARAM1_VALUE5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE5_SHIFT)) & PXP_HIST32_PARAM1_VALUE5_MASK) +#define PXP_HIST32_PARAM1_VALUE6_MASK (0x3F0000U) +#define PXP_HIST32_PARAM1_VALUE6_SHIFT (16U) +#define PXP_HIST32_PARAM1_VALUE6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE6_SHIFT)) & PXP_HIST32_PARAM1_VALUE6_MASK) +#define PXP_HIST32_PARAM1_VALUE7_MASK (0x3F000000U) +#define PXP_HIST32_PARAM1_VALUE7_SHIFT (24U) +#define PXP_HIST32_PARAM1_VALUE7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM1_VALUE7_SHIFT)) & PXP_HIST32_PARAM1_VALUE7_MASK) + +/*! @name HIST32_PARAM2 - 32-level Histogram Parameter 2 Register. */ +#define PXP_HIST32_PARAM2_VALUE8_MASK (0x3FU) +#define PXP_HIST32_PARAM2_VALUE8_SHIFT (0U) +#define PXP_HIST32_PARAM2_VALUE8(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE8_SHIFT)) & PXP_HIST32_PARAM2_VALUE8_MASK) +#define PXP_HIST32_PARAM2_VALUE9_MASK (0x3F00U) +#define PXP_HIST32_PARAM2_VALUE9_SHIFT (8U) +#define PXP_HIST32_PARAM2_VALUE9(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE9_SHIFT)) & PXP_HIST32_PARAM2_VALUE9_MASK) +#define PXP_HIST32_PARAM2_VALUE10_MASK (0x3F0000U) +#define PXP_HIST32_PARAM2_VALUE10_SHIFT (16U) +#define PXP_HIST32_PARAM2_VALUE10(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE10_SHIFT)) & PXP_HIST32_PARAM2_VALUE10_MASK) +#define PXP_HIST32_PARAM2_VALUE11_MASK (0x3F000000U) +#define PXP_HIST32_PARAM2_VALUE11_SHIFT (24U) +#define PXP_HIST32_PARAM2_VALUE11(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM2_VALUE11_SHIFT)) & PXP_HIST32_PARAM2_VALUE11_MASK) + +/*! @name HIST32_PARAM3 - 32-level Histogram Parameter 3 Register. */ +#define PXP_HIST32_PARAM3_VALUE12_MASK (0x3FU) +#define PXP_HIST32_PARAM3_VALUE12_SHIFT (0U) +#define PXP_HIST32_PARAM3_VALUE12(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE12_SHIFT)) & PXP_HIST32_PARAM3_VALUE12_MASK) +#define PXP_HIST32_PARAM3_VALUE13_MASK (0x3F00U) +#define PXP_HIST32_PARAM3_VALUE13_SHIFT (8U) +#define PXP_HIST32_PARAM3_VALUE13(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE13_SHIFT)) & PXP_HIST32_PARAM3_VALUE13_MASK) +#define PXP_HIST32_PARAM3_VALUE14_MASK (0x3F0000U) +#define PXP_HIST32_PARAM3_VALUE14_SHIFT (16U) +#define PXP_HIST32_PARAM3_VALUE14(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE14_SHIFT)) & PXP_HIST32_PARAM3_VALUE14_MASK) +#define PXP_HIST32_PARAM3_VALUE15_MASK (0x3F000000U) +#define PXP_HIST32_PARAM3_VALUE15_SHIFT (24U) +#define PXP_HIST32_PARAM3_VALUE15(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM3_VALUE15_SHIFT)) & PXP_HIST32_PARAM3_VALUE15_MASK) + +/*! @name HIST32_PARAM4 - 32-level Histogram Parameter 0 Register. */ +#define PXP_HIST32_PARAM4_VALUE16_MASK (0x3FU) +#define PXP_HIST32_PARAM4_VALUE16_SHIFT (0U) +#define PXP_HIST32_PARAM4_VALUE16(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE16_SHIFT)) & PXP_HIST32_PARAM4_VALUE16_MASK) +#define PXP_HIST32_PARAM4_VALUE17_MASK (0x3F00U) +#define PXP_HIST32_PARAM4_VALUE17_SHIFT (8U) +#define PXP_HIST32_PARAM4_VALUE17(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE17_SHIFT)) & PXP_HIST32_PARAM4_VALUE17_MASK) +#define PXP_HIST32_PARAM4_VALUE18_MASK (0x3F0000U) +#define PXP_HIST32_PARAM4_VALUE18_SHIFT (16U) +#define PXP_HIST32_PARAM4_VALUE18(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE18_SHIFT)) & PXP_HIST32_PARAM4_VALUE18_MASK) +#define PXP_HIST32_PARAM4_VALUE19_MASK (0x3F000000U) +#define PXP_HIST32_PARAM4_VALUE19_SHIFT (24U) +#define PXP_HIST32_PARAM4_VALUE19(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM4_VALUE19_SHIFT)) & PXP_HIST32_PARAM4_VALUE19_MASK) + +/*! @name HIST32_PARAM5 - 32-level Histogram Parameter 1 Register. */ +#define PXP_HIST32_PARAM5_VALUE20_MASK (0x3FU) +#define PXP_HIST32_PARAM5_VALUE20_SHIFT (0U) +#define PXP_HIST32_PARAM5_VALUE20(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE20_SHIFT)) & PXP_HIST32_PARAM5_VALUE20_MASK) +#define PXP_HIST32_PARAM5_VALUE21_MASK (0x3F00U) +#define PXP_HIST32_PARAM5_VALUE21_SHIFT (8U) +#define PXP_HIST32_PARAM5_VALUE21(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE21_SHIFT)) & PXP_HIST32_PARAM5_VALUE21_MASK) +#define PXP_HIST32_PARAM5_VALUE22_MASK (0x3F0000U) +#define PXP_HIST32_PARAM5_VALUE22_SHIFT (16U) +#define PXP_HIST32_PARAM5_VALUE22(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE22_SHIFT)) & PXP_HIST32_PARAM5_VALUE22_MASK) +#define PXP_HIST32_PARAM5_VALUE23_MASK (0x3F000000U) +#define PXP_HIST32_PARAM5_VALUE23_SHIFT (24U) +#define PXP_HIST32_PARAM5_VALUE23(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM5_VALUE23_SHIFT)) & PXP_HIST32_PARAM5_VALUE23_MASK) + +/*! @name HIST32_PARAM6 - 32-level Histogram Parameter 2 Register. */ +#define PXP_HIST32_PARAM6_VALUE24_MASK (0x3FU) +#define PXP_HIST32_PARAM6_VALUE24_SHIFT (0U) +#define PXP_HIST32_PARAM6_VALUE24(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE24_SHIFT)) & PXP_HIST32_PARAM6_VALUE24_MASK) +#define PXP_HIST32_PARAM6_VALUE25_MASK (0x3F00U) +#define PXP_HIST32_PARAM6_VALUE25_SHIFT (8U) +#define PXP_HIST32_PARAM6_VALUE25(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE25_SHIFT)) & PXP_HIST32_PARAM6_VALUE25_MASK) +#define PXP_HIST32_PARAM6_VALUE26_MASK (0x3F0000U) +#define PXP_HIST32_PARAM6_VALUE26_SHIFT (16U) +#define PXP_HIST32_PARAM6_VALUE26(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE26_SHIFT)) & PXP_HIST32_PARAM6_VALUE26_MASK) +#define PXP_HIST32_PARAM6_VALUE27_MASK (0x3F000000U) +#define PXP_HIST32_PARAM6_VALUE27_SHIFT (24U) +#define PXP_HIST32_PARAM6_VALUE27(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM6_VALUE27_SHIFT)) & PXP_HIST32_PARAM6_VALUE27_MASK) + +/*! @name HIST32_PARAM7 - 32-level Histogram Parameter 3 Register. */ +#define PXP_HIST32_PARAM7_VALUE28_MASK (0x3FU) +#define PXP_HIST32_PARAM7_VALUE28_SHIFT (0U) +#define PXP_HIST32_PARAM7_VALUE28(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE28_SHIFT)) & PXP_HIST32_PARAM7_VALUE28_MASK) +#define PXP_HIST32_PARAM7_VALUE29_MASK (0x3F00U) +#define PXP_HIST32_PARAM7_VALUE29_SHIFT (8U) +#define PXP_HIST32_PARAM7_VALUE29(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE29_SHIFT)) & PXP_HIST32_PARAM7_VALUE29_MASK) +#define PXP_HIST32_PARAM7_VALUE30_MASK (0x3F0000U) +#define PXP_HIST32_PARAM7_VALUE30_SHIFT (16U) +#define PXP_HIST32_PARAM7_VALUE30(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE30_SHIFT)) & PXP_HIST32_PARAM7_VALUE30_MASK) +#define PXP_HIST32_PARAM7_VALUE31_MASK (0x3F000000U) +#define PXP_HIST32_PARAM7_VALUE31_SHIFT (24U) +#define PXP_HIST32_PARAM7_VALUE31(x) (((uint32_t)(((uint32_t)(x)) << PXP_HIST32_PARAM7_VALUE31_SHIFT)) & PXP_HIST32_PARAM7_VALUE31_MASK) + +/*! @name HANDSHAKE_READY_MUX0 - This register defines the pxp subblock handshake signals ready mux on top level. */ +#define PXP_HANDSHAKE_READY_MUX0_HSK0_MASK (0xFU) +#define PXP_HANDSHAKE_READY_MUX0_HSK0_SHIFT (0U) +#define PXP_HANDSHAKE_READY_MUX0_HSK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK0_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK0_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK1_MASK (0xF0U) +#define PXP_HANDSHAKE_READY_MUX0_HSK1_SHIFT (4U) +#define PXP_HANDSHAKE_READY_MUX0_HSK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK1_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK1_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK2_MASK (0xF00U) +#define PXP_HANDSHAKE_READY_MUX0_HSK2_SHIFT (8U) +#define PXP_HANDSHAKE_READY_MUX0_HSK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK2_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK2_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK3_MASK (0xF000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK3_SHIFT (12U) +#define PXP_HANDSHAKE_READY_MUX0_HSK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK3_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK3_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK4_MASK (0xF0000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK4_SHIFT (16U) +#define PXP_HANDSHAKE_READY_MUX0_HSK4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK4_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK4_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK5_MASK (0xF00000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK5_SHIFT (20U) +#define PXP_HANDSHAKE_READY_MUX0_HSK5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK5_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK5_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK6_MASK (0xF000000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK6_SHIFT (24U) +#define PXP_HANDSHAKE_READY_MUX0_HSK6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK6_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK6_MASK) +#define PXP_HANDSHAKE_READY_MUX0_HSK7_MASK (0xF0000000U) +#define PXP_HANDSHAKE_READY_MUX0_HSK7_SHIFT (28U) +#define PXP_HANDSHAKE_READY_MUX0_HSK7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX0_HSK7_SHIFT)) & PXP_HANDSHAKE_READY_MUX0_HSK7_MASK) + +/*! @name HANDSHAKE_READY_MUX1 - This register defines the pxp subblock handshake signals ready mux on top level. */ +#define PXP_HANDSHAKE_READY_MUX1_HSK8_MASK (0xFU) +#define PXP_HANDSHAKE_READY_MUX1_HSK8_SHIFT (0U) +#define PXP_HANDSHAKE_READY_MUX1_HSK8(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK8_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK8_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK9_MASK (0xF0U) +#define PXP_HANDSHAKE_READY_MUX1_HSK9_SHIFT (4U) +#define PXP_HANDSHAKE_READY_MUX1_HSK9(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK9_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK9_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK10_MASK (0xF00U) +#define PXP_HANDSHAKE_READY_MUX1_HSK10_SHIFT (8U) +#define PXP_HANDSHAKE_READY_MUX1_HSK10(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK10_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK10_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK11_MASK (0xF000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK11_SHIFT (12U) +#define PXP_HANDSHAKE_READY_MUX1_HSK11(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK11_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK11_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK12_MASK (0xF0000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK12_SHIFT (16U) +#define PXP_HANDSHAKE_READY_MUX1_HSK12(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK12_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK12_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK13_MASK (0xF00000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK13_SHIFT (20U) +#define PXP_HANDSHAKE_READY_MUX1_HSK13(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK13_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK13_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK14_MASK (0xF000000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK14_SHIFT (24U) +#define PXP_HANDSHAKE_READY_MUX1_HSK14(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK14_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK14_MASK) +#define PXP_HANDSHAKE_READY_MUX1_HSK15_MASK (0xF0000000U) +#define PXP_HANDSHAKE_READY_MUX1_HSK15_SHIFT (28U) +#define PXP_HANDSHAKE_READY_MUX1_HSK15(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_READY_MUX1_HSK15_SHIFT)) & PXP_HANDSHAKE_READY_MUX1_HSK15_MASK) + +/*! @name HANDSHAKE_DONE_MUX0 - This register defines the pxp subblock handshake signals done mux on top level. */ +#define PXP_HANDSHAKE_DONE_MUX0_HSK0_MASK (0xFU) +#define PXP_HANDSHAKE_DONE_MUX0_HSK0_SHIFT (0U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK0(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK0_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK0_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK1_MASK (0xF0U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK1_SHIFT (4U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK1(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK1_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK1_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK2_MASK (0xF00U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK2_SHIFT (8U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK2(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK2_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK2_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK3_MASK (0xF000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK3_SHIFT (12U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK3(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK3_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK3_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK4_MASK (0xF0000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK4_SHIFT (16U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK4(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK4_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK4_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK5_MASK (0xF00000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK5_SHIFT (20U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK5(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK5_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK5_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK6_MASK (0xF000000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK6_SHIFT (24U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK6(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK6_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK6_MASK) +#define PXP_HANDSHAKE_DONE_MUX0_HSK7_MASK (0xF0000000U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK7_SHIFT (28U) +#define PXP_HANDSHAKE_DONE_MUX0_HSK7(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX0_HSK7_SHIFT)) & PXP_HANDSHAKE_DONE_MUX0_HSK7_MASK) + +/*! @name HANDSHAKE_DONE_MUX1 - This register defines the pxp subblock handshake signals done mux on top level. */ +#define PXP_HANDSHAKE_DONE_MUX1_HSK8_MASK (0xFU) +#define PXP_HANDSHAKE_DONE_MUX1_HSK8_SHIFT (0U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK8(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK8_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK8_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK9_MASK (0xF0U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK9_SHIFT (4U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK9(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK9_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK9_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK10_MASK (0xF00U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK10_SHIFT (8U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK10(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK10_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK10_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK11_MASK (0xF000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK11_SHIFT (12U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK11(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK11_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK11_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK12_MASK (0xF0000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK12_SHIFT (16U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK12(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK12_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK12_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK13_MASK (0xF00000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK13_SHIFT (20U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK13(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK13_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK13_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK14_MASK (0xF000000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK14_SHIFT (24U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK14(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK14_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK14_MASK) +#define PXP_HANDSHAKE_DONE_MUX1_HSK15_MASK (0xF0000000U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK15_SHIFT (28U) +#define PXP_HANDSHAKE_DONE_MUX1_HSK15(x) (((uint32_t)(((uint32_t)(x)) << PXP_HANDSHAKE_DONE_MUX1_HSK15_SHIFT)) & PXP_HANDSHAKE_DONE_MUX1_HSK15_MASK) + + +/*! + * @} + */ /* end of group PXP_Register_Masks */ + + +/* PXP - Peripheral instance base addresses */ +/** Peripheral PXP base address */ +#define PXP_BASE (0x21CC000u) +/** Peripheral PXP base pointer */ +#define PXP ((PXP_Type *)PXP_BASE) +/** Array initializer of PXP peripheral base addresses */ +#define PXP_BASE_ADDRS { PXP_BASE } +/** Array initializer of PXP peripheral base pointers */ +#define PXP_BASE_PTRS { PXP } +/** Interrupt vectors for the PXP peripheral type */ +#define PXP_IRQ0_IRQS { PXP_IRQ0_IRQn } +#define PXP_IRQ1_IRQS { PXP_IRQ1_IRQn } + +/*! + * @} + */ /* end of group PXP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- QuadSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer + * @{ + */ + +/** QuadSPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ + __IO uint32_t FLSHCR; /**< Flash Configuration Register, offset: 0xC */ + __IO uint32_t BUF0CR; /**< Buffer0 Configuration Register, offset: 0x10 */ + __IO uint32_t BUF1CR; /**< Buffer1 Configuration Register, offset: 0x14 */ + __IO uint32_t BUF2CR; /**< Buffer2 Configuration Register, offset: 0x18 */ + __IO uint32_t BUF3CR; /**< Buffer3 Configuration Register, offset: 0x1C */ + __IO uint32_t BFGENCR; /**< Buffer Generic Configuration Register, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ + __IO uint32_t BUF1IND; /**< Buffer1 Top Index Register, offset: 0x34 */ + __IO uint32_t BUF2IND; /**< Buffer2 Top Index Register, offset: 0x38 */ + uint8_t RESERVED_2[196]; + __IO uint32_t SFAR; /**< Serial Flash Address Register, offset: 0x100 */ + uint8_t RESERVED_3[4]; + __IO uint32_t SMPR; /**< Sampling Register, offset: 0x108 */ + __I uint32_t RBSR; /**< RX Buffer Status Register, offset: 0x10C */ + __IO uint32_t RBCT; /**< RX Buffer Control Register, offset: 0x110 */ + uint8_t RESERVED_4[60]; + __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ + __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ + uint8_t RESERVED_5[4]; + __I uint32_t SR; /**< Status Register, offset: 0x15C */ + __IO uint32_t FR; /**< Flag Register, offset: 0x160 */ + __IO uint32_t RSER; /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */ + __I uint32_t SPNDST; /**< Sequence Suspend Status Register, offset: 0x168 */ + __IO uint32_t SPTRCLR; /**< Sequence Pointer Clear Register, offset: 0x16C */ + uint8_t RESERVED_6[16]; + __IO uint32_t SFA1AD; /**< Serial Flash A1 Top Address, offset: 0x180 */ + __IO uint32_t SFA2AD; /**< Serial Flash A2 Top Address, offset: 0x184 */ + __IO uint32_t SFB1AD; /**< Serial Flash B1Top Address, offset: 0x188 */ + __IO uint32_t SFB2AD; /**< Serial Flash B2Top Address, offset: 0x18C */ + uint8_t RESERVED_7[112]; + __IO uint32_t RBDR[32]; /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_8[128]; + __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x300 */ + __IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x304 */ + uint8_t RESERVED_9[8]; + __IO uint32_t LUT[64]; /**< Look-up Table register, array offset: 0x310, array step: 0x4 */ +} QuadSPI_Type; + +/* ---------------------------------------------------------------------------- + -- QuadSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +#define QuadSPI_MCR_SWRSTSD_MASK (0x1U) +#define QuadSPI_MCR_SWRSTSD_SHIFT (0U) +#define QuadSPI_MCR_SWRSTSD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTSD_SHIFT)) & QuadSPI_MCR_SWRSTSD_MASK) +#define QuadSPI_MCR_SWRSTHD_MASK (0x2U) +#define QuadSPI_MCR_SWRSTHD_SHIFT (1U) +#define QuadSPI_MCR_SWRSTHD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK) +#define QuadSPI_MCR_END_CFG_MASK (0xCU) +#define QuadSPI_MCR_END_CFG_SHIFT (2U) +#define QuadSPI_MCR_END_CFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_END_CFG_SHIFT)) & QuadSPI_MCR_END_CFG_MASK) +#define QuadSPI_MCR_DQS_EN_MASK (0x40U) +#define QuadSPI_MCR_DQS_EN_SHIFT (6U) +#define QuadSPI_MCR_DQS_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_EN_SHIFT)) & QuadSPI_MCR_DQS_EN_MASK) +#define QuadSPI_MCR_DDR_EN_MASK (0x80U) +#define QuadSPI_MCR_DDR_EN_SHIFT (7U) +#define QuadSPI_MCR_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DDR_EN_SHIFT)) & QuadSPI_MCR_DDR_EN_MASK) +#define QuadSPI_MCR_CLR_RXF_MASK (0x400U) +#define QuadSPI_MCR_CLR_RXF_SHIFT (10U) +#define QuadSPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_RXF_SHIFT)) & QuadSPI_MCR_CLR_RXF_MASK) +#define QuadSPI_MCR_CLR_TXF_MASK (0x800U) +#define QuadSPI_MCR_CLR_TXF_SHIFT (11U) +#define QuadSPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_TXF_SHIFT)) & QuadSPI_MCR_CLR_TXF_MASK) +#define QuadSPI_MCR_MDIS_MASK (0x4000U) +#define QuadSPI_MCR_MDIS_SHIFT (14U) +#define QuadSPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_MDIS_SHIFT)) & QuadSPI_MCR_MDIS_MASK) +#define QuadSPI_MCR_DQS_LOOPBACK_EN_MASK (0x1000000U) +#define QuadSPI_MCR_DQS_LOOPBACK_EN_SHIFT (24U) +#define QuadSPI_MCR_DQS_LOOPBACK_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_LOOPBACK_EN_SHIFT)) & QuadSPI_MCR_DQS_LOOPBACK_EN_MASK) +#define QuadSPI_MCR_DQS_PHASE_EN_MASK (0x40000000U) +#define QuadSPI_MCR_DQS_PHASE_EN_SHIFT (30U) +#define QuadSPI_MCR_DQS_PHASE_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_PHASE_EN_SHIFT)) & QuadSPI_MCR_DQS_PHASE_EN_MASK) + +/*! @name IPCR - IP Configuration Register */ +#define QuadSPI_IPCR_IDATSZ_MASK (0xFFFFU) +#define QuadSPI_IPCR_IDATSZ_SHIFT (0U) +#define QuadSPI_IPCR_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_IDATSZ_SHIFT)) & QuadSPI_IPCR_IDATSZ_MASK) +#define QuadSPI_IPCR_PAR_EN_MASK (0x10000U) +#define QuadSPI_IPCR_PAR_EN_SHIFT (16U) +#define QuadSPI_IPCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_PAR_EN_SHIFT)) & QuadSPI_IPCR_PAR_EN_MASK) +#define QuadSPI_IPCR_SEQID_MASK (0xF000000U) +#define QuadSPI_IPCR_SEQID_SHIFT (24U) +#define QuadSPI_IPCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK) + +/*! @name FLSHCR - Flash Configuration Register */ +#define QuadSPI_FLSHCR_TCSS_MASK (0xFU) +#define QuadSPI_FLSHCR_TCSS_SHIFT (0U) +#define QuadSPI_FLSHCR_TCSS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSS_SHIFT)) & QuadSPI_FLSHCR_TCSS_MASK) +#define QuadSPI_FLSHCR_TCSH_MASK (0xF00U) +#define QuadSPI_FLSHCR_TCSH_SHIFT (8U) +#define QuadSPI_FLSHCR_TCSH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSH_SHIFT)) & QuadSPI_FLSHCR_TCSH_MASK) + +/*! @name BUF0CR - Buffer0 Configuration Register */ +#define QuadSPI_BUF0CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF0CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF0CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_MSTRID_SHIFT)) & QuadSPI_BUF0CR_MSTRID_MASK) +#define QuadSPI_BUF0CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF0CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF0CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_ADATSZ_SHIFT)) & QuadSPI_BUF0CR_ADATSZ_MASK) +#define QuadSPI_BUF0CR_HP_EN_MASK (0x80000000U) +#define QuadSPI_BUF0CR_HP_EN_SHIFT (31U) +#define QuadSPI_BUF0CR_HP_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_HP_EN_SHIFT)) & QuadSPI_BUF0CR_HP_EN_MASK) + +/*! @name BUF1CR - Buffer1 Configuration Register */ +#define QuadSPI_BUF1CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF1CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF1CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_MSTRID_SHIFT)) & QuadSPI_BUF1CR_MSTRID_MASK) +#define QuadSPI_BUF1CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF1CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF1CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_ADATSZ_SHIFT)) & QuadSPI_BUF1CR_ADATSZ_MASK) + +/*! @name BUF2CR - Buffer2 Configuration Register */ +#define QuadSPI_BUF2CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF2CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF2CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_MSTRID_SHIFT)) & QuadSPI_BUF2CR_MSTRID_MASK) +#define QuadSPI_BUF2CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF2CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF2CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_ADATSZ_SHIFT)) & QuadSPI_BUF2CR_ADATSZ_MASK) + +/*! @name BUF3CR - Buffer3 Configuration Register */ +#define QuadSPI_BUF3CR_MSTRID_MASK (0xFU) +#define QuadSPI_BUF3CR_MSTRID_SHIFT (0U) +#define QuadSPI_BUF3CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_MSTRID_SHIFT)) & QuadSPI_BUF3CR_MSTRID_MASK) +#define QuadSPI_BUF3CR_ADATSZ_MASK (0xFF00U) +#define QuadSPI_BUF3CR_ADATSZ_SHIFT (8U) +#define QuadSPI_BUF3CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ADATSZ_SHIFT)) & QuadSPI_BUF3CR_ADATSZ_MASK) +#define QuadSPI_BUF3CR_ALLMST_MASK (0x80000000U) +#define QuadSPI_BUF3CR_ALLMST_SHIFT (31U) +#define QuadSPI_BUF3CR_ALLMST(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ALLMST_SHIFT)) & QuadSPI_BUF3CR_ALLMST_MASK) + +/*! @name BFGENCR - Buffer Generic Configuration Register */ +#define QuadSPI_BFGENCR_SEQID_MASK (0xF000U) +#define QuadSPI_BFGENCR_SEQID_SHIFT (12U) +#define QuadSPI_BFGENCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_SEQID_SHIFT)) & QuadSPI_BFGENCR_SEQID_MASK) +#define QuadSPI_BFGENCR_PAR_EN_MASK (0x10000U) +#define QuadSPI_BFGENCR_PAR_EN_SHIFT (16U) +#define QuadSPI_BFGENCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_PAR_EN_SHIFT)) & QuadSPI_BFGENCR_PAR_EN_MASK) + +/*! @name BUF0IND - Buffer0 Top Index Register */ +#define QuadSPI_BUF0IND_TPINDX0_MASK (0xFFFFFFF8U) +#define QuadSPI_BUF0IND_TPINDX0_SHIFT (3U) +#define QuadSPI_BUF0IND_TPINDX0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0IND_TPINDX0_SHIFT)) & QuadSPI_BUF0IND_TPINDX0_MASK) + +/*! @name BUF1IND - Buffer1 Top Index Register */ +#define QuadSPI_BUF1IND_TPINDX1_MASK (0xFFFFFFF8U) +#define QuadSPI_BUF1IND_TPINDX1_SHIFT (3U) +#define QuadSPI_BUF1IND_TPINDX1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1IND_TPINDX1_SHIFT)) & QuadSPI_BUF1IND_TPINDX1_MASK) + +/*! @name BUF2IND - Buffer2 Top Index Register */ +#define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) +#define QuadSPI_BUF2IND_TPINDX2_SHIFT (3U) +#define QuadSPI_BUF2IND_TPINDX2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK) + +/*! @name SFAR - Serial Flash Address Register */ +#define QuadSPI_SFAR_SFADR_MASK (0xFFFFFFFFU) +#define QuadSPI_SFAR_SFADR_SHIFT (0U) +#define QuadSPI_SFAR_SFADR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFAR_SFADR_SHIFT)) & QuadSPI_SFAR_SFADR_MASK) + +/*! @name SMPR - Sampling Register */ +#define QuadSPI_SMPR_SDRSMP_MASK (0x60U) +#define QuadSPI_SMPR_SDRSMP_SHIFT (5U) +#define QuadSPI_SMPR_SDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_SDRSMP_SHIFT)) & QuadSPI_SMPR_SDRSMP_MASK) +#define QuadSPI_SMPR_DDRSMP_MASK (0x70000U) +#define QuadSPI_SMPR_DDRSMP_SHIFT (16U) +#define QuadSPI_SMPR_DDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_DDRSMP_SHIFT)) & QuadSPI_SMPR_DDRSMP_MASK) + +/*! @name RBSR - RX Buffer Status Register */ +#define QuadSPI_RBSR_RDBFL_MASK (0x3F00U) +#define QuadSPI_RBSR_RDBFL_SHIFT (8U) +#define QuadSPI_RBSR_RDBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDBFL_SHIFT)) & QuadSPI_RBSR_RDBFL_MASK) +#define QuadSPI_RBSR_RDCTR_MASK (0xFFFF0000U) +#define QuadSPI_RBSR_RDCTR_SHIFT (16U) +#define QuadSPI_RBSR_RDCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDCTR_SHIFT)) & QuadSPI_RBSR_RDCTR_MASK) + +/*! @name RBCT - RX Buffer Control Register */ +#define QuadSPI_RBCT_WMRK_MASK (0x1FU) +#define QuadSPI_RBCT_WMRK_SHIFT (0U) +#define QuadSPI_RBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_WMRK_SHIFT)) & QuadSPI_RBCT_WMRK_MASK) +#define QuadSPI_RBCT_RXBRD_MASK (0x100U) +#define QuadSPI_RBCT_RXBRD_SHIFT (8U) +#define QuadSPI_RBCT_RXBRD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_RXBRD_SHIFT)) & QuadSPI_RBCT_RXBRD_MASK) + +/*! @name TBSR - TX Buffer Status Register */ +#define QuadSPI_TBSR_TRBFL_MASK (0x1F00U) +#define QuadSPI_TBSR_TRBFL_SHIFT (8U) +#define QuadSPI_TBSR_TRBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRBFL_SHIFT)) & QuadSPI_TBSR_TRBFL_MASK) +#define QuadSPI_TBSR_TRCTR_MASK (0xFFFF0000U) +#define QuadSPI_TBSR_TRCTR_SHIFT (16U) +#define QuadSPI_TBSR_TRCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRCTR_SHIFT)) & QuadSPI_TBSR_TRCTR_MASK) + +/*! @name TBDR - TX Buffer Data Register */ +#define QuadSPI_TBDR_TXDATA_MASK (0xFFFFFFFFU) +#define QuadSPI_TBDR_TXDATA_SHIFT (0U) +#define QuadSPI_TBDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBDR_TXDATA_SHIFT)) & QuadSPI_TBDR_TXDATA_MASK) + +/*! @name SR - Status Register */ +#define QuadSPI_SR_BUSY_MASK (0x1U) +#define QuadSPI_SR_BUSY_SHIFT (0U) +#define QuadSPI_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_BUSY_SHIFT)) & QuadSPI_SR_BUSY_MASK) +#define QuadSPI_SR_IP_ACC_MASK (0x2U) +#define QuadSPI_SR_IP_ACC_SHIFT (1U) +#define QuadSPI_SR_IP_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_IP_ACC_SHIFT)) & QuadSPI_SR_IP_ACC_MASK) +#define QuadSPI_SR_AHB_ACC_MASK (0x4U) +#define QuadSPI_SR_AHB_ACC_SHIFT (2U) +#define QuadSPI_SR_AHB_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB_ACC_SHIFT)) & QuadSPI_SR_AHB_ACC_MASK) +#define QuadSPI_SR_AHBGNT_MASK (0x20U) +#define QuadSPI_SR_AHBGNT_SHIFT (5U) +#define QuadSPI_SR_AHBGNT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBGNT_SHIFT)) & QuadSPI_SR_AHBGNT_MASK) +#define QuadSPI_SR_AHBTRN_MASK (0x40U) +#define QuadSPI_SR_AHBTRN_SHIFT (6U) +#define QuadSPI_SR_AHBTRN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBTRN_SHIFT)) & QuadSPI_SR_AHBTRN_MASK) +#define QuadSPI_SR_AHB0NE_MASK (0x80U) +#define QuadSPI_SR_AHB0NE_SHIFT (7U) +#define QuadSPI_SR_AHB0NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK) +#define QuadSPI_SR_AHB1NE_MASK (0x100U) +#define QuadSPI_SR_AHB1NE_SHIFT (8U) +#define QuadSPI_SR_AHB1NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1NE_SHIFT)) & QuadSPI_SR_AHB1NE_MASK) +#define QuadSPI_SR_AHB2NE_MASK (0x200U) +#define QuadSPI_SR_AHB2NE_SHIFT (9U) +#define QuadSPI_SR_AHB2NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2NE_SHIFT)) & QuadSPI_SR_AHB2NE_MASK) +#define QuadSPI_SR_AHB3NE_MASK (0x400U) +#define QuadSPI_SR_AHB3NE_SHIFT (10U) +#define QuadSPI_SR_AHB3NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3NE_SHIFT)) & QuadSPI_SR_AHB3NE_MASK) +#define QuadSPI_SR_AHB0FUL_MASK (0x800U) +#define QuadSPI_SR_AHB0FUL_SHIFT (11U) +#define QuadSPI_SR_AHB0FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK) +#define QuadSPI_SR_AHB1FUL_MASK (0x1000U) +#define QuadSPI_SR_AHB1FUL_SHIFT (12U) +#define QuadSPI_SR_AHB1FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1FUL_SHIFT)) & QuadSPI_SR_AHB1FUL_MASK) +#define QuadSPI_SR_AHB2FUL_MASK (0x2000U) +#define QuadSPI_SR_AHB2FUL_SHIFT (13U) +#define QuadSPI_SR_AHB2FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2FUL_SHIFT)) & QuadSPI_SR_AHB2FUL_MASK) +#define QuadSPI_SR_AHB3FUL_MASK (0x4000U) +#define QuadSPI_SR_AHB3FUL_SHIFT (14U) +#define QuadSPI_SR_AHB3FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3FUL_SHIFT)) & QuadSPI_SR_AHB3FUL_MASK) +#define QuadSPI_SR_RXWE_MASK (0x10000U) +#define QuadSPI_SR_RXWE_SHIFT (16U) +#define QuadSPI_SR_RXWE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK) +#define QuadSPI_SR_RXFULL_MASK (0x80000U) +#define QuadSPI_SR_RXFULL_SHIFT (19U) +#define QuadSPI_SR_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK) +#define QuadSPI_SR_RXDMA_MASK (0x800000U) +#define QuadSPI_SR_RXDMA_SHIFT (23U) +#define QuadSPI_SR_RXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXDMA_SHIFT)) & QuadSPI_SR_RXDMA_MASK) +#define QuadSPI_SR_TXEDA_MASK (0x1000000U) +#define QuadSPI_SR_TXEDA_SHIFT (24U) +#define QuadSPI_SR_TXEDA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXEDA_SHIFT)) & QuadSPI_SR_TXEDA_MASK) +#define QuadSPI_SR_TXFULL_MASK (0x8000000U) +#define QuadSPI_SR_TXFULL_SHIFT (27U) +#define QuadSPI_SR_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK) +#define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) +#define QuadSPI_SR_DLPSMP_SHIFT (29U) +#define QuadSPI_SR_DLPSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK) + +/*! @name FR - Flag Register */ +#define QuadSPI_FR_TFF_MASK (0x1U) +#define QuadSPI_FR_TFF_SHIFT (0U) +#define QuadSPI_FR_TFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TFF_SHIFT)) & QuadSPI_FR_TFF_MASK) +#define QuadSPI_FR_IPGEF_MASK (0x10U) +#define QuadSPI_FR_IPGEF_SHIFT (4U) +#define QuadSPI_FR_IPGEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPGEF_SHIFT)) & QuadSPI_FR_IPGEF_MASK) +#define QuadSPI_FR_IPIEF_MASK (0x40U) +#define QuadSPI_FR_IPIEF_SHIFT (6U) +#define QuadSPI_FR_IPIEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPIEF_SHIFT)) & QuadSPI_FR_IPIEF_MASK) +#define QuadSPI_FR_IPAEF_MASK (0x80U) +#define QuadSPI_FR_IPAEF_SHIFT (7U) +#define QuadSPI_FR_IPAEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPAEF_SHIFT)) & QuadSPI_FR_IPAEF_MASK) +#define QuadSPI_FR_IUEF_MASK (0x800U) +#define QuadSPI_FR_IUEF_SHIFT (11U) +#define QuadSPI_FR_IUEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IUEF_SHIFT)) & QuadSPI_FR_IUEF_MASK) +#define QuadSPI_FR_ABOF_MASK (0x1000U) +#define QuadSPI_FR_ABOF_SHIFT (12U) +#define QuadSPI_FR_ABOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABOF_SHIFT)) & QuadSPI_FR_ABOF_MASK) +#define QuadSPI_FR_ABSEF_MASK (0x8000U) +#define QuadSPI_FR_ABSEF_SHIFT (15U) +#define QuadSPI_FR_ABSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK) +#define QuadSPI_FR_RBDF_MASK (0x10000U) +#define QuadSPI_FR_RBDF_SHIFT (16U) +#define QuadSPI_FR_RBDF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBDF_SHIFT)) & QuadSPI_FR_RBDF_MASK) +#define QuadSPI_FR_RBOF_MASK (0x20000U) +#define QuadSPI_FR_RBOF_SHIFT (17U) +#define QuadSPI_FR_RBOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBOF_SHIFT)) & QuadSPI_FR_RBOF_MASK) +#define QuadSPI_FR_ILLINE_MASK (0x800000U) +#define QuadSPI_FR_ILLINE_SHIFT (23U) +#define QuadSPI_FR_ILLINE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK) +#define QuadSPI_FR_TBUF_MASK (0x4000000U) +#define QuadSPI_FR_TBUF_SHIFT (26U) +#define QuadSPI_FR_TBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBUF_SHIFT)) & QuadSPI_FR_TBUF_MASK) +#define QuadSPI_FR_TBFF_MASK (0x8000000U) +#define QuadSPI_FR_TBFF_SHIFT (27U) +#define QuadSPI_FR_TBFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBFF_SHIFT)) & QuadSPI_FR_TBFF_MASK) +#define QuadSPI_FR_DLPFF_MASK (0x80000000U) +#define QuadSPI_FR_DLPFF_SHIFT (31U) +#define QuadSPI_FR_DLPFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_DLPFF_SHIFT)) & QuadSPI_FR_DLPFF_MASK) + +/*! @name RSER - Interrupt and DMA Request Select and Enable Register */ +#define QuadSPI_RSER_TFIE_MASK (0x1U) +#define QuadSPI_RSER_TFIE_SHIFT (0U) +#define QuadSPI_RSER_TFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TFIE_SHIFT)) & QuadSPI_RSER_TFIE_MASK) +#define QuadSPI_RSER_IPGEIE_MASK (0x10U) +#define QuadSPI_RSER_IPGEIE_SHIFT (4U) +#define QuadSPI_RSER_IPGEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPGEIE_SHIFT)) & QuadSPI_RSER_IPGEIE_MASK) +#define QuadSPI_RSER_IPIEIE_MASK (0x40U) +#define QuadSPI_RSER_IPIEIE_SHIFT (6U) +#define QuadSPI_RSER_IPIEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPIEIE_SHIFT)) & QuadSPI_RSER_IPIEIE_MASK) +#define QuadSPI_RSER_IPAEIE_MASK (0x80U) +#define QuadSPI_RSER_IPAEIE_SHIFT (7U) +#define QuadSPI_RSER_IPAEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPAEIE_SHIFT)) & QuadSPI_RSER_IPAEIE_MASK) +#define QuadSPI_RSER_IUEIE_MASK (0x800U) +#define QuadSPI_RSER_IUEIE_SHIFT (11U) +#define QuadSPI_RSER_IUEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IUEIE_SHIFT)) & QuadSPI_RSER_IUEIE_MASK) +#define QuadSPI_RSER_ABOIE_MASK (0x1000U) +#define QuadSPI_RSER_ABOIE_SHIFT (12U) +#define QuadSPI_RSER_ABOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABOIE_SHIFT)) & QuadSPI_RSER_ABOIE_MASK) +#define QuadSPI_RSER_ABSEIE_MASK (0x8000U) +#define QuadSPI_RSER_ABSEIE_SHIFT (15U) +#define QuadSPI_RSER_ABSEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABSEIE_SHIFT)) & QuadSPI_RSER_ABSEIE_MASK) +#define QuadSPI_RSER_RBDIE_MASK (0x10000U) +#define QuadSPI_RSER_RBDIE_SHIFT (16U) +#define QuadSPI_RSER_RBDIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDIE_SHIFT)) & QuadSPI_RSER_RBDIE_MASK) +#define QuadSPI_RSER_RBOIE_MASK (0x20000U) +#define QuadSPI_RSER_RBOIE_SHIFT (17U) +#define QuadSPI_RSER_RBOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBOIE_SHIFT)) & QuadSPI_RSER_RBOIE_MASK) +#define QuadSPI_RSER_RBDDE_MASK (0x200000U) +#define QuadSPI_RSER_RBDDE_SHIFT (21U) +#define QuadSPI_RSER_RBDDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDDE_SHIFT)) & QuadSPI_RSER_RBDDE_MASK) +#define QuadSPI_RSER_ILLINIE_MASK (0x800000U) +#define QuadSPI_RSER_ILLINIE_SHIFT (23U) +#define QuadSPI_RSER_ILLINIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ILLINIE_SHIFT)) & QuadSPI_RSER_ILLINIE_MASK) +#define QuadSPI_RSER_TBUIE_MASK (0x4000000U) +#define QuadSPI_RSER_TBUIE_SHIFT (26U) +#define QuadSPI_RSER_TBUIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBUIE_SHIFT)) & QuadSPI_RSER_TBUIE_MASK) +#define QuadSPI_RSER_TBFIE_MASK (0x8000000U) +#define QuadSPI_RSER_TBFIE_SHIFT (27U) +#define QuadSPI_RSER_TBFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFIE_SHIFT)) & QuadSPI_RSER_TBFIE_MASK) +#define QuadSPI_RSER_DLPFIE_MASK (0x80000000U) +#define QuadSPI_RSER_DLPFIE_SHIFT (31U) +#define QuadSPI_RSER_DLPFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_DLPFIE_SHIFT)) & QuadSPI_RSER_DLPFIE_MASK) + +/*! @name SPNDST - Sequence Suspend Status Register */ +#define QuadSPI_SPNDST_SUSPND_MASK (0x1U) +#define QuadSPI_SPNDST_SUSPND_SHIFT (0U) +#define QuadSPI_SPNDST_SUSPND(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SUSPND_SHIFT)) & QuadSPI_SPNDST_SUSPND_MASK) +#define QuadSPI_SPNDST_SPDBUF_MASK (0xC0U) +#define QuadSPI_SPNDST_SPDBUF_SHIFT (6U) +#define QuadSPI_SPNDST_SPDBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SPDBUF_SHIFT)) & QuadSPI_SPNDST_SPDBUF_MASK) +#define QuadSPI_SPNDST_DATLFT_MASK (0xFE00U) +#define QuadSPI_SPNDST_DATLFT_SHIFT (9U) +#define QuadSPI_SPNDST_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_DATLFT_SHIFT)) & QuadSPI_SPNDST_DATLFT_MASK) + +/*! @name SPTRCLR - Sequence Pointer Clear Register */ +#define QuadSPI_SPTRCLR_BFPTRC_MASK (0x1U) +#define QuadSPI_SPTRCLR_BFPTRC_SHIFT (0U) +#define QuadSPI_SPTRCLR_BFPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_BFPTRC_SHIFT)) & QuadSPI_SPTRCLR_BFPTRC_MASK) +#define QuadSPI_SPTRCLR_IPPTRC_MASK (0x100U) +#define QuadSPI_SPTRCLR_IPPTRC_SHIFT (8U) +#define QuadSPI_SPTRCLR_IPPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_IPPTRC_SHIFT)) & QuadSPI_SPTRCLR_IPPTRC_MASK) + +/*! @name SFA1AD - Serial Flash A1 Top Address */ +#define QuadSPI_SFA1AD_TPADA1_MASK (0xFFFFFC00U) +#define QuadSPI_SFA1AD_TPADA1_SHIFT (10U) +#define QuadSPI_SFA1AD_TPADA1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA1AD_TPADA1_SHIFT)) & QuadSPI_SFA1AD_TPADA1_MASK) + +/*! @name SFA2AD - Serial Flash A2 Top Address */ +#define QuadSPI_SFA2AD_TPADA2_MASK (0xFFFFFC00U) +#define QuadSPI_SFA2AD_TPADA2_SHIFT (10U) +#define QuadSPI_SFA2AD_TPADA2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA2AD_TPADA2_SHIFT)) & QuadSPI_SFA2AD_TPADA2_MASK) + +/*! @name SFB1AD - Serial Flash B1Top Address */ +#define QuadSPI_SFB1AD_TPADB1_MASK (0xFFFFFC00U) +#define QuadSPI_SFB1AD_TPADB1_SHIFT (10U) +#define QuadSPI_SFB1AD_TPADB1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB1AD_TPADB1_SHIFT)) & QuadSPI_SFB1AD_TPADB1_MASK) + +/*! @name SFB2AD - Serial Flash B2Top Address */ +#define QuadSPI_SFB2AD_TPADB2_MASK (0xFFFFFC00U) +#define QuadSPI_SFB2AD_TPADB2_SHIFT (10U) +#define QuadSPI_SFB2AD_TPADB2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB2AD_TPADB2_SHIFT)) & QuadSPI_SFB2AD_TPADB2_MASK) + +/*! @name RBDR - RX Buffer Data Register */ +#define QuadSPI_RBDR_RXDATA_MASK (0xFFFFFFFFU) +#define QuadSPI_RBDR_RXDATA_SHIFT (0U) +#define QuadSPI_RBDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBDR_RXDATA_SHIFT)) & QuadSPI_RBDR_RXDATA_MASK) + +/* The count of QuadSPI_RBDR */ +#define QuadSPI_RBDR_COUNT (32U) + +/*! @name LUTKEY - LUT Key Register */ +#define QuadSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) +#define QuadSPI_LUTKEY_KEY_SHIFT (0U) +#define QuadSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUTKEY_KEY_SHIFT)) & QuadSPI_LUTKEY_KEY_MASK) + +/*! @name LCKCR - LUT Lock Configuration Register */ +#define QuadSPI_LCKCR_LOCK_MASK (0x1U) +#define QuadSPI_LCKCR_LOCK_SHIFT (0U) +#define QuadSPI_LCKCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK) +#define QuadSPI_LCKCR_UNLOCK_MASK (0x2U) +#define QuadSPI_LCKCR_UNLOCK_SHIFT (1U) +#define QuadSPI_LCKCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_UNLOCK_SHIFT)) & QuadSPI_LCKCR_UNLOCK_MASK) + +/*! @name LUT - Look-up Table register */ +#define QuadSPI_LUT_OPRND0_MASK (0xFFU) +#define QuadSPI_LUT_OPRND0_SHIFT (0U) +#define QuadSPI_LUT_OPRND0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND0_SHIFT)) & QuadSPI_LUT_OPRND0_MASK) +#define QuadSPI_LUT_PAD0_MASK (0x300U) +#define QuadSPI_LUT_PAD0_SHIFT (8U) +#define QuadSPI_LUT_PAD0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD0_SHIFT)) & QuadSPI_LUT_PAD0_MASK) +#define QuadSPI_LUT_INSTR0_MASK (0xFC00U) +#define QuadSPI_LUT_INSTR0_SHIFT (10U) +#define QuadSPI_LUT_INSTR0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR0_SHIFT)) & QuadSPI_LUT_INSTR0_MASK) +#define QuadSPI_LUT_OPRND1_MASK (0xFF0000U) +#define QuadSPI_LUT_OPRND1_SHIFT (16U) +#define QuadSPI_LUT_OPRND1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND1_SHIFT)) & QuadSPI_LUT_OPRND1_MASK) +#define QuadSPI_LUT_PAD1_MASK (0x3000000U) +#define QuadSPI_LUT_PAD1_SHIFT (24U) +#define QuadSPI_LUT_PAD1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD1_SHIFT)) & QuadSPI_LUT_PAD1_MASK) +#define QuadSPI_LUT_INSTR1_MASK (0xFC000000U) +#define QuadSPI_LUT_INSTR1_SHIFT (26U) +#define QuadSPI_LUT_INSTR1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR1_SHIFT)) & QuadSPI_LUT_INSTR1_MASK) + +/* The count of QuadSPI_LUT */ +#define QuadSPI_LUT_COUNT (64U) + + +/*! + * @} + */ /* end of group QuadSPI_Register_Masks */ + + +/* QuadSPI - Peripheral instance base addresses */ +/** Peripheral QuadSPI base address */ +#define QuadSPI_BASE (0x21E0000u) +/** Peripheral QuadSPI base pointer */ +#define QuadSPI ((QuadSPI_Type *)QuadSPI_BASE) +/** Array initializer of QuadSPI peripheral base addresses */ +#define QuadSPI_BASE_ADDRS { QuadSPI_BASE } +/** Array initializer of QuadSPI peripheral base pointers */ +#define QuadSPI_BASE_PTRS { QuadSPI } +/** Interrupt vectors for the QuadSPI peripheral type */ +#define QuadSPI_IRQS { QSPI_IRQn } + +/*! + * @} + */ /* end of group QuadSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer + * @{ + */ + +/** RNG - Register Layout Typedef */ +typedef struct { + __I uint32_t VER; /**< RNGB version ID register, offset: 0x0 */ + __IO uint32_t CMD; /**< RNGB command register, offset: 0x4 */ + __IO uint32_t CR; /**< RNGB control register, offset: 0x8 */ + __I uint32_t SR; /**< RNGB status register, offset: 0xC */ + __I uint32_t ESR; /**< RNGB error status register, offset: 0x10 */ + __I uint32_t OUT; /**< RNGB Output FIFO, offset: 0x14 */ +} RNG_Type; + +/* ---------------------------------------------------------------------------- + -- RNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RNG_Register_Masks RNG Register Masks + * @{ + */ + +/*! @name VER - RNGB version ID register */ +#define RNG_VER_MINOR_MASK (0xFFU) +#define RNG_VER_MINOR_SHIFT (0U) +#define RNG_VER_MINOR(x) (((uint32_t)(((uint32_t)(x)) << RNG_VER_MINOR_SHIFT)) & RNG_VER_MINOR_MASK) +#define RNG_VER_MAJOR_MASK (0xFF00U) +#define RNG_VER_MAJOR_SHIFT (8U) +#define RNG_VER_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << RNG_VER_MAJOR_SHIFT)) & RNG_VER_MAJOR_MASK) +#define RNG_VER_TYPE_MASK (0xF0000000U) +#define RNG_VER_TYPE_SHIFT (28U) +#define RNG_VER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << RNG_VER_TYPE_SHIFT)) & RNG_VER_TYPE_MASK) + +/*! @name CMD - RNGB command register */ +#define RNG_CMD_ST_MASK (0x1U) +#define RNG_CMD_ST_SHIFT (0U) +#define RNG_CMD_ST(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_ST_SHIFT)) & RNG_CMD_ST_MASK) +#define RNG_CMD_GS_MASK (0x2U) +#define RNG_CMD_GS_SHIFT (1U) +#define RNG_CMD_GS(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_GS_SHIFT)) & RNG_CMD_GS_MASK) +#define RNG_CMD_CI_MASK (0x10U) +#define RNG_CMD_CI_SHIFT (4U) +#define RNG_CMD_CI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_CI_SHIFT)) & RNG_CMD_CI_MASK) +#define RNG_CMD_CE_MASK (0x20U) +#define RNG_CMD_CE_SHIFT (5U) +#define RNG_CMD_CE(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_CE_SHIFT)) & RNG_CMD_CE_MASK) +#define RNG_CMD_SR_MASK (0x40U) +#define RNG_CMD_SR_SHIFT (6U) +#define RNG_CMD_SR(x) (((uint32_t)(((uint32_t)(x)) << RNG_CMD_SR_SHIFT)) & RNG_CMD_SR_MASK) + +/*! @name CR - RNGB control register */ +#define RNG_CR_FUFMOD_MASK (0x3U) +#define RNG_CR_FUFMOD_SHIFT (0U) +#define RNG_CR_FUFMOD(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_FUFMOD_SHIFT)) & RNG_CR_FUFMOD_MASK) +#define RNG_CR_AR_MASK (0x10U) +#define RNG_CR_AR_SHIFT (4U) +#define RNG_CR_AR(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_AR_SHIFT)) & RNG_CR_AR_MASK) +#define RNG_CR_MASKDONE_MASK (0x20U) +#define RNG_CR_MASKDONE_SHIFT (5U) +#define RNG_CR_MASKDONE(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_MASKDONE_SHIFT)) & RNG_CR_MASKDONE_MASK) +#define RNG_CR_MASKERR_MASK (0x40U) +#define RNG_CR_MASKERR_SHIFT (6U) +#define RNG_CR_MASKERR(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_MASKERR_SHIFT)) & RNG_CR_MASKERR_MASK) + +/*! @name SR - RNGB status register */ +#define RNG_SR_BUSY_MASK (0x2U) +#define RNG_SR_BUSY_SHIFT (1U) +#define RNG_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_BUSY_SHIFT)) & RNG_SR_BUSY_MASK) +#define RNG_SR_SLP_MASK (0x4U) +#define RNG_SR_SLP_SHIFT (2U) +#define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK) +#define RNG_SR_RS_MASK (0x8U) +#define RNG_SR_RS_SHIFT (3U) +#define RNG_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_RS_SHIFT)) & RNG_SR_RS_MASK) +#define RNG_SR_STDN_MASK (0x10U) +#define RNG_SR_STDN_SHIFT (4U) +#define RNG_SR_STDN(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_STDN_SHIFT)) & RNG_SR_STDN_MASK) +#define RNG_SR_SDN_MASK (0x20U) +#define RNG_SR_SDN_SHIFT (5U) +#define RNG_SR_SDN(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SDN_SHIFT)) & RNG_SR_SDN_MASK) +#define RNG_SR_NSDN_MASK (0x40U) +#define RNG_SR_NSDN_SHIFT (6U) +#define RNG_SR_NSDN(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_NSDN_SHIFT)) & RNG_SR_NSDN_MASK) +#define RNG_SR_FIFO_LVL_MASK (0xF00U) +#define RNG_SR_FIFO_LVL_SHIFT (8U) +#define RNG_SR_FIFO_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_FIFO_LVL_SHIFT)) & RNG_SR_FIFO_LVL_MASK) +#define RNG_SR_FIFO_SIZE_MASK (0xF000U) +#define RNG_SR_FIFO_SIZE_SHIFT (12U) +#define RNG_SR_FIFO_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_FIFO_SIZE_SHIFT)) & RNG_SR_FIFO_SIZE_MASK) +#define RNG_SR_ERR_MASK (0x10000U) +#define RNG_SR_ERR_SHIFT (16U) +#define RNG_SR_ERR(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERR_SHIFT)) & RNG_SR_ERR_MASK) +#define RNG_SR_ST_PF_MASK (0xE00000U) +#define RNG_SR_ST_PF_SHIFT (21U) +#define RNG_SR_ST_PF(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ST_PF_SHIFT)) & RNG_SR_ST_PF_MASK) +#define RNG_SR_STATPF_MASK (0xFF000000U) +#define RNG_SR_STATPF_SHIFT (24U) +#define RNG_SR_STATPF(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_STATPF_SHIFT)) & RNG_SR_STATPF_MASK) + +/*! @name ESR - RNGB error status register */ +#define RNG_ESR_LFE_MASK (0x1U) +#define RNG_ESR_LFE_SHIFT (0U) +#define RNG_ESR_LFE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_LFE_SHIFT)) & RNG_ESR_LFE_MASK) +#define RNG_ESR_OSCE_MASK (0x2U) +#define RNG_ESR_OSCE_SHIFT (1U) +#define RNG_ESR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_OSCE_SHIFT)) & RNG_ESR_OSCE_MASK) +#define RNG_ESR_STE_MASK (0x4U) +#define RNG_ESR_STE_SHIFT (2U) +#define RNG_ESR_STE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_STE_SHIFT)) & RNG_ESR_STE_MASK) +#define RNG_ESR_SATE_MASK (0x8U) +#define RNG_ESR_SATE_SHIFT (3U) +#define RNG_ESR_SATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_SATE_SHIFT)) & RNG_ESR_SATE_MASK) +#define RNG_ESR_FUFE_MASK (0x10U) +#define RNG_ESR_FUFE_SHIFT (4U) +#define RNG_ESR_FUFE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ESR_FUFE_SHIFT)) & RNG_ESR_FUFE_MASK) + +/*! @name OUT - RNGB Output FIFO */ +#define RNG_OUT_RANDOUT_MASK (0xFFFFFFFFU) +#define RNG_OUT_RANDOUT_SHIFT (0U) +#define RNG_OUT_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OUT_RANDOUT_SHIFT)) & RNG_OUT_RANDOUT_MASK) + + +/*! + * @} + */ /* end of group RNG_Register_Masks */ + + +/* RNG - Peripheral instance base addresses */ +/** Peripheral RNG base address */ +#define RNG_BASE (0x2284000u) +/** Peripheral RNG base pointer */ +#define RNG ((RNG_Type *)RNG_BASE) +/** Array initializer of RNG peripheral base addresses */ +#define RNG_BASE_ADDRS { RNG_BASE } +/** Array initializer of RNG peripheral base pointers */ +#define RNG_BASE_PTRS { RNG } + +/*! + * @} + */ /* end of group RNG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ROMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer + * @{ + */ + +/** ROMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[212]; + __IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */ + __IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */ + __I uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */ + __IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */ + __IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_1[200]; + __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */ +} ROMC_Type; + +/* ---------------------------------------------------------------------------- + -- ROMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Register_Masks ROMC Register Masks + * @{ + */ + +/*! @name ROMPATCHD - ROMC Data Registers */ +#define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) +#define ROMC_ROMPATCHD_DATAX_SHIFT (0U) +#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK) + +/* The count of ROMC_ROMPATCHD */ +#define ROMC_ROMPATCHD_COUNT (8U) + +/*! @name ROMPATCHCNTL - ROMC Control Register */ +#define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU) +#define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U) +#define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK) +#define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U) +#define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U) +#define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK) + +/*! @name ROMPATCHENL - ROMC Enable Register Low */ +#define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU) +#define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U) +#define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK) + +/*! @name ROMPATCHA - ROMC Address Registers */ +#define ROMC_ROMPATCHA_THUMBX_MASK (0x1U) +#define ROMC_ROMPATCHA_THUMBX_SHIFT (0U) +#define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK) +#define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) +#define ROMC_ROMPATCHA_ADDRX_SHIFT (1U) +#define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK) + +/* The count of ROMC_ROMPATCHA */ +#define ROMC_ROMPATCHA_COUNT (16U) + +/*! @name ROMPATCHSR - ROMC Status Register */ +#define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU) +#define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U) +#define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK) +#define ROMC_ROMPATCHSR_SW_MASK (0x20000U) +#define ROMC_ROMPATCHSR_SW_SHIFT (17U) +#define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) + + +/*! + * @} + */ /* end of group ROMC_Register_Masks */ + + +/* ROMC - Peripheral instance base addresses */ +/** Peripheral ROMC base address */ +#define ROMC_BASE (0x21AC000u) +/** Peripheral ROMC base pointer */ +#define ROMC ((ROMC_Type *)ROMC_BASE) +/** Array initializer of ROMC peripheral base addresses */ +#define ROMC_BASE_ADDRS { ROMC_BASE } +/** Array initializer of ROMC peripheral base pointers */ +#define ROMC_BASE_PTRS { ROMC } + +/*! + * @} + */ /* end of group ROMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SDMAARM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMAARM_Peripheral_Access_Layer SDMAARM Peripheral Access Layer + * @{ + */ + +/** SDMAARM - Register Layout Typedef */ +typedef struct { + __IO uint32_t MC0PTR; /**< ARM platform Channel 0 Pointer, offset: 0x0 */ + __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */ + __IO uint32_t STOP_STAT; /**< Channel Stop/Channel Status, offset: 0x8 */ + __IO uint32_t HSTART; /**< Channel Start, offset: 0xC */ + __IO uint32_t EVTOVR; /**< Channel Event Override, offset: 0x10 */ + __IO uint32_t DSPOVR; /**< Channel BP Override, offset: 0x14 */ + __IO uint32_t HOSTOVR; /**< Channel ARM platform Override, offset: 0x18 */ + __IO uint32_t EVTPEND; /**< Channel Event Pending, offset: 0x1C */ + uint8_t RESERVED_0[4]; + __I uint32_t RESET; /**< Reset Register, offset: 0x24 */ + __I uint32_t EVTERR; /**< DMA Request Error Register, offset: 0x28 */ + __IO uint32_t INTRMASK; /**< Channel ARM platform Interrupt Mask, offset: 0x2C */ + __I uint32_t PSW; /**< Schedule Status, offset: 0x30 */ + __I uint32_t EVTERRDBG; /**< DMA Request Error Register, offset: 0x34 */ + __IO uint32_t CONFIG; /**< Configuration Register, offset: 0x38 */ + __IO uint32_t SDMA_LOCK; /**< SDMA LOCK, offset: 0x3C */ + __IO uint32_t ONCE_ENB; /**< OnCE Enable, offset: 0x40 */ + __IO uint32_t ONCE_DATA; /**< OnCE Data Register, offset: 0x44 */ + __IO uint32_t ONCE_INSTR; /**< OnCE Instruction Register, offset: 0x48 */ + __I uint32_t ONCE_STAT; /**< OnCE Status Register, offset: 0x4C */ + __IO uint32_t ONCE_CMD; /**< OnCE Command Register, offset: 0x50 */ + uint8_t RESERVED_1[4]; + __IO uint32_t ILLINSTADDR; /**< Illegal Instruction Trap Address, offset: 0x58 */ + __IO uint32_t CHN0ADDR; /**< Channel 0 Boot Address, offset: 0x5C */ + __I uint32_t EVT_MIRROR; /**< DMA Requests, offset: 0x60 */ + __I uint32_t EVT_MIRROR2; /**< DMA Requests 2, offset: 0x64 */ + uint8_t RESERVED_2[8]; + __IO uint32_t XTRIG_CONF1; /**< Cross-Trigger Events Configuration Register 1, offset: 0x70 */ + __IO uint32_t XTRIG_CONF2; /**< Cross-Trigger Events Configuration Register 2, offset: 0x74 */ + uint8_t RESERVED_3[136]; + __IO uint32_t SDMA_CHNPRI[32]; /**< Channel Priority Registers, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_4[128]; + __IO uint32_t CHNENBL[48]; /**< Channel Enable RAM, array offset: 0x200, array step: 0x4 */ +} SDMAARM_Type; + +/* ---------------------------------------------------------------------------- + -- SDMAARM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks + * @{ + */ + +/*! @name MC0PTR - ARM platform Channel 0 Pointer */ +#define SDMAARM_MC0PTR_MC0PTR_MASK (0xFFFFFFFFU) +#define SDMAARM_MC0PTR_MC0PTR_SHIFT (0U) +#define SDMAARM_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_MC0PTR_MC0PTR_SHIFT)) & SDMAARM_MC0PTR_MC0PTR_MASK) + +/*! @name INTR - Channel Interrupts */ +#define SDMAARM_INTR_HI_MASK (0xFFFFFFFFU) +#define SDMAARM_INTR_HI_SHIFT (0U) +#define SDMAARM_INTR_HI(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTR_HI_SHIFT)) & SDMAARM_INTR_HI_MASK) + +/*! @name STOP_STAT - Channel Stop/Channel Status */ +#define SDMAARM_STOP_STAT_HE_MASK (0xFFFFFFFFU) +#define SDMAARM_STOP_STAT_HE_SHIFT (0U) +#define SDMAARM_STOP_STAT_HE(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_STOP_STAT_HE_SHIFT)) & SDMAARM_STOP_STAT_HE_MASK) + +/*! @name HSTART - Channel Start */ +#define SDMAARM_HSTART_HSTART_HE_MASK (0xFFFFFFFFU) +#define SDMAARM_HSTART_HSTART_HE_SHIFT (0U) +#define SDMAARM_HSTART_HSTART_HE(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_HSTART_HSTART_HE_SHIFT)) & SDMAARM_HSTART_HSTART_HE_MASK) + +/*! @name EVTOVR - Channel Event Override */ +#define SDMAARM_EVTOVR_EO_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTOVR_EO_SHIFT (0U) +#define SDMAARM_EVTOVR_EO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTOVR_EO_SHIFT)) & SDMAARM_EVTOVR_EO_MASK) + +/*! @name DSPOVR - Channel BP Override */ +#define SDMAARM_DSPOVR_DO_MASK (0xFFFFFFFFU) +#define SDMAARM_DSPOVR_DO_SHIFT (0U) +#define SDMAARM_DSPOVR_DO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DSPOVR_DO_SHIFT)) & SDMAARM_DSPOVR_DO_MASK) + +/*! @name HOSTOVR - Channel ARM platform Override */ +#define SDMAARM_HOSTOVR_HO_MASK (0xFFFFFFFFU) +#define SDMAARM_HOSTOVR_HO_SHIFT (0U) +#define SDMAARM_HOSTOVR_HO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_HOSTOVR_HO_SHIFT)) & SDMAARM_HOSTOVR_HO_MASK) + +/*! @name EVTPEND - Channel Event Pending */ +#define SDMAARM_EVTPEND_EP_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTPEND_EP_SHIFT (0U) +#define SDMAARM_EVTPEND_EP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTPEND_EP_SHIFT)) & SDMAARM_EVTPEND_EP_MASK) + +/*! @name RESET - Reset Register */ +#define SDMAARM_RESET_RESET_MASK (0x1U) +#define SDMAARM_RESET_RESET_SHIFT (0U) +#define SDMAARM_RESET_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESET_SHIFT)) & SDMAARM_RESET_RESET_MASK) +#define SDMAARM_RESET_RESCHED_MASK (0x2U) +#define SDMAARM_RESET_RESCHED_SHIFT (1U) +#define SDMAARM_RESET_RESCHED(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESCHED_SHIFT)) & SDMAARM_RESET_RESCHED_MASK) + +/*! @name EVTERR - DMA Request Error Register */ +#define SDMAARM_EVTERR_CHNERR_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTERR_CHNERR_SHIFT (0U) +#define SDMAARM_EVTERR_CHNERR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERR_CHNERR_SHIFT)) & SDMAARM_EVTERR_CHNERR_MASK) + +/*! @name INTRMASK - Channel ARM platform Interrupt Mask */ +#define SDMAARM_INTRMASK_HIMASK_MASK (0xFFFFFFFFU) +#define SDMAARM_INTRMASK_HIMASK_SHIFT (0U) +#define SDMAARM_INTRMASK_HIMASK(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTRMASK_HIMASK_SHIFT)) & SDMAARM_INTRMASK_HIMASK_MASK) + +/*! @name PSW - Schedule Status */ +#define SDMAARM_PSW_CCR_MASK (0xFU) +#define SDMAARM_PSW_CCR_SHIFT (0U) +#define SDMAARM_PSW_CCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCR_SHIFT)) & SDMAARM_PSW_CCR_MASK) +#define SDMAARM_PSW_CCP_MASK (0xF0U) +#define SDMAARM_PSW_CCP_SHIFT (4U) +#define SDMAARM_PSW_CCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCP_SHIFT)) & SDMAARM_PSW_CCP_MASK) +#define SDMAARM_PSW_NCR_MASK (0x1F00U) +#define SDMAARM_PSW_NCR_SHIFT (8U) +#define SDMAARM_PSW_NCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCR_SHIFT)) & SDMAARM_PSW_NCR_MASK) +#define SDMAARM_PSW_NCP_MASK (0xE000U) +#define SDMAARM_PSW_NCP_SHIFT (13U) +#define SDMAARM_PSW_NCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCP_SHIFT)) & SDMAARM_PSW_NCP_MASK) + +/*! @name EVTERRDBG - DMA Request Error Register */ +#define SDMAARM_EVTERRDBG_CHNERR_MASK (0xFFFFFFFFU) +#define SDMAARM_EVTERRDBG_CHNERR_SHIFT (0U) +#define SDMAARM_EVTERRDBG_CHNERR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERRDBG_CHNERR_SHIFT)) & SDMAARM_EVTERRDBG_CHNERR_MASK) + +/*! @name CONFIG - Configuration Register */ +#define SDMAARM_CONFIG_CSM_MASK (0x3U) +#define SDMAARM_CONFIG_CSM_SHIFT (0U) +#define SDMAARM_CONFIG_CSM(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_CSM_SHIFT)) & SDMAARM_CONFIG_CSM_MASK) +#define SDMAARM_CONFIG_ACR_MASK (0x10U) +#define SDMAARM_CONFIG_ACR_SHIFT (4U) +#define SDMAARM_CONFIG_ACR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_ACR_SHIFT)) & SDMAARM_CONFIG_ACR_MASK) +#define SDMAARM_CONFIG_RTDOBS_MASK (0x800U) +#define SDMAARM_CONFIG_RTDOBS_SHIFT (11U) +#define SDMAARM_CONFIG_RTDOBS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_RTDOBS_SHIFT)) & SDMAARM_CONFIG_RTDOBS_MASK) +#define SDMAARM_CONFIG_DSPDMA_MASK (0x1000U) +#define SDMAARM_CONFIG_DSPDMA_SHIFT (12U) +#define SDMAARM_CONFIG_DSPDMA(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_DSPDMA_SHIFT)) & SDMAARM_CONFIG_DSPDMA_MASK) + +/*! @name SDMA_LOCK - SDMA LOCK */ +#define SDMAARM_SDMA_LOCK_LOCK_MASK (0x1U) +#define SDMAARM_SDMA_LOCK_LOCK_SHIFT (0U) +#define SDMAARM_SDMA_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_LOCK_SHIFT)) & SDMAARM_SDMA_LOCK_LOCK_MASK) +#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK (0x2U) +#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT (1U) +#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT)) & SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK) + +/*! @name ONCE_ENB - OnCE Enable */ +#define SDMAARM_ONCE_ENB_ENB_MASK (0x1U) +#define SDMAARM_ONCE_ENB_ENB_SHIFT (0U) +#define SDMAARM_ONCE_ENB_ENB(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_ENB_ENB_SHIFT)) & SDMAARM_ONCE_ENB_ENB_MASK) + +/*! @name ONCE_DATA - OnCE Data Register */ +#define SDMAARM_ONCE_DATA_DATA_MASK (0xFFFFFFFFU) +#define SDMAARM_ONCE_DATA_DATA_SHIFT (0U) +#define SDMAARM_ONCE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_DATA_DATA_SHIFT)) & SDMAARM_ONCE_DATA_DATA_MASK) + +/*! @name ONCE_INSTR - OnCE Instruction Register */ +#define SDMAARM_ONCE_INSTR_INSTR_MASK (0xFFFFU) +#define SDMAARM_ONCE_INSTR_INSTR_SHIFT (0U) +#define SDMAARM_ONCE_INSTR_INSTR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_INSTR_INSTR_SHIFT)) & SDMAARM_ONCE_INSTR_INSTR_MASK) + +/*! @name ONCE_STAT - OnCE Status Register */ +#define SDMAARM_ONCE_STAT_ECDR_MASK (0x7U) +#define SDMAARM_ONCE_STAT_ECDR_SHIFT (0U) +#define SDMAARM_ONCE_STAT_ECDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ECDR_SHIFT)) & SDMAARM_ONCE_STAT_ECDR_MASK) +#define SDMAARM_ONCE_STAT_MST_MASK (0x80U) +#define SDMAARM_ONCE_STAT_MST_SHIFT (7U) +#define SDMAARM_ONCE_STAT_MST(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_MST_SHIFT)) & SDMAARM_ONCE_STAT_MST_MASK) +#define SDMAARM_ONCE_STAT_SWB_MASK (0x100U) +#define SDMAARM_ONCE_STAT_SWB_SHIFT (8U) +#define SDMAARM_ONCE_STAT_SWB(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_SWB_SHIFT)) & SDMAARM_ONCE_STAT_SWB_MASK) +#define SDMAARM_ONCE_STAT_ODR_MASK (0x200U) +#define SDMAARM_ONCE_STAT_ODR_SHIFT (9U) +#define SDMAARM_ONCE_STAT_ODR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ODR_SHIFT)) & SDMAARM_ONCE_STAT_ODR_MASK) +#define SDMAARM_ONCE_STAT_EDR_MASK (0x400U) +#define SDMAARM_ONCE_STAT_EDR_SHIFT (10U) +#define SDMAARM_ONCE_STAT_EDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_EDR_SHIFT)) & SDMAARM_ONCE_STAT_EDR_MASK) +#define SDMAARM_ONCE_STAT_RCV_MASK (0x800U) +#define SDMAARM_ONCE_STAT_RCV_SHIFT (11U) +#define SDMAARM_ONCE_STAT_RCV(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_RCV_SHIFT)) & SDMAARM_ONCE_STAT_RCV_MASK) +#define SDMAARM_ONCE_STAT_PST_MASK (0xF000U) +#define SDMAARM_ONCE_STAT_PST_SHIFT (12U) +#define SDMAARM_ONCE_STAT_PST(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_PST_SHIFT)) & SDMAARM_ONCE_STAT_PST_MASK) + +/*! @name ONCE_CMD - OnCE Command Register */ +#define SDMAARM_ONCE_CMD_CMD_MASK (0xFU) +#define SDMAARM_ONCE_CMD_CMD_SHIFT (0U) +#define SDMAARM_ONCE_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_CMD_CMD_SHIFT)) & SDMAARM_ONCE_CMD_CMD_MASK) + +/*! @name ILLINSTADDR - Illegal Instruction Trap Address */ +#define SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK (0x3FFFU) +#define SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT (0U) +#define SDMAARM_ILLINSTADDR_ILLINSTADDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT)) & SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK) + +/*! @name CHN0ADDR - Channel 0 Boot Address */ +#define SDMAARM_CHN0ADDR_CHN0ADDR_MASK (0x3FFFU) +#define SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT (0U) +#define SDMAARM_CHN0ADDR_CHN0ADDR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT)) & SDMAARM_CHN0ADDR_CHN0ADDR_MASK) +#define SDMAARM_CHN0ADDR_SMSZ_MASK (0x4000U) +#define SDMAARM_CHN0ADDR_SMSZ_SHIFT (14U) +#define SDMAARM_CHN0ADDR_SMSZ(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_SMSZ_SHIFT)) & SDMAARM_CHN0ADDR_SMSZ_MASK) + +/*! @name EVT_MIRROR - DMA Requests */ +#define SDMAARM_EVT_MIRROR_EVENTS_MASK (0xFFFFFFFFU) +#define SDMAARM_EVT_MIRROR_EVENTS_SHIFT (0U) +#define SDMAARM_EVT_MIRROR_EVENTS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR_EVENTS_MASK) + +/*! @name EVT_MIRROR2 - DMA Requests 2 */ +#define SDMAARM_EVT_MIRROR2_EVENTS_MASK (0xFFFFU) +#define SDMAARM_EVT_MIRROR2_EVENTS_SHIFT (0U) +#define SDMAARM_EVT_MIRROR2_EVENTS(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR2_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR2_EVENTS_MASK) + +/*! @name XTRIG_CONF1 - Cross-Trigger Events Configuration Register 1 */ +#define SDMAARM_XTRIG_CONF1_NUM0_MASK (0x3FU) +#define SDMAARM_XTRIG_CONF1_NUM0_SHIFT (0U) +#define SDMAARM_XTRIG_CONF1_NUM0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM0_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM0_MASK) +#define SDMAARM_XTRIG_CONF1_CNF0_MASK (0x40U) +#define SDMAARM_XTRIG_CONF1_CNF0_SHIFT (6U) +#define SDMAARM_XTRIG_CONF1_CNF0(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF0_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF0_MASK) +#define SDMAARM_XTRIG_CONF1_NUM1_MASK (0x3F00U) +#define SDMAARM_XTRIG_CONF1_NUM1_SHIFT (8U) +#define SDMAARM_XTRIG_CONF1_NUM1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM1_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM1_MASK) +#define SDMAARM_XTRIG_CONF1_CNF1_MASK (0x4000U) +#define SDMAARM_XTRIG_CONF1_CNF1_SHIFT (14U) +#define SDMAARM_XTRIG_CONF1_CNF1(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF1_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF1_MASK) +#define SDMAARM_XTRIG_CONF1_NUM2_MASK (0x3F0000U) +#define SDMAARM_XTRIG_CONF1_NUM2_SHIFT (16U) +#define SDMAARM_XTRIG_CONF1_NUM2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM2_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM2_MASK) +#define SDMAARM_XTRIG_CONF1_CNF2_MASK (0x400000U) +#define SDMAARM_XTRIG_CONF1_CNF2_SHIFT (22U) +#define SDMAARM_XTRIG_CONF1_CNF2(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF2_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF2_MASK) +#define SDMAARM_XTRIG_CONF1_NUM3_MASK (0x3F000000U) +#define SDMAARM_XTRIG_CONF1_NUM3_SHIFT (24U) +#define SDMAARM_XTRIG_CONF1_NUM3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM3_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM3_MASK) +#define SDMAARM_XTRIG_CONF1_CNF3_MASK (0x40000000U) +#define SDMAARM_XTRIG_CONF1_CNF3_SHIFT (30U) +#define SDMAARM_XTRIG_CONF1_CNF3(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF3_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF3_MASK) + +/*! @name XTRIG_CONF2 - Cross-Trigger Events Configuration Register 2 */ +#define SDMAARM_XTRIG_CONF2_NUM4_MASK (0x3FU) +#define SDMAARM_XTRIG_CONF2_NUM4_SHIFT (0U) +#define SDMAARM_XTRIG_CONF2_NUM4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM4_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM4_MASK) +#define SDMAARM_XTRIG_CONF2_CNF4_MASK (0x40U) +#define SDMAARM_XTRIG_CONF2_CNF4_SHIFT (6U) +#define SDMAARM_XTRIG_CONF2_CNF4(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF4_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF4_MASK) +#define SDMAARM_XTRIG_CONF2_NUM5_MASK (0x3F00U) +#define SDMAARM_XTRIG_CONF2_NUM5_SHIFT (8U) +#define SDMAARM_XTRIG_CONF2_NUM5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM5_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM5_MASK) +#define SDMAARM_XTRIG_CONF2_CNF5_MASK (0x4000U) +#define SDMAARM_XTRIG_CONF2_CNF5_SHIFT (14U) +#define SDMAARM_XTRIG_CONF2_CNF5(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF5_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF5_MASK) +#define SDMAARM_XTRIG_CONF2_NUM6_MASK (0x3F0000U) +#define SDMAARM_XTRIG_CONF2_NUM6_SHIFT (16U) +#define SDMAARM_XTRIG_CONF2_NUM6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM6_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM6_MASK) +#define SDMAARM_XTRIG_CONF2_CNF6_MASK (0x400000U) +#define SDMAARM_XTRIG_CONF2_CNF6_SHIFT (22U) +#define SDMAARM_XTRIG_CONF2_CNF6(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF6_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF6_MASK) +#define SDMAARM_XTRIG_CONF2_NUM7_MASK (0x3F000000U) +#define SDMAARM_XTRIG_CONF2_NUM7_SHIFT (24U) +#define SDMAARM_XTRIG_CONF2_NUM7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM7_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM7_MASK) +#define SDMAARM_XTRIG_CONF2_CNF7_MASK (0x40000000U) +#define SDMAARM_XTRIG_CONF2_CNF7_SHIFT (30U) +#define SDMAARM_XTRIG_CONF2_CNF7(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF7_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF7_MASK) + +/*! @name SDMA_CHNPRI - Channel Priority Registers */ +#define SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK (0x7U) +#define SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT (0U) +#define SDMAARM_SDMA_CHNPRI_CHNPRIn(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT)) & SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK) + +/* The count of SDMAARM_SDMA_CHNPRI */ +#define SDMAARM_SDMA_CHNPRI_COUNT (32U) + +/*! @name CHNENBL - Channel Enable RAM */ +#define SDMAARM_CHNENBL_ENBLn_MASK (0xFFFFFFFFU) +#define SDMAARM_CHNENBL_ENBLn_SHIFT (0U) +#define SDMAARM_CHNENBL_ENBLn(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHNENBL_ENBLn_SHIFT)) & SDMAARM_CHNENBL_ENBLn_MASK) + +/* The count of SDMAARM_CHNENBL */ +#define SDMAARM_CHNENBL_COUNT (48U) + + +/*! + * @} + */ /* end of group SDMAARM_Register_Masks */ + + +/* SDMAARM - Peripheral instance base addresses */ +/** Peripheral SDMAARM base address */ +#define SDMAARM_BASE (0x20EC000u) +/** Peripheral SDMAARM base pointer */ +#define SDMAARM ((SDMAARM_Type *)SDMAARM_BASE) +/** Array initializer of SDMAARM peripheral base addresses */ +#define SDMAARM_BASE_ADDRS { SDMAARM_BASE } +/** Array initializer of SDMAARM peripheral base pointers */ +#define SDMAARM_BASE_PTRS { SDMAARM } +/** Interrupt vectors for the SDMAARM peripheral type */ +#define SDMAARM_IRQS { SDMA_IRQn } + +/*! + * @} + */ /* end of group SDMAARM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer + * @{ + */ + +/** SNVS - Register Layout Typedef */ +/* zuozhongkai 2018/12/13 */ +typedef struct { + __IO uint32_t HPLR; /**< SNVS_HP Lock register, offset: 0x0 */ + __IO uint32_t HPCOMR; /**< SNVS_HP Command register, offset: 0x4 */ + __IO uint32_t HPCR; /**< SNVS_HP Control register, offset: 0x8 */ + __IO uint32_t HPSICR; /**< SNVS_HP Control register, offset: 0x8 */ + __IO uint32_t HPSVCR; + __IO uint32_t HPSR; + __IO uint32_t HPSVSR; + __IO uint32_t HPHACIVR; + __IO uint32_t HPHACR; + __IO uint32_t HPRTCMR; + __IO uint32_t HPRTCLR; + __IO uint32_t HPTAMR; + __IO uint32_t HPTALR; + __IO uint32_t LPLR; + __IO uint32_t LPCR; + __IO uint32_t LPMKCR; + __IO uint32_t LPSVCR; + __IO uint32_t LPTGFCR; + __IO uint32_t LPTDCR; + __IO uint32_t LPSR; + __IO uint32_t LPSRTCMR; + __IO uint32_t LPSRTCLR; + __IO uint32_t LPTAR; + __IO uint32_t LPSMCMR; + __IO uint32_t LPSMCLR; +}SNVS_Type; + + +/* ---------------------------------------------------------------------------- + -- SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Register_Masks SNVS Register Masks + * @{ + */ + +/*! @name HPLR - SNVS_HP Lock register */ +#define SNVS_HPLR_MC_SL_MASK (0x10U) +#define SNVS_HPLR_MC_SL_SHIFT (4U) +#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK) +#define SNVS_HPLR_GPR_SL_MASK (0x20U) +#define SNVS_HPLR_GPR_SL_SHIFT (5U) +#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK) + +/*! @name HPCOMR - SNVS_HP Command register */ +#define SNVS_HPCOMR_LP_SWR_MASK (0x10U) +#define SNVS_HPCOMR_LP_SWR_SHIFT (4U) +#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK) +#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U) +#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U) +#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK) +#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) +#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) +#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) + +/*! @name HPCR - SNVS_HP Control register */ +#define SNVS_HPCR_RTC_EN_MASK (0x1U) +#define SNVS_HPCR_RTC_EN_SHIFT (0U) +#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) +#define SNVS_HPCR_HPTA_EN_MASK (0x2U) +#define SNVS_HPCR_HPTA_EN_SHIFT (1U) +#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) +#define SNVS_HPCR_PI_EN_MASK (0x8U) +#define SNVS_HPCR_PI_EN_SHIFT (3U) +#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) +#define SNVS_HPCR_PI_FREQ_MASK (0xF0U) +#define SNVS_HPCR_PI_FREQ_SHIFT (4U) +#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK) +#define SNVS_HPCR_HPCALB_EN_MASK (0x100U) +#define SNVS_HPCR_HPCALB_EN_SHIFT (8U) +#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) +#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) +#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U) +#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) +#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U) +#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U) +#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK) +#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U) +#define SNVS_HPCR_BTN_MASK_SHIFT (27U) +#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) + +/*! @name HPSR - SNVS_HP Status register */ +#define SNVS_HPSR_BTN_MASK (0x40U) +#define SNVS_HPSR_BTN_SHIFT (6U) +#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK) +#define SNVS_HPSR_BI_MASK (0x80U) +#define SNVS_HPSR_BI_SHIFT (7U) +#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK) + +/*! @name HPRTCMR - SNVS_HP Real-Time Counter MSB Register */ +#define SNVS_HPRTCMR_RTC_MASK (0xFFFFFFFFU) +#define SNVS_HPRTCMR_RTC_SHIFT (0U) +#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) + +/*! @name HPRTCLR - SNVS_HP Real-Time Counter LSB Register */ +#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) +#define SNVS_HPRTCLR_RTC_SHIFT (0U) +#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) + +/*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ +#define SNVS_HPTAMR_HPTA_MASK (0x7FFFU) +#define SNVS_HPTAMR_HPTA_SHIFT (0U) +#define SNVS_HPTAMR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_SHIFT)) & SNVS_HPTAMR_HPTA_MASK) + +/*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ +#define SNVS_HPTALR_HPTA_MASK (0xFFFFFFFFU) +#define SNVS_HPTALR_HPTA_SHIFT (0U) +#define SNVS_HPTALR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_SHIFT)) & SNVS_HPTALR_HPTA_MASK) + +/*! @name LPLR - SNVS_LP Lock Register */ +#define SNVS_LPLR_MC_HL_MASK (0x10U) +#define SNVS_LPLR_MC_HL_SHIFT (4U) +#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) +#define SNVS_LPLR_GPR_HL_MASK (0x20U) +#define SNVS_LPLR_GPR_HL_SHIFT (5U) +#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) + +/*! @name LPCR - SNVS_LP Control Register */ +#define SNVS_LPCR_MC_ENV_MASK (0x4U) +#define SNVS_LPCR_MC_ENV_SHIFT (2U) +#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) +#define SNVS_LPCR_DP_EN_MASK (0x20U) +#define SNVS_LPCR_DP_EN_SHIFT (5U) +#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK) +#define SNVS_LPCR_TOP_MASK (0x40U) +#define SNVS_LPCR_TOP_SHIFT (6U) +#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK) +#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U) +#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U) +#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK) +#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U) +#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U) +#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK) +#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U) +#define SNVS_LPCR_DEBOUNCE_SHIFT (18U) +#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK) +#define SNVS_LPCR_ON_TIME_MASK (0x300000U) +#define SNVS_LPCR_ON_TIME_SHIFT (20U) +#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK) +#define SNVS_LPCR_PK_EN_MASK (0x400000U) +#define SNVS_LPCR_PK_EN_SHIFT (22U) +#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK) +#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U) +#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U) +#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK) + +/*! @name LPSR - SNVS_LP Status Register */ +#define SNVS_LPSR_MCR_MASK (0x4U) +#define SNVS_LPSR_MCR_SHIFT (2U) +#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) +#define SNVS_LPSR_EO_MASK (0x20000U) +#define SNVS_LPSR_EO_SHIFT (17U) +#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK) +#define SNVS_LPSR_SPO_MASK (0x40000U) +#define SNVS_LPSR_SPO_SHIFT (18U) +#define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK) + +/*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ +#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) +#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) +#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) +#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) +#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) + +/*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ +#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) +#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) + +/*! @name LPGPR - SNVS_LP General-Purpose Register */ +#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR_GPR_SHIFT (0U) +#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) + +/*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ +#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) +#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) +#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) +#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U) +#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U) +#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK) +#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) +#define SNVS_HPVIDR1_IP_ID_SHIFT (16U) +#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) + +/*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ +#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) +#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) +#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) +#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U) +#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U) +#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK) +#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U) +#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U) +#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK) +#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) +#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) +#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) + + +/*! + * @} + */ /* end of group SNVS_Register_Masks */ + + +/* SNVS - Peripheral instance base addresses */ +/** Peripheral SNVS base address */ +#define SNVS_BASE (0x20CC000u) +/** Peripheral SNVS base pointer */ +#define SNVS ((SNVS_Type *)SNVS_BASE) +/** Array initializer of SNVS peripheral base addresses */ +#define SNVS_BASE_ADDRS { SNVS_BASE } +/** Array initializer of SNVS peripheral base pointers */ +#define SNVS_BASE_PTRS { SNVS } +/** Interrupt vectors for the SNVS peripheral type */ +#define SNVS_IRQS { SNVS_IRQn } +#define SNVS_CONSOLIDATED_IRQS { SNVS_Consolidated_IRQn } +#define SNVS_SECURITY_IRQS { SNVS_Security_IRQn } + +/*! + * @} + */ /* end of group SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPBA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPBA_Peripheral_Access_Layer SPBA Peripheral Access Layer + * @{ + */ + +/** SPBA - Register Layout Typedef */ +typedef struct { + __IO uint32_t PRR[32]; /**< Peripheral Rights Register, array offset: 0x0, array step: 0x4 */ +} SPBA_Type; + +/* ---------------------------------------------------------------------------- + -- SPBA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPBA_Register_Masks SPBA Register Masks + * @{ + */ + +/*! @name PRR - Peripheral Rights Register */ +#define SPBA_PRR_RARA_MASK (0x1U) +#define SPBA_PRR_RARA_SHIFT (0U) +#define SPBA_PRR_RARA(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARA_SHIFT)) & SPBA_PRR_RARA_MASK) +#define SPBA_PRR_RARB_MASK (0x2U) +#define SPBA_PRR_RARB_SHIFT (1U) +#define SPBA_PRR_RARB(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARB_SHIFT)) & SPBA_PRR_RARB_MASK) +#define SPBA_PRR_RARC_MASK (0x4U) +#define SPBA_PRR_RARC_SHIFT (2U) +#define SPBA_PRR_RARC(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARC_SHIFT)) & SPBA_PRR_RARC_MASK) +#define SPBA_PRR_ROI_MASK (0x30000U) +#define SPBA_PRR_ROI_SHIFT (16U) +#define SPBA_PRR_ROI(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_ROI_SHIFT)) & SPBA_PRR_ROI_MASK) +#define SPBA_PRR_RMO_MASK (0xC0000000U) +#define SPBA_PRR_RMO_SHIFT (30U) +#define SPBA_PRR_RMO(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RMO_SHIFT)) & SPBA_PRR_RMO_MASK) + +/* The count of SPBA_PRR */ +#define SPBA_PRR_COUNT (32U) + + +/*! + * @} + */ /* end of group SPBA_Register_Masks */ + + +/* SPBA - Peripheral instance base addresses */ +/** Peripheral SPBA base address */ +#define SPBA_BASE (0x203C000u) +/** Peripheral SPBA base pointer */ +#define SPBA ((SPBA_Type *)SPBA_BASE) +/** Array initializer of SPBA peripheral base addresses */ +#define SPBA_BASE_ADDRS { SPBA_BASE } +/** Array initializer of SPBA peripheral base pointers */ +#define SPBA_BASE_PTRS { SPBA } + +/*! + * @} + */ /* end of group SPBA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer + * @{ + */ + +/** SPDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ + __IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */ + __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ + __IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */ + union { /* offset: 0x10 */ + __IO uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */ + __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ + }; + __I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */ + __I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */ + __I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */ + __I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */ + __I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */ + __I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */ + __IO uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */ + __IO uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */ + __IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */ + __IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */ + uint8_t RESERVED_0[8]; + __I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */ + uint8_t RESERVED_1[8]; + __IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */ +} SPDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SPDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Register_Masks SPDIF Register Masks + * @{ + */ + +/*! @name SCR - SPDIF Configuration Register */ +#define SPDIF_SCR_USRC_SEL_MASK (0x3U) +#define SPDIF_SCR_USRC_SEL_SHIFT (0U) +#define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK) +#define SPDIF_SCR_TXSEL_MASK (0x1CU) +#define SPDIF_SCR_TXSEL_SHIFT (2U) +#define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK) +#define SPDIF_SCR_VALCTRL_MASK (0x20U) +#define SPDIF_SCR_VALCTRL_SHIFT (5U) +#define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK) +#define SPDIF_SCR_DMA_TX_EN_MASK (0x100U) +#define SPDIF_SCR_DMA_TX_EN_SHIFT (8U) +#define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK) +#define SPDIF_SCR_DMA_RX_EN_MASK (0x200U) +#define SPDIF_SCR_DMA_RX_EN_SHIFT (9U) +#define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK) +#define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U) +#define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U) +#define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK) +#define SPDIF_SCR_SOFT_RESET_MASK (0x1000U) +#define SPDIF_SCR_SOFT_RESET_SHIFT (12U) +#define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK) +#define SPDIF_SCR_LOW_POWER_MASK (0x2000U) +#define SPDIF_SCR_LOW_POWER_SHIFT (13U) +#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U) +#define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) +#define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U) +#define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U) +#define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK) +#define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U) +#define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U) +#define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK) +#define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U) +#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U) +#define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK) +#define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U) +#define SPDIF_SCR_RXFIFO_RST_SHIFT (21U) +#define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK) +#define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U) +#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U) +#define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK) +#define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) +#define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) +#define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK) + +/*! @name SRCD - CDText Control Register */ +#define SPDIF_SRCD_USYNCMODE_MASK (0x2U) +#define SPDIF_SRCD_USYNCMODE_SHIFT (1U) +#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK) + +/*! @name SRPC - PhaseConfig Register */ +#define SPDIF_SRPC_GAINSEL_MASK (0x38U) +#define SPDIF_SRPC_GAINSEL_SHIFT (3U) +#define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK) +#define SPDIF_SRPC_LOCK_MASK (0x40U) +#define SPDIF_SRPC_LOCK_SHIFT (6U) +#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) +#define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) +#define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) +#define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK) + +/*! @name SIE - InterruptEn Register */ +#define SPDIF_SIE_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIE_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) +#define SPDIF_SIE_TXEM_MASK (0x2U) +#define SPDIF_SIE_TXEM_SHIFT (1U) +#define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK) +#define SPDIF_SIE_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIE_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK) +#define SPDIF_SIE_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIE_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK) +#define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK) +#define SPDIF_SIE_UQERR_MASK (0x20U) +#define SPDIF_SIE_UQERR_SHIFT (5U) +#define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK) +#define SPDIF_SIE_UQSYNC_MASK (0x40U) +#define SPDIF_SIE_UQSYNC_SHIFT (6U) +#define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK) +#define SPDIF_SIE_QRXOV_MASK (0x80U) +#define SPDIF_SIE_QRXOV_SHIFT (7U) +#define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK) +#define SPDIF_SIE_QRXFUL_MASK (0x100U) +#define SPDIF_SIE_QRXFUL_SHIFT (8U) +#define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK) +#define SPDIF_SIE_URXOV_MASK (0x200U) +#define SPDIF_SIE_URXOV_SHIFT (9U) +#define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK) +#define SPDIF_SIE_URXFUL_MASK (0x400U) +#define SPDIF_SIE_URXFUL_SHIFT (10U) +#define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK) +#define SPDIF_SIE_BITERR_MASK (0x4000U) +#define SPDIF_SIE_BITERR_SHIFT (14U) +#define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK) +#define SPDIF_SIE_SYMERR_MASK (0x8000U) +#define SPDIF_SIE_SYMERR_SHIFT (15U) +#define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK) +#define SPDIF_SIE_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIE_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK) +#define SPDIF_SIE_CNEW_MASK (0x20000U) +#define SPDIF_SIE_CNEW_SHIFT (17U) +#define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK) +#define SPDIF_SIE_TXRESYN_MASK (0x40000U) +#define SPDIF_SIE_TXRESYN_SHIFT (18U) +#define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK) +#define SPDIF_SIE_TXUNOV_MASK (0x80000U) +#define SPDIF_SIE_TXUNOV_SHIFT (19U) +#define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK) +#define SPDIF_SIE_LOCK_MASK (0x100000U) +#define SPDIF_SIE_LOCK_SHIFT (20U) +#define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) + +/*! @name SIC - InterruptClear Register */ +#define SPDIF_SIC_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIC_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) +#define SPDIF_SIC_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIC_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK) +#define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK) +#define SPDIF_SIC_UQERR_MASK (0x20U) +#define SPDIF_SIC_UQERR_SHIFT (5U) +#define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK) +#define SPDIF_SIC_UQSYNC_MASK (0x40U) +#define SPDIF_SIC_UQSYNC_SHIFT (6U) +#define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK) +#define SPDIF_SIC_QRXOV_MASK (0x80U) +#define SPDIF_SIC_QRXOV_SHIFT (7U) +#define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK) +#define SPDIF_SIC_URXOV_MASK (0x200U) +#define SPDIF_SIC_URXOV_SHIFT (9U) +#define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK) +#define SPDIF_SIC_BITERR_MASK (0x4000U) +#define SPDIF_SIC_BITERR_SHIFT (14U) +#define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK) +#define SPDIF_SIC_SYMERR_MASK (0x8000U) +#define SPDIF_SIC_SYMERR_SHIFT (15U) +#define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK) +#define SPDIF_SIC_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIC_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK) +#define SPDIF_SIC_CNEW_MASK (0x20000U) +#define SPDIF_SIC_CNEW_SHIFT (17U) +#define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK) +#define SPDIF_SIC_TXRESYN_MASK (0x40000U) +#define SPDIF_SIC_TXRESYN_SHIFT (18U) +#define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK) +#define SPDIF_SIC_TXUNOV_MASK (0x80000U) +#define SPDIF_SIC_TXUNOV_SHIFT (19U) +#define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK) +#define SPDIF_SIC_LOCK_MASK (0x100000U) +#define SPDIF_SIC_LOCK_SHIFT (20U) +#define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) + +/*! @name SIS - InterruptStat Register */ +#define SPDIF_SIS_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIS_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) +#define SPDIF_SIS_TXEM_MASK (0x2U) +#define SPDIF_SIS_TXEM_SHIFT (1U) +#define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK) +#define SPDIF_SIS_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIS_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK) +#define SPDIF_SIS_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIS_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK) +#define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK) +#define SPDIF_SIS_UQERR_MASK (0x20U) +#define SPDIF_SIS_UQERR_SHIFT (5U) +#define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK) +#define SPDIF_SIS_UQSYNC_MASK (0x40U) +#define SPDIF_SIS_UQSYNC_SHIFT (6U) +#define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK) +#define SPDIF_SIS_QRXOV_MASK (0x80U) +#define SPDIF_SIS_QRXOV_SHIFT (7U) +#define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK) +#define SPDIF_SIS_QRXFUL_MASK (0x100U) +#define SPDIF_SIS_QRXFUL_SHIFT (8U) +#define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK) +#define SPDIF_SIS_URXOV_MASK (0x200U) +#define SPDIF_SIS_URXOV_SHIFT (9U) +#define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK) +#define SPDIF_SIS_URXFUL_MASK (0x400U) +#define SPDIF_SIS_URXFUL_SHIFT (10U) +#define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK) +#define SPDIF_SIS_BITERR_MASK (0x4000U) +#define SPDIF_SIS_BITERR_SHIFT (14U) +#define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK) +#define SPDIF_SIS_SYMERR_MASK (0x8000U) +#define SPDIF_SIS_SYMERR_SHIFT (15U) +#define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK) +#define SPDIF_SIS_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIS_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK) +#define SPDIF_SIS_CNEW_MASK (0x20000U) +#define SPDIF_SIS_CNEW_SHIFT (17U) +#define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK) +#define SPDIF_SIS_TXRESYN_MASK (0x40000U) +#define SPDIF_SIS_TXRESYN_SHIFT (18U) +#define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK) +#define SPDIF_SIS_TXUNOV_MASK (0x80000U) +#define SPDIF_SIS_TXUNOV_SHIFT (19U) +#define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK) +#define SPDIF_SIS_LOCK_MASK (0x100000U) +#define SPDIF_SIS_LOCK_SHIFT (20U) +#define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) + +/*! @name SRL - SPDIFRxLeft Register */ +#define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_SRL_RXDATALEFT_SHIFT (0U) +#define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) + +/*! @name SRR - SPDIFRxRight Register */ +#define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_SRR_RXDATARIGHT_SHIFT (0U) +#define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) + +/*! @name SRCSH - SPDIFRxCChannel_h Register */ +#define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) +#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) +#define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) + +/*! @name SRCSL - SPDIFRxCChannel_l Register */ +#define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) +#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) +#define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) + +/*! @name SRU - UchannelRx Register */ +#define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRU_RXUCHANNEL_SHIFT (0U) +#define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) + +/*! @name SRQ - QchannelRx Register */ +#define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) +#define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) + +/*! @name STL - SPDIFTxLeft Register */ +#define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_STL_TXDATALEFT_SHIFT (0U) +#define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) + +/*! @name STR - SPDIFTxRight Register */ +#define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_STR_TXDATARIGHT_SHIFT (0U) +#define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) + +/*! @name STCSCH - SPDIFTxCChannelCons_h Register */ +#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) +#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) +#define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) + +/*! @name STCSCL - SPDIFTxCChannelCons_l Register */ +#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) +#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) +#define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) + +/*! @name SRFM - FreqMeas Register */ +#define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) +#define SPDIF_SRFM_FREQMEAS_SHIFT (0U) +#define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) + +/*! @name STC - SPDIFTxClk Register */ +#define SPDIF_STC_TXCLK_DF_MASK (0x7FU) +#define SPDIF_STC_TXCLK_DF_SHIFT (0U) +#define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK) +#define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U) +#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U) +#define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK) +#define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U) +#define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U) +#define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK) +#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) +#define SPDIF_STC_SYSCLK_DF_SHIFT (11U) +#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) + + +/*! + * @} + */ /* end of group SPDIF_Register_Masks */ + + +/* SPDIF - Peripheral instance base addresses */ +/** Peripheral SPDIF base address */ +#define SPDIF_BASE (0x2004000u) +/** Peripheral SPDIF base pointer */ +#define SPDIF ((SPDIF_Type *)SPDIF_BASE) +/** Array initializer of SPDIF peripheral base addresses */ +#define SPDIF_BASE_ADDRS { SPDIF_BASE } +/** Array initializer of SPDIF peripheral base pointers */ +#define SPDIF_BASE_PTRS { SPDIF } +/** Interrupt vectors for the SPDIF peripheral type */ +#define SPDIF_IRQS { SPDIF_IRQn } + +/*! + * @} + */ /* end of group SPDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer + * @{ + */ + +/** SRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ + __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x4 */ + __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x8 */ + uint8_t RESERVED_0[8]; + __I uint32_t SISR; /**< SRC Interrupt Status Register, offset: 0x14 */ + uint8_t RESERVED_1[4]; + __I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x1C */ + __IO uint32_t GPR[10]; /**< SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x20, array step: 0x4 */ +} SRC_Type; + +/* ---------------------------------------------------------------------------- + -- SRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Register_Masks SRC Register Masks + * @{ + */ + +/*! @name SCR - SRC Control Register */ +#define SRC_SCR_WARM_RESET_ENABLE_MASK (0x1U) +#define SRC_SCR_WARM_RESET_ENABLE_SHIFT (0U) +#define SRC_SCR_WARM_RESET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_WARM_RESET_ENABLE_SHIFT)) & SRC_SCR_WARM_RESET_ENABLE_MASK) +#define SRC_SCR_WARM_RST_BYPASS_COUNT_MASK (0x60U) +#define SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT (5U) +#define SRC_SCR_WARM_RST_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT)) & SRC_SCR_WARM_RST_BYPASS_COUNT_MASK) +#define SRC_SCR_MASK_WDOG_RST_MASK (0x780U) +#define SRC_SCR_MASK_WDOG_RST_SHIFT (7U) +#define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK) +#define SRC_SCR_EIM_RST_MASK (0x800U) +#define SRC_SCR_EIM_RST_SHIFT (11U) +#define SRC_SCR_EIM_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_EIM_RST_SHIFT)) & SRC_SCR_EIM_RST_MASK) +#define SRC_SCR_CORE0_RST_MASK (0x2000U) +#define SRC_SCR_CORE0_RST_SHIFT (13U) +#define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK) +#define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U) +#define SRC_SCR_CORE0_DBG_RST_SHIFT (17U) +#define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK) +#define SRC_SCR_CORES_DBG_RST_MASK (0x200000U) +#define SRC_SCR_CORES_DBG_RST_SHIFT (21U) +#define SRC_SCR_CORES_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORES_DBG_RST_SHIFT)) & SRC_SCR_CORES_DBG_RST_MASK) +#define SRC_SCR_WDOG3_RST_OPTN_MASK (0x1000000U) +#define SRC_SCR_WDOG3_RST_OPTN_SHIFT (24U) +#define SRC_SCR_WDOG3_RST_OPTN(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_WDOG3_RST_OPTN_SHIFT)) & SRC_SCR_WDOG3_RST_OPTN_MASK) +#define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U) +#define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U) +#define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK) +#define SRC_SCR_MIX_RST_STRCH_MASK (0xC000000U) +#define SRC_SCR_MIX_RST_STRCH_SHIFT (26U) +#define SRC_SCR_MIX_RST_STRCH(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MIX_RST_STRCH_SHIFT)) & SRC_SCR_MIX_RST_STRCH_MASK) +#define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U) +#define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U) +#define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK) + +/*! @name SBMR1 - SRC Boot Mode Register 1 */ +#define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU) +#define SRC_SBMR1_BOOT_CFG1_SHIFT (0U) +#define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK) +#define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U) +#define SRC_SBMR1_BOOT_CFG2_SHIFT (8U) +#define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK) +#define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U) +#define SRC_SBMR1_BOOT_CFG3_SHIFT (16U) +#define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK) +#define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U) +#define SRC_SBMR1_BOOT_CFG4_SHIFT (24U) +#define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK) + +/*! @name SRSR - SRC Reset Status Register */ +#define SRC_SRSR_IPP_RESET_B_MASK (0x1U) +#define SRC_SRSR_IPP_RESET_B_SHIFT (0U) +#define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK) +#define SRC_SRSR_CSU_RESET_B_MASK (0x4U) +#define SRC_SRSR_CSU_RESET_B_SHIFT (2U) +#define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK) +#define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U) +#define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U) +#define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK) +#define SRC_SRSR_WDOG_RST_B_MASK (0x10U) +#define SRC_SRSR_WDOG_RST_B_SHIFT (4U) +#define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK) +#define SRC_SRSR_JTAG_RST_B_MASK (0x20U) +#define SRC_SRSR_JTAG_RST_B_SHIFT (5U) +#define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK) +#define SRC_SRSR_JTAG_SW_RST_MASK (0x40U) +#define SRC_SRSR_JTAG_SW_RST_SHIFT (6U) +#define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK) +#define SRC_SRSR_WDOG3_RST_B_MASK (0x80U) +#define SRC_SRSR_WDOG3_RST_B_SHIFT (7U) +#define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK) +#define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U) +#define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U) +#define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK) +#define SRC_SRSR_WARM_BOOT_MASK (0x10000U) +#define SRC_SRSR_WARM_BOOT_SHIFT (16U) +#define SRC_SRSR_WARM_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WARM_BOOT_SHIFT)) & SRC_SRSR_WARM_BOOT_MASK) + +/*! @name SISR - SRC Interrupt Status Register */ +#define SRC_SISR_CORE0_WDOG_RST_REQ_MASK (0x20U) +#define SRC_SISR_CORE0_WDOG_RST_REQ_SHIFT (5U) +#define SRC_SISR_CORE0_WDOG_RST_REQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SISR_CORE0_WDOG_RST_REQ_SHIFT)) & SRC_SISR_CORE0_WDOG_RST_REQ_MASK) + +/*! @name SBMR2 - SRC Boot Mode Register 2 */ +#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U) +#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U) +#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) +#define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U) +#define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U) +#define SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK) +#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U) +#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U) +#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK) +#define SRC_SBMR2_BMOD_MASK (0x3000000U) +#define SRC_SBMR2_BMOD_SHIFT (24U) +#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) + +/*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */ +#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) +#define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK) + +/* The count of SRC_GPR */ +#define SRC_GPR_COUNT (10U) + + +/*! + * @} + */ /* end of group SRC_Register_Masks */ + + +/* SRC - Peripheral instance base addresses */ +/** Peripheral SRC base address */ +#define SRC_BASE (0x20D8000u) +/** Peripheral SRC base pointer */ +#define SRC ((SRC_Type *)SRC_BASE) +/** Array initializer of SRC peripheral base addresses */ +#define SRC_BASE_ADDRS { SRC_BASE } +/** Array initializer of SRC peripheral base pointers */ +#define SRC_BASE_PTRS { SRC } +/** Interrupt vectors for the SRC peripheral type */ +#define SRC_IRQS { SRC_IRQn } +#define SRC_COMBINED_IRQS { SRC_Combined_IRQn } +/* Backward compatibility */ +#define SRC_SCR_WRE_MASK SRC_SCR_WARM_RESET_ENABLE_MASK +#define SRC_SCR_WRE_SHIFT SRC_SCR_WARM_RESET_ENABLE_SHIFT +#define SRC_SCR_WRE(x) SRC_SCR_WARM_RESET_ENABLE(x) +#define SRC_SCR_WRBC_MASK SRC_SCR_WARM_RST_BYPASS_COUNT_MASK +#define SRC_SCR_WRBC_SHIFT SRC_SCR_WARM_RST_BYPASS_COUNT_SHIFT +#define SRC_SCR_WRBC(x) SRC_SCR_WARM_RST_BYPASS_COUNT(x) +#define SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASK +#define SRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFT +#define SRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x) +#define SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASK +#define SRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFT +#define SRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x) +#define SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASK +#define SRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFT +#define SRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x) +#define SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASK +#define SRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFT +#define SRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x) +#define SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASK +#define SRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFT +#define SRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x) +#define SRC_SRSR_WBI_MASK SRC_SRSR_WARM_BOOT_MASK +#define SRC_SRSR_WBI_SHIFT SRC_SRSR_WARM_BOOT_SHIFT +#define SRC_SRSR_WBI(x) SRC_SRSR_WARM_BOOT(x) +/* Extra definition */ +#define SRC_SRSR_W1C_BITS_MASK (SRC_SRSR_WDOG3_RST_B_MASK \ + | SRC_SRSR_JTAG_SW_RST_MASK \ + | SRC_SRSR_JTAG_RST_B_MASK \ + | SRC_SRSR_WDOG_RST_B_MASK \ + | SRC_SRSR_IPP_USER_RESET_B_MASK \ + | SRC_SRSR_CSU_RESET_B_MASK \ + | SRC_SRSR_IPP_RESET_B_MASK) + + +/*! + * @} + */ /* end of group SRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TEMPMON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer + * @{ + */ + +/** TEMPMON - Register Layout Typedef */ +typedef struct { + __IO uint32_t TEMPSENSE0; /**< Tempsensor Control Register 0, offset: 0x0 */ + __IO uint32_t TEMPSENSE0_SET; /**< Tempsensor Control Register 0, offset: 0x4 */ + __IO uint32_t TEMPSENSE0_CLR; /**< Tempsensor Control Register 0, offset: 0x8 */ + __IO uint32_t TEMPSENSE0_TOG; /**< Tempsensor Control Register 0, offset: 0xC */ + __IO uint32_t TEMPSENSE1; /**< Tempsensor Control Register 1, offset: 0x10 */ + __IO uint32_t TEMPSENSE1_SET; /**< Tempsensor Control Register 1, offset: 0x14 */ + __IO uint32_t TEMPSENSE1_CLR; /**< Tempsensor Control Register 1, offset: 0x18 */ + __IO uint32_t TEMPSENSE1_TOG; /**< Tempsensor Control Register 1, offset: 0x1C */ + uint8_t RESERVED_0[240]; + __IO uint32_t TEMPSENSE2; /**< Tempsensor Control Register 2, offset: 0x110 */ + __IO uint32_t TEMPSENSE2_SET; /**< Tempsensor Control Register 2, offset: 0x114 */ + __IO uint32_t TEMPSENSE2_CLR; /**< Tempsensor Control Register 2, offset: 0x118 */ + __IO uint32_t TEMPSENSE2_TOG; /**< Tempsensor Control Register 2, offset: 0x11C */ +} TEMPMON_Type; + +/* ---------------------------------------------------------------------------- + -- TEMPMON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks + * @{ + */ + +/*! @name TEMPSENSE0 - Tempsensor Control Register 0 */ +#define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE0_SET - Tempsensor Control Register 0 */ +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE0_CLR - Tempsensor Control Register 0 */ +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE0_TOG - Tempsensor Control Register 0 */ +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U) +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE1 - Tempsensor Control Register 1 */ +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK) + +/*! @name TEMPSENSE1_SET - Tempsensor Control Register 1 */ +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK) + +/*! @name TEMPSENSE1_CLR - Tempsensor Control Register 1 */ +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) + +/*! @name TEMPSENSE1_TOG - Tempsensor Control Register 1 */ +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) + +/*! @name TEMPSENSE2 - Tempsensor Control Register 2 */ +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE2_SET - Tempsensor Control Register 2 */ +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE2_CLR - Tempsensor Control Register 2 */ +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK) + +/*! @name TEMPSENSE2_TOG - Tempsensor Control Register 2 */ +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK) + + +/*! + * @} + */ /* end of group TEMPMON_Register_Masks */ + + +/* TEMPMON - Peripheral instance base addresses */ +/** Peripheral TEMPMON base address */ +#define TEMPMON_BASE (0x20C8180u) +/** Peripheral TEMPMON base pointer */ +#define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE) +/** Array initializer of TEMPMON peripheral base addresses */ +#define TEMPMON_BASE_ADDRS { TEMPMON_BASE } +/** Array initializer of TEMPMON peripheral base pointers */ +#define TEMPMON_BASE_PTRS { TEMPMON } +/** Interrupt vectors for the TEMPMON peripheral type */ +#define TEMPMON_IRQS { TEMPMON_IRQn } + +/*! + * @} + */ /* end of group TEMPMON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSC_Peripheral_Access_Layer TSC Peripheral Access Layer + * @{ + */ + +/** TSC - Register Layout Typedef */ +typedef struct { + __IO uint32_t BASIC_SETTING; /**< PS Input Buffer Address, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PS_INPUT_BUFFER_ADDR; /**< PS Input Buffer Address, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t FLOW_CONTROL; /**< Flow Control, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __I uint32_t MEASEURE_VALUE; /**< Measure Value, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __IO uint32_t INT_EN; /**< Interrupt Enable, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t INT_SIG_EN; /**< Interrupt Signal Enable, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t INT_STATUS; /**< Intterrupt Status, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t DEBUG_MODE; /**< , offset: 0x70 */ + uint8_t RESERVED_7[12]; + __IO uint32_t DEBUG_MODE2; /**< , offset: 0x80 */ +} TSC_Type; + +/* ---------------------------------------------------------------------------- + -- TSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSC_Register_Masks TSC Register Masks + * @{ + */ + +/*! @name BASIC_SETTING - PS Input Buffer Address */ +#define TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U) +#define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U) +#define TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK) +#define TSC_BASIC_SETTING__4_5_WIRE_MASK (0x10U) +#define TSC_BASIC_SETTING__4_5_WIRE_SHIFT (4U) +#define TSC_BASIC_SETTING__4_5_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING__4_5_WIRE_SHIFT)) & TSC_BASIC_SETTING__4_5_WIRE_MASK) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK) + +/*! @name PS_INPUT_BUFFER_ADDR - PS Input Buffer Address */ +#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU) +#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_SHIFT (0U) +#define TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_SHIFT)) & TSC_PS_INPUT_BUFFER_ADDR_PRE_CHARGE_TIME_MASK) + +/*! @name FLOW_CONTROL - Flow Control */ +#define TSC_FLOW_CONTROL_SW_RST_MASK (0x1U) +#define TSC_FLOW_CONTROL_SW_RST_SHIFT (0U) +#define TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK) +#define TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U) +#define TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U) +#define TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK) +#define TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U) +#define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U) +#define TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK) +#define TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U) +#define TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U) +#define TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK) +#define TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U) +#define TSC_FLOW_CONTROL_DISABLE_SHIFT (16U) +#define TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK) + +/*! @name MEASEURE_VALUE - Measure Value */ +#define TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU) +#define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U) +#define TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK) +#define TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U) +#define TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U) +#define TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK) + +/*! @name INT_EN - Interrupt Enable */ +#define TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U) +#define TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U) +#define TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK) +#define TSC_INT_EN_DETECT_INT_EN_MASK (0x10U) +#define TSC_INT_EN_DETECT_INT_EN_SHIFT (4U) +#define TSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK) +#define TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U) +#define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U) +#define TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK) + +/*! @name INT_SIG_EN - Interrupt Signal Enable */ +#define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U) +#define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U) +#define TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK) +#define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U) +#define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U) +#define TSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK) +#define TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U) +#define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U) +#define TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK) + +/*! @name INT_STATUS - Intterrupt Status */ +#define TSC_INT_STATUS_MEASURE_MASK (0x1U) +#define TSC_INT_STATUS_MEASURE_SHIFT (0U) +#define TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK) +#define TSC_INT_STATUS_DETECT_MASK (0x10U) +#define TSC_INT_STATUS_DETECT_SHIFT (4U) +#define TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK) +#define TSC_INT_STATUS_VALID_MASK (0x100U) +#define TSC_INT_STATUS_VALID_SHIFT (8U) +#define TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK) +#define TSC_INT_STATUS_IDLE_SW_MASK (0x1000U) +#define TSC_INT_STATUS_IDLE_SW_SHIFT (12U) +#define TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK) + +/*! @name DEBUG_MODE - */ +#define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU) +#define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U) +#define TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_MASK (0x1000U) +#define TSC_DEBUG_MODE_ADC_COCO_SHIFT (12U) +#define TSC_DEBUG_MODE_ADC_COCO(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK) +#define TSC_DEBUG_MODE_EXT_HWTS_MASK (0x1F0000U) +#define TSC_DEBUG_MODE_EXT_HWTS_SHIFT (16U) +#define TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK) +#define TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U) +#define TSC_DEBUG_MODE_TRIGGER_SHIFT (24U) +#define TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK) +#define TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U) +#define TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U) +#define TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK) + +/*! @name DEBUG_MODE2 - */ +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U) +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U) +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK) +#define TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U) +#define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U) +#define TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK) +#define TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U) +#define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U) +#define TSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK) +#define TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U) +#define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U) +#define TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK) + + +/*! + * @} + */ /* end of group TSC_Register_Masks */ + + +/* TSC - Peripheral instance base addresses */ +/** Peripheral TSC base address */ +#define TSC_BASE (0x2040000u) +/** Peripheral TSC base pointer */ +#define TSC ((TSC_Type *)TSC_BASE) +/** Array initializer of TSC peripheral base addresses */ +#define TSC_BASE_ADDRS { TSC_BASE } +/** Array initializer of TSC peripheral base pointers */ +#define TSC_BASE_PTRS { TSC } +/** Interrupt vectors for the TSC peripheral type */ +#define TSC_IRQS { TSC_IRQn } + +/*! + * @} + */ /* end of group TSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer + * @{ + */ + +/** UART - Register Layout Typedef */ +typedef struct { + __I uint32_t URXD; /**< UART Receiver Register, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t UTXD; /**< UART Transmitter Register, offset: 0x40 */ + uint8_t RESERVED_1[60]; + __IO uint32_t UCR1; /**< UART Control Register 1, offset: 0x80 */ + __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */ + __IO uint32_t UCR3; /**< UART Control Register 3, offset: 0x88 */ + __IO uint32_t UCR4; /**< UART Control Register 4, offset: 0x8C */ + __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */ + __IO uint32_t USR1; /**< UART Status Register 1, offset: 0x94 */ + __IO uint32_t USR2; /**< UART Status Register 2, offset: 0x98 */ + __IO uint32_t UESC; /**< UART Escape Character Register, offset: 0x9C */ + __IO uint32_t UTIM; /**< UART Escape Timer Register, offset: 0xA0 */ + __IO uint32_t UBIR; /**< UART BRM Incremental Register, offset: 0xA4 */ + __IO uint32_t UBMR; /**< UART BRM Modulator Register, offset: 0xA8 */ + __I uint32_t UBRC; /**< UART Baud Rate Count Register, offset: 0xAC */ + __IO uint32_t ONEMS; /**< UART One Millisecond Register, offset: 0xB0 */ + __IO uint32_t UTS; /**< UART Test Register, offset: 0xB4 */ + __IO uint32_t UMCR; /**< UART RS-485 Mode Control Register, offset: 0xB8 */ +} UART_Type; + +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/*! @name URXD - UART Receiver Register */ +#define UART_URXD_RX_DATA_MASK (0xFFU) +#define UART_URXD_RX_DATA_SHIFT (0U) +#define UART_URXD_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_RX_DATA_SHIFT)) & UART_URXD_RX_DATA_MASK) +#define UART_URXD_PRERR_MASK (0x400U) +#define UART_URXD_PRERR_SHIFT (10U) +#define UART_URXD_PRERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_PRERR_SHIFT)) & UART_URXD_PRERR_MASK) +#define UART_URXD_BRK_MASK (0x800U) +#define UART_URXD_BRK_SHIFT (11U) +#define UART_URXD_BRK(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_BRK_SHIFT)) & UART_URXD_BRK_MASK) +#define UART_URXD_FRMERR_MASK (0x1000U) +#define UART_URXD_FRMERR_SHIFT (12U) +#define UART_URXD_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_FRMERR_SHIFT)) & UART_URXD_FRMERR_MASK) +#define UART_URXD_OVRRUN_MASK (0x2000U) +#define UART_URXD_OVRRUN_SHIFT (13U) +#define UART_URXD_OVRRUN(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_OVRRUN_SHIFT)) & UART_URXD_OVRRUN_MASK) +#define UART_URXD_ERR_MASK (0x4000U) +#define UART_URXD_ERR_SHIFT (14U) +#define UART_URXD_ERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_ERR_SHIFT)) & UART_URXD_ERR_MASK) +#define UART_URXD_CHARRDY_MASK (0x8000U) +#define UART_URXD_CHARRDY_SHIFT (15U) +#define UART_URXD_CHARRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_CHARRDY_SHIFT)) & UART_URXD_CHARRDY_MASK) + +/*! @name UTXD - UART Transmitter Register */ +#define UART_UTXD_TX_DATA_MASK (0xFFU) +#define UART_UTXD_TX_DATA_SHIFT (0U) +#define UART_UTXD_TX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_UTXD_TX_DATA_SHIFT)) & UART_UTXD_TX_DATA_MASK) + +/*! @name UCR1 - UART Control Register 1 */ +#define UART_UCR1_UARTEN_MASK (0x1U) +#define UART_UCR1_UARTEN_SHIFT (0U) +#define UART_UCR1_UARTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_UARTEN_SHIFT)) & UART_UCR1_UARTEN_MASK) +#define UART_UCR1_DOZE_MASK (0x2U) +#define UART_UCR1_DOZE_SHIFT (1U) +#define UART_UCR1_DOZE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_DOZE_SHIFT)) & UART_UCR1_DOZE_MASK) +#define UART_UCR1_ATDMAEN_MASK (0x4U) +#define UART_UCR1_ATDMAEN_SHIFT (2U) +#define UART_UCR1_ATDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ATDMAEN_SHIFT)) & UART_UCR1_ATDMAEN_MASK) +#define UART_UCR1_TXDMAEN_MASK (0x8U) +#define UART_UCR1_TXDMAEN_SHIFT (3U) +#define UART_UCR1_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXDMAEN_SHIFT)) & UART_UCR1_TXDMAEN_MASK) +#define UART_UCR1_SNDBRK_MASK (0x10U) +#define UART_UCR1_SNDBRK_SHIFT (4U) +#define UART_UCR1_SNDBRK(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_SNDBRK_SHIFT)) & UART_UCR1_SNDBRK_MASK) +#define UART_UCR1_RTSDEN_MASK (0x20U) +#define UART_UCR1_RTSDEN_SHIFT (5U) +#define UART_UCR1_RTSDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RTSDEN_SHIFT)) & UART_UCR1_RTSDEN_MASK) +#define UART_UCR1_TXMPTYEN_MASK (0x40U) +#define UART_UCR1_TXMPTYEN_SHIFT (6U) +#define UART_UCR1_TXMPTYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXMPTYEN_SHIFT)) & UART_UCR1_TXMPTYEN_MASK) +#define UART_UCR1_IREN_MASK (0x80U) +#define UART_UCR1_IREN_SHIFT (7U) +#define UART_UCR1_IREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IREN_SHIFT)) & UART_UCR1_IREN_MASK) +#define UART_UCR1_RXDMAEN_MASK (0x100U) +#define UART_UCR1_RXDMAEN_SHIFT (8U) +#define UART_UCR1_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RXDMAEN_SHIFT)) & UART_UCR1_RXDMAEN_MASK) +#define UART_UCR1_RRDYEN_MASK (0x200U) +#define UART_UCR1_RRDYEN_SHIFT (9U) +#define UART_UCR1_RRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RRDYEN_SHIFT)) & UART_UCR1_RRDYEN_MASK) +#define UART_UCR1_ICD_MASK (0xC00U) +#define UART_UCR1_ICD_SHIFT (10U) +#define UART_UCR1_ICD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ICD_SHIFT)) & UART_UCR1_ICD_MASK) +#define UART_UCR1_IDEN_MASK (0x1000U) +#define UART_UCR1_IDEN_SHIFT (12U) +#define UART_UCR1_IDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IDEN_SHIFT)) & UART_UCR1_IDEN_MASK) +#define UART_UCR1_TRDYEN_MASK (0x2000U) +#define UART_UCR1_TRDYEN_SHIFT (13U) +#define UART_UCR1_TRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TRDYEN_SHIFT)) & UART_UCR1_TRDYEN_MASK) +#define UART_UCR1_ADBR_MASK (0x4000U) +#define UART_UCR1_ADBR_SHIFT (14U) +#define UART_UCR1_ADBR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADBR_SHIFT)) & UART_UCR1_ADBR_MASK) +#define UART_UCR1_ADEN_MASK (0x8000U) +#define UART_UCR1_ADEN_SHIFT (15U) +#define UART_UCR1_ADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADEN_SHIFT)) & UART_UCR1_ADEN_MASK) + +/*! @name UCR2 - UART Control Register 2 */ +#define UART_UCR2_SRST_MASK (0x1U) +#define UART_UCR2_SRST_SHIFT (0U) +#define UART_UCR2_SRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_SRST_SHIFT)) & UART_UCR2_SRST_MASK) +#define UART_UCR2_RXEN_MASK (0x2U) +#define UART_UCR2_RXEN_SHIFT (1U) +#define UART_UCR2_RXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RXEN_SHIFT)) & UART_UCR2_RXEN_MASK) +#define UART_UCR2_TXEN_MASK (0x4U) +#define UART_UCR2_TXEN_SHIFT (2U) +#define UART_UCR2_TXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_TXEN_SHIFT)) & UART_UCR2_TXEN_MASK) +#define UART_UCR2_ATEN_MASK (0x8U) +#define UART_UCR2_ATEN_SHIFT (3U) +#define UART_UCR2_ATEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ATEN_SHIFT)) & UART_UCR2_ATEN_MASK) +#define UART_UCR2_RTSEN_MASK (0x10U) +#define UART_UCR2_RTSEN_SHIFT (4U) +#define UART_UCR2_RTSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTSEN_SHIFT)) & UART_UCR2_RTSEN_MASK) +#define UART_UCR2_WS_MASK (0x20U) +#define UART_UCR2_WS_SHIFT (5U) +#define UART_UCR2_WS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_WS_SHIFT)) & UART_UCR2_WS_MASK) +#define UART_UCR2_STPB_MASK (0x40U) +#define UART_UCR2_STPB_SHIFT (6U) +#define UART_UCR2_STPB(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_STPB_SHIFT)) & UART_UCR2_STPB_MASK) +#define UART_UCR2_PROE_MASK (0x80U) +#define UART_UCR2_PROE_SHIFT (7U) +#define UART_UCR2_PROE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PROE_SHIFT)) & UART_UCR2_PROE_MASK) +#define UART_UCR2_PREN_MASK (0x100U) +#define UART_UCR2_PREN_SHIFT (8U) +#define UART_UCR2_PREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PREN_SHIFT)) & UART_UCR2_PREN_MASK) +#define UART_UCR2_RTEC_MASK (0x600U) +#define UART_UCR2_RTEC_SHIFT (9U) +#define UART_UCR2_RTEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTEC_SHIFT)) & UART_UCR2_RTEC_MASK) +#define UART_UCR2_ESCEN_MASK (0x800U) +#define UART_UCR2_ESCEN_SHIFT (11U) +#define UART_UCR2_ESCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCEN_SHIFT)) & UART_UCR2_ESCEN_MASK) +#define UART_UCR2_CTS_MASK (0x1000U) +#define UART_UCR2_CTS_SHIFT (12U) +#define UART_UCR2_CTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTS_SHIFT)) & UART_UCR2_CTS_MASK) +#define UART_UCR2_CTSC_MASK (0x2000U) +#define UART_UCR2_CTSC_SHIFT (13U) +#define UART_UCR2_CTSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTSC_SHIFT)) & UART_UCR2_CTSC_MASK) +#define UART_UCR2_IRTS_MASK (0x4000U) +#define UART_UCR2_IRTS_SHIFT (14U) +#define UART_UCR2_IRTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_IRTS_SHIFT)) & UART_UCR2_IRTS_MASK) +#define UART_UCR2_ESCI_MASK (0x8000U) +#define UART_UCR2_ESCI_SHIFT (15U) +#define UART_UCR2_ESCI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCI_SHIFT)) & UART_UCR2_ESCI_MASK) + +/*! @name UCR3 - UART Control Register 3 */ +#define UART_UCR3_ACIEN_MASK (0x1U) +#define UART_UCR3_ACIEN_SHIFT (0U) +#define UART_UCR3_ACIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ACIEN_SHIFT)) & UART_UCR3_ACIEN_MASK) +#define UART_UCR3_INVT_MASK (0x2U) +#define UART_UCR3_INVT_SHIFT (1U) +#define UART_UCR3_INVT(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_INVT_SHIFT)) & UART_UCR3_INVT_MASK) +#define UART_UCR3_RXDMUXSEL_MASK (0x4U) +#define UART_UCR3_RXDMUXSEL_SHIFT (2U) +#define UART_UCR3_RXDMUXSEL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDMUXSEL_SHIFT)) & UART_UCR3_RXDMUXSEL_MASK) +#define UART_UCR3_DTRDEN_MASK (0x8U) +#define UART_UCR3_DTRDEN_SHIFT (3U) +#define UART_UCR3_DTRDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTRDEN_SHIFT)) & UART_UCR3_DTRDEN_MASK) +#define UART_UCR3_AWAKEN_MASK (0x10U) +#define UART_UCR3_AWAKEN_SHIFT (4U) +#define UART_UCR3_AWAKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AWAKEN_SHIFT)) & UART_UCR3_AWAKEN_MASK) +#define UART_UCR3_AIRINTEN_MASK (0x20U) +#define UART_UCR3_AIRINTEN_SHIFT (5U) +#define UART_UCR3_AIRINTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AIRINTEN_SHIFT)) & UART_UCR3_AIRINTEN_MASK) +#define UART_UCR3_RXDSEN_MASK (0x40U) +#define UART_UCR3_RXDSEN_SHIFT (6U) +#define UART_UCR3_RXDSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDSEN_SHIFT)) & UART_UCR3_RXDSEN_MASK) +#define UART_UCR3_ADNIMP_MASK (0x80U) +#define UART_UCR3_ADNIMP_SHIFT (7U) +#define UART_UCR3_ADNIMP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ADNIMP_SHIFT)) & UART_UCR3_ADNIMP_MASK) +#define UART_UCR3_RI_MASK (0x100U) +#define UART_UCR3_RI_SHIFT (8U) +#define UART_UCR3_RI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RI_SHIFT)) & UART_UCR3_RI_MASK) +#define UART_UCR3_DCD_MASK (0x200U) +#define UART_UCR3_DCD_SHIFT (9U) +#define UART_UCR3_DCD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DCD_SHIFT)) & UART_UCR3_DCD_MASK) +#define UART_UCR3_DSR_MASK (0x400U) +#define UART_UCR3_DSR_SHIFT (10U) +#define UART_UCR3_DSR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DSR_SHIFT)) & UART_UCR3_DSR_MASK) +#define UART_UCR3_FRAERREN_MASK (0x800U) +#define UART_UCR3_FRAERREN_SHIFT (11U) +#define UART_UCR3_FRAERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_FRAERREN_SHIFT)) & UART_UCR3_FRAERREN_MASK) +#define UART_UCR3_PARERREN_MASK (0x1000U) +#define UART_UCR3_PARERREN_SHIFT (12U) +#define UART_UCR3_PARERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_PARERREN_SHIFT)) & UART_UCR3_PARERREN_MASK) +#define UART_UCR3_DTREN_MASK (0x2000U) +#define UART_UCR3_DTREN_SHIFT (13U) +#define UART_UCR3_DTREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTREN_SHIFT)) & UART_UCR3_DTREN_MASK) +#define UART_UCR3_DPEC_MASK (0xC000U) +#define UART_UCR3_DPEC_SHIFT (14U) +#define UART_UCR3_DPEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DPEC_SHIFT)) & UART_UCR3_DPEC_MASK) + +/*! @name UCR4 - UART Control Register 4 */ +#define UART_UCR4_DREN_MASK (0x1U) +#define UART_UCR4_DREN_SHIFT (0U) +#define UART_UCR4_DREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_DREN_SHIFT)) & UART_UCR4_DREN_MASK) +#define UART_UCR4_OREN_MASK (0x2U) +#define UART_UCR4_OREN_SHIFT (1U) +#define UART_UCR4_OREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_OREN_SHIFT)) & UART_UCR4_OREN_MASK) +#define UART_UCR4_BKEN_MASK (0x4U) +#define UART_UCR4_BKEN_SHIFT (2U) +#define UART_UCR4_BKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_BKEN_SHIFT)) & UART_UCR4_BKEN_MASK) +#define UART_UCR4_TCEN_MASK (0x8U) +#define UART_UCR4_TCEN_SHIFT (3U) +#define UART_UCR4_TCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_TCEN_SHIFT)) & UART_UCR4_TCEN_MASK) +#define UART_UCR4_LPBYP_MASK (0x10U) +#define UART_UCR4_LPBYP_SHIFT (4U) +#define UART_UCR4_LPBYP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_LPBYP_SHIFT)) & UART_UCR4_LPBYP_MASK) +#define UART_UCR4_IRSC_MASK (0x20U) +#define UART_UCR4_IRSC_SHIFT (5U) +#define UART_UCR4_IRSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IRSC_SHIFT)) & UART_UCR4_IRSC_MASK) +#define UART_UCR4_IDDMAEN_MASK (0x40U) +#define UART_UCR4_IDDMAEN_SHIFT (6U) +#define UART_UCR4_IDDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IDDMAEN_SHIFT)) & UART_UCR4_IDDMAEN_MASK) +#define UART_UCR4_WKEN_MASK (0x80U) +#define UART_UCR4_WKEN_SHIFT (7U) +#define UART_UCR4_WKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_WKEN_SHIFT)) & UART_UCR4_WKEN_MASK) +#define UART_UCR4_ENIRI_MASK (0x100U) +#define UART_UCR4_ENIRI_SHIFT (8U) +#define UART_UCR4_ENIRI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_ENIRI_SHIFT)) & UART_UCR4_ENIRI_MASK) +#define UART_UCR4_INVR_MASK (0x200U) +#define UART_UCR4_INVR_SHIFT (9U) +#define UART_UCR4_INVR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_INVR_SHIFT)) & UART_UCR4_INVR_MASK) +#define UART_UCR4_CTSTL_MASK (0xFC00U) +#define UART_UCR4_CTSTL_SHIFT (10U) +#define UART_UCR4_CTSTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_CTSTL_SHIFT)) & UART_UCR4_CTSTL_MASK) + +/*! @name UFCR - UART FIFO Control Register */ +#define UART_UFCR_RXTL_MASK (0x3FU) +#define UART_UFCR_RXTL_SHIFT (0U) +#define UART_UFCR_RXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RXTL_SHIFT)) & UART_UFCR_RXTL_MASK) +#define UART_UFCR_DCEDTE_MASK (0x40U) +#define UART_UFCR_DCEDTE_SHIFT (6U) +#define UART_UFCR_DCEDTE(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_DCEDTE_SHIFT)) & UART_UFCR_DCEDTE_MASK) +#define UART_UFCR_RFDIV_MASK (0x380U) +#define UART_UFCR_RFDIV_SHIFT (7U) +#define UART_UFCR_RFDIV(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RFDIV_SHIFT)) & UART_UFCR_RFDIV_MASK) +#define UART_UFCR_TXTL_MASK (0xFC00U) +#define UART_UFCR_TXTL_SHIFT (10U) +#define UART_UFCR_TXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_TXTL_SHIFT)) & UART_UFCR_TXTL_MASK) + +/*! @name USR1 - UART Status Register 1 */ +#define UART_USR1_SAD_MASK (0x8U) +#define UART_USR1_SAD_SHIFT (3U) +#define UART_USR1_SAD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_SAD_SHIFT)) & UART_USR1_SAD_MASK) +#define UART_USR1_AWAKE_MASK (0x10U) +#define UART_USR1_AWAKE_SHIFT (4U) +#define UART_USR1_AWAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AWAKE_SHIFT)) & UART_USR1_AWAKE_MASK) +#define UART_USR1_AIRINT_MASK (0x20U) +#define UART_USR1_AIRINT_SHIFT (5U) +#define UART_USR1_AIRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AIRINT_SHIFT)) & UART_USR1_AIRINT_MASK) +#define UART_USR1_RXDS_MASK (0x40U) +#define UART_USR1_RXDS_SHIFT (6U) +#define UART_USR1_RXDS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RXDS_SHIFT)) & UART_USR1_RXDS_MASK) +#define UART_USR1_DTRD_MASK (0x80U) +#define UART_USR1_DTRD_SHIFT (7U) +#define UART_USR1_DTRD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_DTRD_SHIFT)) & UART_USR1_DTRD_MASK) +#define UART_USR1_AGTIM_MASK (0x100U) +#define UART_USR1_AGTIM_SHIFT (8U) +#define UART_USR1_AGTIM(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AGTIM_SHIFT)) & UART_USR1_AGTIM_MASK) +#define UART_USR1_RRDY_MASK (0x200U) +#define UART_USR1_RRDY_SHIFT (9U) +#define UART_USR1_RRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RRDY_SHIFT)) & UART_USR1_RRDY_MASK) +#define UART_USR1_FRAMERR_MASK (0x400U) +#define UART_USR1_FRAMERR_SHIFT (10U) +#define UART_USR1_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_FRAMERR_SHIFT)) & UART_USR1_FRAMERR_MASK) +#define UART_USR1_ESCF_MASK (0x800U) +#define UART_USR1_ESCF_SHIFT (11U) +#define UART_USR1_ESCF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_ESCF_SHIFT)) & UART_USR1_ESCF_MASK) +#define UART_USR1_RTSD_MASK (0x1000U) +#define UART_USR1_RTSD_SHIFT (12U) +#define UART_USR1_RTSD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSD_SHIFT)) & UART_USR1_RTSD_MASK) +#define UART_USR1_TRDY_MASK (0x2000U) +#define UART_USR1_TRDY_SHIFT (13U) +#define UART_USR1_TRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_TRDY_SHIFT)) & UART_USR1_TRDY_MASK) +#define UART_USR1_RTSS_MASK (0x4000U) +#define UART_USR1_RTSS_SHIFT (14U) +#define UART_USR1_RTSS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSS_SHIFT)) & UART_USR1_RTSS_MASK) +#define UART_USR1_PARITYERR_MASK (0x8000U) +#define UART_USR1_PARITYERR_SHIFT (15U) +#define UART_USR1_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_PARITYERR_SHIFT)) & UART_USR1_PARITYERR_MASK) + +/*! @name USR2 - UART Status Register 2 */ +#define UART_USR2_RDR_MASK (0x1U) +#define UART_USR2_RDR_SHIFT (0U) +#define UART_USR2_RDR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RDR_SHIFT)) & UART_USR2_RDR_MASK) +#define UART_USR2_ORE_MASK (0x2U) +#define UART_USR2_ORE_SHIFT (1U) +#define UART_USR2_ORE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ORE_SHIFT)) & UART_USR2_ORE_MASK) +#define UART_USR2_BRCD_MASK (0x4U) +#define UART_USR2_BRCD_SHIFT (2U) +#define UART_USR2_BRCD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_BRCD_SHIFT)) & UART_USR2_BRCD_MASK) +#define UART_USR2_TXDC_MASK (0x8U) +#define UART_USR2_TXDC_SHIFT (3U) +#define UART_USR2_TXDC(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXDC_SHIFT)) & UART_USR2_TXDC_MASK) +#define UART_USR2_RTSF_MASK (0x10U) +#define UART_USR2_RTSF_SHIFT (4U) +#define UART_USR2_RTSF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RTSF_SHIFT)) & UART_USR2_RTSF_MASK) +#define UART_USR2_DCDIN_MASK (0x20U) +#define UART_USR2_DCDIN_SHIFT (5U) +#define UART_USR2_DCDIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDIN_SHIFT)) & UART_USR2_DCDIN_MASK) +#define UART_USR2_DCDDELT_MASK (0x40U) +#define UART_USR2_DCDDELT_SHIFT (6U) +#define UART_USR2_DCDDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDDELT_SHIFT)) & UART_USR2_DCDDELT_MASK) +#define UART_USR2_WAKE_MASK (0x80U) +#define UART_USR2_WAKE_SHIFT (7U) +#define UART_USR2_WAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_WAKE_SHIFT)) & UART_USR2_WAKE_MASK) +#define UART_USR2_IRINT_MASK (0x100U) +#define UART_USR2_IRINT_SHIFT (8U) +#define UART_USR2_IRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IRINT_SHIFT)) & UART_USR2_IRINT_MASK) +#define UART_USR2_RIIN_MASK (0x200U) +#define UART_USR2_RIIN_SHIFT (9U) +#define UART_USR2_RIIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIIN_SHIFT)) & UART_USR2_RIIN_MASK) +#define UART_USR2_RIDELT_MASK (0x400U) +#define UART_USR2_RIDELT_SHIFT (10U) +#define UART_USR2_RIDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIDELT_SHIFT)) & UART_USR2_RIDELT_MASK) +#define UART_USR2_ACST_MASK (0x800U) +#define UART_USR2_ACST_SHIFT (11U) +#define UART_USR2_ACST(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ACST_SHIFT)) & UART_USR2_ACST_MASK) +#define UART_USR2_IDLE_MASK (0x1000U) +#define UART_USR2_IDLE_SHIFT (12U) +#define UART_USR2_IDLE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IDLE_SHIFT)) & UART_USR2_IDLE_MASK) +#define UART_USR2_DTRF_MASK (0x2000U) +#define UART_USR2_DTRF_SHIFT (13U) +#define UART_USR2_DTRF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DTRF_SHIFT)) & UART_USR2_DTRF_MASK) +#define UART_USR2_TXFE_MASK (0x4000U) +#define UART_USR2_TXFE_SHIFT (14U) +#define UART_USR2_TXFE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXFE_SHIFT)) & UART_USR2_TXFE_MASK) +#define UART_USR2_ADET_MASK (0x8000U) +#define UART_USR2_ADET_SHIFT (15U) +#define UART_USR2_ADET(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ADET_SHIFT)) & UART_USR2_ADET_MASK) + +/*! @name UESC - UART Escape Character Register */ +#define UART_UESC_ESC_CHAR_MASK (0xFFU) +#define UART_UESC_ESC_CHAR_SHIFT (0U) +#define UART_UESC_ESC_CHAR(x) (((uint32_t)(((uint32_t)(x)) << UART_UESC_ESC_CHAR_SHIFT)) & UART_UESC_ESC_CHAR_MASK) + +/*! @name UTIM - UART Escape Timer Register */ +#define UART_UTIM_TIM_MASK (0xFFFU) +#define UART_UTIM_TIM_SHIFT (0U) +#define UART_UTIM_TIM(x) (((uint32_t)(((uint32_t)(x)) << UART_UTIM_TIM_SHIFT)) & UART_UTIM_TIM_MASK) + +/*! @name UBIR - UART BRM Incremental Register */ +#define UART_UBIR_INC_MASK (0xFFFFU) +#define UART_UBIR_INC_SHIFT (0U) +#define UART_UBIR_INC(x) (((uint32_t)(((uint32_t)(x)) << UART_UBIR_INC_SHIFT)) & UART_UBIR_INC_MASK) + +/*! @name UBMR - UART BRM Modulator Register */ +#define UART_UBMR_MOD_MASK (0xFFFFU) +#define UART_UBMR_MOD_SHIFT (0U) +#define UART_UBMR_MOD(x) (((uint32_t)(((uint32_t)(x)) << UART_UBMR_MOD_SHIFT)) & UART_UBMR_MOD_MASK) + +/*! @name UBRC - UART Baud Rate Count Register */ +#define UART_UBRC_BCNT_MASK (0xFFFFU) +#define UART_UBRC_BCNT_SHIFT (0U) +#define UART_UBRC_BCNT(x) (((uint32_t)(((uint32_t)(x)) << UART_UBRC_BCNT_SHIFT)) & UART_UBRC_BCNT_MASK) + +/*! @name ONEMS - UART One Millisecond Register */ +#define UART_ONEMS_ONEMS_MASK (0xFFFFFFU) +#define UART_ONEMS_ONEMS_SHIFT (0U) +#define UART_ONEMS_ONEMS(x) (((uint32_t)(((uint32_t)(x)) << UART_ONEMS_ONEMS_SHIFT)) & UART_ONEMS_ONEMS_MASK) + +/*! @name UTS - UART Test Register */ +#define UART_UTS_SOFTRST_MASK (0x1U) +#define UART_UTS_SOFTRST_SHIFT (0U) +#define UART_UTS_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_SOFTRST_SHIFT)) & UART_UTS_SOFTRST_MASK) +#define UART_UTS_RXFULL_MASK (0x8U) +#define UART_UTS_RXFULL_SHIFT (3U) +#define UART_UTS_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXFULL_SHIFT)) & UART_UTS_RXFULL_MASK) +#define UART_UTS_TXFULL_MASK (0x10U) +#define UART_UTS_TXFULL_SHIFT (4U) +#define UART_UTS_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXFULL_SHIFT)) & UART_UTS_TXFULL_MASK) +#define UART_UTS_RXEMPTY_MASK (0x20U) +#define UART_UTS_RXEMPTY_SHIFT (5U) +#define UART_UTS_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXEMPTY_SHIFT)) & UART_UTS_RXEMPTY_MASK) +#define UART_UTS_TXEMPTY_MASK (0x40U) +#define UART_UTS_TXEMPTY_SHIFT (6U) +#define UART_UTS_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXEMPTY_SHIFT)) & UART_UTS_TXEMPTY_MASK) +#define UART_UTS_RXDBG_MASK (0x200U) +#define UART_UTS_RXDBG_SHIFT (9U) +#define UART_UTS_RXDBG(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXDBG_SHIFT)) & UART_UTS_RXDBG_MASK) +#define UART_UTS_LOOPIR_MASK (0x400U) +#define UART_UTS_LOOPIR_SHIFT (10U) +#define UART_UTS_LOOPIR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOPIR_SHIFT)) & UART_UTS_LOOPIR_MASK) +#define UART_UTS_DBGEN_MASK (0x800U) +#define UART_UTS_DBGEN_SHIFT (11U) +#define UART_UTS_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_DBGEN_SHIFT)) & UART_UTS_DBGEN_MASK) +#define UART_UTS_LOOP_MASK (0x1000U) +#define UART_UTS_LOOP_SHIFT (12U) +#define UART_UTS_LOOP(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOP_SHIFT)) & UART_UTS_LOOP_MASK) +#define UART_UTS_FRCPERR_MASK (0x2000U) +#define UART_UTS_FRCPERR_SHIFT (13U) +#define UART_UTS_FRCPERR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_FRCPERR_SHIFT)) & UART_UTS_FRCPERR_MASK) + +/*! @name UMCR - UART RS-485 Mode Control Register */ +#define UART_UMCR_MDEN_MASK (0x1U) +#define UART_UMCR_MDEN_SHIFT (0U) +#define UART_UMCR_MDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_MDEN_SHIFT)) & UART_UMCR_MDEN_MASK) +#define UART_UMCR_SLAM_MASK (0x2U) +#define UART_UMCR_SLAM_SHIFT (1U) +#define UART_UMCR_SLAM(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLAM_SHIFT)) & UART_UMCR_SLAM_MASK) +#define UART_UMCR_TXB8_MASK (0x4U) +#define UART_UMCR_TXB8_SHIFT (2U) +#define UART_UMCR_TXB8(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_TXB8_SHIFT)) & UART_UMCR_TXB8_MASK) +#define UART_UMCR_SADEN_MASK (0x8U) +#define UART_UMCR_SADEN_SHIFT (3U) +#define UART_UMCR_SADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SADEN_SHIFT)) & UART_UMCR_SADEN_MASK) +#define UART_UMCR_SLADDR_MASK (0xFF00U) +#define UART_UMCR_SLADDR_SHIFT (8U) +#define UART_UMCR_SLADDR(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLADDR_SHIFT)) & UART_UMCR_SLADDR_MASK) + + +/*! + * @} + */ /* end of group UART_Register_Masks */ + + +/* UART - Peripheral instance base addresses */ +/** Peripheral UART1 base address */ +#define UART1_BASE (0x2020000u) +/** Peripheral UART1 base pointer */ +#define UART1 ((UART_Type *)UART1_BASE) +/** Peripheral UART2 base address */ +#define UART2_BASE (0x21E8000u) +/** Peripheral UART2 base pointer */ +#define UART2 ((UART_Type *)UART2_BASE) +/** Peripheral UART3 base address */ +#define UART3_BASE (0x21EC000u) +/** Peripheral UART3 base pointer */ +#define UART3 ((UART_Type *)UART3_BASE) +/** Peripheral UART4 base address */ +#define UART4_BASE (0x21F0000u) +/** Peripheral UART4 base pointer */ +#define UART4 ((UART_Type *)UART4_BASE) +/** Peripheral UART5 base address */ +#define UART5_BASE (0x21F4000u) +/** Peripheral UART5 base pointer */ +#define UART5 ((UART_Type *)UART5_BASE) +/** Peripheral UART6 base address */ +#define UART6_BASE (0x21FC000u) +/** Peripheral UART6 base pointer */ +#define UART6 ((UART_Type *)UART6_BASE) +/** Peripheral UART7 base address */ +#define UART7_BASE (0x2018000u) +/** Peripheral UART7 base pointer */ +#define UART7 ((UART_Type *)UART7_BASE) +/** Peripheral UART8 base address */ +#define UART8_BASE (0x2288000u) +/** Peripheral UART8 base pointer */ +#define UART8 ((UART_Type *)UART8_BASE) +/** Array initializer of UART peripheral base addresses */ +#define UART_BASE_ADDRS { 0u, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE, UART6_BASE, UART7_BASE, UART8_BASE } +/** Array initializer of UART peripheral base pointers */ +#define UART_BASE_PTRS { (UART_Type *)0u, UART1, UART2, UART3, UART4, UART5, UART6, UART7, UART8 } +/** Interrupt vectors for the UART peripheral type */ +#define UART_IRQS { NotAvail_IRQn, UART1_IRQn, UART2_IRQn, UART3_IRQn, UART4_IRQn, UART5_IRQn, UART6_IRQn, UART7_IRQn, UART8_IRQn } + +/*! + * @} + */ /* end of group UART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint32_t ID; /**< Identification register, offset: 0x0 */ + __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ + __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ + __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ + __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ + __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ + uint8_t RESERVED_0[104]; + __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ + __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ + __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ + __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ + __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ + uint8_t RESERVED_1[108]; + __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ + uint8_t RESERVED_2[1]; + __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ + uint8_t RESERVED_3[20]; + __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ + uint8_t RESERVED_4[2]; + __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ + uint8_t RESERVED_5[24]; + __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */ + __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */ + __IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */ + __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ + uint8_t RESERVED_6[4]; + union { /* offset: 0x154 */ + __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ + __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ + }; + union { /* offset: 0x158 */ + __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ + __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ + }; + uint8_t RESERVED_7[4]; + __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ + __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ + uint8_t RESERVED_8[16]; + __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ + __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ + __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */ + __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ + uint8_t RESERVED_9[28]; + __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ + __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ + __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ + __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ + __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ + __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ + __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ + __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ + __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name ID - Identification register */ +#define USB_ID_ID_MASK (0x3FU) +#define USB_ID_ID_SHIFT (0U) +#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) +#define USB_ID_NID_MASK (0x3F00U) +#define USB_ID_NID_SHIFT (8U) +#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK) +#define USB_ID_REVISION_MASK (0xFF0000U) +#define USB_ID_REVISION_SHIFT (16U) +#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) + +/*! @name HWGENERAL - Hardware General */ +#define USB_HWGENERAL_PHYW_MASK (0x30U) +#define USB_HWGENERAL_PHYW_SHIFT (4U) +#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) +#define USB_HWGENERAL_PHYM_MASK (0x1C0U) +#define USB_HWGENERAL_PHYM_SHIFT (6U) +#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) +#define USB_HWGENERAL_SM_MASK (0x600U) +#define USB_HWGENERAL_SM_SHIFT (9U) +#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) + +/*! @name HWHOST - Host Hardware Parameters */ +#define USB_HWHOST_HC_MASK (0x1U) +#define USB_HWHOST_HC_SHIFT (0U) +#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) +#define USB_HWHOST_NPORT_MASK (0xEU) +#define USB_HWHOST_NPORT_SHIFT (1U) +#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) + +/*! @name HWDEVICE - Device Hardware Parameters */ +#define USB_HWDEVICE_DC_MASK (0x1U) +#define USB_HWDEVICE_DC_SHIFT (0U) +#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) +#define USB_HWDEVICE_DEVEP_MASK (0x3EU) +#define USB_HWDEVICE_DEVEP_SHIFT (1U) +#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) + +/*! @name HWTXBUF - TX Buffer Hardware Parameters */ +#define USB_HWTXBUF_TXBURST_MASK (0xFFU) +#define USB_HWTXBUF_TXBURST_SHIFT (0U) +#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) +#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) +#define USB_HWTXBUF_TXCHANADD_SHIFT (16U) +#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) + +/*! @name HWRXBUF - RX Buffer Hardware Parameters */ +#define USB_HWRXBUF_RXBURST_MASK (0xFFU) +#define USB_HWRXBUF_RXBURST_SHIFT (0U) +#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) +#define USB_HWRXBUF_RXADD_MASK (0xFF00U) +#define USB_HWRXBUF_RXADD_SHIFT (8U) +#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) + +/*! @name GPTIMER0LD - General Purpose Timer #0 Load */ +#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) + +/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ +#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) +#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +#define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) +#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) +#define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) +#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +#define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) + +/*! @name GPTIMER1LD - General Purpose Timer #1 Load */ +#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) + +/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ +#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) +#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +#define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) +#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) +#define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) +#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +#define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) + +/*! @name SBUSCFG - System Bus Config */ +#define USB_SBUSCFG_AHBBRST_MASK (0x7U) +#define USB_SBUSCFG_AHBBRST_SHIFT (0U) +#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) + +/*! @name CAPLENGTH - Capability Registers Length */ +#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) +#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) +#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) + +/*! @name HCIVERSION - Host Controller Interface Version */ +#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) +#define USB_HCIVERSION_HCIVERSION_SHIFT (0U) +#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +#define USB_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USB_HCSPARAMS_N_PORTS_SHIFT (0U) +#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) +#define USB_HCSPARAMS_PPC_MASK (0x10U) +#define USB_HCSPARAMS_PPC_SHIFT (4U) +#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK) +#define USB_HCSPARAMS_N_PCC_MASK (0xF00U) +#define USB_HCSPARAMS_N_PCC_SHIFT (8U) +#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) +#define USB_HCSPARAMS_N_CC_MASK (0xF000U) +#define USB_HCSPARAMS_N_CC_SHIFT (12U) +#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) +#define USB_HCSPARAMS_PI_MASK (0x10000U) +#define USB_HCSPARAMS_PI_SHIFT (16U) +#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK) +#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U) +#define USB_HCSPARAMS_N_PTT_SHIFT (20U) +#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK) +#define USB_HCSPARAMS_N_TT_MASK (0xF000000U) +#define USB_HCSPARAMS_N_TT_SHIFT (24U) +#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) + +/*! @name HCCPARAMS - Host Controller Capability Parameters */ +#define USB_HCCPARAMS_ADC_MASK (0x1U) +#define USB_HCCPARAMS_ADC_SHIFT (0U) +#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) +#define USB_HCCPARAMS_PFL_MASK (0x2U) +#define USB_HCCPARAMS_PFL_SHIFT (1U) +#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK) +#define USB_HCCPARAMS_ASP_MASK (0x4U) +#define USB_HCCPARAMS_ASP_SHIFT (2U) +#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK) +#define USB_HCCPARAMS_IST_MASK (0xF0U) +#define USB_HCCPARAMS_IST_SHIFT (4U) +#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK) +#define USB_HCCPARAMS_EECP_MASK (0xFF00U) +#define USB_HCCPARAMS_EECP_SHIFT (8U) +#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) + +/*! @name DCIVERSION - Device Controller Interface Version */ +#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) +#define USB_DCIVERSION_DCIVERSION_SHIFT (0U) +#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) + +/*! @name DCCPARAMS - Device Controller Capability Parameters */ +#define USB_DCCPARAMS_DEN_MASK (0x1FU) +#define USB_DCCPARAMS_DEN_SHIFT (0U) +#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) +#define USB_DCCPARAMS_DC_MASK (0x80U) +#define USB_DCCPARAMS_DC_SHIFT (7U) +#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK) +#define USB_DCCPARAMS_HC_MASK (0x100U) +#define USB_DCCPARAMS_HC_SHIFT (8U) +#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) + +/*! @name USBCMD - USB Command Register */ +#define USB_USBCMD_RS_MASK (0x1U) +#define USB_USBCMD_RS_SHIFT (0U) +#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) +#define USB_USBCMD_RST_MASK (0x2U) +#define USB_USBCMD_RST_SHIFT (1U) +#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK) +#define USB_USBCMD_FS_1_MASK (0xCU) +#define USB_USBCMD_FS_1_SHIFT (2U) +#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) +#define USB_USBCMD_PSE_MASK (0x10U) +#define USB_USBCMD_PSE_SHIFT (4U) +#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) +#define USB_USBCMD_ASE_MASK (0x20U) +#define USB_USBCMD_ASE_SHIFT (5U) +#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) +#define USB_USBCMD_IAA_MASK (0x40U) +#define USB_USBCMD_IAA_SHIFT (6U) +#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK) +#define USB_USBCMD_ASP_MASK (0x300U) +#define USB_USBCMD_ASP_SHIFT (8U) +#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK) +#define USB_USBCMD_ASPE_MASK (0x800U) +#define USB_USBCMD_ASPE_SHIFT (11U) +#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK) +#define USB_USBCMD_ATDTW_MASK (0x1000U) +#define USB_USBCMD_ATDTW_SHIFT (12U) +#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK) +#define USB_USBCMD_SUTW_MASK (0x2000U) +#define USB_USBCMD_SUTW_SHIFT (13U) +#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) +#define USB_USBCMD_FS_2_MASK (0x8000U) +#define USB_USBCMD_FS_2_SHIFT (15U) +#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) +#define USB_USBCMD_ITC_MASK (0xFF0000U) +#define USB_USBCMD_ITC_SHIFT (16U) +#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) + +/*! @name USBSTS - USB Status Register */ +#define USB_USBSTS_UI_MASK (0x1U) +#define USB_USBSTS_UI_SHIFT (0U) +#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) +#define USB_USBSTS_UEI_MASK (0x2U) +#define USB_USBSTS_UEI_SHIFT (1U) +#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) +#define USB_USBSTS_PCI_MASK (0x4U) +#define USB_USBSTS_PCI_SHIFT (2U) +#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) +#define USB_USBSTS_FRI_MASK (0x8U) +#define USB_USBSTS_FRI_SHIFT (3U) +#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) +#define USB_USBSTS_SEI_MASK (0x10U) +#define USB_USBSTS_SEI_SHIFT (4U) +#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) +#define USB_USBSTS_AAI_MASK (0x20U) +#define USB_USBSTS_AAI_SHIFT (5U) +#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) +#define USB_USBSTS_URI_MASK (0x40U) +#define USB_USBSTS_URI_SHIFT (6U) +#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) +#define USB_USBSTS_SRI_MASK (0x80U) +#define USB_USBSTS_SRI_SHIFT (7U) +#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) +#define USB_USBSTS_SLI_MASK (0x100U) +#define USB_USBSTS_SLI_SHIFT (8U) +#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) +#define USB_USBSTS_ULPII_MASK (0x400U) +#define USB_USBSTS_ULPII_SHIFT (10U) +#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) +#define USB_USBSTS_HCH_MASK (0x1000U) +#define USB_USBSTS_HCH_SHIFT (12U) +#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK) +#define USB_USBSTS_RCL_MASK (0x2000U) +#define USB_USBSTS_RCL_SHIFT (13U) +#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK) +#define USB_USBSTS_PS_MASK (0x4000U) +#define USB_USBSTS_PS_SHIFT (14U) +#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK) +#define USB_USBSTS_AS_MASK (0x8000U) +#define USB_USBSTS_AS_SHIFT (15U) +#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK) +#define USB_USBSTS_NAKI_MASK (0x10000U) +#define USB_USBSTS_NAKI_SHIFT (16U) +#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK) +#define USB_USBSTS_TI0_MASK (0x1000000U) +#define USB_USBSTS_TI0_SHIFT (24U) +#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) +#define USB_USBSTS_TI1_MASK (0x2000000U) +#define USB_USBSTS_TI1_SHIFT (25U) +#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) + +/*! @name USBINTR - Interrupt Enable Register */ +#define USB_USBINTR_UE_MASK (0x1U) +#define USB_USBINTR_UE_SHIFT (0U) +#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) +#define USB_USBINTR_UEE_MASK (0x2U) +#define USB_USBINTR_UEE_SHIFT (1U) +#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK) +#define USB_USBINTR_PCE_MASK (0x4U) +#define USB_USBINTR_PCE_SHIFT (2U) +#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK) +#define USB_USBINTR_FRE_MASK (0x8U) +#define USB_USBINTR_FRE_SHIFT (3U) +#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK) +#define USB_USBINTR_SEE_MASK (0x10U) +#define USB_USBINTR_SEE_SHIFT (4U) +#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK) +#define USB_USBINTR_AAE_MASK (0x20U) +#define USB_USBINTR_AAE_SHIFT (5U) +#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK) +#define USB_USBINTR_URE_MASK (0x40U) +#define USB_USBINTR_URE_SHIFT (6U) +#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK) +#define USB_USBINTR_SRE_MASK (0x80U) +#define USB_USBINTR_SRE_SHIFT (7U) +#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK) +#define USB_USBINTR_SLE_MASK (0x100U) +#define USB_USBINTR_SLE_SHIFT (8U) +#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK) +#define USB_USBINTR_ULPIE_MASK (0x400U) +#define USB_USBINTR_ULPIE_SHIFT (10U) +#define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK) +#define USB_USBINTR_NAKE_MASK (0x10000U) +#define USB_USBINTR_NAKE_SHIFT (16U) +#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK) +#define USB_USBINTR_UAIE_MASK (0x40000U) +#define USB_USBINTR_UAIE_SHIFT (18U) +#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK) +#define USB_USBINTR_UPIE_MASK (0x80000U) +#define USB_USBINTR_UPIE_SHIFT (19U) +#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK) +#define USB_USBINTR_TIE0_MASK (0x1000000U) +#define USB_USBINTR_TIE0_SHIFT (24U) +#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK) +#define USB_USBINTR_TIE1_MASK (0x2000000U) +#define USB_USBINTR_TIE1_SHIFT (25U) +#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) + +/*! @name FRINDEX - USB Frame Index */ +#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) +#define USB_FRINDEX_FRINDEX_SHIFT (0U) +#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) + +/*! @name DEVICEADDR - Device Address */ +#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) +#define USB_DEVICEADDR_USBADRA_SHIFT (24U) +#define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) +#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) +#define USB_DEVICEADDR_USBADR_SHIFT (25U) +#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) + +/*! @name PERIODICLISTBASE - Frame List Base Address */ +#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) +#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) +#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) + +/*! @name ASYNCLISTADDR - Next Asynch. Address */ +#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) +#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) +#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) + +/*! @name ENDPTLISTADDR - Endpoint List Address */ +#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) +#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) +#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) + +/*! @name BURSTSIZE - Programmable Burst Size */ +#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) +#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) +#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) +#define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U) +#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) +#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) + +/*! @name TXFILLTUNING - TX FIFO Fill Tuning */ +#define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU) +#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) +#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) +#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) +#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) +#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) +#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) +#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) +#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) + +/*! @name ENDPTNAK - Endpoint NAK */ +#define USB_ENDPTNAK_EPRN_MASK (0xFFU) +#define USB_ENDPTNAK_EPRN_SHIFT (0U) +#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) +#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) +#define USB_ENDPTNAK_EPTN_SHIFT (16U) +#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) + +/*! @name ENDPTNAKEN - Endpoint NAK Enable */ +#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) +#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) +#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) +#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) +#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) +#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) + +/*! @name CONFIGFLAG - Configure Flag Register */ +#define USB_CONFIGFLAG_CF_MASK (0x1U) +#define USB_CONFIGFLAG_CF_SHIFT (0U) +#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) + +/*! @name PORTSC1 - Port Status & Control */ +#define USB_PORTSC1_CCS_MASK (0x1U) +#define USB_PORTSC1_CCS_SHIFT (0U) +#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) +#define USB_PORTSC1_CSC_MASK (0x2U) +#define USB_PORTSC1_CSC_SHIFT (1U) +#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK) +#define USB_PORTSC1_PE_MASK (0x4U) +#define USB_PORTSC1_PE_SHIFT (2U) +#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK) +#define USB_PORTSC1_PEC_MASK (0x8U) +#define USB_PORTSC1_PEC_SHIFT (3U) +#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) +#define USB_PORTSC1_OCA_MASK (0x10U) +#define USB_PORTSC1_OCA_SHIFT (4U) +#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) +#define USB_PORTSC1_OCC_MASK (0x20U) +#define USB_PORTSC1_OCC_SHIFT (5U) +#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK) +#define USB_PORTSC1_FPR_MASK (0x40U) +#define USB_PORTSC1_FPR_SHIFT (6U) +#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK) +#define USB_PORTSC1_SUSP_MASK (0x80U) +#define USB_PORTSC1_SUSP_SHIFT (7U) +#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK) +#define USB_PORTSC1_PR_MASK (0x100U) +#define USB_PORTSC1_PR_SHIFT (8U) +#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK) +#define USB_PORTSC1_HSP_MASK (0x200U) +#define USB_PORTSC1_HSP_SHIFT (9U) +#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) +#define USB_PORTSC1_LS_MASK (0xC00U) +#define USB_PORTSC1_LS_SHIFT (10U) +#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) +#define USB_PORTSC1_PP_MASK (0x1000U) +#define USB_PORTSC1_PP_SHIFT (12U) +#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK) +#define USB_PORTSC1_PO_MASK (0x2000U) +#define USB_PORTSC1_PO_SHIFT (13U) +#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) +#define USB_PORTSC1_PIC_MASK (0xC000U) +#define USB_PORTSC1_PIC_SHIFT (14U) +#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) +#define USB_PORTSC1_PTC_MASK (0xF0000U) +#define USB_PORTSC1_PTC_SHIFT (16U) +#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) +#define USB_PORTSC1_WKCN_MASK (0x100000U) +#define USB_PORTSC1_WKCN_SHIFT (20U) +#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK) +#define USB_PORTSC1_WKDC_MASK (0x200000U) +#define USB_PORTSC1_WKDC_SHIFT (21U) +#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK) +#define USB_PORTSC1_WKOC_MASK (0x400000U) +#define USB_PORTSC1_WKOC_SHIFT (22U) +#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) +#define USB_PORTSC1_PHCD_MASK (0x800000U) +#define USB_PORTSC1_PHCD_SHIFT (23U) +#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) +#define USB_PORTSC1_PFSC_MASK (0x1000000U) +#define USB_PORTSC1_PFSC_SHIFT (24U) +#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) +#define USB_PORTSC1_PTS_2_MASK (0x2000000U) +#define USB_PORTSC1_PTS_2_SHIFT (25U) +#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) +#define USB_PORTSC1_PSPD_MASK (0xC000000U) +#define USB_PORTSC1_PSPD_SHIFT (26U) +#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) +#define USB_PORTSC1_PTW_MASK (0x10000000U) +#define USB_PORTSC1_PTW_SHIFT (28U) +#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) +#define USB_PORTSC1_STS_MASK (0x20000000U) +#define USB_PORTSC1_STS_SHIFT (29U) +#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK) +#define USB_PORTSC1_PTS_1_MASK (0xC0000000U) +#define USB_PORTSC1_PTS_1_SHIFT (30U) +#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) + +/*! @name OTGSC - On-The-Go Status & control */ +#define USB_OTGSC_VD_MASK (0x1U) +#define USB_OTGSC_VD_SHIFT (0U) +#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) +#define USB_OTGSC_VC_MASK (0x2U) +#define USB_OTGSC_VC_SHIFT (1U) +#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK) +#define USB_OTGSC_OT_MASK (0x8U) +#define USB_OTGSC_OT_SHIFT (3U) +#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK) +#define USB_OTGSC_DP_MASK (0x10U) +#define USB_OTGSC_DP_SHIFT (4U) +#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK) +#define USB_OTGSC_IDPU_MASK (0x20U) +#define USB_OTGSC_IDPU_SHIFT (5U) +#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK) +#define USB_OTGSC_ID_MASK (0x100U) +#define USB_OTGSC_ID_SHIFT (8U) +#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK) +#define USB_OTGSC_AVV_MASK (0x200U) +#define USB_OTGSC_AVV_SHIFT (9U) +#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK) +#define USB_OTGSC_ASV_MASK (0x400U) +#define USB_OTGSC_ASV_SHIFT (10U) +#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK) +#define USB_OTGSC_BSV_MASK (0x800U) +#define USB_OTGSC_BSV_SHIFT (11U) +#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK) +#define USB_OTGSC_BSE_MASK (0x1000U) +#define USB_OTGSC_BSE_SHIFT (12U) +#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK) +#define USB_OTGSC_TOG_1MS_MASK (0x2000U) +#define USB_OTGSC_TOG_1MS_SHIFT (13U) +#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK) +#define USB_OTGSC_DPS_MASK (0x4000U) +#define USB_OTGSC_DPS_SHIFT (14U) +#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK) +#define USB_OTGSC_IDIS_MASK (0x10000U) +#define USB_OTGSC_IDIS_SHIFT (16U) +#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK) +#define USB_OTGSC_AVVIS_MASK (0x20000U) +#define USB_OTGSC_AVVIS_SHIFT (17U) +#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) +#define USB_OTGSC_ASVIS_MASK (0x40000U) +#define USB_OTGSC_ASVIS_SHIFT (18U) +#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) +#define USB_OTGSC_BSVIS_MASK (0x80000U) +#define USB_OTGSC_BSVIS_SHIFT (19U) +#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) +#define USB_OTGSC_BSEIS_MASK (0x100000U) +#define USB_OTGSC_BSEIS_SHIFT (20U) +#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) +#define USB_OTGSC_STATUS_1MS_MASK (0x200000U) +#define USB_OTGSC_STATUS_1MS_SHIFT (21U) +#define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK) +#define USB_OTGSC_DPIS_MASK (0x400000U) +#define USB_OTGSC_DPIS_SHIFT (22U) +#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) +#define USB_OTGSC_IDIE_MASK (0x1000000U) +#define USB_OTGSC_IDIE_SHIFT (24U) +#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK) +#define USB_OTGSC_AVVIE_MASK (0x2000000U) +#define USB_OTGSC_AVVIE_SHIFT (25U) +#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK) +#define USB_OTGSC_ASVIE_MASK (0x4000000U) +#define USB_OTGSC_ASVIE_SHIFT (26U) +#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK) +#define USB_OTGSC_BSVIE_MASK (0x8000000U) +#define USB_OTGSC_BSVIE_SHIFT (27U) +#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK) +#define USB_OTGSC_BSEIE_MASK (0x10000000U) +#define USB_OTGSC_BSEIE_SHIFT (28U) +#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK) +#define USB_OTGSC_EN_1MS_MASK (0x20000000U) +#define USB_OTGSC_EN_1MS_SHIFT (29U) +#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK) +#define USB_OTGSC_DPIE_MASK (0x40000000U) +#define USB_OTGSC_DPIE_SHIFT (30U) +#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) + +/*! @name USBMODE - USB Device Mode */ +#define USB_USBMODE_CM_MASK (0x3U) +#define USB_USBMODE_CM_SHIFT (0U) +#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) +#define USB_USBMODE_ES_MASK (0x4U) +#define USB_USBMODE_ES_SHIFT (2U) +#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) +#define USB_USBMODE_SLOM_MASK (0x8U) +#define USB_USBMODE_SLOM_SHIFT (3U) +#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) +#define USB_USBMODE_SDIS_MASK (0x10U) +#define USB_USBMODE_SDIS_SHIFT (4U) +#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) + +/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) + +/*! @name ENDPTPRIME - Endpoint Prime */ +#define USB_ENDPTPRIME_PERB_MASK (0xFFU) +#define USB_ENDPTPRIME_PERB_SHIFT (0U) +#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) +#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) +#define USB_ENDPTPRIME_PETB_SHIFT (16U) +#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) + +/*! @name ENDPTFLUSH - Endpoint Flush */ +#define USB_ENDPTFLUSH_FERB_MASK (0xFFU) +#define USB_ENDPTFLUSH_FERB_SHIFT (0U) +#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) +#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) +#define USB_ENDPTFLUSH_FETB_SHIFT (16U) +#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) + +/*! @name ENDPTSTAT - Endpoint Status */ +#define USB_ENDPTSTAT_ERBR_MASK (0xFFU) +#define USB_ENDPTSTAT_ERBR_SHIFT (0U) +#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) +#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) +#define USB_ENDPTSTAT_ETBR_SHIFT (16U) +#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) + +/*! @name ENDPTCOMPLETE - Endpoint Complete */ +#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) +#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) +#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) +#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) +#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) +#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) + +/*! @name ENDPTCTRL0 - Endpoint Control0 */ +#define USB_ENDPTCTRL0_RXS_MASK (0x1U) +#define USB_ENDPTCTRL0_RXS_SHIFT (0U) +#define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) +#define USB_ENDPTCTRL0_RXT_MASK (0xCU) +#define USB_ENDPTCTRL0_RXT_SHIFT (2U) +#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK) +#define USB_ENDPTCTRL0_RXE_MASK (0x80U) +#define USB_ENDPTCTRL0_RXE_SHIFT (7U) +#define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK) +#define USB_ENDPTCTRL0_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL0_TXS_SHIFT (16U) +#define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK) +#define USB_ENDPTCTRL0_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL0_TXT_SHIFT (18U) +#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK) +#define USB_ENDPTCTRL0_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL0_TXE_SHIFT (23U) +#define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) + +/*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ +#define USB_ENDPTCTRL_RXS_MASK (0x1U) +#define USB_ENDPTCTRL_RXS_SHIFT (0U) +#define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) +#define USB_ENDPTCTRL_RXD_MASK (0x2U) +#define USB_ENDPTCTRL_RXD_SHIFT (1U) +#define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK) +#define USB_ENDPTCTRL_RXT_MASK (0xCU) +#define USB_ENDPTCTRL_RXT_SHIFT (2U) +#define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK) +#define USB_ENDPTCTRL_RXI_MASK (0x20U) +#define USB_ENDPTCTRL_RXI_SHIFT (5U) +#define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK) +#define USB_ENDPTCTRL_RXR_MASK (0x40U) +#define USB_ENDPTCTRL_RXR_SHIFT (6U) +#define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK) +#define USB_ENDPTCTRL_RXE_MASK (0x80U) +#define USB_ENDPTCTRL_RXE_SHIFT (7U) +#define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK) +#define USB_ENDPTCTRL_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL_TXS_SHIFT (16U) +#define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK) +#define USB_ENDPTCTRL_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL_TXD_SHIFT (17U) +#define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK) +#define USB_ENDPTCTRL_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL_TXT_SHIFT (18U) +#define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK) +#define USB_ENDPTCTRL_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL_TXI_SHIFT (21U) +#define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK) +#define USB_ENDPTCTRL_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL_TXR_SHIFT (22U) +#define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK) +#define USB_ENDPTCTRL_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL_TXE_SHIFT (23U) +#define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) + +/* The count of USB_ENDPTCTRL */ +#define USB_ENDPTCTRL_COUNT (7U) + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB1 base address */ +#define USB1_BASE (0x2184000u) +/** Peripheral USB1 base pointer */ +#define USB1 ((USB_Type *)USB1_BASE) +/** Peripheral USB2 base address */ +#define USB2_BASE (0x2184200u) +/** Peripheral USB2 base pointer */ +#define USB2 ((USB_Type *)USB2_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn } +/* Backward compatibility */ +#define GPTIMER0CTL GPTIMER0CTRL +#define GPTIMER1CTL GPTIMER1CTRL +#define USB_SBUSCFG SBUSCFG +#define EPLISTADDR ENDPTLISTADDR +#define EPSETUPSR ENDPTSETUPSTAT +#define EPPRIME ENDPTPRIME +#define EPFLUSH ENDPTFLUSH +#define EPSR ENDPTSTAT +#define EPCOMPLETE ENDPTCOMPLETE +#define EPCR ENDPTCTRL +#define EPCR0 ENDPTCTRL0 +#define USBHS_ID_ID_MASK USB_ID_ID_MASK +#define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT +#define USBHS_ID_ID(x) USB_ID_ID(x) +#define USBHS_ID_NID_MASK USB_ID_NID_MASK +#define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT +#define USBHS_ID_NID(x) USB_ID_NID(x) +#define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK +#define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT +#define USBHS_ID_REVISION(x) USB_ID_REVISION(x) +#define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK +#define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT +#define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x) +#define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK +#define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT +#define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x) +#define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK +#define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT +#define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x) +#define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK +#define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT +#define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x) +#define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK +#define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT +#define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x) +#define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK +#define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT +#define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x) +#define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK +#define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT +#define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x) +#define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK +#define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT +#define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x) +#define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK +#define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT +#define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x) +#define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK +#define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT +#define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x) +#define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK +#define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT +#define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x) +#define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK +#define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT +#define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x) +#define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK +#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x) +#define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK +#define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x) +#define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK +#define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x) +#define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK +#define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x) +#define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK +#define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT +#define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x) +#define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK +#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x) +#define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK +#define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x) +#define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK +#define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x) +#define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK +#define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x) +#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK +#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT +#define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x) +#define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x) +#define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK +#define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT +#define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x) +#define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK +#define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT +#define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x) +#define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK +#define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT +#define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x) +#define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK +#define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT +#define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x) +#define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK +#define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT +#define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x) +#define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK +#define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT +#define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x) +#define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK +#define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT +#define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x) +#define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK +#define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT +#define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x) +#define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK +#define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT +#define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x) +#define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK +#define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT +#define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x) +#define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK +#define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT +#define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x) +#define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK +#define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT +#define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x) +#define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK +#define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT +#define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x) +#define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK +#define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT +#define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x) +#define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK +#define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT +#define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x) +#define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK +#define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT +#define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x) +#define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK +#define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT +#define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x) +#define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK +#define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT +#define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x) +#define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK +#define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT +#define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x) +#define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK +#define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT +#define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x) +#define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK +#define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT +#define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x) +#define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK +#define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT +#define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x) +#define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK +#define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT +#define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x) +#define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK +#define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT +#define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x) +#define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK +#define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT +#define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x) +#define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK +#define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT +#define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x) +#define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK +#define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT +#define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x) +#define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK +#define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT +#define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x) +#define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK +#define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT +#define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x) +#define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK +#define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT +#define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x) +#define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK +#define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT +#define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x) +#define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK +#define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT +#define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x) +#define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK +#define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT +#define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x) +#define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK +#define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT +#define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x) +#define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK +#define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT +#define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x) +#define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK +#define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT +#define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x) +#define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK +#define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT +#define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x) +#define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK +#define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT +#define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x) +#define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK +#define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT +#define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x) +#define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK +#define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT +#define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x) +#define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK +#define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT +#define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x) +#define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK +#define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT +#define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x) +#define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK +#define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT +#define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x) +#define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK +#define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT +#define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x) +#define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK +#define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT +#define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x) +#define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK +#define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT +#define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x) +#define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK +#define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT +#define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x) +#define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK +#define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT +#define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x) +#define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK +#define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT +#define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x) +#define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK +#define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT +#define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x) +#define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK +#define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT +#define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x) +#define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK +#define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT +#define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x) +#define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK +#define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT +#define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x) +#define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK +#define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT +#define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x) +#define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK +#define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT +#define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x) +#define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK +#define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT +#define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x) +#define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK +#define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT +#define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x) +#define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK +#define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT +#define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x) +#define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK +#define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT +#define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x) +#define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK +#define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT +#define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x) +#define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK +#define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT +#define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x) +#define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK +#define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT +#define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x) +#define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK +#define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT +#define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x) +#define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK +#define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT +#define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x) +#define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK +#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT +#define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x) +#define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK +#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT +#define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x) +#define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK +#define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT +#define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x) +#define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK +#define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT +#define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x) +#define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK +#define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT +#define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x) +#define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK +#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT +#define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x) +#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK +#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT +#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x) +#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK +#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT +#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x) +#define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK +#define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT +#define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x) +#define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK +#define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT +#define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x) +#define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK +#define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT +#define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x) +#define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK +#define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT +#define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x) +#define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK +#define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT +#define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x) +#define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK +#define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT +#define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x) +#define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK +#define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT +#define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x) +#define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK +#define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT +#define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x) +#define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK +#define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT +#define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x) +#define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK +#define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT +#define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x) +#define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK +#define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT +#define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x) +#define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK +#define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT +#define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x) +#define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK +#define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT +#define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x) +#define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK +#define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT +#define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x) +#define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK +#define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT +#define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x) +#define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK +#define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT +#define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x) +#define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK +#define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT +#define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x) +#define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK +#define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT +#define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x) +#define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK +#define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT +#define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x) +#define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK +#define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT +#define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x) +#define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK +#define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT +#define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x) +#define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK +#define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT +#define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x) +#define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK +#define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT +#define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x) +#define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK +#define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT +#define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x) +#define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK +#define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT +#define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x) +#define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK +#define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT +#define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x) +#define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK +#define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT +#define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x) +#define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK +#define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT +#define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x) +#define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK +#define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT +#define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x) +#define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK +#define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT +#define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x) +#define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK +#define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT +#define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x) +#define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK +#define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT +#define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x) +#define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK +#define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT +#define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x) +#define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK +#define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT +#define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x) +#define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK +#define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT +#define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x) +#define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK +#define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT +#define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x) +#define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK +#define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT +#define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x) +#define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK +#define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT +#define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x) +#define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK +#define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT +#define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x) +#define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK +#define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT +#define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x) +#define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK +#define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT +#define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x) +#define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK +#define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT +#define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x) +#define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK +#define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT +#define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x) +#define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK +#define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT +#define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x) +#define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK +#define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT +#define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x) +#define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK +#define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT +#define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x) +#define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK +#define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT +#define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x) +#define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK +#define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT +#define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x) +#define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK +#define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT +#define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x) +#define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK +#define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT +#define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x) +#define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK +#define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT +#define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x) +#define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK +#define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT +#define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x) +#define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK +#define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT +#define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x) +#define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK +#define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT +#define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x) +#define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK +#define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT +#define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x) +#define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK +#define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT +#define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x) +#define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK +#define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT +#define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x) +#define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK +#define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT +#define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x) +#define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK +#define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT +#define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x) +#define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK +#define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT +#define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x) +#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK +#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT +#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) +#define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK +#define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT +#define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x) +#define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK +#define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT +#define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x) +#define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK +#define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT +#define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x) +#define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK +#define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT +#define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x) +#define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK +#define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT +#define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x) +#define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK +#define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT +#define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x) +#define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK +#define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT +#define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x) +#define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK +#define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT +#define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x) +#define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK +#define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT +#define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x) +#define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK +#define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT +#define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x) +#define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK +#define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT +#define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x) +#define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK +#define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT +#define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x) +#define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK +#define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT +#define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x) +#define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK +#define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT +#define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x) +#define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK +#define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT +#define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x) +#define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK +#define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT +#define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x) +#define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK +#define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT +#define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x) +#define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK +#define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT +#define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x) +#define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK +#define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT +#define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x) +#define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK +#define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT +#define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x) +#define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK +#define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT +#define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x) +#define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK +#define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT +#define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x) +#define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK +#define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT +#define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x) +#define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK +#define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT +#define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x) +#define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK +#define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT +#define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x) +#define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK +#define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT +#define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x) +#define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT +#define USBHS_Type USB_Type +#define USBHS_BASE_ADDRS { USB1_BASE, USB2_BASE } +#define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn } + + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBNC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer + * @{ + */ + +/** USBNC - Register Layout Typedef */ +typedef struct { + __IO uint32_t USB_OTGn_CTRL; /**< USB OTGn Control Register, offset: 0x0 */ + uint8_t RESERVED_0[20]; + __IO uint32_t USB_OTGn_PHY_CTRL_0; /**< OTGn UTMI PHY Control 0 Register, offset: 0x18 */ +} USBNC_Type; + +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/*! @name USB_OTGn_CTRL - USB OTGn Control Register */ +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK) +#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U) +#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U) +#define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK) +#define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U) +#define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U) +#define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U) +#define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U) +#define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK) + +/*! @name USB_OTGn_PHY_CTRL_0 - OTGn UTMI PHY Control 0 Register */ +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U) +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U) +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK) + + +/*! + * @} + */ /* end of group USBNC_Register_Masks */ + + +/* USBNC - Peripheral instance base addresses */ +/** Peripheral USBNC1 base address */ +#define USBNC1_BASE (0x2184800u) +/** Peripheral USBNC1 base pointer */ +#define USBNC1 ((USBNC_Type *)USBNC1_BASE) +/** Peripheral USBNC2 base address */ +#define USBNC2_BASE (0x2184804u) +/** Peripheral USBNC2 base pointer */ +#define USBNC2 ((USBNC_Type *)USBNC2_BASE) +/** Array initializer of USBNC peripheral base addresses */ +#define USBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE } +/** Array initializer of USBNC peripheral base pointers */ +#define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 } + +/*! + * @} + */ /* end of group USBNC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ + __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ + __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ + __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ + __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ + __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ + __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */ + __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */ + __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */ + __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */ + __I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */ + uint8_t RESERVED_1[12]; + __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ + __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ + __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ + __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ + __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - USB PHY Power-Down Register */ +#define USBPHY_PWD_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_RSVD0_SHIFT (0U) +#define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK) +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) +#define USBPHY_PWD_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_RSVD1_SHIFT (13U) +#define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK) +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +#define USBPHY_PWD_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_RSVD2_SHIFT (21U) +#define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK) + +/*! @name PWD_SET - USB PHY Power-Down Register */ +#define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_SET_RSVD0_SHIFT (0U) +#define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK) +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) +#define USBPHY_PWD_SET_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_SET_RSVD1_SHIFT (13U) +#define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK) +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +#define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_SET_RSVD2_SHIFT (21U) +#define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK) + +/*! @name PWD_CLR - USB PHY Power-Down Register */ +#define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_CLR_RSVD0_SHIFT (0U) +#define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK) +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) +#define USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_CLR_RSVD1_SHIFT (13U) +#define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK) +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +#define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_CLR_RSVD2_SHIFT (21U) +#define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK) + +/*! @name PWD_TOG - USB PHY Power-Down Register */ +#define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_TOG_RSVD0_SHIFT (0U) +#define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK) +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) +#define USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_TOG_RSVD1_SHIFT (13U) +#define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK) +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +#define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_TOG_RSVD2_SHIFT (21U) +#define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK) + +/*! @name TX - USB PHY Transmitter Control Register */ +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) +#define USBPHY_TX_RSVD0_MASK (0xF0U) +#define USBPHY_TX_RSVD0_SHIFT (4U) +#define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK) +#define USBPHY_TX_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK) +#define USBPHY_TX_RSVD1_MASK (0xF000U) +#define USBPHY_TX_RSVD1_SHIFT (12U) +#define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK) +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) +#define USBPHY_TX_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_RSVD2_SHIFT (20U) +#define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_RSVD5_SHIFT (29U) +#define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK) + +/*! @name TX_SET - USB PHY Transmitter Control Register */ +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) +#define USBPHY_TX_SET_RSVD0_MASK (0xF0U) +#define USBPHY_TX_SET_RSVD0_SHIFT (4U) +#define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK) +#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK) +#define USBPHY_TX_SET_RSVD1_MASK (0xF000U) +#define USBPHY_TX_SET_RSVD1_SHIFT (12U) +#define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK) +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) +#define USBPHY_TX_SET_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_SET_RSVD2_SHIFT (20U) +#define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_SET_RSVD5_SHIFT (29U) +#define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK) + +/*! @name TX_CLR - USB PHY Transmitter Control Register */ +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) +#define USBPHY_TX_CLR_RSVD0_MASK (0xF0U) +#define USBPHY_TX_CLR_RSVD0_SHIFT (4U) +#define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK) +#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK) +#define USBPHY_TX_CLR_RSVD1_MASK (0xF000U) +#define USBPHY_TX_CLR_RSVD1_SHIFT (12U) +#define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK) +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) +#define USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_CLR_RSVD2_SHIFT (20U) +#define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_CLR_RSVD5_SHIFT (29U) +#define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK) + +/*! @name TX_TOG - USB PHY Transmitter Control Register */ +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) +#define USBPHY_TX_TOG_RSVD0_MASK (0xF0U) +#define USBPHY_TX_TOG_RSVD0_SHIFT (4U) +#define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK) +#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK) +#define USBPHY_TX_TOG_RSVD1_MASK (0xF000U) +#define USBPHY_TX_TOG_RSVD1_SHIFT (12U) +#define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK) +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) +#define USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_TOG_RSVD2_SHIFT (20U) +#define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_TOG_RSVD5_SHIFT (29U) +#define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK) + +/*! @name RX - USB PHY Receiver Control Register */ +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) +#define USBPHY_RX_RSVD0_MASK (0x8U) +#define USBPHY_RX_RSVD0_SHIFT (3U) +#define USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK) +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) +#define USBPHY_RX_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_RSVD1_SHIFT (7U) +#define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK) +#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) +#define USBPHY_RX_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_RSVD2_SHIFT (23U) +#define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK) + +/*! @name RX_SET - USB PHY Receiver Control Register */ +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) +#define USBPHY_RX_SET_RSVD0_MASK (0x8U) +#define USBPHY_RX_SET_RSVD0_SHIFT (3U) +#define USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK) +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) +#define USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_SET_RSVD1_SHIFT (7U) +#define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK) +#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) +#define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_SET_RSVD2_SHIFT (23U) +#define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK) + +/*! @name RX_CLR - USB PHY Receiver Control Register */ +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) +#define USBPHY_RX_CLR_RSVD0_MASK (0x8U) +#define USBPHY_RX_CLR_RSVD0_SHIFT (3U) +#define USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK) +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) +#define USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_CLR_RSVD1_SHIFT (7U) +#define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK) +#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) +#define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_CLR_RSVD2_SHIFT (23U) +#define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK) + +/*! @name RX_TOG - USB PHY Receiver Control Register */ +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) +#define USBPHY_RX_TOG_RSVD0_MASK (0x8U) +#define USBPHY_RX_TOG_RSVD0_SHIFT (3U) +#define USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK) +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) +#define USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_TOG_RSVD1_SHIFT (7U) +#define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK) +#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) +#define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_TOG_RSVD2_SHIFT (23U) +#define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK) + +/*! @name CTRL - USB PHY General Control Register */ +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK) +#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) + +/*! @name CTRL_SET - USB PHY General Control Register */ +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_SET_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) + +/*! @name CTRL_CLR - USB PHY General Control Register */ +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_CLR_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) + +/*! @name CTRL_TOG - USB PHY General Control Register */ +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_TOG_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) + +/*! @name STATUS - USB PHY Status Register */ +#define USBPHY_STATUS_RSVD0_MASK (0x7U) +#define USBPHY_STATUS_RSVD0_SHIFT (0U) +#define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) +#define USBPHY_STATUS_RSVD1_MASK (0x30U) +#define USBPHY_STATUS_RSVD1_SHIFT (4U) +#define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) +#define USBPHY_STATUS_RSVD2_MASK (0x80U) +#define USBPHY_STATUS_RSVD2_SHIFT (7U) +#define USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK) +#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) +#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) +#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) +#define USBPHY_STATUS_RSVD3_MASK (0x200U) +#define USBPHY_STATUS_RSVD3_SHIFT (9U) +#define USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK) +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +#define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U) +#define USBPHY_STATUS_RSVD4_SHIFT (11U) +#define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK) + +/*! @name DEBUG - USB PHY Debug Register */ +#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK) +#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK) +#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK) +#define USBPHY_DEBUG_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK) + +/*! @name DEBUG_SET - USB PHY Debug Register */ +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_SET_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_SET_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_SET_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK) +#define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK) + +/*! @name DEBUG_CLR - USB PHY Debug Register */ +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK) +#define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK) + +/*! @name DEBUG_TOG - USB PHY Debug Register */ +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK) +#define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK) + +/*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */ +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK) + +/*! @name DEBUG1 - UTMI Debug Status Register 1 */ +#define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK) +#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK) + +/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ +#define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK) + +/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ +#define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK) + +/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ +#define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK) + +/*! @name VERSION - UTMI RTL Version */ +#define USBPHY_VERSION_STEP_MASK (0xFFFFU) +#define USBPHY_VERSION_STEP_SHIFT (0U) +#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) +#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) +#define USBPHY_VERSION_MINOR_SHIFT (16U) +#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) +#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) +#define USBPHY_VERSION_MAJOR_SHIFT (24U) +#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +/** Peripheral USBPHY1 base address */ +#define USBPHY1_BASE (0x20C9000u) +/** Peripheral USBPHY1 base pointer */ +#define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) +/** Peripheral USBPHY2 base address */ +#define USBPHY2_BASE (0x20CA000u) +/** Peripheral USBPHY2 base pointer */ +#define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) +/** Array initializer of USBPHY peripheral base addresses */ +#define USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE } +/** Array initializer of USBPHY peripheral base pointers */ +#define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 } +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer + * @{ + */ + +/** USB_ANALOG - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x60 */ + __IO uint32_t VBUS_DETECT; /**< USB VBUS Detect Register, array offset: 0x0, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_SET; /**< USB VBUS Detect Register, array offset: 0x4, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_CLR; /**< USB VBUS Detect Register, array offset: 0x8, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_TOG; /**< USB VBUS Detect Register, array offset: 0xC, array step: 0x60 */ + __IO uint32_t CHRG_DETECT; /**< USB Charger Detect Register, array offset: 0x10, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_SET; /**< USB Charger Detect Register, array offset: 0x14, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_CLR; /**< USB Charger Detect Register, array offset: 0x18, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_TOG; /**< USB Charger Detect Register, array offset: 0x1C, array step: 0x60 */ + __I uint32_t VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, array offset: 0x20, array step: 0x60 */ + uint8_t RESERVED_0[12]; + __I uint32_t CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, array offset: 0x30, array step: 0x60 */ + uint8_t RESERVED_1[28]; + __IO uint32_t MISC; /**< USB Misc Register, array offset: 0x50, array step: 0x60 */ + __IO uint32_t MISC_SET; /**< USB Misc Register, array offset: 0x54, array step: 0x60 */ + __IO uint32_t MISC_CLR; /**< USB Misc Register, array offset: 0x58, array step: 0x60 */ + __IO uint32_t MISC_TOG; /**< USB Misc Register, array offset: 0x5C, array step: 0x60 */ + } INSTANCE[2]; + __I uint32_t DIGPROG; /**< Chip Silicon Version, offset: 0xC0 */ +} USB_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks + * @{ + */ + +/*! @name VBUS_DETECT - USB VBUS Detect Register */ +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT */ +#define USB_ANALOG_VBUS_DETECT_COUNT (2U) + +/*! @name VBUS_DETECT_SET - USB VBUS Detect Register */ +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT_SET */ +#define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U) + +/*! @name VBUS_DETECT_CLR - USB VBUS Detect Register */ +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT_CLR */ +#define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U) + +/*! @name VBUS_DETECT_TOG - USB VBUS Detect Register */ +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT_TOG */ +#define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U) + +/*! @name CHRG_DETECT - USB Charger Detect Register */ +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT */ +#define USB_ANALOG_CHRG_DETECT_COUNT (2U) + +/*! @name CHRG_DETECT_SET - USB Charger Detect Register */ +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT_SET */ +#define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U) + +/*! @name CHRG_DETECT_CLR - USB Charger Detect Register */ +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT_CLR */ +#define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U) + +/*! @name CHRG_DETECT_TOG - USB Charger Detect Register */ +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT_TOG */ +#define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U) + +/*! @name VBUS_DETECT_STAT - USB VBUS Detect Status Register */ +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U) +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK) + +/* The count of USB_ANALOG_VBUS_DETECT_STAT */ +#define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U) + +/*! @name CHRG_DETECT_STAT - USB Charger Detect Status Register */ +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U) +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U) +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK) + +/* The count of USB_ANALOG_CHRG_DETECT_STAT */ +#define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U) + +/*! @name MISC - USB Misc Register */ +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK) + +/* The count of USB_ANALOG_MISC */ +#define USB_ANALOG_MISC_COUNT (2U) + +/*! @name MISC_SET - USB Misc Register */ +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK) + +/* The count of USB_ANALOG_MISC_SET */ +#define USB_ANALOG_MISC_SET_COUNT (2U) + +/*! @name MISC_CLR - USB Misc Register */ +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK) + +/* The count of USB_ANALOG_MISC_CLR */ +#define USB_ANALOG_MISC_CLR_COUNT (2U) + +/*! @name MISC_TOG - USB Misc Register */ +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK) + +/* The count of USB_ANALOG_MISC_TOG */ +#define USB_ANALOG_MISC_TOG_COUNT (2U) + +/*! @name DIGPROG - Chip Silicon Version */ +#define USB_ANALOG_DIGPROG_MINOR_MASK (0xFFU) +#define USB_ANALOG_DIGPROG_MINOR_SHIFT (0U) +#define USB_ANALOG_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MINOR_SHIFT)) & USB_ANALOG_DIGPROG_MINOR_MASK) +#define USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK (0xFF00U) +#define USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT (8U) +#define USB_ANALOG_DIGPROG_MAJOR_LOWER(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_LOWER_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_LOWER_MASK) +#define USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U) +#define USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT (16U) +#define USB_ANALOG_DIGPROG_MAJOR_UPPER(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_UPPER_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_UPPER_MASK) + + +/*! + * @} + */ /* end of group USB_ANALOG_Register_Masks */ + + +/* USB_ANALOG - Peripheral instance base addresses */ +/** Peripheral USB_ANALOG base address */ +#define USB_ANALOG_BASE (0x20C81A0u) +/** Peripheral USB_ANALOG base pointer */ +#define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE) +/** Array initializer of USB_ANALOG peripheral base addresses */ +#define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE } +/** Array initializer of USB_ANALOG peripheral base pointers */ +#define USB_ANALOG_BASE_PTRS { USB_ANALOG } + +/*! + * @} + */ /* end of group USB_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USDHC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer + * @{ + */ + +/** USDHC - Register Layout Typedef */ +typedef struct { + __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ + __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ + __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ + __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ + __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ + __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ + __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ + __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ + __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ + __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ + __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ + __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ + __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ + __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ + __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ + __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ + __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ + __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ + __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ + __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */ + __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ + __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ + __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ + uint8_t RESERVED_2[84]; + __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ + __IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */ + __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ + __IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */ +} USDHC_Type; + +/* ---------------------------------------------------------------------------- + -- USDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Register_Masks USDHC Register Masks + * @{ + */ + +/*! @name DS_ADDR - DMA System Address */ +#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) +#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) +#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) + +/*! @name BLK_ATT - Block Attributes */ +#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) +#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) +#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) +#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) +#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) +#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) + +/*! @name CMD_ARG - Command Argument */ +#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) +#define USDHC_CMD_ARG_CMDARG_SHIFT (0U) +#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) + +/*! @name CMD_XFR_TYP - Command Transfer Type */ +#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) +#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) +#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) +#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) +#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) +#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) +#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) +#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) +#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) +#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) +#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) +#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) +#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) +#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) +#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) +#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) +#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) +#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) + +/*! @name CMD_RSP0 - Command Response0 */ +#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) +#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) + +/*! @name CMD_RSP1 - Command Response1 */ +#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) +#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) + +/*! @name CMD_RSP2 - Command Response2 */ +#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) +#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) + +/*! @name CMD_RSP3 - Command Response3 */ +#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) +#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) + +/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) + +/*! @name PRES_STATE - Present State */ +#define USDHC_PRES_STATE_CIHB_MASK (0x1U) +#define USDHC_PRES_STATE_CIHB_SHIFT (0U) +#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) +#define USDHC_PRES_STATE_CDIHB_MASK (0x2U) +#define USDHC_PRES_STATE_CDIHB_SHIFT (1U) +#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) +#define USDHC_PRES_STATE_DLA_MASK (0x4U) +#define USDHC_PRES_STATE_DLA_SHIFT (2U) +#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) +#define USDHC_PRES_STATE_SDSTB_MASK (0x8U) +#define USDHC_PRES_STATE_SDSTB_SHIFT (3U) +#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) +#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) +#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) +#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) +#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) +#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) +#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) +#define USDHC_PRES_STATE_PEROFF_MASK (0x40U) +#define USDHC_PRES_STATE_PEROFF_SHIFT (6U) +#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) +#define USDHC_PRES_STATE_SDOFF_MASK (0x80U) +#define USDHC_PRES_STATE_SDOFF_SHIFT (7U) +#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) +#define USDHC_PRES_STATE_WTA_MASK (0x100U) +#define USDHC_PRES_STATE_WTA_SHIFT (8U) +#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) +#define USDHC_PRES_STATE_RTA_MASK (0x200U) +#define USDHC_PRES_STATE_RTA_SHIFT (9U) +#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) +#define USDHC_PRES_STATE_BWEN_MASK (0x400U) +#define USDHC_PRES_STATE_BWEN_SHIFT (10U) +#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) +#define USDHC_PRES_STATE_BREN_MASK (0x800U) +#define USDHC_PRES_STATE_BREN_SHIFT (11U) +#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) +#define USDHC_PRES_STATE_RTR_MASK (0x1000U) +#define USDHC_PRES_STATE_RTR_SHIFT (12U) +#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) +#define USDHC_PRES_STATE_TSCD_MASK (0x8000U) +#define USDHC_PRES_STATE_TSCD_SHIFT (15U) +#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) +#define USDHC_PRES_STATE_CINST_MASK (0x10000U) +#define USDHC_PRES_STATE_CINST_SHIFT (16U) +#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) +#define USDHC_PRES_STATE_CDPL_MASK (0x40000U) +#define USDHC_PRES_STATE_CDPL_SHIFT (18U) +#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) +#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) +#define USDHC_PRES_STATE_WPSPL_SHIFT (19U) +#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) +#define USDHC_PRES_STATE_CLSL_MASK (0x800000U) +#define USDHC_PRES_STATE_CLSL_SHIFT (23U) +#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) +#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) +#define USDHC_PRES_STATE_DLSL_SHIFT (24U) +#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) + +/*! @name PROT_CTRL - Protocol Control */ +#define USDHC_PROT_CTRL_LCTL_MASK (0x1U) +#define USDHC_PROT_CTRL_LCTL_SHIFT (0U) +#define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) +#define USDHC_PROT_CTRL_DTW_MASK (0x6U) +#define USDHC_PROT_CTRL_DTW_SHIFT (1U) +#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) +#define USDHC_PROT_CTRL_D3CD_MASK (0x8U) +#define USDHC_PROT_CTRL_D3CD_SHIFT (3U) +#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) +#define USDHC_PROT_CTRL_EMODE_MASK (0x30U) +#define USDHC_PROT_CTRL_EMODE_SHIFT (4U) +#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) +#define USDHC_PROT_CTRL_CDTL_MASK (0x40U) +#define USDHC_PROT_CTRL_CDTL_SHIFT (6U) +#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) +#define USDHC_PROT_CTRL_CDSS_MASK (0x80U) +#define USDHC_PROT_CTRL_CDSS_SHIFT (7U) +#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) +#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) +#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) +#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) +#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) +#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) +#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) +#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) +#define USDHC_PROT_CTRL_CREQ_SHIFT (17U) +#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) +#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) +#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) +#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) +#define USDHC_PROT_CTRL_IABG_MASK (0x80000U) +#define USDHC_PROT_CTRL_IABG_SHIFT (19U) +#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) +#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) +#define USDHC_PROT_CTRL_WECINT_SHIFT (24U) +#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) +#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) +#define USDHC_PROT_CTRL_WECINS_SHIFT (25U) +#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) +#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) +#define USDHC_PROT_CTRL_WECRM_SHIFT (26U) +#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) +#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U) +#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U) +#define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) + +/*! @name SYS_CTRL - System Control */ +#define USDHC_SYS_CTRL_DVS_MASK (0xF0U) +#define USDHC_SYS_CTRL_DVS_SHIFT (4U) +#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) +#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) +#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) +#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) +#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) +#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) +#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) +#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) +#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) +#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) +#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) +#define USDHC_SYS_CTRL_RSTA_SHIFT (24U) +#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) +#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) +#define USDHC_SYS_CTRL_RSTC_SHIFT (25U) +#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) +#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) +#define USDHC_SYS_CTRL_RSTD_SHIFT (26U) +#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) +#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) +#define USDHC_SYS_CTRL_INITA_SHIFT (27U) +#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) +#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) +#define USDHC_SYS_CTRL_RSTT_SHIFT (28U) +#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) + +/*! @name INT_STATUS - Interrupt Status */ +#define USDHC_INT_STATUS_CC_MASK (0x1U) +#define USDHC_INT_STATUS_CC_SHIFT (0U) +#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) +#define USDHC_INT_STATUS_TC_MASK (0x2U) +#define USDHC_INT_STATUS_TC_SHIFT (1U) +#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) +#define USDHC_INT_STATUS_BGE_MASK (0x4U) +#define USDHC_INT_STATUS_BGE_SHIFT (2U) +#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) +#define USDHC_INT_STATUS_DINT_MASK (0x8U) +#define USDHC_INT_STATUS_DINT_SHIFT (3U) +#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) +#define USDHC_INT_STATUS_BWR_MASK (0x10U) +#define USDHC_INT_STATUS_BWR_SHIFT (4U) +#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) +#define USDHC_INT_STATUS_BRR_MASK (0x20U) +#define USDHC_INT_STATUS_BRR_SHIFT (5U) +#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) +#define USDHC_INT_STATUS_CINS_MASK (0x40U) +#define USDHC_INT_STATUS_CINS_SHIFT (6U) +#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) +#define USDHC_INT_STATUS_CRM_MASK (0x80U) +#define USDHC_INT_STATUS_CRM_SHIFT (7U) +#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) +#define USDHC_INT_STATUS_CINT_MASK (0x100U) +#define USDHC_INT_STATUS_CINT_SHIFT (8U) +#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) +#define USDHC_INT_STATUS_RTE_MASK (0x1000U) +#define USDHC_INT_STATUS_RTE_SHIFT (12U) +#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) +#define USDHC_INT_STATUS_TP_MASK (0x4000U) +#define USDHC_INT_STATUS_TP_SHIFT (14U) +#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) +#define USDHC_INT_STATUS_CTOE_MASK (0x10000U) +#define USDHC_INT_STATUS_CTOE_SHIFT (16U) +#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) +#define USDHC_INT_STATUS_CCE_MASK (0x20000U) +#define USDHC_INT_STATUS_CCE_SHIFT (17U) +#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) +#define USDHC_INT_STATUS_CEBE_MASK (0x40000U) +#define USDHC_INT_STATUS_CEBE_SHIFT (18U) +#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) +#define USDHC_INT_STATUS_CIE_MASK (0x80000U) +#define USDHC_INT_STATUS_CIE_SHIFT (19U) +#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) +#define USDHC_INT_STATUS_DTOE_MASK (0x100000U) +#define USDHC_INT_STATUS_DTOE_SHIFT (20U) +#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) +#define USDHC_INT_STATUS_DCE_MASK (0x200000U) +#define USDHC_INT_STATUS_DCE_SHIFT (21U) +#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) +#define USDHC_INT_STATUS_DEBE_MASK (0x400000U) +#define USDHC_INT_STATUS_DEBE_SHIFT (22U) +#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) +#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) +#define USDHC_INT_STATUS_AC12E_SHIFT (24U) +#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) +#define USDHC_INT_STATUS_TNE_MASK (0x4000000U) +#define USDHC_INT_STATUS_TNE_SHIFT (26U) +#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) +#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) +#define USDHC_INT_STATUS_DMAE_SHIFT (28U) +#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) + +/*! @name INT_STATUS_EN - Interrupt Status Enable */ +#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) +#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) +#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) +#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) +#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) +#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) +#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) +#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) +#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) +#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) +#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) +#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) +#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) +#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) +#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) +#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) +#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) +#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) +#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) +#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) +#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) +#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) +#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) +#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) +#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) +#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) +#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) +#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) +#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) +#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) +#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U) +#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U) +#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) +#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) +#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) +#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) +#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) +#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) +#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) +#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) +#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) +#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) +#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) +#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) +#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) +#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) +#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) +#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) +#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) +#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) +#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) +#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) +#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) +#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) +#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) +#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) +#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) +#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) +#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) +#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) +#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) +#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) +#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) + +/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ +#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) +#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) +#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) +#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) +#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) +#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) +#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) +#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) +#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) +#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) +#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) +#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) +#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) +#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) +#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) +#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) +#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) +#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) +#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) +#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) +#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) +#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U) +#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U) +#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) +#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) +#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) +#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) +#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) +#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) +#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) +#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) +#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) +#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) +#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) +#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) +#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) +#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) +#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) + +/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) + +/*! @name HOST_CTRL_CAP - Host Controller Capabilities */ +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) +#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) +#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) +#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) +#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) +#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) +#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) +#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) +#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) +#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) +#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) +#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) +#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) +#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) +#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) +#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) +#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) +#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) +#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) +#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) +#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) +#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) +#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) +#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) +#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) + +/*! @name WTMK_LVL - Watermark Level */ +#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) +#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) +#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) +#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U) +#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U) +#define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK) +#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) +#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) +#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) +#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) +#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) +#define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) + +/*! @name MIX_CTRL - Mixer Control */ +#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) +#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) +#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) +#define USDHC_MIX_CTRL_BCEN_MASK (0x2U) +#define USDHC_MIX_CTRL_BCEN_SHIFT (1U) +#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) +#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) +#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) +#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) +#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) +#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) +#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) +#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) +#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) +#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) +#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) +#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) +#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) +#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) +#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) +#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) +#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) +#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) +#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) +#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) +#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) +#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) +#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) +#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) +#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) +#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) + +/*! @name FORCE_EVENT - Force Event */ +#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) +#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) +#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) +#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) +#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) +#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) +#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) +#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) +#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) +#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) +#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) +#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) +#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) +#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) +#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) +#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) +#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) +#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) +#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) +#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) +#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) +#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) +#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) +#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) +#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) +#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) +#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) +#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) +#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) +#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) +#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) +#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) +#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) +#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) +#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) +#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) +#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) +#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) +#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) +#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) +#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) + +/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */ +#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) +#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) +#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) +#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) +#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) +#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) +#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) + +/*! @name ADMA_SYS_ADDR - ADMA System Address */ +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) + +/*! @name DLL_CTRL - DLL (Delay Line) Control */ +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) + +/*! @name DLL_STATUS - DLL Status */ +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) + +/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) + +/*! @name VEND_SPEC - Vendor Specific Register */ +#define USDHC_VEND_SPEC_EXT_DMA_EN_MASK (0x1U) +#define USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT (0U) +#define USDHC_VEND_SPEC_EXT_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT)) & USDHC_VEND_SPEC_EXT_DMA_EN_MASK) +#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) +#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) +#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) +#define USDHC_VEND_SPEC_DAT3_CD_POL_MASK (0x10U) +#define USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT (4U) +#define USDHC_VEND_SPEC_DAT3_CD_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT)) & USDHC_VEND_SPEC_DAT3_CD_POL_MASK) +#define USDHC_VEND_SPEC_CD_POL_MASK (0x20U) +#define USDHC_VEND_SPEC_CD_POL_SHIFT (5U) +#define USDHC_VEND_SPEC_CD_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CD_POL_SHIFT)) & USDHC_VEND_SPEC_CD_POL_MASK) +#define USDHC_VEND_SPEC_WP_POL_MASK (0x40U) +#define USDHC_VEND_SPEC_WP_POL_SHIFT (6U) +#define USDHC_VEND_SPEC_WP_POL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_WP_POL_SHIFT)) & USDHC_VEND_SPEC_WP_POL_MASK) +#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK (0x80U) +#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT (7U) +#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT)) & USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) +#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK (0x800U) +#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT (11U) +#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK) +#define USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK (0x1000U) +#define USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT (12U) +#define USDHC_VEND_SPEC_HCLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK) +#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK (0x2000U) +#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT (13U) +#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK) +#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK (0x4000U) +#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT (14U) +#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) +#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) +#define USDHC_VEND_SPEC_INT_ST_VAL_MASK (0xFF0000U) +#define USDHC_VEND_SPEC_INT_ST_VAL_SHIFT (16U) +#define USDHC_VEND_SPEC_INT_ST_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_INT_ST_VAL_SHIFT)) & USDHC_VEND_SPEC_INT_ST_VAL_MASK) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) +#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) + +/*! @name MMC_BOOT - MMC Boot Register */ +#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) +#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) +#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) +#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) +#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) +#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) +#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) +#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) +#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) +#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) +#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) +#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) + +/*! @name VEND_SPEC2 - Vendor Specific 2 Register */ +#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK (0x1U) +#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT (0U) +#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK) +#define USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK (0x2U) +#define USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT (1U) +#define USDHC_VEND_SPEC2_SDR104_OE_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK) +#define USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK (0x4U) +#define USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT (2U) +#define USDHC_VEND_SPEC2_SDR104_NSD_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) +#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK (0x80U) +#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT (7U) +#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x800000U) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (23U) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) + +/*! @name TUNING_CTRL - Tuning Control Register */ +#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU) +#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) +#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) +#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) +#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) +#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) + + +/*! + * @} + */ /* end of group USDHC_Register_Masks */ + + +/* USDHC - Peripheral instance base addresses */ +/** Peripheral USDHC1 base address */ +#define USDHC1_BASE (0x2190000u) +/** Peripheral USDHC1 base pointer */ +#define USDHC1 ((USDHC_Type *)USDHC1_BASE) +/** Peripheral USDHC2 base address */ +#define USDHC2_BASE (0x2194000u) +/** Peripheral USDHC2 base pointer */ +#define USDHC2 ((USDHC_Type *)USDHC2_BASE) +/** Array initializer of USDHC peripheral base addresses */ +#define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE } +/** Array initializer of USDHC peripheral base pointers */ +#define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 } +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn } + +/*! + * @} + */ /* end of group USDHC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */ + __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */ + __I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */ + __IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */ + __IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */ +} WDOG_Type; + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/*! @name WCR - Watchdog Control Register */ +#define WDOG_WCR_WDZST_MASK (0x1U) +#define WDOG_WCR_WDZST_SHIFT (0U) +#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) +#define WDOG_WCR_WDBG_MASK (0x2U) +#define WDOG_WCR_WDBG_SHIFT (1U) +#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) +#define WDOG_WCR_WDE_MASK (0x4U) +#define WDOG_WCR_WDE_SHIFT (2U) +#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) +#define WDOG_WCR_WDT_MASK (0x8U) +#define WDOG_WCR_WDT_SHIFT (3U) +#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) +#define WDOG_WCR_SRS_MASK (0x10U) +#define WDOG_WCR_SRS_SHIFT (4U) +#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) +#define WDOG_WCR_WDA_MASK (0x20U) +#define WDOG_WCR_WDA_SHIFT (5U) +#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) +#define WDOG_WCR_SRE_MASK (0x40U) +#define WDOG_WCR_SRE_SHIFT (6U) +#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) +#define WDOG_WCR_WDW_MASK (0x80U) +#define WDOG_WCR_WDW_SHIFT (7U) +#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) +#define WDOG_WCR_WT_MASK (0xFF00U) +#define WDOG_WCR_WT_SHIFT (8U) +#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) + +/*! @name WSR - Watchdog Service Register */ +#define WDOG_WSR_WSR_MASK (0xFFFFU) +#define WDOG_WSR_WSR_SHIFT (0U) +#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) + +/*! @name WRSR - Watchdog Reset Status Register */ +#define WDOG_WRSR_SFTW_MASK (0x1U) +#define WDOG_WRSR_SFTW_SHIFT (0U) +#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) +#define WDOG_WRSR_TOUT_MASK (0x2U) +#define WDOG_WRSR_TOUT_SHIFT (1U) +#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) +#define WDOG_WRSR_POR_MASK (0x10U) +#define WDOG_WRSR_POR_SHIFT (4U) +#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) + +/*! @name WICR - Watchdog Interrupt Control Register */ +#define WDOG_WICR_WICT_MASK (0xFFU) +#define WDOG_WICR_WICT_SHIFT (0U) +#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) +#define WDOG_WICR_WTIS_MASK (0x4000U) +#define WDOG_WICR_WTIS_SHIFT (14U) +#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) +#define WDOG_WICR_WIE_MASK (0x8000U) +#define WDOG_WICR_WIE_SHIFT (15U) +#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) + +/*! @name WMCR - Watchdog Miscellaneous Control Register */ +#define WDOG_WMCR_PDE_MASK (0x1U) +#define WDOG_WMCR_PDE_SHIFT (0U) +#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) + + +/*! + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG1 base address */ +#define WDOG1_BASE (0x20BC000u) +/** Peripheral WDOG1 base pointer */ +#define WDOG1 ((WDOG_Type *)WDOG1_BASE) +/** Peripheral WDOG2 base address */ +#define WDOG2_BASE (0x20C0000u) +/** Peripheral WDOG2 base pointer */ +#define WDOG2 ((WDOG_Type *)WDOG2_BASE) +/** Peripheral WDOG3 base address */ +#define WDOG3_BASE (0x21E4000u) +/** Peripheral WDOG3 base pointer */ +#define WDOG3 ((WDOG_Type *)WDOG3_BASE) +/** Array initializer of WDOG peripheral base addresses */ +#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE, WDOG3_BASE } +/** Array initializer of WDOG peripheral base pointers */ +#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2, WDOG3 } +/** Interrupt vectors for the WDOG peripheral type */ +#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn, WDOG3_IRQn } + +/*! + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Peripheral_Access_Layer XTALOSC24M Peripheral Access Layer + * @{ + */ + +/** XTALOSC24M - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[336]; + __IO uint32_t OSC_CONFIG0; /**< XTAL OSC Configuration 0 Register, offset: 0x150 */ + __IO uint32_t OSC_CONFIG0_SET; /**< XTAL OSC Configuration 0 Register, offset: 0x154 */ + __IO uint32_t OSC_CONFIG0_CLR; /**< XTAL OSC Configuration 0 Register, offset: 0x158 */ + __IO uint32_t OSC_CONFIG0_TOG; /**< XTAL OSC Configuration 0 Register, offset: 0x15C */ + __IO uint32_t OSC_CONFIG1; /**< XTAL OSC Configuration 1 Register, offset: 0x160 */ + __IO uint32_t OSC_CONFIG1_SET; /**< XTAL OSC Configuration 1 Register, offset: 0x164 */ + __IO uint32_t OSC_CONFIG1_CLR; /**< XTAL OSC Configuration 1 Register, offset: 0x168 */ + __IO uint32_t OSC_CONFIG1_TOG; /**< XTAL OSC Configuration 1 Register, offset: 0x16C */ + __IO uint32_t OSC_CONFIG2; /**< XTAL OSC Configuration 2 Register, offset: 0x170 */ + __IO uint32_t OSC_CONFIG2_SET; /**< XTAL OSC Configuration 2 Register, offset: 0x174 */ + __IO uint32_t OSC_CONFIG2_CLR; /**< XTAL OSC Configuration 2 Register, offset: 0x178 */ + __IO uint32_t OSC_CONFIG2_TOG; /**< XTAL OSC Configuration 2 Register, offset: 0x17C */ +} XTALOSC24M_Type; + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks + * @{ + */ + +/*! @name OSC_CONFIG0 - XTAL OSC Configuration 0 Register */ +#define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK) + +/*! @name OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register */ +#define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK) + +/*! @name OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register */ +#define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK) + +/*! @name OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register */ +#define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK) + +/*! @name OSC_CONFIG1 - XTAL OSC Configuration 1 Register */ +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK) + +/*! @name OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register */ +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK) + +/*! @name OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register */ +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK) + +/*! @name OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register */ +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK) + +/*! @name OSC_CONFIG2 - XTAL OSC Configuration 2 Register */ +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK) + +/*! @name OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register */ +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK) + +/*! @name OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register */ +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK) + +/*! @name OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register */ +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK) + + +/*! + * @} + */ /* end of group XTALOSC24M_Register_Masks */ + + +/* XTALOSC24M - Peripheral instance base addresses */ +/** Peripheral XTALOSC24M base address */ +#define XTALOSC24M_BASE (0x20C8150u) +/** Peripheral XTALOSC24M base pointer */ +#define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE) +/** Array initializer of XTALOSC24M peripheral base addresses */ +#define XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE } +/** Array initializer of XTALOSC24M peripheral base pointers */ +#define XTALOSC24M_BASE_PTRS { XTALOSC24M } + +/*! + * @} + */ /* end of group XTALOSC24M_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _MCIMX6Y2_H_ */ + diff --git a/board/ALPHA_I.MX_emmc_256ddr/imx6ul/bsp.h b/board/ALPHA_I.MX_emmc_256ddr/imx6ul/bsp.h new file mode 100644 index 00000000..72f59621 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/imx6ul/bsp.h @@ -0,0 +1,20 @@ +#ifndef __IMX6UL_H +#define __IMX6UL_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : bsp.h +作者 : 左忠凯 +版本 : V1.0 +描述 : 包含一些常用的头文件。 +其他 : 无 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/3 左忠凯创建 +***************************************************************/ +#include "cc.h" +#include "MCIMX6Y2.h" +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "core_ca7.h" + +#endif + diff --git a/board/ALPHA_I.MX_emmc_256ddr/imx6ul/cc.h b/board/ALPHA_I.MX_emmc_256ddr/imx6ul/cc.h new file mode 100644 index 00000000..14199bc0 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/imx6ul/cc.h @@ -0,0 +1,40 @@ +#ifndef __CC_H +#define __CC_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : cc.h +作者 : 左忠凯 +版本 : V1.0 +描述 : 有关变量类型的定义，NXP官方SDK的一些移植文件会用到。 +其他 : 无 +日志 : 初版V1.0 2019/1/3 左忠凯创建 +***************************************************************/ + +/* + * 自定义一些数据类型供库文件使用 + */ +#define __I volatile +#define __O volatile +#define __IO volatile + +#define ON 1 +#define OFF 0 + +typedef signed char int8_t; +typedef signed short int int16_t; +typedef signed int int32_t; +typedef unsigned char uint8_t; +typedef unsigned short int uint16_t; +typedef unsigned int uint32_t; +typedef unsigned long long uint64_t; +typedef signed char s8; +typedef signed short int s16; +typedef signed int s32; +typedef signed long long int s64; +typedef unsigned char u8; +typedef unsigned short int u16; +typedef unsigned int u32; +typedef unsigned long long int u64; + + +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/imx6ul/core_ca7.h b/board/ALPHA_I.MX_emmc_256ddr/imx6ul/core_ca7.h new file mode 100644 index 00000000..403b82d4 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/imx6ul/core_ca7.h @@ -0,0 +1,733 @@ +#ifndef __CORTEX_CA7_H +#define __CORTEX_CA7_H +/*************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : core_ca7.h +作者 : 左忠凯 +版本 : V1.0 +描述 : Cortex-A7内核通用文件。 +其他 : 本文件主要实现了对GIC操作函数 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯创建 +***************************************************************/ +#include +#include + + +#define FORCEDINLINE __attribute__((always_inline)) +#define __ASM __asm /* GNU C语言内嵌汇编关键字 */ +#define __INLINE inline /* GNU内联关键字 */ +#define __STATIC_INLINE static inline + + +#define __IM volatile const /* 只读 */ +#define __OM volatile /* 只写 */ +#define __IOM volatile /* 读写 */ +#define __STRINGIFY(x) #x + +/* C语言实现MCR指令 */ +#define __MCR(coproc, opcode_1, src, CRn, CRm, opcode_2) \ + __ASM volatile ("MCR " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \ + "%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " \ + __STRINGIFY(opcode_2) \ + : : "r" (src) ) + +/* C语言实现MRC指令 */ +#define __MRC(coproc, opcode_1, CRn, CRm, opcode_2) \ + ({ \ + uint32_t __dst; \ + __ASM volatile ("MRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \ + "%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " \ + __STRINGIFY(opcode_2) \ + : "=r" (__dst) ); \ + __dst; \ + }) + +/* 其他一些C语言内嵌汇编 */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_APSR(uint32_t apsr) +{ + __ASM volatile ("MSR apsr, %0" : : "r" (apsr) : "cc"); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPSR(uint32_t cpsr) +{ + __ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc"); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void) +{ + uint32_t result; + + __ASM volatile ("VMRS %0, fpexc" : "=r" (result) ); + return result; +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) +{ + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc)); +} + + +/******************************************************************************* + * 一些内核寄存器定义和抽象 + 定义如下几个内核寄存器: + - CPSR + - CP15 + ******************************************************************************/ + +/* CPSR寄存器 + * 参考资料：ARM Cortex-A(armV7)编程手册V4.0.pdf P46 + */ +typedef union +{ + struct + { + uint32_t M:5; /*!< bit: 0.. 4 Mode field */ + uint32_t T:1; /*!< bit: 5 Thumb execution state bit */ + uint32_t F:1; /*!< bit: 6 FIQ mask bit */ + uint32_t I:1; /*!< bit: 7 IRQ mask bit */ + uint32_t A:1; /*!< bit: 8 Asynchronous abort mask bit */ + uint32_t E:1; /*!< bit: 9 Endianness execution state bit */ + uint32_t IT1:6; /*!< bit: 10..15 If-Then execution state bits 2-7 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved0:4; /*!< bit: 20..23 Reserved */ + uint32_t J:1; /*!< bit: 24 Jazelle bit */ + uint32_t IT0:2; /*!< bit: 25..26 If-Then execution state bits 0-1 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CPSR_Type; + + +/* CP15的SCTLR寄存器 + * 参考资料：Cortex-A7 Technical ReferenceManua.pdf P105 + */ +typedef union +{ + struct + { + uint32_t M:1; /*!< bit: 0 MMU enable */ + uint32_t A:1; /*!< bit: 1 Alignment check enable */ + uint32_t C:1; /*!< bit: 2 Cache enable */ + uint32_t _reserved0:2; /*!< bit: 3.. 4 Reserved */ + uint32_t CP15BEN:1; /*!< bit: 5 CP15 barrier enable */ + uint32_t _reserved1:1; /*!< bit: 6 Reserved */ + uint32_t B:1; /*!< bit: 7 Endianness model */ + uint32_t _reserved2:2; /*!< bit: 8.. 9 Reserved */ + uint32_t SW:1; /*!< bit: 10 SWP and SWPB enable */ + uint32_t Z:1; /*!< bit: 11 Branch prediction enable */ + uint32_t I:1; /*!< bit: 12 Instruction cache enable */ + uint32_t V:1; /*!< bit: 13 Vectors bit */ + uint32_t RR:1; /*!< bit: 14 Round Robin select */ + uint32_t _reserved3:2; /*!< bit:15..16 Reserved */ + uint32_t HA:1; /*!< bit: 17 Hardware Access flag enable */ + uint32_t _reserved4:1; /*!< bit: 18 Reserved */ + uint32_t WXN:1; /*!< bit: 19 Write permission implies XN */ + uint32_t UWXN:1; /*!< bit: 20 Unprivileged write permission implies PL1 XN */ + uint32_t FI:1; /*!< bit: 21 Fast interrupts configuration enable */ + uint32_t U:1; /*!< bit: 22 Alignment model */ + uint32_t _reserved5:1; /*!< bit: 23 Reserved */ + uint32_t VE:1; /*!< bit: 24 Interrupt Vectors Enable */ + uint32_t EE:1; /*!< bit: 25 Exception Endianness */ + uint32_t _reserved6:1; /*!< bit: 26 Reserved */ + uint32_t NMFI:1; /*!< bit: 27 Non-maskable FIQ (NMFI) support */ + uint32_t TRE:1; /*!< bit: 28 TEX remap enable. */ + uint32_t AFE:1; /*!< bit: 29 Access flag enable */ + uint32_t TE:1; /*!< bit: 30 Thumb Exception enable */ + uint32_t _reserved7:1; /*!< bit: 31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} SCTLR_Type; + +/* CP15 寄存器SCTLR各个位定义 */ +#define SCTLR_TE_Pos 30U /*!< SCTLR: TE Position */ +#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< SCTLR: TE Mask */ + +#define SCTLR_AFE_Pos 29U /*!< SCTLR: AFE Position */ +#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< SCTLR: AFE Mask */ + +#define SCTLR_TRE_Pos 28U /*!< SCTLR: TRE Position */ +#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< SCTLR: TRE Mask */ + +#define SCTLR_NMFI_Pos 27U /*!< SCTLR: NMFI Position */ +#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< SCTLR: NMFI Mask */ + +#define SCTLR_EE_Pos 25U /*!< SCTLR: EE Position */ +#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< SCTLR: EE Mask */ + +#define SCTLR_VE_Pos 24U /*!< SCTLR: VE Position */ +#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< SCTLR: VE Mask */ + +#define SCTLR_U_Pos 22U /*!< SCTLR: U Position */ +#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /*!< SCTLR: U Mask */ + +#define SCTLR_FI_Pos 21U /*!< SCTLR: FI Position */ +#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< SCTLR: FI Mask */ + +#define SCTLR_UWXN_Pos 20U /*!< SCTLR: UWXN Position */ +#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< SCTLR: UWXN Mask */ + +#define SCTLR_WXN_Pos 19U /*!< SCTLR: WXN Position */ +#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< SCTLR: WXN Mask */ + +#define SCTLR_HA_Pos 17U /*!< SCTLR: HA Position */ +#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /*!< SCTLR: HA Mask */ + +#define SCTLR_RR_Pos 14U /*!< SCTLR: RR Position */ +#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< SCTLR: RR Mask */ + +#define SCTLR_V_Pos 13U /*!< SCTLR: V Position */ +#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< SCTLR: V Mask */ + +#define SCTLR_I_Pos 12U /*!< SCTLR: I Position */ +#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< SCTLR: I Mask */ + +#define SCTLR_Z_Pos 11U /*!< SCTLR: Z Position */ +#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< SCTLR: Z Mask */ + +#define SCTLR_SW_Pos 10U /*!< SCTLR: SW Position */ +#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< SCTLR: SW Mask */ + +#define SCTLR_B_Pos 7U /*!< SCTLR: B Position */ +#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /*!< SCTLR: B Mask */ + +#define SCTLR_CP15BEN_Pos 5U /*!< SCTLR: CP15BEN Position */ +#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< SCTLR: CP15BEN Mask */ + +#define SCTLR_C_Pos 2U /*!< SCTLR: C Position */ +#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< SCTLR: C Mask */ + +#define SCTLR_A_Pos 1U /*!< SCTLR: A Position */ +#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< SCTLR: A Mask */ + +#define SCTLR_M_Pos 0U /*!< SCTLR: M Position */ +#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< SCTLR: M Mask */ + +/* CP15的ACTLR寄存器 + * 参考资料:Cortex-A7 Technical ReferenceManua.pdf P113 + */ +typedef union +{ + struct + { + uint32_t _reserved0:6; /*!< bit: 0.. 5 Reserved */ + uint32_t SMP:1; /*!< bit: 6 Enables coherent requests to the processor */ + uint32_t _reserved1:3; /*!< bit: 7.. 9 Reserved */ + uint32_t DODMBS:1; /*!< bit: 10 Disable optimized data memory barrier behavior */ + uint32_t L2RADIS:1; /*!< bit: 11 L2 Data Cache read-allocate mode disable */ + uint32_t L1RADIS:1; /*!< bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< bit:13..14 L1 Data prefetch control */ + uint32_t DDVM:1; /*!< bit: 15 Disable Distributed Virtual Memory (DVM) transactions */ + uint32_t _reserved3:12; /*!< bit:16..27 Reserved */ + uint32_t DDI:1; /*!< bit: 28 Disable dual issue */ + uint32_t _reserved7:3; /*!< bit:29..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} ACTLR_Type; + +#define ACTLR_DDI_Pos 28U /*!< ACTLR: DDI Position */ +#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< ACTLR: DDI Mask */ + +#define ACTLR_DDVM_Pos 15U /*!< ACTLR: DDVM Position */ +#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< ACTLR: DDVM Mask */ + +#define ACTLR_L1PCTL_Pos 13U /*!< ACTLR: L1PCTL Position */ +#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< ACTLR: L1PCTL Mask */ + +#define ACTLR_L1RADIS_Pos 12U /*!< ACTLR: L1RADIS Position */ +#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< ACTLR: L1RADIS Mask */ + +#define ACTLR_L2RADIS_Pos 11U /*!< ACTLR: L2RADIS Position */ +#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< ACTLR: L2RADIS Mask */ + +#define ACTLR_DODMBS_Pos 10U /*!< ACTLR: DODMBS Position */ +#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< ACTLR: DODMBS Mask */ + +#define ACTLR_SMP_Pos 6U /*!< ACTLR: SMP Position */ +#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< ACTLR: SMP Mask */ + + +/* CP15的CPACR寄存器 + * 参考资料：Cortex-A7 Technical ReferenceManua.pdf P115 + */ +typedef union +{ + struct + { + uint32_t _reserved0:20; /*!< bit: 0..19 Reserved */ + uint32_t cp10:2; /*!< bit:20..21 Access rights for coprocessor 10 */ + uint32_t cp11:2; /*!< bit:22..23 Access rights for coprocessor 11 */ + uint32_t _reserved1:6; /*!< bit:24..29 Reserved */ + uint32_t D32DIS:1; /*!< bit: 30 Disable use of registers D16-D31 of the VFP register file */ + uint32_t ASEDIS:1; /*!< bit: 31 Disable Advanced SIMD Functionality */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CPACR_Type; + +#define CPACR_ASEDIS_Pos 31U /*!< CPACR: ASEDIS Position */ +#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< CPACR: ASEDIS Mask */ + +#define CPACR_D32DIS_Pos 30U /*!< CPACR: D32DIS Position */ +#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< CPACR: D32DIS Mask */ + +#define CPACR_cp11_Pos 22U /*!< CPACR: cp11 Position */ +#define CPACR_cp11_Msk (3UL << CPACR_cp11_Pos) /*!< CPACR: cp11 Mask */ + +#define CPACR_cp10_Pos 20U /*!< CPACR: cp10 Position */ +#define CPACR_cp10_Msk (3UL << CPACR_cp10_Pos) /*!< CPACR: cp10 Mask */ + + +/* CP15的DFSR寄存器 + * 参考资料：Cortex-A7 Technical ReferenceManua.pdf P128 + */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< bit: 0.. 3 Fault Status bits bit 0-3 */ + uint32_t Domain:4; /*!< bit: 4.. 7 Fault on which domain */ + uint32_t _reserved0:2; /*!< bit: 8.. 9 Reserved */ + uint32_t FS1:1; /*!< bit: 10 Fault Status bits bit 4 */ + uint32_t WnR:1; /*!< bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< bit: 12 External abort type */ + uint32_t CM:1; /*!< bit: 13 Cache maintenance fault */ + uint32_t _reserved1:18; /*!< bit:14..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} DFSR_Type; + +#define DFSR_CM_Pos 13U /*!< DFSR: CM Position */ +#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< DFSR: CM Mask */ + +#define DFSR_Ext_Pos 12U /*!< DFSR: Ext Position */ +#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< DFSR: Ext Mask */ + +#define DFSR_WnR_Pos 11U /*!< DFSR: WnR Position */ +#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< DFSR: WnR Mask */ + +#define DFSR_FS1_Pos 10U /*!< DFSR: FS1 Position */ +#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< DFSR: FS1 Mask */ + +#define DFSR_Domain_Pos 4U /*!< DFSR: Domain Position */ +#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< DFSR: Domain Mask */ + +#define DFSR_FS0_Pos 0U /*!< DFSR: FS0 Position */ +#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< DFSR: FS0 Mask */ + + +/* CP15的IFSR寄存器 + * 参考资料：Cortex-A7 Technical ReferenceManua.pdf P131 + */ +typedef union +{ + struct + { + uint32_t FS0:4; /*!< bit: 0.. 3 Fault Status bits bit 0-3 */ + uint32_t _reserved0:6; /*!< bit: 4.. 9 Reserved */ + uint32_t FS1:1; /*!< bit: 10 Fault Status bits bit 4 */ + uint32_t _reserved1:1; /*!< bit: 11 Reserved */ + uint32_t ExT:1; /*!< bit: 12 External abort type */ + uint32_t _reserved2:19; /*!< bit:13..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IFSR_Type; + +#define IFSR_ExT_Pos 12U /*!< IFSR: ExT Position */ +#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< IFSR: ExT Mask */ + +#define IFSR_FS1_Pos 10U /*!< IFSR: FS1 Position */ +#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< IFSR: FS1 Mask */ + +#define IFSR_FS0_Pos 0U /*!< IFSR: FS0 Position */ +#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< IFSR: FS0 Mask */ + + +/* CP15的ISR寄存器 + * 参考资料：ARM ArchitectureReference Manual ARMv7-A and ARMv7-R edition.pdf P1640 + */ +typedef union +{ + struct + { + uint32_t _reserved0:6; /*!< bit: 0.. 5 Reserved */ + uint32_t F:1; /*!< bit: 6 FIQ pending bit */ + uint32_t I:1; /*!< bit: 7 IRQ pending bit */ + uint32_t A:1; /*!< bit: 8 External abort pending bit */ + uint32_t _reserved1:23; /*!< bit:14..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} ISR_Type; + +#define ISR_A_Pos 13U /*!< ISR: A Position */ +#define ISR_A_Msk (1UL << ISR_A_Pos) /*!< ISR: A Mask */ + +#define ISR_I_Pos 12U /*!< ISR: I Position */ +#define ISR_I_Msk (1UL << ISR_I_Pos) /*!< ISR: I Mask */ + +#define ISR_F_Pos 11U /*!< ISR: F Position */ +#define ISR_F_Msk (1UL << ISR_F_Pos) /*!< ISR: F Mask */ + + +/* Mask and shift a bit field value for use in a register bit range. */ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/* Mask and shift a register value to extract a bit filed value. */ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + + +/******************************************************************************* + * CP15 访问函数 + ******************************************************************************/ + +FORCEDINLINE __STATIC_INLINE uint32_t __get_SCTLR(void) +{ + return __MRC(15, 0, 1, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) +{ + __MCR(15, 0, sctlr, 1, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_ACTLR(void) +{ + return __MRC(15, 0, 1, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE void __set_ACTLR(uint32_t actlr) +{ + __MCR(15, 0, actlr, 1, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_CPACR(void) +{ + return __MRC(15, 0, 1, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE void __set_CPACR(uint32_t cpacr) +{ + __MCR(15, 0, cpacr, 1, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_TTBR0(void) +{ + return __MRC(15, 0, 2, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) +{ + __MCR(15, 0, ttbr0, 2, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_TTBR1(void) +{ + return __MRC(15, 0, 2, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE void __set_TTBR1(uint32_t ttbr1) +{ + __MCR(15, 0, ttbr1, 2, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_TTBCR(void) +{ + return __MRC(15, 0, 2, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE void __set_TTBCR(uint32_t ttbcr) +{ + __MCR(15, 0, ttbcr, 2, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_DACR(void) +{ + return __MRC(15, 0, 3, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_DACR(uint32_t dacr) +{ + __MCR(15, 0, dacr, 3, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_DFSR(void) +{ + return __MRC(15, 0, 5, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_DFSR(uint32_t dfsr) +{ + __MCR(15, 0, dfsr, 5, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_IFSR(void) +{ + return __MRC(15, 0, 5, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE void __set_IFSR(uint32_t ifsr) +{ + __MCR(15, 0, ifsr, 5, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_DFAR(void) +{ + return __MRC(15, 0, 6, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_DFAR(uint32_t dfar) +{ + __MCR(15, 0, dfar, 6, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_IFAR(void) +{ + return __MRC(15, 0, 6, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE void __set_IFAR(uint32_t ifar) +{ + __MCR(15, 0, ifar, 6, 0, 2); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_VBAR(void) +{ + return __MRC(15, 0, 12, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_VBAR(uint32_t vbar) +{ + __MCR(15, 0, vbar, 12, 0, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_ISR(void) +{ + return __MRC(15, 0, 12, 1, 0); +} + +FORCEDINLINE __STATIC_INLINE void __set_ISR(uint32_t isr) +{ + __MCR(15, 0, isr, 12, 1, 0); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_CONTEXTIDR(void) +{ + return __MRC(15, 0, 13, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE void __set_CONTEXTIDR(uint32_t contextidr) +{ + __MCR(15, 0, contextidr, 13, 0, 1); +} + +FORCEDINLINE __STATIC_INLINE uint32_t __get_CBAR(void) +{ + return __MRC(15, 4, 15, 0, 0); +} + +/******************************************************************************* + * GIC相关内容 + *有关GIC的内容，参考：ARM Generic Interrupt Controller(ARM GIC控制器)V2.0.pdf + ******************************************************************************/ + +/* + * GIC寄存器描述结构体， + * GIC分为分发器端和CPU接口端 + */ +typedef struct +{ + uint32_t RESERVED0[1024]; + __IOM uint32_t D_CTLR; /*!< Offset: 0x1000 (R/W) Distributor Control Register */ + __IM uint32_t D_TYPER; /*!< Offset: 0x1004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t D_IIDR; /*!< Offset: 0x1008 (R/ ) Distributor Implementer Identification Register */ + uint32_t RESERVED1[29]; + __IOM uint32_t D_IGROUPR[16]; /*!< Offset: 0x1080 - 0x0BC (R/W) Interrupt Group Registers */ + uint32_t RESERVED2[16]; + __IOM uint32_t D_ISENABLER[16]; /*!< Offset: 0x1100 - 0x13C (R/W) Interrupt Set-Enable Registers */ + uint32_t RESERVED3[16]; + __IOM uint32_t D_ICENABLER[16]; /*!< Offset: 0x1180 - 0x1BC (R/W) Interrupt Clear-Enable Registers */ + uint32_t RESERVED4[16]; + __IOM uint32_t D_ISPENDR[16]; /*!< Offset: 0x1200 - 0x23C (R/W) Interrupt Set-Pending Registers */ + uint32_t RESERVED5[16]; + __IOM uint32_t D_ICPENDR[16]; /*!< Offset: 0x1280 - 0x2BC (R/W) Interrupt Clear-Pending Registers */ + uint32_t RESERVED6[16]; + __IOM uint32_t D_ISACTIVER[16]; /*!< Offset: 0x1300 - 0x33C (R/W) Interrupt Set-Active Registers */ + uint32_t RESERVED7[16]; + __IOM uint32_t D_ICACTIVER[16]; /*!< Offset: 0x1380 - 0x3BC (R/W) Interrupt Clear-Active Registers */ + uint32_t RESERVED8[16]; + __IOM uint8_t D_IPRIORITYR[512]; /*!< Offset: 0x1400 - 0x5FC (R/W) Interrupt Priority Registers */ + uint32_t RESERVED9[128]; + __IOM uint8_t D_ITARGETSR[512]; /*!< Offset: 0x1800 - 0x9FC (R/W) Interrupt Targets Registers */ + uint32_t RESERVED10[128]; + __IOM uint32_t D_ICFGR[32]; /*!< Offset: 0x1C00 - 0xC7C (R/W) Interrupt configuration registers */ + uint32_t RESERVED11[32]; + __IM uint32_t D_PPISR; /*!< Offset: 0x1D00 (R/ ) Private Peripheral Interrupt Status Register */ + __IM uint32_t D_SPISR[15]; /*!< Offset: 0x1D04 - 0xD3C (R/ ) Shared Peripheral Interrupt Status Registers */ + uint32_t RESERVED12[112]; + __OM uint32_t D_SGIR; /*!< Offset: 0x1F00 ( /W) Software Generated Interrupt Register */ + uint32_t RESERVED13[3]; + __IOM uint8_t D_CPENDSGIR[16]; /*!< Offset: 0x1F10 - 0xF1C (R/W) SGI Clear-Pending Registers */ + __IOM uint8_t D_SPENDSGIR[16]; /*!< Offset: 0x1F20 - 0xF2C (R/W) SGI Set-Pending Registers */ + uint32_t RESERVED14[40]; + __IM uint32_t D_PIDR4; /*!< Offset: 0x1FD0 (R/ ) Peripheral ID4 Register */ + __IM uint32_t D_PIDR5; /*!< Offset: 0x1FD4 (R/ ) Peripheral ID5 Register */ + __IM uint32_t D_PIDR6; /*!< Offset: 0x1FD8 (R/ ) Peripheral ID6 Register */ + __IM uint32_t D_PIDR7; /*!< Offset: 0x1FDC (R/ ) Peripheral ID7 Register */ + __IM uint32_t D_PIDR0; /*!< Offset: 0x1FE0 (R/ ) Peripheral ID0 Register */ + __IM uint32_t D_PIDR1; /*!< Offset: 0x1FE4 (R/ ) Peripheral ID1 Register */ + __IM uint32_t D_PIDR2; /*!< Offset: 0x1FE8 (R/ ) Peripheral ID2 Register */ + __IM uint32_t D_PIDR3; /*!< Offset: 0x1FEC (R/ ) Peripheral ID3 Register */ + __IM uint32_t D_CIDR0; /*!< Offset: 0x1FF0 (R/ ) Component ID0 Register */ + __IM uint32_t D_CIDR1; /*!< Offset: 0x1FF4 (R/ ) Component ID1 Register */ + __IM uint32_t D_CIDR2; /*!< Offset: 0x1FF8 (R/ ) Component ID2 Register */ + __IM uint32_t D_CIDR3; /*!< Offset: 0x1FFC (R/ ) Component ID3 Register */ + + __IOM uint32_t C_CTLR; /*!< Offset: 0x2000 (R/W) CPU Interface Control Register */ + __IOM uint32_t C_PMR; /*!< Offset: 0x2004 (R/W) Interrupt Priority Mask Register */ + __IOM uint32_t C_BPR; /*!< Offset: 0x2008 (R/W) Binary Point Register */ + __IM uint32_t C_IAR; /*!< Offset: 0x200C (R/ ) Interrupt Acknowledge Register */ + __OM uint32_t C_EOIR; /*!< Offset: 0x2010 ( /W) End Of Interrupt Register */ + __IM uint32_t C_RPR; /*!< Offset: 0x2014 (R/ ) Running Priority Register */ + __IM uint32_t C_HPPIR; /*!< Offset: 0x2018 (R/ ) Highest Priority Pending Interrupt Register */ + __IOM uint32_t C_ABPR; /*!< Offset: 0x201C (R/W) Aliased Binary Point Register */ + __IM uint32_t C_AIAR; /*!< Offset: 0x2020 (R/ ) Aliased Interrupt Acknowledge Register */ + __OM uint32_t C_AEOIR; /*!< Offset: 0x2024 ( /W) Aliased End Of Interrupt Register */ + __IM uint32_t C_AHPPIR; /*!< Offset: 0x2028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ + uint32_t RESERVED15[41]; + __IOM uint32_t C_APR0; /*!< Offset: 0x20D0 (R/W) Active Priority Register */ + uint32_t RESERVED16[3]; + __IOM uint32_t C_NSAPR0; /*!< Offset: 0x20E0 (R/W) Non-secure Active Priority Register */ + uint32_t RESERVED17[6]; + __IM uint32_t C_IIDR; /*!< Offset: 0x20FC (R/ ) CPU Interface Identification Register */ + uint32_t RESERVED18[960]; + __OM uint32_t C_DIR; /*!< Offset: 0x3000 ( /W) Deactivate Interrupt Register */ +} GIC_Type; + + +/* + * GIC初始化 + * 为了简单使用GIC的group0 + */ +FORCEDINLINE __STATIC_INLINE void GIC_Init(void) +{ + uint32_t i; + uint32_t irqRegs; + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + irqRegs = (gic->D_TYPER & 0x1FUL) + 1; + + /* On POR, all SPI is in group 0, level-sensitive and using 1-N model */ + + /* Disable all PPI, SGI and SPI */ + for (i = 0; i < irqRegs; i++) + gic->D_ICENABLER[i] = 0xFFFFFFFFUL; + + /* Make all interrupts have higher priority */ + gic->C_PMR = (0xFFUL << (8 - __GIC_PRIO_BITS)) & 0xFFUL; + + /* No subpriority, all priority level allows preemption */ + gic->C_BPR = 7 - __GIC_PRIO_BITS; + + /* Enable group0 distribution */ + gic->D_CTLR = 1UL; + + /* Enable group0 signaling */ + gic->C_CTLR = 1UL; +} + +/* + * 使能指定的中断 + */ +FORCEDINLINE __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + gic->D_ISENABLER[((uint32_t)(int32_t)IRQn) >> 5] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + +/* + * 关闭指定的中断 + */ + +FORCEDINLINE __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + gic->D_ICENABLER[((uint32_t)(int32_t)IRQn) >> 5] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + +/* + * 返回中断号 + */ +FORCEDINLINE __STATIC_INLINE uint32_t GIC_AcknowledgeIRQ(void) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + return gic->C_IAR & 0x1FFFUL; +} + +/* + * 向EOIR写入发送中断的中断号来释放中断 + */ +FORCEDINLINE __STATIC_INLINE void GIC_DeactivateIRQ(uint32_t value) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + gic->C_EOIR = value; +} + +/* + * 获取运行优先级 + */ +FORCEDINLINE __STATIC_INLINE uint32_t GIC_GetRunningPriority(void) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + return gic->C_RPR & 0xFFUL; +} + +/* + * 设置组优先级 + */ +FORCEDINLINE __STATIC_INLINE void GIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + gic->C_BPR = PriorityGroup & 0x7UL; +} + +/* + * 获取组优先级 + */ +FORCEDINLINE __STATIC_INLINE uint32_t GIC_GetPriorityGrouping(void) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + + return gic->C_BPR & 0x7UL; +} + +/* + * 设置优先级 + */ +FORCEDINLINE __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + gic->D_IPRIORITYR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8UL - __GIC_PRIO_BITS)) & (uint32_t)0xFFUL); +} + +/* + * 获取优先级 + */ +FORCEDINLINE __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + GIC_Type *gic = (GIC_Type *)(__get_CBAR() & 0xFFFF0000UL); + return(((uint32_t)gic->D_IPRIORITYR[((uint32_t)(int32_t)IRQn)] >> (8UL - __GIC_PRIO_BITS))); +} + + +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/imx6ul/fsl_common.h b/board/ALPHA_I.MX_emmc_256ddr/imx6ul/fsl_common.h new file mode 100644 index 00000000..dcdff439 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/imx6ul/fsl_common.h @@ -0,0 +1,124 @@ +/************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : fsl_common.h +作者 : 左忠凯修改NXP官方SDK +版本 : V1.0 +描述 : NXP官方SDK的通用关宏定义文档 +其他 : NXP官方SDK的通用宏定义文档，默认基于IAR的， + 由左忠凯移植到Liux下。 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯移植 +**************************************************************/ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include "cc.h" /* cc.h为自行添加的文件 */ +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */ +}; + +/*! @brief Generic status return codes. */ +enum _generic_status +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + + +#endif /* _FSL_COMMON_H_ */ diff --git a/board/ALPHA_I.MX_emmc_256ddr/imx6ul/fsl_iomuxc.h b/board/ALPHA_I.MX_emmc_256ddr/imx6ul/fsl_iomuxc.h new file mode 100644 index 00000000..941ddddf --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/imx6ul/fsl_iomuxc.h @@ -0,0 +1,1123 @@ +/************************************************************** +Copyright © zuozhongkai Co., Ltd. 1998-2019. All rights reserved. +文件名 : fsl_iomuxc.h +作者 : 左忠凯修改NXP官方SDK +版本 : V1.0 +描述 : NXP官方SDK的寄存器地址定义文档 +其他 : NXP官方SDK的寄存器地址定义文档，默认基于IAR的， + 由左忠凯移植到Liux下。 +论坛 : www.openedv.com +日志 : 初版V1.0 2019/1/4 左忠凯移植 +**************************************************************/ + +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "MCIMX6Y2.h" +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.0. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @name Pin function ID */ +/*@{*/ +/*! @brief The pin function ID is a tuple of */ +#define IOMUXC_SNVS_BOOT_MODE0_GPIO5_IO10 0x02290000U, 0x5U, 0x00000000U, 0x0U, 0x02290044U +#define IOMUXC_SNVS_BOOT_MODE1_GPIO5_IO11 0x02290004U, 0x5U, 0x00000000U, 0x0U, 0x02290048U +#define IOMUXC_SNVS_SNVS_TAMPER0_GPIO5_IO00 0x02290008U, 0x5U, 0x00000000U, 0x0U, 0x0229004CU +#define IOMUXC_SNVS_SNVS_TAMPER1_GPIO5_IO01 0x0229000CU, 0x5U, 0x00000000U, 0x0U, 0x02290050U +#define IOMUXC_SNVS_SNVS_TAMPER2_GPIO5_IO02 0x02290010U, 0x5U, 0x00000000U, 0x0U, 0x02290054U +#define IOMUXC_SNVS_SNVS_TAMPER3_GPIO5_IO03 0x02290014U, 0x5U, 0x00000000U, 0x0U, 0x02290058U +#define IOMUXC_SNVS_SNVS_TAMPER4_GPIO5_IO04 0x02290018U, 0x5U, 0x00000000U, 0x0U, 0x0229005CU +#define IOMUXC_SNVS_SNVS_TAMPER5_GPIO5_IO05 0x0229001CU, 0x5U, 0x00000000U, 0x0U, 0x02290060U +#define IOMUXC_SNVS_SNVS_TAMPER6_GPIO5_IO06 0x02290020U, 0x5U, 0x00000000U, 0x0U, 0x02290064U +#define IOMUXC_SNVS_SNVS_TAMPER7_GPIO5_IO07 0x02290024U, 0x5U, 0x00000000U, 0x0U, 0x02290068U +#define IOMUXC_SNVS_SNVS_TAMPER8_GPIO5_IO08 0x02290028U, 0x5U, 0x00000000U, 0x0U, 0x0229006CU +#define IOMUXC_SNVS_SNVS_TAMPER9_GPIO5_IO09 0x0229002CU, 0x5U, 0x00000000U, 0x0U, 0x02290070U +#define IOMUXC_SNVS_TEST_MODE 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x02290030U +#define IOMUXC_SNVS_POR_B 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x02290034U +#define IOMUXC_SNVS_ONOFF 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x02290038U +#define IOMUXC_SNVS_SNVS_PMIC_ON_REQ 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x0229003CU +#define IOMUXC_SNVS_CCM_PMIC_STBY_REQ 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x02290040U +#define IOMUXC_JTAG_MOD_SJC_MOD 0x020E0044U, 0x0U, 0x00000000U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_MOD_GPT2_CLK 0x020E0044U, 0x1U, 0x020E05A0U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_MOD_SPDIF_OUT 0x020E0044U, 0x2U, 0x00000000U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_MOD_ENET1_REF_CLK_25M 0x020E0044U, 0x3U, 0x00000000U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_MOD_CCM_PMIC_RDY 0x020E0044U, 0x4U, 0x020E04C0U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_MOD_GPIO1_IO10 0x020E0044U, 0x5U, 0x00000000U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_MOD_SDMA_EXT_EVENT00 0x020E0044U, 0x6U, 0x020E0610U, 0x0U, 0x020E02D0U +#define IOMUXC_JTAG_TMS_SJC_TMS 0x020E0048U, 0x0U, 0x00000000U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_GPT2_CAPTURE1 0x020E0048U, 0x1U, 0x020E0598U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_SAI2_MCLK 0x020E0048U, 0x2U, 0x020E05F0U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_CCM_CLKO1 0x020E0048U, 0x3U, 0x00000000U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_CCM_WAIT 0x020E0048U, 0x4U, 0x00000000U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_GPIO1_IO11 0x020E0048U, 0x5U, 0x00000000U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_SDMA_EXT_EVENT01 0x020E0048U, 0x6U, 0x020E0614U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TMS_EPIT1_OUT 0x020E0048U, 0x8U, 0x00000000U, 0x0U, 0x020E02D4U +#define IOMUXC_JTAG_TDO_SJC_TDO 0x020E004CU, 0x0U, 0x00000000U, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_GPT2_CAPTURE2 0x020E004CU, 0x1U, 0x020E059CU, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_SAI2_TX_SYNC 0x020E004CU, 0x2U, 0x020E05FCU, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_CCM_CLKO2 0x020E004CU, 0x3U, 0x00000000U, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_CCM_STOP 0x020E004CU, 0x4U, 0x00000000U, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_GPIO1_IO12 0x020E004CU, 0x5U, 0x00000000U, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_MQS_RIGHT 0x020E004CU, 0x6U, 0x00000000U, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDO_EPIT2_OUT 0x020E004CU, 0x8U, 0x00000000U, 0x0U, 0x020E02D8U +#define IOMUXC_JTAG_TDI_SJC_TDI 0x020E0050U, 0x0U, 0x00000000U, 0x0U, 0x020E02DCU +#define IOMUXC_JTAG_TDI_GPT2_COMPARE1 0x020E0050U, 0x1U, 0x00000000U, 0x0U, 0x020E02DCU +#define IOMUXC_JTAG_TDI_SAI2_TX_BCLK 0x020E0050U, 0x2U, 0x020E05F8U, 0x0U, 0x020E02DCU +#define IOMUXC_JTAG_TDI_PWM6_OUT 0x020E0050U, 0x4U, 0x00000000U, 0x0U, 0x020E02DCU +#define IOMUXC_JTAG_TDI_GPIO1_IO13 0x020E0050U, 0x5U, 0x00000000U, 0x0U, 0x020E02DCU +#define IOMUXC_JTAG_TDI_MQS_LEFT 0x020E0050U, 0x6U, 0x00000000U, 0x0U, 0x020E02DCU +#define IOMUXC_JTAG_TCK_SJC_TCK 0x020E0054U, 0x0U, 0x00000000U, 0x0U, 0x020E02E0U +#define IOMUXC_JTAG_TCK_GPT2_COMPARE2 0x020E0054U, 0x1U, 0x00000000U, 0x0U, 0x020E02E0U +#define IOMUXC_JTAG_TCK_SAI2_RX_DATA 0x020E0054U, 0x2U, 0x020E05F4U, 0x0U, 0x020E02E0U +#define IOMUXC_JTAG_TCK_PWM7_OUT 0x020E0054U, 0x4U, 0x00000000U, 0x0U, 0x020E02E0U +#define IOMUXC_JTAG_TCK_GPIO1_IO14 0x020E0054U, 0x5U, 0x00000000U, 0x0U, 0x020E02E0U +#define IOMUXC_JTAG_TRST_B_SJC_TRSTB 0x020E0058U, 0x0U, 0x00000000U, 0x0U, 0x020E02E4U +#define IOMUXC_JTAG_TRST_B_GPT2_COMPARE3 0x020E0058U, 0x1U, 0x00000000U, 0x0U, 0x020E02E4U +#define IOMUXC_JTAG_TRST_B_SAI2_TX_DATA 0x020E0058U, 0x2U, 0x00000000U, 0x0U, 0x020E02E4U +#define IOMUXC_JTAG_TRST_B_PWM8_OUT 0x020E0058U, 0x4U, 0x00000000U, 0x0U, 0x020E02E4U +#define IOMUXC_JTAG_TRST_B_GPIO1_IO15 0x020E0058U, 0x5U, 0x00000000U, 0x0U, 0x020E02E4U +#define IOMUXC_GPIO1_IO00_I2C2_SCL 0x020E005CU, 0x0U, 0x020E05ACU, 0x1U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_GPT1_CAPTURE1 0x020E005CU, 0x1U, 0x020E058CU, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_ANATOP_OTG1_ID 0x020E005CU, 0x2U, 0x020E04B8U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_ENET1_REF_CLK1 0x020E005CU, 0x3U, 0x020E0574U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_MQS_RIGHT 0x020E005CU, 0x4U, 0x00000000U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x020E005CU, 0x5U, 0x00000000U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_ENET1_1588_EVENT0_IN 0x020E005CU, 0x6U, 0x00000000U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_SRC_SYSTEM_RESET 0x020E005CU, 0x7U, 0x00000000U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO00_WDOG3_WDOG_B 0x020E005CU, 0x8U, 0x00000000U, 0x0U, 0x020E02E8U +#define IOMUXC_GPIO1_IO01_I2C2_SDA 0x020E0060U, 0x0U, 0x020E05B0U, 0x1U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_GPT1_COMPARE1 0x020E0060U, 0x1U, 0x00000000U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_USB_OTG1_OC 0x020E0060U, 0x2U, 0x020E0664U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_ENET2_REF_CLK2 0x020E0060U, 0x3U, 0x020E057CU, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_MQS_LEFT 0x020E0060U, 0x4U, 0x00000000U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x020E0060U, 0x5U, 0x00000000U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_ENET1_1588_EVENT0_OUT 0x020E0060U, 0x6U, 0x00000000U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_SRC_EARLY_RESET 0x020E0060U, 0x7U, 0x00000000U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO01_WDOG1_WDOG_B 0x020E0060U, 0x8U, 0x00000000U, 0x0U, 0x020E02ECU +#define IOMUXC_GPIO1_IO02_I2C1_SCL 0x020E0064U, 0x0U, 0x020E05A4U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_GPT1_COMPARE2 0x020E0064U, 0x1U, 0x00000000U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_USB_OTG2_PWR 0x020E0064U, 0x2U, 0x00000000U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_ENET1_REF_CLK_25M 0x020E0064U, 0x3U, 0x00000000U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_USDHC1_WP 0x020E0064U, 0x4U, 0x020E066CU, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x020E0064U, 0x5U, 0x00000000U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_SDMA_EXT_EVENT00 0x020E0064U, 0x6U, 0x020E0610U, 0x1U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_SRC_ANY_PU_RESET 0x020E0064U, 0x7U, 0x00000000U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_UART1_TX 0x020E0064U, 0x8U, 0x00000000U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO02_UART1_RX 0x020E0064U, 0x8U, 0x020E0624U, 0x0U, 0x020E02F0U +#define IOMUXC_GPIO1_IO03_I2C1_SDA 0x020E0068U, 0x0U, 0x020E05A8U, 0x1U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_GPT1_COMPARE3 0x020E0068U, 0x1U, 0x00000000U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_USB_OTG2_OC 0x020E0068U, 0x2U, 0x020E0660U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_USDHC1_CD_B 0x020E0068U, 0x4U, 0x020E0668U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x020E0068U, 0x5U, 0x00000000U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_CCM_DI0_EXT_CLK 0x020E0068U, 0x6U, 0x00000000U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_SRC_TESTER_ACK 0x020E0068U, 0x7U, 0x00000000U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_UART1_RX 0x020E0068U, 0x8U, 0x020E0624U, 0x1U, 0x020E02F4U +#define IOMUXC_GPIO1_IO03_UART1_TX 0x020E0068U, 0x8U, 0x00000000U, 0x0U, 0x020E02F4U +#define IOMUXC_GPIO1_IO04_ENET1_REF_CLK1 0x020E006CU, 0x0U, 0x020E0574U, 0x1U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_PWM3_OUT 0x020E006CU, 0x1U, 0x00000000U, 0x0U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_USB_OTG1_PWR 0x020E006CU, 0x2U, 0x00000000U, 0x0U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_USDHC1_RESET_B 0x020E006CU, 0x4U, 0x00000000U, 0x0U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x020E006CU, 0x5U, 0x00000000U, 0x0U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_ENET2_1588_EVENT0_IN 0x020E006CU, 0x6U, 0x00000000U, 0x0U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_UART5_TX 0x020E006CU, 0x8U, 0x00000000U, 0x0U, 0x020E02F8U +#define IOMUXC_GPIO1_IO04_UART5_RX 0x020E006CU, 0x8U, 0x020E0644U, 0x2U, 0x020E02F8U +#define IOMUXC_GPIO1_IO05_ENET2_REF_CLK2 0x020E0070U, 0x0U, 0x020E057CU, 0x1U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_PWM4_OUT 0x020E0070U, 0x1U, 0x00000000U, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_ANATOP_OTG2_ID 0x020E0070U, 0x2U, 0x020E04BCU, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_CSI_FIELD 0x020E0070U, 0x3U, 0x020E0530U, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_USDHC1_VSELECT 0x020E0070U, 0x4U, 0x00000000U, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x020E0070U, 0x5U, 0x00000000U, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_ENET2_1588_EVENT0_OUT 0x020E0070U, 0x6U, 0x00000000U, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_UART5_RX 0x020E0070U, 0x8U, 0x020E0644U, 0x3U, 0x020E02FCU +#define IOMUXC_GPIO1_IO05_UART5_TX 0x020E0070U, 0x8U, 0x00000000U, 0x0U, 0x020E02FCU +#define IOMUXC_GPIO1_IO06_ENET1_MDIO 0x020E0074U, 0x0U, 0x020E0578U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_ENET2_MDIO 0x020E0074U, 0x1U, 0x020E0580U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_USB_OTG_PWR_WAKE 0x020E0074U, 0x2U, 0x00000000U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_CSI_MCLK 0x020E0074U, 0x3U, 0x00000000U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_USDHC2_WP 0x020E0074U, 0x4U, 0x020E069CU, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x020E0074U, 0x5U, 0x00000000U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_CCM_WAIT 0x020E0074U, 0x6U, 0x00000000U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_CCM_REF_EN_B 0x020E0074U, 0x7U, 0x00000000U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_UART1_CTS_B 0x020E0074U, 0x8U, 0x00000000U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO06_UART1_RTS_B 0x020E0074U, 0x8U, 0x020E0620U, 0x0U, 0x020E0300U +#define IOMUXC_GPIO1_IO07_ENET1_MDC 0x020E0078U, 0x0U, 0x00000000U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_ENET2_MDC 0x020E0078U, 0x1U, 0x00000000U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_USB_OTG_HOST_MODE 0x020E0078U, 0x2U, 0x00000000U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_CSI_PIXCLK 0x020E0078U, 0x3U, 0x020E0528U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_USDHC2_CD_B 0x020E0078U, 0x4U, 0x020E0674U, 0x1U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x020E0078U, 0x5U, 0x00000000U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_CCM_STOP 0x020E0078U, 0x6U, 0x00000000U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_UART1_RTS_B 0x020E0078U, 0x8U, 0x020E0620U, 0x1U, 0x020E0304U +#define IOMUXC_GPIO1_IO07_UART1_CTS_B 0x020E0078U, 0x8U, 0x00000000U, 0x0U, 0x020E0304U +#define IOMUXC_GPIO1_IO08_PWM1_OUT 0x020E007CU, 0x0U, 0x00000000U, 0x0U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_WDOG1_WDOG_B 0x020E007CU, 0x1U, 0x00000000U, 0x0U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_SPDIF_OUT 0x020E007CU, 0x2U, 0x00000000U, 0x0U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_CSI_VSYNC 0x020E007CU, 0x3U, 0x020E052CU, 0x1U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_USDHC2_VSELECT 0x020E007CU, 0x4U, 0x00000000U, 0x0U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x020E007CU, 0x5U, 0x00000000U, 0x0U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_CCM_PMIC_RDY 0x020E007CU, 0x6U, 0x020E04C0U, 0x1U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_UART5_RTS_B 0x020E007CU, 0x8U, 0x020E0640U, 0x1U, 0x020E0308U +#define IOMUXC_GPIO1_IO08_UART5_CTS_B 0x020E007CU, 0x8U, 0x00000000U, 0x0U, 0x020E0308U +#define IOMUXC_GPIO1_IO09_PWM2_OUT 0x020E0080U, 0x0U, 0x00000000U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_WDOG1_WDOG_ANY 0x020E0080U, 0x1U, 0x00000000U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_SPDIF_IN 0x020E0080U, 0x2U, 0x020E0618U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_CSI_HSYNC 0x020E0080U, 0x3U, 0x020E0524U, 0x1U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_USDHC2_RESET_B 0x020E0080U, 0x4U, 0x00000000U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x020E0080U, 0x5U, 0x00000000U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_USDHC1_RESET_B 0x020E0080U, 0x6U, 0x00000000U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_UART5_CTS_B 0x020E0080U, 0x8U, 0x00000000U, 0x0U, 0x020E030CU +#define IOMUXC_GPIO1_IO09_UART5_RTS_B 0x020E0080U, 0x8U, 0x020E0640U, 0x2U, 0x020E030CU +#define IOMUXC_UART1_TX_DATA_UART1_TX 0x020E0084U, 0x0U, 0x00000000U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_UART1_RX 0x020E0084U, 0x0U, 0x020E0624U, 0x2U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_ENET1_RDATA02 0x020E0084U, 0x1U, 0x00000000U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_I2C3_SCL 0x020E0084U, 0x2U, 0x020E05B4U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_CSI_DATA02 0x020E0084U, 0x3U, 0x020E04C4U, 0x1U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_GPT1_COMPARE1 0x020E0084U, 0x4U, 0x00000000U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_GPIO1_IO16 0x020E0084U, 0x5U, 0x00000000U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_SPDIF_OUT 0x020E0084U, 0x8U, 0x00000000U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_UART5_TX 0x020E0084U, 0x9U, 0x00000000U, 0x0U, 0x020E0310U +#define IOMUXC_UART1_TX_DATA_UART5_RX 0x020E0084U, 0x9U, 0x020E0644U, 0x4U, 0x020E0310U +#define IOMUXC_UART1_RX_DATA_UART1_RX 0x020E0088U, 0x0U, 0x020E0624U, 0x3U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_UART1_TX 0x020E0088U, 0x0U, 0x00000000U, 0x0U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_ENET1_RDATA03 0x020E0088U, 0x1U, 0x00000000U, 0x0U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_I2C3_SDA 0x020E0088U, 0x2U, 0x020E05B8U, 0x0U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_CSI_DATA03 0x020E0088U, 0x3U, 0x020E04C8U, 0x1U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_GPT1_CLK 0x020E0088U, 0x4U, 0x020E0594U, 0x0U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_GPIO1_IO17 0x020E0088U, 0x5U, 0x00000000U, 0x0U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_SPDIF_IN 0x020E0088U, 0x8U, 0x020E0618U, 0x1U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_UART5_RX 0x020E0088U, 0x9U, 0x020E0644U, 0x5U, 0x020E0314U +#define IOMUXC_UART1_RX_DATA_UART5_TX 0x020E0088U, 0x9U, 0x00000000U, 0x0U, 0x020E0314U +#define IOMUXC_UART1_CTS_B_UART1_CTS_B 0x020E008CU, 0x0U, 0x00000000U, 0x0U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_UART1_RTS_B 0x020E008CU, 0x0U, 0x020E0620U, 0x2U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_ENET1_RX_CLK 0x020E008CU, 0x1U, 0x00000000U, 0x0U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_USDHC1_WP 0x020E008CU, 0x2U, 0x020E066CU, 0x1U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_CSI_DATA04 0x020E008CU, 0x3U, 0x020E04D8U, 0x0U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_ENET2_1588_EVENT1_IN 0x020E008CU, 0x4U, 0x00000000U, 0x0U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_GPIO1_IO18 0x020E008CU, 0x5U, 0x00000000U, 0x0U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_USDHC2_WP 0x020E008CU, 0x8U, 0x020E069CU, 0x1U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_UART5_CTS_B 0x020E008CU, 0x9U, 0x00000000U, 0x0U, 0x020E0318U +#define IOMUXC_UART1_CTS_B_UART5_RTS_B 0x020E008CU, 0x9U, 0x020E0640U, 0x3U, 0x020E0318U +#define IOMUXC_UART1_RTS_B_UART1_RTS_B 0x020E0090U, 0x0U, 0x020E0620U, 0x3U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_UART1_CTS_B 0x020E0090U, 0x0U, 0x00000000U, 0x0U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_ENET1_TX_ER 0x020E0090U, 0x1U, 0x00000000U, 0x0U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_USDHC1_CD_B 0x020E0090U, 0x2U, 0x020E0668U, 0x1U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_CSI_DATA05 0x020E0090U, 0x3U, 0x020E04CCU, 0x1U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_ENET2_1588_EVENT1_OUT 0x020E0090U, 0x4U, 0x00000000U, 0x0U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_GPIO1_IO19 0x020E0090U, 0x5U, 0x00000000U, 0x0U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_USDHC2_CD_B 0x020E0090U, 0x8U, 0x020E0674U, 0x2U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_UART5_RTS_B 0x020E0090U, 0x9U, 0x020E0640U, 0x4U, 0x020E031CU +#define IOMUXC_UART1_RTS_B_UART5_CTS_B 0x020E0090U, 0x9U, 0x00000000U, 0x0U, 0x020E031CU +#define IOMUXC_UART2_TX_DATA_UART2_TX 0x020E0094U, 0x0U, 0x00000000U, 0x0U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_UART2_RX 0x020E0094U, 0x0U, 0x020E062CU, 0x0U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_ENET1_TDATA02 0x020E0094U, 0x1U, 0x00000000U, 0x0U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_I2C4_SCL 0x020E0094U, 0x2U, 0x020E05BCU, 0x0U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_CSI_DATA06 0x020E0094U, 0x3U, 0x020E04DCU, 0x0U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_GPT1_CAPTURE1 0x020E0094U, 0x4U, 0x020E058CU, 0x1U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_GPIO1_IO20 0x020E0094U, 0x5U, 0x00000000U, 0x0U, 0x020E0320U +#define IOMUXC_UART2_TX_DATA_ECSPI3_SS0 0x020E0094U, 0x8U, 0x020E0560U, 0x0U, 0x020E0320U +#define IOMUXC_UART2_RX_DATA_UART2_RX 0x020E0098U, 0x0U, 0x020E062CU, 0x1U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_UART2_TX 0x020E0098U, 0x0U, 0x00000000U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_ENET1_TDATA03 0x020E0098U, 0x1U, 0x00000000U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_I2C4_SDA 0x020E0098U, 0x2U, 0x020E05C0U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_CSI_DATA07 0x020E0098U, 0x3U, 0x020E04E0U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_GPT1_CAPTURE2 0x020E0098U, 0x4U, 0x020E0590U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_GPIO1_IO21 0x020E0098U, 0x5U, 0x00000000U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_SJC_DONE 0x020E0098U, 0x7U, 0x00000000U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_RX_DATA_ECSPI3_SCLK 0x020E0098U, 0x8U, 0x020E0554U, 0x0U, 0x020E0324U +#define IOMUXC_UART2_CTS_B_UART2_CTS_B 0x020E009CU, 0x0U, 0x00000000U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_UART2_RTS_B 0x020E009CU, 0x0U, 0x020E0628U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_ENET1_CRS 0x020E009CU, 0x1U, 0x00000000U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_FLEXCAN2_TX 0x020E009CU, 0x2U, 0x00000000U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_CSI_DATA08 0x020E009CU, 0x3U, 0x020E04E4U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_GPT1_COMPARE2 0x020E009CU, 0x4U, 0x00000000U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_GPIO1_IO22 0x020E009CU, 0x5U, 0x00000000U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_SJC_DE_B 0x020E009CU, 0x7U, 0x00000000U, 0x0U, 0x020E0328U +#define IOMUXC_UART2_CTS_B_ECSPI3_MOSI 0x020E009CU, 0x8U, 0x020E055CU, 0x0U, 0x020E0328U +#define IOMUXC_UART2_RTS_B_UART2_RTS_B 0x020E00A0U, 0x0U, 0x020E0628U, 0x1U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_UART2_CTS_B 0x020E00A0U, 0x0U, 0x00000000U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_ENET1_COL 0x020E00A0U, 0x1U, 0x00000000U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_FLEXCAN2_RX 0x020E00A0U, 0x2U, 0x020E0588U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_CSI_DATA09 0x020E00A0U, 0x3U, 0x020E04E8U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_GPT1_COMPARE3 0x020E00A0U, 0x4U, 0x00000000U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_GPIO1_IO23 0x020E00A0U, 0x5U, 0x00000000U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_SJC_FAIL 0x020E00A0U, 0x7U, 0x00000000U, 0x0U, 0x020E032CU +#define IOMUXC_UART2_RTS_B_ECSPI3_MISO 0x020E00A0U, 0x8U, 0x020E0558U, 0x0U, 0x020E032CU +#define IOMUXC_UART3_TX_DATA_UART3_TX 0x020E00A4U, 0x0U, 0x00000000U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_UART3_RX 0x020E00A4U, 0x0U, 0x020E0634U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_ENET2_RDATA02 0x020E00A4U, 0x1U, 0x00000000U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_CSI_DATA01 0x020E00A4U, 0x3U, 0x020E04D4U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_UART2_CTS_B 0x020E00A4U, 0x4U, 0x00000000U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_UART2_RTS_B 0x020E00A4U, 0x4U, 0x020E0628U, 0x2U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_GPIO1_IO24 0x020E00A4U, 0x5U, 0x00000000U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_SJC_JTAG_ACT 0x020E00A4U, 0x7U, 0x00000000U, 0x0U, 0x020E0330U +#define IOMUXC_UART3_TX_DATA_ANATOP_OTG1_ID 0x020E00A4U, 0x8U, 0x020E04B8U, 0x1U, 0x020E0330U +#define IOMUXC_UART3_RX_DATA_UART3_RX 0x020E00A8U, 0x0U, 0x020E0634U, 0x1U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_UART3_TX 0x020E00A8U, 0x0U, 0x00000000U, 0x0U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_ENET2_RDATA03 0x020E00A8U, 0x1U, 0x00000000U, 0x0U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_CSI_DATA00 0x020E00A8U, 0x3U, 0x020E04D0U, 0x0U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_UART2_RTS_B 0x020E00A8U, 0x4U, 0x020E0628U, 0x3U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_UART2_CTS_B 0x020E00A8U, 0x4U, 0x00000000U, 0x0U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_GPIO1_IO25 0x020E00A8U, 0x5U, 0x00000000U, 0x0U, 0x020E0334U +#define IOMUXC_UART3_RX_DATA_EPIT1_OUT 0x020E00A8U, 0x8U, 0x00000000U, 0x0U, 0x020E0334U +#define IOMUXC_UART3_CTS_B_UART3_CTS_B 0x020E00ACU, 0x0U, 0x00000000U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_UART3_RTS_B 0x020E00ACU, 0x0U, 0x020E0630U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_ENET2_RX_CLK 0x020E00ACU, 0x1U, 0x00000000U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_FLEXCAN1_TX 0x020E00ACU, 0x2U, 0x00000000U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_CSI_DATA10 0x020E00ACU, 0x3U, 0x020E04ECU, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_ENET1_1588_EVENT1_IN 0x020E00ACU, 0x4U, 0x00000000U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_GPIO1_IO26 0x020E00ACU, 0x5U, 0x00000000U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_CTS_B_EPIT2_OUT 0x020E00ACU, 0x8U, 0x00000000U, 0x0U, 0x020E0338U +#define IOMUXC_UART3_RTS_B_UART3_RTS_B 0x020E00B0U, 0x0U, 0x020E0630U, 0x1U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_UART3_CTS_B 0x020E00B0U, 0x0U, 0x00000000U, 0x0U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_ENET2_TX_ER 0x020E00B0U, 0x1U, 0x00000000U, 0x0U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_FLEXCAN1_RX 0x020E00B0U, 0x2U, 0x020E0584U, 0x0U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_CSI_DATA11 0x020E00B0U, 0x3U, 0x020E04F0U, 0x0U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_ENET1_1588_EVENT1_OUT 0x020E00B0U, 0x4U, 0x00000000U, 0x0U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_GPIO1_IO27 0x020E00B0U, 0x5U, 0x00000000U, 0x0U, 0x020E033CU +#define IOMUXC_UART3_RTS_B_WDOG1_WDOG_B 0x020E00B0U, 0x8U, 0x00000000U, 0x0U, 0x020E033CU +#define IOMUXC_UART4_TX_DATA_UART4_TX 0x020E00B4U, 0x0U, 0x00000000U, 0x0U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_UART4_RX 0x020E00B4U, 0x0U, 0x020E063CU, 0x0U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_ENET2_TDATA02 0x020E00B4U, 0x1U, 0x00000000U, 0x0U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_I2C1_SCL 0x020E00B4U, 0x2U, 0x020E05A4U, 0x1U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_CSI_DATA12 0x020E00B4U, 0x3U, 0x020E04F4U, 0x0U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_CSU_CSU_ALARM_AUT02 0x020E00B4U, 0x4U, 0x00000000U, 0x0U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_GPIO1_IO28 0x020E00B4U, 0x5U, 0x00000000U, 0x0U, 0x020E0340U +#define IOMUXC_UART4_TX_DATA_ECSPI2_SCLK 0x020E00B4U, 0x8U, 0x020E0544U, 0x1U, 0x020E0340U +#define IOMUXC_UART4_RX_DATA_UART4_RX 0x020E00B8U, 0x0U, 0x020E063CU, 0x1U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_UART4_TX 0x020E00B8U, 0x0U, 0x00000000U, 0x0U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_ENET2_TDATA03 0x020E00B8U, 0x1U, 0x00000000U, 0x0U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_I2C1_SDA 0x020E00B8U, 0x2U, 0x020E05A8U, 0x2U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_CSI_DATA13 0x020E00B8U, 0x3U, 0x020E04F8U, 0x0U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_CSU_CSU_ALARM_AUT01 0x020E00B8U, 0x4U, 0x00000000U, 0x0U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_GPIO1_IO29 0x020E00B8U, 0x5U, 0x00000000U, 0x0U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_ECSPI2_SS0 0x020E00B8U, 0x8U, 0x020E0550U, 0x1U, 0x020E0344U +#define IOMUXC_UART4_RX_DATA_EPDC_PWRCTRL01 0x020E00B8U, 0x9U, 0x00000000U, 0x0U, 0x020E0344U +#define IOMUXC_UART5_TX_DATA_GPIO1_IO30 0x020E00BCU, 0x5U, 0x00000000U, 0x0U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_ECSPI2_MOSI 0x020E00BCU, 0x8U, 0x020E054CU, 0x0U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_EPDC_PWRCTRL02 0x020E00BCU, 0x9U, 0x00000000U, 0x0U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_UART5_TX 0x020E00BCU, 0x0U, 0x00000000U, 0x0U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_UART5_RX 0x020E00BCU, 0x0U, 0x020E0644U, 0x6U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_ENET2_CRS 0x020E00BCU, 0x1U, 0x00000000U, 0x0U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_I2C2_SCL 0x020E00BCU, 0x2U, 0x020E05ACU, 0x2U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_CSI_DATA14 0x020E00BCU, 0x3U, 0x020E04FCU, 0x0U, 0x020E0348U +#define IOMUXC_UART5_TX_DATA_CSU_CSU_ALARM_AUT00 0x020E00BCU, 0x4U, 0x00000000U, 0x0U, 0x020E0348U +#define IOMUXC_UART5_RX_DATA_UART5_RX 0x020E00C0U, 0x0U, 0x020E0644U, 0x7U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_UART5_TX 0x020E00C0U, 0x0U, 0x00000000U, 0x0U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_ENET2_COL 0x020E00C0U, 0x1U, 0x00000000U, 0x0U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_I2C2_SDA 0x020E00C0U, 0x2U, 0x020E05B0U, 0x2U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_CSI_DATA15 0x020E00C0U, 0x3U, 0x020E0500U, 0x0U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_CSU_CSU_INT_DEB 0x020E00C0U, 0x4U, 0x00000000U, 0x0U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_GPIO1_IO31 0x020E00C0U, 0x5U, 0x00000000U, 0x0U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_ECSPI2_MISO 0x020E00C0U, 0x8U, 0x020E0548U, 0x1U, 0x020E034CU +#define IOMUXC_UART5_RX_DATA_EPDC_PWRCTRL03 0x020E00C0U, 0x9U, 0x00000000U, 0x0U, 0x020E034CU +#define IOMUXC_ENET1_RX_DATA0_ENET1_RDATA00 0x020E00C4U, 0x0U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_UART4_RTS_B 0x020E00C4U, 0x1U, 0x020E0638U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_UART4_CTS_B 0x020E00C4U, 0x1U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_PWM1_OUT 0x020E00C4U, 0x2U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_CSI_DATA16 0x020E00C4U, 0x3U, 0x020E0504U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_FLEXCAN1_TX 0x020E00C4U, 0x4U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_GPIO2_IO00 0x020E00C4U, 0x5U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_KPP_ROW00 0x020E00C4U, 0x6U, 0x020E05D0U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_USDHC1_LCTL 0x020E00C4U, 0x8U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA0_EPDC_SDCE04 0x020E00C4U, 0x9U, 0x00000000U, 0x0U, 0x020E0350U +#define IOMUXC_ENET1_RX_DATA1_ENET1_RDATA01 0x020E00C8U, 0x0U, 0x00000000U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_UART4_CTS_B 0x020E00C8U, 0x1U, 0x00000000U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_UART4_RTS_B 0x020E00C8U, 0x1U, 0x020E0638U, 0x1U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_PWM2_OUT 0x020E00C8U, 0x2U, 0x00000000U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_CSI_DATA17 0x020E00C8U, 0x3U, 0x020E0508U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_FLEXCAN1_RX 0x020E00C8U, 0x4U, 0x020E0584U, 0x1U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_GPIO2_IO01 0x020E00C8U, 0x5U, 0x00000000U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_KPP_COL00 0x020E00C8U, 0x6U, 0x020E05C4U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_USDHC2_LCTL 0x020E00C8U, 0x8U, 0x00000000U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_DATA1_EPDC_SDCE05 0x020E00C8U, 0x9U, 0x00000000U, 0x0U, 0x020E0354U +#define IOMUXC_ENET1_RX_EN_ENET1_RX_EN 0x020E00CCU, 0x0U, 0x00000000U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_UART5_RTS_B 0x020E00CCU, 0x1U, 0x020E0640U, 0x5U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_UART5_CTS_B 0x020E00CCU, 0x1U, 0x00000000U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_CSI_DATA18 0x020E00CCU, 0x3U, 0x020E050CU, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_FLEXCAN2_TX 0x020E00CCU, 0x4U, 0x00000000U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_GPIO2_IO02 0x020E00CCU, 0x5U, 0x00000000U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_KPP_ROW01 0x020E00CCU, 0x6U, 0x020E05D4U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_USDHC1_VSELECT 0x020E00CCU, 0x8U, 0x00000000U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_RX_EN_EPDC_SDCE06 0x020E00CCU, 0x9U, 0x00000000U, 0x0U, 0x020E0358U +#define IOMUXC_ENET1_TX_DATA0_ENET1_TDATA00 0x020E00D0U, 0x0U, 0x00000000U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_UART5_CTS_B 0x020E00D0U, 0x1U, 0x00000000U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_UART5_RTS_B 0x020E00D0U, 0x1U, 0x020E0640U, 0x6U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_CSI_DATA19 0x020E00D0U, 0x3U, 0x020E0510U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_FLEXCAN2_RX 0x020E00D0U, 0x4U, 0x020E0588U, 0x1U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_GPIO2_IO03 0x020E00D0U, 0x5U, 0x00000000U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_KPP_COL01 0x020E00D0U, 0x6U, 0x020E05C8U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_USDHC2_VSELECT 0x020E00D0U, 0x8U, 0x00000000U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA0_EPDC_SDCE07 0x020E00D0U, 0x9U, 0x00000000U, 0x0U, 0x020E035CU +#define IOMUXC_ENET1_TX_DATA1_ENET1_TDATA01 0x020E00D4U, 0x0U, 0x00000000U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_UART6_CTS_B 0x020E00D4U, 0x1U, 0x00000000U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_UART6_RTS_B 0x020E00D4U, 0x1U, 0x020E0648U, 0x2U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_PWM5_OUT 0x020E00D4U, 0x2U, 0x00000000U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_CSI_DATA20 0x020E00D4U, 0x3U, 0x020E0514U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_ENET2_MDIO 0x020E00D4U, 0x4U, 0x020E0580U, 0x1U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_GPIO2_IO04 0x020E00D4U, 0x5U, 0x00000000U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_KPP_ROW02 0x020E00D4U, 0x6U, 0x020E05D8U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_WDOG1_WDOG_RST_B_DEB 0x020E00D4U, 0x8U, 0x00000000U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_DATA1_EPDC_SDCE08 0x020E00D4U, 0x9U, 0x00000000U, 0x0U, 0x020E0360U +#define IOMUXC_ENET1_TX_EN_ENET1_TX_EN 0x020E00D8U, 0x0U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_UART6_RTS_B 0x020E00D8U, 0x1U, 0x020E0648U, 0x3U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_UART6_CTS_B 0x020E00D8U, 0x1U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_PWM6_OUT 0x020E00D8U, 0x2U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_CSI_DATA21 0x020E00D8U, 0x3U, 0x020E0518U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_ENET2_MDC 0x020E00D8U, 0x4U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_GPIO2_IO05 0x020E00D8U, 0x5U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_KPP_COL02 0x020E00D8U, 0x6U, 0x020E05CCU, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_WDOG2_WDOG_RST_B_DEB 0x020E00D8U, 0x8U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_EN_EPDC_SDCE09 0x020E00D8U, 0x9U, 0x00000000U, 0x0U, 0x020E0364U +#define IOMUXC_ENET1_TX_CLK_ENET1_TX_CLK 0x020E00DCU, 0x0U, 0x00000000U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_UART7_CTS_B 0x020E00DCU, 0x1U, 0x00000000U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_UART7_RTS_B 0x020E00DCU, 0x1U, 0x020E0650U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_PWM7_OUT 0x020E00DCU, 0x2U, 0x00000000U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_CSI_DATA22 0x020E00DCU, 0x3U, 0x020E051CU, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_ENET1_REF_CLK1 0x020E00DCU, 0x4U, 0x020E0574U, 0x2U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_GPIO2_IO06 0x020E00DCU, 0x5U, 0x00000000U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_KPP_ROW03 0x020E00DCU, 0x6U, 0x00000000U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_GPT1_CLK 0x020E00DCU, 0x8U, 0x020E0594U, 0x1U, 0x020E0368U +#define IOMUXC_ENET1_TX_CLK_EPDC_SDOED 0x020E00DCU, 0x9U, 0x00000000U, 0x0U, 0x020E0368U +#define IOMUXC_ENET1_RX_ER_ENET1_RX_ER 0x020E00E0U, 0x0U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_UART7_RTS_B 0x020E00E0U, 0x1U, 0x020E0650U, 0x1U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_UART7_CTS_B 0x020E00E0U, 0x1U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_PWM8_OUT 0x020E00E0U, 0x2U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_CSI_DATA23 0x020E00E0U, 0x3U, 0x020E0520U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_EIM_CRE 0x020E00E0U, 0x4U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_GPIO2_IO07 0x020E00E0U, 0x5U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_KPP_COL03 0x020E00E0U, 0x6U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_GPT1_CAPTURE2 0x020E00E0U, 0x8U, 0x020E0590U, 0x1U, 0x020E036CU +#define IOMUXC_ENET1_RX_ER_EPDC_SDOEZ 0x020E00E0U, 0x9U, 0x00000000U, 0x0U, 0x020E036CU +#define IOMUXC_ENET2_RX_DATA0_ENET2_RDATA00 0x020E00E4U, 0x0U, 0x00000000U, 0x0U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_UART6_TX 0x020E00E4U, 0x1U, 0x00000000U, 0x0U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_UART6_RX 0x020E00E4U, 0x1U, 0x020E064CU, 0x1U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_I2C3_SCL 0x020E00E4U, 0x3U, 0x020E05B4U, 0x1U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_ENET1_MDIO 0x020E00E4U, 0x4U, 0x020E0578U, 0x1U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_GPIO2_IO08 0x020E00E4U, 0x5U, 0x00000000U, 0x0U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_KPP_ROW04 0x020E00E4U, 0x6U, 0x00000000U, 0x0U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_USB_OTG1_PWR 0x020E00E4U, 0x8U, 0x00000000U, 0x0U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA0_EPDC_SDDO08 0x020E00E4U, 0x9U, 0x00000000U, 0x0U, 0x020E0370U +#define IOMUXC_ENET2_RX_DATA1_ENET2_RDATA01 0x020E00E8U, 0x0U, 0x00000000U, 0x0U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_UART6_RX 0x020E00E8U, 0x1U, 0x020E064CU, 0x2U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_UART6_TX 0x020E00E8U, 0x1U, 0x00000000U, 0x0U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_I2C3_SDA 0x020E00E8U, 0x3U, 0x020E05B8U, 0x1U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_ENET1_MDC 0x020E00E8U, 0x4U, 0x00000000U, 0x0U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_GPIO2_IO09 0x020E00E8U, 0x5U, 0x00000000U, 0x0U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_KPP_COL04 0x020E00E8U, 0x6U, 0x00000000U, 0x0U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_USB_OTG1_OC 0x020E00E8U, 0x8U, 0x020E0664U, 0x1U, 0x020E0374U +#define IOMUXC_ENET2_RX_DATA1_EPDC_SDDO09 0x020E00E8U, 0x9U, 0x00000000U, 0x0U, 0x020E0374U +#define IOMUXC_ENET2_RX_EN_ENET2_RX_EN 0x020E00ECU, 0x0U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_UART7_TX 0x020E00ECU, 0x1U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_UART7_RX 0x020E00ECU, 0x1U, 0x020E0654U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_I2C4_SCL 0x020E00ECU, 0x3U, 0x020E05BCU, 0x1U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_EIM_ADDR26 0x020E00ECU, 0x4U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_GPIO2_IO10 0x020E00ECU, 0x5U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_KPP_ROW05 0x020E00ECU, 0x6U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_ENET1_REF_CLK_25M 0x020E00ECU, 0x8U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_RX_EN_EPDC_SDDO10 0x020E00ECU, 0x9U, 0x00000000U, 0x0U, 0x020E0378U +#define IOMUXC_ENET2_TX_DATA0_ENET2_TDATA00 0x020E00F0U, 0x0U, 0x00000000U, 0x0U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_UART7_RX 0x020E00F0U, 0x1U, 0x020E0654U, 0x1U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_UART7_TX 0x020E00F0U, 0x1U, 0x00000000U, 0x0U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_I2C4_SDA 0x020E00F0U, 0x3U, 0x020E05C0U, 0x1U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_EIM_EB_B02 0x020E00F0U, 0x4U, 0x00000000U, 0x0U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_GPIO2_IO11 0x020E00F0U, 0x5U, 0x00000000U, 0x0U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_KPP_COL05 0x020E00F0U, 0x6U, 0x00000000U, 0x0U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA0_EPDC_SDDO11 0x020E00F0U, 0x9U, 0x00000000U, 0x0U, 0x020E037CU +#define IOMUXC_ENET2_TX_DATA1_ENET2_TDATA01 0x020E00F4U, 0x0U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_UART8_TX 0x020E00F4U, 0x1U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_UART8_RX 0x020E00F4U, 0x1U, 0x020E065CU, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_ECSPI4_SCLK 0x020E00F4U, 0x3U, 0x020E0564U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_EIM_EB_B03 0x020E00F4U, 0x4U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_GPIO2_IO12 0x020E00F4U, 0x5U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_KPP_ROW06 0x020E00F4U, 0x6U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_USB_OTG2_PWR 0x020E00F4U, 0x8U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_DATA1_EPDC_SDDO12 0x020E00F4U, 0x9U, 0x00000000U, 0x0U, 0x020E0380U +#define IOMUXC_ENET2_TX_EN_ENET2_TX_EN 0x020E00F8U, 0x0U, 0x00000000U, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_UART8_RX 0x020E00F8U, 0x1U, 0x020E065CU, 0x1U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_UART8_TX 0x020E00F8U, 0x1U, 0x00000000U, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_ECSPI4_MOSI 0x020E00F8U, 0x3U, 0x020E056CU, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_EIM_ACLK_FREERUN 0x020E00F8U, 0x4U, 0x00000000U, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_GPIO2_IO13 0x020E00F8U, 0x5U, 0x00000000U, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_KPP_COL06 0x020E00F8U, 0x6U, 0x00000000U, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_USB_OTG2_OC 0x020E00F8U, 0x8U, 0x020E0660U, 0x1U, 0x020E0384U +#define IOMUXC_ENET2_TX_EN_EPDC_SDDO13 0x020E00F8U, 0x9U, 0x00000000U, 0x0U, 0x020E0384U +#define IOMUXC_ENET2_TX_CLK_ENET2_TX_CLK 0x020E00FCU, 0x0U, 0x00000000U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_UART8_CTS_B 0x020E00FCU, 0x1U, 0x00000000U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_UART8_RTS_B 0x020E00FCU, 0x1U, 0x020E0658U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_ECSPI4_MISO 0x020E00FCU, 0x3U, 0x020E0568U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_ENET2_REF_CLK2 0x020E00FCU, 0x4U, 0x020E057CU, 0x2U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_GPIO2_IO14 0x020E00FCU, 0x5U, 0x00000000U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_KPP_ROW07 0x020E00FCU, 0x6U, 0x00000000U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_ANATOP_OTG2_ID 0x020E00FCU, 0x8U, 0x020E04BCU, 0x1U, 0x020E0388U +#define IOMUXC_ENET2_TX_CLK_EPDC_SDDO14 0x020E00FCU, 0x9U, 0x00000000U, 0x0U, 0x020E0388U +#define IOMUXC_ENET2_RX_ER_ENET2_RX_ER 0x020E0100U, 0x0U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_UART8_RTS_B 0x020E0100U, 0x1U, 0x020E0658U, 0x1U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_UART8_CTS_B 0x020E0100U, 0x1U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_ECSPI4_SS0 0x020E0100U, 0x3U, 0x020E0570U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_EIM_ADDR25 0x020E0100U, 0x4U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_GPIO2_IO15 0x020E0100U, 0x5U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_KPP_COL07 0x020E0100U, 0x6U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_WDOG1_WDOG_ANY 0x020E0100U, 0x8U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_ENET2_RX_ER_EPDC_SDDO15 0x020E0100U, 0x9U, 0x00000000U, 0x0U, 0x020E038CU +#define IOMUXC_LCD_CLK_LCDIF_CLK 0x020E0104U, 0x0U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_LCDIF_WR_RWN 0x020E0104U, 0x1U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_UART4_TX 0x020E0104U, 0x2U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_UART4_RX 0x020E0104U, 0x2U, 0x020E063CU, 0x2U, 0x020E0390U +#define IOMUXC_LCD_CLK_SAI3_MCLK 0x020E0104U, 0x3U, 0x020E0600U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_EIM_CS2_B 0x020E0104U, 0x4U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_GPIO3_IO00 0x020E0104U, 0x5U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_WDOG1_WDOG_RST_B_DEB 0x020E0104U, 0x8U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_CLK_EPDC_SDCLK 0x020E0104U, 0x9U, 0x00000000U, 0x0U, 0x020E0390U +#define IOMUXC_LCD_ENABLE_LCDIF_ENABLE 0x020E0108U, 0x0U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_LCDIF_RD_E 0x020E0108U, 0x1U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_UART4_RX 0x020E0108U, 0x2U, 0x020E063CU, 0x3U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_UART4_TX 0x020E0108U, 0x2U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_SAI3_TX_SYNC 0x020E0108U, 0x3U, 0x020E060CU, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_EIM_CS3_B 0x020E0108U, 0x4U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_GPIO3_IO01 0x020E0108U, 0x5U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_ECSPI2_RDY 0x020E0108U, 0x8U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_ENABLE_EPDC_SDLE 0x020E0108U, 0x9U, 0x00000000U, 0x0U, 0x020E0394U +#define IOMUXC_LCD_HSYNC_LCDIF_HSYNC 0x020E010CU, 0x0U, 0x020E05DCU, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_LCDIF_RS 0x020E010CU, 0x1U, 0x00000000U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_UART4_CTS_B 0x020E010CU, 0x2U, 0x00000000U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_UART4_RTS_B 0x020E010CU, 0x2U, 0x020E0638U, 0x2U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_SAI3_TX_BCLK 0x020E010CU, 0x3U, 0x020E0608U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_WDOG3_WDOG_RST_B_DEB 0x020E010CU, 0x4U, 0x00000000U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_GPIO3_IO02 0x020E010CU, 0x5U, 0x00000000U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_ECSPI2_SS1 0x020E010CU, 0x8U, 0x00000000U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_HSYNC_EPDC_SDOE 0x020E010CU, 0x9U, 0x00000000U, 0x0U, 0x020E0398U +#define IOMUXC_LCD_VSYNC_LCDIF_VSYNC 0x020E0110U, 0x0U, 0x00000000U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_LCDIF_BUSY 0x020E0110U, 0x1U, 0x020E05DCU, 0x1U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_UART4_RTS_B 0x020E0110U, 0x2U, 0x020E0638U, 0x3U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_UART4_CTS_B 0x020E0110U, 0x2U, 0x00000000U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_SAI3_RX_DATA 0x020E0110U, 0x3U, 0x020E0604U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_WDOG2_WDOG_B 0x020E0110U, 0x4U, 0x00000000U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_GPIO3_IO03 0x020E0110U, 0x5U, 0x00000000U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_ECSPI2_SS2 0x020E0110U, 0x8U, 0x00000000U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_VSYNC_EPDC_SDCE00 0x020E0110U, 0x9U, 0x00000000U, 0x0U, 0x020E039CU +#define IOMUXC_LCD_RESET_LCDIF_RESET 0x020E0114U, 0x0U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_LCDIF_CS 0x020E0114U, 0x1U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_CA7_MX6ULL_EVENTI 0x020E0114U, 0x2U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_SAI3_TX_DATA 0x020E0114U, 0x3U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_WDOG1_WDOG_ANY 0x020E0114U, 0x4U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_GPIO3_IO04 0x020E0114U, 0x5U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_ECSPI2_SS3 0x020E0114U, 0x8U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_RESET_EPDC_GDOE 0x020E0114U, 0x9U, 0x00000000U, 0x0U, 0x020E03A0U +#define IOMUXC_LCD_DATA00_LCDIF_DATA00 0x020E0118U, 0x0U, 0x00000000U, 0x0U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_PWM1_OUT 0x020E0118U, 0x1U, 0x00000000U, 0x0U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_ENET1_1588_EVENT2_IN 0x020E0118U, 0x3U, 0x00000000U, 0x0U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_I2C3_SDA 0x020E0118U, 0x4U, 0x020E05B8U, 0x2U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_GPIO3_IO05 0x020E0118U, 0x5U, 0x00000000U, 0x0U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_SRC_BT_CFG00 0x020E0118U, 0x6U, 0x00000000U, 0x0U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_SAI1_MCLK 0x020E0118U, 0x8U, 0x020E05E0U, 0x1U, 0x020E03A4U +#define IOMUXC_LCD_DATA00_EPDC_SDDO00 0x020E0118U, 0x9U, 0x00000000U, 0x0U, 0x020E03A4U +#define IOMUXC_LCD_DATA01_LCDIF_DATA01 0x020E011CU, 0x0U, 0x00000000U, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_PWM2_OUT 0x020E011CU, 0x1U, 0x00000000U, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_ENET1_1588_EVENT2_OUT 0x020E011CU, 0x3U, 0x00000000U, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_I2C3_SCL 0x020E011CU, 0x4U, 0x020E05B4U, 0x2U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_GPIO3_IO06 0x020E011CU, 0x5U, 0x00000000U, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_SRC_BT_CFG01 0x020E011CU, 0x6U, 0x00000000U, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_SAI1_TX_SYNC 0x020E011CU, 0x8U, 0x020E05ECU, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA01_EPDC_SDDO01 0x020E011CU, 0x9U, 0x00000000U, 0x0U, 0x020E03A8U +#define IOMUXC_LCD_DATA02_LCDIF_DATA02 0x020E0120U, 0x0U, 0x00000000U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_PWM3_OUT 0x020E0120U, 0x1U, 0x00000000U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_ENET1_1588_EVENT3_IN 0x020E0120U, 0x3U, 0x00000000U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_I2C4_SDA 0x020E0120U, 0x4U, 0x020E05C0U, 0x2U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_GPIO3_IO07 0x020E0120U, 0x5U, 0x00000000U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_SRC_BT_CFG02 0x020E0120U, 0x6U, 0x00000000U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_SAI1_TX_BCLK 0x020E0120U, 0x8U, 0x020E05E8U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA02_EPDC_SDDO02 0x020E0120U, 0x9U, 0x00000000U, 0x0U, 0x020E03ACU +#define IOMUXC_LCD_DATA03_LCDIF_DATA03 0x020E0124U, 0x0U, 0x00000000U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_PWM4_OUT 0x020E0124U, 0x1U, 0x00000000U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_ENET1_1588_EVENT3_OUT 0x020E0124U, 0x3U, 0x00000000U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_I2C4_SCL 0x020E0124U, 0x4U, 0x020E05BCU, 0x2U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_GPIO3_IO08 0x020E0124U, 0x5U, 0x00000000U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_SRC_BT_CFG03 0x020E0124U, 0x6U, 0x00000000U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_SAI1_RX_DATA 0x020E0124U, 0x8U, 0x020E05E4U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA03_EPDC_SDDO03 0x020E0124U, 0x9U, 0x00000000U, 0x0U, 0x020E03B0U +#define IOMUXC_LCD_DATA04_LCDIF_DATA04 0x020E0128U, 0x0U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_UART8_CTS_B 0x020E0128U, 0x1U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_UART8_RTS_B 0x020E0128U, 0x1U, 0x020E0658U, 0x2U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_ENET2_1588_EVENT2_IN 0x020E0128U, 0x3U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_SPDIF_SR_CLK 0x020E0128U, 0x4U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_GPIO3_IO09 0x020E0128U, 0x5U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_SRC_BT_CFG04 0x020E0128U, 0x6U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_SAI1_TX_DATA 0x020E0128U, 0x8U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA04_EPDC_SDDO04 0x020E0128U, 0x9U, 0x00000000U, 0x0U, 0x020E03B4U +#define IOMUXC_LCD_DATA05_LCDIF_DATA05 0x020E012CU, 0x0U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_UART8_RTS_B 0x020E012CU, 0x1U, 0x020E0658U, 0x3U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_UART8_CTS_B 0x020E012CU, 0x1U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_ENET2_1588_EVENT2_OUT 0x020E012CU, 0x3U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_SPDIF_OUT 0x020E012CU, 0x4U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_GPIO3_IO10 0x020E012CU, 0x5U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_SRC_BT_CFG05 0x020E012CU, 0x6U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_ECSPI1_SS1 0x020E012CU, 0x8U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA05_EPDC_SDDO05 0x020E012CU, 0x9U, 0x00000000U, 0x0U, 0x020E03B8U +#define IOMUXC_LCD_DATA06_LCDIF_DATA06 0x020E0130U, 0x0U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_UART7_CTS_B 0x020E0130U, 0x1U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_UART7_RTS_B 0x020E0130U, 0x1U, 0x020E0650U, 0x2U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_ENET2_1588_EVENT3_IN 0x020E0130U, 0x3U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_SPDIF_LOCK 0x020E0130U, 0x4U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_GPIO3_IO11 0x020E0130U, 0x5U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_SRC_BT_CFG06 0x020E0130U, 0x6U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_ECSPI1_SS2 0x020E0130U, 0x8U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA06_EPDC_SDDO06 0x020E0130U, 0x9U, 0x00000000U, 0x0U, 0x020E03BCU +#define IOMUXC_LCD_DATA07_LCDIF_DATA07 0x020E0134U, 0x0U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_UART7_RTS_B 0x020E0134U, 0x1U, 0x020E0650U, 0x3U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_UART7_CTS_B 0x020E0134U, 0x1U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_ENET2_1588_EVENT3_OUT 0x020E0134U, 0x3U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_SPDIF_EXT_CLK 0x020E0134U, 0x4U, 0x020E061CU, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_GPIO3_IO12 0x020E0134U, 0x5U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_SRC_BT_CFG07 0x020E0134U, 0x6U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_ECSPI1_SS3 0x020E0134U, 0x8U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA07_EPDC_SDDO07 0x020E0134U, 0x9U, 0x00000000U, 0x0U, 0x020E03C0U +#define IOMUXC_LCD_DATA08_LCDIF_DATA08 0x020E0138U, 0x0U, 0x00000000U, 0x0U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_SPDIF_IN 0x020E0138U, 0x1U, 0x020E0618U, 0x2U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_CSI_DATA16 0x020E0138U, 0x3U, 0x020E0504U, 0x1U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_EIM_DATA00 0x020E0138U, 0x4U, 0x00000000U, 0x0U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_GPIO3_IO13 0x020E0138U, 0x5U, 0x00000000U, 0x0U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_SRC_BT_CFG08 0x020E0138U, 0x6U, 0x00000000U, 0x0U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_FLEXCAN1_TX 0x020E0138U, 0x8U, 0x00000000U, 0x0U, 0x020E03C4U +#define IOMUXC_LCD_DATA08_EPDC_PWRIRQ 0x020E0138U, 0x9U, 0x00000000U, 0x0U, 0x020E03C4U +#define IOMUXC_LCD_DATA09_LCDIF_DATA09 0x020E013CU, 0x0U, 0x00000000U, 0x0U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_SAI3_MCLK 0x020E013CU, 0x1U, 0x020E0600U, 0x1U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_CSI_DATA17 0x020E013CU, 0x3U, 0x020E0508U, 0x1U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_EIM_DATA01 0x020E013CU, 0x4U, 0x00000000U, 0x0U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_GPIO3_IO14 0x020E013CU, 0x5U, 0x00000000U, 0x0U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_SRC_BT_CFG09 0x020E013CU, 0x6U, 0x00000000U, 0x0U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_FLEXCAN1_RX 0x020E013CU, 0x8U, 0x020E0584U, 0x2U, 0x020E03C8U +#define IOMUXC_LCD_DATA09_EPDC_PWRWAKE 0x020E013CU, 0x9U, 0x00000000U, 0x0U, 0x020E03C8U +#define IOMUXC_LCD_DATA10_LCDIF_DATA10 0x020E0140U, 0x0U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_SAI3_RX_SYNC 0x020E0140U, 0x1U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_CSI_DATA18 0x020E0140U, 0x3U, 0x020E050CU, 0x1U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_EIM_DATA02 0x020E0140U, 0x4U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_GPIO3_IO15 0x020E0140U, 0x5U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_SRC_BT_CFG10 0x020E0140U, 0x6U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_FLEXCAN2_TX 0x020E0140U, 0x8U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA10_EPDC_PWRCOM 0x020E0140U, 0x9U, 0x00000000U, 0x0U, 0x020E03CCU +#define IOMUXC_LCD_DATA11_LCDIF_DATA11 0x020E0144U, 0x0U, 0x00000000U, 0x0U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_SAI3_RX_BCLK 0x020E0144U, 0x1U, 0x00000000U, 0x0U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_CSI_DATA19 0x020E0144U, 0x3U, 0x020E0510U, 0x1U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_EIM_DATA03 0x020E0144U, 0x4U, 0x00000000U, 0x0U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_GPIO3_IO16 0x020E0144U, 0x5U, 0x00000000U, 0x0U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_SRC_BT_CFG11 0x020E0144U, 0x6U, 0x00000000U, 0x0U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_FLEXCAN2_RX 0x020E0144U, 0x8U, 0x020E0588U, 0x2U, 0x020E03D0U +#define IOMUXC_LCD_DATA11_EPDC_PWRSTAT 0x020E0144U, 0x9U, 0x00000000U, 0x0U, 0x020E03D0U +#define IOMUXC_LCD_DATA12_LCDIF_DATA12 0x020E0148U, 0x0U, 0x00000000U, 0x0U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_SAI3_TX_SYNC 0x020E0148U, 0x1U, 0x020E060CU, 0x1U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_CSI_DATA20 0x020E0148U, 0x3U, 0x020E0514U, 0x1U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_EIM_DATA04 0x020E0148U, 0x4U, 0x00000000U, 0x0U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_GPIO3_IO17 0x020E0148U, 0x5U, 0x00000000U, 0x0U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_SRC_BT_CFG12 0x020E0148U, 0x6U, 0x00000000U, 0x0U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_ECSPI1_RDY 0x020E0148U, 0x8U, 0x00000000U, 0x0U, 0x020E03D4U +#define IOMUXC_LCD_DATA12_EPDC_PWRCTRL00 0x020E0148U, 0x9U, 0x00000000U, 0x0U, 0x020E03D4U +#define IOMUXC_LCD_DATA13_LCDIF_DATA13 0x020E014CU, 0x0U, 0x00000000U, 0x0U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_SAI3_TX_BCLK 0x020E014CU, 0x1U, 0x020E0608U, 0x1U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_CSI_DATA21 0x020E014CU, 0x3U, 0x020E0518U, 0x1U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_EIM_DATA05 0x020E014CU, 0x4U, 0x00000000U, 0x0U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_GPIO3_IO18 0x020E014CU, 0x5U, 0x00000000U, 0x0U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_SRC_BT_CFG13 0x020E014CU, 0x6U, 0x00000000U, 0x0U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_USDHC2_RESET_B 0x020E014CU, 0x8U, 0x00000000U, 0x0U, 0x020E03D8U +#define IOMUXC_LCD_DATA13_EPDC_BDR00 0x020E014CU, 0x9U, 0x00000000U, 0x0U, 0x020E03D8U +#define IOMUXC_LCD_DATA14_LCDIF_DATA14 0x020E0150U, 0x0U, 0x00000000U, 0x0U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_SAI3_RX_DATA 0x020E0150U, 0x1U, 0x020E0604U, 0x1U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_CSI_DATA22 0x020E0150U, 0x3U, 0x020E051CU, 0x1U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_EIM_DATA06 0x020E0150U, 0x4U, 0x00000000U, 0x0U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_GPIO3_IO19 0x020E0150U, 0x5U, 0x00000000U, 0x0U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_SRC_BT_CFG14 0x020E0150U, 0x6U, 0x00000000U, 0x0U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_USDHC2_DATA4 0x020E0150U, 0x8U, 0x020E068CU, 0x0U, 0x020E03DCU +#define IOMUXC_LCD_DATA14_EPDC_SDSHR 0x020E0150U, 0x9U, 0x00000000U, 0x0U, 0x020E03DCU +#define IOMUXC_LCD_DATA15_LCDIF_DATA15 0x020E0154U, 0x0U, 0x00000000U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_SAI3_TX_DATA 0x020E0154U, 0x1U, 0x00000000U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_CSI_DATA23 0x020E0154U, 0x3U, 0x020E0520U, 0x1U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_EIM_DATA07 0x020E0154U, 0x4U, 0x00000000U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_GPIO3_IO20 0x020E0154U, 0x5U, 0x00000000U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_SRC_BT_CFG15 0x020E0154U, 0x6U, 0x00000000U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_USDHC2_DATA5 0x020E0154U, 0x8U, 0x020E0690U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA15_EPDC_GDRL 0x020E0154U, 0x9U, 0x00000000U, 0x0U, 0x020E03E0U +#define IOMUXC_LCD_DATA16_LCDIF_DATA16 0x020E0158U, 0x0U, 0x00000000U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_UART7_TX 0x020E0158U, 0x1U, 0x00000000U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_UART7_RX 0x020E0158U, 0x1U, 0x020E0654U, 0x2U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_CSI_DATA01 0x020E0158U, 0x3U, 0x020E04D4U, 0x1U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_EIM_DATA08 0x020E0158U, 0x4U, 0x00000000U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_GPIO3_IO21 0x020E0158U, 0x5U, 0x00000000U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_SRC_BT_CFG24 0x020E0158U, 0x6U, 0x00000000U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_USDHC2_DATA6 0x020E0158U, 0x8U, 0x020E0694U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA16_EPDC_GDCLK 0x020E0158U, 0x9U, 0x00000000U, 0x0U, 0x020E03E4U +#define IOMUXC_LCD_DATA17_LCDIF_DATA17 0x020E015CU, 0x0U, 0x00000000U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_UART7_RX 0x020E015CU, 0x1U, 0x020E0654U, 0x3U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_UART7_TX 0x020E015CU, 0x1U, 0x00000000U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_CSI_DATA00 0x020E015CU, 0x3U, 0x020E04D0U, 0x1U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_EIM_DATA09 0x020E015CU, 0x4U, 0x00000000U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_GPIO3_IO22 0x020E015CU, 0x5U, 0x00000000U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_SRC_BT_CFG25 0x020E015CU, 0x6U, 0x00000000U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_USDHC2_DATA7 0x020E015CU, 0x8U, 0x020E0698U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA17_EPDC_GDSP 0x020E015CU, 0x9U, 0x00000000U, 0x0U, 0x020E03E8U +#define IOMUXC_LCD_DATA18_LCDIF_DATA18 0x020E0160U, 0x0U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_PWM5_OUT 0x020E0160U, 0x1U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_CA7_MX6ULL_EVENTO 0x020E0160U, 0x2U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_CSI_DATA10 0x020E0160U, 0x3U, 0x020E04ECU, 0x1U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_EIM_DATA10 0x020E0160U, 0x4U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_GPIO3_IO23 0x020E0160U, 0x5U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_SRC_BT_CFG26 0x020E0160U, 0x6U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_USDHC2_CMD 0x020E0160U, 0x8U, 0x020E0678U, 0x1U, 0x020E03ECU +#define IOMUXC_LCD_DATA18_EPDC_BDR01 0x020E0160U, 0x9U, 0x00000000U, 0x0U, 0x020E03ECU +#define IOMUXC_LCD_DATA19_EIM_DATA11 0x020E0164U, 0x4U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_GPIO3_IO24 0x020E0164U, 0x5U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_SRC_BT_CFG27 0x020E0164U, 0x6U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_USDHC2_CLK 0x020E0164U, 0x8U, 0x020E0670U, 0x1U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_EPDC_VCOM00 0x020E0164U, 0x9U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_LCDIF_DATA19 0x020E0164U, 0x0U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_PWM6_OUT 0x020E0164U, 0x1U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_WDOG1_WDOG_ANY 0x020E0164U, 0x2U, 0x00000000U, 0x0U, 0x020E03F0U +#define IOMUXC_LCD_DATA19_CSI_DATA11 0x020E0164U, 0x3U, 0x020E04F0U, 0x1U, 0x020E03F0U +#define IOMUXC_LCD_DATA20_EIM_DATA12 0x020E0168U, 0x4U, 0x00000000U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_GPIO3_IO25 0x020E0168U, 0x5U, 0x00000000U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_SRC_BT_CFG28 0x020E0168U, 0x6U, 0x00000000U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_USDHC2_DATA0 0x020E0168U, 0x8U, 0x020E067CU, 0x1U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_EPDC_VCOM01 0x020E0168U, 0x9U, 0x00000000U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_LCDIF_DATA20 0x020E0168U, 0x0U, 0x00000000U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_UART8_TX 0x020E0168U, 0x1U, 0x00000000U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_UART8_RX 0x020E0168U, 0x1U, 0x020E065CU, 0x2U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_ECSPI1_SCLK 0x020E0168U, 0x2U, 0x020E0534U, 0x0U, 0x020E03F4U +#define IOMUXC_LCD_DATA20_CSI_DATA12 0x020E0168U, 0x3U, 0x020E04F4U, 0x1U, 0x020E03F4U +#define IOMUXC_LCD_DATA21_LCDIF_DATA21 0x020E016CU, 0x0U, 0x00000000U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_UART8_RX 0x020E016CU, 0x1U, 0x020E065CU, 0x3U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_UART8_TX 0x020E016CU, 0x1U, 0x00000000U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_ECSPI1_SS0 0x020E016CU, 0x2U, 0x020E0540U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_CSI_DATA13 0x020E016CU, 0x3U, 0x020E04F8U, 0x1U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_EIM_DATA13 0x020E016CU, 0x4U, 0x00000000U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_GPIO3_IO26 0x020E016CU, 0x5U, 0x00000000U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_SRC_BT_CFG29 0x020E016CU, 0x6U, 0x00000000U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_USDHC2_DATA1 0x020E016CU, 0x8U, 0x020E0680U, 0x1U, 0x020E03F8U +#define IOMUXC_LCD_DATA21_EPDC_SDCE01 0x020E016CU, 0x9U, 0x00000000U, 0x0U, 0x020E03F8U +#define IOMUXC_LCD_DATA22_LCDIF_DATA22 0x020E0170U, 0x0U, 0x00000000U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_MQS_RIGHT 0x020E0170U, 0x1U, 0x00000000U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_ECSPI1_MOSI 0x020E0170U, 0x2U, 0x020E053CU, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_CSI_DATA14 0x020E0170U, 0x3U, 0x020E04FCU, 0x1U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_EIM_DATA14 0x020E0170U, 0x4U, 0x00000000U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_GPIO3_IO27 0x020E0170U, 0x5U, 0x00000000U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_SRC_BT_CFG30 0x020E0170U, 0x6U, 0x00000000U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_USDHC2_DATA2 0x020E0170U, 0x8U, 0x020E0684U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA22_EPDC_SDCE02 0x020E0170U, 0x9U, 0x00000000U, 0x0U, 0x020E03FCU +#define IOMUXC_LCD_DATA23_EPDC_SDCE03 0x020E0174U, 0x9U, 0x00000000U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_LCDIF_DATA23 0x020E0174U, 0x0U, 0x00000000U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_MQS_LEFT 0x020E0174U, 0x1U, 0x00000000U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_ECSPI1_MISO 0x020E0174U, 0x2U, 0x020E0538U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_CSI_DATA15 0x020E0174U, 0x3U, 0x020E0500U, 0x1U, 0x020E0400U +#define IOMUXC_LCD_DATA23_EIM_DATA15 0x020E0174U, 0x4U, 0x00000000U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_GPIO3_IO28 0x020E0174U, 0x5U, 0x00000000U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_SRC_BT_CFG31 0x020E0174U, 0x6U, 0x00000000U, 0x0U, 0x020E0400U +#define IOMUXC_LCD_DATA23_USDHC2_DATA3 0x020E0174U, 0x8U, 0x020E0688U, 0x1U, 0x020E0400U +#define IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x020E0178U, 0x0U, 0x00000000U, 0x0U, 0x020E0404U +#define IOMUXC_NAND_RE_B_USDHC2_CLK 0x020E0178U, 0x1U, 0x020E0670U, 0x2U, 0x020E0404U +#define IOMUXC_NAND_RE_B_QSPI_B_SCLK 0x020E0178U, 0x2U, 0x00000000U, 0x0U, 0x020E0404U +#define IOMUXC_NAND_RE_B_KPP_ROW00 0x020E0178U, 0x3U, 0x020E05D0U, 0x1U, 0x020E0404U +#define IOMUXC_NAND_RE_B_EIM_EB_B00 0x020E0178U, 0x4U, 0x00000000U, 0x0U, 0x020E0404U +#define IOMUXC_NAND_RE_B_GPIO4_IO00 0x020E0178U, 0x5U, 0x00000000U, 0x0U, 0x020E0404U +#define IOMUXC_NAND_RE_B_ECSPI3_SS2 0x020E0178U, 0x8U, 0x00000000U, 0x0U, 0x020E0404U +#define IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x020E017CU, 0x0U, 0x00000000U, 0x0U, 0x020E0408U +#define IOMUXC_NAND_WE_B_USDHC2_CMD 0x020E017CU, 0x1U, 0x020E0678U, 0x2U, 0x020E0408U +#define IOMUXC_NAND_WE_B_QSPI_B_SS0_B 0x020E017CU, 0x2U, 0x00000000U, 0x0U, 0x020E0408U +#define IOMUXC_NAND_WE_B_KPP_COL00 0x020E017CU, 0x3U, 0x020E05C4U, 0x1U, 0x020E0408U +#define IOMUXC_NAND_WE_B_EIM_EB_B01 0x020E017CU, 0x4U, 0x00000000U, 0x0U, 0x020E0408U +#define IOMUXC_NAND_WE_B_GPIO4_IO01 0x020E017CU, 0x5U, 0x00000000U, 0x0U, 0x020E0408U +#define IOMUXC_NAND_WE_B_ECSPI3_SS3 0x020E017CU, 0x8U, 0x00000000U, 0x0U, 0x020E0408U +#define IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x020E0180U, 0x0U, 0x00000000U, 0x0U, 0x020E040CU +#define IOMUXC_NAND_DATA00_USDHC2_DATA0 0x020E0180U, 0x1U, 0x020E067CU, 0x2U, 0x020E040CU +#define IOMUXC_NAND_DATA00_QSPI_B_SS1_B 0x020E0180U, 0x2U, 0x00000000U, 0x0U, 0x020E040CU +#define IOMUXC_NAND_DATA00_KPP_ROW01 0x020E0180U, 0x3U, 0x020E05D4U, 0x1U, 0x020E040CU +#define IOMUXC_NAND_DATA00_EIM_AD08 0x020E0180U, 0x4U, 0x00000000U, 0x0U, 0x020E040CU +#define IOMUXC_NAND_DATA00_GPIO4_IO02 0x020E0180U, 0x5U, 0x00000000U, 0x0U, 0x020E040CU +#define IOMUXC_NAND_DATA00_ECSPI4_RDY 0x020E0180U, 0x8U, 0x00000000U, 0x0U, 0x020E040CU +#define IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x020E0184U, 0x0U, 0x00000000U, 0x0U, 0x020E0410U +#define IOMUXC_NAND_DATA01_USDHC2_DATA1 0x020E0184U, 0x1U, 0x020E0680U, 0x2U, 0x020E0410U +#define IOMUXC_NAND_DATA01_QSPI_B_DQS 0x020E0184U, 0x2U, 0x00000000U, 0x0U, 0x020E0410U +#define IOMUXC_NAND_DATA01_KPP_COL01 0x020E0184U, 0x3U, 0x020E05C8U, 0x1U, 0x020E0410U +#define IOMUXC_NAND_DATA01_EIM_AD09 0x020E0184U, 0x4U, 0x00000000U, 0x0U, 0x020E0410U +#define IOMUXC_NAND_DATA01_GPIO4_IO03 0x020E0184U, 0x5U, 0x00000000U, 0x0U, 0x020E0410U +#define IOMUXC_NAND_DATA01_ECSPI4_SS1 0x020E0184U, 0x8U, 0x00000000U, 0x0U, 0x020E0410U +#define IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x020E0188U, 0x0U, 0x00000000U, 0x0U, 0x020E0414U +#define IOMUXC_NAND_DATA02_USDHC2_DATA2 0x020E0188U, 0x1U, 0x020E0684U, 0x1U, 0x020E0414U +#define IOMUXC_NAND_DATA02_QSPI_B_DATA00 0x020E0188U, 0x2U, 0x00000000U, 0x0U, 0x020E0414U +#define IOMUXC_NAND_DATA02_KPP_ROW02 0x020E0188U, 0x3U, 0x020E05D8U, 0x1U, 0x020E0414U +#define IOMUXC_NAND_DATA02_EIM_AD10 0x020E0188U, 0x4U, 0x00000000U, 0x0U, 0x020E0414U +#define IOMUXC_NAND_DATA02_GPIO4_IO04 0x020E0188U, 0x5U, 0x00000000U, 0x0U, 0x020E0414U +#define IOMUXC_NAND_DATA02_ECSPI4_SS2 0x020E0188U, 0x8U, 0x00000000U, 0x0U, 0x020E0414U +#define IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x020E018CU, 0x0U, 0x00000000U, 0x0U, 0x020E0418U +#define IOMUXC_NAND_DATA03_USDHC2_DATA3 0x020E018CU, 0x1U, 0x020E0688U, 0x2U, 0x020E0418U +#define IOMUXC_NAND_DATA03_QSPI_B_DATA01 0x020E018CU, 0x2U, 0x00000000U, 0x0U, 0x020E0418U +#define IOMUXC_NAND_DATA03_KPP_COL02 0x020E018CU, 0x3U, 0x020E05CCU, 0x1U, 0x020E0418U +#define IOMUXC_NAND_DATA03_EIM_AD11 0x020E018CU, 0x4U, 0x00000000U, 0x0U, 0x020E0418U +#define IOMUXC_NAND_DATA03_GPIO4_IO05 0x020E018CU, 0x5U, 0x00000000U, 0x0U, 0x020E0418U +#define IOMUXC_NAND_DATA03_ECSPI4_SS3 0x020E018CU, 0x8U, 0x00000000U, 0x0U, 0x020E0418U +#define IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x020E0190U, 0x0U, 0x00000000U, 0x0U, 0x020E041CU +#define IOMUXC_NAND_DATA04_USDHC2_DATA4 0x020E0190U, 0x1U, 0x020E068CU, 0x1U, 0x020E041CU +#define IOMUXC_NAND_DATA04_QSPI_B_DATA02 0x020E0190U, 0x2U, 0x00000000U, 0x0U, 0x020E041CU +#define IOMUXC_NAND_DATA04_ECSPI4_SCLK 0x020E0190U, 0x3U, 0x020E0564U, 0x1U, 0x020E041CU +#define IOMUXC_NAND_DATA04_EIM_AD12 0x020E0190U, 0x4U, 0x00000000U, 0x0U, 0x020E041CU +#define IOMUXC_NAND_DATA04_GPIO4_IO06 0x020E0190U, 0x5U, 0x00000000U, 0x0U, 0x020E041CU +#define IOMUXC_NAND_DATA04_UART2_TX 0x020E0190U, 0x8U, 0x00000000U, 0x0U, 0x020E041CU +#define IOMUXC_NAND_DATA04_UART2_RX 0x020E0190U, 0x8U, 0x020E062CU, 0x2U, 0x020E041CU +#define IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x020E0194U, 0x0U, 0x00000000U, 0x0U, 0x020E0420U +#define IOMUXC_NAND_DATA05_USDHC2_DATA5 0x020E0194U, 0x1U, 0x020E0690U, 0x1U, 0x020E0420U +#define IOMUXC_NAND_DATA05_QSPI_B_DATA03 0x020E0194U, 0x2U, 0x00000000U, 0x0U, 0x020E0420U +#define IOMUXC_NAND_DATA05_ECSPI4_MOSI 0x020E0194U, 0x3U, 0x020E056CU, 0x1U, 0x020E0420U +#define IOMUXC_NAND_DATA05_EIM_AD13 0x020E0194U, 0x4U, 0x00000000U, 0x0U, 0x020E0420U +#define IOMUXC_NAND_DATA05_GPIO4_IO07 0x020E0194U, 0x5U, 0x00000000U, 0x0U, 0x020E0420U +#define IOMUXC_NAND_DATA05_UART2_RX 0x020E0194U, 0x8U, 0x020E062CU, 0x3U, 0x020E0420U +#define IOMUXC_NAND_DATA05_UART2_TX 0x020E0194U, 0x8U, 0x00000000U, 0x0U, 0x020E0420U +#define IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x020E0198U, 0x0U, 0x00000000U, 0x0U, 0x020E0424U +#define IOMUXC_NAND_DATA06_USDHC2_DATA6 0x020E0198U, 0x1U, 0x020E0694U, 0x1U, 0x020E0424U +#define IOMUXC_NAND_DATA06_SAI2_RX_BCLK 0x020E0198U, 0x2U, 0x00000000U, 0x0U, 0x020E0424U +#define IOMUXC_NAND_DATA06_ECSPI4_MISO 0x020E0198U, 0x3U, 0x020E0568U, 0x1U, 0x020E0424U +#define IOMUXC_NAND_DATA06_EIM_AD14 0x020E0198U, 0x4U, 0x00000000U, 0x0U, 0x020E0424U +#define IOMUXC_NAND_DATA06_GPIO4_IO08 0x020E0198U, 0x5U, 0x00000000U, 0x0U, 0x020E0424U +#define IOMUXC_NAND_DATA06_UART2_CTS_B 0x020E0198U, 0x8U, 0x00000000U, 0x0U, 0x020E0424U +#define IOMUXC_NAND_DATA06_UART2_RTS_B 0x020E0198U, 0x8U, 0x020E0628U, 0x4U, 0x020E0424U +#define IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x020E019CU, 0x0U, 0x00000000U, 0x0U, 0x020E0428U +#define IOMUXC_NAND_DATA07_USDHC2_DATA7 0x020E019CU, 0x1U, 0x020E0698U, 0x1U, 0x020E0428U +#define IOMUXC_NAND_DATA07_QSPI_A_SS1_B 0x020E019CU, 0x2U, 0x00000000U, 0x0U, 0x020E0428U +#define IOMUXC_NAND_DATA07_ECSPI4_SS0 0x020E019CU, 0x3U, 0x020E0570U, 0x1U, 0x020E0428U +#define IOMUXC_NAND_DATA07_EIM_AD15 0x020E019CU, 0x4U, 0x00000000U, 0x0U, 0x020E0428U +#define IOMUXC_NAND_DATA07_GPIO4_IO09 0x020E019CU, 0x5U, 0x00000000U, 0x0U, 0x020E0428U +#define IOMUXC_NAND_DATA07_UART2_RTS_B 0x020E019CU, 0x8U, 0x020E0628U, 0x5U, 0x020E0428U +#define IOMUXC_NAND_DATA07_UART2_CTS_B 0x020E019CU, 0x8U, 0x00000000U, 0x0U, 0x020E0428U +#define IOMUXC_NAND_ALE_RAWNAND_ALE 0x020E01A0U, 0x0U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_ALE_USDHC2_RESET_B 0x020E01A0U, 0x1U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_ALE_QSPI_A_DQS 0x020E01A0U, 0x2U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_ALE_PWM3_OUT 0x020E01A0U, 0x3U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_ALE_EIM_ADDR17 0x020E01A0U, 0x4U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_ALE_GPIO4_IO10 0x020E01A0U, 0x5U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_ALE_ECSPI3_SS1 0x020E01A0U, 0x8U, 0x00000000U, 0x0U, 0x020E042CU +#define IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x020E01A4U, 0x0U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_WP_B_USDHC1_RESET_B 0x020E01A4U, 0x1U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_WP_B_QSPI_A_SCLK 0x020E01A4U, 0x2U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_WP_B_PWM4_OUT 0x020E01A4U, 0x3U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_WP_B_EIM_BCLK 0x020E01A4U, 0x4U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_WP_B_GPIO4_IO11 0x020E01A4U, 0x5U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_WP_B_ECSPI3_RDY 0x020E01A4U, 0x8U, 0x00000000U, 0x0U, 0x020E0430U +#define IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x020E01A8U, 0x0U, 0x00000000U, 0x0U, 0x020E0434U +#define IOMUXC_NAND_READY_B_USDHC1_DATA4 0x020E01A8U, 0x1U, 0x00000000U, 0x0U, 0x020E0434U +#define IOMUXC_NAND_READY_B_QSPI_A_DATA00 0x020E01A8U, 0x2U, 0x00000000U, 0x0U, 0x020E0434U +#define IOMUXC_NAND_READY_B_ECSPI3_SS0 0x020E01A8U, 0x3U, 0x020E0560U, 0x1U, 0x020E0434U +#define IOMUXC_NAND_READY_B_EIM_CS1_B 0x020E01A8U, 0x4U, 0x00000000U, 0x0U, 0x020E0434U +#define IOMUXC_NAND_READY_B_GPIO4_IO12 0x020E01A8U, 0x5U, 0x00000000U, 0x0U, 0x020E0434U +#define IOMUXC_NAND_READY_B_UART3_TX 0x020E01A8U, 0x8U, 0x00000000U, 0x0U, 0x020E0434U +#define IOMUXC_NAND_READY_B_UART3_RX 0x020E01A8U, 0x8U, 0x020E0634U, 0x2U, 0x020E0434U +#define IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x020E01ACU, 0x0U, 0x00000000U, 0x0U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_USDHC1_DATA5 0x020E01ACU, 0x1U, 0x00000000U, 0x0U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_QSPI_A_DATA01 0x020E01ACU, 0x2U, 0x00000000U, 0x0U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_ECSPI3_SCLK 0x020E01ACU, 0x3U, 0x020E0554U, 0x1U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_EIM_DTACK_B 0x020E01ACU, 0x4U, 0x00000000U, 0x0U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_GPIO4_IO13 0x020E01ACU, 0x5U, 0x00000000U, 0x0U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_UART3_RX 0x020E01ACU, 0x8U, 0x020E0634U, 0x3U, 0x020E0438U +#define IOMUXC_NAND_CE0_B_UART3_TX 0x020E01ACU, 0x8U, 0x00000000U, 0x0U, 0x020E0438U +#define IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x020E01B0U, 0x0U, 0x00000000U, 0x0U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_USDHC1_DATA6 0x020E01B0U, 0x1U, 0x00000000U, 0x0U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_QSPI_A_DATA02 0x020E01B0U, 0x2U, 0x00000000U, 0x0U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_ECSPI3_MOSI 0x020E01B0U, 0x3U, 0x020E055CU, 0x1U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_EIM_ADDR18 0x020E01B0U, 0x4U, 0x00000000U, 0x0U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_GPIO4_IO14 0x020E01B0U, 0x5U, 0x00000000U, 0x0U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_UART3_CTS_B 0x020E01B0U, 0x8U, 0x00000000U, 0x0U, 0x020E043CU +#define IOMUXC_NAND_CE1_B_UART3_RTS_B 0x020E01B0U, 0x8U, 0x020E0630U, 0x2U, 0x020E043CU +#define IOMUXC_NAND_CLE_RAWNAND_CLE 0x020E01B4U, 0x0U, 0x00000000U, 0x0U, 0x020E0440U +#define IOMUXC_NAND_CLE_USDHC1_DATA7 0x020E01B4U, 0x1U, 0x00000000U, 0x0U, 0x020E0440U +#define IOMUXC_NAND_CLE_QSPI_A_DATA03 0x020E01B4U, 0x2U, 0x00000000U, 0x0U, 0x020E0440U +#define IOMUXC_NAND_CLE_ECSPI3_MISO 0x020E01B4U, 0x3U, 0x020E0558U, 0x1U, 0x020E0440U +#define IOMUXC_NAND_CLE_EIM_ADDR16 0x020E01B4U, 0x4U, 0x00000000U, 0x0U, 0x020E0440U +#define IOMUXC_NAND_CLE_GPIO4_IO15 0x020E01B4U, 0x5U, 0x00000000U, 0x0U, 0x020E0440U +#define IOMUXC_NAND_CLE_UART3_RTS_B 0x020E01B4U, 0x8U, 0x020E0630U, 0x3U, 0x020E0440U +#define IOMUXC_NAND_CLE_UART3_CTS_B 0x020E01B4U, 0x8U, 0x00000000U, 0x0U, 0x020E0440U +#define IOMUXC_NAND_DQS_RAWNAND_DQS 0x020E01B8U, 0x0U, 0x00000000U, 0x0U, 0x020E0444U +#define IOMUXC_NAND_DQS_CSI_FIELD 0x020E01B8U, 0x1U, 0x020E0530U, 0x1U, 0x020E0444U +#define IOMUXC_NAND_DQS_QSPI_A_SS0_B 0x020E01B8U, 0x2U, 0x00000000U, 0x0U, 0x020E0444U +#define IOMUXC_NAND_DQS_PWM5_OUT 0x020E01B8U, 0x3U, 0x00000000U, 0x0U, 0x020E0444U +#define IOMUXC_NAND_DQS_EIM_WAIT 0x020E01B8U, 0x4U, 0x00000000U, 0x0U, 0x020E0444U +#define IOMUXC_NAND_DQS_GPIO4_IO16 0x020E01B8U, 0x5U, 0x00000000U, 0x0U, 0x020E0444U +#define IOMUXC_NAND_DQS_SDMA_EXT_EVENT01 0x020E01B8U, 0x6U, 0x020E0614U, 0x1U, 0x020E0444U +#define IOMUXC_NAND_DQS_SPDIF_EXT_CLK 0x020E01B8U, 0x8U, 0x020E061CU, 0x1U, 0x020E0444U +#define IOMUXC_SD1_CMD_USDHC1_CMD 0x020E01BCU, 0x0U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CMD_GPT2_COMPARE1 0x020E01BCU, 0x1U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CMD_SAI2_RX_SYNC 0x020E01BCU, 0x2U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CMD_SPDIF_OUT 0x020E01BCU, 0x3U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CMD_EIM_ADDR19 0x020E01BCU, 0x4U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CMD_GPIO2_IO16 0x020E01BCU, 0x5U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CMD_SDMA_EXT_EVENT00 0x020E01BCU, 0x6U, 0x020E0610U, 0x2U, 0x020E0448U +#define IOMUXC_SD1_CMD_USB_OTG1_PWR 0x020E01BCU, 0x8U, 0x00000000U, 0x0U, 0x020E0448U +#define IOMUXC_SD1_CLK_USDHC1_CLK 0x020E01C0U, 0x0U, 0x00000000U, 0x0U, 0x020E044CU +#define IOMUXC_SD1_CLK_GPT2_COMPARE2 0x020E01C0U, 0x1U, 0x00000000U, 0x0U, 0x020E044CU +#define IOMUXC_SD1_CLK_SAI2_MCLK 0x020E01C0U, 0x2U, 0x020E05F0U, 0x1U, 0x020E044CU +#define IOMUXC_SD1_CLK_SPDIF_IN 0x020E01C0U, 0x3U, 0x020E0618U, 0x3U, 0x020E044CU +#define IOMUXC_SD1_CLK_EIM_ADDR20 0x020E01C0U, 0x4U, 0x00000000U, 0x0U, 0x020E044CU +#define IOMUXC_SD1_CLK_GPIO2_IO17 0x020E01C0U, 0x5U, 0x00000000U, 0x0U, 0x020E044CU +#define IOMUXC_SD1_CLK_USB_OTG1_OC 0x020E01C0U, 0x8U, 0x020E0664U, 0x2U, 0x020E044CU +#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x020E01C4U, 0x0U, 0x00000000U, 0x0U, 0x020E0450U +#define IOMUXC_SD1_DATA0_GPT2_COMPARE3 0x020E01C4U, 0x1U, 0x00000000U, 0x0U, 0x020E0450U +#define IOMUXC_SD1_DATA0_SAI2_TX_SYNC 0x020E01C4U, 0x2U, 0x020E05FCU, 0x1U, 0x020E0450U +#define IOMUXC_SD1_DATA0_FLEXCAN1_TX 0x020E01C4U, 0x3U, 0x00000000U, 0x0U, 0x020E0450U +#define IOMUXC_SD1_DATA0_EIM_ADDR21 0x020E01C4U, 0x4U, 0x00000000U, 0x0U, 0x020E0450U +#define IOMUXC_SD1_DATA0_GPIO2_IO18 0x020E01C4U, 0x5U, 0x00000000U, 0x0U, 0x020E0450U +#define IOMUXC_SD1_DATA0_ANATOP_OTG1_ID 0x020E01C4U, 0x8U, 0x020E04B8U, 0x2U, 0x020E0450U +#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x020E01C8U, 0x0U, 0x00000000U, 0x0U, 0x020E0454U +#define IOMUXC_SD1_DATA1_GPT2_CLK 0x020E01C8U, 0x1U, 0x020E05A0U, 0x1U, 0x020E0454U +#define IOMUXC_SD1_DATA1_SAI2_TX_BCLK 0x020E01C8U, 0x2U, 0x020E05F8U, 0x1U, 0x020E0454U +#define IOMUXC_SD1_DATA1_FLEXCAN1_RX 0x020E01C8U, 0x3U, 0x020E0584U, 0x3U, 0x020E0454U +#define IOMUXC_SD1_DATA1_EIM_ADDR22 0x020E01C8U, 0x4U, 0x00000000U, 0x0U, 0x020E0454U +#define IOMUXC_SD1_DATA1_GPIO2_IO19 0x020E01C8U, 0x5U, 0x00000000U, 0x0U, 0x020E0454U +#define IOMUXC_SD1_DATA1_USB_OTG2_PWR 0x020E01C8U, 0x8U, 0x00000000U, 0x0U, 0x020E0454U +#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x020E01CCU, 0x0U, 0x00000000U, 0x0U, 0x020E0458U +#define IOMUXC_SD1_DATA2_GPT2_CAPTURE1 0x020E01CCU, 0x1U, 0x020E0598U, 0x1U, 0x020E0458U +#define IOMUXC_SD1_DATA2_SAI2_RX_DATA 0x020E01CCU, 0x2U, 0x020E05F4U, 0x1U, 0x020E0458U +#define IOMUXC_SD1_DATA2_FLEXCAN2_TX 0x020E01CCU, 0x3U, 0x00000000U, 0x0U, 0x020E0458U +#define IOMUXC_SD1_DATA2_EIM_ADDR23 0x020E01CCU, 0x4U, 0x00000000U, 0x0U, 0x020E0458U +#define IOMUXC_SD1_DATA2_GPIO2_IO20 0x020E01CCU, 0x5U, 0x00000000U, 0x0U, 0x020E0458U +#define IOMUXC_SD1_DATA2_CCM_CLKO1 0x020E01CCU, 0x6U, 0x00000000U, 0x0U, 0x020E0458U +#define IOMUXC_SD1_DATA2_USB_OTG2_OC 0x020E01CCU, 0x8U, 0x020E0660U, 0x2U, 0x020E0458U +#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x020E01D0U, 0x0U, 0x00000000U, 0x0U, 0x020E045CU +#define IOMUXC_SD1_DATA3_GPT2_CAPTURE2 0x020E01D0U, 0x1U, 0x020E059CU, 0x1U, 0x020E045CU +#define IOMUXC_SD1_DATA3_SAI2_TX_DATA 0x020E01D0U, 0x2U, 0x00000000U, 0x0U, 0x020E045CU +#define IOMUXC_SD1_DATA3_FLEXCAN2_RX 0x020E01D0U, 0x3U, 0x020E0588U, 0x3U, 0x020E045CU +#define IOMUXC_SD1_DATA3_EIM_ADDR24 0x020E01D0U, 0x4U, 0x00000000U, 0x0U, 0x020E045CU +#define IOMUXC_SD1_DATA3_GPIO2_IO21 0x020E01D0U, 0x5U, 0x00000000U, 0x0U, 0x020E045CU +#define IOMUXC_SD1_DATA3_CCM_CLKO2 0x020E01D0U, 0x6U, 0x00000000U, 0x0U, 0x020E045CU +#define IOMUXC_SD1_DATA3_ANATOP_OTG2_ID 0x020E01D0U, 0x8U, 0x020E04BCU, 0x2U, 0x020E045CU +#define IOMUXC_CSI_MCLK_CSI_MCLK 0x020E01D4U, 0x0U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_USDHC2_CD_B 0x020E01D4U, 0x1U, 0x020E0674U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_RAWNAND_CE2_B 0x020E01D4U, 0x2U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_I2C1_SDA 0x020E01D4U, 0x3U, 0x020E05A8U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_EIM_CS0_B 0x020E01D4U, 0x4U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_GPIO4_IO17 0x020E01D4U, 0x5U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_SNVS_HP_VIO_5_CTL 0x020E01D4U, 0x6U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_UART6_TX 0x020E01D4U, 0x8U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_UART6_RX 0x020E01D4U, 0x8U, 0x020E064CU, 0x0U, 0x020E0460U +#define IOMUXC_CSI_MCLK_ESAI_TX3_RX2 0x020E01D4U, 0x9U, 0x00000000U, 0x0U, 0x020E0460U +#define IOMUXC_CSI_PIXCLK_CSI_PIXCLK 0x020E01D8U, 0x0U, 0x020E0528U, 0x1U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_USDHC2_WP 0x020E01D8U, 0x1U, 0x020E069CU, 0x2U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_RAWNAND_CE3_B 0x020E01D8U, 0x2U, 0x00000000U, 0x0U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_I2C1_SCL 0x020E01D8U, 0x3U, 0x020E05A4U, 0x2U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_EIM_OE 0x020E01D8U, 0x4U, 0x00000000U, 0x0U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_GPIO4_IO18 0x020E01D8U, 0x5U, 0x00000000U, 0x0U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_SNVS_HP_VIO_5 0x020E01D8U, 0x6U, 0x00000000U, 0x0U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_UART6_RX 0x020E01D8U, 0x8U, 0x020E064CU, 0x3U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_UART6_TX 0x020E01D8U, 0x8U, 0x00000000U, 0x0U, 0x020E0464U +#define IOMUXC_CSI_PIXCLK_ESAI_TX2_RX3 0x020E01D8U, 0x9U, 0x00000000U, 0x0U, 0x020E0464U +#define IOMUXC_CSI_VSYNC_CSI_VSYNC 0x020E01DCU, 0x0U, 0x020E052CU, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_USDHC2_CLK 0x020E01DCU, 0x1U, 0x020E0670U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_I2C2_SDA 0x020E01DCU, 0x3U, 0x020E05B0U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_EIM_RW 0x020E01DCU, 0x4U, 0x00000000U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_GPIO4_IO19 0x020E01DCU, 0x5U, 0x00000000U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_PWM7_OUT 0x020E01DCU, 0x6U, 0x00000000U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_UART6_RTS_B 0x020E01DCU, 0x8U, 0x020E0648U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_UART6_CTS_B 0x020E01DCU, 0x8U, 0x00000000U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_VSYNC_ESAI_TX4_RX1 0x020E01DCU, 0x9U, 0x00000000U, 0x0U, 0x020E0468U +#define IOMUXC_CSI_HSYNC_CSI_HSYNC 0x020E01E0U, 0x0U, 0x020E0524U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_USDHC2_CMD 0x020E01E0U, 0x1U, 0x020E0678U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_I2C2_SCL 0x020E01E0U, 0x3U, 0x020E05ACU, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_EIM_LBA_B 0x020E01E0U, 0x4U, 0x00000000U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_GPIO4_IO20 0x020E01E0U, 0x5U, 0x00000000U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_PWM8_OUT 0x020E01E0U, 0x6U, 0x00000000U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_UART6_CTS_B 0x020E01E0U, 0x8U, 0x00000000U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_UART6_RTS_B 0x020E01E0U, 0x8U, 0x020E0648U, 0x1U, 0x020E046CU +#define IOMUXC_CSI_HSYNC_ESAI_TX1 0x020E01E0U, 0x9U, 0x00000000U, 0x0U, 0x020E046CU +#define IOMUXC_CSI_DATA00_CSI_DATA02 0x020E01E4U, 0x0U, 0x020E04C4U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_USDHC2_DATA0 0x020E01E4U, 0x1U, 0x020E067CU, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_ECSPI2_SCLK 0x020E01E4U, 0x3U, 0x020E0544U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_EIM_AD00 0x020E01E4U, 0x4U, 0x00000000U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_GPIO4_IO21 0x020E01E4U, 0x5U, 0x00000000U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_SRC_INT_BOOT 0x020E01E4U, 0x6U, 0x00000000U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_UART5_TX 0x020E01E4U, 0x8U, 0x00000000U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_UART5_RX 0x020E01E4U, 0x8U, 0x020E0644U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA00_ESAI_TX_HF_CLK 0x020E01E4U, 0x9U, 0x00000000U, 0x0U, 0x020E0470U +#define IOMUXC_CSI_DATA01_CSI_DATA03 0x020E01E8U, 0x0U, 0x020E04C8U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_USDHC2_DATA1 0x020E01E8U, 0x1U, 0x020E0680U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_ECSPI2_SS0 0x020E01E8U, 0x3U, 0x020E0550U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_EIM_AD01 0x020E01E8U, 0x4U, 0x00000000U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_GPIO4_IO22 0x020E01E8U, 0x5U, 0x00000000U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_SAI1_MCLK 0x020E01E8U, 0x6U, 0x020E05E0U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_UART5_RX 0x020E01E8U, 0x8U, 0x020E0644U, 0x1U, 0x020E0474U +#define IOMUXC_CSI_DATA01_UART5_TX 0x020E01E8U, 0x8U, 0x00000000U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA01_ESAI_RX_HF_CLK 0x020E01E8U, 0x9U, 0x00000000U, 0x0U, 0x020E0474U +#define IOMUXC_CSI_DATA02_CSI_DATA04 0x020E01ECU, 0x0U, 0x020E04D8U, 0x1U, 0x020E0478U +#define IOMUXC_CSI_DATA02_USDHC2_DATA2 0x020E01ECU, 0x1U, 0x020E0684U, 0x2U, 0x020E0478U +#define IOMUXC_CSI_DATA02_ECSPI2_MOSI 0x020E01ECU, 0x3U, 0x020E054CU, 0x1U, 0x020E0478U +#define IOMUXC_CSI_DATA02_EIM_AD02 0x020E01ECU, 0x4U, 0x00000000U, 0x0U, 0x020E0478U +#define IOMUXC_CSI_DATA02_GPIO4_IO23 0x020E01ECU, 0x5U, 0x00000000U, 0x0U, 0x020E0478U +#define IOMUXC_CSI_DATA02_SAI1_RX_SYNC 0x020E01ECU, 0x6U, 0x00000000U, 0x0U, 0x020E0478U +#define IOMUXC_CSI_DATA02_UART5_RTS_B 0x020E01ECU, 0x8U, 0x020E0640U, 0x7U, 0x020E0478U +#define IOMUXC_CSI_DATA02_UART5_CTS_B 0x020E01ECU, 0x8U, 0x00000000U, 0x0U, 0x020E0478U +#define IOMUXC_CSI_DATA02_ESAI_RX_FS 0x020E01ECU, 0x9U, 0x00000000U, 0x0U, 0x020E0478U +#define IOMUXC_CSI_DATA03_CSI_DATA05 0x020E01F0U, 0x0U, 0x020E04CCU, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_USDHC2_DATA3 0x020E01F0U, 0x1U, 0x020E0688U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_ECSPI2_MISO 0x020E01F0U, 0x3U, 0x020E0548U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_EIM_AD03 0x020E01F0U, 0x4U, 0x00000000U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_GPIO4_IO24 0x020E01F0U, 0x5U, 0x00000000U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_SAI1_RX_BCLK 0x020E01F0U, 0x6U, 0x00000000U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_UART5_CTS_B 0x020E01F0U, 0x8U, 0x00000000U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_UART5_RTS_B 0x020E01F0U, 0x8U, 0x020E0640U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA03_ESAI_RX_CLK 0x020E01F0U, 0x9U, 0x00000000U, 0x0U, 0x020E047CU +#define IOMUXC_CSI_DATA04_CSI_DATA06 0x020E01F4U, 0x0U, 0x020E04DCU, 0x1U, 0x020E0480U +#define IOMUXC_CSI_DATA04_USDHC2_DATA4 0x020E01F4U, 0x1U, 0x020E068CU, 0x2U, 0x020E0480U +#define IOMUXC_CSI_DATA04_ECSPI1_SCLK 0x020E01F4U, 0x3U, 0x020E0534U, 0x1U, 0x020E0480U +#define IOMUXC_CSI_DATA04_EIM_AD04 0x020E01F4U, 0x4U, 0x00000000U, 0x0U, 0x020E0480U +#define IOMUXC_CSI_DATA04_GPIO4_IO25 0x020E01F4U, 0x5U, 0x00000000U, 0x0U, 0x020E0480U +#define IOMUXC_CSI_DATA04_SAI1_TX_SYNC 0x020E01F4U, 0x6U, 0x020E05ECU, 0x1U, 0x020E0480U +#define IOMUXC_CSI_DATA04_USDHC1_WP 0x020E01F4U, 0x8U, 0x020E066CU, 0x2U, 0x020E0480U +#define IOMUXC_CSI_DATA04_ESAI_TX_FS 0x020E01F4U, 0x9U, 0x00000000U, 0x0U, 0x020E0480U +#define IOMUXC_CSI_DATA05_CSI_DATA07 0x020E01F8U, 0x0U, 0x020E04E0U, 0x1U, 0x020E0484U +#define IOMUXC_CSI_DATA05_USDHC2_DATA5 0x020E01F8U, 0x1U, 0x020E0690U, 0x2U, 0x020E0484U +#define IOMUXC_CSI_DATA05_ECSPI1_SS0 0x020E01F8U, 0x3U, 0x020E0540U, 0x1U, 0x020E0484U +#define IOMUXC_CSI_DATA05_EIM_AD05 0x020E01F8U, 0x4U, 0x00000000U, 0x0U, 0x020E0484U +#define IOMUXC_CSI_DATA05_GPIO4_IO26 0x020E01F8U, 0x5U, 0x00000000U, 0x0U, 0x020E0484U +#define IOMUXC_CSI_DATA05_SAI1_TX_BCLK 0x020E01F8U, 0x6U, 0x020E05E8U, 0x1U, 0x020E0484U +#define IOMUXC_CSI_DATA05_USDHC1_CD_B 0x020E01F8U, 0x8U, 0x020E0668U, 0x2U, 0x020E0484U +#define IOMUXC_CSI_DATA05_ESAI_TX_CLK 0x020E01F8U, 0x9U, 0x00000000U, 0x0U, 0x020E0484U +#define IOMUXC_CSI_DATA06_CSI_DATA08 0x020E01FCU, 0x0U, 0x020E04E4U, 0x1U, 0x020E0488U +#define IOMUXC_CSI_DATA06_USDHC2_DATA6 0x020E01FCU, 0x1U, 0x020E0694U, 0x2U, 0x020E0488U +#define IOMUXC_CSI_DATA06_ECSPI1_MOSI 0x020E01FCU, 0x3U, 0x020E053CU, 0x1U, 0x020E0488U +#define IOMUXC_CSI_DATA06_EIM_AD06 0x020E01FCU, 0x4U, 0x00000000U, 0x0U, 0x020E0488U +#define IOMUXC_CSI_DATA06_GPIO4_IO27 0x020E01FCU, 0x5U, 0x00000000U, 0x0U, 0x020E0488U +#define IOMUXC_CSI_DATA06_SAI1_RX_DATA 0x020E01FCU, 0x6U, 0x020E05E4U, 0x1U, 0x020E0488U +#define IOMUXC_CSI_DATA06_USDHC1_RESET_B 0x020E01FCU, 0x8U, 0x00000000U, 0x0U, 0x020E0488U +#define IOMUXC_CSI_DATA06_ESAI_TX5_RX0 0x020E01FCU, 0x9U, 0x00000000U, 0x0U, 0x020E0488U +#define IOMUXC_CSI_DATA07_CSI_DATA09 0x020E0200U, 0x0U, 0x020E04E8U, 0x1U, 0x020E048CU +#define IOMUXC_CSI_DATA07_USDHC2_DATA7 0x020E0200U, 0x1U, 0x020E0698U, 0x2U, 0x020E048CU +#define IOMUXC_CSI_DATA07_ECSPI1_MISO 0x020E0200U, 0x3U, 0x020E0538U, 0x1U, 0x020E048CU +#define IOMUXC_CSI_DATA07_EIM_AD07 0x020E0200U, 0x4U, 0x00000000U, 0x0U, 0x020E048CU +#define IOMUXC_CSI_DATA07_GPIO4_IO28 0x020E0200U, 0x5U, 0x00000000U, 0x0U, 0x020E048CU +#define IOMUXC_CSI_DATA07_SAI1_TX_DATA 0x020E0200U, 0x6U, 0x00000000U, 0x0U, 0x020E048CU +#define IOMUXC_CSI_DATA07_USDHC1_VSELECT 0x020E0200U, 0x8U, 0x00000000U, 0x0U, 0x020E048CU +#define IOMUXC_CSI_DATA07_ESAI_TX0 0x020E0200U, 0x9U, 0x00000000U, 0x0U, 0x020E048CU +#define IOMUXC_DRAM_ADDR00 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0204U +#define IOMUXC_DRAM_ADDR01 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0208U +#define IOMUXC_DRAM_ADDR02 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E020CU +#define IOMUXC_DRAM_ADDR03 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0210U +#define IOMUXC_DRAM_ADDR04 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0214U +#define IOMUXC_DRAM_ADDR05 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0218U +#define IOMUXC_DRAM_ADDR06 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E021CU +#define IOMUXC_DRAM_ADDR07 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0220U +#define IOMUXC_DRAM_ADDR08 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0224U +#define IOMUXC_DRAM_ADDR09 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0228U +#define IOMUXC_DRAM_ADDR10 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E022CU +#define IOMUXC_DRAM_ADDR11 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0230U +#define IOMUXC_DRAM_ADDR12 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0234U +#define IOMUXC_DRAM_ADDR13 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0238U +#define IOMUXC_DRAM_ADDR14 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E023CU +#define IOMUXC_DRAM_ADDR15 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0240U +#define IOMUXC_DRAM_DQM0 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0244U +#define IOMUXC_DRAM_DQM1 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0248U +#define IOMUXC_DRAM_RAS_B 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E024CU +#define IOMUXC_DRAM_CAS_B 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0250U +#define IOMUXC_DRAM_CS0_B 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0254U +#define IOMUXC_DRAM_CS1_B 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0258U +#define IOMUXC_DRAM_SDWE_B 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E025CU +#define IOMUXC_DRAM_ODT0 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0260U +#define IOMUXC_DRAM_ODT1 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0264U +#define IOMUXC_DRAM_SDBA0 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0268U +#define IOMUXC_DRAM_SDBA1 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E026CU +#define IOMUXC_DRAM_SDBA2 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0270U +#define IOMUXC_DRAM_SDCKE0 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0274U +#define IOMUXC_DRAM_SDCKE1 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0278U +#define IOMUXC_DRAM_SDCLK0_P 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E027CU +#define IOMUXC_DRAM_SDQS0_P 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0280U +#define IOMUXC_DRAM_SDQS1_P 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0284U +#define IOMUXC_DRAM_RESET 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0288U +#define IOMUXC_GRP_ADDDS 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0490U +#define IOMUXC_GRP_DDRMODE_CTL 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0494U +#define IOMUXC_GRP_B0DS 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E0498U +#define IOMUXC_GRP_DDRPK 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E049CU +#define IOMUXC_GRP_CTLDS 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E04A0U +#define IOMUXC_GRP_B1DS 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E04A4U +#define IOMUXC_GRP_DDRHYS 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E04A8U +#define IOMUXC_GRP_DDRPKE 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E04ACU +#define IOMUXC_GRP_DDRMODE 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E04B0U +#define IOMUXC_GRP_DDR_TYPE 0x00000000U, 0x0U, 0x00000000U, 0x0U, 0x020E04B4U + + + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the ENET1_RX_DATA0 Pad as FLEXCAN1_TX: + * @code + * IOMUXC_SetPinMux(IOMUXC_ENET1_RX_DATA0_FLEXCAN1_TX, 0); + * @endcode + * + * This is an example to set the GPIO1_IO02 Pad as I2C1_SCL: + * @code + * IOMUXC_SetPinMux(IOMUXC_GPIO1_IO02_I2C1_SCL, 0); + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param inputOnfield Software input on field. + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy); + } +} + +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_GPIO1_IO02_I2C1_SCL: + * @code + * IOMUXC_SetPinConfig(IOMUXC_GPIO1_IO02_I2C1_SCL, IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(2U)); + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param configValue The pin config value. + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/board/ALPHA_I.MX_emmc_256ddr/src/main.c b/board/ALPHA_I.MX_emmc_256ddr/src/main.c new file mode 100644 index 00000000..823861e9 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/src/main.c @@ -0,0 +1,63 @@ +#include "tos_k.h" + +#include "bsp_clk.h" +#include "bsp_delay.h" +#include "bsp_led.h" +#include "bsp_beep.h" +#include "bsp_key.h" +#include "bsp_int.h" +#include "bsp_uart.h" +#include "bsp_exit.h" +#include "bsp_epittimer.h" + +void task1_entry(void *arg) +{ + while (1) { + printf("task1\r\n"); + tos_task_delay(2000); + } +} + +void task2_entry(void *arg) +{ + while (1) { + printf("task2\r\n"); + tos_task_delay(3000); + } +} + +k_task_t task1; +k_stack_t task1_stack[512]; + +k_task_t task2; +k_stack_t task2_stack[512]; + +int main(void) +{ + unsigned char state = OFF; + + uart_init(); + led_init(); + beep_init(); + key_init(); + + tos_knl_init(); + + tos_task_create(&task1, "task1", task1_entry, NULL, + 4, + task1_stack, sizeof(task1_stack), + 0); + tos_task_create(&task2, "task2", task2_entry, NULL, + 4, + task2_stack, sizeof(task2_stack), + 0); + + tos_knl_start(); + + while (1) { + delay(3000); + } + + return 0; +} + diff --git a/board/ALPHA_I.MX_emmc_256ddr/stdio/include/ctype.h b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/ctype.h new file mode 100644 index 00000000..1e488373 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/ctype.h @@ -0,0 +1,49 @@ +/* + * NOTE! This ctype does not handle EOF like the standard C + * library is required to. + */ + +#define _U 0x01 /* upper */ +#define _L 0x02 /* lower */ +#define _D 0x04 /* digit */ +#define _C 0x08 /* cntrl */ +#define _P 0x10 /* punct */ +#define _S 0x20 /* white space (space/lf/tab) */ +#define _X 0x40 /* hex digit */ +#define _SP 0x80 /* hard space (0x20) */ + +extern unsigned char _ctype[]; + +#define __ismask(x) (_ctype[(int)(unsigned char)(x)]) + +#define isalnum(c) ((__ismask(c)&(_U|_L|_D)) != 0) +#define isalpha(c) ((__ismask(c)&(_U|_L)) != 0) +#define iscntrl(c) ((__ismask(c)&(_C)) != 0) +#define isdigit(c) ((__ismask(c)&(_D)) != 0) +#define isgraph(c) ((__ismask(c)&(_P|_U|_L|_D)) != 0) +#define islower(c) ((__ismask(c)&(_L)) != 0) +#define isprint(c) ((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0) +#define ispunct(c) ((__ismask(c)&(_P)) != 0) +#define isspace(c) ((__ismask(c)&(_S)) != 0) +#define isupper(c) ((__ismask(c)&(_U)) != 0) +#define isxdigit(c) ((__ismask(c)&(_D|_X)) != 0) + +#define isascii(c) (((unsigned char)(c))<=0x7f) +#define toascii(c) (((unsigned char)(c))&0x7f) + +static inline unsigned char __tolower(unsigned char c) +{ + if (isupper(c)) + c -= 'A'-'a'; + return c; +} + +static inline unsigned char __toupper(unsigned char c) +{ + if (islower(c)) + c -= 'a'-'A'; + return c; +} + +#define tolower(c) __tolower(c) +#define toupper(c) __toupper(c) diff --git a/board/ALPHA_I.MX_emmc_256ddr/stdio/include/div64.h b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/div64.h new file mode 100644 index 00000000..fc67fe0e --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/div64.h @@ -0,0 +1,35 @@ +#ifndef __ASM_ARM_DIV64 +#define __ASM_ARM_DIV64 +//#include + +/* + * The semantics of do_div() are: + * + * uint32_t do_div(uint64_t *n, uint32_t base) + * { + * uint32_t remainder = *n % base; + * *n = *n / base; + * return remainder; + * } + * + * In other words, a 64-bit dividend with a 32-bit divisor producing + * a 64-bit result and a 32-bit remainder. To accomplish this optimally + * we call a special __do_div64 helper with completely non standard + * calling convention for arguments and results (beware). + */ +extern unsigned int __div64_32(unsigned long long *dividend, unsigned int divisor); + +# define do_div(n,base) ({ \ + unsigned int __base = (base); \ + unsigned int __rem; \ + (void)(((typeof((n)) *)0) == ((uint64_t *)0)); \ + if (((n) >> 32) == 0) { \ + __rem = (unsigned int)(n) % __base; \ + (n) = (unsigned int)(n) / __base; \ + } else \ + __rem = __div64_32(&(n), __base); \ + __rem; \ + }) + + +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/stdio/include/gcclib.h b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/gcclib.h new file mode 100644 index 00000000..65314a3d --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/gcclib.h @@ -0,0 +1,25 @@ +/* gcclib.h -- definitions for various functions 'borrowed' from gcc-2.95.3 */ +/* I Molton 29/07/01 */ + +#define BITS_PER_UNIT 8 +#define SI_TYPE_SIZE (sizeof (SItype) * BITS_PER_UNIT) + +typedef unsigned int UQItype __attribute__ ((mode (QI))); +typedef int SItype __attribute__ ((mode (SI))); +typedef unsigned int USItype __attribute__ ((mode (SI))); +typedef int DItype __attribute__ ((mode (DI))); +typedef int word_type __attribute__ ((mode (__word__))); +typedef unsigned int UDItype __attribute__ ((mode (DI))); + +#ifdef __ARMEB__ + struct DIstruct {SItype high, low;}; +#else + struct DIstruct {SItype low, high;}; +#endif + +typedef union +{ + struct DIstruct s; + DItype ll; +} DIunion; + diff --git a/board/ALPHA_I.MX_emmc_256ddr/stdio/include/kernel.h b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/kernel.h new file mode 100644 index 00000000..40502d9c --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/kernel.h @@ -0,0 +1,6 @@ +#define INT_MAX ((int)(~0U>>1)) +#define INT_MIN (-INT_MAX - 1) +#define UINT_MAX (~0U) +#define LONG_MAX ((long)(~0UL>>1)) +#define LONG_MIN (-LONG_MAX - 1) +#define ULONG_MAX (~0UL) diff --git a/board/ALPHA_I.MX_emmc_256ddr/stdio/include/printf.h b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/printf.h new file mode 100644 index 00000000..e3fa0be5 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/printf.h @@ -0,0 +1,26 @@ + +#ifndef _STDIO_H +#define _STDIO_H + +#include "types.h" + +#ifndef _VALIST +#define _VALIST + +typedef char *va_list; +#endif /* _VALIST */ + +extern int vsnprintf(char *buf, size_t size, const char *fmt, va_list args); +extern int snprintf(char * buf, size_t size, const char *fmt, ...); +extern int vsprintf(char *buf, const char *fmt, va_list args); +extern int sprintf(char * buf, const char *fmt, ...); +extern int vsscanf(const char * buf, const char * fmt, va_list args); +extern int sscanf(const char * buf, const char * fmt, ...); + +extern void putc(unsigned char c); +extern unsigned char getc(void); + +int printf(const char *fmt, ...); +int scanf(const char * fmt, ...); + +#endif /* _STDIO_H */ diff --git a/board/ALPHA_I.MX_emmc_256ddr/stdio/include/string.h b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/string.h new file mode 100644 index 00000000..317ea136 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/string.h @@ -0,0 +1,78 @@ + +/* We don't want strings.h stuff being user by user stuff by accident */ + + +//#include /* for size_t */ +//#include /* for NULL */ + +#include "types.h" + +extern char * ___strtok; +extern char * strpbrk(const char *,const char *); +extern char * strtok(char *,const char *); +extern char * strsep(char **,const char *); +extern size_t strspn(const char *,const char *); + + +/* + * Include machine specific inline routines + */ +//#include + +#ifndef __HAVE_ARCH_STRCPY +extern char * strcpy(char *,const char *); +#endif +#ifndef __HAVE_ARCH_STRNCPY +extern char * strncpy(char *,const char *, size_t); +#endif +#ifndef __HAVE_ARCH_STRCAT +extern char * strcat(char *, const char *); +#endif +#ifndef __HAVE_ARCH_STRNCAT +extern char * strncat(char *, const char *, size_t); +#endif +#ifndef __HAVE_ARCH_STRCMP +extern int strcmp(const char *,const char *); +#endif +#ifndef __HAVE_ARCH_STRNCMP +extern int strncmp(const char *,const char *,size_t); +#endif +#ifndef __HAVE_ARCH_STRNICMP +extern int strnicmp(const char *, const char *, size_t); +#endif +#ifndef __HAVE_ARCH_STRCHR +extern char * strchr(const char *,int); +#endif +#ifndef __HAVE_ARCH_STRRCHR +extern char * strrchr(const char *,int); +#endif +#ifndef __HAVE_ARCH_STRSTR +extern char * strstr(const char *,const char *); +#endif +#ifndef __HAVE_ARCH_STRLEN +extern size_t strlen(const char *); +#endif +#ifndef __HAVE_ARCH_STRNLEN +extern size_t strnlen(const char *,size_t); +#endif + +#ifndef __HAVE_ARCH_MEMSET +extern void * memset(void *,int,size_t); +#endif +#ifndef __HAVE_ARCH_MEMCPY +extern void * memcpy(void *,const void *,size_t); +#endif +#ifndef __HAVE_ARCH_MEMMOVE +extern void * memmove(void *,const void *,size_t); +#endif +#ifndef __HAVE_ARCH_MEMSCAN +extern void * memscan(void *,int,size_t); +#endif +#ifndef __HAVE_ARCH_MEMCMP +extern int memcmp(const void *,const void *,size_t); +#endif +#ifndef __HAVE_ARCH_MEMCHR +extern void * memchr(const void *,int,size_t); +#endif + + diff --git a/board/ALPHA_I.MX_emmc_256ddr/stdio/include/system.h b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/system.h new file mode 100644 index 00000000..77d0dcf0 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/system.h @@ -0,0 +1,388 @@ +#ifndef __ASM_ARM_SYSTEM_H +#define __ASM_ARM_SYSTEM_H + +#ifdef __KERNEL__ + +#include + +#define CPU_ARCH_UNKNOWN 0 +#define CPU_ARCH_ARMv3 1 +#define CPU_ARCH_ARMv4 2 +#define CPU_ARCH_ARMv4T 3 +#define CPU_ARCH_ARMv5 4 +#define CPU_ARCH_ARMv5T 5 +#define CPU_ARCH_ARMv5TE 6 +#define CPU_ARCH_ARMv5TEJ 7 +#define CPU_ARCH_ARMv6 8 + +/* + * CR1 bits (CP#15 CR1) + */ +#define CR_M (1 << 0) /* MMU enable */ +#define CR_A (1 << 1) /* Alignment abort enable */ +#define CR_C (1 << 2) /* Dcache enable */ +#define CR_W (1 << 3) /* Write buffer enable */ +#define CR_P (1 << 4) /* 32-bit exception handler */ +#define CR_D (1 << 5) /* 32-bit data address range */ +#define CR_L (1 << 6) /* Implementation defined */ +#define CR_B (1 << 7) /* Big endian */ +#define CR_S (1 << 8) /* System MMU protection */ +#define CR_R (1 << 9) /* ROM MMU protection */ +#define CR_F (1 << 10) /* Implementation defined */ +#define CR_Z (1 << 11) /* Implementation defined */ +#define CR_I (1 << 12) /* Icache enable */ +#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ +#define CR_RR (1 << 14) /* Round Robin cache replacement */ +#define CR_L4 (1 << 15) /* LDR pc can set T bit */ +#define CR_DT (1 << 16) +#define CR_IT (1 << 18) +#define CR_ST (1 << 19) +#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ +#define CR_U (1 << 22) /* Unaligned access operation */ +#define CR_XP (1 << 23) /* Extended page tables */ +#define CR_VE (1 << 24) /* Vectored interrupts */ + +#define CPUID_ID 0 +#define CPUID_CACHETYPE 1 +#define CPUID_TCM 2 +#define CPUID_TLBTYPE 3 + +#define read_cpuid(reg) \ + ({ \ + unsigned int __val; \ + asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \ + : "=r" (__val) \ + : \ + : "cc"); \ + __val; \ + }) + +/* + * This is used to ensure the compiler did actually allocate the register we + * asked it for some inline assembly sequences. Apparently we can't trust + * the compiler from one version to another so a bit of paranoia won't hurt. + * This string is meant to be concatenated with the inline asm string and + * will cause compilation to stop on mismatch. + * (for details, see gcc PR 15089) + */ +#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" + +#ifndef __ASSEMBLY__ + +#include + +struct thread_info; +struct task_struct; + +/* information about the system we're running on */ +extern unsigned int system_rev; +extern unsigned int system_serial_low; +extern unsigned int system_serial_high; +extern unsigned int mem_fclk_21285; + +struct pt_regs; + +void die(const char *msg, struct pt_regs *regs, int err) + __attribute__((noreturn)); + +void die_if_kernel(const char *str, struct pt_regs *regs, int err); + +void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, + struct pt_regs *), + int sig, const char *name); + +#include + +#define xchg(ptr,x) \ + ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) + +#define tas(ptr) (xchg((ptr),1)) + +extern asmlinkage void __backtrace(void); + +extern int cpu_architecture(void); + +#define set_cr(x) \ + __asm__ __volatile__( \ + "mcr p15, 0, %0, c1, c0, 0 @ set CR" \ + : : "r" (x) : "cc") + +#define get_cr() \ + ({ \ + unsigned int __val; \ + __asm__ __volatile__( \ + "mrc p15, 0, %0, c1, c0, 0 @ get CR" \ + : "=r" (__val) : : "cc"); \ + __val; \ + }) + +extern unsigned long cr_no_alignment; /* defined in entry-armv.S */ +extern unsigned long cr_alignment; /* defined in entry-armv.S */ + +#define UDBG_UNDEFINED (1 << 0) +#define UDBG_SYSCALL (1 << 1) +#define UDBG_BADABORT (1 << 2) +#define UDBG_SEGV (1 << 3) +#define UDBG_BUS (1 << 4) + +extern unsigned int user_debug; + +#if __LINUX_ARM_ARCH__ >= 4 +#define vectors_high() (cr_alignment & CR_V) +#else +#define vectors_high() (0) +#endif + +#define mb() __asm__ __volatile__ ("" : : : "memory") +#define rmb() mb() +#define wmb() mb() +#define read_barrier_depends() do { } while(0) +#define set_mb(var, value) do { var = value; mb(); } while (0) +#define set_wmb(var, value) do { var = value; wmb(); } while (0) +#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); + +#ifdef CONFIG_SMP +/* + * Define our own context switch locking. This allows us to enable + * interrupts over the context switch, otherwise we end up with high + * interrupt latency. The real problem area is switch_mm() which may + * do a full cache flush. + */ +#define prepare_arch_switch(rq,next) \ +do { \ + spin_lock(&(next)->switch_lock); \ + spin_unlock_irq(&(rq)->lock); \ +} while (0) + +#define finish_arch_switch(rq,prev) \ + spin_unlock(&(prev)->switch_lock) + +#define task_running(rq,p) \ + ((rq)->curr == (p) || spin_is_locked(&(p)->switch_lock)) +#else +/* + * Our UP-case is more simple, but we assume knowledge of how + * spin_unlock_irq() and friends are implemented. This avoids + * us needlessly decrementing and incrementing the preempt count. + */ +#define prepare_arch_switch(rq,next) local_irq_enable() +#define finish_arch_switch(rq,prev) spin_unlock(&(rq)->lock) +#define task_running(rq,p) ((rq)->curr == (p)) +#endif + +/* + * switch_to(prev, next) should switch from task `prev' to `next' + * `prev' will never be the same as `next'. schedule() itself + * contains the memory barrier to tell GCC not to cache `current'. + */ +extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *); + +#define switch_to(prev,next,last) \ +do { \ + last = __switch_to(prev,prev->thread_info,next->thread_info); \ +} while (0) + +/* + * CPU interrupt mask handling. + */ +#if __LINUX_ARM_ARCH__ >= 6 + +#define local_irq_save(x) \ + ({ \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ local_irq_save\n" \ + "cpsid i" \ + : "=r" (x) : : "memory", "cc"); \ + }) + +#define local_irq_enable() __asm__("cpsie i @ __sti" : : : "memory", "cc") +#define local_irq_disable() __asm__("cpsid i @ __cli" : : : "memory", "cc") +#define local_fiq_enable() __asm__("cpsie f @ __stf" : : : "memory", "cc") +#define local_fiq_disable() __asm__("cpsid f @ __clf" : : : "memory", "cc") + +#else + +/* + * Save the current interrupt enable state & disable IRQs + */ +#define local_irq_save(x) \ + ({ \ + unsigned long temp; \ + (void) (&temp == &x); \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ local_irq_save\n" \ +" orr %1, %0, #128\n" \ +" msr cpsr_c, %1" \ + : "=r" (x), "=r" (temp) \ + : \ + : "memory", "cc"); \ + }) + +/* + * Enable IRQs + */ +#define local_irq_enable() \ + ({ \ + unsigned long temp; \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ local_irq_enable\n" \ +" bic %0, %0, #128\n" \ +" msr cpsr_c, %0" \ + : "=r" (temp) \ + : \ + : "memory", "cc"); \ + }) + +/* + * Disable IRQs + */ +#define local_irq_disable() \ + ({ \ + unsigned long temp; \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ local_irq_disable\n" \ +" orr %0, %0, #128\n" \ +" msr cpsr_c, %0" \ + : "=r" (temp) \ + : \ + : "memory", "cc"); \ + }) + +/* + * Enable FIQs + */ +#define local_fiq_enable() \ + ({ \ + unsigned long temp; \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ stf\n" \ +" bic %0, %0, #64\n" \ +" msr cpsr_c, %0" \ + : "=r" (temp) \ + : \ + : "memory", "cc"); \ + }) + +/* + * Disable FIQs + */ +#define local_fiq_disable() \ + ({ \ + unsigned long temp; \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ clf\n" \ +" orr %0, %0, #64\n" \ +" msr cpsr_c, %0" \ + : "=r" (temp) \ + : \ + : "memory", "cc"); \ + }) + +#endif + +/* + * Save the current interrupt enable state. + */ +#define local_save_flags(x) \ + ({ \ + __asm__ __volatile__( \ + "mrs %0, cpsr @ local_save_flags" \ + : "=r" (x) : : "memory", "cc"); \ + }) + +/* + * restore saved IRQ & FIQ state + */ +#define local_irq_restore(x) \ + __asm__ __volatile__( \ + "msr cpsr_c, %0 @ local_irq_restore\n" \ + : \ + : "r" (x) \ + : "memory", "cc") + +#define irqs_disabled() \ +({ \ + unsigned long flags; \ + local_save_flags(flags); \ + flags & PSR_I_BIT; \ +}) + +#ifdef CONFIG_SMP +#error SMP not supported + +#define smp_mb() mb() +#define smp_rmb() rmb() +#define smp_wmb() wmb() +#define smp_read_barrier_depends() read_barrier_depends() + +#else + +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#define smp_read_barrier_depends() do { } while(0) + +#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) +/* + * On the StrongARM, "swp" is terminally broken since it bypasses the + * cache totally. This means that the cache becomes inconsistent, and, + * since we use normal loads/stores as well, this is really bad. + * Typically, this causes oopsen in filp_close, but could have other, + * more disasterous effects. There are two work-arounds: + * 1. Disable interrupts and emulate the atomic swap + * 2. Clean the cache, perform atomic swap, flush the cache + * + * We choose (1) since its the "easiest" to achieve here and is not + * dependent on the processor type. + */ +#define swp_is_buggy +#endif + +static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size) +{ + extern void __bad_xchg(volatile void *, int); + unsigned long ret; +#ifdef swp_is_buggy + unsigned long flags; +#endif + + switch (size) { +#ifdef swp_is_buggy + case 1: + local_irq_save(flags); + ret = *(volatile unsigned char *)ptr; + *(volatile unsigned char *)ptr = x; + local_irq_restore(flags); + break; + + case 4: + local_irq_save(flags); + ret = *(volatile unsigned long *)ptr; + *(volatile unsigned long *)ptr = x; + local_irq_restore(flags); + break; +#else + case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]" + : "=&r" (ret) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; + case 4: __asm__ __volatile__ ("swp %0, %1, [%2]" + : "=&r" (ret) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; +#endif + default: __bad_xchg(ptr, size), ret = 0; + } + + return ret; +} + +#endif /* CONFIG_SMP */ + +#endif /* __ASSEMBLY__ */ + +#endif /* __KERNEL__ */ + +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/stdio/include/types.h b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/types.h new file mode 100644 index 00000000..bf08db0b --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/types.h @@ -0,0 +1,15 @@ + +#ifndef _TPYES_H +#define _TPYES_H + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef _SIZE_T +#define _SIZE_T +typedef unsigned int size_t; +#endif /* _SIZE_T */ + + +#endif /* _TPYES_H */ diff --git a/board/ALPHA_I.MX_emmc_256ddr/stdio/include/vsprintf.h b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/vsprintf.h new file mode 100644 index 00000000..7137fd18 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/stdio/include/vsprintf.h @@ -0,0 +1,46 @@ +/* + * Use local definitions of C library macros and functions + * NOTE: The function implementations may not be as efficient + * as an inline or assembly code implementation provided by a + * native C library. + */ + +#include "types.h" + +#ifndef va_arg + +#ifndef _VALIST +#define _VALIST +typedef char *va_list; +#endif /* _VALIST */ + +/* + * Storage alignment properties + */ +#define NATIVE_INT int +#define _AUPBND (sizeof (NATIVE_INT) - 1) +#define _ADNBND (sizeof (NATIVE_INT) - 1) + +/* + * Variable argument list macro definitions + */ + +#define _bnd(X, bnd) (((sizeof (X)) + (bnd)) & (~(bnd))) +#define va_arg(ap, T) (*(T *)(((ap) += (_bnd (T, _AUPBND))) - (_bnd (T,_ADNBND)))) +#define va_end(ap) (void) 0 +#define va_start(ap, A) (void) ((ap) = (((char *) &(A)) + (_bnd (A,_AUPBND)))) + +#endif /* va_arg */ + +unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base); +long simple_strtol(const char *cp,char **endp,unsigned int base); +unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base); +long long simple_strtoll(const char *cp,char **endp,unsigned int base); +//static int skip_atoi(const char **s); +//char * number(char * buf, char * end, long long num, int base, int size, int precision, int type); +int vsnprintf(char *buf, size_t size, const char *fmt, va_list args); +int snprintf(char * buf, size_t size, const char *fmt, ...); +int vsprintf(char *buf, const char *fmt, va_list args); +int sprintf(char * buf, const char *fmt, ...); +int vsscanf(const char * buf, const char * fmt, va_list args); +int sscanf(const char * buf, const char * fmt, ...); diff --git a/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/ctype.c b/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/ctype.c new file mode 100644 index 00000000..719f652e --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/ctype.c @@ -0,0 +1,33 @@ +/* + * linux/lib/ctype.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ + +#include "ctype.h" + +unsigned char _ctype[] = { +_C,_C,_C,_C,_C,_C,_C,_C, /* 0-7 */ +_C,_C|_S,_C|_S,_C|_S,_C|_S,_C|_S,_C,_C, /* 8-15 */ +_C,_C,_C,_C,_C,_C,_C,_C, /* 16-23 */ +_C,_C,_C,_C,_C,_C,_C,_C, /* 24-31 */ +_S|_SP,_P,_P,_P,_P,_P,_P,_P, /* 32-39 */ +_P,_P,_P,_P,_P,_P,_P,_P, /* 40-47 */ +_D,_D,_D,_D,_D,_D,_D,_D, /* 48-55 */ +_D,_D,_P,_P,_P,_P,_P,_P, /* 56-63 */ +_P,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U|_X,_U, /* 64-71 */ +_U,_U,_U,_U,_U,_U,_U,_U, /* 72-79 */ +_U,_U,_U,_U,_U,_U,_U,_U, /* 80-87 */ +_U,_U,_U,_P,_P,_P,_P,_P, /* 88-95 */ +_P,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L|_X,_L, /* 96-103 */ +_L,_L,_L,_L,_L,_L,_L,_L, /* 104-111 */ +_L,_L,_L,_L,_L,_L,_L,_L, /* 112-119 */ +_L,_L,_L,_P,_P,_P,_P,_C, /* 120-127 */ +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */ +0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */ +_S|_SP,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 160-175 */ +_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P,_P, /* 176-191 */ +_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U,_U, /* 192-207 */ +_U,_U,_U,_U,_U,_U,_U,_P,_U,_U,_U,_U,_U,_U,_U,_L, /* 208-223 */ +_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L,_L, /* 224-239 */ +_L,_L,_L,_L,_L,_L,_L,_P,_L,_L,_L,_L,_L,_L,_L,_L}; /* 240-255 */ diff --git a/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/div64.c b/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/div64.c new file mode 100644 index 00000000..d0086111 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/div64.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2003 Bernardo Innocenti + * + * Based on former do_div() implementation from asm-parisc/div64.h: + * Copyright (C) 1999 Hewlett-Packard Co + * Copyright (C) 1999 David Mosberger-Tang + * + * + * Generic C version of 64bit/32bit division and modulo, with + * 64bit result and 32bit remainder. + * + * The fast case for (n>>32 == 0) is handled inline by do_div(). + * + * Code generated for this function might be very inefficient + * for some CPUs. __div64_32() can be overridden by linking arch-specific + * assembly versions such as arch/powerpc/lib/div64.S and arch/sh/lib/div64.S. + */ + +#include "div64.h" + +unsigned int __div64_32(unsigned long long *n, unsigned int base) +{ + unsigned long long rem = *n; + unsigned long long b = base; + unsigned long long res, d = 1; + unsigned int high = rem >> 32; + + /* Reduce the thing a bit first */ + res = 0; + if (high >= base) { + high /= base; + res = (unsigned long long ) high << 32; + rem -= (unsigned long long ) (high*base) << 32; + } + + while ((signed long long )b > 0 && b < rem) { + b = b+b; + d = d+d; + } + + do { + if (rem >= b) { + rem -= b; + res += d; + } + b >>= 1; + d >>= 1; + } while (d); + + *n = res; + return rem; +} diff --git a/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/lib1funcs.S b/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/lib1funcs.S new file mode 100644 index 00000000..6eec708d --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/lib1funcs.S @@ -0,0 +1,323 @@ +/* + * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines + * + * Author: Nicolas Pitre + * - contributed to gcc-3.4 on Sep 30, 2003 + * - adapted for the Linux kernel on Oct 2, 2003 + */ + +/* Copyright 1995, 1996, 1998, 1999, 2000, 2003 Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file into combinations with other programs, +and to distribute those combinations without any restriction coming +from the use of this file. (The General Public License restrictions +do apply in other respects; for example, they cover modification of +the file, and distribution when not linked into a combine +executable.) + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* +#include +#include +*/ + +#define ALIGN .align 4,0x90 +#define __LINUX_ARM_ARCH__ 1 + +#define ENTRY(name) \ + .globl name; \ + ALIGN; \ + name: + +.macro ARM_DIV_BODY dividend, divisor, result, curbit + +#if __LINUX_ARM_ARCH__ >= 5 + + clz \curbit, \divisor + clz \result, \dividend + sub \result, \curbit, \result + mov \curbit, #1 + mov \divisor, \divisor, lsl \result + mov \curbit, \curbit, lsl \result + mov \result, #0 + +#else + + @ Initially shift the divisor left 3 bits if possible, + @ set curbit accordingly. This allows for curbit to be located + @ at the left end of each 4 bit nibbles in the division loop + @ to save one loop in most cases. + tst \divisor, #0xe0000000 + moveq \divisor, \divisor, lsl #3 + moveq \curbit, #8 + movne \curbit, #1 + + @ Unless the divisor is very big, shift it up in multiples of + @ four bits, since this is the amount of unwinding in the main + @ division loop. Continue shifting until the divisor is + @ larger than the dividend. +1: cmp \divisor, #0x10000000 + cmplo \divisor, \dividend + movlo \divisor, \divisor, lsl #4 + movlo \curbit, \curbit, lsl #4 + blo 1b + + @ For very big divisors, we must shift it a bit at a time, or + @ we will be in danger of overflowing. +1: cmp \divisor, #0x80000000 + cmplo \divisor, \dividend + movlo \divisor, \divisor, lsl #1 + movlo \curbit, \curbit, lsl #1 + blo 1b + + mov \result, #0 + +#endif + + @ Division loop +1: cmp \dividend, \divisor + subhs \dividend, \dividend, \divisor + orrhs \result, \result, \curbit + cmp \dividend, \divisor, lsr #1 + subhs \dividend, \dividend, \divisor, lsr #1 + orrhs \result, \result, \curbit, lsr #1 + cmp \dividend, \divisor, lsr #2 + subhs \dividend, \dividend, \divisor, lsr #2 + orrhs \result, \result, \curbit, lsr #2 + cmp \dividend, \divisor, lsr #3 + subhs \dividend, \dividend, \divisor, lsr #3 + orrhs \result, \result, \curbit, lsr #3 + cmp \dividend, #0 @ Early termination? + movnes \curbit, \curbit, lsr #4 @ No, any more bits to do? + movne \divisor, \divisor, lsr #4 + bne 1b + +.endm + + +.macro ARM_DIV2_ORDER divisor, order + +#if __LINUX_ARM_ARCH__ >= 5 + + clz \order, \divisor + rsb \order, \order, #31 + +#else + + cmp \divisor, #(1 << 16) + movhs \divisor, \divisor, lsr #16 + movhs \order, #16 + movlo \order, #0 + + cmp \divisor, #(1 << 8) + movhs \divisor, \divisor, lsr #8 + addhs \order, \order, #8 + + cmp \divisor, #(1 << 4) + movhs \divisor, \divisor, lsr #4 + addhs \order, \order, #4 + + cmp \divisor, #(1 << 2) + addhi \order, \order, #3 + addls \order, \order, \divisor, lsr #1 + +#endif + +.endm + + +.macro ARM_MOD_BODY dividend, divisor, order, spare + +#if __LINUX_ARM_ARCH__ >= 5 + + clz \order, \divisor + clz \spare, \dividend + sub \order, \order, \spare + mov \divisor, \divisor, lsl \order + +#else + + mov \order, #0 + + @ Unless the divisor is very big, shift it up in multiples of + @ four bits, since this is the amount of unwinding in the main + @ division loop. Continue shifting until the divisor is + @ larger than the dividend. +1: cmp \divisor, #0x10000000 + cmplo \divisor, \dividend + movlo \divisor, \divisor, lsl #4 + addlo \order, \order, #4 + blo 1b + + @ For very big divisors, we must shift it a bit at a time, or + @ we will be in danger of overflowing. +1: cmp \divisor, #0x80000000 + cmplo \divisor, \dividend + movlo \divisor, \divisor, lsl #1 + addlo \order, \order, #1 + blo 1b + +#endif + + @ Perform all needed substractions to keep only the reminder. + @ Do comparisons in batch of 4 first. + subs \order, \order, #3 @ yes, 3 is intended here + blt 2f + +1: cmp \dividend, \divisor + subhs \dividend, \dividend, \divisor + cmp \dividend, \divisor, lsr #1 + subhs \dividend, \dividend, \divisor, lsr #1 + cmp \dividend, \divisor, lsr #2 + subhs \dividend, \dividend, \divisor, lsr #2 + cmp \dividend, \divisor, lsr #3 + subhs \dividend, \dividend, \divisor, lsr #3 + cmp \dividend, #1 + mov \divisor, \divisor, lsr #4 + subges \order, \order, #4 + bge 1b + + tst \order, #3 + teqne \dividend, #0 + beq 5f + + @ Either 1, 2 or 3 comparison/substractions are left. +2: cmn \order, #2 + blt 4f + beq 3f + cmp \dividend, \divisor + subhs \dividend, \dividend, \divisor + mov \divisor, \divisor, lsr #1 +3: cmp \dividend, \divisor + subhs \dividend, \dividend, \divisor + mov \divisor, \divisor, lsr #1 +4: cmp \dividend, \divisor + subhs \dividend, \dividend, \divisor +5: +.endm + + +#if 0 +ENTRY(__udivsi3) + + subs r2, r1, #1 + moveq pc, lr + bcc Ldiv0 + cmp r0, r1 + bls 11f + tst r1, r2 + beq 12f + + ARM_DIV_BODY r0, r1, r2, r3 + + mov r0, r2 + mov pc, lr + +11: moveq r0, #1 + movne r0, #0 + mov pc, lr + +12: ARM_DIV2_ORDER r1, r2 + + mov r0, r0, lsr r2 + mov pc, lr + #endif + +ENTRY(__umodsi3) + + subs r2, r1, #1 @ compare divisor with 1 + bcc Ldiv0 + cmpne r0, r1 @ compare dividend with divisor + moveq r0, #0 + tsthi r1, r2 @ see if divisor is power of 2 + andeq r0, r0, r2 + movls pc, lr + + ARM_MOD_BODY r0, r1, r2, r3 + + mov pc, lr + +#if 0 +ENTRY(__divsi3) + + cmp r1, #0 + eor ip, r0, r1 @ save the sign of the result. + beq Ldiv0 + rsbmi r1, r1, #0 @ loops below use unsigned. + subs r2, r1, #1 @ division by 1 or -1 ? + beq 10f + movs r3, r0 + rsbmi r3, r0, #0 @ positive dividend value + cmp r3, r1 + bls 11f + tst r1, r2 @ divisor is power of 2 ? + beq 12f + + ARM_DIV_BODY r3, r1, r0, r2 + + cmp ip, #0 + rsbmi r0, r0, #0 + mov pc, lr + +10: teq ip, r0 @ same sign ? + rsbmi r0, r0, #0 + mov pc, lr + +11: movlo r0, #0 + moveq r0, ip, asr #31 + orreq r0, r0, #1 + mov pc, lr + +12: ARM_DIV2_ORDER r1, r2 + + cmp ip, #0 + mov r0, r3, lsr r2 + rsbmi r0, r0, #0 + mov pc, lr +#endif + +ENTRY(__modsi3) + + cmp r1, #0 + beq Ldiv0 + rsbmi r1, r1, #0 @ loops below use unsigned. + movs ip, r0 @ preserve sign of dividend + rsbmi r0, r0, #0 @ if negative make positive + subs r2, r1, #1 @ compare divisor with 1 + cmpne r0, r1 @ compare dividend with divisor + moveq r0, #0 + tsthi r1, r2 @ see if divisor is power of 2 + andeq r0, r0, r2 + bls 10f + + ARM_MOD_BODY r0, r1, r2, r3 + +10: cmp ip, #0 + rsbmi r0, r0, #0 + mov pc, lr + + +Ldiv0: + + str lr, [sp, #-4]! +/* bl __div0 */ + mov r0, #0 @ About as wrong as it could be. + ldr pc, [sp], #4 + + diff --git a/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/muldi3.c b/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/muldi3.c new file mode 100644 index 00000000..44d611b1 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/muldi3.c @@ -0,0 +1,77 @@ +/* More subroutines needed by GCC output code on some machines. */ +/* Compile this one with gcc. */ +/* Copyright (C) 1989, 92-98, 1999 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you link this library with other files, + some of which are compiled with GCC, to produce an executable, + this library does not by itself cause the resulting executable + to be covered by the GNU General Public License. + This exception does not however invalidate any other reasons why + the executable file might be covered by the GNU General Public License. + */ +/* support functions required by the kernel. based on code from gcc-2.95.3 */ +/* I Molton 29/07/01 */ + +#include "gcclib.h" + +#define umul_ppmm(xh, xl, a, b) \ +{register USItype __t0, __t1, __t2; \ + __asm__ ("%@ Inlined umul_ppmm \n\ + mov %2, %5, lsr #16 \n\ + mov %0, %6, lsr #16 \n\ + bic %3, %5, %2, lsl #16 \n\ + bic %4, %6, %0, lsl #16 \n\ + mul %1, %3, %4 \n\ + mul %4, %2, %4 \n\ + mul %3, %0, %3 \n\ + mul %0, %2, %0 \n\ + adds %3, %4, %3 \n\ + addcs %0, %0, #65536 \n\ + adds %1, %1, %3, lsl #16 \n\ + adc %0, %0, %3, lsr #16" \ + : "=&r" ((USItype) (xh)), \ + "=r" ((USItype) (xl)), \ + "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \ + : "r" ((USItype) (a)), \ + "r" ((USItype) (b)));} + + +#define __umulsidi3(u, v) \ + ({DIunion __w; \ + umul_ppmm (__w.s.high, __w.s.low, u, v); \ + __w.ll; }) + + +DItype +__muldi3 (DItype u, DItype v) +{ + DIunion w; + DIunion uu, vv; + + uu.ll = u, + vv.ll = v; + + w.ll = __umulsidi3 (uu.s.low, vv.s.low); + w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high + + (USItype) uu.s.high * (USItype) vv.s.low); + + return w.ll; +} + diff --git a/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/printf.c b/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/printf.c new file mode 100644 index 00000000..c070bbce --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/printf.c @@ -0,0 +1,60 @@ +#include "vsprintf.h" +#include "string.h" +#include "printf.h" +#include "bsp_uart.h" + +extern void uart_putc(unsigned char c); +extern unsigned char uart_getc(void); + +#define OUTBUFSIZE 1024 +#define INBUFSIZE 1024 + + +static char g_pcOutBuf[OUTBUFSIZE]; +static char g_pcInBuf[INBUFSIZE]; + + +int printf(const char *fmt, ...) +{ + int i; + int len; + va_list args; + + va_start(args, fmt); + len = vsprintf(g_pcOutBuf,fmt,args); + va_end(args); + for (i = 0; i < strlen(g_pcOutBuf); i++) + { + uart_putc(g_pcOutBuf[i]); + } + return len; +} + +int scanf(const char * fmt, ...) +{ + int i = 0; + unsigned char c; + va_list args; + + while(1) + { + c = uart_getc(); + uart_putc(c); + if((c == 0x0d) || (c == 0x0a)) + { + g_pcInBuf[i] = '\0'; + break; + } + else + { + g_pcInBuf[i++] = c; + } + } + + va_start(args,fmt); + i = vsscanf(g_pcInBuf,fmt,args); + va_end(args); + + return i; +} + diff --git a/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/string.c b/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/string.c new file mode 100644 index 00000000..80132285 --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/string.c @@ -0,0 +1,533 @@ +/* + * linux/lib/string.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ + +/* + * stupid library routines.. The optimized versions should generally be found + * as inline code in + * + * These are buggy as well.. + * + * * Fri Jun 25 1999, Ingo Oeser + * - Added strsep() which will replace strtok() soon (because strsep() is + * reentrant and should be faster). Use only strsep() in new code, please. + */ +//#include +//#include +//#include "types.h" +#include "ctype.h" +#include "string.h" + +#ifndef __HAVE_ARCH_STRNICMP +/** + * strnicmp - Case insensitive, length-limited string comparison + * @s1: One string + * @s2: The other string + * @len: the maximum number of characters to compare + */ +int strnicmp(const char *s1, const char *s2, size_t len) +{ + /* Yes, Virginia, it had better be unsigned */ + unsigned char c1, c2; + + c1 = 0; c2 = 0; + if (len) { + do { + c1 = *s1; c2 = *s2; + s1++; s2++; + if (!c1) + break; + if (!c2) + break; + if (c1 == c2) + continue; + c1 = tolower(c1); + c2 = tolower(c2); + if (c1 != c2) + break; + } while (--len); + } + return (int)c1 - (int)c2; +} +#endif + +char * ___strtok; + +#ifndef __HAVE_ARCH_STRCPY +/** + * strcpy - Copy a %NUL terminated string + * @dest: Where to copy the string to + * @src: Where to copy the string from + */ +char * strcpy(char * dest,const char *src) +{ + char *tmp = dest; + + while ((*dest++ = *src++) != '\0') + /* nothing */; + return tmp; +} +#endif + +#ifndef __HAVE_ARCH_STRNCPY +/** + * strncpy - Copy a length-limited, %NUL-terminated string + * @dest: Where to copy the string to + * @src: Where to copy the string from + * @count: The maximum number of bytes to copy + * + * Note that unlike userspace strncpy, this does not %NUL-pad the buffer. + * However, the result is not %NUL-terminated if the source exceeds + * @count bytes. + */ +char * strncpy(char * dest,const char *src,size_t count) +{ + char *tmp = dest; + + while (count-- && (*dest++ = *src++) != '\0') + /* nothing */; + + return tmp; +} +#endif + +#ifndef __HAVE_ARCH_STRCAT +/** + * strcat - Append one %NUL-terminated string to another + * @dest: The string to be appended to + * @src: The string to append to it + */ +char * strcat(char * dest, const char * src) +{ + char *tmp = dest; + + while (*dest) + dest++; + while ((*dest++ = *src++) != '\0') + ; + + return tmp; +} +#endif + +#ifndef __HAVE_ARCH_STRNCAT +/** + * strncat - Append a length-limited, %NUL-terminated string to another + * @dest: The string to be appended to + * @src: The string to append to it + * @count: The maximum numbers of bytes to copy + * + * Note that in contrast to strncpy, strncat ensures the result is + * terminated. + */ +char * strncat(char *dest, const char *src, size_t count) +{ + char *tmp = dest; + + if (count) { + while (*dest) + dest++; + while ((*dest++ = *src++)) { + if (--count == 0) { + *dest = '\0'; + break; + } + } + } + + return tmp; +} +#endif + +#ifndef __HAVE_ARCH_STRCMP +/** + * strcmp - Compare two strings + * @cs: One string + * @ct: Another string + */ +int strcmp(const char * cs,const char * ct) +{ + register signed char __res; + + while (1) { + if ((__res = *cs - *ct++) != 0 || !*cs++) + break; + } + + return __res; +} +#endif + +#ifndef __HAVE_ARCH_STRNCMP +/** + * strncmp - Compare two length-limited strings + * @cs: One string + * @ct: Another string + * @count: The maximum number of bytes to compare + */ +int strncmp(const char * cs,const char * ct,size_t count) +{ + register signed char __res = 0; + + while (count) { + if ((__res = *cs - *ct++) != 0 || !*cs++) + break; + count--; + } + + return __res; +} +#endif + +#ifndef __HAVE_ARCH_STRCHR +/** + * strchr - Find the first occurrence of a character in a string + * @s: The string to be searched + * @c: The character to search for + */ +char * strchr(const char * s, int c) +{ + for(; *s != (char) c; ++s) + if (*s == '\0') + return NULL; + return (char *) s; +} +#endif + +#ifndef __HAVE_ARCH_STRRCHR +/** + * strrchr - Find the last occurrence of a character in a string + * @s: The string to be searched + * @c: The character to search for + */ +char * strrchr(const char * s, int c) +{ + const char *p = s + strlen(s); + do { + if (*p == (char)c) + return (char *)p; + } while (--p >= s); + return NULL; +} +#endif + +#ifndef __HAVE_ARCH_STRLEN +/** + * strlen - Find the length of a string + * @s: The string to be sized + */ +size_t strlen(const char * s) +{ + const char *sc; + + for (sc = s; *sc != '\0'; ++sc) + /* nothing */; + return sc - s; +} +#endif + +#ifndef __HAVE_ARCH_STRNLEN +/** + * strnlen - Find the length of a length-limited string + * @s: The string to be sized + * @count: The maximum number of bytes to search + */ +size_t strnlen(const char * s, size_t count) +{ + const char *sc; + + for (sc = s; count-- && *sc != '\0'; ++sc) + /* nothing */; + return sc - s; +} +#endif + +#ifndef __HAVE_ARCH_STRSPN +/** + * strspn - Calculate the length of the initial substring of @s which only + * contain letters in @accept + * @s: The string to be searched + * @accept: The string to search for + */ +size_t strspn(const char *s, const char *accept) +{ + const char *p; + const char *a; + size_t count = 0; + + for (p = s; *p != '\0'; ++p) { + for (a = accept; *a != '\0'; ++a) { + if (*p == *a) + break; + } + if (*a == '\0') + return count; + ++count; + } + + return count; +} +#endif + +#ifndef __HAVE_ARCH_STRPBRK +/** + * strpbrk - Find the first occurrence of a set of characters + * @cs: The string to be searched + * @ct: The characters to search for + */ +char * strpbrk(const char * cs,const char * ct) +{ + const char *sc1,*sc2; + + for( sc1 = cs; *sc1 != '\0'; ++sc1) { + for( sc2 = ct; *sc2 != '\0'; ++sc2) { + if (*sc1 == *sc2) + return (char *) sc1; + } + } + return NULL; +} +#endif + +#ifndef __HAVE_ARCH_STRTOK +/** + * strtok - Split a string into tokens + * @s: The string to be searched + * @ct: The characters to search for + * + * WARNING: strtok is deprecated, use strsep instead. + */ +char * strtok(char * s,const char * ct) +{ + char *sbegin, *send; + + sbegin = s ? s : ___strtok; + if (!sbegin) { + return NULL; + } + sbegin += strspn(sbegin,ct); + if (*sbegin == '\0') { + ___strtok = NULL; + return( NULL ); + } + send = strpbrk( sbegin, ct); + if (send && *send != '\0') + *send++ = '\0'; + ___strtok = send; + return (sbegin); +} +#endif + +#ifndef __HAVE_ARCH_STRSEP +/** + * strsep - Split a string into tokens + * @s: The string to be searched + * @ct: The characters to search for + * + * strsep() updates @s to point after the token, ready for the next call. + * + * It returns empty tokens, too, behaving exactly like the libc function + * of that name. In fact, it was stolen from glibc2 and de-fancy-fied. + * Same semantics, slimmer shape. ;) + */ +char * strsep(char **s, const char *ct) +{ + char *sbegin = *s, *end; + + if (sbegin == NULL) + return NULL; + + end = strpbrk(sbegin, ct); + if (end) + *end++ = '\0'; + *s = end; + + return sbegin; +} +#endif + +#ifndef __HAVE_ARCH_MEMSET +/** + * memset - Fill a region of memory with the given value + * @s: Pointer to the start of the area. + * @c: The byte to fill the area with + * @count: The size of the area. + * + * Do not use memset() to access IO space, use memset_io() instead. + */ +void * memset(void * s,int c,size_t count) +{ + char *xs = (char *) s; + + while (count--) + *xs++ = c; + + return s; +} +#endif + +#ifndef __HAVE_ARCH_BCOPY +/** + * bcopy - Copy one area of memory to another + * @src: Where to copy from + * @dest: Where to copy to + * @count: The size of the area. + * + * Note that this is the same as memcpy(), with the arguments reversed. + * memcpy() is the standard, bcopy() is a legacy BSD function. + * + * You should not use this function to access IO space, use memcpy_toio() + * or memcpy_fromio() instead. + */ +void bcopy(const void *src, void *dest, size_t count) +{ + char *destTmp = (char *)dest; + char *srcTmp = (char *)src; + + while (count--) + *destTmp++ = *srcTmp++; +} +#endif + +#ifndef __HAVE_ARCH_MEMCPY +/** + * memcpy - Copy one area of memory to another + * @dest: Where to copy to + * @src: Where to copy from + * @count: The size of the area. + * + * You should not use this function to access IO space, use memcpy_toio() + * or memcpy_fromio() instead. + */ +void * memcpy(void * dest,const void *src,size_t count) +{ + char *tmp = (char *) dest, *s = (char *) src; + + while (count--) + *tmp++ = *s++; + + return dest; +} +#endif + +#ifndef __HAVE_ARCH_MEMMOVE +/** + * memmove - Copy one area of memory to another + * @dest: Where to copy to + * @src: Where to copy from + * @count: The size of the area. + * + * Unlike memcpy(), memmove() copes with overlapping areas. + */ +void * memmove(void * dest,const void *src,size_t count) +{ + char *tmp, *s; + + if (dest <= src) { + tmp = (char *) dest; + s = (char *) src; + while (count--) + *tmp++ = *s++; + } + else { + tmp = (char *) dest + count; + s = (char *) src + count; + while (count--) + *--tmp = *--s; + } + + return dest; +} +#endif + +#ifndef __HAVE_ARCH_MEMCMP +/** + * memcmp - Compare two areas of memory + * @cs: One area of memory + * @ct: Another area of memory + * @count: The size of the area. + */ +int memcmp(const void * cs,const void * ct,size_t count) +{ + const unsigned char *su1, *su2; + int res = 0; + + for( su1 = (const unsigned char *)cs, su2 = (const unsigned char *)ct; 0 < count; ++su1, ++su2, count--) + if ((res = *su1 - *su2) != 0) + break; + return res; +} +#endif + +#ifndef __HAVE_ARCH_MEMSCAN +/** + * memscan - Find a character in an area of memory. + * @addr: The memory area + * @c: The byte to search for + * @size: The size of the area. + * + * returns the address of the first occurrence of @c, or 1 byte past + * the area if @c is not found + */ +void * memscan(void * addr, int c, size_t size) +{ + unsigned char * p = (unsigned char *) addr; + + while (size) { + if (*p == c) + return (void *) p; + p++; + size--; + } + return (void *) p; +} +#endif + +#ifndef __HAVE_ARCH_STRSTR +/** + * strstr - Find the first substring in a %NUL terminated string + * @s1: The string to be searched + * @s2: The string to search for + */ +char * strstr(const char * s1,const char * s2) +{ + int l1, l2; + + l2 = strlen(s2); + if (!l2) + return (char *) s1; + l1 = strlen(s1); + while (l1 >= l2) { + l1--; + if (!memcmp(s1,s2,l2)) + return (char *) s1; + s1++; + } + return NULL; +} +#endif + +#ifndef __HAVE_ARCH_MEMCHR +/** + * memchr - Find a character in an area of memory. + * @s: The memory area + * @c: The byte to search for + * @n: The size of the area. + * + * returns the address of the first occurrence of @c, or %NULL + * if @c is not found + */ +void *memchr(const void *s, int c, size_t n) +{ + const unsigned char *p = (const unsigned char *)s; + while (n-- != 0) { + if ((unsigned char)c == *p++) { + return (void *)(p-1); + } + } + return NULL; +} + +#endif diff --git a/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/vsprintf.c b/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/vsprintf.c new file mode 100644 index 00000000..a1bb97bc --- /dev/null +++ b/board/ALPHA_I.MX_emmc_256ddr/stdio/lib/vsprintf.c @@ -0,0 +1,1066 @@ +/* + * linux/lib/vsprintf.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ + +/* vsprintf.c -- Lars Wirzenius & Linus Torvalds. */ +/* + * Wirzenius wrote this portably, Torvalds fucked it up :-) + */ + +/* + * Fri Jul 13 2001 Crutcher Dunnavant + * - changed to provide snprintf and vsnprintf functions + * So Feb 1 16:51:32 CET 2004 Juergen Quade + * - scnprintf and vscnprintf + */ + +//#include +//#include +#include "types.h" +#include "kernel.h" + +#include "ctype.h" +#include "string.h" +#include "div64.h" +#include "vsprintf.h" +#include "bsp_uart.h" + +#define unlikely(x) __builtin_expect(!!(x), 0) + +#define ADDCH(str, ch) do { \ + if ((str) < end) \ + *(str) = (ch); \ + ++str; \ + } while (0) + + +/** + * simple_strtoul - convert a string to an unsigned long + * @cp: The start of the string + * @endp: A pointer to the end of the parsed string will be placed here + * @base: The number base to use + */ +unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base) +{ + unsigned long result = 0,value; + + if (!base) { + base = 10; + if (*cp == '0') { + base = 8; + cp++; + if ((toupper(*cp) == 'X') && isxdigit(cp[1])) { + cp++; + base = 16; + } + } + } else if (base == 16) { + if (cp[0] == '0' && toupper(cp[1]) == 'X') + cp += 2; + } + while (isxdigit(*cp) && + (value = isdigit(*cp) ? *cp-'0' : toupper(*cp)-'A'+10) < base) { + result = result*base + value; + cp++; + } + if (endp) + *endp = (char *)cp; + return result; +} + +//EXPORT_SYMBOL(simple_strtoul); + +/** + * simple_strtol - convert a string to a signed long + * @cp: The start of the string + * @endp: A pointer to the end of the parsed string will be placed here + * @base: The number base to use + */ +long simple_strtol(const char *cp,char **endp,unsigned int base) +{ + if(*cp=='-') + return -simple_strtoul(cp+1,endp,base); + return simple_strtoul(cp,endp,base); +} + +//EXPORT_SYMBOL(simple_strtol); + +/** + * simple_strtoull - convert a string to an unsigned long long + * @cp: The start of the string + * @endp: A pointer to the end of the parsed string will be placed here + * @base: The number base to use + */ +unsigned long long simple_strtoull(const char *cp,char **endp,unsigned int base) +{ + unsigned long long result = 0,value; + + if (!base) { + base = 10; + if (*cp == '0') { + base = 8; + cp++; + if ((toupper(*cp) == 'X') && isxdigit(cp[1])) { + cp++; + base = 16; + } + } + } else if (base == 16) { + if (cp[0] == '0' && toupper(cp[1]) == 'X') + cp += 2; + } + while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp) + ? toupper(*cp) : *cp)-'A'+10) < base) { + result = result*base + value; + cp++; + } + if (endp) + *endp = (char *)cp; + return result; +} + +//EXPORT_SYMBOL(simple_strtoull); + +/** + * simple_strtoll - convert a string to a signed long long + * @cp: The start of the string + * @endp: A pointer to the end of the parsed string will be placed here + * @base: The number base to use + */ +long long simple_strtoll(const char *cp,char **endp,unsigned int base) +{ + if(*cp=='-') + return -simple_strtoull(cp+1,endp,base); + return simple_strtoull(cp,endp,base); +} + +static int skip_atoi(const char **s) +{ + int i=0; + + while (isdigit(**s)) + i = i*10 + *((*s)++) - '0'; + return i; +} + +#define ZEROPAD 1 /* pad with zero */ +#define SIGN 2 /* unsigned/signed long */ +#define PLUS 4 /* show plus */ +#define SPACE 8 /* space if plus */ +#define LEFT 16 /* left justified */ +#define SPECIAL 32 /* 0x */ +#define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */ + +#define SMALL 32 /* Must be 32 == 0x20 */ + + + +//static char * number(char * buf, char * end, unsigned long long num, int base, int size, int precision, int type) +static char *put_dec_trunc(char *buf, unsigned q) +{ + unsigned d3, d2, d1, d0; + d1 = (q>>4) & 0xf; + d2 = (q>>8) & 0xf; + d3 = (q>>12); + + d0 = 6*(d3 + d2 + d1) + (q & 0xf); + q = (d0 * 0xcd) >> 11; + d0 = d0 - 10*q; + *buf++ = d0 + '0'; /* least significant digit */ + d1 = q + 9*d3 + 5*d2 + d1; + if (d1 != 0) { + q = (d1 * 0xcd) >> 11; + d1 = d1 - 10*q; + *buf++ = d1 + '0'; /* next digit */ + + d2 = q + 2*d2; + if ((d2 != 0) || (d3 != 0)) { + q = (d2 * 0xd) >> 7; + d2 = d2 - 10*q; + *buf++ = d2 + '0'; /* next digit */ + + d3 = q + 4*d3; + if (d3 != 0) { + q = (d3 * 0xcd) >> 11; + d3 = d3 - 10*q; + *buf++ = d3 + '0'; /* next digit */ + if (q != 0) + *buf++ = q + '0'; /* most sign. digit */ + } + } + } + return buf; +} + +/* Same with if's removed. Always emits five digits */ +static char *put_dec_full(char *buf, unsigned q) +{ + /* BTW, if q is in [0,9999], 8-bit ints will be enough, */ + /* but anyway, gcc produces better code with full-sized ints */ + unsigned d3, d2, d1, d0; + d1 = (q>>4) & 0xf; + d2 = (q>>8) & 0xf; + d3 = (q>>12); + + /* + * Possible ways to approx. divide by 10 + * gcc -O2 replaces multiply with shifts and adds + * (x * 0xcd) >> 11: 11001101 - shorter code than * 0x67 (on i386) + * (x * 0x67) >> 10: 1100111 + * (x * 0x34) >> 9: 110100 - same + * (x * 0x1a) >> 8: 11010 - same + * (x * 0x0d) >> 7: 1101 - same, shortest code (on i386) + */ + + d0 = 6*(d3 + d2 + d1) + (q & 0xf); + q = (d0 * 0xcd) >> 11; + d0 = d0 - 10*q; + *buf++ = d0 + '0'; + d1 = q + 9*d3 + 5*d2 + d1; + q = (d1 * 0xcd) >> 11; + d1 = d1 - 10*q; + *buf++ = d1 + '0'; + + d2 = q + 2*d2; + q = (d2 * 0xd) >> 7; + d2 = d2 - 10*q; + *buf++ = d2 + '0'; + + d3 = q + 4*d3; + q = (d3 * 0xcd) >> 11; /* - shorter code */ + /* q = (d3 * 0x67) >> 10; - would also work */ + d3 = d3 - 10*q; + *buf++ = d3 + '0'; + *buf++ = q + '0'; + return buf; +} + +/* No inlining helps gcc to use registers better */ +static char *put_dec(char *buf, uint64_t num) +{ + while (1) { + unsigned rem; + if (num < 100000) + return put_dec_trunc(buf, num); + rem = do_div(num, 100000); + buf = put_dec_full(buf, rem); + } +} + +static char *number(char *buf, char *end, signed long long num, int base, int size, int precision, int type) +{ + /* we are called with base 8, 10 or 16, only, thus don't need "G..." */ + static const char digits[16] = "0123456789ABCDEF"; + + char tmp[100]; + char sign; + char locase; + int need_pfx = ((type & SPECIAL) && base != 10); + int i; + + /* locase = 0 or 0x20. ORing digits or letters with 'locase' + * produces same digits or (maybe lowercased) letters */ + locase = (type & SMALL); + if (type & LEFT) + type &= ~ZEROPAD; + sign = 0; + + if (type & SIGN) { + if (num < 0) { + sign = '-'; + num = - num; + size--; + + } else if (type & PLUS) { + sign = '+'; + size--; + } else if (type & SPACE) { + sign = ' '; + size--; + } + } + if (need_pfx) { + size--; + if (base == 16) + size--; + + } + + /* generate full string in tmp[], in reverse order */ + i = 0; + if (num == 0) + tmp[i++] = '0'; + /* Generic code, for any base: + else do { + tmp[i++] = (digits[do_div(num,base)] | locase); + } while (num != 0); + */ + else if (base != 10) { /* 8 or 16 */ + int mask = base - 1; + int shift = 3; + + if (base == 16) + shift = 4; + + do { + tmp[i++] = (digits[((unsigned char)num) & mask] + | locase); + num >>= shift; + } while (num); + } else { /* base 10 */ + i = put_dec(tmp, num) - tmp; + } + /* printing 100 using %2d gives "100", not "00" */ + if (i > precision) + precision = i; + /* leading space padding */ + size -= precision; + if (!(type & (ZEROPAD + LEFT))) { + while (--size >= 0) + ADDCH(buf, ' '); + } + /* sign */ + if (sign) + ADDCH(buf, sign); + /* "0x" / "0" prefix */ + if (need_pfx) { + ADDCH(buf, '0'); + if (base == 16) + ADDCH(buf, 'X' | locase); + } + /* zero or space padding */ + if (!(type & LEFT)) { + char c = (type & ZEROPAD) ? '0' : ' '; + + while (--size >= 0) + ADDCH(buf, c); + } + /* hmm even more zero padding? */ + while (i <= --precision) + ADDCH(buf, '0'); + /* actual digits of result */ + while (--i >= 0) + ADDCH(buf, tmp[i]); + /* trailing space padding */ + while (--size >= 0) + ADDCH(buf, ' '); + return buf; +} + +#if 0 +static char * number(char * buf, char * end, unsigned long long num, int base, int size, int precision, int type) +{ + char c,sign,tmp[66]; + const char *digits; + static const char small_digits[] = "0123456789abcdefghijklmnopqrstuvwxyz"; + static const char large_digits[] = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; + int i; + + puts("digits\r\n"); + digits = (type & LARGE) ? large_digits : small_digits; + if (type & LEFT) + type &= ~ZEROPAD; + if (base < 2 || base > 36) + return NULL; + c = (type & ZEROPAD) ? '0' : ' '; + sign = 0; + if (type & SIGN) { + if ((signed long long) num < 0) { + sign = '-'; + num = - (signed long long) num; + size--; + } else if (type & PLUS) { + sign = '+'; + size--; + } else if (type & SPACE) { + sign = ' '; + size--; + } + } + if (type & SPECIAL) { + if (base == 16) + size -= 2; + else if (base == 8) + size--; + } + i = 0; + if (num == 0) + tmp[i++]='0'; + else while (num != 0) + tmp[i++] = digits[do_div(num,base)]; + if (i > precision) + precision = i; + size -= precision; + if (!(type&(ZEROPAD+LEFT))) { + while(size-->0) { + if (buf <= end) + *buf = ' '; + ++buf; + } + } + if (sign) { + if (buf <= end) + *buf = sign; + ++buf; + } + if (type & SPECIAL) { + if (base==8) { + if (buf <= end) + *buf = '0'; + ++buf; + } else if (base==16) { + if (buf <= end) + *buf = '0'; + ++buf; + if (buf <= end) + *buf = digits[33]; + ++buf; + } + } + puts("type&LEFT\r\n"); + if (!(type & LEFT)) { + while (size-- > 0) { + if (buf <= end) + *buf = c; + ++buf; + } + } + while (i < precision--) { + if (buf <= end) + *buf = '0'; + ++buf; + } + while (i-- > 0) { + if (buf <= end) + *buf = tmp[i]; + ++buf; + } + while (size-- > 0) { + if (buf <= end) + *buf = ' '; + ++buf; + } + return buf; +} +#endif +/** + * vsnprintf - Format a string and place it in a buffer + * @buf: The buffer to place the result into + * @size: The size of the buffer, including the trailing null space + * @fmt: The format string to use + * @args: Arguments for the format string + * + * The return value is the number of characters which would + * be generated for the given input, excluding the trailing + * '\0', as per ISO C99. If you want to have the exact + * number of characters written into @buf as return value + * (not including the trailing '\0'), use vscnprintf. If the + * return is greater than or equal to @size, the resulting + * string is truncated. + * + * Call this function if you are already dealing with a va_list. + * You probably want snprintf instead. + */ +int vsnprintf(char *buf, size_t size, const char *fmt, va_list args) +{ + int len; + unsigned long long num; + int i, base; + char *str, *end, c; + const char *s; + + int flags; /* flags to number() */ + + int field_width; /* width of output field */ + int precision; /* min. # of digits for integers; max + number of chars for from string */ + int qualifier; /* 'h', 'l', or 'L' for integer fields */ + /* 'z' support added 23/7/1999 S.H. */ + /* 'z' changed to 'Z' --davidm 1/25/99 */ + + /* Reject out-of-range values early */ + if (unlikely((int) size < 0)) { + /* There can be only one.. */ +// static int warn = 1; +// WARN_ON(warn); +// warn = 0; + return 0; + } + + str = buf; + end = buf + size - 1; + + if (end < buf - 1) { + end = ((void *) -1); + size = end - buf + 1; + } + + for (; *fmt ; ++fmt) { + if (*fmt != '%') { + if (str <= end) + *str = *fmt; + ++str; + continue; + } + + /* process flags */ + flags = 0; + repeat: + ++fmt; /* this also skips first '%' */ + switch (*fmt) { + case '-': flags |= LEFT; goto repeat; + case '+': flags |= PLUS; goto repeat; + case ' ': flags |= SPACE; goto repeat; + case '#': flags |= SPECIAL; goto repeat; + case '0': flags |= ZEROPAD; goto repeat; + } + /* get field width */ + field_width = -1; + if (isdigit(*fmt)) + field_width = skip_atoi(&fmt); + else if (*fmt == '*') { + ++fmt; + /* it's the next argument */ + field_width = va_arg(args, int); + if (field_width < 0) { + field_width = -field_width; + flags |= LEFT; + } + } + + /* get the precision */ + precision = -1; + if (*fmt == '.') { + ++fmt; + if (isdigit(*fmt)) + precision = skip_atoi(&fmt); + else if (*fmt == '*') { + ++fmt; + /* it's the next argument */ + precision = va_arg(args, int); + } + if (precision < 0) + precision = 0; + } + + /* get the conversion qualifier */ + qualifier = -1; + if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' || + *fmt =='Z' || *fmt == 'z') { + qualifier = *fmt; + ++fmt; + if (qualifier == 'l' && *fmt == 'l') { + qualifier = 'L'; + ++fmt; + } + } + + /* default base */ + base = 10; + + switch (*fmt) { + + case 'c': + if (!(flags & LEFT)) { + while (--field_width > 0) { + if (str <= end) + *str = ' '; + ++str; + } + } + c = (unsigned char) va_arg(args, int); + if (str <= end) + *str = c; + ++str; + while (--field_width > 0) { + if (str <= end) + *str = ' '; + ++str; + } + continue; + + case 's': + s = va_arg(args, char *); + if ((unsigned long)s < 1024)//PAGE_SIZE) + s = ""; + + len = strnlen(s, precision); + + if (!(flags & LEFT)) { + while (len < field_width--) { + if (str <= end) + *str = ' '; + ++str; + } + } + for (i = 0; i < len; ++i) { + if (str <= end) + *str = *s; + ++str; ++s; + } + while (len < field_width--) { + if (str <= end) + *str = ' '; + ++str; + } + continue; + + case 'p': + if (field_width == -1) { + field_width = 2*sizeof(void *); + flags |= ZEROPAD; + } + str = number(str, end, + (unsigned long) va_arg(args, void *), + 16, field_width, precision, flags); + continue; + + + case 'n': + /* FIXME: + * What does C99 say about the overflow case here? */ + if (qualifier == 'l') { + long * ip = va_arg(args, long *); + *ip = (str - buf); + } else if (qualifier == 'Z' || qualifier == 'z') { + size_t * ip = va_arg(args, size_t *); + *ip = (str - buf); + } else { + int * ip = va_arg(args, int *); + *ip = (str - buf); + } + continue; + + case '%': + if (str <= end) + *str = '%'; + ++str; + continue; + + /* integer number formats - set up the flags and "break" */ + case 'o': + base = 8; + break; + + case 'X': + flags |= LARGE; + case 'x': + base = 16; + break; + + case 'd': + case 'i': + flags |= SIGN; + case 'u': + break; + + default: + if (str <= end) + *str = '%'; + ++str; + if (*fmt) { + if (str <= end) + *str = *fmt; + ++str; + } else { + --fmt; + } + continue; + } + + if (qualifier == 'L') + num = va_arg(args, unsigned long long); + else if (qualifier == 'l') { + num = va_arg(args, unsigned long); + if (flags & SIGN) + num = (signed long) num; + } else if (qualifier == 'Z' || qualifier == 'z') { + num = va_arg(args, size_t); + } else if (qualifier == 'h') { + num = (unsigned short) va_arg(args, int); + if (flags & SIGN) + num = (signed short) num; + } else { + num = va_arg(args, unsigned int); + if (flags & SIGN) + num = (signed int) num; + } + str = number(str, end, num, base, + field_width, precision, flags); + } + if (str <= end) + *str = '\0'; + else if (size > 0) + /* don't write out a null byte if the buf size is zero */ + *end = '\0'; + /* the trailing null byte doesn't count towards the total + * ++str; + */ + return str-buf; +} + +//EXPORT_SYMBOL(vsnprintf); + +/** + * vscnprintf - Format a string and place it in a buffer + * @buf: The buffer to place the result into + * @size: The size of the buffer, including the trailing null space + * @fmt: The format string to use + * @args: Arguments for the format string + * + * The return value is the number of characters which have been written into + * the @buf not including the trailing '\0'. If @size is <= 0 the function + * returns 0. + * + * Call this function if you are already dealing with a va_list. + * You probably want scnprintf instead. + */ +int vscnprintf(char *buf, size_t size, const char *fmt, va_list args) +{ + int i; + + i=vsnprintf(buf,size,fmt,args); + return (i >= size) ? (size - 1) : i; +} + +//EXPORT_SYMBOL(vscnprintf); + +/** + * snprintf - Format a string and place it in a buffer + * @buf: The buffer to place the result into + * @size: The size of the buffer, including the trailing null space + * @fmt: The format string to use + * @...: Arguments for the format string + * + * The return value is the number of characters which would be + * generated for the given input, excluding the trailing null, + * as per ISO C99. If the return is greater than or equal to + * @size, the resulting string is truncated. + */ +int snprintf(char * buf, size_t size, const char *fmt, ...) +{ + va_list args; + int i; + + va_start(args, fmt); + i=vsnprintf(buf,size,fmt,args); + va_end(args); + return i; +} + +//EXPORT_SYMBOL(snprintf); + +/** + * scnprintf - Format a string and place it in a buffer + * @buf: The buffer to place the result into + * @size: The size of the buffer, including the trailing null space + * @fmt: The format string to use + * @...: Arguments for the format string + * + * The return value is the number of characters written into @buf not including + * the trailing '\0'. If @size is <= 0 the function returns 0. If the return is + * greater than or equal to @size, the resulting string is truncated. + */ + +int scnprintf(char * buf, size_t size, const char *fmt, ...) +{ + va_list args; + int i; + + va_start(args, fmt); + i = vsnprintf(buf, size, fmt, args); + va_end(args); + return (i >= size) ? (size - 1) : i; +} +//EXPORT_SYMBOL(scnprintf); + + +/** + * vsprintf - Format a string and place it in a buffer + * @buf: The buffer to place the result into + * @fmt: The format string to use + * @args: Arguments for the format string + * + * The function returns the number of characters written + * into @buf. Use vsnprintf or vscnprintf in order to avoid + * buffer overflows. + * + * Call this function if you are already dealing with a va_list. + * You probably want sprintf instead. + */ +int vsprintf(char *buf, const char *fmt, va_list args) +{ + return vsnprintf(buf, (~0U)>>1, fmt, args); +} + +//EXPORT_SYMBOL(vsprintf); + +/** + * sprintf - Format a string and place it in a buffer + * @buf: The buffer to place the result into + * @fmt: The format string to use + * @...: Arguments for the format string + * + * The function returns the number of characters written + * into @buf. Use snprintf or scnprintf in order to avoid + * buffer overflows. + */ +int sprintf(char * buf, const char *fmt, ...) +{ + va_list args; + int i; + + va_start(args, fmt); +/* putc('P'); + putc(0x0d); + putc(0x0a); +*/ + i=vsprintf(buf,fmt,args); +/* putc('E'); + putc(0x0d); + putc(0x0a); +*/ + va_end(args); + return i; +} + +//EXPORT_SYMBOL(sprintf); + +/** + * vsscanf - Unformat a buffer into a list of arguments + * @buf: input buffer + * @fmt: format of buffer + * @args: arguments + */ +int vsscanf(const char * buf, const char * fmt, va_list args) +{ + const char *str = buf; + char *next; + char digit; + int num = 0; + int qualifier; + int base; + int field_width; + int is_sign = 0; + + while(*fmt && *str) { + /* skip any white space in format */ + /* white space in format matchs any amount of + * white space, including none, in the input. + */ + if (isspace(*fmt)) { + while (isspace(*fmt)) + ++fmt; + while (isspace(*str)) + ++str; + } + + /* anything that is not a conversion must match exactly */ + if (*fmt != '%' && *fmt) { + if (*fmt++ != *str++) + break; + continue; + } + + if (!*fmt) + break; + ++fmt; + + /* skip this conversion. + * advance both strings to next white space + */ + if (*fmt == '*') { + while (!isspace(*fmt) && *fmt) + fmt++; + while (!isspace(*str) && *str) + str++; + continue; + } + + /* get field width */ + field_width = -1; + if (isdigit(*fmt)) + field_width = skip_atoi(&fmt); + + /* get conversion qualifier */ + qualifier = -1; + if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' || + *fmt == 'Z' || *fmt == 'z') { + qualifier = *fmt++; + if (unlikely(qualifier == *fmt)) { + if (qualifier == 'h') { + qualifier = 'H'; + fmt++; + } else if (qualifier == 'l') { + qualifier = 'L'; + fmt++; + } + } + } + base = 10; + is_sign = 0; + + if (!*fmt || !*str) + break; + + switch(*fmt++) { + case 'c': + { + char *s = (char *) va_arg(args,char*); + if (field_width == -1) + field_width = 1; + do { + *s++ = *str++; + } while (--field_width > 0 && *str); + num++; + } + continue; + case 's': + { + char *s = (char *) va_arg(args, char *); + if(field_width == -1) + field_width = INT_MAX; + /* first, skip leading white space in buffer */ + while (isspace(*str)) + str++; + + /* now copy until next white space */ + while (*str && !isspace(*str) && field_width--) { + *s++ = *str++; + } + *s = '\0'; + num++; + } + continue; + case 'n': + /* return number of characters read so far */ + { + int *i = (int *)va_arg(args,int*); + *i = str - buf; + } + continue; + case 'o': + base = 8; + break; + case 'x': + case 'X': + base = 16; + break; + case 'i': + base = 0; + case 'd': + is_sign = 1; + case 'u': + break; + case '%': + /* looking for '%' in str */ + if (*str++ != '%') + return num; + continue; + default: + /* invalid format; stop here */ + return num; + } + + /* have some sort of integer conversion. + * first, skip white space in buffer. + */ + while (isspace(*str)) + str++; + + digit = *str; + if (is_sign && digit == '-') + digit = *(str + 1); + + if (!digit + || (base == 16 && !isxdigit(digit)) + || (base == 10 && !isdigit(digit)) + || (base == 8 && (!isdigit(digit) || digit > '7')) + || (base == 0 && !isdigit(digit))) + break; + + switch(qualifier) { + case 'H': /* that's 'hh' in format */ + if (is_sign) { + signed char *s = (signed char *) va_arg(args,signed char *); + *s = (signed char) simple_strtol(str,&next,base); + } else { + unsigned char *s = (unsigned char *) va_arg(args, unsigned char *); + *s = (unsigned char) simple_strtoul(str, &next, base); + } + break; + case 'h': + if (is_sign) { + short *s = (short *) va_arg(args,short *); + *s = (short) simple_strtol(str,&next,base); + } else { + unsigned short *s = (unsigned short *) va_arg(args, unsigned short *); + *s = (unsigned short) simple_strtoul(str, &next, base); + } + break; + case 'l': + if (is_sign) { + long *l = (long *) va_arg(args,long *); + *l = simple_strtol(str,&next,base); + } else { + unsigned long *l = (unsigned long*) va_arg(args,unsigned long*); + *l = simple_strtoul(str,&next,base); + } + break; + case 'L': + if (is_sign) { + long long *l = (long long*) va_arg(args,long long *); + *l = simple_strtoll(str,&next,base); + } else { + unsigned long long *l = (unsigned long long*) va_arg(args,unsigned long long*); + *l = simple_strtoull(str,&next,base); + } + break; + case 'Z': + case 'z': + { + size_t *s = (size_t*) va_arg(args,size_t*); + *s = (size_t) simple_strtoul(str,&next,base); + } + break; + default: + if (is_sign) { + int *i = (int *) va_arg(args, int*); + *i = (int) simple_strtol(str,&next,base); + } else { + unsigned int *i = (unsigned int*) va_arg(args, unsigned int*); + *i = (unsigned int) simple_strtoul(str,&next,base); + } + break; + } + num++; + + if (!next) + break; + str = next; + } + return num; +} + +//EXPORT_SYMBOL(vsscanf); + +/** + * sscanf - Unformat a buffer into a list of arguments + * @buf: input buffer + * @fmt: formatting of buffer + * @...: resulting arguments + */ +int sscanf(const char * buf, const char * fmt, ...) +{ + va_list args; + int i; + + va_start(args,fmt); + i = vsscanf(buf,fmt,args); + va_end(args); + return i; +} + +//EXPORT_SYMBOL(sscanf); diff --git a/components/shell/tos_shell.c b/components/shell/tos_shell.c index 88ec9bdd..db023b30 100644 --- a/components/shell/tos_shell.c +++ b/components/shell/tos_shell.c @@ -101,7 +101,7 @@ __STATIC__ void shell_cmd_process(void) ++pos; } - while ((*pos == ' ' || *pos == '\t') && *pos) { + while (*pos == ' ' || *pos == '\t') { *pos++ = '\0'; } diff --git a/kernel/core/include/tos_slist.h b/kernel/core/include/tos_slist.h index 262e867e..1a92dc51 100644 --- a/kernel/core/include/tos_slist.h +++ b/kernel/core/include/tos_slist.h @@ -19,7 +19,7 @@ #define _TOS_SLIST_H_ typedef struct k_slist_node_st { - struct k_slist_node_st *next; + struct k_slist_node_st *next; } k_slist_t; #define TOS_SLIST_NODE(dummy) \ diff --git a/kernel/core/tos_sys.c b/kernel/core/tos_sys.c index 447d17b8..6ebf878a 100644 --- a/kernel/core/tos_sys.c +++ b/kernel/core/tos_sys.c @@ -159,6 +159,7 @@ __API__ k_err_t tos_knl_start(void) k_next_task = readyqueue_highest_ready_task_get(); k_curr_task = k_next_task; k_knl_state = KNL_STATE_RUNNING; + cpu_sched_start(); return K_ERR_NONE;