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wangjianyu3 6b4d1cf9fa arch/esp32s3: The MISO, MOSI and C/S are optional 
The MISO or MOSI pin is optional.
The C/S pin is unnecessary when `ESP32S3_SPI_UDCS` is enabled.

Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
 		2026-04-27 09:58:34 +08:00
..
arm arm:modlib not support unwind table now 2026-04-27 09:57:19 +08:00
arm64 arm64/qemu: Add support for arm64 qemu's maximum feature cpu 2026-04-27 09:44:45 +08:00
avr arch: add noinstrument_function to up_irq_save/restore 2026-04-21 01:36:08 +08:00
ceva arch: add noinstrument_function to up_irq_save/restore 2026-04-21 01:36:08 +08:00
dummy
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hc arch: add noinstrument_function to up_irq_save/restore 2026-04-21 01:36:08 +08:00
mips nuttx/atomic: replace atomic_fetch_xxx with atomic_xxx just like zephyr 2026-04-21 01:35:40 +08:00
misoc nuttx/atomic: replace atomic_fetch_xxx with atomic_xxx just like zephyr 2026-04-21 01:35:40 +08:00
or1k arch: add noinstrument_function to up_irq_save/restore 2026-04-21 01:36:08 +08:00
renesas arch: add noinstrument_function to up_irq_save/restore 2026-04-21 01:36:08 +08:00
risc-v perf: add noinstrument_function to up_perf_gettime and related functions 2026-04-21 01:36:08 +08:00
sim sim: use libunwind to record backtrace 2026-04-27 09:50:20 +08:00
sparc nuttx/atomic: replace atomic_fetch_xxx with atomic_xxx just like zephyr 2026-04-21 01:35:40 +08:00
tricore perf: add noinstrument_function to up_perf_gettime and related functions 2026-04-21 01:36:08 +08:00
x86 arch: add noinstrument_function to up_irq_save/restore 2026-04-21 01:36:08 +08:00
x86_64 fs: migrate to SPDX identifier 2026-04-27 09:45:00 +08:00
xtensa arch/esp32s3: The MISO, MOSI and C/S are optional 2026-04-27 09:58:34 +08:00
z16 sched: unify the thread exit running task behavior. 2026-04-21 01:35:42 +08:00
z80 sched: unify the thread exit running task behavior. 2026-04-21 01:35:42 +08:00
CMakeLists.txt arch/cmake: KERNEL mode libarch 2026-04-21 01:23:49 +08:00
Kconfig arch/arm/src: realize atomic for chip "cxd56","rp2040" and "lc823450". 2026-04-21 01:35:01 +08:00