From 5730319ab0ff38a2096371cc57c79133e61b09c5 Mon Sep 17 00:00:00 2001 From: Beichen Date: Fri, 12 Aug 2022 17:24:59 +0800 Subject: [PATCH 01/59] =?UTF-8?q?Ubiquitous/RT-Thread=5FFusion=5FXiUOS/aii?= =?UTF-8?q?t=5Fboard/xidatong-riscv64/base-drivers/:=20Add=20ch438.c?= =?UTF-8?q?=E3=80=81ch438.h=20and=20update=20Sconscript.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../xidatong-riscv64/base-drivers/SConscript | 3 + .../xidatong-riscv64/base-drivers/ch438.c | 484 ++++++++++++++++++ .../xidatong-riscv64/base-drivers/ch438.h | 251 +++++++++ 3 files changed, 738 insertions(+) create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/ch438.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/ch438.h diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/SConscript b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/SConscript index ef646a25..35df2481 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/SConscript +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/SConscript @@ -31,6 +31,9 @@ if GetDepend('RT_USING_WDT'): if GetDepend('BSP_USING_LCD'): src += ['drv_lcd.c'] src += ['drv_mpylcd.c'] + +if GetDepend('BSP_USING_CH438'): + src += ['ch438.c'] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/ch438.c b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/ch438.c new file mode 100644 index 00000000..f561deb5 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/ch438.c @@ -0,0 +1,484 @@ +#include +#include +#include +#include +#include "board.h" +#include "ch438.h" +#include "sleep.h" +#include + +static rt_uint8_t offsetadd[] = {0x00,0x10,0x20,0x30,0x08,0x18,0x28,0x38,}; /* Offset address of serial port number */ +struct rt_serial_device *extuart_serial_parm[8]; + +void CH438_INIT(void) +{ + CH438_set_output(); + gpiohs_set_drive_mode(FPIOA_CH438_NWR, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_NRD, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_ALE, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_485_DIR, GPIO_DM_OUTPUT); + + gpiohs_set_pin(FPIOA_CH438_NWR, GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_NRD, GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_ALE, GPIO_PV_HIGH); +} + +void CH438_PORT_INIT( rt_uint8_t ext_uart_no,rt_uint32_t BaudRate ) +{ + rt_uint32_t div; + rt_uint8_t DLL,DLM,dlab; + rt_uint8_t REG_LCR_ADDR; + rt_uint8_t REG_DLL_ADDR; + rt_uint8_t REG_DLM_ADDR; + rt_uint8_t REG_IER_ADDR; + rt_uint8_t REG_MCR_ADDR; + rt_uint8_t REG_FCR_ADDR; + rt_uint8_t REG_RBR_ADDR; + rt_uint8_t REG_THR_ADDR; + rt_uint8_t REG_IIR_ADDR; + + REG_LCR_ADDR = offsetadd[ext_uart_no] | REG_LCR0_ADDR; + REG_DLL_ADDR = offsetadd[ext_uart_no] | REG_DLL0_ADDR; + REG_DLM_ADDR = offsetadd[ext_uart_no] | REG_DLM0_ADDR; + REG_IER_ADDR = offsetadd[ext_uart_no] | REG_IER0_ADDR; + REG_MCR_ADDR = offsetadd[ext_uart_no] | REG_MCR0_ADDR; + REG_FCR_ADDR = offsetadd[ext_uart_no] | REG_FCR0_ADDR; + REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR; + REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR; + REG_IIR_ADDR = offsetadd[ext_uart_no] | REG_IIR0_ADDR; + + WriteCH438Data( REG_IER_ADDR, BIT_IER_RESET ); /* Reset the serial port */ + rt_thread_delay(50); + + dlab = ReadCH438Data(REG_IER_ADDR); + dlab &= 0xDF; + WriteCH438Data(REG_IER_ADDR, dlab); + + dlab = ReadCH438Data(REG_LCR_ADDR); + dlab |= 0x80; + WriteCH438Data(REG_LCR_ADDR, dlab); + + div = ( Fpclk >> 4 ) / BaudRate; + DLM = div >> 8; + DLL = div & 0xff; + WriteCH438Data( REG_DLL_ADDR, DLL ); /* Set baud rate */ + WriteCH438Data( REG_DLM_ADDR, DLM ); + WriteCH438Data( REG_FCR_ADDR, BIT_FCR_RECVTG1 | BIT_FCR_RECVTG0 | BIT_FCR_FIFOEN ); /* Set FIFO mode */ + + WriteCH438Data( REG_LCR_ADDR, BIT_LCR_WORDSZ1 | BIT_LCR_WORDSZ0 ); + + WriteCH438Data( REG_IER_ADDR, /*BIT_IER_IEMODEM | BIT_IER_IETHRE | BIT_IER_IELINES | */BIT_IER_IERECV ); + + WriteCH438Data( REG_MCR_ADDR, BIT_MCR_OUT2 ); + + WriteCH438Data(REG_FCR_ADDR,ReadCH438Data(REG_FCR_ADDR)| BIT_FCR_RFIFORST | BIT_FCR_TFIFORST); + +} + +static void CH438_set_output(void) +{ + gpiohs_set_drive_mode(FPIOA_CH438_D0, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D1, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D2, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D3, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D4, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D5, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D6, GPIO_DM_OUTPUT); + gpiohs_set_drive_mode(FPIOA_CH438_D7, GPIO_DM_OUTPUT); + +} +static void CH438_set_input(void) +{ + gpiohs_set_drive_mode(FPIOA_CH438_D0, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D1, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D2, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D3, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D4, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D5, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D6, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_drive_mode(FPIOA_CH438_D7, GPIO_DM_INPUT_PULL_UP); + +} + + +void set_485_input(rt_uint8_t ch_no) +{ + if(ch_no == 1) + gpiohs_set_pin(FPIOA_485_DIR, GPIO_PV_LOW); +} + +void set_485_output(rt_uint8_t ch_no) +{ + if(ch_no == 1) + gpiohs_set_pin(FPIOA_485_DIR, GPIO_PV_HIGH); +} + +rt_uint8_t ReadCH438Data( rt_uint8_t addr ) +{ + rt_uint8_t dat = 0; + + gpiohs_set_pin(FPIOA_CH438_NWR,GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_NRD,GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_HIGH); + + CH438_set_output(); + usleep(1); + + if(addr &0x80) gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_LOW); + if(addr &0x40) gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_LOW); + if(addr &0x20) gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_LOW); + if(addr &0x10) gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_LOW); + if(addr &0x08) gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_LOW); + if(addr &0x04) gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_LOW); + if(addr &0x02) gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_LOW); + if(addr &0x01) gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_LOW); + + usleep(1); + + gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_LOW); + + usleep(1); + + CH438_set_input(); + usleep(1); + + gpiohs_set_pin(FPIOA_CH438_NRD,GPIO_PV_LOW); + + usleep(1); + + dat = 0; + if (gpiohs_get_pin(FPIOA_CH438_D7)) dat |= 0x80; + if (gpiohs_get_pin(FPIOA_CH438_D6)) dat |= 0x40; + if (gpiohs_get_pin(FPIOA_CH438_D5)) dat |= 0x20; + if (gpiohs_get_pin(FPIOA_CH438_D4)) dat |= 0x10; + if (gpiohs_get_pin(FPIOA_CH438_D3)) dat |= 0x08; + if (gpiohs_get_pin(FPIOA_CH438_D2)) dat |= 0x04; + if (gpiohs_get_pin(FPIOA_CH438_D1)) dat |= 0x02; + if (gpiohs_get_pin(FPIOA_CH438_D0)) dat |= 0x01; + + gpiohs_set_pin(FPIOA_CH438_NRD,GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_HIGH); + + usleep(1); + + return dat; +} + + +static void WriteCH438Data( rt_uint8_t addr, rt_uint8_t dat) +{ + gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_NRD,GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_NWR,GPIO_PV_HIGH); + + CH438_set_output(); + usleep(1); + + if(addr &0x80) gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_LOW); + if(addr &0x40) gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_LOW); + if(addr &0x20) gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_LOW); + if(addr &0x10) gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_LOW); + if(addr &0x08) gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_LOW); + if(addr &0x04) gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_LOW); + if(addr &0x02) gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_LOW); + if(addr &0x01) gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_LOW); + + usleep(1); + + gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_LOW); + usleep(1); + + if(dat &0x80) gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D7,GPIO_PV_LOW); + if(dat &0x40) gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D6,GPIO_PV_LOW); + if(dat &0x20) gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D5,GPIO_PV_LOW); + if(dat &0x10) gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D4,GPIO_PV_LOW); + if(dat &0x08) gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D3,GPIO_PV_LOW); + if(dat &0x04) gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D2,GPIO_PV_LOW); + if(dat &0x02) gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D1,GPIO_PV_LOW); + if(dat &0x01) gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_HIGH); else gpiohs_set_pin(FPIOA_CH438_D0,GPIO_PV_LOW); + + usleep(1); + + gpiohs_set_pin(FPIOA_CH438_NWR,GPIO_PV_LOW); + + usleep(1); + + gpiohs_set_pin(FPIOA_CH438_NWR,GPIO_PV_HIGH); + gpiohs_set_pin(FPIOA_CH438_ALE,GPIO_PV_HIGH); + + usleep(1); + + CH438_set_input(); + + return; +} + +static void WriteCH438Block( rt_uint8_t mAddr, rt_uint8_t mLen, rt_uint8_t *mBuf ) +{ + while ( mLen -- ) + WriteCH438Data( mAddr, *mBuf++ ); +} + +static int Ch438Irq(void *parameter) +{ + rt_uint8_t gInterruptStatus; + rt_uint8_t port = 0; + struct rt_serial_device *serial = (struct rt_serial_device *)parameter; + /* multi irq may happen*/ + gInterruptStatus = ReadCH438Data(REG_SSR_ADDR); + port = log(gInterruptStatus & 0xFF)/log(2); + + rt_hw_serial_isr(extuart_serial_parm[port], RT_SERIAL_EVENT_RX_IND); +} + +static rt_err_t rt_extuart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + rt_uint32_t baud_rate = cfg->baud_rate; + rt_uint16_t port = cfg->reserved; + + CH438_PORT_INIT(port, baud_rate); + + return RT_EOK; +} + +static rt_err_t extuart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + rt_uint16_t ext_uart_no = serial->config.reserved; + static rt_uint16_t register_flag = 0; + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + if(1 == register_flag) + { + gpiohs_irq_unregister(FPIOA_CH438_INT); + register_flag = 0; + } + break; + case RT_DEVICE_CTRL_SET_INT: + if(0 == register_flag) + { + gpiohs_set_drive_mode(FPIOA_CH438_INT, GPIO_DM_INPUT_PULL_UP); + gpiohs_set_pin_edge(FPIOA_CH438_INT,GPIO_PE_FALLING); + gpiohs_irq_register(FPIOA_CH438_INT, 1, Ch438Irq, (void*)serial); + register_flag = 1; + } + + break; + } + return (RT_EOK); +} + +static int drv_extuart_putc(struct rt_serial_device *serial, char c) +{ + uint16_t ext_uart_no = serial->config.reserved; + rt_uint8_t REG_LSR_ADDR,REG_THR_ADDR; + + REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR; + REG_THR_ADDR = offsetadd[ext_uart_no] | REG_THR0_ADDR; + + + if((ReadCH438Data( REG_LSR_ADDR ) & BIT_LSR_TEMT) != 0) + { + WriteCH438Block( REG_THR_ADDR, 1, &c ); + return 1; + } else { + return 0; + } + +} + +static int drv_extuart_getc(struct rt_serial_device *serial) +{ + rt_uint8_t dat = 0; + rt_uint8_t REG_LSR_ADDR,REG_RBR_ADDR; + uint16_t ext_uart_no = serial->config.reserved;///< get extern uart port + + REG_LSR_ADDR = offsetadd[ext_uart_no] | REG_LSR0_ADDR; + REG_RBR_ADDR = offsetadd[ext_uart_no] | REG_RBR0_ADDR; + + if((ReadCH438Data(REG_LSR_ADDR) & BIT_LSR_DATARDY) == 0x01) + { + dat = ReadCH438Data( REG_RBR_ADDR ); + if(dat >= 0) + return dat; + } else { + return -1; + } +} + +const struct rt_uart_ops extuart_ops = +{ + rt_extuart_configure, + extuart_control, + drv_extuart_putc, + drv_extuart_getc, + RT_NULL +}; + +int rt_hw_ch438_init(void) +{ + struct rt_serial_device *extserial; + struct device_uart *extuart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_err_t ret; + + { + static struct rt_serial_device extserial0; + + extserial = &extserial0; + extserial->ops = &extuart_ops; + extserial->config = config; + extserial->config.baud_rate = 115200; + extserial->config.reserved = 0; ///< extern uart port + + extuart_serial_parm[0] = &extserial0; + + ret = rt_hw_serial_register(extserial, + "extuart_dev0", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + extuart); + if(ret < 0){ + rt_kprintf("extuart_dev0 register failed.\n"); + } + } + { + static struct rt_serial_device extserial1; + + extserial = &extserial1; + extserial->ops = &extuart_ops; + extserial->config = config; + extserial->config.baud_rate = 9600; + extserial->config.reserved = 1; ///< extern uart port + + extuart_serial_parm[1] = &extserial1; + + ret = rt_hw_serial_register(extserial, + "extuart_dev1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + extuart); + if(ret < 0){ + rt_kprintf("extuart_dev1 register failed.\n"); + } + } + { + static struct rt_serial_device extserial2; + + extserial = &extserial2; + extserial->ops = &extuart_ops; + extserial->config = config; + extserial->config.baud_rate = 9600; + extserial->config.reserved = 2; ///< extern uart port + + extuart_serial_parm[2] = &extserial2; + + ret = rt_hw_serial_register(extserial, + "extuart_dev2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + extuart); + if(ret < 0){ + rt_kprintf("extuart_dev2 register failed.\n"); + } + + } + { + static struct rt_serial_device extserial3; + + extserial = &extserial3; + extserial->ops = &extuart_ops; + extserial->config = config; + extserial->config.baud_rate = 9600; + extserial->config.reserved = 3; ///< extern uart port + + ret = rt_hw_serial_register(extserial, + "extuart_dev3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + extuart); + if(ret < 0){ + rt_kprintf("extuart_dev3 register failed.\n"); + } + + extuart_serial_parm[3] = &extserial3; + } + { + static struct rt_serial_device extserial4; + + extserial = &extserial4; + extserial->ops = &extuart_ops; + extserial->config = config; + extserial->config.baud_rate = 9600; + extserial->config.reserved = 4; ///< extern uart port + + ret = rt_hw_serial_register(extserial, + "extuart_dev4", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + extuart); + if(ret < 0){ + rt_kprintf("extuart_dev4 register failed.\n"); + } + + extuart_serial_parm[4] = &extserial4; + } + { + static struct rt_serial_device extserial5; + + extserial = &extserial5; + extserial->ops = &extuart_ops; + extserial->config = config; + extserial->config.baud_rate = 115200; + extserial->config.reserved = 5; ///< extern uart port + + ret = rt_hw_serial_register(extserial, + "extuart_dev5", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + extuart); + if(ret < 0){ + rt_kprintf("extuart_dev5 register failed.\n"); + } + + extuart_serial_parm[5] = &extserial5; + } + { + static struct rt_serial_device extserial6; + + extserial = &extserial6; + extserial->ops = &extuart_ops; + extserial->config = config; + extserial->config.baud_rate = 57600; + extserial->config.reserved = 6; ///< extern uart port + + ret = rt_hw_serial_register(extserial, + "extuart_dev6", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + extuart); + if(ret < 0){ + rt_kprintf("extuart_dev6 register failed.\n"); + } + + extuart_serial_parm[6] = &extserial6; + } + { + static struct rt_serial_device extserial7; + + extserial = &extserial7; + extserial->ops = &extuart_ops; + extserial->config = config; + extserial->config.baud_rate = 9600; + extserial->config.reserved = 7; ///< extern uart port + + ret = rt_hw_serial_register(extserial, + "extuart_dev7", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + extuart); + if(ret < 0){ + rt_kprintf("extuart_dev7 register failed.\n"); + } + extuart_serial_parm[7] = &extserial7; + + } + + CH438_INIT(); + return 0; +} +INIT_DEVICE_EXPORT(rt_hw_ch438_init); diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/ch438.h b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/ch438.h new file mode 100644 index 00000000..bb42f30d --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/ch438.h @@ -0,0 +1,251 @@ +#ifndef __CH438_H_ +#define __CH438_H_ + +#include "board.h" + +#define BUFFSIZE 255 + +/******************************************************************************************/ + +/* CH438serial port0 register address */ + +#define REG_RBR0_ADDR 0x00 /* serial port0receive buffer register address */ +#define REG_THR0_ADDR 0x00 /* serial port0send hold register address */ +#define REG_IER0_ADDR 0x01 /* serial port0interrupt enable register address */ +#define REG_IIR0_ADDR 0x02 /* serial port0interrupt identifies register address */ +#define REG_FCR0_ADDR 0x02 /* serial port0FIFO controls register address */ +#define REG_LCR0_ADDR 0x03 /* serial port0circuit control register address */ +#define REG_MCR0_ADDR 0x04 /* serial port0MODEM controls register address */ +#define REG_LSR0_ADDR 0x05 /* serial port0line status register address */ +#define REG_MSR0_ADDR 0x06 /* serial port0address of MODEM status register */ +#define REG_SCR0_ADDR 0x07 /* serial port0the user can define the register address */ +#define REG_DLL0_ADDR 0x00 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM0_ADDR 0x01 /* Baud rate divisor latch high 8-bit byte address */ + +/* CH438serial port1 register address */ + +#define REG_RBR1_ADDR 0x10 /* serial port1receive buffer register address */ +#define REG_THR1_ADDR 0x10 /* serial port1send hold register address */ +#define REG_IER1_ADDR 0x11 /* serial port1interrupt enable register address */ +#define REG_IIR1_ADDR 0x12 /* serial port1interrupt identifies register address */ +#define REG_FCR1_ADDR 0x12 /* serial port1FIFO controls register address */ +#define REG_LCR1_ADDR 0x13 /* serial port1circuit control register address */ +#define REG_MCR1_ADDR 0x14 /* serial port1MODEM controls register address */ +#define REG_LSR1_ADDR 0x15 /* serial port1line status register address */ +#define REG_MSR1_ADDR 0x16 /* serial port1address of MODEM status register */ +#define REG_SCR1_ADDR 0x17 /* serial port1the user can define the register address */ +#define REG_DLL1_ADDR 0x10 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM1_ADDR 0x11 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port2 register address */ + +#define REG_RBR2_ADDR 0x20 /* serial port2receive buffer register address */ +#define REG_THR2_ADDR 0x20 /* serial port2send hold register address */ +#define REG_IER2_ADDR 0x21 /* serial port2interrupt enable register address */ +#define REG_IIR2_ADDR 0x22 /* serial port2interrupt identifies register address */ +#define REG_FCR2_ADDR 0x22 /* serial port2FIFO controls register address */ +#define REG_LCR2_ADDR 0x23 /* serial port2circuit control register address */ +#define REG_MCR2_ADDR 0x24 /* serial port2MODEM controls register address */ +#define REG_LSR2_ADDR 0x25 /* serial port2line status register address */ +#define REG_MSR2_ADDR 0x26 /* serial port2address of MODEM status register */ +#define REG_SCR2_ADDR 0x27 /* serial port2the user can define the register address */ +#define REG_DLL2_ADDR 0x20 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM2_ADDR 0x21 /* Baud rate divisor latch high 8-bit byte address */ + + + +/* CH438serial port3 register address */ + +#define REG_RBR3_ADDR 0x30 /* serial port3receive buffer register address */ +#define REG_THR3_ADDR 0x30 /* serial port3send hold register address */ +#define REG_IER3_ADDR 0x31 /* serial port3interrupt enable register address */ +#define REG_IIR3_ADDR 0x32 /* serial port3interrupt identifies register address */ +#define REG_FCR3_ADDR 0x32 /* serial port3FIFO controls register address */ +#define REG_LCR3_ADDR 0x33 /* serial port3circuit control register address */ +#define REG_MCR3_ADDR 0x34 /* serial port3MODEM controls register address */ +#define REG_LSR3_ADDR 0x35 /* serial port3line status register address */ +#define REG_MSR3_ADDR 0x36 /* serial port3address of MODEM status register */ +#define REG_SCR3_ADDR 0x37 /* serial port3the user can define the register address */ +#define REG_DLL3_ADDR 0x30 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM3_ADDR 0x31 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port4 register address */ + +#define REG_RBR4_ADDR 0x08 /* serial port4receive buffer register address */ +#define REG_THR4_ADDR 0x08 /* serial port4send hold register address */ +#define REG_IER4_ADDR 0x09 /* serial port4interrupt enable register address */ +#define REG_IIR4_ADDR 0x0A /* serial port4interrupt identifies register address */ +#define REG_FCR4_ADDR 0x0A /* serial port4FIFO controls register address */ +#define REG_LCR4_ADDR 0x0B /* serial port4circuit control register address */ +#define REG_MCR4_ADDR 0x0C /* serial port4MODEM controls register address */ +#define REG_LSR4_ADDR 0x0D /* serial port4line status register address */ +#define REG_MSR4_ADDR 0x0E /* serial port4address of MODEM status register */ +#define REG_SCR4_ADDR 0x0F /* serial port4the user can define the register address */ +#define REG_DLL4_ADDR 0x08 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM4_ADDR 0x09 /* Baud rate divisor latch high 8-bit byte address */ + + + +/* CH438serial port5 register address */ + +#define REG_RBR5_ADDR 0x18 /* serial port5receive buffer register address */ +#define REG_THR5_ADDR 0x18 /* serial port5send hold register address */ +#define REG_IER5_ADDR 0x19 /* serial port5interrupt enable register address */ +#define REG_IIR5_ADDR 0x1A /* serial port5interrupt identifies register address */ +#define REG_FCR5_ADDR 0x1A /* serial port5FIFO controls register address */ +#define REG_LCR5_ADDR 0x1B /* serial port5circuit control register address */ +#define REG_MCR5_ADDR 0x1C /* serial port5MODEM controls register address */ +#define REG_LSR5_ADDR 0x1D /* serial port5line status register address */ +#define REG_MSR5_ADDR 0x1E /* serial port5address of MODEM status register */ +#define REG_SCR5_ADDR 0x1F /* serial port5the user can define the register address */ +#define REG_DLL5_ADDR 0x18 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM5_ADDR 0x19 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port6 register address */ + +#define REG_RBR6_ADDR 0x28 /* serial port6receive buffer register address */ +#define REG_THR6_ADDR 0x28 /* serial port6send hold register address */ +#define REG_IER6_ADDR 0x29 /* serial port6interrupt enable register address */ +#define REG_IIR6_ADDR 0x2A /* serial port6interrupt identifies register address */ +#define REG_FCR6_ADDR 0x2A /* serial port6FIFO controls register address */ +#define REG_LCR6_ADDR 0x2B /* serial port6circuit control register address */ +#define REG_MCR6_ADDR 0x2C /* serial port6MODEM controls register address */ +#define REG_LSR6_ADDR 0x2D /* serial port6line status register address */ +#define REG_MSR6_ADDR 0x2E /* serial port6address of MODEM status register */ +#define REG_SCR6_ADDR 0x2F /* serial port6the user can define the register address */ +#define REG_DLL6_ADDR 0x28 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM6_ADDR 0x29 /* Baud rate divisor latch high 8-bit byte address */ + + +/* CH438serial port7 register address */ + +#define REG_RBR7_ADDR 0x38 /* serial port7receive buffer register address */ +#define REG_THR7_ADDR 0x38 /* serial port7send hold register address */ +#define REG_IER7_ADDR 0x39 /* serial port7interrupt enable register address */ +#define REG_IIR7_ADDR 0x3A /* serial port7interrupt identifies register address */ +#define REG_FCR7_ADDR 0x3A /* serial port7FIFO controls register address */ +#define REG_LCR7_ADDR 0x3B /* serial port7circuit control register address */ +#define REG_MCR7_ADDR 0x3C /* serial port7MODEM controls register address */ +#define REG_LSR7_ADDR 0x3D /* serial port7line status register address */ +#define REG_MSR7_ADDR 0x3E /* serial port7address of MODEM status register */ +#define REG_SCR7_ADDR 0x3F /* serial port7the user can define the register address */ +#define REG_DLL7_ADDR 0x38 /* Baud rate divisor latch low 8-bit byte address */ +#define REG_DLM7_ADDR 0x39 /* Baud rate divisor latch high 8-bit byte address */ + + +#define REG_SSR_ADDR 0x4F /* pecial status register address */ + + +/* IER register bit */ + +#define BIT_IER_RESET 0x80 /* The bit is 1 soft reset serial port */ +#define BIT_IER_LOWPOWER 0x40 /* The bit is 1 close serial port internal reference clock */ +#define BIT_IER_SLP 0x20 /* serial port0 is SLP, 1 close clock vibrator */ +#define BIT_IER1_CK2X 0x20 /* serial port1 is CK2X, 1 force the external clock signal after 2 times as internal reference clock */ +#define BIT_IER_IEMODEM 0x08 /* The bit is 1 allows MODEM input status to interrupt */ +#define BIT_IER_IELINES 0x04 /* The bit is 1 allow receiving line status to be interrupted */ +#define BIT_IER_IETHRE 0x02 /* The bit is 1 allows the send hold register to break in mid-air */ +#define BIT_IER_IERECV 0x01 /* The bit is 1 allows receiving data interrupts */ + +/* IIR register bit */ + +#define BIT_IIR_FIFOENS1 0x80 +#define BIT_IIR_FIFOENS0 0x40 /* The two is 1 said use FIFO */ + +/* Interrupt type: 0001 has no interrupt, 0110 receiving line status is interrupted, 0100 receiving data can be interrupted, +1100 received data timeout interrupt, 0010THR register air interrupt, 0000MODEM input change interrupt */ +#define BIT_IIR_IID3 0x08 +#define BIT_IIR_IID2 0x04 +#define BIT_IIR_IID1 0x02 +#define BIT_IIR_NOINT 0x01 + +/* FCR register bit */ + +/* Trigger point: 00 corresponds to 1 byte, 01 corresponds to 16 bytes, 10 corresponds to 64 bytes, 11 corresponds to 112 bytes */ +#define BIT_FCR_RECVTG1 0x80 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ +#define BIT_FCR_RECVTG0 0x40 /* Set the trigger point for FIFO interruption and automatic hardware flow control */ + +#define BIT_FCR_TFIFORST 0x04 /* The bit is 1 empty the data sent in FIFO */ +#define BIT_FCR_RFIFORST 0x02 /* The bit is 1 empty the data sent in FIFO */ +#define BIT_FCR_FIFOEN 0x01 /* The bit is 1 use FIFO, 0 disable FIFO */ + +/* LCR register bit */ + +#define BIT_LCR_DLAB 0x80 /* To access DLL, DLM, 0 to access RBR/THR/IER */ +#define BIT_LCR_BREAKEN 0x40 /* 1 forces a BREAK line interval*/ + +/* Set the check format: when PAREN is 1, 00 odd check, 01 even check, 10 MARK (set 1), 11 blank (SPACE, clear 0) */ +#define BIT_LCR_PARMODE1 0x20 /* Sets the parity bit format */ +#define BIT_LCR_PARMODE0 0x10 /* Sets the parity bit format */ + +#define BIT_LCR_PAREN 0x08 /* A value of 1 allows you to generate and receive parity bits when sending */ +#define BIT_LCR_STOPBIT 0x04 /* If is 1, then two stop bits, is 0, a stop bit */ + +/* Set word length: 00 for 5 data bits, 01 for 6 data bits, 10 for 7 data bits and 11 for 8 data bits */ +#define BIT_LCR_WORDSZ1 0x02 /* Set the word length length */ +#define BIT_LCR_WORDSZ0 0x01 + +/* MCR register bit */ + +#define BIT_MCR_AFE 0x20 /* For 1 allows automatic flow control of CTS and RTS hardware */ +#define BIT_MCR_LOOP 0x10 /* Is the test mode of 1 enabling internal loop */ +#define BIT_MCR_OUT2 0x08 /* 1 Allows an interrupt request for the serial port output */ +#define BIT_MCR_OUT1 0x04 /* The MODEM control bit defined for the user */ +#define BIT_MCR_RTS 0x02 /* The bit is 1 RTS pin output effective */ +#define BIT_MCR_DTR 0x01 /* The bit is 1 DTR pin output effective */ + +/* LSR register bit */ + +#define BIT_LSR_RFIFOERR 0x80 /* 1 said There is at least one error in receiving FIFO */ +#define BIT_LSR_TEMT 0x40 /* 1 said THR and TSR are empty */ +#define BIT_LSR_THRE 0x20 /* 1 said THR is empty*/ +#define BIT_LSR_BREAKINT 0x10 /* The bit is 1 said the BREAK line interval was detected*/ +#define BIT_LSR_FRAMEERR 0x08 /* The bit is 1 said error reading data frame */ +#define BIT_LSR_PARERR 0x04 /* The bit is 1 said parity error */ +#define BIT_LSR_OVERR 0x02 /* 1 said receive FIFO buffer overflow */ +#define BIT_LSR_DATARDY 0x01 /* The bit is 1 said receive data received in FIFO */ + +/* MSR register bit */ + +#define BIT_MSR_DCD 0x80 /* The bit is 1 said DCD pin effective */ +#define BIT_MSR_RI 0x40 /* The bit is 1 said RI pin effective */ +#define BIT_MSR_DSR 0x20 /* The bit is 1 said DSR pin effective */ +#define BIT_MSR_CTS 0x10 /* The bit is 1 said CTS pin effective */ +#define BIT_MSR_DDCD 0x08 /* The bit is 1 said DCD pin The input state has changed */ +#define BIT_MSR_TERI 0x04 /* The bit is 1 said RI pin The input state has changed */ +#define BIT_MSR_DDSR 0x02 /* The bit is 1 said DSR pin The input state has changed */ +#define BIT_MSR_DCTS 0x01 /* The bit is 1 said CTS pin The input state has changed */ + +/* Interrupt status code */ + +#define INT_NOINT 0x01 /* There is no interruption */ +#define INT_THR_EMPTY 0x02 /* THR empty interruption */ +#define INT_RCV_OVERTIME 0x0C /* Receive timeout interrupt */ +#define INT_RCV_SUCCESS 0x04 /* Interrupts are available to receive data */ +#define INT_RCV_LINES 0x06 /* Receiving line status interrupted */ +#define INT_MODEM_CHANGE 0x00 /* MODEM input changes interrupt */ + +#define CH438_IIR_FIFOS_ENABLED 0xC0 /* use FIFO */ + + +#define Fpclk 1843200 /* Define the internal clock frequency */ + + +void CH438_INIT(void); +void CH438_PORT_INIT( rt_uint8_t ext_uart_no,rt_uint32_t BaudRate ); +rt_uint8_t ReadCH438Data( rt_uint8_t addr ); +void CH438UARTSend( rt_uint8_t ext_uart_no,rt_uint8_t *Data, rt_uint8_t Num ); +rt_uint8_t CH438UARTRcv( rt_uint8_t ext_uart_no, rt_uint8_t* buf ); +void set_485_input(rt_uint8_t ch_no); +void set_485_output(rt_uint8_t ch_no); + + +static void CH438_set_output(void); +static void CH438_set_input(void); +static void WriteCH438Data( rt_uint8_t addr, rt_uint8_t dat); +static void WriteCH438Block( rt_uint8_t mAddr, rt_uint8_t mLen, rt_uint8_t *mBuf ); + +#endif -- 2.34.1 From 459d9c1c129e1c9fe38f443c09be9ad694df35f0 Mon Sep 17 00:00:00 2001 From: Beichen Date: Tue, 30 Aug 2022 21:06:52 +0800 Subject: [PATCH 02/59] =?UTF-8?q?1.Ubiquitous/RT-Thread=5FFusion=5FXiUOS/a?= =?UTF-8?q?pp=5Fmatch=5Frt-thread/wiznet/src/=EF=BC=9AModify=20wiz.c=20to?= =?UTF-8?q?=20increase=20wiz=20thread=20stack=20size=202.Ubiquitous/RT-Thr?= =?UTF-8?q?ead=5FFusion=5FXiUOS/aiit=5Fboard/xidatong-riscv64/:=20Modify?= =?UTF-8?q?=20.config=20and=20rtconfig.h=20to=20increase=20workqueue=20sta?= =?UTF-8?q?cksize?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/.config | 2 +- .../aiit_board/xidatong-riscv64/rtconfig.h | 2 +- .../RT-Thread_Fusion_XiUOS/app_match_rt-thread/wiznet/src/wiz.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/.config b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/.config index e12d4079..5b0b894d 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/.config +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/.config @@ -169,7 +169,7 @@ CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_PIPE_BUFSZ=512 CONFIG_RT_USING_SYSTEM_WORKQUEUE=y -CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=5120 CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_SERIAL_V1=y diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/rtconfig.h b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/rtconfig.h index eee446b1..9cbaecb9 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/rtconfig.h +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/rtconfig.h @@ -121,7 +121,7 @@ #define RT_USING_DEVICE_IPC #define RT_PIPE_BUFSZ 512 #define RT_USING_SYSTEM_WORKQUEUE -#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 5120 #define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL #define RT_USING_SERIAL_V1 diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/wiznet/src/wiz.c b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/wiznet/src/wiz.c index 6e8105ca..e0fb4e24 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/wiznet/src/wiz.c +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/app_match_rt-thread/wiznet/src/wiz.c @@ -876,7 +876,7 @@ static int wiz_interrupt_init(rt_base_t isr_pin) } /* create WIZnet SPI RX thread */ - tid = rt_thread_create("wiz", wiz_data_thread_entry, RT_NULL, 1024, RT_THREAD_PRIORITY_MAX / 6, 20); + tid = rt_thread_create("wiz", wiz_data_thread_entry, RT_NULL, 2048, RT_THREAD_PRIORITY_MAX / 6, 20); if (tid != RT_NULL) { rt_thread_startup(tid); -- 2.34.1 From aff5bbcc5e9b151fb7cb5540e2dad1874a630e8a Mon Sep 17 00:00:00 2001 From: Beichen Date: Wed, 31 Aug 2022 20:53:44 +0800 Subject: [PATCH 03/59] =?UTF-8?q?1=E3=80=81APP=5FFramework/Framework/trans?= =?UTF-8?q?form=5Flayer/rtthread/=EF=BC=9AModify=20transform.h=EF=BC=9B=20?= =?UTF-8?q?2=E3=80=81Ubiquitous/RT-Thread=5FFusion=5FXiUOS/aiit=5Fboard/xi?= =?UTF-8?q?datong-riscv64/=EF=BC=9Aupdate=20.config=20and=20rtconfig.h?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../transform_layer/rtthread/transform.h | 1 + .../aiit_board/xidatong-riscv64/.config | 21 ++++++++++++++++++- .../aiit_board/xidatong-riscv64/rtconfig.h | 10 +++++++++ 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/APP_Framework/Framework/transform_layer/rtthread/transform.h b/APP_Framework/Framework/transform_layer/rtthread/transform.h index 5eb7fece..c476ccaa 100644 --- a/APP_Framework/Framework/transform_layer/rtthread/transform.h +++ b/APP_Framework/Framework/transform_layer/rtthread/transform.h @@ -144,6 +144,7 @@ struct SerialDataCfg uint8_t serial_bit_order; uint8_t serial_invert_mode; uint16_t serial_buffer_size; + int32 serial_timeout; uint8_t is_ext_uart; uint8_t ext_uart_no; diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/.config b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/.config index 5b0b894d..dca96777 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/.config +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/.config @@ -356,7 +356,26 @@ CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y # CONFIG_ADD_NUTTX_FETURES is not set CONFIG_ADD_RTTHREAD_FETURES=y # CONFIG_SUPPORT_SENSOR_FRAMEWORK is not set -# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set +CONFIG_SUPPORT_CONNECTION_FRAMEWORK=y +CONFIG_CONNECTION_FRAMEWORK_DEBUG=y +# CONFIG_CONNECTION_INDUSTRIAL_ETHERNET is not set +# CONFIG_CONNECTION_INDUSTRIAL_FIELDBUS is not set +# CONFIG_CONNECTION_INDUSTRIAL_WLAN is not set +# CONFIG_CONNECTION_ADAPTER_LORA is not set +# CONFIG_CONNECTION_ADAPTER_4G is not set +# CONFIG_CONNECTION_ADAPTER_NB is not set +# CONFIG_CONNECTION_ADAPTER_WIFI is not set +# CONFIG_CONNECTION_ADAPTER_ETHERNET is not set +CONFIG_CONNECTION_ADAPTER_BLUETOOTH=y +CONFIG_ADAPTER_HC08=y +CONFIG_ADAPTER_BLUETOOTH_HC08="hc08-1" +CONFIG_ADAPTER_HC08_RECV_BUFFER_SIZE=128 +CONFIG_ADAPTER_HC08_WORK_ROLE="M" +CONFIG_ADAPTER_HC08_DRIVER_EXTUART=y +CONFIG_ADAPTER_HC08_DRIVER="/dev/extuart_dev1" +CONFIG_ADAPTER_HC08_DRIVER_EXT_PORT=1 +# CONFIG_CONNECTION_ADAPTER_ZIGBEE is not set +# CONFIG_CONNECTION_ADAPTER_5G is not set # CONFIG_SUPPORT_KNOWING_FRAMEWORK is not set # CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/rtconfig.h b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/rtconfig.h index 9cbaecb9..0ba26d90 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/rtconfig.h +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/rtconfig.h @@ -218,6 +218,16 @@ #define TRANSFORM_LAYER_ATTRIUBUTE #define ADD_RTTHREAD_FETURES +#define SUPPORT_CONNECTION_FRAMEWORK +#define CONNECTION_FRAMEWORK_DEBUG +#define CONNECTION_ADAPTER_BLUETOOTH +#define ADAPTER_HC08 +#define ADAPTER_BLUETOOTH_HC08 "hc08-1" +#define ADAPTER_HC08_RECV_BUFFER_SIZE 128 +#define ADAPTER_HC08_WORK_ROLE "M" +#define ADAPTER_HC08_DRIVER_EXTUART +#define ADAPTER_HC08_DRIVER "/dev/extuart_dev1" +#define ADAPTER_HC08_DRIVER_EXT_PORT 1 /* Security */ -- 2.34.1 From c2edb741e51b07a6093a01b039ddf62262d1cbfa Mon Sep 17 00:00:00 2001 From: Beichen Date: Thu, 1 Sep 2022 14:36:05 +0800 Subject: [PATCH 04/59] =?UTF-8?q?Ubiquitous/RT-Thread=5FFusion=5FXiUOS/aii?= =?UTF-8?q?t=5Fboard/xidatong-riscv64/=EF=BC=9Aupdate=20.config=E3=80=81rt?= =?UTF-8?q?config.h=E3=80=81drv=5Fio=5Fconfig.h=20and=20ch438.c=20to=20sol?= =?UTF-8?q?ve=20the=20problem=20of=20extended=20serial=20port=20registrati?= =?UTF-8?q?on=20failure?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../aiit_board/xidatong-riscv64/.config | 16 ++++++++-- .../xidatong-riscv64/base-drivers/ch438.c | 6 ++-- .../base-drivers/drv_io_config.h | 29 +++++++++++++++++++ .../aiit_board/xidatong-riscv64/rtconfig.h | 15 +++++++++- 4 files changed, 60 insertions(+), 6 deletions(-) diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/.config b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/.config index dca96777..8340b4cd 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/.config +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/.config @@ -11,7 +11,7 @@ CONFIG_BOARD_K210_EVB=y # # RT-Thread Kernel # -CONFIG_RT_NAME_MAX=8 +CONFIG_RT_NAME_MAX=12 # CONFIG_RT_USING_BIG_ENDIAN is not set # CONFIG_RT_USING_ARCH_DATA_TYPE is not set CONFIG_RT_USING_SMP=y @@ -307,7 +307,19 @@ CONFIG_BSP_SPI1_SS0_PIN=12 # Onboard Peripheral Drivers # # CONFIG_BSP_USING_LCD is not set -# CONFIG_BSP_USING_CH438 is not set +CONFIG_BSP_USING_CH438=y +CONFIG_BSP_CH438_ALE_PIN=24 +CONFIG_BSP_CH438_NWR_PIN=25 +CONFIG_BSP_CH438_NRD_PIN=26 +CONFIG_BSP_CH438_D0_PIN=27 +CONFIG_BSP_CH438_D1_PIN=28 +CONFIG_BSP_CH438_D2_PIN=29 +CONFIG_BSP_CH438_D3_PIN=30 +CONFIG_BSP_CH438_D4_PIN=31 +CONFIG_BSP_CH438_D5_PIN=32 +CONFIG_BSP_CH438_D6_PIN=33 +CONFIG_BSP_CH438_D7_PIN=34 +CONFIG_BSP_CH438_INT_PIN=35 # # Kendryte SDK Config diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/ch438.c b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/ch438.c index f561deb5..eff21b6c 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/ch438.c +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/ch438.c @@ -1,6 +1,6 @@ #include #include -#include +#include "drv_io_config.h" #include #include "board.h" #include "ch438.h" @@ -349,7 +349,7 @@ int rt_hw_ch438_init(void) extserial = &extserial1; extserial->ops = &extuart_ops; extserial->config = config; - extserial->config.baud_rate = 9600; + extserial->config.baud_rate = 115200; extserial->config.reserved = 1; ///< extern uart port extuart_serial_parm[1] = &extserial1; @@ -368,7 +368,7 @@ int rt_hw_ch438_init(void) extserial = &extserial2; extserial->ops = &extuart_ops; extserial->config = config; - extserial->config.baud_rate = 9600; + extserial->config.baud_rate = 115200; extserial->config.reserved = 2; ///< extern uart port extuart_serial_parm[2] = &extserial2; diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_io_config.h b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_io_config.h index 1b725e9e..2f52607f 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_io_config.h +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_io_config.h @@ -44,6 +44,35 @@ enum HS_GPIO_CONFIG GPIO_ALLOC_START /* index of gpio driver start */ }; +#define FPIOA_CH438_ALE 11 +#define FPIOA_CH438_NWR 12 +#define FPIOA_CH438_NRD 13 +#define FPIOA_CH438_D0 14 +#define FPIOA_CH438_D1 15 +#define FPIOA_CH438_D2 16 +#define FPIOA_CH438_D3 17 +#define FPIOA_CH438_D4 18 +#define FPIOA_CH438_D5 19 +#define FPIOA_CH438_D6 20 +#define FPIOA_CH438_D7 21 +#define FPIOA_CH438_INT 22 +#define FPIOA_485_DIR 23 + +//PIN.define +#define BSP_CH438_ALE_PIN 24 +#define BSP_CH438_NWR_PIN 25 +#define BSP_CH438_NRD_PIN 26 + +#define BSP_CH438_D0_PIN 27 +#define BSP_CH438_D1_PIN 28 +#define BSP_CH438_D2_PIN 29 +#define BSP_CH438_D3_PIN 30 +#define BSP_CH438_D4_PIN 31 +#define BSP_CH438_D5_PIN 32 +#define BSP_CH438_D6_PIN 33 +#define BSP_CH438_D7_PIN 34 +#define BSP_CH438_INT_PIN 35 + extern int io_config_init(void); #endif diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/rtconfig.h b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/rtconfig.h index 0ba26d90..c95179dc 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/rtconfig.h +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/rtconfig.h @@ -12,7 +12,7 @@ /* RT-Thread Kernel */ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 12 #define RT_USING_SMP #define RT_CPUS_NR 2 #define RT_ALIGN_SIZE 8 @@ -190,6 +190,19 @@ /* Onboard Peripheral Drivers */ +#define BSP_USING_CH438 +#define BSP_CH438_ALE_PIN 24 +#define BSP_CH438_NWR_PIN 25 +#define BSP_CH438_NRD_PIN 26 +#define BSP_CH438_D0_PIN 27 +#define BSP_CH438_D1_PIN 28 +#define BSP_CH438_D2_PIN 29 +#define BSP_CH438_D3_PIN 30 +#define BSP_CH438_D4_PIN 31 +#define BSP_CH438_D5_PIN 32 +#define BSP_CH438_D6_PIN 33 +#define BSP_CH438_D7_PIN 34 +#define BSP_CH438_INT_PIN 35 /* Kendryte SDK Config */ -- 2.34.1 From 5f017b8822b60d78401b200437994c00a3e5749b Mon Sep 17 00:00:00 2001 From: Beichen Date: Thu, 8 Sep 2022 17:11:57 +0800 Subject: [PATCH 05/59] Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/: update drv_io_config.c --- .../xidatong-riscv64/base-drivers/drv_io_config.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_io_config.c b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_io_config.c index b2a0a5a3..0207b802 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_io_config.c +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_io_config.c @@ -139,6 +139,20 @@ static struct io_config #ifdef BSP_PWM_CHN3_ENABLE IOCONFIG(BSP_PWM_CHN3_PIN, FUNC_TIMER2_TOGGLE4), #endif +#ifdef BSP_USING_CH438 + IOCONFIG(BSP_CH438_ALE_PIN, HS_GPIO(FPIOA_CH438_ALE)), + IOCONFIG(BSP_CH438_NWR_PIN, HS_GPIO(FPIOA_CH438_NWR)), + IOCONFIG(BSP_CH438_NRD_PIN, HS_GPIO(FPIOA_CH438_NRD)), + IOCONFIG(BSP_CH438_INT_PIN, HS_GPIO(FPIOA_CH438_INT)), + IOCONFIG(BSP_CH438_D0_PIN, HS_GPIO(FPIOA_CH438_D0)), + IOCONFIG(BSP_CH438_D1_PIN, HS_GPIO(FPIOA_CH438_D1)), + IOCONFIG(BSP_CH438_D2_PIN, HS_GPIO(FPIOA_CH438_D2)), + IOCONFIG(BSP_CH438_D3_PIN, HS_GPIO(FPIOA_CH438_D3)), + IOCONFIG(BSP_CH438_D4_PIN, HS_GPIO(FPIOA_CH438_D4)), + IOCONFIG(BSP_CH438_D5_PIN, HS_GPIO(FPIOA_CH438_D5)), + IOCONFIG(BSP_CH438_D6_PIN, HS_GPIO(FPIOA_CH438_D6)), + IOCONFIG(BSP_CH438_D7_PIN, HS_GPIO(FPIOA_CH438_D7)), +#endif }; static int print_io_config() -- 2.34.1 From 79718abd8e10e6d2acbb158af033220f06ff04a3 Mon Sep 17 00:00:00 2001 From: Beichen Date: Tue, 13 Sep 2022 09:38:03 +0800 Subject: [PATCH 06/59] =?UTF-8?q?1=E3=80=81Ubiquitous/RT-Thread=5FFusion?= =?UTF-8?q?=5FXiUOS/aiit=5Fboard/xidatong-riscv64/applications/:=20update?= =?UTF-8?q?=20main.c(add=20the=20FrameworkInit())=EF=BC=9B2=E3=80=81APP=5F?= =?UTF-8?q?Framework/Framework/connection/bluetooth/hc08/:=20update=20Kcon?= =?UTF-8?q?fig?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- APP_Framework/Framework/connection/bluetooth/hc08/Kconfig | 6 +++--- .../aiit_board/xidatong-riscv64/applications/main.c | 3 ++- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/APP_Framework/Framework/connection/bluetooth/hc08/Kconfig b/APP_Framework/Framework/connection/bluetooth/hc08/Kconfig index f7c0e5ec..af1a20dd 100644 --- a/APP_Framework/Framework/connection/bluetooth/hc08/Kconfig +++ b/APP_Framework/Framework/connection/bluetooth/hc08/Kconfig @@ -65,7 +65,7 @@ if ADD_RTTHREAD_FETURES config ADAPTER_HC08_DRIVER_EXTUART bool "Using extra uart to support bluetooth" - default n + default y config ADAPTER_HC08_DRIVER string "HC08 device uart driver path" @@ -75,10 +75,10 @@ if ADD_RTTHREAD_FETURES if ADAPTER_HC08_DRIVER_EXTUART config ADAPTER_HC08_DRIVER string "HC08 device extra uart driver path" - default "/dev/dev2" + default "/dev/extuart_dev1" config ADAPTER_HC08_DRIVER_EXT_PORT int "if HC08 device using extuart, choose port" - default "2" + default "1" endif endif diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/applications/main.c b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/applications/main.c index cf701b92..f5031eb2 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/applications/main.c +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/applications/main.c @@ -22,7 +22,7 @@ #include #include //#define LED_G 12 - +extern int FrameworkInit(void); int main(void) { //rt_pin_mode(LED_G, PIN_MODE_OUTPUT); @@ -32,6 +32,7 @@ int main(void) sprintf(info1,"xuos-intelligence k210 "); sprintf(info2,"build %s %s",__DATE__,__TIME__); printf("%s %s \n",info1,info2); + FrameworkInit(); #ifdef BSP_USING_LCD #include lcd_show_string(0,60,24,info1); -- 2.34.1 From 80f0045e0b3206dd03a3bd3078e72f5d00ad23bb Mon Sep 17 00:00:00 2001 From: Beichen Date: Fri, 30 Sep 2022 20:13:20 +0800 Subject: [PATCH 07/59] =?UTF-8?q?1=E3=80=81Ubiquitous/RT-Thread=5FFusion?= =?UTF-8?q?=5FXiUOS/aiit=5Fboard/xidatong-riscv64/base-drivers/:=20add=20d?= =?UTF-8?q?rv=5Fsoft=5Fi2c.c=E3=80=81drv=5Fsoft=5Fi2c.h=20and=20update=20S?= =?UTF-8?q?conscipt=E3=80=81Kconfig.=202=E3=80=81Ubiquitous/RT-Thread=5FFu?= =?UTF-8?q?sion=5FXiUOS/aiit=5Fboard/xidatong-riscv64/=EF=BC=9Aupdate=20.c?= =?UTF-8?q?onfig=20and=20rtconfig.h=20to=20support=20i2c=20function=20and?= =?UTF-8?q?=20register=20to=20bus=20framework.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../aiit_board/xidatong-riscv64/.config | 14 +- .../xidatong-riscv64/base-drivers/Kconfig | 10 +- .../xidatong-riscv64/base-drivers/SConscript | 8 +- .../base-drivers/drv_soft_i2c.c | 187 ++++++++++++++++++ .../base-drivers/drv_soft_i2c.h | 68 +++++++ .../aiit_board/xidatong-riscv64/rtconfig.h | 5 + 6 files changed, 282 insertions(+), 10 deletions(-) create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_soft_i2c.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_soft_i2c.h diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/.config b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/.config index 8340b4cd..ba0fafa7 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/.config +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/.config @@ -179,7 +179,10 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_HWTIMER is not set # CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set # CONFIG_RT_USING_PHY is not set CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_ADC is not set @@ -292,7 +295,9 @@ CONFIG_BSP_USING_UART_HS=y # CONFIG_BSP_USING_UART1 is not set # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART3 is not set -# CONFIG_BSP_USING_I2C1 is not set +CONFIG_BSP_USING_I2C1=y +CONFIG_BSP_I2C1_SDA_PIN=15 +CONFIG_BSP_I2C1_SCL_PIN=17 CONFIG_BSP_USING_SPI1=y CONFIG_BSP_SPI1_CLK_PIN=9 CONFIG_BSP_SPI1_D0_PIN=11 @@ -307,6 +312,11 @@ CONFIG_BSP_SPI1_SS0_PIN=12 # Onboard Peripheral Drivers # # CONFIG_BSP_USING_LCD is not set +# CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_LOW is not set +# CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_HIGH is not set +# CONFIG_BSP_BOARD_KD233 is not set +# CONFIG_BSP_BOARD_K210_OPENMV_TEST is not set +# CONFIG_BSP_BOARD_USER is not set CONFIG_BSP_USING_CH438=y CONFIG_BSP_CH438_ALE_PIN=24 CONFIG_BSP_CH438_NWR_PIN=25 diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/Kconfig b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/Kconfig index f2edf26d..16a78060 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/Kconfig +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/Kconfig @@ -60,15 +60,15 @@ menu "On-chip Peripheral Drivers" endif menuconfig BSP_USING_I2C1 - bool "Enable I2C1" + bool "Enable I2C1" select RT_USING_I2C default n - if BSP_USING_I2C11 - config BSP_I2C1_SDA_PIN + if BSP_USING_I2C1 + config BSP_I2C1_SDA_PIN int "I2C1 sda pin number" default 15 - config BSP_I2C1_CLK_PIN - int "I2C1 clk pin number" + config BSP_I2C1_SCL_PIN + int "I2C1 scl pin number" default 17 endif diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/SConscript b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/SConscript index 35df2481..58de1706 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/SConscript +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/SConscript @@ -19,8 +19,10 @@ if GetDepend('RT_USING_PIN'): if GetDepend('RT_USING_HWTIMER'): src += [drv_path + 'drv_hw_timer.c'] + if GetDepend('RT_USING_I2C'): - src += [drv_path + 'drv_i2c.c'] + src += ['drv_soft_i2c.c'] + if GetDepend('RT_USING_SPI'): src += ['drv_spi.c'] if GetDepend('RT_USING_PWM'): @@ -32,8 +34,8 @@ if GetDepend('BSP_USING_LCD'): src += ['drv_lcd.c'] src += ['drv_mpylcd.c'] -if GetDepend('BSP_USING_CH438'): - src += ['ch438.c'] +# if GetDepend('BSP_USING_CH438'): +# src += ['ch438.c'] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_soft_i2c.c b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_soft_i2c.c new file mode 100644 index 00000000..7e719603 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_soft_i2c.c @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2020 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2012-04-25 weety first version + */ + +/** +* @file drv_soft_i2c.c +* @brief support xidatong-riscv64-board i2c function and register to bus framework +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2022-09-30 +*/ + + +#include +#include +#include +#include "board.h" +#include +#include +#include +#include +#include "drv_soft_i2c.h" +#include +#include + + +static struct rt_i2c_config i2c_config[] = +{ +#ifdef BSP_USING_I2C0 + I2C0_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C1 + I2C1_BUS_CONFIG +#endif +}; + +static struct rt_i2c i2c_bus[sizeof(i2c_config) / sizeof(i2c_config[0])] = {0}; + +/** + * This function initializes the i2c pin. + * + * @param xidatong i2c dirver class. + */ +static void i2c_gpio_init(struct rt_i2c *i2c) +{ + struct rt_i2c_config *cfg = (struct rt_i2c_config *)i2c->ops.data; + + rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT); + rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT); + + rt_pin_write(cfg->scl, PIN_HIGH); + rt_pin_write(cfg->sda, PIN_HIGH); +} + +/** + * This function sets the sda pin. + * + * @param i2c config class. + * @param The sda pin state. + */ +static void set_sda(void *data, rt_int32_t state) +{ + struct rt_i2c_config *cfg = (struct rt_i2c_config *)data; + rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT); // PIN_MODE_OUTPUT_OD -> PIN_MODE_OUTPUT + if (state) + { + rt_pin_write(cfg->sda, PIN_HIGH); + } + else + { + rt_pin_write(cfg->sda, PIN_LOW); + } +} + +/** + * This function sets the scl pin. + * + * @param i2c config class. + * @param The scl pin state. + */ +static void set_scl(void *data, rt_int32_t state) +{ + struct rt_i2c_config *cfg = (struct rt_i2c_config *)data; + rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT); // PIN_MODE_OUTPUT_OD -> PIN_MODE_OUTPUT + if (state) + { + rt_pin_write(cfg->scl, PIN_HIGH); + } + else + { + rt_pin_write(cfg->scl, PIN_LOW); + } +} + +/** + * This function gets the sda pin state. + * + * @param The sda pin state. + */ +static rt_int32_t get_sda(void *data) +{ + struct rt_i2c_config *cfg = (struct rt_i2c_config *)data; + rt_pin_mode(cfg->sda, PIN_MODE_INPUT_PULLUP); + return rt_pin_read(cfg->sda); +} + +/** + * This function gets the scl pin state. + * + * @param The scl pin state. + */ +static rt_int32_t get_scl(void *data) +{ + struct rt_i2c_config *cfg = (struct rt_i2c_config *)data; + rt_pin_mode(cfg->scl, PIN_MODE_INPUT_PULLUP); + return rt_pin_read(cfg->scl); +} + +static const struct rt_i2c_bit_ops bit_ops = + { + .data = RT_NULL, + .set_sda = set_sda, + .set_scl = set_scl, + .get_sda = get_sda, + .get_scl = get_scl, + .udelay = usleep, + .delay_us = 1, + .timeout = 100}; + +/** + * if i2c is locked, this function will unlock it + * + * @param xidatong config class + * + * @return RT_EOK indicates successful unlock. + */ +static rt_err_t I2cBusReset(const struct rt_i2c_config *cfg) +{ + rt_int32_t i = 0; + if (PIN_LOW == rt_pin_read(cfg->sda)) + { + while (i++ < 9) + { + rt_pin_write(cfg->scl, PIN_HIGH); + usleep(100); + rt_pin_write(cfg->scl, PIN_LOW); + usleep(100); + } + } + if (PIN_LOW == rt_pin_read(cfg->sda)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +/* I2C initialization function */ +int rt_hw_i2c_init(void) +{ + rt_err_t result; + + for (int i = 0; i < sizeof(i2c_bus) / sizeof(struct rt_i2c); i++) + { + i2c_bus[i].ops = bit_ops; + i2c_bus[i].ops.data = (void *)&i2c_config[i]; + i2c_bus[i].i2c2_bus.priv = &i2c_bus[i].ops; + i2c_gpio_init(&i2c_bus[i]); + result = rt_i2c_bit_add_bus(&i2c_bus[i].i2c2_bus, i2c_config[i].name); + RT_ASSERT(result == RT_EOK); + I2cBusReset(&i2c_config[i]); + + LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", + i2c_config[i].name, + i2c_config[i].scl, + i2c_config[i].sda); + } + + return RT_EOK; +} +INIT_BOARD_EXPORT(rt_hw_i2c_init); diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_soft_i2c.h b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_soft_i2c.h new file mode 100644 index 00000000..97c9b5d6 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_soft_i2c.h @@ -0,0 +1,68 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file connect_i2c.h +* @brief define aiit-arm32-board i2c function and struct +* @version 1.0 +* @author AIIT XUOS Lab +* @date 2021-04-25 +*/ + +#ifndef __DRV_I2C_H__ +#define __DRV_I2C_H__ + + +#include +#include "board.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct rt_i2c_config +{ + char *name; + rt_uint8_t scl; + rt_uint8_t sda; +}; + +/* rt i2c dirver class */ +struct rt_i2c +{ + struct rt_i2c_bit_ops ops; + struct rt_i2c_bus_device i2c2_bus; +}; + +#ifdef BSP_USING_I2C0 +#define I2C0_BUS_CONFIG \ + { \ + .scl = BSP_I2C0_SCL_PIN, \ + .sda = BSP_I2C0_SDA_PIN, \ + .name = "i2c0", \ + } +#endif + +#ifdef BSP_USING_I2C1 +#define I2C1_BUS_CONFIG \ + { \ + .scl = BSP_I2C1_SCL_PIN, \ + .sda = BSP_I2C1_SDA_PIN, \ + .name = "i2c1", \ + } +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_I2C_H__ */ diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/rtconfig.h b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/rtconfig.h index c95179dc..8f349a89 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/rtconfig.h +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/rtconfig.h @@ -127,6 +127,8 @@ #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS #define RT_USING_PIN #define RT_USING_SPI @@ -181,6 +183,9 @@ #define __STACKSIZE__ 4096 #define BSP_USING_UART_HS +#define BSP_USING_I2C1 +#define BSP_I2C1_SDA_PIN 15 +#define BSP_I2C1_SCL_PIN 17 #define BSP_USING_SPI1 #define BSP_SPI1_CLK_PIN 9 #define BSP_SPI1_D0_PIN 11 -- 2.34.1 From 6b36810c09e043a5c90971013765bf37c337c9ca Mon Sep 17 00:00:00 2001 From: Beichen Date: Fri, 30 Sep 2022 20:29:31 +0800 Subject: [PATCH 08/59] =?UTF-8?q?Ubiquitous/RT-Thread=5FFusion=5FXiUOS/aii?= =?UTF-8?q?t=5Fboard/xidatong-riscv64/base-drivers/:=20update=20drv=5Fsoft?= =?UTF-8?q?=5Fi2c.c=E3=80=81drv=5Fsoft=5Fi2c.h.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../base-drivers/drv_soft_i2c.c | 18 ++++++++++-------- .../base-drivers/drv_soft_i2c.h | 12 ++++++------ 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_soft_i2c.c b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_soft_i2c.c index 7e719603..84f89029 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_soft_i2c.c +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_soft_i2c.c @@ -1,12 +1,14 @@ /* - * Copyright (c) 2020 RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2012-04-25 weety first version - */ +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ /** * @file drv_soft_i2c.c diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_soft_i2c.h b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_soft_i2c.h index 97c9b5d6..bba7867d 100644 --- a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_soft_i2c.h +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/base-drivers/drv_soft_i2c.h @@ -11,15 +11,15 @@ */ /** -* @file connect_i2c.h -* @brief define aiit-arm32-board i2c function and struct +* @file drv_soft_i2c.h +* @brief define xidatong-riscv64-board i2c function and struct * @version 1.0 * @author AIIT XUOS Lab -* @date 2021-04-25 +* @date 2022-09-30 */ -#ifndef __DRV_I2C_H__ -#define __DRV_I2C_H__ +#ifndef __DRV_SOFT_I2C_H__ +#define __DRV_SOFT_I2C_H__ #include @@ -65,4 +65,4 @@ struct rt_i2c } #endif -#endif /* __DRV_I2C_H__ */ +#endif /* __DRV_SOFT_I2C_H__ */ -- 2.34.1 From 837cea3b3534052221a2b2544284c069fbcad254 Mon Sep 17 00:00:00 2001 From: chunyexixiaoyu <834670833@qq.com> Date: Sat, 8 Oct 2022 10:21:38 +0800 Subject: [PATCH 09/59] Ubiquitous/RT-Thread_Fusion_XiUOS/: add k210 education bsp 1.w5500 supported 2.dvp port optimized 3.lcd adapted --- .gitmodules | 3 + .../aiit_board/k210_edu/.config | 471 ++++++ .../aiit_board/k210_edu/.gitignore | 228 +++ .../aiit_board/k210_edu/Kconfig | 37 + .../aiit_board/k210_edu/README.md | 29 + .../aiit_board/k210_edu/SConscript | 13 + .../aiit_board/k210_edu/SConstruct | 69 + .../k210_edu/applications/SConscript | 26 + .../aiit_board/k210_edu/applications/iperf.c | 522 +++++++ .../k210_edu/applications/lcd_test.c | 100 ++ .../aiit_board/k210_edu/applications/main.c | 75 + .../k210_edu/applications/ov2640_test.c | 151 ++ .../k210_edu/applications/sdcard_wr_test.c | 59 + .../k210_edu/applications/tcp_client.c | 144 ++ .../k210_edu/applications/tcp_client.h | 11 + .../k210_edu/applications/tcp_server.c | 174 +++ .../k210_edu/applications/tcp_server.h | 11 + .../aiit_board/k210_edu/base-drivers/Kconfig | 248 ++++ .../k210_edu/base-drivers/SConscript | 40 + .../aiit_board/k210_edu/base-drivers/board.c | 144 ++ .../aiit_board/k210_edu/base-drivers/board.h | 26 + .../k210_edu/base-drivers/dmalock.c | 90 ++ .../k210_edu/base-drivers/dmalock.h | 14 + .../k210_edu/base-drivers/drv_dvp.c | 177 +++ .../k210_edu/base-drivers/drv_dvp.h | 46 + .../k210_edu/base-drivers/drv_gpio.c | 267 ++++ .../k210_edu/base-drivers/drv_gpio.h | 16 + .../k210_edu/base-drivers/drv_interrupt.c | 27 + .../k210_edu/base-drivers/drv_io_config.c | 206 +++ .../k210_edu/base-drivers/drv_io_config.h | 58 + .../k210_edu/base-drivers/drv_lcd.c | 550 +++++++ .../k210_edu/base-drivers/drv_lcd.h | 91 ++ .../k210_edu/base-drivers/drv_mpylcd.c | 1301 +++++++++++++++++ .../k210_edu/base-drivers/drv_mpymachine.c | 27 + .../k210_edu/base-drivers/drv_soft_spi.c | 273 ++++ .../k210_edu/base-drivers/drv_soft_spi.h | 58 + .../k210_edu/base-drivers/drv_spi.c | 301 ++++ .../k210_edu/base-drivers/drv_spi.h | 16 + .../aiit_board/k210_edu/base-drivers/heap.c | 11 + .../k210_edu/base-drivers/sdcard_port.c | 44 + .../aiit_board/k210_edu/kendryte-sdk/Kconfig | 7 + .../k210_edu/kendryte-sdk/SConscript | 37 + .../k210_edu/kendryte-sdk/kendryte-sdk-source | 1 + .../aiit_board/k210_edu/link.lds | 170 +++ .../aiit_board/k210_edu/link_stacksize.lds | 1 + .../aiit_board/k210_edu/rtconfig.h | 290 ++++ .../aiit_board/k210_edu/rtconfig.py | 49 + .../aiit_board/k210_edu/test/tcp_client.png | Bin 0 -> 59466 bytes .../aiit_board/k210_edu/test/tcp_server.png | Bin 0 -> 100358 bytes .../aiit_board/k210_edu/test/w5500.png | Bin 0 -> 122523 bytes 50 files changed, 6709 insertions(+) create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/.config create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/.gitignore create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/Kconfig create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/README.md create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/SConscript create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/SConstruct create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/applications/SConscript create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/applications/iperf.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/applications/lcd_test.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/applications/main.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/applications/ov2640_test.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/applications/sdcard_wr_test.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/applications/tcp_client.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/applications/tcp_client.h create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/applications/tcp_server.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/applications/tcp_server.h create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/Kconfig create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/SConscript create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/board.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/board.h create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/dmalock.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/dmalock.h create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/drv_dvp.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/drv_dvp.h create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/drv_gpio.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/drv_gpio.h create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/drv_interrupt.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/drv_io_config.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/drv_io_config.h create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/drv_lcd.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/drv_lcd.h create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/drv_mpylcd.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/drv_mpymachine.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/drv_soft_spi.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/drv_soft_spi.h create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/drv_spi.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/drv_spi.h create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/heap.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/base-drivers/sdcard_port.c create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/kendryte-sdk/Kconfig create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/kendryte-sdk/SConscript create mode 160000 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/kendryte-sdk/kendryte-sdk-source create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/link.lds create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/link_stacksize.lds create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/rtconfig.h create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/rtconfig.py create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/test/tcp_client.png create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/test/tcp_server.png create mode 100644 Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/test/w5500.png diff --git a/.gitmodules b/.gitmodules index 389e23ce..513c5690 100644 --- a/.gitmodules +++ b/.gitmodules @@ -22,3 +22,6 @@ [submodule "Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/kendryte-sdk/kendryte-sdk-source"] path = Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/xidatong-riscv64/kendryte-sdk/kendryte-sdk-source url = https://code.gitlink.org.cn/chunyexixiaoyu/kendryte-sdk-source.git +[submodule "Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/kendryte-sdk/kendryte-sdk-source"] + path = Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/kendryte-sdk/kendryte-sdk-source + url = https://code.gitlink.org.cn/chunyexixiaoyu/kendryte-sdk-source.git diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/.config b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/.config new file mode 100644 index 00000000..3a390bd5 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/.config @@ -0,0 +1,471 @@ +# +# Automatically generated file; DO NOT EDIT. +# XIUOS Rt-thread Configuration +# +CONFIG_ROOT_DIR="../../../.." +CONFIG_BSP_DIR="." +CONFIG_RT_Thread_DIR="../.." +CONFIG_RTT_DIR="../../rt-thread" +CONFIG_BOARD_K210_EVB=y + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_BIG_ENDIAN is not set +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +CONFIG_RT_USING_SMP=y +CONFIG_RT_CPUS_NR=2 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=4096 +CONFIG_SYSTEM_THREAD_STACK_SIZE=4096 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_ASM_MEMCPY is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +CONFIG_RT_DEBUG_INIT_CONFIG=y +CONFIG_RT_DEBUG_INIT=1 +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +CONFIG_RT_USING_SIGNALS=y + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_MEMHEAP=y +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uarths" +# CONFIG_RT_PRINTF_LONGLONG is not set +CONFIG_RT_VER_NUM=0x40004 +CONFIG_ARCH_CPU_64BIT=y +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV_FPU=y +CONFIG_ARCH_RISCV_FPU_S=y +CONFIG_ARCH_RISCV64=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=10240 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +CONFIG_RT_USING_CPLUSPLUS=y +# CONFIG_RT_USING_CPLUSPLUS11 is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_RT_USING_MSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=20480 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=16 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=16 +CONFIG_DFS_FD_MAX=64 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=4096 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_QSPI is not set +CONFIG_RT_USING_SPI_MSD=y +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +CONFIG_RT_USING_PTHREADS=y +CONFIG_PTHREAD_NUM_MAX=8 +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +CONFIG_RT_LIBC_USING_TIME=y +# CONFIG_RT_USING_MODULE is not set +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# Network +# + +# +# Socket abstraction layer +# +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y +# CONFIG_SAL_USING_POSIX is not set +CONFIG_SAL_SOCKETS_NUM=16 + +# +# Network interface device +# +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RT_LINK is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# Board Drivers Config +# + +# +# On-chip Peripheral Drivers +# +CONFIG___STACKSIZE__=4096 +CONFIG_BSP_USING_UART_HS=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_SPI1 is not set +CONFIG_BSP_USING_SOFT_SPI=y +CONFIG_BSP_SOFT_SPI_CLK_PIN=26 +CONFIG_BSP_SOFT_SPI_MOSI_PIN=27 +CONFIG_BSP_SOFT_SPI_MISO_PIN=25 +CONFIG_RT_USING_SOFT_SPI_CS0=y +CONFIG_RT_USING_SOFT_SPI_CS0_PIN=28 + +# +# Onboard Peripheral Drivers +# +CONFIG_BSP_USING_LCD=y +CONFIG_BSP_LCD_CS_PIN=37 +CONFIG_BSP_LCD_WR_PIN=38 +CONFIG_BSP_LCD_DC_PIN=39 +CONFIG_BSP_LCD_RST_PIN=36 +CONFIG_BSP_LCD_BACKLIGHT_PIN=-1 +CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_LOW=y +# CONFIG_BSP_LCD_BACKLIGHT_ACTIVE_HIGH is not set +CONFIG_BSP_LCD_CLK_FREQ=15000000 +CONFIG_BSP_BOARD_KD233=y +# CONFIG_BSP_BOARD_K210_OPENMV_TEST is not set +# CONFIG_BSP_BOARD_USER is not set +CONFIG_BSP_LCD_X_MAX=320 +CONFIG_BSP_LCD_Y_MAX=320 +CONFIG_BSP_USING_DVP=y + +# +# The default pin assignment is based on the Maix Duino K210 development board +# +CONFIG_BSP_DVP_SCCB_SDA_PIN=47 +CONFIG_BSP_DVP_SCCB_SCLK_PIN=46 +CONFIG_BSP_DVP_CMOS_RST_PIN=40 +CONFIG_BSP_DVP_CMOS_VSYNC_PIN=45 +CONFIG_BSP_DVP_CMOS_PWDN_PIN=41 +CONFIG_BSP_DVP_CMOS_XCLK_PIN=42 +CONFIG_BSP_DVP_CMOS_PCLK_PIN=43 +CONFIG_BSP_DVP_CMOS_HREF_PIN=44 +CONFIG_BSP_USING_SDCARD=y + +# +# Kendryte SDK Config +# +CONFIG_PKG_KENDRYTE_SDK_VERNUM=0x0055 + +# +# MicroPython +# +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# More Drivers +# +# CONFIG_PKG_USING_RW007 is not set +CONFIG_DRV_USING_OV2640=y +CONFIG_OV2640_JPEG_MODE=y +# CONFIG_OV2640_RGB565_MODE is not set +CONFIG_OV2640_X_RESOLUTION_IMAGE_OUTSIZE=240 +CONFIG_OV2640_Y_RESOLUTION_IMAGE_OUTSIZE=240 +CONFIG_OV2640_X_IMAGE_WINDOWS_SIZE=400 + +# +# the value must be greater than OV2640_X_RESOLUTION_IMAGE_OUTSIZE +# +CONFIG_OV2640_Y_IMAGE_WINDOWS_SIZE=400 + +# +# the value must be greater than OV2640_Y_RESOLUTION_IMAGE_OUTSIZE +# +# CONFIG_DRV_USING_HS300X is not set +# CONFIG_DRV_USING_SX1278 is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# APP_Framework +# + +# +# Framework +# +CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y +# CONFIG_ADD_XIZI_FETURES is not set +# CONFIG_ADD_NUTTX_FETURES is not set +CONFIG_ADD_RTTHREAD_FETURES=y +# CONFIG_SUPPORT_SENSOR_FRAMEWORK is not set +# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set +CONFIG_SUPPORT_KNOWING_FRAMEWORK=y +# CONFIG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_USING_KNOWING_FILTER is not set +# CONFIG_USING_OTA_MODEL is not set +# CONFIG_USING_IMAGE_PROCESSING is not set +# CONFIG_USING_CMSIS_5 is not set +CONFIG_USING_KPU_PROCESSING=y +CONFIG_USING_YOLOV2=y +CONFIG_USING_YOLOV2_JSONPARSER=y +CONFIG_USING_K210_YOLOV2_DETECT=y +# CONFIG_USING_NNOM is not set +# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set + +# +# Security +# +# CONFIG_CRYPTO is not set + +# +# Applications +# + +# +# config stack size and priority of main task +# +CONFIG_MAIN_KTASK_STACK_SIZE=1024 + +# +# ota app +# +# CONFIG_APPLICATION_OTA is not set + +# +# test app +# +# CONFIG_USER_TEST is not set + +# +# connection app +# +# CONFIG_APPLICATION_CONNECTION is not set + +# +# control app +# + +# +# knowing app +# +CONFIG_APPLICATION_KNOWING=y +CONFIG_K210_DETECT_ENTRY=y +# CONFIG_IRIS_ML_DEMO is not set +# CONFIG_K210_FFT_TEST is not set +# CONFIG_USING_IMAGE_PROCESSING_APP is not set + +# +# sensor app +# +CONFIG_APPLICATION_SENSOR=y +# CONFIG_APPLICATION_SENSOR_HCHO is not set +# CONFIG_APPLICATION_SENSOR_TVOC is not set +# CONFIG_APPLICATION_SENSOR_IAQ is not set +# CONFIG_APPLICATION_SENSOR_CH4 is not set +# CONFIG_APPLICATION_SENSOR_CO2 is not set +# CONFIG_APPLICATION_SENSOR_PM1_0 is not set +# CONFIG_APPLICATION_SENSOR_PM2_5 is not set +# CONFIG_APPLICATION_SENSOR_PM10 is not set +# CONFIG_APPLICATION_SENSOR_VOICE is not set +# CONFIG_APPLICATION_SENSOR_TEMPERATURE is not set +# CONFIG_APPLICATION_SENSOR_HUMIDITY is not set +# CONFIG_APPLICATION_SENSOR_WINDDIRECTION is not set +# CONFIG_APPLICATION_SENSOR_WINDSPEED is not set +# CONFIG_APPLICATION_SENSOR_ALTITUDE is not set +# CONFIG_USING_EMBEDDED_DATABASE_APP is not set +# CONFIG_APP_USING_WEBNET is not set + +# +# lib +# +CONFIG_APP_SELECT_NEWLIB=y +# CONFIG_APP_SELECT_OTHER_LIB is not set +CONFIG_LIB_USING_CJSON=y +# CONFIG_LIB_USING_QUEUE is not set +# CONFIG_LIB_LV is not set + +# +# LVGL configuration +# +# CONFIG_LV_CONF_MINIMAL is not set +# CONFIG_USING_EMBEDDED_DATABASE is not set diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/.gitignore b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/.gitignore new file mode 100644 index 00000000..14e2fd4e --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/.gitignore @@ -0,0 +1,228 @@ +# this +*.old +*.dblite +cconfig.h +*.bin +*.map +# rtconfig.h +# .config + +# General +.DS_Store +.AppleDouble +.LSOverride + +# Icon must end with two \r +Icon + + +# Thumbnails +._* + +# Files that might appear in the root of a volume +.DocumentRevisions-V100 +.fseventsd +.Spotlight-V100 +.TemporaryItems +.Trashes +.VolumeIcon.icns +.com.apple.timemachine.donotpresent + +# Directories potentially created on remote AFP share +.AppleDB +.AppleDesktop +Network Trash Folder +Temporary Items +.apdisk + +# Byte-compiled / optimized / DLL files +__pycache__/ +*.py[cod] +*$py.class + +# C extensions +*.so + +# Distribution / packaging +.Python +build/ +develop-eggs/ +dist/ +downloads/ +eggs/ +.eggs/ +lib/ +lib64/ +parts/ +sdist/ +var/ +wheels/ +share/python-wheels/ +*.egg-info/ +.installed.cfg +*.egg +MANIFEST + +# PyInstaller +# Usually these files are written by a python script from a template +# before PyInstaller builds the exe, so as to inject date/other infos into it. +*.manifest +*.spec + +# Installer logs +pip-log.txt +pip-delete-this-directory.txt + +# Unit test / coverage reports +htmlcov/ +.tox/ +.nox/ +.coverage +.coverage.* +.cache +nosetests.xml +coverage.xml +*.cover +*.py,cover +.hypothesis/ +.pytest_cache/ +cover/ + +# Translations +*.mo +*.pot + +# Django stuff: +*.log +local_settings.py +db.sqlite3 +db.sqlite3-journal + +# Flask stuff: +instance/ +.webassets-cache + +# Scrapy stuff: +.scrapy + +# Sphinx documentation +docs/_build/ + +# PyBuilder +.pybuilder/ +target/ + +# Jupyter Notebook +.ipynb_checkpoints + +# IPython +profile_default/ +ipython_config.py + +# pyenv +# For a library or package, you might want to ignore these files since the code is +# intended to run in multiple environments; otherwise, check them in: +# .python-version + +# pipenv +# According to pypa/pipenv#598, it is recommended to include Pipfile.lock in version control. +# However, in case of collaboration, if having platform-specific dependencies or dependencies +# having no cross-platform support, pipenv may install dependencies that don't work, or not +# install all needed dependencies. +#Pipfile.lock + +# PEP 582; used by e.g. github.com/David-OConnor/pyflow +__pypackages__/ + +# Celery stuff +celerybeat-schedule +celerybeat.pid + +# SageMath parsed files +*.sage.py + +# Environments +.env +.venv +env/ +venv/ +ENV/ +env.bak/ +venv.bak/ + +# Spyder project settings +.spyderproject +.spyproject + +# Rope project settings +.ropeproject + +# mkdocs documentation +/site + +# mypy +.mypy_cache/ +.dmypy.json +dmypy.json + +# Pyre type checker +.pyre/ + +# pytype static type analyzer +.pytype/ + +# Cython debug symbols +cython_debug/ + +# Prerequisites +*.d + +# Object files +*.o +*.ko +*.obj +*.elf + +# Linker output +*.ilk +*.map +*.exp + +# Precompiled Headers +*.gch +*.pch + +# Libraries +*.lib +*.a +*.la +*.lo + +# Shared objects (inc. Windows DLLs) +*.dll +*.so +*.so.* +*.dylib + +# Executables +*.exe +*.out +*.app +*.i*86 +*.x86_64 +*.hex + +# Debug files +*.dSYM/ +*.su +*.idb +*.pdb + +# Kernel Module Compile Results +*.mod* +*.cmd +.tmp_versions/ +modules.order +Module.symvers +Mkfile.old +dkms.con \ No newline at end of file diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/Kconfig b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/Kconfig new file mode 100644 index 00000000..e48e9683 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/Kconfig @@ -0,0 +1,37 @@ +mainmenu "XIUOS Rt-thread Configuration" + +config ROOT_DIR + string + default "../../../.." + +config BSP_DIR + string + default "." + +config RT_Thread_DIR + string + default "../.." + +config RTT_DIR + string + default "../../rt-thread" + +config BOARD_K210_EVB + bool + select ARCH_RISCV64 + select ARCH_RISCV_FPU_S + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +config APP_DIR + string + default "../../../../APP_Framework" + +source "$RTT_DIR/Kconfig" +source "base-drivers/Kconfig" +source "kendryte-sdk/Kconfig" +source "$RT_Thread_DIR/micropython/Kconfig" +source "$RT_Thread_DIR/app_match_rt-thread/Kconfig" +source "$ROOT_DIR/APP_Framework/Kconfig" + diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/README.md b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/README.md new file mode 100644 index 00000000..a755c607 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/README.md @@ -0,0 +1,29 @@ +# 教育开发板k210_edu说明 + +## 板载资源 + +该教育开发板板载摄像头dvp接口，可外接（ov2640、ov5640等），同时还外接屏幕lcd（320*320），以及W5500网卡。 + + + +## 编译说明 +先下载源码，进入xiuos根目录： + + git submodule init + git submodule update Ubiquitous/RT-Thread_Fusion_XiUOS/rt-thread + git submodule update Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/kendryte-sdk/kendryte-sdk-source +下载好相应的源码以及勘智官方K210 sdk到指定目录 + +下载risc-v的工具链，[下载地址](https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases) + +在`rtconfig.py`中将risc-v工具链的本地路径加入文档。 + +然后执行scons编译： + scons + +也可以利用env工具编译，指定工具链路径 + + set RTT_EXEC_PATH=D:\xpack-riscv-none-embed-gcc-8.2.0-3.1-win32-x64\xPack\RISC-V Embedded GCC\8.2.0-3.1\bin + + scons + diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/SConscript b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/SConscript new file mode 100644 index 00000000..3d15055d --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/SConscript @@ -0,0 +1,13 @@ +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/SConstruct b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/SConstruct new file mode 100644 index 00000000..c3fa5fe1 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/SConstruct @@ -0,0 +1,69 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../rt-thread') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +# use ASPPCOM to replace ASCOM, ASPPCOM will use CFLAGS/CPPFLAGS with AS +env['ASCOM'] = env['ASPPCOM'] + +AddOption('--compiledb', + dest = 'compiledb', + action = 'store_true', + default = False, + help = 'generate compile_commands.json') + +if GetOption('compiledb'): + if int(SCons.__version__.split('.')[0]) >= 4: + env['COMPILATIONDB_USE_ABSPATH'] = True + env.Tool('compilation_db') + env.CompilationDatabase('compile_commands.json') + else: + print('Warning: --compiledb only support on SCons 4.0+') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False) + +stack_size = 4096 + +stack_lds = open('link_stacksize.lds', 'w') +if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__') +stack_lds.write('__STACKSIZE__ = %d;' % stack_size) +stack_lds.close() + +# include more drivers +objs.extend(SConscript(os.getcwd() + '/../../app_match_rt-thread/SConscript')) + +# include APP_Framework/Framework +objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Framework/SConscript')) + +# include APP_Framework/Applications +objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Applications/SConscript')) + +# include APP_Framework/lib +objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/lib/SConscript')) + +# include Ubiquitous/RT-Thread/micropython +objs.extend(SConscript(os.getcwd() + '/../../micropython/SConscript')) + +# make a building +DoBuilding(TARGET, objs) diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/applications/SConscript b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/applications/SConscript new file mode 100644 index 00000000..ecbf1586 --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/applications/SConscript @@ -0,0 +1,26 @@ +from building import * + +cwd = GetCurrentDir() +src = [ + 'main.c' +] +CPPPATH = [cwd] + +## 设置 lcd_test.c 的依赖宏 +if GetDepend('DRV_USING_OV2640'): + src += ['ov2640_test.c'] +if GetDepend('BSP_USING_LCD'): + src += ['lcd_test.c'] +## 设置 tcp_client.c 和 tcp_server.c 的依赖宏 +if GetDepend('PKG_USING_WIZNET'): + src += ['tcp_client.c'] + src += ['tcp_server.c'] + src += ['iperf.c'] +if GetDepend('BSP_USING_SDCARD'): + src += ['sdcard_wr_test.c'] +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') + + + diff --git a/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/applications/iperf.c b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/applications/iperf.c new file mode 100644 index 00000000..e19c81ea --- /dev/null +++ b/Ubiquitous/RT-Thread_Fusion_XiUOS/aiit_board/k210_edu/applications/iperf.c @@ -0,0 +1,522 @@ +/** +* iperf-liked network performance tool +* +*/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define DBG_SECTION_NAME "iperf" +#define DBG_LEVEL DBG_INFO +#include + +#define IPERF_PORT 5001 +#define IPERF_BUFSZ (4 * 1024) + +#define IPERF_MODE_STOP 0 +#define IPERF_MODE_SERVER 1 +#define IPERF_MODE_CLIENT 2 + +typedef struct +{ + int mode; + char *host; + int port; +} IPERF_PARAM; +static IPERF_PARAM param = {IPERF_MODE_STOP, NULL, IPERF_PORT}; + +static void iperf_udp_client(void *thread_param) +{ + int sock; + rt_uint32_t *buffer; + struct sockaddr_in server; + rt_uint32_t packet_count = 0; + rt_uint32_t tick; + int send_size; + + send_size = IPERF_BUFSZ > 1470 ? 1470 : IPERF_BUFSZ; + buffer = rt_malloc(IPERF_BUFSZ); + if (buffer == NULL) + { + return; + } + memset(buffer, 0x00, IPERF_BUFSZ); + sock = socket(PF_INET, SOCK_DGRAM, 0); + if(sock < 0) + { + LOG_E("can't create socket! exit!"); + return; + } + server.sin_family = PF_INET; + server.sin_port = htons(param.port); + server.sin_addr.s_addr = inet_addr(param.host); + LOG_I("iperf udp mode run..."); + while (param.mode != IPERF_MODE_STOP) + { + packet_count++; + tick = rt_tick_get(); + buffer[0] = htonl(packet_count); + buffer[1] = htonl(tick / RT_TICK_PER_SECOND); + buffer[2] = htonl((tick % RT_TICK_PER_SECOND) * 1000); + sendto(sock, buffer, send_size, 0, (struct sockaddr *)&server, sizeof(struct sockaddr_in)); + } + closesocket(sock); + rt_free(buffer); +} + +static void iperf_udp_server(void *thread_param) +{ + int sock; + rt_uint32_t *buffer; + struct sockaddr_in server; + struct sockaddr_in sender; + int sender_len, r_size; + rt_uint64_t sentlen; + rt_uint32_t pcount = 0, last_pcount = 0; + rt_uint32_t lost, total; + rt_tick_t tick1, tick2; + struct timeval timeout; + + buffer = rt_malloc(IPERF_BUFSZ); + if (buffer == NULL) + { + return; + } + sock = socket(PF_INET, SOCK_DGRAM, 0); + if(sock < 0) + { + LOG_E("can't create socket! exit!"); + return; + } + server.sin_family = PF_INET; + server.sin_port = htons(param.port); + server.sin_addr.s_addr = inet_addr("0.0.0.0"); + + timeout.tv_sec = 2; + timeout.tv_usec = 0; + if (setsockopt(sock, SOL_SOCKET, SO_RCVTIMEO, &timeout, sizeof(timeout)) == -1) + { + LOG_E("setsockopt failed!"); + closesocket(sock); + rt_free(buffer); + return; + } + if (bind(sock, (struct sockaddr *)&server, sizeof(struct sockaddr_in)) < 0) + { + LOG_E("iperf server bind failed! exit!"); + closesocket(sock); + rt_free(buffer); + return; + } + while (param.mode != IPERF_MODE_STOP) + { + tick1 = rt_tick_get(); + tick2 = tick1; + lost = 0; + total = 0; + sentlen = 0; + while ((tick2 - tick1) < (RT_TICK_PER_SECOND * 5)) + { + r_size = recvfrom(sock, buffer, IPERF_BUFSZ, 0, (struct sockaddr *)&sender, (socklen_t*)&sender_len); + if (r_size > 12) + { + pcount = ntohl(buffer[0]); + if (last_pcount < pcount) + { + lost += pcount - last_pcount - 1; + total += pcount - last_pcount; + } + else + { + last_pcount = pcount; + } + last_pcount = pcount; + sentlen += r_size; + } + tick2 = rt_tick_get(); + } + if (sentlen > 0) + { + long data; + int integer, decimal; + rt_thread_t tid; + + tid = rt_thread_self(); + data = sentlen * RT_TICK_PER_SECOND / 125 / (tick2 - tick1); + integer = data/1000; + decimal = data%1000; + LOG_I("%s: %d.%03d0 Mbps! lost:%d total:%d\n", tid->name, integer, decimal, lost, total); + } + } + rt_free(buffer); + closesocket(sock); +} + +static void iperf_client(void *thread_param) +{ + int i; + int sock; + int ret; + int tips = 1; + uint8_t *send_buf; + rt_uint64_t sentlen; + rt_tick_t tick1, tick2; + struct sockaddr_in addr; + + send_buf = (uint8_t *) rt_malloc(IPERF_BUFSZ); + if (!send_buf) return ; + + for (i = 0; i < IPERF_BUFSZ; i ++) + send_buf[i] = i & 0xff; + + while (param.mode != IPERF_MODE_STOP) + { + sock = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP); + if (sock < 0) + { + LOG_E("create socket failed!"); + rt_thread_delay(RT_TICK_PER_SECOND); + continue; + } + + addr.sin_family = PF_INET; + addr.sin_port = htons(param.port); + addr.sin_addr.s_addr = inet_addr((char *)param.host); + + ret = connect(sock, (const struct sockaddr *)&addr, sizeof(addr)); + if (ret == -1) + { + if (tips) + { + LOG_E("Connect to iperf server faile, Waiting for the server to open!"); + tips = 0; + } + closesocket(sock); + rt_thread_delay(RT_TICK_PER_SECOND); + continue; + } + + LOG_I("Connect to iperf server successful!"); + + { + int flag = 1; + + setsockopt(sock, + IPPROTO_TCP, /* set option at TCP level */ + TCP_NODELAY, /* name of option */ + (void *) &flag, /* the cast is historical cruft */ + sizeof(int)); /* length of option value */ + } + + sentlen = 0; + + tick1 = rt_tick_get(); + while (param.mode != IPERF_MODE_STOP) + { + tick2 = rt_tick_get(); + if (tick2 - tick1 >= RT_TICK_PER_SECOND * 5) + { + long data; + int integer, decimal; + rt_thread_t tid; + + tid = rt_thread_self(); + data = sentlen * RT_TICK_PER_SECOND / 125 / (tick2 - tick1); + integer = data/1000; + decimal = data%1000; + LOG_I("%s: %d.%03d0 Mbps!", tid->name, integer, decimal); + tick1 = tick2; + sentlen = 0; + } + + ret = send(sock, send_buf, IPERF_BUFSZ, 0); + if (ret > 0) + { + sentlen += ret; + } + + if (ret < 0) break; + } + + closesocket(sock); + + rt_thread_delay(RT_TICK_PER_SECOND * 2); + LOG_W("Disconnected, iperf server shut down!"); + tips = 1; + } + rt_free(send_buf); +} + +void iperf_server(void *thread_param) +{ + uint8_t *recv_data; + socklen_t sin_size; + rt_tick_t tick1, tick2; + int sock = -1, connected, bytes_received; + rt_uint64_t recvlen; + struct sockaddr_in server_addr, client_addr; + fd_set readset; + struct timeval timeout; + + recv_data = (uint8_t *)rt_malloc(IPERF_BUFSZ); + if (recv_data == RT_NULL) + { + LOG_E("No memory!"); + goto __exit; + } + + sock = socket(AF_INET, SOCK_STREAM, 0); + if (sock < 0) + { + LOG_E("Socket error!"); + goto __exit; + } + + server_addr.sin_family = AF_INET; + server_addr.sin_port = htons(param.port); + server_addr.sin_addr.s_addr = INADDR_ANY; + memset(&(server_addr.sin_zero), 0x0, sizeof(server_addr.sin_zero)); + + if (bind(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)) == -1) + { + LOG_E("Unable to bind!"); + goto __exit; + } + + if (listen(sock, 5) == -1) + { + LOG_E("Listen error!"); + goto __exit; + } + + timeout.tv_sec = 3; + timeout.tv_usec = 0; + + while (param.mode != IPERF_MODE_STOP) + { + FD_ZERO(&readset); + FD_SET(sock, &readset); + + if (select(sock + 1, &readset, RT_NULL, RT_NULL, &timeout) == 0) + continue; + + sin_size = sizeof(struct sockaddr_in); + + connected = accept(sock, (struct sockaddr *)&client_addr, &sin_size); + + LOG_I("new client connected from (%s, %d)", + inet_ntoa(client_addr.sin_addr), ntohs(client_addr.sin_port)); + + { + int flag = 1; + + setsockopt(connected, + IPPROTO_TCP, /* set option at TCP level */ + TCP_NODELAY, /* name of option */ + (void *) &flag, /* the cast is historical cruft */ + sizeof(int)); /* length of option value */ + } + + recvlen = 0; + tick1 = rt_tick_get(); + while (param.mode != IPERF_MODE_STOP) + { + bytes_received = recv(connected, recv_data, IPERF_BUFSZ, 0); + if (bytes_received <= 0) break; + + recvlen += bytes_received; + + tick2 = rt_tick_get(); + if (tick2 - tick1 >= RT_TICK_PER_SECOND * 5) + { + long data; + int integer, decimal; + rt_thread_t tid; + + tid = rt_thread_self(); + data = recvlen * RT_TICK_PER_SECOND / 125 / (tick2 - tick1); + integer = data/1000; + decimal = data%1000; + LOG_I("%s: %d.%03d0 Mbps!", tid->name, integer, decimal); + tick1 = tick2; + recvlen = 0; + } + } + LOG_W("client disconnected (%s, %d)", + inet_ntoa(client_addr.sin_addr), ntohs(client_addr.sin_port)); + if (connected >= 0) closesocket(connected); + connected = -1; + } + +__exit: + if (sock >= 0) closesocket(sock); + if (recv_data) rt_free(recv_data); +} + +void iperf_usage(void) +{ + rt_kprintf("Usage: iperf [-s|-c host] [options] [multi-threaded]\n"); + rt_kprintf(" iperf [-h|--stop]\n"); + rt_kprintf("\n"); + rt_kprintf("Client/Server:\n"); + rt_kprintf(" -p # server port to listen on/connect to\n"); + rt_kprintf("\n"); + rt_kprintf("Server specific:\n"); + rt_kprintf(" -s run in server mode\n"); + rt_kprintf("\n"); + rt_kprintf("Client specific:\n"); + rt_kprintf(" -c run in client mode, connecting to \n"); + rt_kprintf("\n"); + rt_kprintf("Miscellaneous:\n"); + rt_kprintf(" -h print this message and quit\n"); + rt_kprintf(" --stop stop iperf program\n"); + rt_kprintf(" -u testing UDP protocol\n"); + rt_kprintf(" -m