mirror of https://github.com/XS-MLVP/mlvp.git
33 lines
886 B
Verilog
33 lines
886 B
Verilog
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module mem (
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input logic clk,
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input logic rst_n,
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input logic [1:0] bank,
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input logic [3:0] addr,
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input logic [7:0] data_in,
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input logic write_enable,
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output logic [7:0] data_out,
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output logic [31:0] out_counter
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);
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reg [7:0] memory [3:0][15:0];
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reg [7:0] data_buffer;
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reg [31:0] wcounter;
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reg [31:0] ocounter;
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reg [31:0] rcounter;
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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data_buffer <= 8'b0;
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wcounter <= 32'b0;
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rcounter <= 32'b0;
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end else if (write_enable) begin
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memory[bank][addr] <= data_in;
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wcounter <= wcounter + 1;
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end else begin
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data_buffer <= memory[bank][addr];
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rcounter <= rcounter + 1;
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end
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end
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assign data_out = data_buffer;
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assign out_counter = ocounter;
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endmodule
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