mirror of https://github.com/XS-MLVP/picker.git
18 lines
388 B
Verilog
18 lines
388 B
Verilog
module RandomGenerator (
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input wire clk,
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input wire reset,
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input [15:0] seed,
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output [15:0] random_number
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);
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reg [15:0] lfsr;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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lfsr <= seed;
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end else begin
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lfsr <= {lfsr[14:0], lfsr[15] ^ lfsr[14]};
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end
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end
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assign random_number = lfsr;
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endmodule |