picker/example/DualPortStackCb
J. Wang fa9c9bfe63
Adopt slang as default SystemVerilog frontend and clean up codegen (#80)
* feat(parser): adopt slang as the default SystemVerilog frontend

- replace export RTL parsing with slang elaboration
- replace pack transaction parsing with slang
- remove Verible from normal parser and packaging flows
- fetch pinned slang and fmt releases via make init
- refresh tests and docs for the slang-based workflow

* fix(codegen): resolve filelist-relative inputs and quiet false missing-file logs

* refact(codegen): tidy up content about `_with_slang`

* feat(verible): Remove content about verible

* fix(gcc): Fix ignored attributes in gcc

* fix(parser): avoid gcc ambiguous overload in uvm parse_sv_transactions
2026-03-27 11:04:20 +08:00
..
dual_port_stack.v example: add DualPortStackCb 2024-11-26 13:58:51 +08:00
example.cpp fix #24 : remove dpi set function for output signal, which case multi-driven 2024-12-12 06:11:36 +00:00
example.go example: add DualPortStackCb 2024-11-26 13:58:51 +08:00
example.java fix(issue #36): add dut name to pakage name 2025-04-30 11:23:00 +08:00
example.py example: add DualPortStackCb 2024-11-26 13:58:51 +08:00
example.scala fix(issue #36): add dut name to pakage name 2025-04-30 11:23:00 +08:00
example_async.py Fix typo of example_async.py 2025-08-06 11:23:10 +08:00
release-verilator.sh Adopt slang as default SystemVerilog frontend and clean up codegen (#80) 2026-03-27 11:04:20 +08:00