mirror of https://github.com/XS-MLVP/picker.git
35 lines
521 B
Verilog
35 lines
521 B
Verilog
// A verilog 128-bit full adder with carry in and carry out
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module Adder #(
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parameter WIDTH = 128
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) (
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input [WIDTH-1:0] a,
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input [WIDTH-1:0] b,
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input cin,
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output [WIDTH-1:0] sum,
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output cout
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);
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assign {cout, sum} = a + b + cin;
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endmodule
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module Adder_128 (
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input [127:0] a,
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input [127:0] b,
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input cin,
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output [127:0] sum,
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output cout
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);
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Adder #(
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.WIDTH(128)
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) adder (
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.a(a),
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.b(b),
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.cin(cin),
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.sum(sum),
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.cout(cout)
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);
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endmodule |