mirror of https://github.com/XS-MLVP/picker.git
43 lines
888 B
Verilog
43 lines
888 B
Verilog
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module multi_clock (
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input wire clk1,
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input wire clk2,
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input wire clk3,
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input wire clk4,
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input wire clk5,
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input wire clk6,
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output reg [31:0] reg1,
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output reg [31:0] reg2,
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output reg [31:0] reg3,
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output reg [31:0] reg4,
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output reg [31:0] reg5,
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output reg [31:0] reg6
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);
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initial begin
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reg1 = 32'b0;
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reg2 = 32'b0;
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reg3 = 32'b0;
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reg4 = 32'b0;
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reg5 = 32'b0;
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reg6 = 32'b0;
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end
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always @(posedge clk1) begin
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reg1 <= reg1 + 1;
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end
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always @(posedge clk2) begin
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reg2 <= reg2 + 1;
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end
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always @(posedge clk3) begin
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reg3 <= reg3 + 1;
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end
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always @(posedge clk4) begin
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reg4 <= reg4 + 1;
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end
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always @(posedge clk5) begin
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reg5 <= reg5 + 1;
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end
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always @(posedge clk6) begin
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reg6 <= reg6 + 1;
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end
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endmodule
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