mirror of https://github.com/XS-MLVP/picker.git
139 lines
4.4 KiB
Systemverilog
139 lines
4.4 KiB
Systemverilog
//==============================================================================//
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// File : example_uvm_dut.sv
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// Author : automatically generated by picker
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// Date : 2025-12-15 20:01:23
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// Description: UVM testbench for adder_trans example
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// Supports bidirectional communication (Python ←→ UVM)
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// - Driver receives transactions from Python
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// - Monitor sends transactions back to Python
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// Version : v0.1
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//==============================================================================//
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import uvm_pkg::*;
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import uvmc_pkg::*;
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// Include common utility package before agents
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`include "adder_trans/utils_pkg.sv"
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// Single transaction mode: include transaction definition and agent
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`include "../example/Pack/adder_trans.sv"
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`include "adder_trans/xagent.sv"
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interface example_interface(input clk, input rst_n);
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// Add your DUT interface signals here if needed
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// For this example, we just verify that transactions are received
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endinterface //example_interface
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class adder_python_monitor extends adder_trans_xmonitor;
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`uvm_component_utils(adder_python_monitor)
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adder_trans prev_tr;
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function new(string name = "adder_python_monitor", uvm_component parent = null);
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super.new(name, parent);
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endfunction
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virtual function void build_phase(uvm_phase phase);
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super.build_phase(phase);
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prev_tr = adder_trans::type_id::create("prev_tr");
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endfunction
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// Monitor independently samples interface
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virtual task run_phase(uvm_phase phase);
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adder_trans tr;
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forever begin
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// Wait for signal change (input change indicates new transaction)
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// Wait for combinational logic to settle
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#1step
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// Sample all signals
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tr = adder_trans::type_id::create("tr");
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tr.randomize();
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sequence_send(tr);
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prev_tr.copy(tr);
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`uvm_info("ADDER_MON", $sformatf("Sampled: a=0x%0x, b=0x%0x, cin=%0d -> sum=0x%0x, cout=%0d",
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tr.a, tr.b, tr.cin, tr.sum, tr.cout), UVM_LOW)
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end
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endtask
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endclass
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class example_env extends uvm_env;
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`uvm_component_utils(example_env)
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// Single transaction mode
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adder_trans_xagent xagent;
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adder_trans_xagent_config xagent_config;
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adder_python_monitor mon;
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function new (string name = "example_env", uvm_component parent = null);
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super.new(name,parent);
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// Single transaction config - use factory override for custom driver type
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xagent_config = new("xagent_config");
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// Set to UVM_ACTIVE for both monitor and driver (default behavior)
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xagent_config.is_active = UVM_PASSIVE; // UVM_ACTIVE;
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uvm_config_db#(adder_trans_xagent_config)::set(this,"xagent", "adder_trans_xagent_config", xagent_config);
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// Use factory override to replace default driver with example driver
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set_type_override_by_type(adder_trans_xmonitor::get_type(), adder_python_monitor::get_type());
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endfunction
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function void build_phase(uvm_phase phase);
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super.build_phase(phase);
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// Build single agent
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xagent = adder_trans_xagent::type_id::create("xagent",this);
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endfunction
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virtual task main_phase(uvm_phase phase);
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phase.raise_objection(this);
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// Just wait for Python to send transactions
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// Python controls the simulation time via Step() calls
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#10000; // Wait long enough for Python to complete
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phase.drop_objection(this);
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endtask
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endclass
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class example_test extends uvm_test;
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`uvm_component_utils(example_test)
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example_env env;
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function new (string name = "example_test", uvm_component parent = null);
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super.new(name,parent);
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endfunction
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function void build_phase(uvm_phase phase);
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super.build_phase(phase);
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env = example_env::type_id::create("example_env",this);
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endfunction
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endclass
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module sv_main;
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logic clk;
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logic rst_n;
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example_interface vif(clk,rst_n);
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initial begin
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clk = 0;
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forever begin
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#2
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clk <= ~clk;
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end
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end
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initial begin
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rst_n <= 1'b0;
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#10
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rst_n <= 1'b1;
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end
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initial begin
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uvm_config_db #(virtual example_interface)::set(null,"uvm_test_top.example_env","vif",vif);
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run_test("example_test");
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end
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endmodule
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