mirror of https://github.com/XS-MLVP/picker.git
35 lines
791 B
Verilog
35 lines
791 B
Verilog
module vpi(input wire clk,
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output wire v1,
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output wire [7:0] v2,
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output wire [31:0] v3,
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output wire [63:0] v4
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);
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reg _v1;
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reg [7:0] _v2;
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reg [31:0] _v3;
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reg [63:0] _v4;
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reg _v1_base;
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reg [7:0] _v2_base;
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reg [31:0] _v3_base;
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reg [63:0] _v4_base;
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assign v1 = _v1;
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assign v2 = _v2;
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assign v3 = _v3;
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assign v4 = _v4;
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always @(posedge clk) begin
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_v1 <= _v1 + 1 + _v1_base;
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_v2 <= _v2 + 1 + _v2_base;
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_v3 <= _v3 + 1 + _v3_base;
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_v4 <= _v4 + 1 + _v4_base;
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end
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initial begin
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_v1 = 1'b0;
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_v2 = 8'b0;
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_v3 = 32'b0;
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_v4 = 64'b0;
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_v2_base = 8'b0;
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_v3_base = 32'b0;
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_v4_base = 64'b0;
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end
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endmodule
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