mirror of https://github.com/XS-MLVP/picker.git
96 lines
2.7 KiB
Systemverilog
96 lines
2.7 KiB
Systemverilog
import uvm_pkg::*;
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import uvmc_pkg::*;
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`include "../adder_trans.sv"
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`include "../adder_trans/adder_trans_xagent.sv"
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interface example_interface(input clk, input rst_n);
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int data;
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logic valid;
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endinterface
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class example_driver extends adder_trans_xdriver;
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`uvm_component_utils(example_driver);
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function new (string name = "example_driver", uvm_component parent = null);
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super.new(name,parent);
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endfunction
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virtual function void build_phase(uvm_phase phase);
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super.build_phase(phase);
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endfunction
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function sequence_receive(adder_trans tr);
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`uvm_info("example_driver", $sformatf("uvm receive message: \n%s",tr.sprint()), UVM_LOW)
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endfunction
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endclass
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class example_env extends uvm_env;
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`uvm_component_utils(example_env)
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adder_trans_xagent xagent;
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adder_trans_xagent_config xagent_config;
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virtual example_interface vif;
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function new (string name = "example_env", uvm_component parent = null);
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super.new(name,parent);
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xagent_config = new("xagent_config");
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xagent_config.drv_type = example_driver::get_type();
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uvm_config_db#(adder_trans_xagent_config)::set(this,"xagent", "adder_trans_xagent_config", xagent_config);
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endfunction
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function void build_phase(uvm_phase phase);
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super.build_phase(phase);
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xagent = adder_trans_xagent::type_id::create("xagent",this);
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if(!uvm_config_db#(virtual example_interface)::get(this,"","vif",vif))
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`uvm_fatal("example_env","virtual interface must be set for vif")
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endfunction
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virtual task main_phase(uvm_phase phase);
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phase.raise_objection(this);
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for (int i = 0; i < 30; i++)begin
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@(posedge vif.clk)
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vif.data <= i;
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vif.valid <= 1'b1;
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@(posedge vif.clk)
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vif.valid <= 1'b0;
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end
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endtask
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endclass
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class example_test extends uvm_test;
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`uvm_component_utils(example_test)
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example_env env;
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function new (string name = "example_test", uvm_component parent = null);
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super.new(name,parent);
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endfunction
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function void build_phase(uvm_phase phase);
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super.build_phase(phase);
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env = example_env::type_id::create("example_env",this);
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endfunction
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endclass
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module sv_main;
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logic clk;
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logic rst_n;
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example_interface vif(clk,rst_n);
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initial begin
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clk = 0;
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forever begin
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#2
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clk <= ~clk;
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end
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end
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initial begin
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rst_n <= 1'b0;
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#10
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rst_n <= 1'b0;
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end
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initial begin
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uvm_config_db #(virtual example_interface)::set(null,"uvm_test_top.example_env","vif",vif);
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run_test("example_test");
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end
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endmodule |