Commit Graph

61 Commits

Author SHA1 Message Date
Zhicheng 0063b63f58
Add backend simulator GSIM support (#50)
New features:

- add firrtl parser
- add gsim example
- support gsim complete
- support internal signal parse for gsim
- test gsim Nutshell success
- readme: update gsim info

---------
Co-authored-by: Makiras <xieyunlonglong@gmail.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
2025-08-13 15:16:15 +08:00
FrankOu2001 679a922b11 Fix(cmake): Correctly select VERILATOR_ROOT
Modify the selection logic for `CMD_VERILATOR_ROOT` in `verilator.cmake`.

When using a Verilator distribution that is not installed from a package manager or compiled from source, such as the one provided by [oss-cad-suite](https://github.com/YosysHQ/oss-cad-suite-build), the output of `verilator -V` can be as follows:

```bash
Summary of configuration:
  Compiled in defaults if not in environment:
    SYSTEMC           =
    SYSTEMC_ARCH      =
    SYSTEMC_INCLUDE   =
    SYSTEMC_LIBDIR    =
    VERILATOR_ROOT    = /yosyshq/share/verilator
    SystemC system-wide = 0

Environment:
    MAKE              =
    PERL              =
    PYTHON3           =
    SYSTEMC           =
    SYSTEMC_ARCH      =
    SYSTEMC_INCLUDE   =
    SYSTEMC_LIBDIR    =
    VERILATOR_BIN     =
    VERILATOR_ROOT    = /opt/oss-cad-suite/share/verilator
```

This output provides two `VERILATOR_ROOT` paths. The one under the `Environment` section is the intended path for this setup.

The previous selection logic would incorrectly choose the first `VERILATOR_ROOT` it found, which was the incorrect one from the `Compiled in defaults` section.

This patch updates the logic to prioritize the `VERILATOR_ROOT` from the `Environment` section. It will only fall back to the `Compiled in defaults` path if the environment one is not available.
2025-08-04 10:56:59 +08:00
Makiras ba5127bd4b
add new feat: appimage (#43)
* [fix] performance analysis and internal signal config

* add dockerfile and ci builder

* [feat] add appimage building process, basic cpp support

* [fix] appimage multi-language support, appimage mode detection

* [feat] integrate verible-verilog-syntax in appiamge, fix dynamic lib search priority

* try ci appimages

* [fix] cmake CMP0171 for codegen keyword

* [fix] cmake CMP0171 for codegen keyword

* [fix] cmake CMP0171 for codegen keyword

* [fix] cmake CMP0171 for codegen keyword

* [fix] cmake CMP0171 for codegen keyword

* [fix] arm64 autobuild

* [fix] arm64 autobuild

* [fix] tag right release

* [fix] format and typos

* [fix] typo explaination should be corrected to 'explanation'

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>

---------

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
2025-07-08 16:04:14 +08:00
yaozhicheng bbca48b8ae feat: export new API GetXClock/GetXPort/OpenWaveform/CloseWaveform 2025-04-30 11:23:00 +08:00
yaozhicheng efd44173d9 python: add more assert int GetInternalSignal 2025-04-30 11:23:00 +08:00
yaozhicheng 66ad33e179 python: support xdata array in GetInternalSignal 2025-04-30 11:23:00 +08:00
yaozhicheng 83b8e5c8c4 python: refine GetInternalSignal & GetInternalSignalList to support both memdirect and vpi 2025-04-30 11:23:00 +08:00
Makiras ddce03de56 add CacheSignalCFG example 2025-04-30 11:23:00 +08:00
Makiras 0db637f940 fix: XClock Order 2025-04-30 11:23:00 +08:00
Makiras cf35240762 refact: passthrough C pointer Step() to xcomm XClock() instead of python wrapper 2025-04-30 11:23:00 +08:00
J. Wang 2528418fe3
Fix typo of `ACondition` (#34) 2025-03-25 16:22:12 +08:00
Makiras 72d4d70490 [WIP] add golang example, waiting for xdata update 2025-01-08 11:35:10 +08:00
Makiras 7b70577b45 feat: add FlushWaveForm() to write wave immediately, for debugger
add doc: API statement
2025-01-08 11:35:10 +08:00
yaozhicheng 8cdeb3ac10 template: add GetInternalSignal for python 2025-01-08 11:35:10 +08:00
Makiras 3aa0b3ccae feat: add vpi functions export and internal signal iteration list 2025-01-08 11:35:10 +08:00
yaozhicheng acd690c3ab typo: fixed 2024-11-19 13:03:48 +08:00
yaozhicheng 3358b79b82 python: keep example.py in result 2024-11-19 12:44:33 +08:00
yaozhicheng 01706450d2 pyhon: mv module files to tdir 2024-11-18 18:06:50 +08:00
yaozhicheng 5fd42a6ecb Python DUT: add setattr assertion 2024-10-25 12:59:40 +08:00
yaozhicheng 325ecd0269 pyton: touch __init__.py in output dir 2024-09-19 15:27:18 +08:00
yaozhicheng 7358d986b7 refine: default purge DUT 2024-08-27 16:34:48 +08:00
yaozhicheng ca4a946c80 new feature: add cascaded ports for python 2024-07-29 17:46:23 +08:00
yaozhicheng ff7e1b984f refine: del exec __init__ 2024-07-29 16:17:04 +08:00
yaozhicheng ed1bd11e4a add option --cp_lib 2024-07-29 05:46:49 +00:00
yaozhicheng 05952736a5 cmake: add func search_libs 2024-07-26 13:41:42 +08:00
yaozhicheng 5e09957aa3 fix: handle import error 2024-07-26 12:23:09 +08:00
Makiras 538409a8b3 update cmake config for multi verilator version and support higher verilator version
picker will find VERILATOR_ROOT by using Verilator 5.026 2024-06-15 rev v5.026

Copyright 2003-2024 by Wilson Snyder.  Verilator is free software; you can
redistribute it and/or modify the Verilator internals under the terms of
either the GNU Lesser General Public License Version 3 or the Perl Artistic
License Version 2.0.

See https://verilator.org for documentation

Summary of configuration:
  Compiled in defaults if not in environment:
    SYSTEMC            =
    SYSTEMC_ARCH       =
    SYSTEMC_INCLUDE    =
    SYSTEMC_LIBDIR     =
    VERILATOR_ROOT     = /opt/verilator5/share/verilator
    SystemC system-wide = 0

Environment:
    MAKE               =
    PERL               =
    SYSTEMC            =
    SYSTEMC_ARCH       =
    SYSTEMC_INCLUDE    =
    SYSTEMC_LIBDIR     =
    VERILATOR_BIN      =
    VERILATOR_ROOT     = /opt/verilator5/share/verilator

Supported features (compiled-in or forced by environment):
    COROUTINES         = 1
    SYSTEMC            =  command
2024-07-25 17:01:37 +08:00
Makiras 98d467d317 optimize argc and argv passage, auto detect whether the argv[0] is filename or args 2024-07-25 06:58:51 +00:00
yaozhicheng c88d3c7d05 fix: []string args for dut 2024-07-25 14:26:58 +08:00
Makiras 2d8e640ef8 update Caches and RnadomGenerator VCS example 2024-07-17 10:34:01 +08:00
yaozhicheng 772cd9efe8 uniform mk 2024-07-17 10:34:01 +08:00
yaozhicheng 805753f834 uniform dut.xclock, dut.xport 2024-07-17 10:34:01 +08:00
yaozhicheng c716808fd2 clean up workspace 2024-07-17 10:34:01 +08:00
yaozhicheng 3f857c4dbb refine user APIs 2024-07-17 10:34:01 +08:00
Makiras 33e7314c73 refactor libDUT init function 2024-07-17 10:34:01 +08:00
Makiras a777499620 optimize multi-instance with hash DPI func name
also add dlclose to release namespace and flag to reuse main namespace
2024-07-17 10:34:01 +08:00
Makiras 7cdd8d576c refacted DutUnifiedBase without inhert and change dlmopen abstract level
due to dlmopen DPI library is simulator-related, we choose to dlmopen whole libUT.so without simulator-related code
2024-07-17 10:34:01 +08:00
Makiras a1192bd277 add multi-instance support with dlmopen for VERILATOR 2024-07-17 10:34:01 +08:00
yaozhicheng f83be8ae7f mute output 2024-06-25 19:48:07 +08:00
yaozhicheng 32d7ca44c6 add default NULL dpi read and write 2024-06-03 15:57:06 +08:00
Miical ad03526c25 Update the python template to change the waveform and coverage file names at initialization 2024-04-29 16:33:17 +08:00
FrankOu2001 292151ec52 Update & Fix bugs: Wrap methods `StepRis` and `StepFal` of `xclock` in `template/python/dut.py`; Fixed bugs in `template/python/dut.py` where calling async functions resulted in coroutines never being awaited. 2024-04-28 11:23:47 +08:00
FrankOu2001 eb5b4b4b06 Fix bugs: Fixed a bug in `template/python/dut.py` where it should have been "RunStep" instead of "RunSetp". 2024-04-27 13:36:42 +08:00
Makiras e4d55c8db3 fix bugs: coverage needs verbose mode, example finalize 2024-04-25 16:18:01 +08:00
Makiras af57c824e1 fix rpath using relative path need $ORIGIN 2024-04-25 16:18:01 +08:00
Makiras f61a0118b1 fix: verilator failed to dump wave in python, optimize example 2024-03-19 06:32:14 +00:00
Makiras 18822e1301 add non-root include/lib search 2024-01-25 02:45:42 +00:00
Miical efc0a13f3d add python test after generation 2024-01-16 02:06:48 +00:00
Miical c5a10f42b6 modify the Python template, add XPin, and package the generated Python code as a Python package. 2023-12-26 11:19:24 +08:00
Makiras e900e948c3 workaround with LDPRELOAD for VCS 2023-12-14 09:09:52 +00:00