Commit Graph

33 Commits

Author SHA1 Message Date
FrankOu2001 679a922b11 Fix(cmake): Correctly select VERILATOR_ROOT
Modify the selection logic for `CMD_VERILATOR_ROOT` in `verilator.cmake`.

When using a Verilator distribution that is not installed from a package manager or compiled from source, such as the one provided by [oss-cad-suite](https://github.com/YosysHQ/oss-cad-suite-build), the output of `verilator -V` can be as follows:

```bash
Summary of configuration:
  Compiled in defaults if not in environment:
    SYSTEMC           =
    SYSTEMC_ARCH      =
    SYSTEMC_INCLUDE   =
    SYSTEMC_LIBDIR    =
    VERILATOR_ROOT    = /yosyshq/share/verilator
    SystemC system-wide = 0

Environment:
    MAKE              =
    PERL              =
    PYTHON3           =
    SYSTEMC           =
    SYSTEMC_ARCH      =
    SYSTEMC_INCLUDE   =
    SYSTEMC_LIBDIR    =
    VERILATOR_BIN     =
    VERILATOR_ROOT    = /opt/oss-cad-suite/share/verilator
```

This output provides two `VERILATOR_ROOT` paths. The one under the `Environment` section is the intended path for this setup.

The previous selection logic would incorrectly choose the first `VERILATOR_ROOT` it found, which was the incorrect one from the `Compiled in defaults` section.

This patch updates the logic to prioritize the `VERILATOR_ROOT` from the `Environment` section. It will only fall back to the `Compiled in defaults` path if the environment one is not available.
2025-08-04 10:56:59 +08:00
Makiras ba5127bd4b
add new feat: appimage (#43)
* [fix] performance analysis and internal signal config

* add dockerfile and ci builder

* [feat] add appimage building process, basic cpp support

* [fix] appimage multi-language support, appimage mode detection

* [feat] integrate verible-verilog-syntax in appiamge, fix dynamic lib search priority

* try ci appimages

* [fix] cmake CMP0171 for codegen keyword

* [fix] cmake CMP0171 for codegen keyword

* [fix] cmake CMP0171 for codegen keyword

* [fix] cmake CMP0171 for codegen keyword

* [fix] cmake CMP0171 for codegen keyword

* [fix] arm64 autobuild

* [fix] arm64 autobuild

* [fix] tag right release

* [fix] format and typos

* [fix] typo explaination should be corrected to 'explanation'

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>

---------

Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
2025-07-08 16:04:14 +08:00
yaozhicheng 7df84adb88 fix(java/scala): fix pakage name 2025-04-30 11:23:00 +08:00
yaozhicheng 2a94e65732 fix(java/scala): make default example to pakage com.ut 2025-04-30 11:23:00 +08:00
yaozhicheng 10eb845acd fix(issue #36): add dut name to pakage name 2025-04-30 11:23:00 +08:00
yaozhicheng 1d09427913 fix(interlsignal/XCFG): Adapt to VPI and Mem direct internal signals 2025-04-30 11:23:00 +08:00
yaozhicheng 32f43c1769 new feat(swig): add GetInternalSignalList/GetInternalSignal for java && test pass 2025-04-30 11:23:00 +08:00
yaozhicheng f8706a0e89 fix(swig): add xcfg and test 2025-04-30 11:23:00 +08:00
yaozhicheng 7a2dc6a7f2 fix(swig): pack *_offset.yaml into jar file 2025-04-30 11:23:00 +08:00
yaozhicheng 97949c235b fix(swig): rename StringVector to avoid xcom confilict 2025-04-30 11:23:00 +08:00
yaozhicheng bbca48b8ae feat: export new API GetXClock/GetXPort/OpenWaveform/CloseWaveform 2025-04-30 11:23:00 +08:00
yaozhicheng 9a6773a070 XClock: new XClock with step func ptr 2025-04-30 11:23:00 +08:00
Makiras 9055cb1e6a add: java vpi internal signal example 2025-01-08 11:35:10 +08:00
yaozhicheng 966cdd2e90 fix purge: rm UT_{{tname}} 2024-11-19 11:19:46 +08:00
yaozhicheng ba41374748 add: support cascaded_signals for java 2024-08-28 15:47:06 +08:00
yaozhicheng 7358d986b7 refine: default purge DUT 2024-08-27 16:34:48 +08:00
yaozhicheng ed1bd11e4a add option --cp_lib 2024-07-29 05:46:49 +00:00
yaozhicheng ad39455c1e fix: fix cmake for vcs 2024-07-29 04:07:40 +00:00
Makiras 538409a8b3 update cmake config for multi verilator version and support higher verilator version
picker will find VERILATOR_ROOT by using Verilator 5.026 2024-06-15 rev v5.026

Copyright 2003-2024 by Wilson Snyder.  Verilator is free software; you can
redistribute it and/or modify the Verilator internals under the terms of
either the GNU Lesser General Public License Version 3 or the Perl Artistic
License Version 2.0.

See https://verilator.org for documentation

Summary of configuration:
  Compiled in defaults if not in environment:
    SYSTEMC            =
    SYSTEMC_ARCH       =
    SYSTEMC_INCLUDE    =
    SYSTEMC_LIBDIR     =
    VERILATOR_ROOT     = /opt/verilator5/share/verilator
    SystemC system-wide = 0

Environment:
    MAKE               =
    PERL               =
    SYSTEMC            =
    SYSTEMC_ARCH       =
    SYSTEMC_INCLUDE    =
    SYSTEMC_LIBDIR     =
    VERILATOR_BIN      =
    VERILATOR_ROOT     = /opt/verilator5/share/verilator

Supported features (compiled-in or forced by environment):
    COROUTINES         = 1
    SYSTEMC            =  command
2024-07-25 17:01:37 +08:00
yaozhicheng c88d3c7d05 fix: []string args for dut 2024-07-25 14:26:58 +08:00
yaozhicheng 772cd9efe8 uniform mk 2024-07-17 10:34:01 +08:00
yaozhicheng 805753f834 uniform dut.xclock, dut.xport 2024-07-17 10:34:01 +08:00
yaozhicheng c716808fd2 clean up workspace 2024-07-17 10:34:01 +08:00
yaozhicheng 55241b5a83 add scala suppor & test Adder pass 2024-07-17 10:34:01 +08:00
yaozhicheng 3f857c4dbb refine user APIs 2024-07-17 10:34:01 +08:00
Makiras 33e7314c73 refactor libDUT init function 2024-07-17 10:34:01 +08:00
Makiras 7cdd8d576c refacted DutUnifiedBase without inhert and change dlmopen abstract level
due to dlmopen DPI library is simulator-related, we choose to dlmopen whole libUT.so without simulator-related code
2024-07-17 10:34:01 +08:00
Makiras a1192bd277 add multi-instance support with dlmopen for VERILATOR 2024-07-17 10:34:01 +08:00
yaozhicheng ce5a54b037 simple_step.java -> example.java 2024-06-25 19:45:35 +08:00
yaozhicheng 3f2697749d add java support 2024-06-25 13:54:54 +08:00
Makiras e8374d56c7 Refactor the overall code logic.
Generate encapsulated C++ classes based on dpi and codegen.
2023-10-27 09:32:38 +00:00
yaozhicheng 48a5cf3376 update 2023-08-16 10:33:29 +08:00
yaozhicheng dd755fdfe6 update 2023-08-14 21:00:52 +08:00