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picker
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109 Commits

Author SHA1 Message Date
FrankOu2001 0b1e3554fb Update: Using the Boolean type to drive the Adder in Java. 2025-08-16 21:59:08 +08:00
Zhicheng 0063b63f58
Add backend simulator GSIM support (#50) 
New features:

- add firrtl parser
- add gsim example
- support gsim complete
- support internal signal parse for gsim
- test gsim Nutshell success
- readme: update gsim info

---------
Co-authored-by: Makiras <xieyunlonglong@gmail.com>
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
 2025-08-13 15:16:15 +08:00
FrankOu2001 912471d630 Fix typo of example_async.py 2025-08-06 11:23:10 +08:00
J. Wang eb9e61023b
Update example.java (#45) 2025-07-24 14:54:11 +08:00
Makiras 0903a84e90
[fix] parallel build error & non-appimage (#44) 2025-07-10 14:48:27 +08:00
yaozhicheng 7df84adb88 fix(java/scala): fix pakage name 2025-04-30 11:23:00 +08:00
yaozhicheng 10eb845acd fix(issue #36): add dut name to pakage name 2025-04-30 11:23:00 +08:00
yaozhicheng 4519c0dbc6 fix(interlsignal): use new GetInternalSignal interface 2025-04-30 11:23:00 +08:00
yaozhicheng 64b98a71a0 feat(swig): add GetInternalSignal/GetInternalSignalList for lua 2025-04-30 11:23:00 +08:00
yaozhicheng 32f43c1769 new feat(swig): add GetInternalSignalList/GetInternalSignal for java && test pass 2025-04-30 11:23:00 +08:00
yaozhicheng 0b6dd5dc6f feat(swig): add attrOf example 2025-04-30 11:23:00 +08:00
yaozhicheng 65cf7b22c3 fix(chisel): fix compile with jar path 2025-04-30 11:23:00 +08:00
yaozhicheng 3f7f8dfd8d refine example(chisel): add reserve internal signals demo 2025-04-30 11:23:00 +08:00
yaozhicheng 7f0ab3da56 fix(example): make waveFile as the class name in chiselUT 2025-04-30 11:23:00 +08:00
yaozhicheng a0f5db47e1 fix(example): add picker check in chiselUT 2025-04-30 11:23:00 +08:00
yaozhicheng aefc247da7 refine(example): chiselUT add inner-signal access 2025-04-30 11:23:00 +08:00
yaozhicheng 88ce73f1c9 refine(example): refine chiselUT example 2025-04-30 11:23:00 +08:00
yaozhicheng f8706a0e89 fix(swig): add xcfg and test 2025-04-30 11:23:00 +08:00
yaozhicheng e62ea8ac0a new example(chisel): add a chisel ut test example 2025-04-30 11:23:00 +08:00
yaozhicheng 047d426bd5 feat: test Open/CloseWaveform functions 2025-04-30 11:23:00 +08:00
yaozhicheng 3af2c8c32d python: refine typo 2025-04-30 11:23:00 +08:00
Makiras 09039290fb fix: too big gen_addr example 2025-04-30 11:23:00 +08:00
Makiras eb9e31d262 fix: remove in_out render for flat-rw 2025-04-30 11:23:00 +08:00
Makiras 870d8f648b fix: relative path emtpy cause use / 
verilator root hardcode, emem_direct rerun logic
 2025-04-30 11:23:00 +08:00
Makiras ddce03de56 add CacheSignalCFG example 2025-04-30 11:23:00 +08:00
yaozhicheng d16372b793 example: del -native 2025-04-30 11:23:00 +08:00
yaozhicheng bac81768d5 native: support native signal for python 2025-04-30 11:23:00 +08:00
J. Wang 2528418fe3
Fix typo of `ACondition` (#34) 2025-03-25 16:22:12 +08:00
Makiras a6699e679f fix: remove redundant code in InternalSignals example cpp file 2025-01-08 11:35:10 +08:00
yaozhicheng 16c55094c5 example-InternalSignals: add lua & scala 2025-01-08 11:35:10 +08:00
yaozhicheng d8e1d17bdf example: del comments 2025-01-08 11:35:10 +08:00
Makiras fcf7db4e9b add example: vpi interal support for cpp 2025-01-08 11:35:10 +08:00
Makiras 9055cb1e6a add: java vpi internal signal example 2025-01-08 11:35:10 +08:00
Makiras 72d4d70490 [WIP] add golang example, waiting for xdata update 2025-01-08 11:35:10 +08:00
Makiras 7b70577b45 feat: add FlushWaveForm() to write wave immediately, for debugger 
add doc: API statement
 2025-01-08 11:35:10 +08:00
yaozhicheng 3c1e6cc43f multi-lang: add Lua support 2025-01-08 11:35:10 +08:00
yaozhicheng a4388a5788 example: add InternalSignals 2025-01-08 11:35:10 +08:00
Makiras 3aa0b3ccae feat: add vpi functions export and internal signal iteration list 2025-01-08 11:35:10 +08:00
yaozhicheng 5e936f25e5 example: add MultiClock test 2024-12-13 17:28:49 +08:00
Makiras 3af0f4f195 fix #24 : remove dpi set function for output signal, which case multi-driven 
change clang-format line break from 80 characters to 120, and reformat the project cpp/hpp
 2024-12-12 06:11:36 +00:00
yaozhicheng 4dd5052fa8 example: add async example 2024-11-26 14:15:56 +08:00
yaozhicheng 0e8c0278a3 example: add DualPortStackCb 2024-11-26 13:58:51 +08:00
yaozhicheng 7755db113d example/RandomGenerator: add go/scala 2024-11-26 10:56:34 +08:00
yaozhicheng 59d3669ee2 example: move Finish to the last line 2024-11-19 16:48:42 +08:00
yaozhicheng 6adb49498b example: fix typo 2024-11-19 05:35:03 +00:00
yaozhicheng a16e123723 example: refine 2024-11-19 13:04:18 +08:00
yaozhicheng e2a9d5f2d8 example: python try import __init__ in example 2024-11-19 12:45:34 +08:00
yaozhicheng 9cd96a1122 exmaple: fix Cache --tdir 2024-11-19 12:23:18 +08:00
yaozhicheng 85d66f69f3 example: fix adder for vcs 2024-11-19 11:36:32 +08:00
yaozhicheng f83e2283bf exmaple adder: refine to vcs 2024-11-19 11:33:18 +08:00