13 Commits

Author	SHA1	Message	Date
J. Wang	fa9c9bfe63	Adopt slang as default SystemVerilog frontend and clean up codegen (#80) ... * feat(parser): adopt slang as the default SystemVerilog frontend - replace export RTL parsing with slang elaboration - replace pack transaction parsing with slang - remove Verible from normal parser and packaging flows - fetch pinned slang and fmt releases via make init - refresh tests and docs for the slang-based workflow * fix(codegen): resolve filelist-relative inputs and quiet false missing-file logs * refact(codegen): tidy up content about `_with_slang` * feat(verible): Remove content about verible * fix(gcc): Fix ignored attributes in gcc * fix(parser): avoid gcc ambiguous overload in uvm parse_sv_transactions	2026-03-27 11:04:20 +08:00
Makiras	742ef2d942	[feat]: optimize file option to optional, auto search file when sname is selected	2025-10-27 21:06:56 +08:00
Makiras	0903a84e90	[fix] parallel build error & non-appimage (#44)	2025-07-10 14:48:27 +08:00
yaozhicheng	7df84adb88	fix(java/scala): fix pakage name	2025-04-30 11:23:00 +08:00
yaozhicheng	10eb845acd	fix(issue #36): add dut name to pakage name	2025-04-30 11:23:00 +08:00
yaozhicheng	64b98a71a0	feat(swig): add GetInternalSignal/GetInternalSignalList for lua	2025-04-30 11:23:00 +08:00
yaozhicheng	32f43c1769	new feat(swig): add GetInternalSignalList/GetInternalSignal for java && test pass	2025-04-30 11:23:00 +08:00
yaozhicheng	f8706a0e89	fix(swig): add xcfg and test	2025-04-30 11:23:00 +08:00
yaozhicheng	3af2c8c32d	python: refine typo	2025-04-30 11:23:00 +08:00
Makiras	09039290fb	fix: too big gen_addr example	2025-04-30 11:23:00 +08:00
Makiras	eb9e31d262	fix: remove in_out render for flat-rw	2025-04-30 11:23:00 +08:00
Makiras	870d8f648b	fix: relative path emtpy cause use / ... verilator root hardcode, emem_direct rerun logic	2025-04-30 11:23:00 +08:00
Makiras	ddce03de56	add CacheSignalCFG example	2025-04-30 11:23:00 +08:00