12 Commits

Author	SHA1	Message	Date
Zhicheng	0063b63f58	Add backend simulator GSIM support (#50) ... New features: - add firrtl parser - add gsim example - support gsim complete - support internal signal parse for gsim - test gsim Nutshell success - readme: update gsim info --------- Co-authored-by: Makiras <xieyunlonglong@gmail.com> Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>	2025-08-13 15:16:15 +08:00
Makiras	4a7efd9701	feat: verilator direct memory access for internal	2025-04-30 11:23:00 +08:00
Makiras	3af0f4f195	fix #24 : remove dpi set function for output signal, which case multi-driven ... change clang-format line break from 80 characters to 120, and reformat the project cpp/hpp	2024-12-12 06:11:36 +00:00
yaozhicheng	2dc1901e60	support static multi-rtl-module	2024-09-18 15:20:00 +08:00
yaozhicheng	cc532efb36	fix options	2024-06-25 19:16:25 +08:00
SFangYy	eebad90ff0	add parse uvm transaction	2024-06-12 16:52:11 +08:00
Makiras	9055071c58	change cli library for pack function	2024-06-07 06:47:50 +00:00
Makiras	731eb34b90	rename mcv to picker	2024-01-16 02:05:56 +00:00
Makiras	7c275b40ce	add quick start example	2023-12-29 10:05:07 +00:00
Makiras	06751a12f8	optimize mcv output content ... add verbose mode and example project mode todo: add python support ,finetune vcs support	2023-12-11 08:36:32 +00:00
Makiras	c673f03c13	add support for internal signal configured by yaml ... refacted code	2023-11-17 07:56:14 +00:00
Makiras	46c5adbf03	optimize code organization, add trace&dump waves for verilator	2023-10-31 09:22:32 +00:00