Commit Graph

23 Commits

Author SHA1 Message Date
J. Wang fa9c9bfe63
Adopt slang as default SystemVerilog frontend and clean up codegen (#80)
* feat(parser): adopt slang as the default SystemVerilog frontend

- replace export RTL parsing with slang elaboration
- replace pack transaction parsing with slang
- remove Verible from normal parser and packaging flows
- fetch pinned slang and fmt releases via make init
- refresh tests and docs for the slang-based workflow

* fix(codegen): resolve filelist-relative inputs and quiet false missing-file logs

* refact(codegen): tidy up content about `_with_slang`

* feat(verible): Remove content about verible

* fix(gcc): Fix ignored attributes in gcc

* fix(parser): avoid gcc ambiguous overload in uvm parse_sv_transactions
2026-03-27 11:04:20 +08:00
Makiras ddce03de56 add CacheSignalCFG example 2025-04-30 11:23:00 +08:00
yaozhicheng a16e123723 example: refine 2024-11-19 13:04:18 +08:00
yaozhicheng 9cd96a1122 exmaple: fix Cache --tdir 2024-11-19 12:23:18 +08:00
Makiras d2e02ab3f6 bug fix: multiple source module names set fault
only optionally add count index when module count > 1
rename module_count to module_diffs, keep moudle.module_count
add PK_DEBUG for module_subfix debug, which is used to identify diff modules and multi same module
remove auto detect module name in  due to detect has been down in
add m_nums for empty
add  PK_DEBUG
remove break in  while processing multi m_names due to maybe 1 file has >1 modules

todo: only add relative tokens instead of all file  token in
2024-09-18 16:44:26 +08:00
Makiras 2d8e640ef8 update Caches and RnadomGenerator VCS example 2024-07-17 10:34:01 +08:00
yaozhicheng 5b104005a5 made pass on verilator 2024-07-17 10:34:01 +08:00
Makiras 542cef7223 update autobuild flags example 2024-07-17 10:34:01 +08:00
yaozhicheng f4b5f8deb5 exports -> export 2024-06-25 19:48:47 +08:00
Makiras 9055071c58 change cli library for pack function 2024-06-07 06:47:50 +00:00
Makiras fd5aa524c3 add autobuild and update xcomm version 2024-04-25 16:18:01 +08:00
Makiras f61a0118b1 fix: verilator failed to dump wave in python, optimize example 2024-03-19 06:32:14 +00:00
Makiras 731eb34b90 rename mcv to picker 2024-01-16 02:05:56 +00:00
Makiras 336e9d9d6c add verilator coverage collection 2023-12-27 06:46:18 +00:00
Makiras 280802d10c add Simlator flags and CC flags option 2023-12-26 07:37:50 +00:00
Makiras 43c13956a8 support multi-source-file 2023-12-26 06:39:49 +00:00
Makiras 81b5521004 [wip] for python 2023-12-14 06:34:58 +00:00
Makiras 3561f26d5f optimize cmake project generate 2023-12-12 03:39:41 +00:00
Makiras 4ff2e087f8 finetune VCS support 2023-12-11 09:37:28 +00:00
Makiras 06751a12f8 optimize mcv output content
add verbose mode and example project mode
todo: add python support ,finetune vcs support
2023-12-11 08:36:32 +00:00
Makiras c673f03c13 add support for internal signal configured by yaml
refacted code
2023-11-17 07:56:14 +00:00
Makiras 192f5e9a00 add VCD&FST support 2023-11-09 02:53:09 +00:00
Makiras 5cf5249605 add cache test, reorganized structural, add clang-format 2023-11-09 02:33:16 +00:00