Commit Graph

10 Commits

Author SHA1 Message Date
FrankOu2001 bc3570eaaa refactor: Enhance waveform export and rename APIs
- Store waveform and coverage export settings in the DUT class.
- **BREAKING CHANGE**: Renamed waveform control APIs to clarify pause/resume semantics:
  - `OpenWaveform` -> `ResumeWaveformDump`
  - `CloseWaveform` -> `PauseWaveformDump`
  - `WaveformClosed` -> `WaveformPaused`
- Fix syntax error in `template/mem_direct/Makefile`.
2025-09-04 15:38:35 +08:00
Makiras 82ff87768f
[feat] add ci tests and workflow optimization
chore(ci,test,build): add CI/tests for GSIM, .sv and Java; xcomm fallback; test preflight
- CI: install default-jdk for Java tests
- Tests: add GSIM export smoke, .sv verilator build, Java export
- test/Makefile: add preflight to auto-clean + rebuild with python+java when missing
- Build: Makefile init falls back to latest master for xcomm when branch missing
- Wire new tests into default test targets
- Run build-and-test and appimage-build on all branches
- Restrict appimage-publish and docker-build-push to master
- Reuse build directory via artifact between jobs to avoid rebuilds
- Fix deps: install swig in CI and AppImage job
- Makefile appimage target reuses existing build/ for install & packing
- Remove standalone AppImage/docker workflows to prevent duplicate runs
- build-and-test: install base toolchain and Kitware CMake
- Build and install SWIG v4.2.1 from source
- Build and install Verilator v5.018 from source
- appimage-build: reuse build/ artifact; minimal deps (appimagetool, linuxdeploy)
- Keep: appimage-build on all branches; publish/docker only on master
- 在 test/Makefile 中让 smoke、sv_build、gsim_smoke 依赖 preflight
- 避免 preflight 执行 clean/rebuild 时其他并发目标找不到构建产物
- preflight 完成后仍保留测试阶段的并行度
2025-09-03 14:24:53 +08:00
yaozhicheng 0b6dd5dc6f feat(swig): add attrOf example 2025-04-30 11:23:00 +08:00
yaozhicheng 65cf7b22c3 fix(chisel): fix compile with jar path 2025-04-30 11:23:00 +08:00
yaozhicheng 3f7f8dfd8d refine example(chisel): add reserve internal signals demo 2025-04-30 11:23:00 +08:00
yaozhicheng 7f0ab3da56 fix(example): make waveFile as the class name in chiselUT 2025-04-30 11:23:00 +08:00
yaozhicheng a0f5db47e1 fix(example): add picker check in chiselUT 2025-04-30 11:23:00 +08:00
yaozhicheng aefc247da7 refine(example): chiselUT add inner-signal access 2025-04-30 11:23:00 +08:00
yaozhicheng 88ce73f1c9 refine(example): refine chiselUT example 2025-04-30 11:23:00 +08:00
yaozhicheng e62ea8ac0a new example(chisel): add a chisel ut test example 2025-04-30 11:23:00 +08:00