8 Commits

Author	SHA1	Message	Date
yichun	301c403754	UVS support in picker (phase 1)	2026-05-12 14:06:51 +08:00
J. Wang	fa9c9bfe63	Adopt slang as default SystemVerilog frontend and clean up codegen (#80) ... * feat(parser): adopt slang as the default SystemVerilog frontend - replace export RTL parsing with slang elaboration - replace pack transaction parsing with slang - remove Verible from normal parser and packaging flows - fetch pinned slang and fmt releases via make init - refresh tests and docs for the slang-based workflow * fix(codegen): resolve filelist-relative inputs and quiet false missing-file logs * refact(codegen): tidy up content about `_with_slang` * feat(verible): Remove content about verible * fix(gcc): Fix ignored attributes in gcc * fix(parser): avoid gcc ambiguous overload in uvm parse_sv_transactions	2026-03-27 11:04:20 +08:00
FrankOu2001	912471d630	Fix typo of example_async.py	2025-08-06 11:23:10 +08:00
yaozhicheng	10eb845acd	fix(issue #36): add dut name to pakage name	2025-04-30 11:23:00 +08:00
J. Wang	2528418fe3	Fix typo of `ACondition` (#34)	2025-03-25 16:22:12 +08:00
Makiras	3af0f4f195	fix #24 : remove dpi set function for output signal, which case multi-driven ... change clang-format line break from 80 characters to 120, and reformat the project cpp/hpp	2024-12-12 06:11:36 +00:00
yaozhicheng	4dd5052fa8	example: add async example	2024-11-26 14:15:56 +08:00
yaozhicheng	0e8c0278a3	example: add DualPortStackCb	2024-11-26 13:58:51 +08:00