add N32G4XM_STB board support
add nationz N32G4XM_STB board support
This commit is contained in:
parent
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eeb2090d50
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/*****************************************************************************
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* Copyright (c) 2019, Nations Technologies Inc.
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*
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* All rights reserved.
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* ****************************************************************************
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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||||
* - Redistributions of source code must retain the above copyright notice,
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||||
* this list of conditions and the disclaimer below.
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*
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* Nations' name may not be used to endorse or promote products derived from
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||||
* this software without specific prior written permission.
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||||
*
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||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
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||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
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||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ****************************************************************************/
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/**
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* @file log.h
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* @author Nations Solution Team
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* @version v1.0.0
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*
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* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
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*/
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#ifndef __LOG_H__
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#define __LOG_H__
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#ifndef LOG_ENABLE
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#define LOG_ENABLE 1
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#endif
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#if LOG_ENABLE
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#include <stdio.h>
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#define LOG_NONE 0
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#define LOG_ERROR 10
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#define LOG_WARNING 20
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#define LOG_INFO 30
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#define LOG_DEBUG 40
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#ifndef LOG_LEVEL
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#define LOG_LEVEL LOG_DEBUG
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#endif
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#if LOG_LEVEL >= LOG_INFO
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#define log_info(...) printf(__VA_ARGS__)
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#else
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#define log_info(...)
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#endif
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#if LOG_LEVEL >= LOG_ERROR
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#define log_error(...) printf(__VA_ARGS__)
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#else
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#define log_error(...)
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#endif
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#if LOG_LEVEL >= LOG_WARNING
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#define log_warning(...) printf(__VA_ARGS__)
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#else
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#define log_warning(...)
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#endif
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#if LOG_LEVEL >= LOG_DEBUG
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#define log_debug(...) printf(__VA_ARGS__)
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#else
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#define log_debug(...)
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#endif
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void log_init(void);
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#else /* !LOG_ENABLE */
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#define log_info(...)
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#define log_warning(...)
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#define log_error(...)
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#define log_debug(...)
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#define log_init()
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#endif
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#define log_func() log_debug("call %s\r\n", __FUNCTION__)
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#endif /* __LOG_H__ */
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/*****************************************************************************
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* Copyright (c) 2019, Nations Technologies Inc.
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*
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* All rights reserved.
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* ****************************************************************************
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Nations' name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ****************************************************************************/
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/**
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* @file main.h
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* @author Nations Solution Team
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* @version v1.0.0
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*
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* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
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*/
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#ifndef __MAIN_H__
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#define __MAIN_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "n32g45x.h"
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#ifdef __cplusplus
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}
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#endif
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#endif /* __MAIN_H__ */
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#ifndef __MCU_INIT_H
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#define __MCU_INIT_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdio.h>
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#include "main.h"
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#include "log.h"
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#include "tos_k.h"
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void board_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /*__ __MCU_INIT_H */
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/*****************************************************************************
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* Copyright (c) 2019, Nations Technologies Inc.
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*
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* All rights reserved.
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* ****************************************************************************
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
|
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* this list of conditions and the disclaimer below.
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*
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* Nations' name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ****************************************************************************/
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/**
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* @file n32g45x_it.h
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* @author Nations Solution Team
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* @version v1.0.0
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*
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* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
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*/
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#ifndef __N32G45X_IT_H__
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#define __N32G45X_IT_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "n32g45x.h"
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void NMI_Handler(void);
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void HardFault_Handler(void);
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void MemManage_Handler(void);
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void BusFault_Handler(void);
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void UsageFault_Handler(void);
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void SVC_Handler(void);
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void DebugMon_Handler(void);
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void PendSV_Handler(void);
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void SysTick_Handler(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __N32G45X_IT_H__ */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/*****************************************************************************
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* Copyright (c) 2019, Nations Technologies Inc.
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*
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* All rights reserved.
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* ****************************************************************************
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* - Redistributions of source code must retain the above copyright notice,
|
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* this list of conditions and the disclaimer below.
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*
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* Nations' name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ****************************************************************************/
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/**
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* @file log.c
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* @author Nations Solution Team
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* @version v1.0.0
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*
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* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
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*/
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#include "log.h"
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#if LOG_ENABLE
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#include "n32g45x.h"
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#include "n32g45x_gpio.h"
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#include "n32g45x_usart.h"
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#include "n32g45x_rcc.h"
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#define LOG_USARTx USART2
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#define LOG_PERIPH RCC_APB1_PERIPH_USART2
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#define LOG_GPIO GPIOB
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#define LOG_PERIPH_GPIO RCC_APB2_PERIPH_GPIOB
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#define LOG_REMAP GPIO_RMP3_USART2
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#define LOG_TX_PIN GPIO_PIN_4
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#define LOG_RX_PIN GPIO_PIN_5
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void log_init(void)
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{
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GPIO_InitType GPIO_InitStructure;
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USART_InitType USART_InitStructure;
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// close JTAG
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RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO | LOG_PERIPH_GPIO, ENABLE);
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if (LOG_REMAP)
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{
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if (LOG_REMAP == GPIO_RMP3_USART2)
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{
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// release PB4
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GPIO_ConfigPinRemap(GPIO_RMP_SW_JTAG_NO_NJTRST, ENABLE);
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}
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GPIO_ConfigPinRemap(LOG_REMAP, ENABLE);
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}
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RCC_EnableAPB1PeriphClk(LOG_PERIPH, ENABLE);
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GPIO_InitStructure.Pin = LOG_TX_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitPeripheral(LOG_GPIO, &GPIO_InitStructure);
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//GPIO_InitStructure.Pin = LOG_RX_PIN;
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//GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
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//GPIO_InitPeripheral(LOG_GPIO, &GPIO_InitStructure);
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USART_InitStructure.BaudRate = 115200;
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USART_InitStructure.WordLength = USART_WL_8B;
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USART_InitStructure.StopBits = USART_STPB_1;
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USART_InitStructure.Parity = USART_PE_NO;
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USART_InitStructure.HardwareFlowControl = USART_HFCTRL_NONE;
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USART_InitStructure.Mode = USART_MODE_TX;
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// init uart
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USART_Init(USART2, &USART_InitStructure);
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// enable uart
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USART_Enable(USART2, ENABLE);
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}
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static int is_lr_sent = 0;
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int fputc(int ch, FILE* f)
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{
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if (ch == '\r')
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{
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is_lr_sent = 1;
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}
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else if (ch == '\n')
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{
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if (!is_lr_sent)
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{
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USART_SendData(LOG_USARTx, (uint8_t)'\r');
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/* Loop until the end of transmission */
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while (USART_GetFlagStatus(LOG_USARTx, USART_FLAG_TXC) == RESET)
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{
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}
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}
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is_lr_sent = 0;
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}
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else
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{
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is_lr_sent = 0;
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}
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USART_SendData(LOG_USARTx, (uint8_t)ch);
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/* Loop until the end of transmission */
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while (USART_GetFlagStatus(LOG_USARTx, USART_FLAG_TXC) == RESET)
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{
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}
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return ch;
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}
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#ifdef USE_FULL_ASSERT
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__WEAK void assert_failed(const uint8_t* expr, const uint8_t* file, uint32_t line)
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{
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log_error("assertion failed: `%s` at %s:%d", expr, file, line);
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while (1)
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{
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}
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}
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#endif // USE_FULL_ASSERT
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#endif // LOG_ENABLE
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#include "mcu_init.h"
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k_task_t task1;
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k_stack_t task1_stack[1024];
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k_task_t task2;
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k_stack_t task2_stack[1024];
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void task1_fun(void *arg)
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{
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int count = 0;
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while (1) {
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printf("###I am task1,count is %d \r\n",count++);
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tos_task_delay(1000);
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}
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}
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void task2_fun(void *arg)
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{
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int count = 0;
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while (1) {
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printf("***I am task2,count is %d \r\n",count++);
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tos_task_delay(2000);
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}
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}
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int main(void)
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{
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k_err_t err;
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board_init();
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printf(" Welcome to TencentOS Tiny!\r\n");
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tos_knl_init(); // TencentOS Tiny kernel initialize
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err = tos_task_create(&task1,
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"task1",
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task1_fun,
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NULL,
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3,
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task1_stack,
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1024,
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20);
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if(err != K_ERR_NONE)
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printf("TencentOS Create task1 fail! code : %d \r\n",err);
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err = tos_task_create(&task2,
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"task2",
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task2_fun,
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NULL,
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4,
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task2_stack,
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1024,
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20);
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if(err != K_ERR_NONE)
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printf("TencentOS Create task2 fail! code : %d \r\n",err);
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tos_knl_start(); // Start TencentOS Tiny
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}
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#include "mcu_init.h"
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void board_init(void)
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{
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log_init();
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}
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#ifdef USE_FULL_ASSERT
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/**
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* @brief Reports the name of the source file and the source line number
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* where the assert_param error has occurred.
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* @param file pointer to the source file name
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* @param line assert_param error line source number
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*/
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void assert_failed(const uint8_t* expr, const uint8_t* file, uint32_t line)
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{
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/* User can add his own implementation to report the file name and line number,
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ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
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/* Infinite loop */
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while (1)
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{
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}
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}
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#endif
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/**
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* @}
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*/
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/**
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* @}
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*/
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/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_it.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x_it.h"
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#include "tos_k.h"
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/** @addtogroup N32G45X_StdPeriph_Template
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern __IO uint32_t CurrDataCounterEnd;
|
||||
|
||||
/******************************************************************************/
|
||||
/* Cortex-M4 Processor Exceptions Handlers */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief This function handles NMI exception.
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Hard Fault exception.
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Hard Fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Memory Manage exception.
|
||||
*/
|
||||
void MemManage_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Memory Manage exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Bus Fault exception.
|
||||
*/
|
||||
void BusFault_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Bus Fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Usage Fault exception.
|
||||
*/
|
||||
void UsageFault_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Usage Fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles SVCall exception.
|
||||
*/
|
||||
void SVC_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Debug Monitor exception.
|
||||
*/
|
||||
void DebugMon_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles SysTick Handler.
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
if (tos_knl_is_running())
|
||||
{
|
||||
tos_knl_irq_enter();
|
||||
tos_tick_handler();
|
||||
tos_knl_irq_leave();
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/* N32G45X Peripherals Interrupt Handlers */
|
||||
/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
|
||||
/* available peripheral interrupt handler's name please refer to the startup */
|
||||
/* file (startup_n32g45x.s). */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief This function handles PPP interrupt request.
|
||||
*/
|
||||
/*void PPP_IRQHandler(void)
|
||||
{
|
||||
}*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,977 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj; *.o</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>TencentOS_Tiny</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>255</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<bEvRecOn>1</bEvRecOn>
|
||||
<bSchkAxf>0</bSchkAxf>
|
||||
<bTchkAxf>0</bTchkAxf>
|
||||
<nTsel>3</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMRTXEVENTFLAGS</Key>
|
||||
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGTARM</Key>
|
||||
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ARMDBGFLAGS</Key>
|
||||
<Name></Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>DLGUARM</Key>
|
||||
<Name></Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0N32G45x.FLM -FS08000000 -FL080000 -FP0($$Device:N32G457MEL7$Flash\N32G45x.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0N32G45x -FL080000 -FS08000000 -FP0($$Device:N32G457MEL7$Flash\N32G45x.FLM)</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>1</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>1</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
<bAutoGenD>0</bAutoGenD>
|
||||
<LntExFlags>0</LntExFlags>
|
||||
<pMisraName></pMisraName>
|
||||
<pszMrule></pszMrule>
|
||||
<pSingCmds></pSingCmds>
|
||||
<pMultCmds></pMultCmds>
|
||||
<pMisraNamep></pMisraNamep>
|
||||
<pszMrulep></pszMrulep>
|
||||
<pSingCmdsp></pSingCmdsp>
|
||||
<pMultCmdsp></pMultCmdsp>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>STARTUP</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>2</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\CMSIS\device\startup\startup_n32g45x.s</PathWithFileName>
|
||||
<FilenameWithoutPath>startup_n32g45x.s</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>CMSIS</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\CMSIS\device\system_n32g45x.c</PathWithFileName>
|
||||
<FilenameWithoutPath>system_n32g45x.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>FWLB</GroupName>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>3</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\misc.c</PathWithFileName>
|
||||
<FilenameWithoutPath>misc.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>4</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_adc.c</PathWithFileName>
|
||||
<FilenameWithoutPath>n32g45x_adc.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>5</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_bkp.c</PathWithFileName>
|
||||
<FilenameWithoutPath>n32g45x_bkp.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>6</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_can.c</PathWithFileName>
|
||||
<FilenameWithoutPath>n32g45x_can.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>7</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_crc.c</PathWithFileName>
|
||||
<FilenameWithoutPath>n32g45x_crc.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>8</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_dac.c</PathWithFileName>
|
||||
<FilenameWithoutPath>n32g45x_dac.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>9</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_dbg.c</PathWithFileName>
|
||||
<FilenameWithoutPath>n32g45x_dbg.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>10</FileNumber>
|
||||
<FileType>1</FileType>
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<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>2</RvdsVP>
|
||||
<RvdsMve>0</RvdsMve>
|
||||
<hadIRAM2>0</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<nSecure>0</nSecure>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x24000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x80000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x8000000</StartAddress>
|
||||
<Size>0x80000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x24000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>0</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>1</uC99>
|
||||
<uGnu>0</uGnu>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>1</v6Lang>
|
||||
<v6LangP>1</v6LangP>
|
||||
<vShortEn>1</vShortEn>
|
||||
<vShortWch>1</vShortWch>
|
||||
<v6Lto>0</v6Lto>
|
||||
<v6WtE>0</v6WtE>
|
||||
<v6Rtti>0</v6Rtti>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define>N32G45X, USE_STDPERIPH_DRIVER</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>..\..\BSP\Inc;..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\CMSIS\core;..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\CMSIS\device;..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\inc;..\..\..\..\arch\arm\arm-v7m\common\include;..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc;..\..\..\..\kernel\core\include;..\..\..\..\kernel\hal\include;..\..\TOS_CONFIG</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<uClangAs>0</uClangAs>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>1</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile></ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>STARTUP</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>startup_n32g45x.s</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\CMSIS\device\startup\startup_n32g45x.s</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>CMSIS</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>system_n32g45x.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\CMSIS\device\system_n32g45x.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>FWLB</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>misc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\misc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_adc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_adc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_bkp.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_bkp.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_can.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_can.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_crc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_crc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_dac.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_dac.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_dbg.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_dbg.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_dma.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_dma.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_dvp.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_dvp.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_exti.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_exti.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_flash.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_flash.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_gpio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_gpio.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_i2c.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_i2c.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_iwdg.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_iwdg.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_pwr.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_pwr.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_qspi.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_qspi.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_rcc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_rcc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_rtc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_rtc.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_sdio.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_sdio.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_spi.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_spi.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_tim.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_tim.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_usart.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_usart.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_wwdg.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_wwdg.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_xfmc.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\platform\vendor_bsp\nationz\Nationstech.N32G45x_Library.0.4.0\n32g45x_std_periph_driver\src\n32g45x_xfmc.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>USER</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\BSP\Src\main.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>n32g45x_it.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\BSP\Src\n32g45x_it.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>log.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\BSP\Src\log.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>mcu_init.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\BSP\Src\mcu_init.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>tos/arch</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>tos_cpu.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>port_c.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_c.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>port_s.S</FileName>
|
||||
<FileType>2</FileType>
|
||||
<FilePath>..\..\..\..\arch\arm\arm-v7m\cortex-m4\armcc\port_s.S</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>tos/kernel</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>tos_barrier.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_barrier.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_binary_heap.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_binary_heap.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_bitmap.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_bitmap.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_char_fifo.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_char_fifo.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_completion.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_completion.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_countdownlatch.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_countdownlatch.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_event.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_event.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_global.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_global.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_mail_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_mail_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_message_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_message_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_mmblk.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_mmblk.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_mmheap.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_mmheap.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_mutex.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_mutex.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_pend.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_pend.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_priority_mail_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_priority_mail_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_priority_message_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_priority_message_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_priority_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_priority_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_ring_queue.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_ring_queue.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_robin.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_robin.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_rwlock.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_rwlock.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_sched.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_sched.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_sem.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_sem.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_stopwatch.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_stopwatch.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_sys.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_sys.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_task.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_task.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_tick.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_tick.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_time.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_time.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>tos_timer.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\..\..\kernel\core\tos_timer.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis/>
|
||||
<components/>
|
||||
<files/>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
#ifndef _TOS_CONFIG_H_
|
||||
#define _TOS_CONFIG_H_
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
#define TOS_CFG_TASK_PRIO_MAX 10u
|
||||
|
||||
#define TOS_CFG_ROUND_ROBIN_EN 1u
|
||||
|
||||
#define TOS_CFG_OBJECT_VERIFY_EN 0u
|
||||
|
||||
#define TOS_CFG_TASK_DYNAMIC_CREATE_EN 0u
|
||||
|
||||
#define TOS_CFG_EVENT_EN 1u
|
||||
|
||||
#define TOS_CFG_MMBLK_EN 1u
|
||||
|
||||
#define TOS_CFG_MMHEAP_EN 1u
|
||||
|
||||
#define TOS_CFG_MMHEAP_DEFAULT_POOL_SIZE 0x100
|
||||
|
||||
#define TOS_CFG_MUTEX_EN 1u
|
||||
|
||||
#define TOS_CFG_TIMER_EN 1u
|
||||
|
||||
#define TOS_CFG_SEM_EN 1u
|
||||
|
||||
#define TOS_CFG_IDLE_TASK_STK_SIZE 128u
|
||||
|
||||
#define TOS_CFG_CPU_TICK_PER_SECOND 1000u
|
||||
|
||||
#define TOS_CFG_CPU_CLOCK (SystemCoreClock)
|
||||
|
||||
#define TOS_CFG_TIMER_AS_PROC 1u
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables.h
|
||||
* Description: Extern declaration for common tables
|
||||
*
|
||||
* $Date: 27. January 2017
|
||||
* $Revision: V.1.5.1
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H
|
||||
#define _ARM_COMMON_TABLES_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
extern const uint16_t armBitRevTable[1024];
|
||||
extern const q15_t armRecipTableQ15[64];
|
||||
extern const q31_t armRecipTableQ31[64];
|
||||
extern const float32_t twiddleCoef_16[32];
|
||||
extern const float32_t twiddleCoef_32[64];
|
||||
extern const float32_t twiddleCoef_64[128];
|
||||
extern const float32_t twiddleCoef_128[256];
|
||||
extern const float32_t twiddleCoef_256[512];
|
||||
extern const float32_t twiddleCoef_512[1024];
|
||||
extern const float32_t twiddleCoef_1024[2048];
|
||||
extern const float32_t twiddleCoef_2048[4096];
|
||||
extern const float32_t twiddleCoef_4096[8192];
|
||||
#define twiddleCoef twiddleCoef_4096
|
||||
extern const q31_t twiddleCoef_16_q31[24];
|
||||
extern const q31_t twiddleCoef_32_q31[48];
|
||||
extern const q31_t twiddleCoef_64_q31[96];
|
||||
extern const q31_t twiddleCoef_128_q31[192];
|
||||
extern const q31_t twiddleCoef_256_q31[384];
|
||||
extern const q31_t twiddleCoef_512_q31[768];
|
||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
||||
extern const q15_t twiddleCoef_16_q15[24];
|
||||
extern const q15_t twiddleCoef_32_q15[48];
|
||||
extern const q15_t twiddleCoef_64_q15[96];
|
||||
extern const q15_t twiddleCoef_128_q15[192];
|
||||
extern const q15_t twiddleCoef_256_q15[384];
|
||||
extern const q15_t twiddleCoef_512_q15[768];
|
||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
||||
extern const float32_t twiddleCoef_rfft_32[32];
|
||||
extern const float32_t twiddleCoef_rfft_64[64];
|
||||
extern const float32_t twiddleCoef_rfft_128[128];
|
||||
extern const float32_t twiddleCoef_rfft_256[256];
|
||||
extern const float32_t twiddleCoef_rfft_512[512];
|
||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
||||
|
||||
/* floating-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
|
||||
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
|
||||
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
|
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
|
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
|
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
|
||||
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
|
||||
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
|
||||
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
|
||||
|
||||
/* fixed-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
||||
|
||||
/* Tables for Fast Math Sine and Cosine */
|
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs.h
|
||||
* Description: Constant structs that are initialized for user convenience.
|
||||
* For example, some can be given as arguments to the arm_cfft_f32() function.
|
||||
*
|
||||
* $Date: 27. January 2017
|
||||
* $Revision: V.1.5.1
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H
|
||||
#define _ARM_CONST_STRUCTS_H
|
||||
|
||||
#include "arm_math.h"
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,865 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler control architecture macros */
|
||||
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
|
||||
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||
|
||||
|
||||
/* CMSIS compiler specific defines */
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static __inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE static __forceinline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __declspec(noreturn)
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __enable_irq(); */
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#else
|
||||
(void)fpscr;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() do {\
|
||||
__schedule_barrier();\
|
||||
__isb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() do {\
|
||||
__schedule_barrier();\
|
||||
__dsb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() do {\
|
||||
__schedule_barrier();\
|
||||
__dmb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,266 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,935 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_iccarm.h
|
||||
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
|
||||
* @version V5.0.7
|
||||
* @date 19. June 2018
|
||||
******************************************************************************/
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2017-2018 IAR Systems
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License")
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
|
||||
#ifndef __CMSIS_ICCARM_H__
|
||||
#define __CMSIS_ICCARM_H__
|
||||
|
||||
#ifndef __ICCARM__
|
||||
#error This file should only be compiled by ICCARM
|
||||
#endif
|
||||
|
||||
#pragma system_include
|
||||
|
||||
#define __IAR_FT _Pragma("inline=forced") __intrinsic
|
||||
|
||||
#if (__VER__ >= 8000000)
|
||||
#define __ICCARM_V8 1
|
||||
#else
|
||||
#define __ICCARM_V8 0
|
||||
#endif
|
||||
|
||||
#ifndef __ALIGNED
|
||||
#if __ICCARM_V8
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#elif (__VER__ >= 7080000)
|
||||
/* Needs IAR language extensions */
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#else
|
||||
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Define compiler macros for CPU architecture, used in CMSIS 5.
|
||||
*/
|
||||
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
|
||||
/* Macros already defined */
|
||||
#else
|
||||
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#elif defined(__ARM8M_BASELINE__)
|
||||
#define __ARM_ARCH_8M_BASE__ 1
|
||||
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
|
||||
#if __ARM_ARCH == 6
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#elif __ARM_ARCH == 7
|
||||
#if __ARM_FEATURE_DSP
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#else
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
#endif /* __ARM_ARCH */
|
||||
#endif /* __ARM_ARCH_PROFILE == 'M' */
|
||||
#endif
|
||||
|
||||
/* Alternativ core deduction for older ICCARM's */
|
||||
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
|
||||
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
|
||||
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
|
||||
#define __ARM_ARCH_8M_BASE__ 1
|
||||
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
|
||||
#define __ARM_ARCH_8M_MAIN__ 1
|
||||
#else
|
||||
#error "Unknown target."
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
|
||||
#define __IAR_M0_FAMILY 1
|
||||
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
|
||||
#define __IAR_M0_FAMILY 1
|
||||
#else
|
||||
#define __IAR_M0_FAMILY 0
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __NO_RETURN
|
||||
#if __ICCARM_V8
|
||||
#define __NO_RETURN __attribute__((__noreturn__))
|
||||
#else
|
||||
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED __packed
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_STRUCT
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_UNION
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
|
||||
#ifndef __FORCEINLINE
|
||||
#define __FORCEINLINE _Pragma("inline=forced")
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint16_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
|
||||
{
|
||||
*(__packed uint16_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint32_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
|
||||
{
|
||||
*(__packed uint32_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__packed struct __iar_u32 { uint32_t v; };
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
|
||||
#endif
|
||||
|
||||
#ifndef __USED
|
||||
#if __ICCARM_V8
|
||||
#define __USED __attribute__((used))
|
||||
#else
|
||||
#define __USED _Pragma("__root")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#if __ICCARM_V8
|
||||
#define __WEAK __attribute__((weak))
|
||||
#else
|
||||
#define __WEAK _Pragma("__weak")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __ICCARM_INTRINSICS_VERSION__
|
||||
#define __ICCARM_INTRINSICS_VERSION__ 0
|
||||
#endif
|
||||
|
||||
#if __ICCARM_INTRINSICS_VERSION__ == 2
|
||||
|
||||
#if defined(__CLZ)
|
||||
#undef __CLZ
|
||||
#endif
|
||||
#if defined(__REVSH)
|
||||
#undef __REVSH
|
||||
#endif
|
||||
#if defined(__RBIT)
|
||||
#undef __RBIT
|
||||
#endif
|
||||
#if defined(__SSAT)
|
||||
#undef __SSAT
|
||||
#endif
|
||||
#if defined(__USAT)
|
||||
#undef __USAT
|
||||
#endif
|
||||
|
||||
#include "iccarm_builtin.h"
|
||||
|
||||
#define __disable_fault_irq __iar_builtin_disable_fiq
|
||||
#define __disable_irq __iar_builtin_disable_interrupt
|
||||
#define __enable_fault_irq __iar_builtin_enable_fiq
|
||||
#define __enable_irq __iar_builtin_enable_interrupt
|
||||
#define __arm_rsr __iar_builtin_rsr
|
||||
#define __arm_wsr __iar_builtin_wsr
|
||||
|
||||
|
||||
#define __get_APSR() (__arm_rsr("APSR"))
|
||||
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
|
||||
#define __get_CONTROL() (__arm_rsr("CONTROL"))
|
||||
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
|
||||
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
#define __get_FPSCR() (__arm_rsr("FPSCR"))
|
||||
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
|
||||
#else
|
||||
#define __get_FPSCR() ( 0 )
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#define __get_IPSR() (__arm_rsr("IPSR"))
|
||||
#define __get_MSP() (__arm_rsr("MSP"))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __get_MSPLIM() (0U)
|
||||
#else
|
||||
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
|
||||
#endif
|
||||
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
|
||||
#define __get_PSP() (__arm_rsr("PSP"))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __get_PSPLIM() (0U)
|
||||
#else
|
||||
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
|
||||
#endif
|
||||
|
||||
#define __get_xPSR() (__arm_rsr("xPSR"))
|
||||
|
||||
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
|
||||
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
|
||||
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
|
||||
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
|
||||
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __set_MSPLIM(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
|
||||
#endif
|
||||
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
|
||||
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __set_PSPLIM(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
|
||||
#endif
|
||||
|
||||
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
|
||||
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
|
||||
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
|
||||
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
|
||||
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
|
||||
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
|
||||
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
|
||||
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
|
||||
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
|
||||
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
|
||||
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
|
||||
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
|
||||
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
|
||||
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __TZ_get_PSPLIM_NS() (0U)
|
||||
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
|
||||
#else
|
||||
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
|
||||
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
|
||||
#endif
|
||||
|
||||
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
|
||||
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
|
||||
|
||||
#define __NOP __iar_builtin_no_operation
|
||||
|
||||
#define __CLZ __iar_builtin_CLZ
|
||||
#define __CLREX __iar_builtin_CLREX
|
||||
|
||||
#define __DMB __iar_builtin_DMB
|
||||
#define __DSB __iar_builtin_DSB
|
||||
#define __ISB __iar_builtin_ISB
|
||||
|
||||
#define __LDREXB __iar_builtin_LDREXB
|
||||
#define __LDREXH __iar_builtin_LDREXH
|
||||
#define __LDREXW __iar_builtin_LDREX
|
||||
|
||||
#define __RBIT __iar_builtin_RBIT
|
||||
#define __REV __iar_builtin_REV
|
||||
#define __REV16 __iar_builtin_REV16
|
||||
|
||||
__IAR_FT int16_t __REVSH(int16_t val)
|
||||
{
|
||||
return (int16_t) __iar_builtin_REVSH(val);
|
||||
}
|
||||
|
||||
#define __ROR __iar_builtin_ROR
|
||||
#define __RRX __iar_builtin_RRX
|
||||
|
||||
#define __SEV __iar_builtin_SEV
|
||||
|
||||
#if !__IAR_M0_FAMILY
|
||||
#define __SSAT __iar_builtin_SSAT
|
||||
#endif
|
||||
|
||||
#define __STREXB __iar_builtin_STREXB
|
||||
#define __STREXH __iar_builtin_STREXH
|
||||
#define __STREXW __iar_builtin_STREX
|
||||
|
||||
#if !__IAR_M0_FAMILY
|
||||
#define __USAT __iar_builtin_USAT
|
||||
#endif
|
||||
|
||||
#define __WFE __iar_builtin_WFE
|
||||
#define __WFI __iar_builtin_WFI
|
||||
|
||||
#if __ARM_MEDIA__
|
||||
#define __SADD8 __iar_builtin_SADD8
|
||||
#define __QADD8 __iar_builtin_QADD8
|
||||
#define __SHADD8 __iar_builtin_SHADD8
|
||||
#define __UADD8 __iar_builtin_UADD8
|
||||
#define __UQADD8 __iar_builtin_UQADD8
|
||||
#define __UHADD8 __iar_builtin_UHADD8
|
||||
#define __SSUB8 __iar_builtin_SSUB8
|
||||
#define __QSUB8 __iar_builtin_QSUB8
|
||||
#define __SHSUB8 __iar_builtin_SHSUB8
|
||||
#define __USUB8 __iar_builtin_USUB8
|
||||
#define __UQSUB8 __iar_builtin_UQSUB8
|
||||
#define __UHSUB8 __iar_builtin_UHSUB8
|
||||
#define __SADD16 __iar_builtin_SADD16
|
||||
#define __QADD16 __iar_builtin_QADD16
|
||||
#define __SHADD16 __iar_builtin_SHADD16
|
||||
#define __UADD16 __iar_builtin_UADD16
|
||||
#define __UQADD16 __iar_builtin_UQADD16
|
||||
#define __UHADD16 __iar_builtin_UHADD16
|
||||
#define __SSUB16 __iar_builtin_SSUB16
|
||||
#define __QSUB16 __iar_builtin_QSUB16
|
||||
#define __SHSUB16 __iar_builtin_SHSUB16
|
||||
#define __USUB16 __iar_builtin_USUB16
|
||||
#define __UQSUB16 __iar_builtin_UQSUB16
|
||||
#define __UHSUB16 __iar_builtin_UHSUB16
|
||||
#define __SASX __iar_builtin_SASX
|
||||
#define __QASX __iar_builtin_QASX
|
||||
#define __SHASX __iar_builtin_SHASX
|
||||
#define __UASX __iar_builtin_UASX
|
||||
#define __UQASX __iar_builtin_UQASX
|
||||
#define __UHASX __iar_builtin_UHASX
|
||||
#define __SSAX __iar_builtin_SSAX
|
||||
#define __QSAX __iar_builtin_QSAX
|
||||
#define __SHSAX __iar_builtin_SHSAX
|
||||
#define __USAX __iar_builtin_USAX
|
||||
#define __UQSAX __iar_builtin_UQSAX
|
||||
#define __UHSAX __iar_builtin_UHSAX
|
||||
#define __USAD8 __iar_builtin_USAD8
|
||||
#define __USADA8 __iar_builtin_USADA8
|
||||
#define __SSAT16 __iar_builtin_SSAT16
|
||||
#define __USAT16 __iar_builtin_USAT16
|
||||
#define __UXTB16 __iar_builtin_UXTB16
|
||||
#define __UXTAB16 __iar_builtin_UXTAB16
|
||||
#define __SXTB16 __iar_builtin_SXTB16
|
||||
#define __SXTAB16 __iar_builtin_SXTAB16
|
||||
#define __SMUAD __iar_builtin_SMUAD
|
||||
#define __SMUADX __iar_builtin_SMUADX
|
||||
#define __SMMLA __iar_builtin_SMMLA
|
||||
#define __SMLAD __iar_builtin_SMLAD
|
||||
#define __SMLADX __iar_builtin_SMLADX
|
||||
#define __SMLALD __iar_builtin_SMLALD
|
||||
#define __SMLALDX __iar_builtin_SMLALDX
|
||||
#define __SMUSD __iar_builtin_SMUSD
|
||||
#define __SMUSDX __iar_builtin_SMUSDX
|
||||
#define __SMLSD __iar_builtin_SMLSD
|
||||
#define __SMLSDX __iar_builtin_SMLSDX
|
||||
#define __SMLSLD __iar_builtin_SMLSLD
|
||||
#define __SMLSLDX __iar_builtin_SMLSLDX
|
||||
#define __SEL __iar_builtin_SEL
|
||||
#define __QADD __iar_builtin_QADD
|
||||
#define __QSUB __iar_builtin_QSUB
|
||||
#define __PKHBT __iar_builtin_PKHBT
|
||||
#define __PKHTB __iar_builtin_PKHTB
|
||||
#endif
|
||||
|
||||
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||
#define __CLZ __cmsis_iar_clz_not_active
|
||||
#define __SSAT __cmsis_iar_ssat_not_active
|
||||
#define __USAT __cmsis_iar_usat_not_active
|
||||
#define __RBIT __cmsis_iar_rbit_not_active
|
||||
#define __get_APSR __cmsis_iar_get_APSR_not_active
|
||||
#endif
|
||||
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
|
||||
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
|
||||
#endif
|
||||
|
||||
#ifdef __INTRINSICS_INCLUDED
|
||||
#error intrinsics.h is already included previously!
|
||||
#endif
|
||||
|
||||
#include <intrinsics.h>
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
|
||||
#undef __CLZ
|
||||
#undef __SSAT
|
||||
#undef __USAT
|
||||
#undef __RBIT
|
||||
#undef __get_APSR
|
||||
|
||||
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
|
||||
{
|
||||
if (data == 0U) { return 32U; }
|
||||
|
||||
uint32_t count = 0U;
|
||||
uint32_t mask = 0x80000000U;
|
||||
|
||||
while ((data & mask) == 0U)
|
||||
{
|
||||
count += 1U;
|
||||
mask = mask >> 1U;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
|
||||
{
|
||||
uint8_t sc = 31U;
|
||||
uint32_t r = v;
|
||||
for (v >>= 1U; v; v >>= 1U)
|
||||
{
|
||||
r <<= 1U;
|
||||
r |= v & 1U;
|
||||
sc--;
|
||||
}
|
||||
return (r << sc);
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm("MRS %0,APSR" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#undef __get_FPSCR
|
||||
#undef __set_FPSCR
|
||||
#define __get_FPSCR() (0)
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#pragma diag_suppress=Pe940
|
||||
#pragma diag_suppress=Pe177
|
||||
|
||||
#define __enable_irq __enable_interrupt
|
||||
#define __disable_irq __disable_interrupt
|
||||
#define __NOP __no_operation
|
||||
|
||||
#define __get_xPSR __get_PSR
|
||||
|
||||
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
|
||||
|
||||
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
|
||||
{
|
||||
return __LDREX((unsigned long *)ptr);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
|
||||
{
|
||||
return __STREX(value, (unsigned long *)ptr);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
__IAR_FT uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
|
||||
return(result);
|
||||
}
|
||||
|
||||
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
|
||||
}
|
||||
|
||||
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
|
||||
}
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
__IAR_FT uint32_t __get_MSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_MSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __get_PSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_PSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_SP_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,SP_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR SP_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
|
||||
#endif
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
|
||||
{
|
||||
uint32_t res;
|
||||
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
|
||||
{
|
||||
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
|
||||
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
|
||||
|
||||
#if __IAR_M0_FAMILY
|
||||
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
|
||||
|
||||
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
|
||||
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint8_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return ((uint16_t)res);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
|
||||
#undef __IAR_FT
|
||||
#undef __IAR_M0_FAMILY
|
||||
#undef __ICCARM_V8
|
||||
|
||||
#pragma diag_default=Pe940
|
||||
#pragma diag_default=Pe177
|
||||
|
||||
#endif /* __CMSIS_ICCARM_H__ */
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.2
|
||||
* @date 19. April 2017
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,270 @@
|
|||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.0.4
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if non-shareable) or 010b (if shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DSB();
|
||||
__ISB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,89 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_conf.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_CONF_H__
|
||||
#define __N32G45X_CONF_H__
|
||||
|
||||
/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
|
||||
|
||||
#include "n32g45x_adc.h"
|
||||
#include "n32g45x_bkp.h"
|
||||
#include "n32g45x_can.h"
|
||||
#include "n32g45x_comp.h"
|
||||
#include "n32g45x_crc.h"
|
||||
#include "n32g45x_dac.h"
|
||||
#include "n32g45x_dbg.h"
|
||||
#include "n32g45x_dma.h"
|
||||
#include "n32g45x_dvp.h"
|
||||
#include "n32g45x_eth.h"
|
||||
#include "n32g45x_exti.h"
|
||||
#include "n32g45x_flash.h"
|
||||
#include "n32g45x_gpio.h"
|
||||
#include "n32g45x_i2c.h"
|
||||
#include "n32g45x_iwdg.h"
|
||||
#include "n32g45x_opamp.h"
|
||||
#include "n32g45x_pwr.h"
|
||||
#include "n32g45x_qspi.h"
|
||||
#include "n32g45x_rcc.h"
|
||||
#include "n32g45x_rtc.h"
|
||||
#include "n32g45x_sdio.h"
|
||||
#include "n32g45x_spi.h"
|
||||
#include "n32g45x_tim.h"
|
||||
#include "n32g45x_usart.h"
|
||||
#include "n32g45x_wwdg.h"
|
||||
#include "n32g45x_xfmc.h"
|
||||
#include "n32g45x_tsc.h"
|
||||
|
||||
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
|
||||
|
||||
/* Uncomment the line below to expanse the "assert_param" macro in the
|
||||
Standard Peripheral Library drivers code */
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
||||
#ifdef USE_FULL_ASSERT
|
||||
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr If expr is false, it calls assert_failed function which reports
|
||||
* the name of the source file and the source line number of the call
|
||||
* that failed. If expr is true, it returns no value.
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((const uint8_t*)#expr, (const uint8_t*)__FILE__, __LINE__))
|
||||
|
||||
void assert_failed(const uint8_t* expr, const uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#endif /* __N32G45X_CONF_H__ */
|
||||
|
|
@ -0,0 +1,433 @@
|
|||
; ****************************************************************************
|
||||
; Copyright (c) 2019, Nations Technologies Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
; ****************************************************************************
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
;
|
||||
; - Redistributions of source code must retain the above copyright notice,
|
||||
; this list of conditions and the disclaimer below.
|
||||
;
|
||||
; Nations' name may not be used to endorse or promote products derived from
|
||||
; this software without specific prior written permission.
|
||||
;
|
||||
; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
; ****************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00001500
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000300
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_WKUP_IRQHandler ; RTC_WKUP
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
|
||||
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
|
||||
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break
|
||||
DCD TIM1_UP_IRQHandler ; TIM1 Update
|
||||
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
|
||||
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
|
||||
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
|
||||
DCD TIM8_BRK_IRQHandler ; TIM8 Break
|
||||
DCD TIM8_UP_IRQHandler ; TIM8 Update
|
||||
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||
DCD ADC3_4_IRQHandler ; ADC3 & ADC4
|
||||
DCD XFMC_IRQHandler ; XFMC
|
||||
DCD SDIO_IRQHandler ; SDIO
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_IRQHandler ; TIM6
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
|
||||
DCD ETH_IRQHandler ; Ethernet global interrupt
|
||||
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line interrupt
|
||||
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
|
||||
DCD QSPI_IRQHandler ; QSPI
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel6
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel7
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||
DCD I2C4_EV_IRQHandler ; I2C4 event
|
||||
DCD I2C4_ER_IRQHandler ; I2C4 error
|
||||
DCD UART6_IRQHandler ; UART6
|
||||
DCD UART7_IRQHandler ; UART7
|
||||
DCD DMA1_Channel8_IRQHandler ; DMA1 Channel8
|
||||
DCD DMA2_Channel8_IRQHandler ; DMA2 Channel8
|
||||
DCD DVP_IRQHandler ; DVP
|
||||
DCD SAC_IRQHandler ; SAC
|
||||
DCD MMU_IRQHandler ; MMU
|
||||
DCD TSC_IRQHandler ; TSC
|
||||
DCD COMP_1_2_3_IRQHandler ; COMP1 & COMP2 & COMP3
|
||||
DCD COMP_4_5_6_IRQHandler ; COMP4 & COMP5 & COMP6
|
||||
DCD COMP7_IRQHandler ; COMP7
|
||||
DCD RSRAM_IRQHandler ; R-SRAM parity error interrupt
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT __main
|
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTCAlarm_IRQHandler [WEAK]
|
||||
EXPORT USBWakeUp_IRQHandler [WEAK]
|
||||
EXPORT TIM8_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM8_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||
EXPORT ADC3_4_IRQHandler [WEAK]
|
||||
EXPORT XFMC_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT ETH_WKUP_IRQHandler [WEAK]
|
||||
EXPORT CAN2_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN2_SCE_IRQHandler [WEAK]
|
||||
EXPORT QSPI_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel7_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C4_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C4_ER_IRQHandler [WEAK]
|
||||
EXPORT UART6_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel8_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel8_IRQHandler [WEAK]
|
||||
EXPORT DVP_IRQHandler [WEAK]
|
||||
EXPORT SAC_IRQHandler [WEAK]
|
||||
EXPORT MMU_IRQHandler [WEAK]
|
||||
EXPORT TSC_IRQHandler [WEAK]
|
||||
EXPORT COMP_1_2_3_IRQHandler [WEAK]
|
||||
EXPORT COMP_4_5_6_IRQHandler [WEAK]
|
||||
EXPORT COMP7_IRQHandler [WEAK]
|
||||
EXPORT RSRAM_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_IRQHandler
|
||||
TAMPER_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_2_IRQHandler
|
||||
USB_HP_CAN1_TX_IRQHandler
|
||||
USB_LP_CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_SCE_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTCAlarm_IRQHandler
|
||||
USBWakeUp_IRQHandler
|
||||
TIM8_BRK_IRQHandler
|
||||
TIM8_UP_IRQHandler
|
||||
TIM8_TRG_COM_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
ADC3_4_IRQHandler
|
||||
XFMC_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
TIM6_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
DMA2_Channel1_IRQHandler
|
||||
DMA2_Channel2_IRQHandler
|
||||
DMA2_Channel3_IRQHandler
|
||||
DMA2_Channel4_IRQHandler
|
||||
DMA2_Channel5_IRQHandler
|
||||
ETH_IRQHandler
|
||||
ETH_WKUP_IRQHandler
|
||||
CAN2_TX_IRQHandler
|
||||
CAN2_RX0_IRQHandler
|
||||
CAN2_RX1_IRQHandler
|
||||
CAN2_SCE_IRQHandler
|
||||
QSPI_IRQHandler
|
||||
DMA2_Channel6_IRQHandler
|
||||
DMA2_Channel7_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
I2C4_EV_IRQHandler
|
||||
I2C4_ER_IRQHandler
|
||||
UART6_IRQHandler
|
||||
UART7_IRQHandler
|
||||
DMA1_Channel8_IRQHandler
|
||||
DMA2_Channel8_IRQHandler
|
||||
DVP_IRQHandler
|
||||
SAC_IRQHandler
|
||||
MMU_IRQHandler
|
||||
TSC_IRQHandler
|
||||
COMP_1_2_3_IRQHandler
|
||||
COMP_4_5_6_IRQHandler
|
||||
COMP7_IRQHandler
|
||||
RSRAM_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,424 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file system_n32g45x.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x.h"
|
||||
|
||||
/* Uncomment the line corresponding to the desired System clock (SYSCLK)
|
||||
frequency (after reset the HSI is used as SYSCLK source)
|
||||
|
||||
IMPORTANT NOTE:
|
||||
==============
|
||||
1. After each device reset the HSI is used as System clock source.
|
||||
|
||||
2. Please make sure that the selected System clock doesn't exceed your
|
||||
device's maximum frequency.
|
||||
|
||||
3. If none of the define below is enabled, the HSI is used as System clock
|
||||
source.
|
||||
|
||||
4. The System clock configuration functions provided within this file assume
|
||||
that:
|
||||
- For Low, Medium and High density Value line devices an external 8MHz
|
||||
crystal is used to drive the System clock.
|
||||
- For Low, Medium and High density devices an external 8MHz crystal is
|
||||
used to drive the System clock.
|
||||
- For Connectivity line devices an external 25MHz crystal is used to
|
||||
drive the System clock. If you are using different crystal you have to adapt
|
||||
those functions accordingly.
|
||||
*/
|
||||
|
||||
#define SYSCLK_USE_HSI 0
|
||||
#define SYSCLK_USE_HSE 1
|
||||
#define SYSCLK_USE_HSI_PLL 2
|
||||
#define SYSCLK_USE_HSE_PLL 3
|
||||
|
||||
#ifndef SYSCLK_FREQ
|
||||
#define SYSCLK_FREQ 144000000
|
||||
#endif
|
||||
|
||||
#ifndef SYSCLK_SRC
|
||||
#define SYSCLK_SRC SYSCLK_USE_HSE_PLL
|
||||
#endif
|
||||
|
||||
#if SYSCLK_SRC == SYSCLK_USE_HSI
|
||||
|
||||
#if SYSCLK_FREQ != HSI_VALUE
|
||||
#error SYSCL_FREQ must be set to HSI_VALUE
|
||||
#endif
|
||||
|
||||
#elif SYSCLK_SRC == SYSCLK_USE_HSE
|
||||
|
||||
#ifndef HSE_VALUE
|
||||
#error HSE_VALUE must be defined!
|
||||
#endif
|
||||
|
||||
#if SYSCLK_FREQ != HSE_VALUE
|
||||
#error SYSCL_FREQ must be set to HSE_VALUE
|
||||
#endif
|
||||
|
||||
#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL
|
||||
|
||||
#if (SYSCLK_FREQ % (HSI_VALUE / 2) == 0) && (SYSCLK_FREQ / (HSI_VALUE / 2) >= 2) \
|
||||
&& (SYSCLK_FREQ / (HSI_VALUE / 2) <= 32)
|
||||
|
||||
#define PLLSRC_DIV 2
|
||||
#define PLL_MUL (SYSCLK_FREQ / (HSI_VALUE / 2))
|
||||
|
||||
#else
|
||||
#error Cannot make a PLL multiply factor to SYSCLK_FREQ.
|
||||
#endif
|
||||
|
||||
#elif SYSCLK_SRC == SYSCLK_USE_HSE_PLL
|
||||
|
||||
#ifndef HSE_VALUE
|
||||
#error HSE_VALUE must be defined!
|
||||
#endif
|
||||
|
||||
#if ((SYSCLK_FREQ % (HSE_VALUE / 2)) == 0) && (SYSCLK_FREQ / (HSE_VALUE / 2) >= 2) \
|
||||
&& (SYSCLK_FREQ / (HSE_VALUE / 2) <= 32)
|
||||
|
||||
#define PLLSRC_DIV 2
|
||||
#define PLL_MUL (SYSCLK_FREQ / (HSE_VALUE / 2))
|
||||
|
||||
#elif (SYSCLK_FREQ % HSE_VALUE == 0) && (SYSCLK_FREQ / HSE_VALUE >= 2) && (SYSCLK_FREQ / HSE_VALUE <= 32)
|
||||
|
||||
#define PLLSRC_DIV 1
|
||||
#define PLL_MUL (SYSCLK_FREQ / HSE_VALUE)
|
||||
|
||||
#else
|
||||
#error Cannot make a PLL multiply factor to SYSCLK_FREQ.
|
||||
#endif
|
||||
|
||||
#else
|
||||
#error wrong value for SYSCLK_SRC
|
||||
#endif
|
||||
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */
|
||||
|
||||
/*******************************************************************************
|
||||
* Clock Definitions
|
||||
*******************************************************************************/
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
static void SetSysClock(void);
|
||||
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
static void SystemInit_ExtMemCtl(void);
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the Embedded Flash Interface, the PLL and update the
|
||||
* SystemCoreClock variable.
|
||||
* @note This function should be used only after reset.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings
|
||||
* ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
|
||||
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
|
||||
/* Set HSIEN bit */
|
||||
RCC->CTRL |= (uint32_t)0x00000001;
|
||||
|
||||
/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
|
||||
RCC->CFG &= (uint32_t)0xF8FFC000;
|
||||
|
||||
/* Reset HSEON, CLKSSEN and PLLEN bits */
|
||||
RCC->CTRL &= (uint32_t)0xFEF6FFFF;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CTRL &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRES/OTGFSPRE bits */
|
||||
RCC->CFG &= (uint32_t)0xF700FFFF;
|
||||
|
||||
/* Reset CFG2 register */
|
||||
RCC->CFG2 = 0x00000000;
|
||||
|
||||
/* Reset CFG3 register */
|
||||
RCC->CFG3 = 0x00000000;
|
||||
|
||||
/* Disable all interrupts and clear pending bits */
|
||||
RCC->CLKINT = 0x009F0000;
|
||||
|
||||
/* Enable ex mode */
|
||||
RCC->APB1PCLKEN |= RCC_APB1PCLKEN_PWREN;
|
||||
PWR->CTRL3 |= 0x00000001;
|
||||
RCC->APB1PCLKEN &= (uint32_t)(~RCC_APB1PCLKEN_PWREN);
|
||||
|
||||
/* Enable ICACHE */
|
||||
// FLASH->ACR |= 0x00000080;
|
||||
|
||||
/* Disable Prefetch Buffer */
|
||||
FLASH->ACR &= (uint32_t)(~0x00000010);
|
||||
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
SystemInit_ExtMemCtl();
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
/* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
|
||||
/* Configure the Flash Latency cycles and enable prefetch buffer */
|
||||
SetSysClock();
|
||||
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or
|
||||
* configure other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any
|
||||
* configuration based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the
|
||||
* HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the
|
||||
* HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the
|
||||
* HSE_VALUE(**) or HSI_VALUE(*) multiplied by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in n32g45x.h file (default value
|
||||
* 8 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in N32G45X.h file (default value
|
||||
* 8 MHz or 25 MHz, depedning on the product used), user has to
|
||||
* ensure that HSE_VALUE is same as the real frequency of the crystal used.
|
||||
* Otherwise, this function may have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using
|
||||
* fractional value for HSE crystal.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp = 0, pllmull = 0, pllsource = 0;
|
||||
|
||||
/* Get SYSCLK source
|
||||
* -------------------------------------------------------*/
|
||||
tmp = RCC->CFG & RCC_CFG_SCLKSTS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00: /* HSI used as system clock */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04: /* HSE used as system clock */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08: /* PLL used as system clock */
|
||||
|
||||
/* Get PLL clock source and multiplication factor
|
||||
* ----------------------*/
|
||||
pllmull = RCC->CFG & RCC_CFG_PLLMULFCT;
|
||||
pllsource = RCC->CFG & RCC_CFG_PLLSRC;
|
||||
|
||||
if ((pllmull & RCC_CFG_PLLMULFCT_4) == 0)
|
||||
{
|
||||
pllmull = (pllmull >> 18) + 2; // PLLMUL[4]=0
|
||||
}
|
||||
else
|
||||
{
|
||||
pllmull = ((pllmull >> 18) - 496) + 1; // PLLMUL[4]=1
|
||||
}
|
||||
|
||||
if (pllsource == 0x00)
|
||||
{
|
||||
/* HSI oscillator clock divided by 2 selected as PLL clock entry */
|
||||
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* HSE selected as PLL clock entry */
|
||||
if ((RCC->CFG & RCC_CFG_PLLHSEPRES) != (uint32_t)RESET)
|
||||
{ /* HSE oscillator clock divided by 2 */
|
||||
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
|
||||
}
|
||||
else
|
||||
{
|
||||
SystemCoreClock = HSE_VALUE * pllmull;
|
||||
}
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Compute HCLK clock frequency ----------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFG & RCC_CFG_AHBPRES) >> 4)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1
|
||||
* prescalers.
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
uint32_t rcc_cfgr = 0;
|
||||
bool HSEStatus = 0;
|
||||
uint32_t StartUpCounter = 0;
|
||||
|
||||
#if SYSCLK_SRC == SYSCLK_USE_HSE || SYSCLK_SRC == SYSCLK_USE_HSE_PLL
|
||||
|
||||
/* Enable HSE */
|
||||
RCC->CTRL |= ((uint32_t)RCC_CTRL_HSEEN);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTRL & RCC_CTRL_HSERDF;
|
||||
StartUpCounter++;
|
||||
} while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
HSEStatus = ((RCC->CTRL & RCC_CTRL_HSERDF) != RESET);
|
||||
if (!HSEStatus)
|
||||
{
|
||||
/* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Flash wait state
|
||||
0: HCLK <= 32M
|
||||
1: HCLK <= 64M
|
||||
2: HCLK <= 96M
|
||||
3: HCLK <= 128M
|
||||
4: HCLK <= 144M
|
||||
*/
|
||||
FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_AC_LATENCY);
|
||||
FLASH->ACR |= (uint32_t)((SYSCLK_FREQ - 1) / 32000000);
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFG |= (uint32_t)RCC_CFG_AHBPRES_DIV1;
|
||||
|
||||
/* PCLK2 max 72M */
|
||||
if (SYSCLK_FREQ > 72000000)
|
||||
{
|
||||
RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV2;
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->CFG |= (uint32_t)RCC_CFG_APB2PRES_DIV1;
|
||||
}
|
||||
|
||||
/* PCLK1 max 36M */
|
||||
if (SYSCLK_FREQ > 72000000)
|
||||
{
|
||||
RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV4;
|
||||
}
|
||||
else if (SYSCLK_FREQ > 36000000)
|
||||
{
|
||||
RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV2;
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->CFG |= (uint32_t)RCC_CFG_APB1PRES_DIV1;
|
||||
}
|
||||
|
||||
#if SYSCLK_SRC == SYSCLK_USE_HSE
|
||||
/* Select HSE as system clock source */
|
||||
RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
|
||||
RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_HSE;
|
||||
|
||||
/* Wait till HSE is used as system clock source */
|
||||
while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x04)
|
||||
{
|
||||
}
|
||||
#elif SYSCLK_SRC == SYSCLK_USE_HSI_PLL || SYSCLK_SRC == SYSCLK_USE_HSE_PLL
|
||||
|
||||
/* clear bits */
|
||||
RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_PLLSRC | RCC_CFG_PLLHSEPRES | RCC_CFG_PLLMULFCT));
|
||||
|
||||
/* set PLL source */
|
||||
rcc_cfgr = RCC->CFG;
|
||||
rcc_cfgr |= (SYSCLK_SRC == SYSCLK_USE_HSI_PLL ? RCC_CFG_PLLSRC_HSI_DIV2 : RCC_CFG_PLLSRC_HSE);
|
||||
|
||||
#if SYSCLK_SRC == SYSCLK_USE_HSE_PLL
|
||||
rcc_cfgr |= (PLLSRC_DIV == 1 ? RCC_CFG_PLLHSEPRES_HSE : RCC_CFG_PLLHSEPRES_HSE_DIV2);
|
||||
#endif
|
||||
|
||||
/* set PLL multiply factor */
|
||||
#if PLL_MUL <= 16
|
||||
rcc_cfgr |= (PLL_MUL - 2) << 18;
|
||||
#else
|
||||
rcc_cfgr |= ((PLL_MUL - 17) << 18) | (1 << 27);
|
||||
#endif
|
||||
|
||||
RCC->CFG = rcc_cfgr;
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTRL |= RCC_CTRL_PLLEN;
|
||||
|
||||
/* Wait till PLL is ready */
|
||||
while ((RCC->CTRL & RCC_CTRL_PLLRDF) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFG &= (uint32_t)((uint32_t) ~(RCC_CFG_SCLKSW));
|
||||
RCC->CFG |= (uint32_t)RCC_CFG_SCLKSW_PLL;
|
||||
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while ((RCC->CFG & (uint32_t)RCC_CFG_SCLKSTS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file system_n32g45x.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __SYSTEM_N32G45X_H__
|
||||
#define __SYSTEM_N32G45X_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup N32G45X_System
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_N32G45X_H__ */
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_aes.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_AES_H__
|
||||
#define __N32G45X_AES_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup N32G45X_Algorithm_Library
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup AES
|
||||
* @brief AES symmetrical cipher algorithm
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define AES_ECB (0x11111111)
|
||||
#define AES_CBC (0x22222222)
|
||||
#define AES_CTR (0x33333333)
|
||||
|
||||
#define AES_ENC (0x44444444)
|
||||
#define AES_DEC (0x55555555)
|
||||
|
||||
enum
|
||||
{
|
||||
AES_Crypto_OK = 0x0, // AES opreation success
|
||||
AES_Init_OK = 0x0, // AES Init opreation success
|
||||
AES_Crypto_ModeError = 0x5a5a5a5a, // Working mode error(Neither ECB nor CBC nor CTR)
|
||||
AES_Crypto_EnOrDeError, // En&De error(Neither encryption nor decryption)
|
||||
AES_Crypto_ParaNull, // the part of input(output/iv) Null
|
||||
AES_Crypto_LengthError, // if Working mode is ECB or CBC,the length of input message must be 4 times and cannot be
|
||||
// zero;
|
||||
// if Working mode is CTR,the length of input message cannot be zero; othets: return AES_Crypto_LengthError
|
||||
|
||||
AES_Crypto_KeyLengthError, // the keyWordLen must be 4 or 6 or 8; othets:return AES_Crypto_KeyLengthError
|
||||
AES_Crypto_UnInitError, // AES uninitialized
|
||||
};
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t* in; // the part of input to be encrypted or decrypted
|
||||
uint32_t* iv; // the part of initial vector
|
||||
uint32_t* out; // the part of out
|
||||
uint32_t* key; // the part of key
|
||||
uint32_t keyWordLen; // the length(by word) of key
|
||||
uint32_t inWordLen; // the length(by word) of plaintext or cipher
|
||||
uint32_t En_De; // 0x44444444- encrypt, 0x55555555 - decrypt
|
||||
uint32_t Mode; // 0x11111111 - ECB, 0x22222222 - CBC, 0x33333333 - CTR
|
||||
} AES_PARM;
|
||||
|
||||
/**
|
||||
* @brief AES_Init
|
||||
* @return AES_Init_OK, AES Init success; othets: AES Init fail
|
||||
* @note
|
||||
*/
|
||||
|
||||
uint32_t AES_Init(AES_PARM* parm);
|
||||
|
||||
/**
|
||||
* @brief AES crypto
|
||||
* @param[in] parm pointer to AES context and the detail please refer to struct AES_PARM in AES.h
|
||||
* @return AES_Crypto_OK, AES crypto success; othets: AES crypto fail(reference to the definition by enum variation)
|
||||
* @note 1.Please refer to the demo in user guidance before using this function
|
||||
* 2.Input and output can be the same buffer
|
||||
* 3. IV can be NULL when ECB mode
|
||||
* 4. If Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
|
||||
* if Working mode is CTR,the length of input message cannot be zero;
|
||||
* 5. If the input is in byte, make sure align by word.
|
||||
*/
|
||||
uint32_t AES_Crypto(AES_PARM* parm);
|
||||
|
||||
/**
|
||||
* @brief AES close
|
||||
* @note if you want to close AES algorithm, this function can be recalled.
|
||||
*/
|
||||
void AES_Close(void);
|
||||
|
||||
/**
|
||||
* @brief Get AES lib version
|
||||
* @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
|
||||
* Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g.
|
||||
* 0x09 stands for CE version.
|
||||
* @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for
|
||||
* standard version, 0x01 is for Tianyu customized version...
|
||||
* @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this
|
||||
* denotes September 13,2018
|
||||
* @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes
|
||||
* version 1.2.
|
||||
* @1.You can recall this function to get AES lib information
|
||||
*/
|
||||
void AES_Version(uint8_t* type, uint8_t* customer, uint8_t date[3], uint8_t* version);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,161 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_algo_common.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_ALGO_COMMON_H__
|
||||
#define __N32G45X_ALGO_COMMON_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup N32G45X_Algorithm_Library
|
||||
* @{
|
||||
*/
|
||||
|
||||
enum
|
||||
{
|
||||
Cpy_OK = 0, // copy success
|
||||
SetZero_OK = 0, // set zero success
|
||||
XOR_OK = 0, // XOR success
|
||||
Reverse_OK = 0, // Reverse success
|
||||
Cmp_EQUAL = 0, // Two big number are equal
|
||||
Cmp_UNEQUAL = 1, // Two big number are not equal
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief disturb the sequence order
|
||||
* @param[in] order pointer to the sequence to be disturbed
|
||||
* @param[in] rand pointer to random number
|
||||
* @param[in] the length of order
|
||||
* @return RandomSort_OK: disturb order success; Others: disturb order fail;
|
||||
* @note
|
||||
*/
|
||||
u32 RandomSort(uint8_t* order, const uint8_t* rand, uint32_t len);
|
||||
|
||||
/**
|
||||
* @brief Copy data by byte
|
||||
* @param[in] dst pointer to destination data
|
||||
* @param[in] src pointer to source data
|
||||
* @param[in] byteLen length
|
||||
* @return Cpy_OK: success; others: fail.
|
||||
* @note 1. dst and src cannot be same
|
||||
*/
|
||||
uint32_t Cpy_U8(uint8_t* dst, uint8_t* src, uint32_t byteLen);
|
||||
|
||||
/**
|
||||
* @brief Copy data by word
|
||||
* @param[in] dst pointer to destination data
|
||||
* @param[in] src pointer to source data
|
||||
* @param[in] wordLen length
|
||||
* @return Cpy_OK: success; others: fail.
|
||||
* @note 1. dst and src must be aligned by word
|
||||
*/
|
||||
uint32_t Cpy_U32(uint32_t* dst, const uint32_t* src, uint32_t wordLen);
|
||||
|
||||
/**
|
||||
* @brief XOR
|
||||
* @param[in] a pointer to one data to be XORed
|
||||
* @param[in] b pointer to another data to be XORed
|
||||
* @param[in] c pointer to result
|
||||
* @param[in] byteLen the length of order
|
||||
* @return XOR_OK: operation success; Others: operation fail;
|
||||
* @note
|
||||
*/
|
||||
uint32_t XOR_U8(uint8_t* a, uint8_t* b, uint8_t* c, uint32_t byteLen);
|
||||
|
||||
/**
|
||||
* @brief XORed two uint32_t arrays
|
||||
* @param[in] a pointer to one data to be XORed
|
||||
* @param[in] b pointer to another data to be XORed
|
||||
* @param[in] c pointer to result
|
||||
* @param[in] wordLen the length of order
|
||||
* @return XOR_OK: operation success; Others: operation fail;
|
||||
* @note
|
||||
*/
|
||||
uint32_t XOR_U32(uint32_t* a, uint32_t* b, uint32_t* c, uint32_t wordLen);
|
||||
|
||||
/**
|
||||
* @brief set zero by byte
|
||||
* @param[in] dst pointer to the address to be set zero
|
||||
* @param[in] byteLen length
|
||||
* @return SetZero_OK: success; others: fail.
|
||||
* @note
|
||||
*/
|
||||
uint32_t SetZero_U8(uint8_t* dst, uint32_t byteLen);
|
||||
|
||||
/**
|
||||
* @brief set zero by word
|
||||
* @param[in] dst pointer to the address to be set zero
|
||||
* @param[in] wordLen length
|
||||
* @return SetZero_OK: success; others: fail.
|
||||
* @note
|
||||
*/
|
||||
uint32_t SetZero_U32(uint32_t* dst, uint32_t wordLen);
|
||||
|
||||
/**
|
||||
* @brief reverse byte order of every word, the words stay the same
|
||||
* @param[in] dst pointer to the destination address
|
||||
* @param[in] src pointer to the source address
|
||||
* @param[in] wordLen length
|
||||
* @return Reverse_OK: success; others: fail.
|
||||
* @note 1.dst and src can be same
|
||||
*/
|
||||
uint32_t ReverseBytesInWord_U32(uint32_t* dst, const uint32_t* src, uint32_t wordLen);
|
||||
|
||||
/**
|
||||
* @brief compare two big number
|
||||
* @param[in] a pointer to one big number
|
||||
* @param[in] aWordLen length of a
|
||||
* @param[in] b pointer to another big number
|
||||
* @param[in] bWordLen length of b
|
||||
* @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
|
||||
*/
|
||||
int32_t Cmp_U32(const uint32_t* a, uint32_t aWordLen, const uint32_t* b, uint32_t bWordLen);
|
||||
|
||||
/**
|
||||
* @brief compare two big number
|
||||
* @param[in] a pointer to one big number
|
||||
* @param[in] aByteLen length of a
|
||||
* @param[in] b pointer to another big number
|
||||
* @param[in] bByteLen length of b
|
||||
* @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
|
||||
*/
|
||||
int32_t Cmp_U8(const uint8_t* a, uint32_t aByteLen, const uint8_t* b, uint32_t bByteLen);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_des.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_DES_H__
|
||||
#define __N32G45X_DES_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup N32G45X_Algorithm_Library
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DES
|
||||
* @brief DES symmetrical cipher algorithm
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DES_ECB (0x11111111)
|
||||
#define DES_CBC (0x22222222)
|
||||
|
||||
#define DES_ENC (0x33333333)
|
||||
#define DES_DEC (0x44444444)
|
||||
|
||||
#define DES_KEY (0x55555555)
|
||||
#define TDES_2KEY (0x66666666)
|
||||
#define TDES_3KEY (0x77777777)
|
||||
|
||||
enum DES
|
||||
{
|
||||
DES_Crypto_OK = 0x0, // DES/TDES opreation success
|
||||
DES_Init_OK = 0x0, // DES/TDES Init opreation success
|
||||
DES_Crypto_ModeError = 0x5a5a5a5a, // Working mode error(Neither ECB nor CBC)
|
||||
DES_Crypto_EnOrDeError, // En&De error(Neither encryption nor decryption)
|
||||
DES_Crypto_ParaNull, // the part of input(output/iv) Null
|
||||
DES_Crypto_LengthError, // the length of input message must be 2 times and cannot be zero
|
||||
DES_Crypto_KeyError, // keyMode error(Neither DES_KEY nor TDES_2KEY nor TDES_3KEY)
|
||||
DES_Crypto_UnInitError, // DES/TDES uninitialized
|
||||
};
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t* in; // the part of input to be encrypted or decrypted
|
||||
uint32_t* iv; // the part of initial vector
|
||||
uint32_t* out; // the part of out
|
||||
uint32_t* key; // the part of key
|
||||
uint32_t inWordLen; // the length(by word) of plaintext or cipher
|
||||
uint32_t En_De; // 0x33333333- encrypt, 0x44444444 - decrypt
|
||||
uint32_t Mode; // 0x11111111 - ECB, 0x22222222 - CBC
|
||||
uint32_t keyMode; // TDES key mode: 0x55555555-key,0x66666666-2key, 0x77777777-3key
|
||||
} DES_PARM;
|
||||
|
||||
/**
|
||||
* @brief DES_Init
|
||||
* @return DES_Init_OK, DES/TDES Init success; othets: DES/TDES Init fail
|
||||
* @note
|
||||
*/
|
||||
uint32_t DES_Init(DES_PARM* parm);
|
||||
|
||||
/**
|
||||
* @brief DES crypto
|
||||
* @param[in] parm pointer to DES/TDES context and the detail please refer to struct DES_PARM in DES.h
|
||||
* @return DES_Crypto_OK, DES/TDES crypto success; othets: DES/TDES crypto fail(reference to the definition by enum
|
||||
* variation)
|
||||
* @note 1.Please refer to the demo in user guidance before using this function
|
||||
* 2.Input and output can be the same buffer
|
||||
* 3. IV can be NULL when ECB mode
|
||||
* 4. The word lengrh of message must be as times as 2.
|
||||
* 5. If the input is in byte, make sure align by word.
|
||||
*/
|
||||
uint32_t DES_Crypto(DES_PARM* parm);
|
||||
|
||||
/**
|
||||
* @brief DES close
|
||||
* @note if you want to close DES algorithm, this function can be recalled.
|
||||
*/
|
||||
void DES_Close(void);
|
||||
|
||||
/**
|
||||
* @brief Get DES/TDES lib version
|
||||
* @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
|
||||
* Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g.
|
||||
* 0x09 stands for CE version.
|
||||
* @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for
|
||||
* standard version, 0x01 is for Tianyu customized version...
|
||||
* @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this
|
||||
* denotes September 13,2018
|
||||
* @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes
|
||||
* version 1.2.
|
||||
* @1.You can recall this function to get DES/TDES lib information
|
||||
*/
|
||||
void DES_Version(uint8_t* type, uint8_t* customer, uint8_t date[3], uint8_t* version);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
|
@ -0,0 +1,228 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_hash.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_HASH_H__
|
||||
#define __N32G45X_HASH_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup N32G45X_Algorithm_Library
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HASH
|
||||
* @brief Message digest algorithms
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ALG_SHA1 (uint16_t)(0x0004)
|
||||
#define ALG_SHA224 (uint16_t)(0x000A)
|
||||
#define ALG_SHA256 (uint16_t)(0x000B)
|
||||
#define ALG_MD5 (uint16_t)(0x000C)
|
||||
#define ALG_SM3 (uint16_t)(0x0012)
|
||||
|
||||
enum
|
||||
{
|
||||
HASH_SEQUENCE_TRUE = 0x0105A5A5, // save IV
|
||||
HASH_SEQUENCE_FALSE = 0x010A5A5A, // not save IV
|
||||
HASH_Init_OK = 0, // hash init success
|
||||
HASH_Start_OK = 0, // hash update success
|
||||
HASH_Update_OK = 0, // hash update success
|
||||
HASH_Complete_OK = 0, // hash complete success
|
||||
HASH_Close_OK = 0, // hash close success
|
||||
HASH_ByteLenPlus_OK = 0, // byte length plus success
|
||||
HASH_PadMsg_OK = 0, // message padding success
|
||||
HASH_ProcMsgBuf_OK = 0, // message processing success
|
||||
SHA1_Hash_OK = 0, // sha1 operation success
|
||||
SM3_Hash_OK = 0, // sm3 operation success
|
||||
SHA224_Hash_OK = 0, // sha224 operation success
|
||||
SHA256_Hash_OK = 0, // sha256 operation success
|
||||
MD5_Hash_OK = 0, // MD5 operation success
|
||||
|
||||
HASH_Init_ERROR = 0x01044400, // hash init error
|
||||
HASH_Start_ERROR, // hash start error
|
||||
HASH_Update_ERROR, // hash update error
|
||||
HASH_ByteLenPlus_ERROR, // hash byte plus error
|
||||
};
|
||||
|
||||
typedef struct _HASH_CTX_ HASH_CTX;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
const uint16_t HashAlgID; // choice hash algorithm
|
||||
const uint32_t *const K, KLen; // K and byte length of K
|
||||
const uint32_t *const IV, IVLen; // IV and byte length of IV
|
||||
const uint32_t HASH_SACCR, HASH_HASHCTRL; // relate registers
|
||||
const uint32_t BlockByteLen, BlockWordLen; // byte length of block, word length of block
|
||||
const uint32_t DigestByteLen, DigestWordLen; // byte length of digest,word length of digest
|
||||
const uint32_t Cycle; // interation times
|
||||
uint32_t (*const ByteLenPlus)(uint32_t*, uint32_t); // function pointer
|
||||
uint32_t (*const PadMsg)(HASH_CTX*); // function pointer
|
||||
} HASH_ALG;
|
||||
|
||||
typedef struct _HASH_CTX_
|
||||
{
|
||||
const HASH_ALG* hashAlg; // pointer to HASH_ALG
|
||||
uint32_t sequence; // TRUE if the IV should be saved
|
||||
uint32_t IV[16];
|
||||
uint32_t msgByteLen[4];
|
||||
uint8_t msgBuf[128 + 4];
|
||||
uint32_t msgIdx;
|
||||
} HASH_CTX;
|
||||
|
||||
extern const HASH_ALG HASH_ALG_SHA1[1];
|
||||
extern const HASH_ALG HASH_ALG_SHA224[1];
|
||||
extern const HASH_ALG HASH_ALG_SHA256[1];
|
||||
extern const HASH_ALG HASH_ALG_MD5[1];
|
||||
extern const HASH_ALG HASH_ALG_SM3[1];
|
||||
|
||||
/**
|
||||
* @brief Hash init
|
||||
* @param[in] ctx pointer to HASH_CTX struct
|
||||
* @return HASH_Init_OK, Hash init success; others: Hash init fail
|
||||
* @note 1.Please refer to the demo in user guidance before using this function
|
||||
*/
|
||||
uint32_t HASH_Init(HASH_CTX* ctx);
|
||||
|
||||
/**
|
||||
* @brief Hash start
|
||||
* @param[in] ctx pointer to HASH_CTX struct
|
||||
* @return HASH_Start_OK, Hash start success; othets: Hash start fail
|
||||
* @note 1.Please refer to the demo in user guidance before using this function
|
||||
* 2.HASH_Init() should be recalled before use this function
|
||||
*/
|
||||
uint32_t HASH_Start(HASH_CTX* ctx);
|
||||
|
||||
/**
|
||||
* @brief Hash update
|
||||
* @param[in] ctx pointer to HASH_CTX struct
|
||||
* @param[in] in pointer to message
|
||||
* @param[in] byteLen message length
|
||||
* @return HASH_Update_OK, Hash update success; othets: Hash update fail
|
||||
* @note 1.Please refer to the demo in user guidance before using this function
|
||||
* 2.HASH_Init() and HASH_Start() should be recalled before use this function
|
||||
*/
|
||||
uint32_t HASH_Update(HASH_CTX* ctx, uint8_t* in, uint32_t byteLen);
|
||||
|
||||
/**
|
||||
* @brief Hash complete
|
||||
* @param[in] ctx pointer to HASH_CTX struct
|
||||
* @param[out] out pointer to hash result,digest
|
||||
* @return HASH_Complete_OK, Hash complete success; othets: Hash complete fail
|
||||
* @note 1.Please refer to the demo in user guidance before using this function
|
||||
* 2.HASH_Init(), HASH_Start() and HASH_Update() should be recalled before use this function
|
||||
*/
|
||||
uint32_t HASH_Complete(HASH_CTX* ctx, uint8_t* out);
|
||||
|
||||
/**
|
||||
* @brief Hash close
|
||||
* @return HASH_Close_OK, Hash close success; othets: Hash close fail
|
||||
* @note 1.Please refer to the demo in user guidance before using this function
|
||||
*/
|
||||
uint32_t HASH_Close(void);
|
||||
|
||||
/**
|
||||
* @brief SM3 Hash for 256bits digest
|
||||
* @param[in] in pointer to message
|
||||
* @param[in] byteLen length of in
|
||||
* @param[out] out pointer tohash result,digest
|
||||
* @return SM3_Hash_OK, SM3 hash success; othets: SM3 hash fail
|
||||
* @note 1.Please refer to the demo in user guidance before using this function
|
||||
*/
|
||||
uint32_t SM3_Hash(uint8_t* in, uint32_t byteLen, uint8_t* out);
|
||||
|
||||
/**
|
||||
* @brief SHA1 Hash
|
||||
* @param[in] in pointer to message
|
||||
* @param[in] byteLen length of in
|
||||
* @param[out] out pointer tohash result,digest
|
||||
* @return SHA1_Hash_OK, SHA1 hash success; othets: SHA1 hash fail
|
||||
* @note 1.Please refer to the demo in user guidance before using this function
|
||||
*/
|
||||
uint32_t SHA1_Hash(uint8_t* in, uint32_t byteLen, uint8_t* out);
|
||||
|
||||
/**
|
||||
* @brief SHA224 Hash
|
||||
* @param[in] in pointer to message
|
||||
* @param[in] byteLen length of in
|
||||
* @param[out] out pointer tohash result,digest
|
||||
* @return SHA224_Hash_OK, SHA224 hash success; othets: SHA224 hash fail
|
||||
* @note 1.Please refer to the demo in user guidance before using this function
|
||||
*/
|
||||
uint32_t SHA224_Hash(uint8_t* in, uint32_t byteLen, uint8_t* out);
|
||||
|
||||
/**
|
||||
* @brief SHA256 Hash
|
||||
* @param[in] in pointer to message
|
||||
* @param[in] byteLen length of in
|
||||
* @param[out] out pointer tohash result,digest
|
||||
* @return SHA256_Hash_OK, SHA256 hash success; othets: SHA256 hash fail
|
||||
* @note 1.Please refer to the demo in user guidance before using this function
|
||||
*/
|
||||
uint32_t SHA256_Hash(uint8_t* in, uint32_t byteLen, uint8_t* out);
|
||||
|
||||
/**
|
||||
* @brief MD5 Hash
|
||||
* @param[in] in pointer to message
|
||||
* @param[in] byteLen length of in
|
||||
* @param[in] out pointer tohash result,digest
|
||||
* @return MD5_Hash_OK, MD5 hash success; othets: MD5 hash fail
|
||||
* @note 1.Please refer to the demo in user guidance before using this function
|
||||
*/
|
||||
uint32_t MD5_Hash(uint8_t* in, uint32_t byteLen, uint8_t* out);
|
||||
|
||||
/**
|
||||
* @brief Get HASH lib version
|
||||
* @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
|
||||
* Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g.
|
||||
* 0x09 stands for CE version.
|
||||
* @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for
|
||||
* standard version, 0x01 is for Tianyu customized version...
|
||||
* @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this
|
||||
* denotes September 13,2018
|
||||
* @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes
|
||||
* version 1.2.
|
||||
* @1.You can recall this function to get RSA lib information
|
||||
*/
|
||||
void HASH_Version(uint8_t* type, uint8_t* customer, uint8_t date[3], uint8_t* version);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_rng.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_RNG_H__
|
||||
#define __N32G45X_RNG_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup N32G45X_Algorithm_Library
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RNG
|
||||
* @brief Random number generator
|
||||
* @{
|
||||
*/
|
||||
|
||||
enum
|
||||
{
|
||||
RNG_OK = 0x5a5a5a5a,
|
||||
LENError = 0x311ECF50, // RNG generation of key length error
|
||||
ADDRNULL = 0x7A9DB86C, // This address is empty
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Get pseudo random number
|
||||
* @param[out] rand pointer to random number
|
||||
* @param[in] wordLen the wordlen of random number
|
||||
* @param[in] seed the seed, can be NULL
|
||||
* @return RNG_OK:get random number success; othets: get random number fail
|
||||
* @note
|
||||
*/
|
||||
uint32_t GetPseudoRand_U32(uint32_t* rand, uint32_t wordLen, uint32_t seed[2]);
|
||||
|
||||
/**
|
||||
* @brief Get true random number
|
||||
* @param[out] rand pointer to random number
|
||||
* @param[in] wordLen the wordlen of random number
|
||||
* @return RNG_OK:get random number success; othets: get random number fail
|
||||
* @note
|
||||
*/
|
||||
uint32_t GetTrueRand_U32(uint32_t* rand, uint32_t wordLen);
|
||||
|
||||
/**
|
||||
* @brief Get RNG lib version
|
||||
* @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
|
||||
* Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g.
|
||||
* 0x09 stands for CE version.
|
||||
* @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for
|
||||
* standard version, 0x01 is for Tianyu customized version...
|
||||
* @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this
|
||||
* denotes September 13,2018
|
||||
* @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes
|
||||
* version 1.2.
|
||||
* @1.You can recall this function to get RSA lib information
|
||||
*/
|
||||
void RNG_Version(uint8_t* type, uint8_t* customer, uint8_t date[3], uint8_t* version);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,229 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file misc.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __MISC_H__
|
||||
#define __MISC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief NVIC Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
|
||||
This parameter can be a value of @ref IRQn_Type
|
||||
(For the complete N32G45X Devices IRQ Channels list, please
|
||||
refer to n32g45x.h file) */
|
||||
|
||||
uint8_t
|
||||
NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
|
||||
specified in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
|
||||
|
||||
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
|
||||
in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
|
||||
|
||||
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
|
||||
will be enabled or disabled.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
} NVIC_InitType;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NVIC_Priority_Table
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
@code
|
||||
The table below gives the allowed values of the pre-emption priority and subpriority according
|
||||
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
|
||||
============================================================================================================================
|
||||
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||
============================================================================================================================
|
||||
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption
|
||||
priority | | | 4 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption
|
||||
priority | | | 3 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption
|
||||
priority | | | 2 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption
|
||||
priority | | | 1 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption
|
||||
priority | | | 0 bits for subpriority
|
||||
============================================================================================================================
|
||||
@endcode
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Vector_Table_Base
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
|
||||
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
|
||||
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || ((VECTTAB) == NVIC_VectTab_FLASH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup System_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
|
||||
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
|
||||
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
|
||||
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || ((LP) == NVIC_LP_SLEEPDEEP) || ((LP) == NVIC_LP_SLEEPONEXIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Preemption_Priority_Group
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_PriorityGroup_0 \
|
||||
((uint32_t)0x700) /*!< 0 bits for pre-emption priority \
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_1 \
|
||||
((uint32_t)0x600) /*!< 1 bits for pre-emption priority \
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_2 \
|
||||
((uint32_t)0x500) /*!< 2 bits for pre-emption priority \
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_3 \
|
||||
((uint32_t)0x400) /*!< 3 bits for pre-emption priority \
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_4 \
|
||||
((uint32_t)0x300) /*!< 4 bits for pre-emption priority \
|
||||
0 bits for subpriority */
|
||||
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) \
|
||||
(((GROUP) == NVIC_PriorityGroup_0) || ((GROUP) == NVIC_PriorityGroup_1) || ((GROUP) == NVIC_PriorityGroup_2) \
|
||||
|| ((GROUP) == NVIC_PriorityGroup_3) || ((GROUP) == NVIC_PriorityGroup_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SysTick_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) \
|
||||
(((SOURCE) == SysTick_CLKSource_HCLK) || ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
|
||||
void NVIC_Init(NVIC_InitType* NVIC_InitStruct);
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd);
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MISC_H__ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,642 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_adc.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_ADC_H__
|
||||
#define __N32G45X_ADC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
#include <stdbool.h>
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ADC Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t WorkMode; /*!< Configures the ADC to operate in independent or
|
||||
dual mode.
|
||||
This parameter can be a value of @ref ADC_mode */
|
||||
|
||||
FunctionalState MultiChEn; /*!< Specifies whether the conversion is performed in
|
||||
Scan (multichannels) or Single (one channel) mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
FunctionalState ContinueConvEn; /*!< Specifies whether the conversion is performed in
|
||||
Continuous or Single mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t ExtTrigSelect; /*!< Defines the external trigger used to start the analog
|
||||
to digital conversion of regular channels. This parameter
|
||||
can be a value of @ref
|
||||
ADC_external_trigger_sources_for_regular_channels_conversion */
|
||||
|
||||
uint32_t DatAlign; /*!< Specifies whether the ADC data alignment is left or right.
|
||||
This parameter can be a value of @ref ADC_data_align */
|
||||
|
||||
uint8_t ChsNumber; /*!< Specifies the number of ADC channels that will be converted
|
||||
using the sequencer for regular channel group.
|
||||
This parameter must range from 1 to 16. */
|
||||
} ADC_InitType;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IsAdcModule(PERIPH) (((PERIPH) == ADC1) || ((PERIPH) == ADC2) || ((PERIPH) == ADC3) || ((PERIPH) == ADC4))
|
||||
|
||||
#define IsAdcDmaModule(PERIPH) (((PERIPH) == ADC1) || ((PERIPH) == ADC3))
|
||||
|
||||
/** @addtogroup ADC_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_WORKMODE_INDEPENDENT ((uint32_t)0x00000000)
|
||||
#define ADC_WORKMODE_SEQ_INJECT_SIMULT ((uint32_t)0x00010000)
|
||||
#define ADC_WORKMODE_SEQ_SIMULT_ALTER_TRIG ((uint32_t)0x00020000)
|
||||
#define ADC_WORKMODE_INJ_SIMULT_FAST_INTERL ((uint32_t)0x00030000)
|
||||
#define ADC_WORKMODE_INT_SIMULT_SLOW_INTERL ((uint32_t)0x00040000)
|
||||
#define ADC_WORKMODE_INJ_SIMULT ((uint32_t)0x00050000)
|
||||
#define ADC_WORKMODE_REG_SIMULT ((uint32_t)0x00060000)
|
||||
#define ADC_WORKMODE_FAST_INTERL ((uint32_t)0x00070000)
|
||||
#define ADC_WORKMODE_SLOW_INTERL ((uint32_t)0x00080000)
|
||||
#define ADC_WORKMODE_ALTER_TRIG ((uint32_t)0x00090000)
|
||||
|
||||
#define IsAdcWorkMode(MODE) \
|
||||
(((MODE) == ADC_WORKMODE_INDEPENDENT) || ((MODE) == ADC_WORKMODE_SEQ_INJECT_SIMULT) \
|
||||
|| ((MODE) == ADC_WORKMODE_SEQ_SIMULT_ALTER_TRIG) || ((MODE) == ADC_WORKMODE_INJ_SIMULT_FAST_INTERL) \
|
||||
|| ((MODE) == ADC_WORKMODE_INT_SIMULT_SLOW_INTERL) || ((MODE) == ADC_WORKMODE_INJ_SIMULT) \
|
||||
|| ((MODE) == ADC_WORKMODE_REG_SIMULT) || ((MODE) == ADC_WORKMODE_FAST_INTERL) \
|
||||
|| ((MODE) == ADC_WORKMODE_SLOW_INTERL) || ((MODE) == ADC_WORKMODE_ALTER_TRIG))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_external_trigger_sources_for_regular_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_EXT_TRIGCONV_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_EXT_TRIGCONV_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_EXT_TRIGCONV_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_EXT_TRIGCONV_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_EXT_TRIGCONV_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */
|
||||
|
||||
#define ADC_EXT_TRIGCONV_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 , ADC3 and ADC4 */
|
||||
#define ADC_EXT_TRIGCONV_NONE ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 , ADC3 and ADC4 */
|
||||
|
||||
#define ADC_EXT_TRIGCONV_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 and ADC4 */
|
||||
#define ADC_EXT_TRIGCONV_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 and ADC4 */
|
||||
#define ADC_EXT_TRIGCONV_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 and ADC4 */
|
||||
#define ADC_EXT_TRIGCONV_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 and ADC4 */
|
||||
#define ADC_EXT_TRIGCONV_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 and ADC4 */
|
||||
#define ADC_EXT_TRIGCONV_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 and ADC4 */
|
||||
|
||||
#define IsAdcExtTrig(REGTRIG) \
|
||||
(((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC2) \
|
||||
|| ((REGTRIG) == ADC_EXT_TRIGCONV_T1_CC3) || ((REGTRIG) == ADC_EXT_TRIGCONV_T2_CC2) \
|
||||
|| ((REGTRIG) == ADC_EXT_TRIGCONV_T3_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_T4_CC4) \
|
||||
|| ((REGTRIG) == ADC_EXT_TRIGCONV_EXT_INT11_TIM8_TRGO) || ((REGTRIG) == ADC_EXT_TRIGCONV_NONE) \
|
||||
|| ((REGTRIG) == ADC_EXT_TRIGCONV_T3_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T2_CC3) \
|
||||
|| ((REGTRIG) == ADC_EXT_TRIGCONV_T8_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T8_TRGO) \
|
||||
|| ((REGTRIG) == ADC_EXT_TRIGCONV_T5_CC1) || ((REGTRIG) == ADC_EXT_TRIGCONV_T5_CC3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_data_align
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_DAT_ALIGN_R ((uint32_t)0x00000000)
|
||||
#define ADC_DAT_ALIGN_L ((uint32_t)0x00000800)
|
||||
#define IsAdcDatAlign(ALIGN) (((ALIGN) == ADC_DAT_ALIGN_R) || ((ALIGN) == ADC_DAT_ALIGN_L))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_channels
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_CH_0 ((uint8_t)0x00)
|
||||
#define ADC_CH_1 ((uint8_t)0x01)
|
||||
#define ADC_CH_2 ((uint8_t)0x02)
|
||||
#define ADC_CH_3 ((uint8_t)0x03)
|
||||
#define ADC_CH_4 ((uint8_t)0x04)
|
||||
#define ADC_CH_5 ((uint8_t)0x05)
|
||||
#define ADC_CH_6 ((uint8_t)0x06)
|
||||
#define ADC_CH_7 ((uint8_t)0x07)
|
||||
#define ADC_CH_8 ((uint8_t)0x08)
|
||||
#define ADC_CH_9 ((uint8_t)0x09)
|
||||
#define ADC_CH_10 ((uint8_t)0x0A)
|
||||
#define ADC_CH_11 ((uint8_t)0x0B)
|
||||
#define ADC_CH_12 ((uint8_t)0x0C)
|
||||
#define ADC_CH_13 ((uint8_t)0x0D)
|
||||
#define ADC_CH_14 ((uint8_t)0x0E)
|
||||
#define ADC_CH_15 ((uint8_t)0x0F)
|
||||
#define ADC_CH_16 ((uint8_t)0x10)
|
||||
#define ADC_CH_17 ((uint8_t)0x11)
|
||||
#define ADC_CH_18 ((uint8_t)0x12)
|
||||
|
||||
#define ADC_CH_TEMP_SENSOR ((uint8_t)ADC_CH_16)
|
||||
#define ADC_CH_INT_VREF ((uint8_t)ADC_CH_18)
|
||||
|
||||
#define IsAdcChannel(CHANNEL) \
|
||||
(((CHANNEL) == ADC_CH_0) || ((CHANNEL) == ADC_CH_1) || ((CHANNEL) == ADC_CH_2) || ((CHANNEL) == ADC_CH_3) \
|
||||
|| ((CHANNEL) == ADC_CH_4) || ((CHANNEL) == ADC_CH_5) || ((CHANNEL) == ADC_CH_6) || ((CHANNEL) == ADC_CH_7) \
|
||||
|| ((CHANNEL) == ADC_CH_8) || ((CHANNEL) == ADC_CH_9) || ((CHANNEL) == ADC_CH_10) || ((CHANNEL) == ADC_CH_11) \
|
||||
|| ((CHANNEL) == ADC_CH_12) || ((CHANNEL) == ADC_CH_13) || ((CHANNEL) == ADC_CH_14) || ((CHANNEL) == ADC_CH_15) \
|
||||
|| ((CHANNEL) == ADC_CH_16) || ((CHANNEL) == ADC_CH_17) || ((CHANNEL) == ADC_CH_18))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_sampling_time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_SAMP_TIME_1CYCLES5 ((uint8_t)0x00)
|
||||
#define ADC_SAMP_TIME_7CYCLES5 ((uint8_t)0x01)
|
||||
#define ADC_SAMP_TIME_13CYCLES5 ((uint8_t)0x02)
|
||||
#define ADC_SAMP_TIME_28CYCLES5 ((uint8_t)0x03)
|
||||
#define ADC_SAMP_TIME_41CYCLES5 ((uint8_t)0x04)
|
||||
#define ADC_SAMP_TIME_55CYCLES5 ((uint8_t)0x05)
|
||||
#define ADC_SAMP_TIME_71CYCLES5 ((uint8_t)0x06)
|
||||
#define ADC_SAMP_TIME_239CYCLES5 ((uint8_t)0x07)
|
||||
#define IsAdcSampleTime(TIME) \
|
||||
(((TIME) == ADC_SAMP_TIME_1CYCLES5) || ((TIME) == ADC_SAMP_TIME_7CYCLES5) || ((TIME) == ADC_SAMP_TIME_13CYCLES5) \
|
||||
|| ((TIME) == ADC_SAMP_TIME_28CYCLES5) || ((TIME) == ADC_SAMP_TIME_41CYCLES5) \
|
||||
|| ((TIME) == ADC_SAMP_TIME_55CYCLES5) || ((TIME) == ADC_SAMP_TIME_71CYCLES5) \
|
||||
|| ((TIME) == ADC_SAMP_TIME_239CYCLES5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_external_trigger_sources_for_injected_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_EXT_TRIG_INJ_CONV_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_EXT_TRIG_INJ_CONV_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_EXT_TRIG_INJ_CONV_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_EXT_TRIG_INJ_CONV_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */
|
||||
#define ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */
|
||||
|
||||
#define ADC_EXT_TRIG_INJ_CONV_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2, ADC3 and ADC4 */
|
||||
#define ADC_EXT_TRIG_INJ_CONV_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2, ADC3 and ADC4 */
|
||||
#define ADC_EXT_TRIG_INJ_CONV_NONE ((uint32_t)0x00007000) /*!< For ADC1, ADC2, ADC3 and ADC4 */
|
||||
|
||||
#define ADC_EXT_TRIG_INJ_CONV_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 and ADC4 */
|
||||
#define ADC_EXT_TRIG_INJ_CONV_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 and ADC4 */
|
||||
#define ADC_EXT_TRIG_INJ_CONV_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 and ADC4 */
|
||||
#define ADC_EXT_TRIG_INJ_CONV_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 and ADC4 */
|
||||
#define ADC_EXT_TRIG_INJ_CONV_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 and ADC4 */
|
||||
|
||||
#define IsAdcExtInjTrig(INJTRIG) \
|
||||
(((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T1_CC4) \
|
||||
|| ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_TRGO) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T2_CC1) \
|
||||
|| ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T3_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T4_TRGO) \
|
||||
|| ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_EXT_INT15_TIM8_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_NONE) \
|
||||
|| ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T4_CC3) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T8_CC2) \
|
||||
|| ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T8_CC4) || ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T5_TRGO) \
|
||||
|| ((INJTRIG) == ADC_EXT_TRIG_INJ_CONV_T5_CC4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_injected_channel_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_INJ_CH_1 ((uint8_t)0x14)
|
||||
#define ADC_INJ_CH_2 ((uint8_t)0x18)
|
||||
#define ADC_INJ_CH_3 ((uint8_t)0x1C)
|
||||
#define ADC_INJ_CH_4 ((uint8_t)0x20)
|
||||
#define IsAdcInjCh(CHANNEL) \
|
||||
(((CHANNEL) == ADC_INJ_CH_1) || ((CHANNEL) == ADC_INJ_CH_2) || ((CHANNEL) == ADC_INJ_CH_3) \
|
||||
|| ((CHANNEL) == ADC_INJ_CH_4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_analog_watchdog_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_ANALOG_WTDG_SINGLEREG_ENABLE ((uint32_t)0x00800200)
|
||||
#define ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE ((uint32_t)0x00400200)
|
||||
#define ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE ((uint32_t)0x00C00200)
|
||||
#define ADC_ANALOG_WTDG_ALLREG_ENABLE ((uint32_t)0x00800000)
|
||||
#define ADC_ANALOG_WTDG_ALLINJEC_ENABLE ((uint32_t)0x00400000)
|
||||
#define ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE ((uint32_t)0x00C00000)
|
||||
#define ADC_ANALOG_WTDG_NONE ((uint32_t)0x00000000)
|
||||
|
||||
#define IsAdcAnalogWatchdog(WATCHDOG) \
|
||||
(((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEINJEC_ENABLE) \
|
||||
|| ((WATCHDOG) == ADC_ANALOG_WTDG_SINGLEREG_OR_INJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ENABLE) \
|
||||
|| ((WATCHDOG) == ADC_ANALOG_WTDG_ALLINJEC_ENABLE) || ((WATCHDOG) == ADC_ANALOG_WTDG_ALLREG_ALLINJEC_ENABLE) \
|
||||
|| ((WATCHDOG) == ADC_ANALOG_WTDG_NONE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_INT_ENDC ((uint16_t)0x0220)
|
||||
#define ADC_INT_AWD ((uint16_t)0x0140)
|
||||
#define ADC_INT_JENDC ((uint16_t)0x0480)
|
||||
|
||||
#define IsAdcInt(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define IsAdcGetInt(IT) (((IT) == ADC_INT_ENDC) || ((IT) == ADC_INT_AWD) || ((IT) == ADC_INT_JENDC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_FLAG_AWDG ((uint8_t)0x01)
|
||||
#define ADC_FLAG_ENDC ((uint8_t)0x02)
|
||||
#define ADC_FLAG_JENDC ((uint8_t)0x04)
|
||||
#define ADC_FLAG_JSTR ((uint8_t)0x08)
|
||||
#define ADC_FLAG_STR ((uint8_t)0x10)
|
||||
#define ADC_FLAG_EOC_ANY ((uint8_t)0x20)
|
||||
#define ADC_FLAG_JEOC_ANY ((uint8_t)0x40)
|
||||
#define IsAdcClrFlag(FLAG) ((((FLAG) & (uint8_t)0x80) == 0x00) && ((FLAG) != 0x00))
|
||||
#define IsAdcGetFlag(FLAG) \
|
||||
(((FLAG) == ADC_FLAG_AWDG) || ((FLAG) == ADC_FLAG_ENDC) || ((FLAG) == ADC_FLAG_JENDC) || ((FLAG) == ADC_FLAG_JSTR) \
|
||||
|| ((FLAG) == ADC_FLAG_STR) || ((FLAG) == ADC_FLAG_EOC_ANY) || ((FLAG) == ADC_FLAG_JEOC_ANY))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_thresholds
|
||||
* @{
|
||||
*/
|
||||
#define IsAdcValid(THRESHOLD) ((THRESHOLD) <= 0xFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_injected_offset
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IsAdcOffsetValid(OFFSET) ((OFFSET) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_injected_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IsAdcInjLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_injected_rank
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IsAdcInjRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_regular_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IsAdcSeqLenValid(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_regular_rank
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IsAdcReqRankValid(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_regular_discontinuous_mode_number
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IsAdcSeqDiscNumberValid(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************** fllowing bit seg in ex register **********************/
|
||||
/**@addtogroup ADC_channels_ex_style
|
||||
* @{
|
||||
*/
|
||||
#define ADC1_Channel_01_PA0 ((uint8_t)0x01)
|
||||
#define ADC1_Channel_02_PA1 ((uint8_t)0x02)
|
||||
#define ADC1_Channel_03_PA6 ((uint8_t)0x03)
|
||||
#define ADC1_Channel_04_PA3 ((uint8_t)0x04)
|
||||
#define ADC1_Channel_05_PF4 ((uint8_t)0x05)
|
||||
#define ADC1_Channel_06_PC0 ((uint8_t)0x06)
|
||||
#define ADC1_Channel_07_PC1 ((uint8_t)0x07)
|
||||
#define ADC1_Channel_08_PC2 ((uint8_t)0x08)
|
||||
#define ADC1_Channel_09_PC3 ((uint8_t)0x09)
|
||||
#define ADC1_Channel_10_PF2 ((uint8_t)0x0A)
|
||||
#define ADC1_Channel_11_PA2 ((uint8_t)0x0B)
|
||||
|
||||
#define ADC2_Channel_01_PA4 ((uint8_t)0x01)
|
||||
#define ADC2_Channel_02_PA5 ((uint8_t)0x02)
|
||||
#define ADC2_Channel_03_PB1 ((uint8_t)0x03)
|
||||
#define ADC2_Channel_04_PA7 ((uint8_t)0x04)
|
||||
#define ADC2_Channel_05_PC4 ((uint8_t)0x05)
|
||||
#define ADC2_Channel_06_PC0 ((uint8_t)0x06)
|
||||
#define ADC2_Channel_07_PC1 ((uint8_t)0x07)
|
||||
#define ADC2_Channel_08_PC2 ((uint8_t)0x08)
|
||||
#define ADC2_Channel_09_PC3 ((uint8_t)0x09)
|
||||
#define ADC2_Channel_10_PF2 ((uint8_t)0x0A)
|
||||
#define ADC2_Channel_11_PA2 ((uint8_t)0x0B)
|
||||
#define ADC2_Channel_12_PC4 ((uint8_t)0x0C)
|
||||
#define ADC2_Channel_13_PB2 ((uint8_t)0x0D)
|
||||
|
||||
#define ADC3_Channel_01_PB11 ((uint8_t)0x01)
|
||||
#define ADC3_Channel_02_PE9 ((uint8_t)0x02)
|
||||
#define ADC3_Channel_03_PE13 ((uint8_t)0x03)
|
||||
#define ADC3_Channel_04_PE12 ((uint8_t)0x04)
|
||||
#define ADC3_Channel_05_PB13 ((uint8_t)0x05)
|
||||
#define ADC3_Channel_06_PE8 ((uint8_t)0x06)
|
||||
#define ADC3_Channel_07_PD10 ((uint8_t)0x07)
|
||||
#define ADC3_Channel_08_PD11 ((uint8_t)0x08)
|
||||
#define ADC3_Channel_09_PD12 ((uint8_t)0x09)
|
||||
#define ADC3_Channel_10_PD13 ((uint8_t)0x0A)
|
||||
#define ADC3_Channel_11_PD14 ((uint8_t)0x0B)
|
||||
#define ADC3_Channel_12_PB0 ((uint8_t)0x0C)
|
||||
#define ADC3_Channel_13_PE7 ((uint8_t)0x0D)
|
||||
#define ADC3_Channel_14_PE10 ((uint8_t)0x0E)
|
||||
#define ADC3_Channel_15_PE11 ((uint8_t)0x0F)
|
||||
|
||||
#define ADC4_Channel_01_PE14 ((uint8_t)0x01)
|
||||
#define ADC4_Channel_02_PE15 ((uint8_t)0x02)
|
||||
#define ADC4_Channel_03_PB12 ((uint8_t)0x03)
|
||||
#define ADC4_Channel_04_PB14 ((uint8_t)0x04)
|
||||
#define ADC4_Channel_05_PB15 ((uint8_t)0x05)
|
||||
#define ADC4_Channel_06_PE8 ((uint8_t)0x06)
|
||||
#define ADC4_Channel_07_PD10 ((uint8_t)0x07)
|
||||
#define ADC4_Channel_08_PD11 ((uint8_t)0x08)
|
||||
#define ADC4_Channel_09_PD12 ((uint8_t)0x09)
|
||||
#define ADC4_Channel_10_PD13 ((uint8_t)0x0A)
|
||||
#define ADC4_Channel_11_PD14 ((uint8_t)0x0B)
|
||||
#define ADC4_Channel_12_PD8 ((uint8_t)0x0C)
|
||||
#define ADC4_Channel_13_PD9 ((uint8_t)0x0D)
|
||||
|
||||
#define ADC_CH_0 ((uint8_t)0x00)
|
||||
#define ADC_CH_1 ((uint8_t)0x01)
|
||||
#define ADC_CH_2 ((uint8_t)0x02)
|
||||
#define ADC_CH_3 ((uint8_t)0x03)
|
||||
#define ADC_CH_4 ((uint8_t)0x04)
|
||||
#define ADC_CH_5 ((uint8_t)0x05)
|
||||
#define ADC_CH_6 ((uint8_t)0x06)
|
||||
#define ADC_CH_7 ((uint8_t)0x07)
|
||||
#define ADC_CH_8 ((uint8_t)0x08)
|
||||
#define ADC_CH_9 ((uint8_t)0x09)
|
||||
#define ADC_CH_10 ((uint8_t)0x0A)
|
||||
#define ADC_CH_11 ((uint8_t)0x0B)
|
||||
#define ADC_CH_12 ((uint8_t)0x0C)
|
||||
#define ADC_CH_13 ((uint8_t)0x0D)
|
||||
#define ADC_CH_14 ((uint8_t)0x0E)
|
||||
#define ADC_CH_15 ((uint8_t)0x0F)
|
||||
#define ADC_CH_16 ((uint8_t)0x10)
|
||||
#define ADC_CH_17 ((uint8_t)0x11)
|
||||
#define ADC_CH_18 ((uint8_t)0x12)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**@addtogroup ADC_dif_sel_ch_definition
|
||||
* @{
|
||||
*/
|
||||
#define aDC_DIFSEL_CHS_MASK ((uint32_t)0x0007FFFF)
|
||||
#define ADC_DIFSEL_CHS_0 ((uint32_t)0x00000001)
|
||||
#define ADC_DIFSEL_CHS_1 ((uint32_t)0x00000002)
|
||||
#define ADC_DIFSEL_CHS_2 ((uint32_t)0x00000004)
|
||||
#define ADC_DIFSEL_CHS_3 ((uint32_t)0x00000008)
|
||||
#define ADC_DIFSEL_CHS_4 ((uint32_t)0x00000010)
|
||||
#define ADC_DIFSEL_CHS_5 ((uint32_t)0x00000020)
|
||||
#define ADC_DIFSEL_CHS_6 ((uint32_t)0x00000040)
|
||||
#define ADC_DIFSEL_CHS_7 ((uint32_t)0x00000080)
|
||||
#define ADC_DIFSEL_CHS_8 ((uint32_t)0x00000100)
|
||||
#define ADC_DIFSEL_CHS_9 ((uint32_t)0x00000200)
|
||||
#define ADC_DIFSEL_CHS_10 ((uint32_t)0x00000400)
|
||||
#define ADC_DIFSEL_CHS_11 ((uint32_t)0x00000800)
|
||||
#define ADC_DIFSEL_CHS_12 ((uint32_t)0x00001000)
|
||||
#define ADC_DIFSEL_CHS_13 ((uint32_t)0x00002000)
|
||||
#define ADC_DIFSEL_CHS_14 ((uint32_t)0x00004000)
|
||||
#define ADC_DIFSEL_CHS_15 ((uint32_t)0x00008000)
|
||||
#define ADC_DIFSEL_CHS_16 ((uint32_t)0x00010000)
|
||||
#define ADC_DIFSEL_CHS_17 ((uint32_t)0x00020000)
|
||||
#define ADC_DIFSEL_CHS_18 ((uint32_t)0x00040000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**@addtogroup ADC_calfact_definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CALFACT_CALFACTD_MSK ((uint32_t)0x3FL << 16)
|
||||
#define ADC_CALFACT_CALFACTS_MSK ((uint32_t)0x3FL << 0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**@addtogroup ADC_ctrl3_definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CTRL3_VABTMEN_MSK ((uint32_t)0x01L << 11)
|
||||
#define ADC_CTRL3_DPWMOD_MSK ((uint32_t)0x01L << 10)
|
||||
#define ADC_CTRL3_JENDCAIEN_MSK ((uint32_t)0x01L << 9)
|
||||
#define ADC_CTRL3_ENDCAIEN_MSK ((uint32_t)0x01L << 8)
|
||||
#define ADC_CTRL3_BPCAL_MSK ((uint32_t)0x01L << 7)
|
||||
#define ADC_CTRL3_CKMOD_MSK ((uint32_t)0x01L << 4)
|
||||
#define ADC_CTRL3_CALALD_MSK ((uint32_t)0x01L << 3)
|
||||
#define ADC_CTRL3_CALDIF_MSK ((uint32_t)0x01L << 2)
|
||||
#define ADC_CTRL3_RES_MSK ((uint32_t)0x03L << 0)
|
||||
#define ADC_SAMPT3_SAMPSEL_MSK ((uint32_t)0x01L << 3)
|
||||
typedef enum
|
||||
{
|
||||
ADC_CTRL3_CKMOD_AHB = 0,
|
||||
ADC_CTRL3_CKMOD_PLL = 1,
|
||||
} ADC_CTRL3_CKMOD;
|
||||
typedef enum
|
||||
{
|
||||
ADC_CTRL3_RES_12BIT = 0,
|
||||
ADC_CTRL3_RES_10BIT = 1,
|
||||
ADC_CTRL3_RES_8BIT = 2,
|
||||
ADC_CTRL3_RES_6BIT = 3,
|
||||
} ADC_CTRL3_RES;
|
||||
typedef struct
|
||||
{
|
||||
FunctionalState VabtMinitEn;
|
||||
FunctionalState DeepPowerModEn;
|
||||
FunctionalState JendcIntEn;
|
||||
FunctionalState EndcIntEn;
|
||||
ADC_CTRL3_CKMOD ClkMode;
|
||||
FunctionalState CalAtuoLoadEn;
|
||||
bool DifModCal;
|
||||
ADC_CTRL3_RES ResBit;
|
||||
bool Samp303Style;
|
||||
} ADC_InitTypeEx;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/*ADC_SAMPT3 only have samp time and smp18[2:0],samp18 is refint ch, change to row function*/
|
||||
/*ADC_IPTST reseverd register ,not to do it*/
|
||||
|
||||
/**@addtogroup ADC_bit_num_definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_RST_BIT_12 ((uint32_t)0x00)
|
||||
#define ADC_RST_BIT_10 ((uint32_t)0x01)
|
||||
#define ADC_RST_BIT_8 ((uint32_t)0x02)
|
||||
#define ADC_RESULT_BIT_6 ((uint32_t)0x03)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_flags_ex_definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_FLAG_RDY ((uint8_t)0x20)
|
||||
#define ADC_FLAG_PD_RDY ((uint8_t)0x40)
|
||||
#define IS_ADC_GET_READY(FLAG) (((FLAG) == ADC_FLAG_RDY) || ((FLAG) == ADC_FLAG_PD_RDY)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void ADC_DeInit(ADC_Module* ADCx);
|
||||
void ADC_Init(ADC_Module* ADCx, ADC_InitType* ADC_InitStruct);
|
||||
void ADC_InitStruct(ADC_InitType* ADC_InitStruct);
|
||||
void ADC_Enable(ADC_Module* ADCx, FunctionalState Cmd);
|
||||
void ADC_EnableDMA(ADC_Module* ADCx, FunctionalState Cmd);
|
||||
void ADC_ConfigInt(ADC_Module* ADCx, uint16_t ADC_IT, FunctionalState Cmd);
|
||||
void ADC_ResetCalibration(ADC_Module* ADCx);
|
||||
FlagStatus ADC_GetResetCalibrationStatus(ADC_Module* ADCx);
|
||||
void ADC_StartCalibration(ADC_Module* ADCx);
|
||||
FlagStatus ADC_GetCalibrationStatus(ADC_Module* ADCx);
|
||||
void ADC_EnableSoftwareStartConv(ADC_Module* ADCx, FunctionalState Cmd);
|
||||
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_Module* ADCx);
|
||||
void ADC_ConfigDiscModeChannelCount(ADC_Module* ADCx, uint8_t Number);
|
||||
void ADC_EnableDiscMode(ADC_Module* ADCx, FunctionalState Cmd);
|
||||
void ADC_ConfigRegularChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_EnableExternalTrigConv(ADC_Module* ADCx, FunctionalState Cmd);
|
||||
uint16_t ADC_GetDat(ADC_Module* ADCx);
|
||||
uint32_t ADC_GetDualModeConversionDat(void);
|
||||
void ADC_EnableAutoInjectedConv(ADC_Module* ADCx, FunctionalState Cmd);
|
||||
void ADC_EnableInjectedDiscMode(ADC_Module* ADCx, FunctionalState Cmd);
|
||||
void ADC_ConfigExternalTrigInjectedConv(ADC_Module* ADCx, uint32_t ADC_ExternalTrigInjecConv);
|
||||
void ADC_EnableExternalTrigInjectedConv(ADC_Module* ADCx, FunctionalState Cmd);
|
||||
void ADC_EnableSoftwareStartInjectedConv(ADC_Module* ADCx, FunctionalState Cmd);
|
||||
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_Module* ADCx);
|
||||
void ADC_ConfigInjectedChannel(ADC_Module* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_ConfigInjectedSequencerLength(ADC_Module* ADCx, uint8_t Length);
|
||||
void ADC_SetInjectedOffsetDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
|
||||
uint16_t ADC_GetInjectedConversionDat(ADC_Module* ADCx, uint8_t ADC_InjectedChannel);
|
||||
void ADC_ConfigAnalogWatchdogWorkChannelType(ADC_Module* ADCx, uint32_t ADC_AnalogWatchdog);
|
||||
void ADC_ConfigAnalogWatchdogThresholds(ADC_Module* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
|
||||
void ADC_ConfigAnalogWatchdogSingleChannel(ADC_Module* ADCx, uint8_t ADC_Channel);
|
||||
void ADC_EnableTempSensorVrefint(FunctionalState Cmd);
|
||||
FlagStatus ADC_GetFlagStatus(ADC_Module* ADCx, uint8_t ADC_FLAG);
|
||||
void ADC_ClearFlag(ADC_Module* ADCx, uint8_t ADC_FLAG);
|
||||
INTStatus ADC_GetIntStatus(ADC_Module* ADCx, uint16_t ADC_IT);
|
||||
void ADC_ClearIntPendingBit(ADC_Module* ADCx, uint16_t ADC_IT);
|
||||
|
||||
void ADC_InitEx(ADC_Module* ADCx, ADC_InitTypeEx* ADC_InitStructEx);
|
||||
FlagStatus ADC_GetFlagStatusNew(ADC_Module* ADCx, uint8_t ADC_FLAG_NEW);
|
||||
void ADC_SetBypassCalibration(ADC_Module* ADCx, FunctionalState en);
|
||||
void ADC_SetConvResultBitNum(ADC_Module* ADCx, uint32_t ResultBitNum);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__N32G45X_ADC_H__ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,199 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_bkp.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_BKP_H__
|
||||
#define __N32G45X_BKP_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup BKP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup BKP_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup BKP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Tamper_Pin_active_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BKP_TP_HIGH ((uint16_t)0x0000)
|
||||
#define BKP_TP_LOW ((uint16_t)0x0001)
|
||||
#define IS_BKP_TP_LEVEL(LEVEL) (((LEVEL) == BKP_TP_HIGH) || ((LEVEL) == BKP_TP_LOW))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_output_source_to_output_on_the_Tamper_pin
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BKP_RTCOUTPUT_NONE ((uint16_t)0x0000)
|
||||
#define BKP_RTCOUTPUT_CALCLK ((uint16_t)0x0080)
|
||||
#define BKP_RTCOUTPUT_ALARM ((uint16_t)0x0100)
|
||||
#define BKP_RTCOUTPUT_SECOND ((uint16_t)0x0300)
|
||||
#define IS_BKP_RTC_RTCOUTPUT(SOURCE) \
|
||||
(((SOURCE) == BKP_RTCOUTPUT_NONE) || ((SOURCE) == BKP_RTCOUTPUT_CALCLK) || ((SOURCE) == BKP_RTCOUTPUT_ALARM) \
|
||||
|| ((SOURCE) == BKP_RTCOUTPUT_SECOND))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Data_Backup_Register
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BKP_DAT1 ((uint16_t)0x0004)
|
||||
#define BKP_DAT2 ((uint16_t)0x0008)
|
||||
#define BKP_DAT3 ((uint16_t)0x000C)
|
||||
#define BKP_DAT4 ((uint16_t)0x0010)
|
||||
#define BKP_DAT5 ((uint16_t)0x0014)
|
||||
#define BKP_DAT6 ((uint16_t)0x0018)
|
||||
#define BKP_DAT7 ((uint16_t)0x001C)
|
||||
#define BKP_DAT8 ((uint16_t)0x0020)
|
||||
#define BKP_DAT9 ((uint16_t)0x0024)
|
||||
#define BKP_DAT10 ((uint16_t)0x0028)
|
||||
#define BKP_DAT11 ((uint16_t)0x0040)
|
||||
#define BKP_DAT12 ((uint16_t)0x0044)
|
||||
#define BKP_DAT13 ((uint16_t)0x0048)
|
||||
#define BKP_DAT14 ((uint16_t)0x004C)
|
||||
#define BKP_DAT15 ((uint16_t)0x0050)
|
||||
#define BKP_DAT16 ((uint16_t)0x0054)
|
||||
#define BKP_DAT17 ((uint16_t)0x0058)
|
||||
#define BKP_DAT18 ((uint16_t)0x005C)
|
||||
#define BKP_DAT19 ((uint16_t)0x0060)
|
||||
#define BKP_DAT20 ((uint16_t)0x0064)
|
||||
#define BKP_DAT21 ((uint16_t)0x0068)
|
||||
#define BKP_DAT22 ((uint16_t)0x006C)
|
||||
#define BKP_DAT23 ((uint16_t)0x0070)
|
||||
#define BKP_DAT24 ((uint16_t)0x0074)
|
||||
#define BKP_DAT25 ((uint16_t)0x0078)
|
||||
#define BKP_DAT26 ((uint16_t)0x007C)
|
||||
#define BKP_DAT27 ((uint16_t)0x0080)
|
||||
#define BKP_DAT28 ((uint16_t)0x0084)
|
||||
#define BKP_DAT29 ((uint16_t)0x0088)
|
||||
#define BKP_DAT30 ((uint16_t)0x008C)
|
||||
#define BKP_DAT31 ((uint16_t)0x0090)
|
||||
#define BKP_DAT32 ((uint16_t)0x0094)
|
||||
#define BKP_DAT33 ((uint16_t)0x0098)
|
||||
#define BKP_DAT34 ((uint16_t)0x009C)
|
||||
#define BKP_DAT35 ((uint16_t)0x00A0)
|
||||
#define BKP_DAT36 ((uint16_t)0x00A4)
|
||||
#define BKP_DAT37 ((uint16_t)0x00A8)
|
||||
#define BKP_DAT38 ((uint16_t)0x00AC)
|
||||
#define BKP_DAT39 ((uint16_t)0x00B0)
|
||||
#define BKP_DAT40 ((uint16_t)0x00B4)
|
||||
#define BKP_DAT41 ((uint16_t)0x00B8)
|
||||
#define BKP_DAT42 ((uint16_t)0x00BC)
|
||||
|
||||
#define IS_BKP_DAT(DAT) \
|
||||
(((DAT) == BKP_DAT1) || ((DAT) == BKP_DAT2) || ((DAT) == BKP_DAT3) || ((DAT) == BKP_DAT4) || ((DAT) == BKP_DAT5) \
|
||||
|| ((DAT) == BKP_DAT6) || ((DAT) == BKP_DAT7) || ((DAT) == BKP_DAT8) || ((DAT) == BKP_DAT9) \
|
||||
|| ((DAT) == BKP_DAT10) || ((DAT) == BKP_DAT11) || ((DAT) == BKP_DAT12) || ((DAT) == BKP_DAT13) \
|
||||
|| ((DAT) == BKP_DAT14) || ((DAT) == BKP_DAT15) || ((DAT) == BKP_DAT16) || ((DAT) == BKP_DAT17) \
|
||||
|| ((DAT) == BKP_DAT18) || ((DAT) == BKP_DAT19) || ((DAT) == BKP_DAT20) || ((DAT) == BKP_DAT21) \
|
||||
|| ((DAT) == BKP_DAT22) || ((DAT) == BKP_DAT23) || ((DAT) == BKP_DAT24) || ((DAT) == BKP_DAT25) \
|
||||
|| ((DAT) == BKP_DAT26) || ((DAT) == BKP_DAT27) || ((DAT) == BKP_DAT28) || ((DAT) == BKP_DAT29) \
|
||||
|| ((DAT) == BKP_DAT30) || ((DAT) == BKP_DAT31) || ((DAT) == BKP_DAT32) || ((DAT) == BKP_DAT33) \
|
||||
|| ((DAT) == BKP_DAT34) || ((DAT) == BKP_DAT35) || ((DAT) == BKP_DAT36) || ((DAT) == BKP_DAT37) \
|
||||
|| ((DAT) == BKP_DAT38) || ((DAT) == BKP_DAT39) || ((DAT) == BKP_DAT40) || ((DAT) == BKP_DAT41) \
|
||||
|| ((DAT) == BKP_DAT42))
|
||||
|
||||
#define IS_BKP_CAL_VALUE(VALUE) ((VALUE) <= 0x7F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup BKP_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup BKP_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void BKP_DeInit(void);
|
||||
void BKP_ConfigTPLevel(uint16_t BKP_TamperPinLevel);
|
||||
void BKP_TPEnable(FunctionalState Cmd);
|
||||
void BKP_TPIntEnable(FunctionalState Cmd);
|
||||
void BKP_ConfigRtcOutput(uint16_t BKP_RTCOutputSource);
|
||||
void BKP_SetRtcCalValue(uint8_t CalibrationValue);
|
||||
void BKP_WriteBkpData(uint16_t BKP_DAT, uint16_t Data);
|
||||
uint16_t BKP_ReadBkpData(uint16_t BKP_DAT);
|
||||
FlagStatus BKP_GetTEFlag(void);
|
||||
void BKP_ClrTEFlag(void);
|
||||
INTStatus BKP_GetTINTFlag(void);
|
||||
void BKP_ClrTINTFlag(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __N32G45X_BKP_H__ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,671 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_can.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_CAN_H__
|
||||
#define __N32G45X_CAN_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || ((PERIPH) == CAN2))
|
||||
|
||||
/**
|
||||
* @brief CAN init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t BaudRatePrescaler; /*!< Specifies the length of a time quantum.
|
||||
It ranges from 1 to 1024. */
|
||||
|
||||
uint8_t OperatingMode; /*!< Specifies the CAN operating mode.
|
||||
This parameter can be a value of
|
||||
@ref CAN_operating_mode */
|
||||
|
||||
uint8_t RSJW; /*!< Specifies the maximum number of time quanta
|
||||
the CAN hardware is allowed to lengthen or
|
||||
shorten a bit to perform resynchronization.
|
||||
This parameter can be a value of
|
||||
@ref CAN_synchronisation_jump_width */
|
||||
|
||||
uint8_t TBS1; /*!< Specifies the number of time quanta in Bit
|
||||
Segment 1. This parameter can be a value of
|
||||
@ref CAN_time_quantum_in_bit_segment_1 */
|
||||
|
||||
uint8_t TBS2; /*!< Specifies the number of time quanta in Bit
|
||||
Segment 2.
|
||||
This parameter can be a value of
|
||||
@ref CAN_time_quantum_in_bit_segment_2 */
|
||||
|
||||
FunctionalState TTCM; /*!< Enable or disable the time triggered
|
||||
communication mode. This parameter can be set
|
||||
either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState ABOM; /*!< Enable or disable the automatic bus-off
|
||||
management. This parameter can be set either
|
||||
to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState AWKUM; /*!< Enable or disable the automatic wake-up mode.
|
||||
This parameter can be set either to ENABLE or
|
||||
DISABLE. */
|
||||
|
||||
FunctionalState NART; /*!< Enable or disable the no-automatic
|
||||
retransmission mode. This parameter can be
|
||||
set either to ENABLE or DISABLE. */
|
||||
|
||||
FunctionalState RFLM; /*!< Enable or disable the Receive DATFIFO Locked mode.
|
||||
This parameter can be set either to ENABLE
|
||||
or DISABLE. */
|
||||
|
||||
FunctionalState TXFP; /*!< Enable or disable the transmit DATFIFO priority.
|
||||
This parameter can be set either to ENABLE
|
||||
or DISABLE. */
|
||||
} CAN_InitType;
|
||||
|
||||
/**
|
||||
* @brief CAN filter init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t Filter_HighId; /*!< Specifies the filter identification number (MSBs for a 32-bit
|
||||
configuration, first one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t Filter_LowId; /*!< Specifies the filter identification number (LSBs for a 32-bit
|
||||
configuration, second one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t FilterMask_HighId; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (MSBs for a 32-bit configuration,
|
||||
first one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t FilterMask_LowId; /*!< Specifies the filter mask number or identification number,
|
||||
according to the mode (LSBs for a 32-bit configuration,
|
||||
second one for a 16-bit configuration).
|
||||
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t Filter_FIFOAssignment; /*!< Specifies the DATFIFO (0 or 1) which will be assigned to the filter.
|
||||
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||
|
||||
uint8_t Filter_Num; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
|
||||
|
||||
uint8_t Filter_Mode; /*!< Specifies the filter mode to be initialized.
|
||||
This parameter can be a value of @ref CAN_filter_mode */
|
||||
|
||||
uint8_t Filter_Scale; /*!< Specifies the filter scale.
|
||||
This parameter can be a value of @ref CAN_filter_scale */
|
||||
|
||||
FunctionalState Filter_Act; /*!< Enable or disable the filter.
|
||||
This parameter can be set either to ENABLE or DISABLE. */
|
||||
} CAN_FilterInitType;
|
||||
|
||||
/**
|
||||
* @brief CAN Tx message structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||
will be transmitted. This parameter can be a value
|
||||
of @ref CAN_identifier_type */
|
||||
|
||||
uint8_t RTR; /*!< Specifies the type of frame for the message that will
|
||||
be transmitted. This parameter can be a value of
|
||||
@ref CAN_remote_transmission_request */
|
||||
|
||||
uint8_t DLC; /*!< Specifies the length of the frame that will be
|
||||
transmitted. This parameter can be a value between
|
||||
0 to 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
|
||||
to 0xFF. */
|
||||
} CanTxMessage;
|
||||
|
||||
/**
|
||||
* @brief CAN Rx message structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StdId; /*!< Specifies the standard identifier.
|
||||
This parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t ExtId; /*!< Specifies the extended identifier.
|
||||
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
uint8_t IDE; /*!< Specifies the type of identifier for the message that
|
||||
will be received. This parameter can be a value of
|
||||
@ref CAN_identifier_type */
|
||||
|
||||
uint8_t RTR; /*!< Specifies the type of frame for the received message.
|
||||
This parameter can be a value of
|
||||
@ref CAN_remote_transmission_request */
|
||||
|
||||
uint8_t DLC; /*!< Specifies the length of the frame that will be received.
|
||||
This parameter can be a value between 0 to 8 */
|
||||
|
||||
uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
|
||||
0xFF. */
|
||||
|
||||
uint8_t FMI; /*!< Specifies the index of the filter the message stored in
|
||||
the mailbox passes through. This parameter can be a
|
||||
value between 0 to 0xFF */
|
||||
} CanRxMessage;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_sleep_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_InitSTS_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
|
||||
#define CAN_InitSTS_Success ((uint8_t)0x01) /*!< CAN initialization OK */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup OperatingMode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Normal_Mode ((uint8_t)0x00) /*!< normal mode */
|
||||
#define CAN_LoopBack_Mode ((uint8_t)0x01) /*!< loopback mode */
|
||||
#define CAN_Silent_Mode ((uint8_t)0x02) /*!< silent mode */
|
||||
#define CAN_Silent_LoopBack_Mode ((uint8_t)0x03) /*!< loopback combined with silent mode */
|
||||
|
||||
#define IS_CAN_MODE(MODE) \
|
||||
(((MODE) == CAN_Normal_Mode) || ((MODE) == CAN_LoopBack_Mode) || ((MODE) == CAN_Silent_Mode) \
|
||||
|| ((MODE) == CAN_Silent_LoopBack_Mode))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup CAN_operating_mode
|
||||
* @{
|
||||
*/
|
||||
#define CAN_Operating_InitMode ((uint8_t)0x00) /*!< Initialization mode */
|
||||
#define CAN_Operating_NormalMode ((uint8_t)0x01) /*!< Normal mode */
|
||||
#define CAN_Operating_SleepMode ((uint8_t)0x02) /*!< sleep mode */
|
||||
|
||||
#define IS_CAN_OPERATING_MODE(MODE) \
|
||||
(((MODE) == CAN_Operating_InitMode) || ((MODE) == CAN_Operating_NormalMode) || ((MODE) == CAN_Operating_SleepMode))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup CAN_Mode_Status
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_ModeSTS_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
|
||||
#define CAN_ModeSTS_Success ((uint8_t)!CAN_ModeSTS_Failed) /*!< CAN entering the specific mode Succeed */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_synchronisation_jump_width
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_RSJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_RSJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_RSJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_RSJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
|
||||
#define IS_CAN_RSJW(SJW) \
|
||||
(((SJW) == CAN_RSJW_1tq) || ((SJW) == CAN_RSJW_2tq) || ((SJW) == CAN_RSJW_3tq) || ((SJW) == CAN_RSJW_4tq))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_time_quantum_in_bit_segment_1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_TBS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_TBS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_TBS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_TBS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
#define CAN_TBS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
|
||||
#define CAN_TBS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
|
||||
#define CAN_TBS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
|
||||
#define CAN_TBS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
|
||||
#define CAN_TBS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
|
||||
#define CAN_TBS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
|
||||
#define CAN_TBS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
|
||||
#define CAN_TBS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
|
||||
#define CAN_TBS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
|
||||
#define CAN_TBS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
|
||||
#define CAN_TBS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
|
||||
#define CAN_TBS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
|
||||
|
||||
#define IS_CAN_TBS1(BS1) ((BS1) <= CAN_TBS1_16tq)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_time_quantum_in_bit_segment_2
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_TBS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
|
||||
#define CAN_TBS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
|
||||
#define CAN_TBS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
|
||||
#define CAN_TBS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
|
||||
#define CAN_TBS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
|
||||
#define CAN_TBS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
|
||||
#define CAN_TBS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
|
||||
#define CAN_TBS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
|
||||
|
||||
#define IS_CAN_TBS2(BS2) ((BS2) <= CAN_TBS2_8tq)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_clock_prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CAN_BAUDRATEPRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_filter_number
|
||||
* @{
|
||||
*/
|
||||
#define IS_CAN_FILTER_NUM(NUMBER) ((NUMBER) <= 13)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_filter_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Filter_IdMaskMode ((uint8_t)0x00) /*!< identifier/mask mode */
|
||||
#define CAN_Filter_IdListMode ((uint8_t)0x01) /*!< identifier list mode */
|
||||
|
||||
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_Filter_IdMaskMode) || ((MODE) == CAN_Filter_IdListMode))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_filter_scale
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Filter_16bitScale ((uint8_t)0x00) /*!< Two 16-bit filters */
|
||||
#define CAN_Filter_32bitScale ((uint8_t)0x01) /*!< One 32-bit filter */
|
||||
|
||||
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_Filter_16bitScale) || ((SCALE) == CAN_Filter_32bitScale))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_filter_FIFO
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter DATFIFO 0 assignment for filter x */
|
||||
#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter DATFIFO 1 assignment for filter x */
|
||||
#define IS_CAN_FILTER_FIFO(DATFIFO) (((DATFIFO) == CAN_FilterFIFO0) || ((DATFIFO) == CAN_FilterFIFO1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Tx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
|
||||
#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
|
||||
#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
|
||||
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_identifier_type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_Standard_Id ((uint32_t)0x00000000) /*!< Standard Id */
|
||||
#define CAN_Extended_Id ((uint32_t)0x00000004) /*!< Extended Id */
|
||||
#define IS_CAN_ID(IDTYPE) (((IDTYPE) == CAN_Standard_Id) || ((IDTYPE) == CAN_Extended_Id))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_remote_transmission_request
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_RTRQ_Data ((uint32_t)0x00000000) /*!< Data frame */
|
||||
#define CAN_RTRQ_Remote ((uint32_t)0x00000002) /*!< Remote frame */
|
||||
#define IS_CAN_RTRQ(RTR) (((RTR) == CAN_RTRQ_Data) || ((RTR) == CAN_RTRQ_Remote))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_transmit_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_TxSTS_Failed ((uint8_t)0x00) /*!< CAN transmission failed */
|
||||
#define CAN_TxSTS_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
|
||||
#define CAN_TxSTS_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
|
||||
#define CAN_TxSTS_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_receive_FIFO_number_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN DATFIFO 0 used to receive */
|
||||
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN DATFIFO 1 used to receive */
|
||||
|
||||
#define IS_CAN_FIFO(DATFIFO) (((DATFIFO) == CAN_FIFO0) || ((DATFIFO) == CAN_FIFO1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_sleep_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_SLEEP_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
|
||||
#define CAN_SLEEP_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_wake_up_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_WKU_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
|
||||
#define CAN_WKU_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup CAN_Error_Code_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_ERRCode_NoErr ((uint8_t)0x00) /*!< No Error */
|
||||
#define CAN_ERRCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
|
||||
#define CAN_ERRCode_FormErr ((uint8_t)0x20) /*!< Form Error */
|
||||
#define CAN_ERRCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
|
||||
#define CAN_ERRCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
|
||||
#define CAN_ERRCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
|
||||
#define CAN_ERRCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
|
||||
#define CAN_ERRCode_SWSetErr ((uint8_t)0x70) /*!< Software Set Error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_flags
|
||||
* @{
|
||||
*/
|
||||
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagSTS()
|
||||
and CAN_ClearFlag() functions. */
|
||||
/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagSTS() function. */
|
||||
|
||||
/* Transmit Flags */
|
||||
#define CAN_FLAG_RQCPM0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
|
||||
#define CAN_FLAG_RQCPM1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
|
||||
#define CAN_FLAG_RQCPM2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
|
||||
|
||||
/* Receive Flags */
|
||||
#define CAN_FLAG_FFMP0 ((uint32_t)0x12000003) /*!< DATFIFO 0 Message Pending Flag */
|
||||
#define CAN_FLAG_FFULL0 ((uint32_t)0x32000008) /*!< DATFIFO 0 Full Flag */
|
||||
#define CAN_FLAG_FFOVR0 ((uint32_t)0x32000010) /*!< DATFIFO 0 Overrun Flag */
|
||||
#define CAN_FLAG_FFMP1 ((uint32_t)0x14000003) /*!< DATFIFO 1 Message Pending Flag */
|
||||
#define CAN_FLAG_FFULL1 ((uint32_t)0x34000008) /*!< DATFIFO 1 Full Flag */
|
||||
#define CAN_FLAG_FFOVR1 ((uint32_t)0x34000010) /*!< DATFIFO 1 Overrun Flag */
|
||||
|
||||
/* Operating Mode Flags */
|
||||
#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
|
||||
#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
|
||||
/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
||||
In this case the SLAK bit can be polled.*/
|
||||
|
||||
/* Error Flags */
|
||||
#define CAN_FLAG_EWGFL ((uint32_t)0x10F00001) /*!< Error Warning Flag */
|
||||
#define CAN_FLAG_EPVFL ((uint32_t)0x10F00002) /*!< Error Passive Flag */
|
||||
#define CAN_FLAG_BOFFL ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
|
||||
#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
|
||||
|
||||
#define IS_CAN_GET_FLAG(FLAG) \
|
||||
(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOFFL) || ((FLAG) == CAN_FLAG_EPVFL) \
|
||||
|| ((FLAG) == CAN_FLAG_EWGFL) || ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FFOVR0) \
|
||||
|| ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFMP0) || ((FLAG) == CAN_FLAG_FFOVR1) \
|
||||
|| ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFMP1) || ((FLAG) == CAN_FLAG_RQCPM2) \
|
||||
|| ((FLAG) == CAN_FLAG_RQCPM1) || ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_SLAK))
|
||||
|
||||
#define IS_CAN_CLEAR_FLAG(FLAG) \
|
||||
(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCPM2) || ((FLAG) == CAN_FLAG_RQCPM1) \
|
||||
|| ((FLAG) == CAN_FLAG_RQCPM0) || ((FLAG) == CAN_FLAG_FFULL0) || ((FLAG) == CAN_FLAG_FFOVR0) \
|
||||
|| ((FLAG) == CAN_FLAG_FFULL1) || ((FLAG) == CAN_FLAG_FFOVR1) || ((FLAG) == CAN_FLAG_WKU) \
|
||||
|| ((FLAG) == CAN_FLAG_SLAK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_INT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
|
||||
|
||||
/* Receive Interrupts */
|
||||
#define CAN_INT_FMP0 ((uint32_t)0x00000002) /*!< DATFIFO 0 message pending Interrupt*/
|
||||
#define CAN_INT_FF0 ((uint32_t)0x00000004) /*!< DATFIFO 0 full Interrupt*/
|
||||
#define CAN_INT_FOV0 ((uint32_t)0x00000008) /*!< DATFIFO 0 overrun Interrupt*/
|
||||
#define CAN_INT_FMP1 ((uint32_t)0x00000010) /*!< DATFIFO 1 message pending Interrupt*/
|
||||
#define CAN_INT_FF1 ((uint32_t)0x00000020) /*!< DATFIFO 1 full Interrupt*/
|
||||
#define CAN_INT_FOV1 ((uint32_t)0x00000040) /*!< DATFIFO 1 overrun Interrupt*/
|
||||
|
||||
/* Operating Mode Interrupts */
|
||||
#define CAN_INT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
|
||||
#define CAN_INT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
|
||||
|
||||
/* Error Interrupts */
|
||||
#define CAN_INT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
|
||||
#define CAN_INT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
|
||||
#define CAN_INT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
|
||||
#define CAN_INT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
|
||||
#define CAN_INT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
|
||||
|
||||
/* Flags named as Interrupts : kept only for FW compatibility */
|
||||
#define CAN_INT_RQCPM0 CAN_INT_TME
|
||||
#define CAN_INT_RQCPM1 CAN_INT_TME
|
||||
#define CAN_INT_RQCPM2 CAN_INT_TME
|
||||
|
||||
#define IS_CAN_INT(IT) \
|
||||
(((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FMP0) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) \
|
||||
|| ((IT) == CAN_INT_FMP1) || ((IT) == CAN_INT_FF1) || ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) \
|
||||
|| ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) || ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) \
|
||||
|| ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK))
|
||||
|
||||
#define IS_CAN_CLEAR_INT(IT) \
|
||||
(((IT) == CAN_INT_TME) || ((IT) == CAN_INT_FF0) || ((IT) == CAN_INT_FOV0) || ((IT) == CAN_INT_FF1) \
|
||||
|| ((IT) == CAN_INT_FOV1) || ((IT) == CAN_INT_EWG) || ((IT) == CAN_INT_EPV) || ((IT) == CAN_INT_BOF) \
|
||||
|| ((IT) == CAN_INT_LEC) || ((IT) == CAN_INT_ERR) || ((IT) == CAN_INT_WKU) || ((IT) == CAN_INT_SLK))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Legacy
|
||||
* @{
|
||||
*/
|
||||
#define CANINITSTSFAILED CAN_InitSTS_Failed
|
||||
#define CANINITSTSOK CAN_InitSTS_Success
|
||||
#define CAN_FilterFIFO0 CAN_Filter_FIFO0
|
||||
#define CAN_FilterFIFO1 CAN_Filter_FIFO1
|
||||
#define CAN_ID_STD CAN_Standard_Id
|
||||
#define CAN_ID_EXT CAN_Extended_Id
|
||||
#define CAN_RTRQ_DATA CAN_RTRQ_Data
|
||||
#define CAN_RTRQ_REMOTE CAN_RTRQ_Remote
|
||||
#define CANTXSTSFAILE CAN_TxSTS_Failed
|
||||
#define CANTXSTSOK CAN_TxSTS_Ok
|
||||
#define CANTXSTSPENDING CAN_TxSTS_Pending
|
||||
#define CAN_STS_NO_MB CAN_TxSTS_NoMailBox
|
||||
#define CANSLEEPFAILED CAN_SLEEP_Failed
|
||||
#define CANSLEEPOK CAN_SLEEP_Ok
|
||||
#define CANWKUFAILED CAN_WKU_Failed
|
||||
#define CANWKUOK CAN_WKU_Ok
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/* Function used to set the CAN configuration to the default reset state *****/
|
||||
void CAN_DeInit(CAN_Module* CANx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
uint8_t CAN_Init(CAN_Module* CANx, CAN_InitType* CAN_InitParam);
|
||||
void CAN1_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct);
|
||||
void CAN2_InitFilter(CAN_FilterInitType* CAN_InitFilterStruct);
|
||||
void CAN_InitStruct(CAN_InitType* CAN_InitParam);
|
||||
void CAN_DebugFreeze(CAN_Module* CANx, FunctionalState Cmd);
|
||||
void CAN_EnTTComMode(CAN_Module* CANx, FunctionalState Cmd);
|
||||
|
||||
/* Transmit functions *********************************************************/
|
||||
uint8_t CAN_TransmitMessage(CAN_Module* CANx, CanTxMessage* TxMessage);
|
||||
uint8_t CAN_TransmitSTS(CAN_Module* CANx, uint8_t TransmitMailbox);
|
||||
void CAN_CancelTransmitMessage(CAN_Module* CANx, uint8_t Mailbox);
|
||||
|
||||
/* Receive functions **********************************************************/
|
||||
void CAN_ReceiveMessage(CAN_Module* CANx, uint8_t FIFONum, CanRxMessage* RxMessage);
|
||||
void CAN_ReleaseFIFO(CAN_Module* CANx, uint8_t FIFONum);
|
||||
uint8_t CAN_PendingMessage(CAN_Module* CANx, uint8_t FIFONum);
|
||||
|
||||
/* Operation modes functions **************************************************/
|
||||
uint8_t CAN_OperatingModeReq(CAN_Module* CANx, uint8_t CAN_OperatingMode);
|
||||
uint8_t CAN_EnterSleep(CAN_Module* CANx);
|
||||
uint8_t CAN_WakeUp(CAN_Module* CANx);
|
||||
|
||||
/* Error management functions *************************************************/
|
||||
uint8_t CAN_GetLastErrCode(CAN_Module* CANx);
|
||||
uint8_t CAN_GetReceiveErrCounter(CAN_Module* CANx);
|
||||
uint8_t CAN_GetLSBTransmitErrCounter(CAN_Module* CANx);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void CAN_INTConfig(CAN_Module* CANx, uint32_t CAN_INT, FunctionalState Cmd);
|
||||
FlagStatus CAN_GetFlagSTS(CAN_Module* CANx, uint32_t CAN_FLAG);
|
||||
void CAN_ClearFlag(CAN_Module* CANx, uint32_t CAN_FLAG);
|
||||
INTStatus CAN_GetIntStatus(CAN_Module* CANx, uint32_t CAN_INT);
|
||||
void CAN_ClearINTPendingBit(CAN_Module* CANx, uint32_t CAN_INT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __N32G45X_CAN_H__ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,365 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_comp.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_COMP_H__
|
||||
#define __N32G45X_COMP_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
#include <stdbool.h>
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
COMP1 = 0,
|
||||
COMP2 = 1,
|
||||
COMP3 = 2,
|
||||
COMP4 = 3,
|
||||
COMP5 = 4,
|
||||
COMP6 = 5,
|
||||
COMP7 = 6
|
||||
} COMPX;
|
||||
|
||||
// COMPx_CTRL
|
||||
#define COMP1_CTRL_INPDAC_MASK (0x01L << 18)
|
||||
#define COMP_CTRL_OUT_MASK (0x01L << 17)
|
||||
#define COMP_CTRL_BLKING_MASK (0x03L << 14)
|
||||
typedef enum
|
||||
{
|
||||
COMP_CTRL_BLKING_NO = (0x0L << 14),
|
||||
COMP_CTRL_BLKING_TIM1_OC5 = (0x1L << 14),
|
||||
COMP_CTRL_BLKING_TIM8_OC5 = (0x2L << 14),
|
||||
} COMP_CTRL_BLKING;
|
||||
#define COMPx_CTRL_HYST_MASK (0x03L << 12)
|
||||
typedef enum
|
||||
{
|
||||
COMP_CTRL_HYST_NO = (0x0L << 12),
|
||||
COMP_CTRL_HYST_LOW = (0x1L << 12),
|
||||
COMP_CTRL_HYST_MID = (0x2L << 12),
|
||||
COMP_CTRL_HYST_HIGH = (0x3L << 12),
|
||||
} COMP_CTRL_HYST;
|
||||
|
||||
#define COMP_POL_MASK (0x01L << 11)
|
||||
#define COMP_CTRL_OUTSEL_MASK (0x0FL << 7)
|
||||
typedef enum
|
||||
{
|
||||
COMPX_CTRL_OUTSEL_NC = (0x0L << 7),
|
||||
// comp1 out trig
|
||||
COMP1_CTRL_OUTSEL_NC = (0x0L << 7),
|
||||
COMP1_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7),
|
||||
COMP1_CTRL_OUTSEL_TIM1_IC1 = (0x2L << 7),
|
||||
COMP1_CTRL_OUTSEL_TIM1_OCrefclear = (0x3L << 7),
|
||||
COMP1_CTRL_OUTSEL_TIM2_IC1 = (0x4L << 7),
|
||||
COMP1_CTRL_OUTSEL_TIM2_OCrefclear = (0x5L << 7),
|
||||
COMP1_CTRL_OUTSEL_TIM3_IC1 = (0x6L << 7),
|
||||
COMP1_CTRL_OUTSEL_TIM3_OCrefclear = (0x7L << 7),
|
||||
COMP1_CTRL_OUTSEL_TIM4_IC1 = (0x8L << 7),
|
||||
COMP1_CTRL_OUTSEL_TIM4_OCrefclear = (0x9L << 7),
|
||||
COMP1_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7),
|
||||
COMP1_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7),
|
||||
// comp2 out trig
|
||||
COMP2_CTRL_OUTSEL_NC = (0x0L << 7),
|
||||
COMP2_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7),
|
||||
COMP2_CTRL_OUTSEL_TIM1_IC1 = (0x2L << 7),
|
||||
COMP2_CTRL_OUTSEL_TIM1_OCrefclear = (0x3L << 7),
|
||||
COMP2_CTRL_OUTSEL_TIM2_IC2 = (0x4L << 7),
|
||||
COMP2_CTRL_OUTSEL_TIM2_OCrefclear = (0x5L << 7),
|
||||
COMP2_CTRL_OUTSEL_TIM3_IC2 = (0x6L << 7),
|
||||
COMP2_CTRL_OUTSEL_TIM3_OCrefclear = (0x7L << 7),
|
||||
COMP2_CTRL_OUTSEL_TIM5_IC1 = (0x8L << 7), ////(0x9L << 7)
|
||||
COMP2_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7),
|
||||
COMP2_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7),
|
||||
// comp3 out trig
|
||||
COMP3_CTRL_OUTSEL_NC = (0x0L << 7),
|
||||
COMP3_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7),
|
||||
COMP3_CTRL_OUTSEL_TIM1_IC1 = (0x2L << 7),
|
||||
COMP3_CTRL_OUTSEL_TIM1_OCrefclear = (0x3L << 7),
|
||||
COMP3_CTRL_OUTSEL_TIM2_IC3 = (0x4L << 7),
|
||||
COMP3_CTRL_OUTSEL_TIM2_OCrefclear = (0x5L << 7),
|
||||
COMP3_CTRL_OUTSEL_TIM4_IC2 = (0x6L << 7),
|
||||
COMP3_CTRL_OUTSEL_TIM4_OCrefclear = (0x7L << 7),
|
||||
COMP3_CTRL_OUTSEL_TIM5_IC2 = (0x8L << 7), //(0x9L << 7)
|
||||
COMP3_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7),
|
||||
COMP3_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7),
|
||||
// comp4 out trig
|
||||
COMP4_CTRL_OUTSEL_NC = (0x0L << 7),
|
||||
COMP4_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7),
|
||||
COMP4_CTRL_OUTSEL_TIM3_IC3 = (0x2L << 7),
|
||||
COMP4_CTRL_OUTSEL_TIM3_OCrefclear = (0x3L << 7),
|
||||
COMP4_CTRL_OUTSEL_TIM4_IC3 = (0x4L << 7),
|
||||
COMP4_CTRL_OUTSEL_TIM4_OCrefclear = (0x5L << 7),
|
||||
COMP4_CTRL_OUTSEL_TIM5_IC3 = (0x6L << 7), //(0x7L << 7)
|
||||
COMP4_CTRL_OUTSEL_TIM8_IC2 = (0x8L << 7),
|
||||
COMP4_CTRL_OUTSEL_TIM8_OCrefclear = (0x9L << 7),
|
||||
COMP4_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7),
|
||||
COMP4_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7),
|
||||
// comp5 out trig
|
||||
COMP5_CTRL_OUTSEL_NC = (0x0L << 7),
|
||||
COMP5_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7),
|
||||
COMP5_CTRL_OUTSEL_TIM2_IC4 = (0x2L << 7),
|
||||
COMP5_CTRL_OUTSEL_TIM2_OCrefclear = (0x3L << 7),
|
||||
COMP5_CTRL_OUTSEL_TIM3_IC4 = (0x4L << 7),
|
||||
COMP5_CTRL_OUTSEL_TIM3_OCrefclear = (0x5L << 7),
|
||||
COMP5_CTRL_OUTSEL_TIM4_IC4 = (0x6L << 7),
|
||||
COMP5_CTRL_OUTSEL_TIM4_OCrefclear = (0x7L << 7),
|
||||
COMP5_CTRL_OUTSEL_TIM8_IC1 = (0x8L << 7),
|
||||
COMP5_CTRL_OUTSEL_TIM8_OCrefclear = (0x9L << 7),
|
||||
COMP5_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7),
|
||||
COMP5_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7),
|
||||
// comp6 out trig
|
||||
COMP6_CTRL_OUTSEL_NC = (0x0L << 7),
|
||||
COMP6_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7),
|
||||
COMP6_CTRL_OUTSEL_TIM2_IC1 = (0x2L << 7),
|
||||
COMP6_CTRL_OUTSEL_TIM2_OCrefclear = (0x3L << 7),
|
||||
COMP6_CTRL_OUTSEL_TIM3_IC1 = (0x4L << 7),
|
||||
COMP6_CTRL_OUTSEL_TIM3_OCrefclear = (0x5L << 7),
|
||||
COMP6_CTRL_OUTSEL_TIM5_IC1 = (0x6L << 7), //(0x7L << 7)
|
||||
COMP6_CTRL_OUTSEL_TIM8_IC1 = (0x8L << 7),
|
||||
COMP6_CTRL_OUTSEL_TIM8_OCrefclear = (0x9L << 7),
|
||||
COMP6_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7),
|
||||
COMP6_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7),
|
||||
// comp7 out trig
|
||||
COMP7_CTRL_OUTSEL_NC = (0x0L << 7),
|
||||
COMP7_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 7),
|
||||
COMP7_CTRL_OUTSEL_TIM2_IC1 = (0x2L << 7),
|
||||
COMP7_CTRL_OUTSEL_TIM2_OCrefclear = (0x3L << 7),
|
||||
COMP7_CTRL_OUTSEL_TIM3_IC1 = (0x4L << 7),
|
||||
COMP7_CTRL_OUTSEL_TIM3_OCrefclear = (0x5L << 7),
|
||||
COMP7_CTRL_OUTSEL_TIM5_IC1 = (0x6L << 7), //(0x7L << 7)
|
||||
COMP7_CTRL_OUTSEL_TIM8_IC1 = (0x8L << 7),
|
||||
COMP7_CTRL_OUTSEL_TIM8_OCrefclear = (0x9L << 7),
|
||||
COMP7_CTRL_OUTSEL_TIM8_BKIN = (0xAL << 7),
|
||||
COMP7_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xBL << 7),
|
||||
} COMP_CTRL_OUTTRIG;
|
||||
|
||||
#define COMP_CTRL_INPSEL_MASK (0x07L<<4)
|
||||
typedef enum {
|
||||
COMPX_CTRL_INPSEL_RES = (0x7L << 4),
|
||||
//comp1 inp sel
|
||||
COMP1_CTRL_INPSEL_PA1 = (0x0L << 4),
|
||||
COMP1_CTRL_INPSEL_PB10 = (0x1L << 4),
|
||||
//comp2 inp sel, need recheck maybe wrong
|
||||
COMP2_CTRL_INPSEL_PA1 = (0x0L << 4),
|
||||
COMP2_CTRL_INPSEL_PB11 = (0x1L << 4),
|
||||
COMP2_CTRL_INPSEL_PA7 = (0x2L << 4),
|
||||
//comp3 inp sel
|
||||
COMP3_CTRL_INPSEL_PB14 = (0x0L << 4),
|
||||
COMP3_CTRL_INPSEL_PB0 = (0x1L << 4),
|
||||
//comp4 inp sel, need recheck maybe wrong
|
||||
COMP4_CTRL_INPSEL_PB14 = (0x0L << 4),
|
||||
COMP4_CTRL_INPSEL_PB0 = (0x1L << 4),
|
||||
COMP4_CTRL_INPSEL_PC9 = (0x2L << 4),
|
||||
COMP4_CTRL_INPSEL_PB15 = (0x3L << 4),
|
||||
//comp5 inp sel
|
||||
COMP5_CTRL_INPSEL_PC3 = (0x0L << 4),
|
||||
COMP5_CTRL_INPSEL_PC4 = (0x1L << 4),
|
||||
COMP5_CTRL_INPSEL_PA3 = (0x2L << 4),
|
||||
//comp6 inp sel, need recheck maybe wrong
|
||||
COMP6_CTRL_INPSEL_PC3 = (0x0L << 4),
|
||||
COMP6_CTRL_INPSEL_PC4 = (0x1L << 4),
|
||||
COMP6_CTRL_INPSEL_PC5 = (0x2L << 4),
|
||||
COMP6_CTRL_INPSEL_PD9 = (0x3L << 4),
|
||||
//comp7 inp sel
|
||||
COMP7_CTRL_INPSEL_PC1 = (0x0L << 4),
|
||||
}COMP_CTRL_INPSEL;
|
||||
|
||||
#define COMP_CTRL_INMSEL_MASK (0x07L<<1)
|
||||
typedef enum {
|
||||
COMPX_CTRL_INMSEL_RES = (0x7L << 1),
|
||||
//comp1 inm sel
|
||||
COMP1_CTRL_INMSEL_PA0 = (0x0L << 1),
|
||||
COMP1_CTRL_INMSEL_DAC1_PA4 = (0x1L << 1),
|
||||
COMP1_CTRL_INMSEL_DAC2_PA5 = (0x2L << 1),
|
||||
COMP1_CTRL_INMSEL_VERF1 = (0x3L << 1),
|
||||
COMP1_CTRL_INMSEL_VERF2 = (0x4L << 1),
|
||||
//comp2 inm sel
|
||||
COMP2_CTRL_INMSEL_PB1 = (0x0L << 1),
|
||||
COMP2_CTRL_INMSEL_PE8 = (0x1L << 1),
|
||||
COMP2_CTRL_INMSEL_DAC1_PA4 = (0x2L << 1),
|
||||
COMP2_CTRL_INMSEL_DAC2_PA5 = (0x3L << 1),
|
||||
COMP2_CTRL_INMSEL_VERF1 = (0x4L << 1),
|
||||
COMP2_CTRL_INMSEL_VERF2 = (0x5L << 1),
|
||||
//comp3 inm sel
|
||||
COMP3_CTRL_INMSEL_PB12 = (0x0L << 1),
|
||||
COMP3_CTRL_INMSEL_DAC1_PA4 = (0x1L << 1),
|
||||
COMP3_CTRL_INMSEL_DAC2_PA5 = (0x2L << 1),
|
||||
COMP3_CTRL_INMSEL_VERF1 = (0x3L << 1),
|
||||
COMP3_CTRL_INMSEL_VERF2 = (0x4L << 1),
|
||||
COMP3_CTRL_INMSEL_PE7 = (0x5L << 1),
|
||||
//comp4 inm sel
|
||||
COMP4_CTRL_INMSEL_PC4 = (0x0L << 1),
|
||||
COMP4_CTRL_INMSEL_DAC1_PA4 = (0x1L << 1),
|
||||
COMP4_CTRL_INMSEL_DAC2_PA5 = (0x2L << 1),
|
||||
COMP4_CTRL_INMSEL_VERF1 = (0x3L << 1),
|
||||
COMP4_CTRL_INMSEL_VERF2 = (0x4L << 1),
|
||||
COMP4_CTRL_INMSEL_PB13 = (0x5L << 1),
|
||||
//comp5 inm sel
|
||||
COMP5_CTRL_INMSEL_PB10 = (0x0L << 1),
|
||||
COMP5_CTRL_INMSEL_DAC1_PA4 = (0x1L << 1),
|
||||
COMP5_CTRL_INMSEL_DAC2_PA5 = (0x2L << 1),
|
||||
COMP5_CTRL_INMSEL_VERF1 = (0x3L << 1),
|
||||
COMP5_CTRL_INMSEL_VERF2 = (0x4L << 1),
|
||||
COMP5_CTRL_INMSEL_PD10 = (0x5L << 1),
|
||||
//comp6 inm sel
|
||||
COMP6_CTRL_INMSEL_PA7 = (0x0L << 1),
|
||||
COMP6_CTRL_INMSEL_DAC1_PA4 = (0x1L << 1),
|
||||
COMP6_CTRL_INMSEL_DAC2_PA5 = (0x2L << 1),
|
||||
COMP6_CTRL_INMSEL_VERF1 = (0x3L << 1),
|
||||
COMP6_CTRL_INMSEL_VERF2 = (0x4L << 1),
|
||||
COMP6_CTRL_INMSEL_PD8 = (0x5L << 1),
|
||||
//comp7 inm sel
|
||||
COMP7_CTRL_INMSEL_PC0 = (0x0L << 1),
|
||||
COMP7_CTRL_INMSEL_DAC1_PA4 = (0x1L << 1),
|
||||
COMP7_CTRL_INMSEL_DAC2_PA5 = (0x2L << 1),
|
||||
COMP7_CTRL_INMSEL_VERF1 = (0x3L << 1),
|
||||
COMP7_CTRL_INMSEL_VERF2 = (0x4L << 1),
|
||||
}COMP_CTRL_INMSEL;
|
||||
|
||||
#define COMP_CTRL_EN_MASK (0x01L << 0)
|
||||
|
||||
//COMPx_FILC
|
||||
#define COMP_FILC_SAMPW_MASK (0x1FL<<6)//Low filter sample window size. Number of samples to monitor is SAMPWIN+1.
|
||||
#define COMP_FILC_THRESH_MASK (0x1FL<<1)//For proper operation, the value of THRESH must be greater than SAMPWIN / 2.
|
||||
#define COMP_FILC_FILEN_MASK (0x01L<<0)//Filter enable.
|
||||
|
||||
//COMP_WINMODE @addtogroup COMP_WINMODE_CMPMD
|
||||
#define COMP_WINMODE_CMPMD_MSK (0x07L <<0)
|
||||
#define COMP_WINMODE_CMP56MD (0x01L <<2)//1: Comparators 5 and 6 can be used in window mode.
|
||||
#define COMP_WINMODE_CMP34MD (0x01L <<1)//1: Comparators 3 and 4 can be used in window mode.
|
||||
#define COMP_WINMODE_CMP12MD (0x01L <<0)//1: Comparators 1 and 2 can be used in window mode.
|
||||
|
||||
// COMP_INTEN @addtogroup COMP_INTEN_CMPIEN
|
||||
#define COMP_INTEN_CMPIEN_MSK (0x7FL << 0)
|
||||
#define COMP_INTEN_CMP7IEN (0x01L << 6) // This bit control Interrput enable of COMP.
|
||||
#define COMP_INTEN_CMP6IEN (0x01L << 5)
|
||||
#define COMP_INTEN_CMP5IEN (0x01L << 4)
|
||||
#define COMP_INTEN_CMP4IEN (0x01L << 3)
|
||||
#define COMP_INTEN_CMP3IEN (0x01L << 2)
|
||||
#define COMP_INTEN_CMP2IEN (0x01L << 1)
|
||||
#define COMP_INTEN_CMP1IEN (0x01L << 0)
|
||||
|
||||
// COMP_INTSTS @addtogroup COMP_INTSTS_CMPIS
|
||||
#define COMP_INTSTS_INTSTS_MSK (0x7FL << 0)
|
||||
#define COMP_INTSTS_CMP7IS (0x01L << 6) // This bit control Interrput enable of COMP.
|
||||
#define COMP_INTSTS_CMP6IS (0x01L << 5)
|
||||
#define COMP_INTSTS_CMP5IS (0x01L << 4)
|
||||
#define COMP_INTSTS_CMP4IS (0x01L << 3)
|
||||
#define COMP_INTSTS_CMP3IS (0x01L << 2)
|
||||
#define COMP_INTSTS_CMP2IS (0x01L << 1)
|
||||
#define COMP_INTSTS_CMP1IS (0x01L << 0)
|
||||
|
||||
// COMP_VREFSCL @addtogroup COMP_VREFSCL
|
||||
#define COMP_VREFSCL_VV2TRM_MSK (0x2FL << 8) // Vref2 Voltage scaler triming value.
|
||||
#define COMP_VREFSCL_VV2EN_MSK (0x01L << 7)
|
||||
#define COMP_VREFSCL_VV1TRM_MSK (0x2FL << 1) // Vref1 Voltage scaler triming value.
|
||||
#define COMP_VREFSCL_VV1EN_MSK (0x01L << 0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief COMP Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
// ctrl
|
||||
bool InpDacConnect; // only COMP1 have this bit
|
||||
|
||||
COMP_CTRL_BLKING Blking; /*see @ref COMP_CTRL_BLKING */
|
||||
|
||||
COMP_CTRL_HYST Hyst;
|
||||
|
||||
bool PolRev; // out polarity reverse
|
||||
|
||||
COMP_CTRL_OUTTRIG OutSel;
|
||||
COMP_CTRL_INPSEL InpSel;
|
||||
COMP_CTRL_INMSEL InmSel;
|
||||
|
||||
bool En;
|
||||
|
||||
// filter
|
||||
uint8_t SampWindow; // 5bit
|
||||
uint8_t Thresh; // 5bit ,need > SampWindow/2
|
||||
bool FilterEn;
|
||||
|
||||
// filter psc
|
||||
uint16_t ClkPsc;
|
||||
} COMP_InitType;
|
||||
|
||||
/** @addtogroup COMP_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void COMP_DeInit(void);
|
||||
void COMP_StructInit(COMP_InitType* COMP_InitStruct);
|
||||
void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct);
|
||||
void COMP_Enable(COMPX COMPx, FunctionalState en);
|
||||
void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel);
|
||||
void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel);
|
||||
void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig);
|
||||
void COMP_SetLock(uint32_t Lock); // see @COMP_LOCK_CMPLK
|
||||
void COMP_SetIntEn(uint32_t IntEn); // see @COMP_INTEN_CMPIEN
|
||||
uint32_t COMP_GetIntSts(void); // return see @COMP_INTSTS_CMPIS
|
||||
void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En); // parma range see @COMP_VREFSCL
|
||||
FlagStatus COMP_GetOutStatus(COMPX COMPx);
|
||||
FlagStatus COMP_GetIntStsOneComp(COMPX COMPx);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__N32G45X_ADC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_crc.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_CRC_H__
|
||||
#define __N32G45X_CRC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void CRC32_ResetCrc(void);
|
||||
uint32_t CRC32_CalcCrc(uint32_t Data);
|
||||
uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t CRC32_GetCrc(void);
|
||||
void CRC32_SetIDat(uint8_t IDValue);
|
||||
uint8_t CRC32_GetIDat(void);
|
||||
|
||||
uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength);
|
||||
uint16_t CRC16_CalcCRC(uint8_t Data);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __N32G45X_CRC_H__ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,307 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_dac.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_DAC_H__
|
||||
#define __N32G45X_DAC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DAC Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
|
||||
uint32_t WaveGen; /*!< Specifies whether DAC channel noise waves or triangle waves
|
||||
are generated, or whether no wave is generated.
|
||||
This parameter can be a value of @ref DAC_wave_generation */
|
||||
|
||||
uint32_t
|
||||
LfsrUnMaskTriAmp; /*!< Specifies the LFSR mask for noise wave generation or
|
||||
the maximum amplitude triangle generation for the DAC channel.
|
||||
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
|
||||
|
||||
uint32_t BufferOutput; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
} DAC_InitType;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_trigger_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_TRG_NONE \
|
||||
((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRG_T6_TRGO \
|
||||
((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel \
|
||||
*/
|
||||
#define DAC_TRG_T8_TRGO \
|
||||
((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel \
|
||||
only in High-density devices*/
|
||||
#define DAC_TRG_T3_TRGO \
|
||||
((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel \
|
||||
only in Connectivity line, Medium-density and Low-density Value Line devices */
|
||||
#define DAC_TRG_T7_TRGO \
|
||||
((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel \
|
||||
*/
|
||||
#define DAC_TRG_T5_TRGO \
|
||||
((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel \
|
||||
*/
|
||||
#define DAC_TRG_T15_TRGO \
|
||||
((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel \
|
||||
only in Medium-density and Low-density Value Line devices*/
|
||||
#define DAC_TRG_T2_TRGO \
|
||||
((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel \
|
||||
*/
|
||||
#define DAC_TRG_T4_TRGO \
|
||||
((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel \
|
||||
*/
|
||||
#define DAC_TRG_EXT_IT9 \
|
||||
((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRG_SOFTWARE ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) \
|
||||
(((TRIGGER) == DAC_TRG_NONE) || ((TRIGGER) == DAC_TRG_T6_TRGO) || ((TRIGGER) == DAC_TRG_T8_TRGO) \
|
||||
|| ((TRIGGER) == DAC_TRG_T7_TRGO) || ((TRIGGER) == DAC_TRG_T5_TRGO) || ((TRIGGER) == DAC_TRG_T2_TRGO) \
|
||||
|| ((TRIGGER) == DAC_TRG_T4_TRGO) || ((TRIGGER) == DAC_TRG_EXT_IT9) || ((TRIGGER) == DAC_TRG_SOFTWARE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_WAVEGEN_NONE ((uint32_t)0x00000000)
|
||||
#define DAC_WAVEGEN_NOISE ((uint32_t)0x00000040)
|
||||
#define DAC_WAVEGEN_TRIANGLE ((uint32_t)0x00000080)
|
||||
#define IS_DAC_GENERATE_WAVE(WAVE) \
|
||||
(((WAVE) == DAC_WAVEGEN_NONE) || ((WAVE) == DAC_WAVEGEN_NOISE) || ((WAVE) == DAC_WAVEGEN_TRIANGLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_lfsrunmask_triangleamplitude
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_UNMASK_LFSRBIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_UNMASK_LFSRBITS1_0 \
|
||||
((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation \
|
||||
*/
|
||||
#define DAC_UNMASK_LFSRBITS2_0 \
|
||||
((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation \
|
||||
*/
|
||||
#define DAC_UNMASK_LFSRBITS3_0 \
|
||||
((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation \
|
||||
*/
|
||||
#define DAC_UNMASK_LFSRBITS4_0 \
|
||||
((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation \
|
||||
*/
|
||||
#define DAC_UNMASK_LFSRBITS5_0 \
|
||||
((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation \
|
||||
*/
|
||||
#define DAC_UNMASK_LFSRBITS6_0 \
|
||||
((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation \
|
||||
*/
|
||||
#define DAC_UNMASK_LFSRBITS7_0 \
|
||||
((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation \
|
||||
*/
|
||||
#define DAC_UNMASK_LFSRBITS8_0 \
|
||||
((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation \
|
||||
*/
|
||||
#define DAC_UNMASK_LFSRBITS9_0 \
|
||||
((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation \
|
||||
*/
|
||||
#define DAC_UNMASK_LFSRBITS10_0 \
|
||||
((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_UNMASK_LFSRBITS11_0 \
|
||||
((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TRIAMP_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TRIAMP_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TRIAMP_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TRIAMP_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TRIAMP_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TRIAMP_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TRIAMP_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TRIAMP_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TRIAMP_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TRIAMP_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TRIAMP_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TRIAMP_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) \
|
||||
(((VALUE) == DAC_UNMASK_LFSRBIT0) || ((VALUE) == DAC_UNMASK_LFSRBITS1_0) || ((VALUE) == DAC_UNMASK_LFSRBITS2_0) \
|
||||
|| ((VALUE) == DAC_UNMASK_LFSRBITS3_0) || ((VALUE) == DAC_UNMASK_LFSRBITS4_0) \
|
||||
|| ((VALUE) == DAC_UNMASK_LFSRBITS5_0) || ((VALUE) == DAC_UNMASK_LFSRBITS6_0) \
|
||||
|| ((VALUE) == DAC_UNMASK_LFSRBITS7_0) || ((VALUE) == DAC_UNMASK_LFSRBITS8_0) \
|
||||
|| ((VALUE) == DAC_UNMASK_LFSRBITS9_0) || ((VALUE) == DAC_UNMASK_LFSRBITS10_0) \
|
||||
|| ((VALUE) == DAC_UNMASK_LFSRBITS11_0) || ((VALUE) == DAC_TRIAMP_1) || ((VALUE) == DAC_TRIAMP_3) \
|
||||
|| ((VALUE) == DAC_TRIAMP_7) || ((VALUE) == DAC_TRIAMP_15) || ((VALUE) == DAC_TRIAMP_31) \
|
||||
|| ((VALUE) == DAC_TRIAMP_63) || ((VALUE) == DAC_TRIAMP_127) || ((VALUE) == DAC_TRIAMP_255) \
|
||||
|| ((VALUE) == DAC_TRIAMP_511) || ((VALUE) == DAC_TRIAMP_1023) || ((VALUE) == DAC_TRIAMP_2047) \
|
||||
|| ((VALUE) == DAC_TRIAMP_4095))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_output_buffer
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_BUFFOUTPUT_ENABLE ((uint32_t)0x00000000)
|
||||
#define DAC_BUFFOUTPUT_DISABLE ((uint32_t)0x00000002)
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_BUFFOUTPUT_ENABLE) || ((STATE) == DAC_BUFFOUTPUT_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Channel_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
|
||||
#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || ((CHANNEL) == DAC_CHANNEL_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_data_alignment
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_ALIGN_R_12BIT ((uint32_t)0x00000000)
|
||||
#define DAC_ALIGN_L_12BIT ((uint32_t)0x00000004)
|
||||
#define DAC_ALIGN_R_8BIT ((uint32_t)0x00000008)
|
||||
#define IS_DAC_ALIGN(ALIGN) \
|
||||
(((ALIGN) == DAC_ALIGN_R_12BIT) || ((ALIGN) == DAC_ALIGN_L_12BIT) || ((ALIGN) == DAC_ALIGN_R_8BIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_WAVE_NOISE ((uint32_t)0x00000040)
|
||||
#define DAC_WAVE_TRIANGLE ((uint32_t)0x00000080)
|
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || ((WAVE) == DAC_WAVE_TRIANGLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_data
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void DAC_DeInit(void);
|
||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitType* DAC_InitStruct);
|
||||
void DAC_ClearStruct(DAC_InitType* DAC_InitStruct);
|
||||
void DAC_Enable(uint32_t DAC_Channel, FunctionalState Cmd);
|
||||
|
||||
void DAC_DmaEnable(uint32_t DAC_Channel, FunctionalState Cmd);
|
||||
void DAC_SoftTrgEnable(uint32_t DAC_Channel, FunctionalState Cmd);
|
||||
void DAC_DualSoftwareTrgEnable(FunctionalState Cmd);
|
||||
void DAC_WaveGenerationEnable(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState Cmd);
|
||||
void DAC_SetCh1Data(uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetCh2Data(uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetDualChData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
|
||||
uint16_t DAC_GetOutputDataVal(uint32_t DAC_Channel);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__N32G45X_DAC_H__ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_dbg.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_DBG_H__
|
||||
#define __N32G45X_DBG_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DBG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DBG_SLP ((uint32_t)0x00000001)
|
||||
#define DBG_STOP ((uint32_t)0x00000002)
|
||||
#define DBG_STDBY ((uint32_t)0x00000004)
|
||||
#define DBG_IWDG_STOP ((uint32_t)0x00000100)
|
||||
#define DBG_WWDG_STOP ((uint32_t)0x00000200)
|
||||
#define DBG_TIM1_STOP ((uint32_t)0x00000400)
|
||||
#define DBG_TIM2_STOP ((uint32_t)0x00000800)
|
||||
#define DBG_TIM3_STOP ((uint32_t)0x00001000)
|
||||
#define DBG_TIM4_STOP ((uint32_t)0x00002000)
|
||||
#define DBG_CAN1_STOP ((uint32_t)0x00004000)
|
||||
#define DBG_I2C1SMBUS_TIMEOUT ((uint32_t)0x00008000)
|
||||
#define DBG_I2C2SMBUS_TIMEOUT ((uint32_t)0x00010000)
|
||||
#define DBG_TIM8_STOP ((uint32_t)0x00020000)
|
||||
#define DBG_TIM5_STOP ((uint32_t)0x00040000)
|
||||
#define DBG_TIM6_STOP ((uint32_t)0x00080000)
|
||||
#define DBG_TIM7_STOP ((uint32_t)0x00100000)
|
||||
#define DBG_CAN2_STOP ((uint32_t)0x00200000)
|
||||
|
||||
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH)&0xFFC000F8) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t DBG_GetRevNum(void);
|
||||
uint32_t DBG_GetDevNum(void);
|
||||
void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd);
|
||||
|
||||
uint32_t DBG_GetFlashSize(void);
|
||||
uint32_t DBG_GetSramSize(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __N32G45X_DBG_H__ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,569 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_dma.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_DMA_H__
|
||||
#define __N32G45X_DMA_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PeriphAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
|
||||
|
||||
uint32_t MemAddr; /*!< Specifies the memory base address for DMAy Channelx. */
|
||||
|
||||
uint32_t Direction; /*!< Specifies if the peripheral is the source or destination.
|
||||
This parameter can be a value of @ref DMA_data_transfer_direction */
|
||||
|
||||
uint32_t BufSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
|
||||
The data unit is equal to the configuration set in PeriphDataSize
|
||||
or MemDataSize members depending in the transfer direction. */
|
||||
|
||||
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
|
||||
|
||||
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_memory_incremented_mode */
|
||||
|
||||
uint32_t PeriphDataSize; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_peripheral_data_size */
|
||||
|
||||
uint32_t MemDataSize; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_memory_data_size */
|
||||
|
||||
uint32_t CircularMode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_circular_normal_mode.
|
||||
@note: The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_priority_level */
|
||||
|
||||
uint32_t Mem2Mem; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
|
||||
This parameter can be a value of @ref DMA_memory_to_memory */
|
||||
} DMA_InitType;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_ALL_PERIPH(PERIPH) \
|
||||
(((PERIPH) == DMA1_CH1) || ((PERIPH) == DMA1_CH2) || ((PERIPH) == DMA1_CH3) || ((PERIPH) == DMA1_CH4) \
|
||||
|| ((PERIPH) == DMA1_CH5) || ((PERIPH) == DMA1_CH6) || ((PERIPH) == DMA1_CH7) || ((PERIPH) == DMA1_CH8) \
|
||||
|| ((PERIPH) == DMA2_CH1) || ((PERIPH) == DMA2_CH2) || ((PERIPH) == DMA2_CH3) || ((PERIPH) == DMA2_CH4) \
|
||||
|| ((PERIPH) == DMA2_CH5) || ((PERIPH) == DMA2_CH6) || ((PERIPH) == DMA2_CH7) || ((PERIPH) == DMA2_CH8))
|
||||
|
||||
/** @addtogroup DMA_data_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_DIR_PERIPH_DST ((uint32_t)0x00000010)
|
||||
#define DMA_DIR_PERIPH_SRC ((uint32_t)0x00000000)
|
||||
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PERIPH_DST) || ((DIR) == DMA_DIR_PERIPH_SRC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_peripheral_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PERIPH_INC_ENABLE ((uint32_t)0x00000040)
|
||||
#define DMA_PERIPH_INC_DISABLE ((uint32_t)0x00000000)
|
||||
#define IS_DMA_PERIPH_INC_STATE(STATE) (((STATE) == DMA_PERIPH_INC_ENABLE) || ((STATE) == DMA_PERIPH_INC_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_memory_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MEM_INC_ENABLE ((uint32_t)0x00000080)
|
||||
#define DMA_MEM_INC_DISABLE ((uint32_t)0x00000000)
|
||||
#define IS_DMA_MEM_INC_STATE(STATE) (((STATE) == DMA_MEM_INC_ENABLE) || ((STATE) == DMA_MEM_INC_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_peripheral_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PERIPH_DATA_SIZE_BYTE ((uint32_t)0x00000000)
|
||||
#define DMA_PERIPH_DATA_SIZE_HALFWORD ((uint32_t)0x00000100)
|
||||
#define DMA_PERIPH_DATA_SIZE_WORD ((uint32_t)0x00000200)
|
||||
#define IS_DMA_PERIPH_DATA_SIZE(SIZE) \
|
||||
(((SIZE) == DMA_PERIPH_DATA_SIZE_BYTE) || ((SIZE) == DMA_PERIPH_DATA_SIZE_HALFWORD) \
|
||||
|| ((SIZE) == DMA_PERIPH_DATA_SIZE_WORD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_memory_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
|
||||
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) \
|
||||
(((SIZE) == DMA_MemoryDataSize_Byte) || ((SIZE) == DMA_MemoryDataSize_HalfWord) \
|
||||
|| ((SIZE) == DMA_MemoryDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_circular_normal_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MODE_CIRCULAR ((uint32_t)0x00000020)
|
||||
#define DMA_MODE_NORMAL ((uint32_t)0x00000000)
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_MODE_CIRCULAR) || ((MODE) == DMA_MODE_NORMAL))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_priority_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)0x00003000)
|
||||
#define DMA_PRIORITY_HIGH ((uint32_t)0x00002000)
|
||||
#define DMA_PRIORITY_MEDIUM ((uint32_t)0x00001000)
|
||||
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000)
|
||||
#define IS_DMA_PRIORITY(PRIORITY) \
|
||||
(((PRIORITY) == DMA_PRIORITY_VERY_HIGH) || ((PRIORITY) == DMA_PRIORITY_HIGH) \
|
||||
|| ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_LOW))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_memory_to_memory
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_M2M_ENABLE ((uint32_t)0x00004000)
|
||||
#define DMA_M2M_DISABLE ((uint32_t)0x00000000)
|
||||
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_ENABLE) || ((STATE) == DMA_M2M_DISABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_INT_TXC ((uint32_t)0x00000002)
|
||||
#define DMA_INT_HTX ((uint32_t)0x00000004)
|
||||
#define DMA_INT_ERR ((uint32_t)0x00000008)
|
||||
#define IS_DMA_CONFIG_INT(IT) ((((IT)&0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define DMA1_INT_GLB1 ((uint32_t)0x00000001)
|
||||
#define DMA1_INT_TXC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_INT_HTX1 ((uint32_t)0x00000004)
|
||||
#define DMA1_INT_ERR1 ((uint32_t)0x00000008)
|
||||
#define DMA1_INT_GLB2 ((uint32_t)0x00000010)
|
||||
#define DMA1_INT_TXC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_INT_HTX2 ((uint32_t)0x00000040)
|
||||
#define DMA1_INT_ERR2 ((uint32_t)0x00000080)
|
||||
#define DMA1_INT_GLB3 ((uint32_t)0x00000100)
|
||||
#define DMA1_INT_TXC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_INT_HTX3 ((uint32_t)0x00000400)
|
||||
#define DMA1_INT_ERR3 ((uint32_t)0x00000800)
|
||||
#define DMA1_INT_GLB4 ((uint32_t)0x00001000)
|
||||
#define DMA1_INT_TXC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_INT_HTX4 ((uint32_t)0x00004000)
|
||||
#define DMA1_INT_ERR4 ((uint32_t)0x00008000)
|
||||
#define DMA1_INT_GLB5 ((uint32_t)0x00010000)
|
||||
#define DMA1_INT_TXC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_INT_HTX5 ((uint32_t)0x00040000)
|
||||
#define DMA1_INT_ERR5 ((uint32_t)0x00080000)
|
||||
#define DMA1_INT_GLB6 ((uint32_t)0x00100000)
|
||||
#define DMA1_INT_TXC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_INT_HTX6 ((uint32_t)0x00400000)
|
||||
#define DMA1_INT_ERR6 ((uint32_t)0x00800000)
|
||||
#define DMA1_INT_GLB7 ((uint32_t)0x01000000)
|
||||
#define DMA1_INT_TXC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_INT_HTX7 ((uint32_t)0x04000000)
|
||||
#define DMA1_INT_ERR7 ((uint32_t)0x08000000)
|
||||
#define DMA1_INT_GLB8 ((uint32_t)0x10000000)
|
||||
#define DMA1_INT_TXC8 ((uint32_t)0x20000000)
|
||||
#define DMA1_INT_HTX8 ((uint32_t)0x40000000)
|
||||
#define DMA1_INT_ERR8 ((uint32_t)0x80000000)
|
||||
|
||||
#define DMA2_INT_GLB1 ((uint32_t)0x00000001)
|
||||
#define DMA2_INT_TXC1 ((uint32_t)0x00000002)
|
||||
#define DMA2_INT_HTX1 ((uint32_t)0x00000004)
|
||||
#define DMA2_INT_ERR1 ((uint32_t)0x00000008)
|
||||
#define DMA2_INT_GLB2 ((uint32_t)0x00000010)
|
||||
#define DMA2_INT_TXC2 ((uint32_t)0x00000020)
|
||||
#define DMA2_INT_HTX2 ((uint32_t)0x00000040)
|
||||
#define DMA2_INT_ERR2 ((uint32_t)0x00000080)
|
||||
#define DMA2_INT_GLB3 ((uint32_t)0x00000100)
|
||||
#define DMA2_INT_TXC3 ((uint32_t)0x00000200)
|
||||
#define DMA2_INT_HTX3 ((uint32_t)0x00000400)
|
||||
#define DMA2_INT_ERR3 ((uint32_t)0x00000800)
|
||||
#define DMA2_INT_GLB4 ((uint32_t)0x00001000)
|
||||
#define DMA2_INT_TXC4 ((uint32_t)0x00002000)
|
||||
#define DMA2_INT_HTX4 ((uint32_t)0x00004000)
|
||||
#define DMA2_INT_ERR4 ((uint32_t)0x00008000)
|
||||
#define DMA2_INT_GLB5 ((uint32_t)0x00010000)
|
||||
#define DMA2_INT_TXC5 ((uint32_t)0x00020000)
|
||||
#define DMA2_INT_HTX5 ((uint32_t)0x00040000)
|
||||
#define DMA2_INT_ERR5 ((uint32_t)0x00080000)
|
||||
#define DMA2_INT_GLB6 ((uint32_t)0x00100000)
|
||||
#define DMA2_INT_TXC6 ((uint32_t)0x00200000)
|
||||
#define DMA2_INT_HTX6 ((uint32_t)0x00400000)
|
||||
#define DMA2_INT_ERR6 ((uint32_t)0x00800000)
|
||||
#define DMA2_INT_GLB7 ((uint32_t)0x01000000)
|
||||
#define DMA2_INT_TXC7 ((uint32_t)0x02000000)
|
||||
#define DMA2_INT_HTX7 ((uint32_t)0x04000000)
|
||||
#define DMA2_INT_ERR7 ((uint32_t)0x08000000)
|
||||
#define DMA2_INT_GLB8 ((uint32_t)0x10000000)
|
||||
#define DMA2_INT_TXC8 ((uint32_t)0x20000000)
|
||||
#define DMA2_INT_HTX8 ((uint32_t)0x40000000)
|
||||
#define DMA2_INT_ERR8 ((uint32_t)0x80000000)
|
||||
|
||||
#define IS_DMA_CLR_INT(IT) (((((IT)&0xF0000000) == 0x00) || (((IT)&0xEFF00000) == 0x00)) && ((IT) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_IT(IT) \
|
||||
(((IT) == DMA1_INT_GLB1) || ((IT) == DMA1_INT_TXC1) || ((IT) == DMA1_INT_HTX1) || ((IT) == DMA1_INT_ERR1) \
|
||||
|| ((IT) == DMA1_INT_GLB2) || ((IT) == DMA1_INT_TXC2) || ((IT) == DMA1_INT_HTX2) || ((IT) == DMA1_INT_ERR2) \
|
||||
|| ((IT) == DMA1_INT_GLB3) || ((IT) == DMA1_INT_TXC3) || ((IT) == DMA1_INT_HTX3) || ((IT) == DMA1_INT_ERR3) \
|
||||
|| ((IT) == DMA1_INT_GLB4) || ((IT) == DMA1_INT_TXC4) || ((IT) == DMA1_INT_HTX4) || ((IT) == DMA1_INT_ERR4) \
|
||||
|| ((IT) == DMA1_INT_GLB5) || ((IT) == DMA1_INT_TXC5) || ((IT) == DMA1_INT_HTX5) || ((IT) == DMA1_INT_ERR5) \
|
||||
|| ((IT) == DMA1_INT_GLB6) || ((IT) == DMA1_INT_TXC6) || ((IT) == DMA1_INT_HTX6) || ((IT) == DMA1_INT_ERR6) \
|
||||
|| ((IT) == DMA1_INT_GLB7) || ((IT) == DMA1_INT_TXC7) || ((IT) == DMA1_INT_HTX7) || ((IT) == DMA1_INT_ERR7) \
|
||||
|| ((IT) == DMA1_INT_GLB8) || ((IT) == DMA1_INT_TXC8) || ((IT) == DMA1_INT_HTX8) || ((IT) == DMA1_INT_ERR8) \
|
||||
|| ((IT) == DMA2_INT_GLB1) || ((IT) == DMA2_INT_TXC1) || ((IT) == DMA2_INT_HTX1) || ((IT) == DMA2_INT_ERR1) \
|
||||
|| ((IT) == DMA2_INT_GLB2) || ((IT) == DMA2_INT_TXC2) || ((IT) == DMA2_INT_HTX2) || ((IT) == DMA2_INT_ERR2) \
|
||||
|| ((IT) == DMA2_INT_GLB3) || ((IT) == DMA2_INT_TXC3) || ((IT) == DMA2_INT_HTX3) || ((IT) == DMA2_INT_ERR3) \
|
||||
|| ((IT) == DMA2_INT_GLB4) || ((IT) == DMA2_INT_TXC4) || ((IT) == DMA2_INT_HTX4) || ((IT) == DMA2_INT_ERR4) \
|
||||
|| ((IT) == DMA2_INT_GLB5) || ((IT) == DMA2_INT_TXC5) || ((IT) == DMA2_INT_HTX5) || ((IT) == DMA2_INT_ERR5) \
|
||||
|| ((IT) == DMA2_INT_GLB6) || ((IT) == DMA2_INT_TXC6) || ((IT) == DMA2_INT_HTX6) || ((IT) == DMA2_INT_ERR6) \
|
||||
|| ((IT) == DMA2_INT_GLB7) || ((IT) == DMA2_INT_TXC7) || ((IT) == DMA2_INT_HTX7) || ((IT) == DMA2_INT_ERR7) \
|
||||
|| ((IT) == DMA2_INT_GLB8) || ((IT) == DMA2_INT_TXC8) || ((IT) == DMA2_INT_HTX8) || ((IT) == DMA2_INT_ERR8))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_flags_definition
|
||||
* @{
|
||||
*/
|
||||
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
|
||||
#define DMA1_FLAG_GL8 ((uint32_t)0x10000000)
|
||||
#define DMA1_FLAG_TC8 ((uint32_t)0x20000000)
|
||||
#define DMA1_FLAG_HT8 ((uint32_t)0x40000000)
|
||||
#define DMA1_FLAG_TE8 ((uint32_t)0x80000000)
|
||||
|
||||
#define DMA2_FLAG_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA2_FLAG_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA2_FLAG_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA2_FLAG_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA2_FLAG_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA2_FLAG_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA2_FLAG_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA2_FLAG_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA2_FLAG_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA2_FLAG_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA2_FLAG_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA2_FLAG_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA2_FLAG_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA2_FLAG_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA2_FLAG_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA2_FLAG_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA2_FLAG_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA2_FLAG_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA2_FLAG_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA2_FLAG_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA2_FLAG_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA2_FLAG_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA2_FLAG_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA2_FLAG_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA2_FLAG_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA2_FLAG_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA2_FLAG_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA2_FLAG_TE7 ((uint32_t)0x08000000)
|
||||
#define DMA2_FLAG_GL8 ((uint32_t)0x10000000)
|
||||
#define DMA2_FLAG_TC8 ((uint32_t)0x20000000)
|
||||
#define DMA2_FLAG_HT8 ((uint32_t)0x40000000)
|
||||
#define DMA2_FLAG_TE8 ((uint32_t)0x80000000)
|
||||
|
||||
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG)&0xF0000000) == 0x00) || (((FLAG)&0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_FLAG(FLAG) \
|
||||
(((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) \
|
||||
|| ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || ((FLAG) == DMA1_FLAG_HT2) \
|
||||
|| ((FLAG) == DMA1_FLAG_TE2) || ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) \
|
||||
|| ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || ((FLAG) == DMA1_FLAG_GL4) \
|
||||
|| ((FLAG) == DMA1_FLAG_TC4) || ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) \
|
||||
|| ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || ((FLAG) == DMA1_FLAG_HT5) \
|
||||
|| ((FLAG) == DMA1_FLAG_TE5) || ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) \
|
||||
|| ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || ((FLAG) == DMA1_FLAG_GL7) \
|
||||
|| ((FLAG) == DMA1_FLAG_TC7) || ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) \
|
||||
|| ((FLAG) == DMA1_FLAG_GL8) || ((FLAG) == DMA1_FLAG_TC8) || ((FLAG) == DMA1_FLAG_HT8) \
|
||||
|| ((FLAG) == DMA1_FLAG_TE8) || ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) \
|
||||
|| ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || ((FLAG) == DMA2_FLAG_GL2) \
|
||||
|| ((FLAG) == DMA2_FLAG_TC2) || ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) \
|
||||
|| ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || ((FLAG) == DMA2_FLAG_HT3) \
|
||||
|| ((FLAG) == DMA2_FLAG_TE3) || ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) \
|
||||
|| ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || ((FLAG) == DMA2_FLAG_GL5) \
|
||||
|| ((FLAG) == DMA2_FLAG_TC5) || ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5) \
|
||||
|| ((FLAG) == DMA2_FLAG_GL6) || ((FLAG) == DMA2_FLAG_TC6) || ((FLAG) == DMA2_FLAG_HT6) \
|
||||
|| ((FLAG) == DMA2_FLAG_TE6) || ((FLAG) == DMA2_FLAG_GL7) || ((FLAG) == DMA2_FLAG_TC7) \
|
||||
|| ((FLAG) == DMA2_FLAG_HT7) || ((FLAG) == DMA2_FLAG_TE7) || ((FLAG) == DMA2_FLAG_GL8) \
|
||||
|| ((FLAG) == DMA2_FLAG_TC8) || ((FLAG) == DMA2_FLAG_HT8) || ((FLAG) == DMA2_FLAG_TE8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Buffer_Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_BUF_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_remap_request_definition
|
||||
* @{
|
||||
*/
|
||||
#define DMA1_REMAP_ADC1 ((uint32_t)0x00000000)
|
||||
#define DMA1_REMAP_UART5_TX ((uint32_t)0x00000001)
|
||||
#define DMA1_REMAP_I2C3_TX ((uint32_t)0x00000002)
|
||||
#define DMA1_REMAP_TIM2_CH3 ((uint32_t)0x00000003)
|
||||
#define DMA1_REMAP_TIM4_CH1 ((uint32_t)0x00000004)
|
||||
#define DMA1_REMAP_USART3_TX ((uint32_t)0x00000005)
|
||||
#define DMA1_REMAP_I2C3_RX ((uint32_t)0x00000006)
|
||||
#define DMA1_REMAP_TIM1_CH1 ((uint32_t)0x00000007)
|
||||
#define DMA1_REMAP_TIM2_UP ((uint32_t)0x00000008)
|
||||
#define DMA1_REMAP_TIM3_CH3 ((uint32_t)0x00000009)
|
||||
#define DMA1_REMAP_SPI1_RX ((uint32_t)0x0000000A)
|
||||
#define DMA1_REMAP_USART3_RX ((uint32_t)0x0000000B)
|
||||
#define DMA1_REMAP_TIM1_CH2 ((uint32_t)0x0000000C)
|
||||
#define DMA1_REMAP_TIM3_CH4 ((uint32_t)0x0000000D)
|
||||
#define DMA1_REMAP_TIM3_UP ((uint32_t)0x0000000E)
|
||||
#define DMA1_REMAP_SPI1_TX ((uint32_t)0x0000000F)
|
||||
#define DMA1_REMAP_USART1_TX ((uint32_t)0x00000010)
|
||||
#define DMA1_REMAP_TIM1_CH4 ((uint32_t)0x00000011)
|
||||
#define DMA1_REMAP_TIM1_TRIG ((uint32_t)0x00000012)
|
||||
#define DMA1_REMAP_TIM1_COM ((uint32_t)0x00000013)
|
||||
#define DMA1_REMAP_TIM4_CH2 ((uint32_t)0x00000014)
|
||||
#define DMA1_REMAP_SPI_I2S2_RX ((uint32_t)0x00000015)
|
||||
#define DMA1_REMAP_I2C2_TX ((uint32_t)0x00000016)
|
||||
#define DMA1_REMAP_USART1_RX ((uint32_t)0x00000017)
|
||||
#define DMA1_REMAP_TIM1_UP ((uint32_t)0x00000018)
|
||||
#define DMA1_REMAP_SPI_I2S2_TX ((uint32_t)0x00000019)
|
||||
#define DMA1_REMAP_TIM4_CH3 ((uint32_t)0x0000001B)
|
||||
#define DMA1_REMAP_I2C2_RX ((uint32_t)0x0000001C)
|
||||
#define DMA1_REMAP_TIM2_CH1 ((uint32_t)0x0000001A)
|
||||
#define DMA1_REMAP_USART2_RX ((uint32_t)0x0000001D)
|
||||
#define DMA1_REMAP_TIM1_CH3 ((uint32_t)0x0000001E)
|
||||
#define DMA1_REMAP_TIM3_CH1 ((uint32_t)0x0000001F)
|
||||
#define DMA1_REMAP_TIM3_TRIG ((uint32_t)0x00000020)
|
||||
#define DMA1_REMAP_I2C1_TX ((uint32_t)0x00000021)
|
||||
#define DMA1_REMAP_USART2_TX ((uint32_t)0x00000022)
|
||||
#define DMA1_REMAP_TIM2_CH2 ((uint32_t)0x00000023)
|
||||
#define DMA1_REMAP_TIM2_CH4 ((uint32_t)0x00000024)
|
||||
#define DMA1_REMAP_TIM4_UP ((uint32_t)0x00000025)
|
||||
#define DMA1_REMAP_I2C1_RX ((uint32_t)0x00000026)
|
||||
#define DMA1_REMAP_ADC2 ((uint32_t)0x00000027)
|
||||
#define DMA1_REMAP_UART5_RX ((uint32_t)0x00000028)
|
||||
#define DMA2_REMAP_TIM5_CH4 ((uint32_t)0x00000000)
|
||||
#define DMA2_REMAP_TIM5_TRIG ((uint32_t)0x00000001)
|
||||
#define DMA2_REMAP_TIM8_CH3 ((uint32_t)0x00000002)
|
||||
#define DMA2_REMAP_TIM8_UP ((uint32_t)0x00000003)
|
||||
#define DMA2_REMAP_SPI_I2S3_RX ((uint32_t)0x00000004)
|
||||
#define DMA2_REMAP_UART6_RX ((uint32_t)0x00000005)
|
||||
#define DMA2_REMAP_TIM8_CH4 ((uint32_t)0x00000006)
|
||||
#define DMA2_REMAP_TIM8_TRIG ((uint32_t)0x00000007)
|
||||
#define DMA2_REMAP_TIM8_COM ((uint32_t)0x00000008)
|
||||
#define DMA2_REMAP_TIM5_CH3 ((uint32_t)0x00000009)
|
||||
#define DMA2_REMAP_TIM5_UP ((uint32_t)0x0000000A)
|
||||
#define DMA2_REMAP_SPI_I2S3_TX ((uint32_t)0x0000000B)
|
||||
#define DMA2_REMAP_UART6_TX ((uint32_t)0x0000000C)
|
||||
#define DMA2_REMAP_TIM8_CH1 ((uint32_t)0x0000000D)
|
||||
#define DMA2_REMAP_UART4_RX ((uint32_t)0x0000000E)
|
||||
#define DMA2_REMAP_TIM6_UP ((uint32_t)0x0000000F)
|
||||
#define DMA2_REMAP_DAC1 ((uint32_t)0x00000010)
|
||||
#define DMA2_REMAP_TIM5_CH2 ((uint32_t)0x00000011)
|
||||
#define DMA2_REMAP_SDIO ((uint32_t)0x00000012)
|
||||
#define DMA2_REMAP_TIM7_UP ((uint32_t)0x00000013)
|
||||
#define DMA2_REMAP_DAC2 ((uint32_t)0x00000014)
|
||||
#define DMA2_REMAP_ADC3 ((uint32_t)0x00000015)
|
||||
#define DMA2_REMAP_TIM8_CH2 ((uint32_t)0x00000016)
|
||||
#define DMA2_REMAP_TIM5_CH1 ((uint32_t)0x00000017)
|
||||
#define DMA2_REMAP_UART4_TX ((uint32_t)0x00000018)
|
||||
#define DMA2_REMAP_QSPI_RX ((uint32_t)0x00000019)
|
||||
#define DMA2_REMAP_I2C4_TX ((uint32_t)0x0000001A)
|
||||
#define DMA2_REMAP_UART7_RX ((uint32_t)0x0000001B)
|
||||
#define DMA2_REMAP_QSPI_TX ((uint32_t)0x0000001C)
|
||||
#define DMA2_REMAP_I2C4_RX ((uint32_t)0x0000001D)
|
||||
#define DMA2_REMAP_UART7_TX ((uint32_t)0x0000001E)
|
||||
#define DMA2_REMAP_ADC4 ((uint32_t)0x0000001F)
|
||||
#define DMA2_REMAP_DVP ((uint32_t)0x00000020)
|
||||
|
||||
#define IS_DMA_REMAP(FLAG) \
|
||||
(((FLAG) == DMA1_REMAP_ADC1) || ((FLAG) == DMA1_REMAP_UART5_TX) || ((FLAG) == DMA1_REMAP_I2C3_TX) \
|
||||
|| ((FLAG) == DMA1_REMAP_TIM2_CH3) || ((FLAG) == DMA1_REMAP_TIM4_CH1) || ((FLAG) == DMA1_REMAP_USART3_TX) \
|
||||
|| ((FLAG) == DMA1_REMAP_I2C3_RX) || ((FLAG) == DMA1_REMAP_TIM1_CH1) || ((FLAG) == DMA1_REMAP_TIM2_UP) \
|
||||
|| ((FLAG) == DMA1_REMAP_TIM3_CH3) || ((FLAG) == DMA1_REMAP_SPI1_RX) || ((FLAG) == DMA1_REMAP_USART3_RX) \
|
||||
|| ((FLAG) == DMA1_REMAP_TIM1_CH2) || ((FLAG) == DMA1_REMAP_TIM3_CH4) || ((FLAG) == DMA1_REMAP_TIM3_UP) \
|
||||
|| ((FLAG) == DMA1_REMAP_SPI1_TX) || ((FLAG) == DMA1_REMAP_USART1_TX) || ((FLAG) == DMA1_REMAP_TIM1_CH4) \
|
||||
|| ((FLAG) == DMA1_REMAP_TIM1_TRIG) || ((FLAG) == DMA1_REMAP_TIM1_COM) || ((FLAG) == DMA1_REMAP_TIM4_CH2) \
|
||||
|| ((FLAG) == DMA1_REMAP_SPI_I2S2_RX) || ((FLAG) == DMA1_REMAP_I2C2_TX) || ((FLAG) == DMA1_REMAP_USART1_RX) \
|
||||
|| ((FLAG) == DMA1_REMAP_TIM1_UP) || ((FLAG) == DMA1_REMAP_SPI_I2S2_TX) || ((FLAG) == DMA1_REMAP_TIM4_CH3) \
|
||||
|| ((FLAG) == DMA1_REMAP_I2C2_RX) || ((FLAG) == DMA1_REMAP_TIM2_CH1) || ((FLAG) == DMA1_REMAP_USART2_RX) \
|
||||
|| ((FLAG) == DMA1_REMAP_TIM1_CH3) || ((FLAG) == DMA1_REMAP_TIM3_CH1) || ((FLAG) == DMA1_REMAP_TIM3_TRIG) \
|
||||
|| ((FLAG) == DMA1_REMAP_I2C1_TX) || ((FLAG) == DMA1_REMAP_USART2_TX) || ((FLAG) == DMA1_REMAP_TIM2_CH2) \
|
||||
|| ((FLAG) == DMA1_REMAP_TIM2_CH4) || ((FLAG) == DMA1_REMAP_TIM4_UP) || ((FLAG) == DMA1_REMAP_I2C1_RX) \
|
||||
|| ((FLAG) == DMA1_REMAP_ADC2) || ((FLAG) == DMA1_REMAP_UART5_RX) || ((FLAG) == DMA2_REMAP_TIM5_CH4) \
|
||||
|| ((FLAG) == DMA2_REMAP_TIM5_TRIG) || ((FLAG) == DMA2_REMAP_TIM8_CH3) || ((FLAG) == DMA2_REMAP_TIM8_UP) \
|
||||
|| ((FLAG) == DMA2_REMAP_SPI_I2S3_RX) || ((FLAG) == DMA2_REMAP_UART6_RX) || ((FLAG) == DMA2_REMAP_TIM8_CH4) \
|
||||
|| ((FLAG) == DMA2_REMAP_TIM8_TRIG) || ((FLAG) == DMA2_REMAP_TIM8_COM) || ((FLAG) == DMA2_REMAP_TIM5_CH3) \
|
||||
|| ((FLAG) == DMA2_REMAP_TIM5_UP) || ((FLAG) == DMA2_REMAP_SPI_I2S3_TX) || ((FLAG) == DMA2_REMAP_UART6_TX) \
|
||||
|| ((FLAG) == DMA2_REMAP_TIM8_CH1) || ((FLAG) == DMA2_REMAP_UART4_RX) || ((FLAG) == DMA2_REMAP_TIM6_UP) \
|
||||
|| ((FLAG) == DMA2_REMAP_DAC1) || ((FLAG) == DMA2_REMAP_TIM5_CH2) || ((FLAG) == DMA2_REMAP_SDIO) \
|
||||
|| ((FLAG) == DMA2_REMAP_TIM7_UP) || ((FLAG) == DMA2_REMAP_DAC2) || ((FLAG) == DMA2_REMAP_ADC3) \
|
||||
|| ((FLAG) == DMA2_REMAP_TIM8_CH2) || ((FLAG) == DMA2_REMAP_TIM5_CH1) || ((FLAG) == DMA2_REMAP_UART4_TX) \
|
||||
|| ((FLAG) == DMA2_REMAP_QSPI_RX) || ((FLAG) == DMA2_REMAP_I2C4_TX) || ((FLAG) == DMA2_REMAP_UART7_RX) \
|
||||
|| ((FLAG) == DMA2_REMAP_QSPI_TX) || ((FLAG) == DMA2_REMAP_I2C4_RX) || ((FLAG) == DMA2_REMAP_UART7_TX) \
|
||||
|| ((FLAG) == DMA2_REMAP_ADC4) || ((FLAG) == DMA2_REMAP_DVP))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void DMA_DeInit(DMA_ChannelType* DMAyChx);
|
||||
void DMA_Init(DMA_ChannelType* DMAyChx, DMA_InitType* DMA_InitParam);
|
||||
void DMA_StructInit(DMA_InitType* DMA_InitParam);
|
||||
void DMA_EnableChannel(DMA_ChannelType* DMAyChx, FunctionalState Cmd);
|
||||
void CMA_ConfigInt(DMA_ChannelType* DMAyChx, uint32_t DMAInt, FunctionalState Cmd);
|
||||
void DMA_SetCurrDataCounter(DMA_ChannelType* DMAyChx, uint16_t DataNumber);
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAyChx);
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAyFlag, DMA_Module* DMAy);
|
||||
void DMA_ClearFlag(uint32_t DMAyFlag, DMA_Module* DMAy);
|
||||
INTStatus DMA_GetIntStatus(uint32_t DMAy_IT, DMA_Module* DMAy);
|
||||
void DMA_ClrIntPendingBit(uint32_t DMAy_IT, DMA_Module* DMAy);
|
||||
void DMA_RequestRemap(uint32_t DMAy_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAyChx, FunctionalState Cmd);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__N32G45X_DMA_H__ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,332 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_dvp.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __N32G45X_DVP_H__
|
||||
#define __N32G45X_DVP_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DVP
|
||||
* @brief DVP driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DVP_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief DVP Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FifoWatermark; /*!< It's will request INT or DMA when the datas reach this number in DATFIFO.*/
|
||||
|
||||
uint16_t LineCapture; /*!< Specifies the number of data line captuered in x lines.
|
||||
This parameter can be a value of @ref
|
||||
DVP_LineSelect_Mode */
|
||||
|
||||
uint16_t ByteCapture; /*!< Specifies the number of stop byte captuered in x bytes.
|
||||
This parameter can be a value of @ref
|
||||
DVP_ByteSelect_Mode */
|
||||
|
||||
uint16_t DataInvert; /*!< Specifies the data invert.
|
||||
This parameter can be a value of @ref
|
||||
DVP_DATA_INVERT */
|
||||
|
||||
uint16_t PixelClkPolarity; /*!< Specifies the pixel clock polarity
|
||||
This parameter can be a value of @ref
|
||||
DVP_Pixel_Polarity */
|
||||
|
||||
uint16_t VsyncPolarity; /*!< Specifies the vertical synchronization polarity
|
||||
This parameter can be a value of @ref
|
||||
DVP_Vsync_Polarity */
|
||||
|
||||
uint16_t HsyncPolarity; /*!< Specifies the Horizontal synchronization polarity
|
||||
This parameter can be a value of @ref
|
||||
DVP_Hsync_Polarity */
|
||||
|
||||
uint16_t CaptureMode; /*!< Specifies the capture mode.
|
||||
This parameter can be a value of @ref
|
||||
DVP_Capture_Mode */
|
||||
|
||||
uint16_t RowStart; /*!< Specifies the startint row of the pixel array in a frame */
|
||||
|
||||
uint16_t ColumnStart; /*!< Specifies the starting column of the pixel array row in a frame */
|
||||
|
||||
uint16_t ImageHeight; /*!< Specifies the image's height in a frame */
|
||||
|
||||
uint16_t ImageWidth; /*!< Specifies the image's width in a frame */
|
||||
|
||||
} DVP_InitType;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DVP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
#define IS_DVP_ALL_PERIPH(PERIPH) (((PERIPH) == DVP))
|
||||
|
||||
/** @addtogroup DVP_FIFO_SOFT_RESET
|
||||
* @{
|
||||
*/
|
||||
#define DVP_FIFO_SOFT_RESET ((uint32_t)0x10000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DVP_LineSelect_Mode
|
||||
* @{
|
||||
*/
|
||||
#define DVP_LSM_MASK (0xe00)
|
||||
#define DVP_LSM_POS (9)
|
||||
|
||||
#define DVP_LINE_CAPTURE_ALL ((uint32_t)0x0000)
|
||||
#define DVP_LINE_CAPTURE_1_2 ((uint32_t)0x0200)
|
||||
#define DVP_LINE_CAPTURE_1_3 ((uint32_t)0x0400)
|
||||
#define DVP_LINE_CAPTURE_1_4 ((uint32_t)0x0600)
|
||||
#define DVP_LINE_CAPTURE_1_5 ((uint32_t)0x0800)
|
||||
#define DVP_LINE_CAPTURE_1_6 ((uint32_t)0x0A00)
|
||||
#define DVP_LINE_CAPTURE_1_7 ((uint32_t)0x0C00)
|
||||
#define DVP_LINE_CAPTURE_1_8 ((uint32_t)0x0E00)
|
||||
#define IS_DVP_ROW_CAPTURE(LSM) \
|
||||
(((LSM) == DVP_LINE_CAPTURE_ALL) || ((LSM) == DVP_LINE_CAPTURE_1_2) || ((LSM) == DVP_LINE_CAPTURE_1_3) \
|
||||
|| ((LSM) == DVP_LINE_CAPTURE_1_4) || ((LSM) == DVP_LINE_CAPTURE_1_5) || ((LSM) == DVP_LINE_CAPTURE_1_6) \
|
||||
|| ((LSM) == DVP_LINE_CAPTURE_1_7) || ((LSM) == DVP_LINE_CAPTURE_1_8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DVP_ByteSelect_Mode
|
||||
* @{
|
||||
*/
|
||||
#define DVP_BSM_MASK (0x1c0)
|
||||
#define DVP_BSM_POS (6)
|
||||
#define DVP_BYTE_CAPTURE_ALL ((uint32_t)0x0000)
|
||||
#define DVP_BYTE_CAPTURE_1_2 ((uint32_t)0x0020)
|
||||
#define DVP_BYTE_CAPTURE_1_3 ((uint32_t)0x0040)
|
||||
#define DVP_BYTE_CAPTURE_1_4 ((uint32_t)0x0060)
|
||||
#define DVP_BYTE_CAPTURE_1_5 ((uint32_t)0x0080)
|
||||
#define DVP_BYTE_CAPTURE_1_6 ((uint32_t)0x00A0)
|
||||
#define DVP_BYTE_CAPTURE_1_7 ((uint32_t)0x00C0)
|
||||
#define DVP_BYTE_CAPTURE_1_8 ((uint32_t)0x00E0)
|
||||
#define IS_DVP_COLUMN_CAPTURE(BSM) \
|
||||
(((BSM) == DVP_BYTE_CAPTURE_ALL) || ((BSM) == DVP_BYTE_CAPTURE_1_2) || ((BSM) == DVP_BYTE_CAPTURE_1_3) \
|
||||
|| ((BSM) == DVP_BYTE_CAPTURE_1_4) || ((BSM) == DVP_BYTE_CAPTURE_1_5) || ((BSM) == DVP_BYTE_CAPTURE_1_6) \
|
||||
|| ((BSM) == DVP_BYTE_CAPTURE_1_7) || ((BSM) == DVP_BYTE_CAPTURE_1_8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DVP_DATA_INVERT
|
||||
* @{
|
||||
*/
|
||||
#define DVP_DATA_INVERT ((uint32_t)0x0020)
|
||||
#define DVP_DATA_NOTINVERT ((uint32_t)0x0000)
|
||||
#define IS_DVP_DATA_INVERT(DATINV) (((DATINV) == DVP_DATA_NOTINVERT) || ((DATINV) == DVP_DATA_INVERT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DVP_Pixel_Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DVP_PIXEL_POLARITY_FALLING ((uint32_t)0x0000)
|
||||
#define DVP_PIXEL_POLARITY_RISING ((uint32_t)0x0010)
|
||||
#define IS_DVP_PIXEL_POLARITY(PCKPOL) \
|
||||
(((PCKPOL) == DVP_PIXEL_POLARITY_FALLING) || ((PCKPOL) == DVP_PIXEL_POLARITY_RISING))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define DVP_WATER_MARK_POS ((uint32_t)12)
|
||||
#define DVP_WATER_MARK_MASK ((uint32_t)0xF000)
|
||||
#define IS_DVP_FIFOWATERMARK(WATERMARK) ((WATERMARK) > 0 && (WATERMARK) <= 4)
|
||||
|
||||
/** @addtogroup DVP_Vsync_Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DVP_VSYNC_POLARITY_HIGH ((uint32_t)0x0008)
|
||||
#define DVP_VSYNC_POLARITY_LOW ((uint32_t)0x0000)
|
||||
#define IS_DVP_VSYNC_POLARITY(VSYNCP) (((VSYNCP) == DVP_VSYNC_POLARITY_HIGH) || ((VSYNCP) == DVP_VSYNC_POLARITY_LOW))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DVP_Hsync_Polarity
|
||||
* @{
|
||||
*/
|
||||
#define DVP_HSYNC_POLARITY_HIGH ((uint32_t)0x0004)
|
||||
#define DVP_HSYNC_POLARITY_LOW ((uint32_t)0x0000)
|
||||
#define IS_DVP_HSYNC_POLARITY(HSYNCP) (((HSYNCP) == DVP_HSYNC_POLARITY_HIGH) || ((HSYNCP) == DVP_HSYNC_POLARITY_LOW))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DVP_Capture_Mode
|
||||
* @{
|
||||
*/
|
||||
#define DVP_CAPTURE_MODE_SINGLE ((uint32_t)0x0000)
|
||||
#define DVP_CAPTURE_MODE_CONTINUE ((uint32_t)0x0002)
|
||||
#define IS_DVP_CAPTURE_MODE(CMODE) (((CMODE) == DVP_CAPTURE_MODE_SINGLE) || ((CMODE) == DVP_CAPTURE_MODE_CONTINUE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DVP_CAPTURE_ENABLE
|
||||
* @{
|
||||
*/
|
||||
#define DVP_CAPTURE_DISABLE ((uint32_t)0x0000)
|
||||
#define DVP_CAPTURE_ENABLE ((uint32_t)0x0001)
|
||||
#define IS_DVP_CAPTURE(CAPTURE) (((CAPTURE) == DVP_CAPTURE_DISABLE) || ((CAPTURE) == DVP_CAPTURE_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DVP_DMA
|
||||
* @{
|
||||
*/
|
||||
#define DVP_DMA_DISABLE ((uint32_t)0x0000)
|
||||
#define DVP_DMA_ENABLE ((uint32_t)0x0400)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DVP_Marked_interrupt
|
||||
* @{
|
||||
*/
|
||||
#define DVP_FLAG_HERR ((uint32_t)0x0200)
|
||||
#define DVP_FLAG_VERR ((uint32_t)0x0100)
|
||||
#define DVP_FLAG_FO ((uint32_t)0x0080)
|
||||
#define DVP_FLAG_FW ((uint32_t)0x0040)
|
||||
#define DVP_FLAG_FF ((uint32_t)0x0020)
|
||||
#define DVP_FLAG_FE ((uint32_t)0x0010)
|
||||
#define DVP_FLAG_LE ((uint32_t)0x0008)
|
||||
#define DVP_FLAG_LS ((uint32_t)0x0004)
|
||||
#define DVP_FLAG_FME ((uint32_t)0x0002)
|
||||
#define DVP_FLAG_FMS ((uint32_t)0x0001)
|
||||
#define IS_DVP_FLAG(FLAG) \
|
||||
(((FLAG) == DVP_FLAG_FMS) || ((FLAG) == DVP_FLAG_FME) || ((FLAG) == DVP_FLAG_LS) || ((FLAG) == DVP_FLAG_LE) \
|
||||
|| ((FLAG) == DVP_FLAG_FE) || ((FLAG) == DVP_FLAG_FF) || ((FLAG) == DVP_FLAG_FW) || ((FLAG) == DVP_FLAG_FO) \
|
||||
|| ((FLAG) == DVP_FLAG_VERR) || ((FLAG) == DVP_FLAG_HERR))
|
||||
|
||||
#define IS_DVP_CLEAR_FLAG(FLAG) \
|
||||
(((FLAG) == DVP_FLAG_FMS) || ((FLAG) == DVP_FLAG_FME) || ((FLAG) == DVP_FLAG_LS) || ((FLAG) == DVP_FLAG_LE) \
|
||||
|| ((FLAG) == DVP_FLAG_FE) || ((FLAG) == DVP_FLAG_FO) || ((FLAG) == DVP_FLAG_VERR) || ((FLAG) == DVP_FLAG_HERR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DVP_Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define DVP_INT_HERR ((uint32_t)0x0200)
|
||||
#define DVP_INT_VERR ((uint32_t)0x0100)
|
||||
#define DVP_INT_FO ((uint32_t)0x0080)
|
||||
#define DVP_INT_FW ((uint32_t)0x0040)
|
||||
#define DVP_INT_FF ((uint32_t)0x0020)
|
||||
#define DVP_INT_FE ((uint32_t)0x0010)
|
||||
#define DVP_INT_LE ((uint32_t)0x0008)
|
||||
#define DVP_INT_LS ((uint32_t)0x0004)
|
||||
#define DVP_INT_FME ((uint32_t)0x0002)
|
||||
#define DVP_INT_FMS ((uint32_t)0x0001)
|
||||
#define IS_DVP_INT(IT) \
|
||||
(((IT) == DVP_INT_FMS) || ((IT) == DVP_INT_FME) || ((IT) == DVP_INT_LS) || ((IT) == DVP_INT_LE) \
|
||||
|| ((IT) == DVP_INT_FE) || ((IT) == DVP_INT_FF) || ((IT) == DVP_INT_FW) || ((IT) == DVP_INT_FO) \
|
||||
|| ((IT) == DVP_INT_VERR) || ((IT) == DVP_INT_HERR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DVP_Flag
|
||||
* @{
|
||||
*/
|
||||
#define DVP_MINT_HERR ((uint32_t)0x0200)
|
||||
#define DVP_MINT_VERR ((uint32_t)0x0100)
|
||||
#define DVP_MINT_FO ((uint32_t)0x0080)
|
||||
#define DVP_MINT_FW ((uint32_t)0x0040)
|
||||
#define DVP_MINT_FF ((uint32_t)0x0020)
|
||||
#define DVP_MINT_FE ((uint32_t)0x0010)
|
||||
#define DVP_MINT_LE ((uint32_t)0x0008)
|
||||
#define DVP_MINT_LS ((uint32_t)0x0004)
|
||||
#define DVP_MINT_FME ((uint32_t)0x0002)
|
||||
#define DVP_MINT_FMS ((uint32_t)0x0001)
|
||||
#define IS_DVP_MINT(Status) \
|
||||
(((Status) == DVP_MINT_FMS) || ((Status) == DVP_MINT_FME) || ((Status) == DVP_MINT_LS) \
|
||||
|| ((Status) == DVP_MINT_LE) || ((Status) == DVP_MINT_FE) || ((Status) == DVP_MINT_FF) \
|
||||
|| ((Status) == DVP_MINT_FW) || ((Status) == DVP_MINT_FO) || ((Status) == DVP_MINT_VERR) \
|
||||
|| ((Status) == DVP_MINT_HERR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DVP_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
void DVP_DeInit(DVP_Module* DVPx);
|
||||
FlagStatus DVP_GetFlagStatus(DVP_Module* DVPx, uint16_t DVP_FLAG);
|
||||
void DVP_ClrFlag(DVP_Module* DVPx, uint16_t DVP_FLAG);
|
||||
INTStatus DVP_GetIntStatus(DVP_Module* DVPx, uint16_t DVP_IT);
|
||||
void DVP_Init(DVP_Module* DVPx, DVP_InitType* DVP_InitStruct);
|
||||
void DVP_InitStruct(DVP_InitType* DVP_InitStruct);
|
||||
void DVP_Enable(DVP_Module* DVPx, FunctionalState Cmd);
|
||||
void DVP_EnableDma(DVP_Module* DVPx, FunctionalState Cmd);
|
||||
uint32_t DVP_ReadFifo(DVP_Module* DVPx);
|
||||
uint32_t DVP_GetFifoCount(DVP_Module* DVPx);
|
||||
void DVP_SetFifoWatermark(DVP_Module* DVPx, uint16_t Watermark);
|
||||
void DVP_ResetFifo(DVP_Module* DVPx);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,222 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_exti.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_EXTI_H__
|
||||
#define __N32G45X_EXTI_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief EXTI mode enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Mode_Interrupt = 0x00,
|
||||
EXTI_Mode_Event = 0x04
|
||||
} EXTI_ModeType;
|
||||
|
||||
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
|
||||
|
||||
/**
|
||||
* @brief EXTI Trigger enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Trigger_Rising = 0x08,
|
||||
EXTI_Trigger_Falling = 0x0C,
|
||||
EXTI_Trigger_Rising_Falling = 0x10
|
||||
} EXTI_TriggerType;
|
||||
|
||||
#define IS_EXTI_TRIGGER(TRIGGER) \
|
||||
(((TRIGGER) == EXTI_Trigger_Rising) || ((TRIGGER) == EXTI_Trigger_Falling) \
|
||||
|| ((TRIGGER) == EXTI_Trigger_Rising_Falling))
|
||||
/**
|
||||
* @brief EXTI Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
|
||||
This parameter can be any combination of @ref EXTI_Lines */
|
||||
|
||||
EXTI_ModeType EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTI_ModeType */
|
||||
|
||||
EXTI_TriggerType EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTI_ModeType */
|
||||
|
||||
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
} EXTI_InitType;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Lines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXTI_LINE0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
|
||||
#define EXTI_LINE1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
|
||||
#define EXTI_LINE2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
|
||||
#define EXTI_LINE3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
|
||||
#define EXTI_LINE4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
|
||||
#define EXTI_LINE5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
|
||||
#define EXTI_LINE6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
|
||||
#define EXTI_LINE7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
|
||||
#define EXTI_LINE8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
|
||||
#define EXTI_LINE9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
|
||||
#define EXTI_LINE10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
|
||||
#define EXTI_LINE11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
|
||||
#define EXTI_LINE12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
|
||||
#define EXTI_LINE13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
|
||||
#define EXTI_LINE14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
|
||||
#define EXTI_LINE15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
|
||||
#define EXTI_LINE16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
|
||||
#define EXTI_LINE17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||
#define EXTI_LINE18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS Wakeup from suspend event */
|
||||
#define EXTI_LINE19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
|
||||
#define EXTI_LINE20 ((uint32_t)0x100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
|
||||
#define EXTI_LINE21 ((uint32_t)0x200000) /*!< External interrupt line 21 Connected to the TSC event */
|
||||
|
||||
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFC00000) == 0x00) && ((LINE) != (uint16_t)0x00))
|
||||
#define IS_GET_EXTI_LINE(LINE) \
|
||||
(((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) \
|
||||
|| ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) \
|
||||
|| ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) \
|
||||
|| ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) \
|
||||
|| ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) \
|
||||
|| ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_TSSEL_Line
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_TSSEL_LINE_MASK ((uint32_t)0x00000)
|
||||
#define EXTI_TSSEL_LINE0 ((uint32_t)0x00000) /*!< External interrupt line 0 */
|
||||
#define EXTI_TSSEL_LINE1 ((uint32_t)0x00001) /*!< External interrupt line 1 */
|
||||
#define EXTI_TSSEL_LINE2 ((uint32_t)0x00002) /*!< External interrupt line 2 */
|
||||
#define EXTI_TSSEL_LINE3 ((uint32_t)0x00003) /*!< External interrupt line 3 */
|
||||
#define EXTI_TSSEL_LINE4 ((uint32_t)0x00004) /*!< External interrupt line 4 */
|
||||
#define EXTI_TSSEL_LINE5 ((uint32_t)0x00005) /*!< External interrupt line 5 */
|
||||
#define EXTI_TSSEL_LINE6 ((uint32_t)0x00006) /*!< External interrupt line 6 */
|
||||
#define EXTI_TSSEL_LINE7 ((uint32_t)0x00007) /*!< External interrupt line 7 */
|
||||
#define EXTI_TSSEL_LINE8 ((uint32_t)0x00008) /*!< External interrupt line 8 */
|
||||
#define EXTI_TSSEL_LINE9 ((uint32_t)0x00009) /*!< External interrupt line 9 */
|
||||
#define EXTI_TSSEL_LINE10 ((uint32_t)0x0000A) /*!< External interrupt line 10 */
|
||||
#define EXTI_TSSEL_LINE11 ((uint32_t)0x0000B) /*!< External interrupt line 11 */
|
||||
#define EXTI_TSSEL_LINE12 ((uint32_t)0x0000C) /*!< External interrupt line 12 */
|
||||
#define EXTI_TSSEL_LINE13 ((uint32_t)0x0000D) /*!< External interrupt line 13 */
|
||||
#define EXTI_TSSEL_LINE14 ((uint32_t)0x0000E) /*!< External interrupt line 14 */
|
||||
#define EXTI_TSSEL_LINE15 ((uint32_t)0x0000F) /*!< External interrupt line 15 */
|
||||
|
||||
#define IS_EXTI_TSSEL_LINE(LINE) \
|
||||
(((LINE) == EXTI_TSSEL_LINE0) || ((LINE) == EXTI_TSSEL_LINE1) || ((LINE) == EXTI_TSSEL_LINE2) \
|
||||
|| ((LINE) == EXTI_TSSEL_LINE3) || ((LINE) == EXTI_TSSEL_LINE4) || ((LINE) == EXTI_TSSEL_LINE5) \
|
||||
|| ((LINE) == EXTI_TSSEL_LINE6) || ((LINE) == EXTI_TSSEL_LINE7) || ((LINE) == EXTI_TSSEL_LINE8) \
|
||||
|| ((LINE) == EXTI_TSSEL_LINE9) || ((LINE) == EXTI_TSSEL_LINE10) || ((LINE) == EXTI_TSSEL_LINE11) \
|
||||
|| ((LINE) == EXTI_TSSEL_LINE12) || ((LINE) == EXTI_TSSEL_LINE13) || ((LINE) == EXTI_TSSEL_LINE14) \
|
||||
|| ((LINE) == EXTI_TSSEL_LINE15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void EXTI_DeInit(void);
|
||||
void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct);
|
||||
void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct);
|
||||
void EXTI_TriggerSWInt(uint32_t EXTI_Line);
|
||||
FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line);
|
||||
void EXTI_ClrStatusFlag(uint32_t EXTI_Line);
|
||||
INTStatus EXTI_GetITStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClrITPendBit(uint32_t EXTI_Line);
|
||||
void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __N32G45X_EXTI_H__ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,366 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_flash.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_FLASH_H__
|
||||
#define __N32G45X_FLASH_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Status
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
FLASH_BUSY = 1,
|
||||
FLASH_ERR_RDKEY,
|
||||
FLASH_ERR_PG,
|
||||
FLASH_ERR_PV,
|
||||
FLASH_ERR_WRP,
|
||||
FLASH_COMPL,
|
||||
FLASH_ERR_EV,
|
||||
FLASH_ERR_ECC,
|
||||
FLASH_TIMEOUT
|
||||
} FLASH_STS;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
FLASH_SMP1 = 0,
|
||||
FLASH_SMP2
|
||||
} FLASH_SMPSEL;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Flash_Latency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_LATENCY_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_LATENCY_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */
|
||||
#define FLASH_LATENCY_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */
|
||||
#define FLASH_LATENCY_3 ((uint32_t)0x00000003) /*!< FLASH Three Latency cycles */
|
||||
#define FLASH_LATENCY_4 ((uint32_t)0x00000004) /*!< FLASH Four Latency cycles */
|
||||
#define FLASH_LATENCY_5 ((uint32_t)0x00000005) /*!< FLASH Five Latency cycles */
|
||||
#define IS_FLASH_LATENCY(LATENCY) \
|
||||
(((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || ((LATENCY) == FLASH_LATENCY_2) \
|
||||
|| ((LATENCY) == FLASH_LATENCY_3) || ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Prefetch_Buffer_Enable_Disable
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_PrefetchBuf_EN ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */
|
||||
#define FLASH_PrefetchBuf_DIS ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */
|
||||
#define IS_FLASH_PREFETCHBUF_STATE(STATE) (((STATE) == FLASH_PrefetchBuf_EN) || ((STATE) == FLASH_PrefetchBuf_DIS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup iCache_Enable_Disable
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_iCache_EN ((uint32_t)0x00000080) /*!< FLASH iCache Enable */
|
||||
#define FLASH_iCache_DIS ((uint32_t)0x00000000) /*!< FLASH iCache Disable */
|
||||
#define IS_FLASH_ICACHE_STATE(STATE) (((STATE) == FLASH_iCache_EN) || ((STATE) == FLASH_iCache_DIS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SMPSEL_SMP1_SMP2
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_SMPSEL_SMP1 ((uint32_t)0x00000000) /*!< FLASH SMPSEL SMP1 */
|
||||
#define FLASH_SMPSEL_SMP2 ((uint32_t)0x00000100) /*!< FLASH SMPSEL SMP2 */
|
||||
#define IS_FLASH_SMPSEL_STATE(STATE) (((STATE) == FLASH_SMPSEL_SMP1) || ((STATE) == FLASH_SMPSEL_SMP2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Values to be used with N32G45X devices */
|
||||
#define FLASH_WRPR_Pages0to1 \
|
||||
((uint32_t)0x00000001) /*!< N32G45X devices: \
|
||||
Write protection of page 0 to 1 */
|
||||
#define FLASH_WRPR_Pages2to3 \
|
||||
((uint32_t)0x00000002) /*!< N32G45X devices: \
|
||||
Write protection of page 2 to 3 */
|
||||
#define FLASH_WRPR_Pages4to5 \
|
||||
((uint32_t)0x00000004) /*!< N32G45X devices: \
|
||||
Write protection of page 4 to 5 */
|
||||
#define FLASH_WRPR_Pages6to7 \
|
||||
((uint32_t)0x00000008) /*!< N32G45X devices: \
|
||||
Write protection of page 6 to 7 */
|
||||
#define FLASH_WRPR_Pages8to9 \
|
||||
((uint32_t)0x00000010) /*!< N32G45X devices: \
|
||||
Write protection of page 8 to 9 */
|
||||
#define FLASH_WRPR_Pages10to11 \
|
||||
((uint32_t)0x00000020) /*!< N32G45X devices: \
|
||||
Write protection of page 10 to 11 */
|
||||
#define FLASH_WRPR_Pages12to13 \
|
||||
((uint32_t)0x00000040) /*!< N32G45X devices: \
|
||||
Write protection of page 12 to 13 */
|
||||
#define FLASH_WRPR_Pages14to15 \
|
||||
((uint32_t)0x00000080) /*!< N32G45X devices: \
|
||||
Write protection of page 14 to 15 */
|
||||
#define FLASH_WRPR_Pages16to17 \
|
||||
((uint32_t)0x00000100) /*!< N32G45X devices: \
|
||||
Write protection of page 16 to 17 */
|
||||
#define FLASH_WRPR_Pages18to19 \
|
||||
((uint32_t)0x00000200) /*!< N32G45X devices: \
|
||||
Write protection of page 18 to 19 */
|
||||
#define FLASH_WRPR_Pages20to21 \
|
||||
((uint32_t)0x00000400) /*!< N32G45X devices: \
|
||||
Write protection of page 20 to 21 */
|
||||
#define FLASH_WRPR_Pages22to23 \
|
||||
((uint32_t)0x00000800) /*!< N32G45X devices: \
|
||||
Write protection of page 22 to 23 */
|
||||
#define FLASH_WRPR_Pages24to25 \
|
||||
((uint32_t)0x00001000) /*!< N32G45X devices: \
|
||||
Write protection of page 24 to 25 */
|
||||
#define FLASH_WRPR_Pages26to27 \
|
||||
((uint32_t)0x00002000) /*!< N32G45X devices: \
|
||||
Write protection of page 26 to 27 */
|
||||
#define FLASH_WRPR_Pages28to29 \
|
||||
((uint32_t)0x00004000) /*!< N32G45X devices: \
|
||||
Write protection of page 28 to 29 */
|
||||
#define FLASH_WRPR_Pages30to31 \
|
||||
((uint32_t)0x00008000) /*!< N32G45X devices: \
|
||||
Write protection of page 30 to 31 */
|
||||
#define FLASH_WRPR_Pages32to33 \
|
||||
((uint32_t)0x00010000) /*!< N32G45X devices: \
|
||||
Write protection of page 32 to 33 */
|
||||
#define FLASH_WRPR_Pages34to35 \
|
||||
((uint32_t)0x00020000) /*!< N32G45X devices: \
|
||||
Write protection of page 34 to 35 */
|
||||
#define FLASH_WRPR_Pages36to37 \
|
||||
((uint32_t)0x00040000) /*!< N32G45X devices: \
|
||||
Write protection of page 36 to 37 */
|
||||
#define FLASH_WRPR_Pages38to39 \
|
||||
((uint32_t)0x00080000) /*!< N32G45X devices: \
|
||||
Write protection of page 38 to 39 */
|
||||
#define FLASH_WRPR_Pages40to41 \
|
||||
((uint32_t)0x00100000) /*!< N32G45X devices: \
|
||||
Write protection of page 40 to 41 */
|
||||
#define FLASH_WRPR_Pages42to43 \
|
||||
((uint32_t)0x00200000) /*!< N32G45X devices: \
|
||||
Write protection of page 42 to 43 */
|
||||
#define FLASH_WRPR_Pages44to45 \
|
||||
((uint32_t)0x00400000) /*!< N32G45X devices: \
|
||||
Write protection of page 44 to 45 */
|
||||
#define FLASH_WRPR_Pages46to47 \
|
||||
((uint32_t)0x00800000) /*!< N32G45X devices: \
|
||||
Write protection of page 46 to 47 */
|
||||
#define FLASH_WRPR_Pages48to49 \
|
||||
((uint32_t)0x01000000) /*!< N32G45X devices: \
|
||||
Write protection of page 48 to 49 */
|
||||
#define FLASH_WRPR_Pages50to51 \
|
||||
((uint32_t)0x02000000) /*!< N32G45X devices: \
|
||||
Write protection of page 50 to 51 */
|
||||
#define FLASH_WRPR_Pages52to53 \
|
||||
((uint32_t)0x04000000) /*!< N32G45X devices: \
|
||||
Write protection of page 52 to 53 */
|
||||
#define FLASH_WRPR_Pages54to55 \
|
||||
((uint32_t)0x08000000) /*!< N32G45X devices: \
|
||||
Write protection of page 54 to 55 */
|
||||
#define FLASH_WRPR_Pages56to57 \
|
||||
((uint32_t)0x10000000) /*!< N32G45X devices: \
|
||||
Write protection of page 56 to 57 */
|
||||
#define FLASH_WRPR_Pages58to59 \
|
||||
((uint32_t)0x20000000) /*!< N32G45X devices: \
|
||||
Write protection of page 58 to 59 */
|
||||
#define FLASH_WRPR_Pages60to61 \
|
||||
((uint32_t)0x40000000) /*!< N32G45X devices: \
|
||||
Write protection of page 60 to 61 */
|
||||
#define FLASH_WRPR_Pages62to127 \
|
||||
((uint32_t)0x80000000) /*!< N32G45X - 256KB devices: Write protection of page 62 to 127 */
|
||||
#define FLASH_WRPR_Pages62to255 \
|
||||
((uint32_t)0x80000000) /*!< N32G45X - 512KB devices: Write protection of page 62 to 255 */
|
||||
|
||||
#define FLASH_WRPR_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */
|
||||
|
||||
#define IS_FLASH_WRPR_PAGE(PAGE) (((PAGE) != 0x00000000))
|
||||
|
||||
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))
|
||||
|
||||
#define IS_OB_DATA_ADDRESS(ADDRESS) ((ADDRESS) == 0x1FFFF804)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Option_Bytes_IWatchdog
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Option_Bytes_nRST_STOP
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_STOP0_NORST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP0_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
|
||||
#define IS_OB_STOP0_SOURCE(SOURCE) (((SOURCE) == OB_STOP0_NORST) || ((SOURCE) == OB_STOP0_RST))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Option_Bytes_nRST_STDBY
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_STDBY_NORST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NORST) || ((SOURCE) == OB_STDBY_RST))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @addtogroup FLASH_Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_INT_ERRIE ((uint32_t)0x00000400) /*!< PGERR WRPRTERR ERROR error interrupt source */
|
||||
#define FLASH_INT_FERR ((uint32_t)0x00000800) /*!< EVERR PVERR ECCERR interrupt source */
|
||||
#define FLASH_INT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */
|
||||
#define FLASH_INT_ECCERRIE ((uint32_t)0x00002000) /*!< ECC error Interrupt source */
|
||||
|
||||
#define IS_FLASH_INT(IT) ((((IT) & (uint32_t)0xFFFFC3FF) == 0x00000000) && (((IT) != 0x00000000)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Flags
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_FLAG_BUSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_RDKEYERR ((uint32_t)0x00000002) /*!< FLASH Read Key error flag */
|
||||
#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */
|
||||
#define FLASH_FLAG_PVERR ((uint32_t)0x00000008) /*!< FLASH Program Verify ERROR flag after program */
|
||||
#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */
|
||||
#define FLASH_FLAG_EVERR ((uint32_t)0x00000040) /*!< FLASH Erase Verify ERROR flag after page erase */
|
||||
#define FLASH_FLAG_ECCERR ((uint32_t)0x00000080) /*!< FLASH ECC ERROR flag when Flash Reading */
|
||||
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */
|
||||
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF00) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
#define IS_FLASH_GET_FLAG(FLAG) \
|
||||
(((FLAG) == FLASH_FLAG_BUSY) || ((FLAG) == FLASH_FLAG_RDKEYERR) || ((FLAG) == FLASH_FLAG_PGERR) \
|
||||
|| ((FLAG) == FLASH_FLAG_PVERR) || ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP) \
|
||||
|| ((FLAG) == FLASH_FLAG_EVERR) || ((FLAG) == FLASH_FLAG_ECCERR) || ((FLAG) == FLASH_FLAG_OPTERR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*------------ Functions used for N32G45X devices -----*/
|
||||
void FLASH_SetLatency(uint32_t FLASH_Latency);
|
||||
void FLASH_PrefetchBufSet(uint32_t FLASH_PrefetchBuf);
|
||||
void FLASH_iCacheRST(void);
|
||||
void FLASH_iCacheCmd(uint32_t FLASH_iCache);
|
||||
void FLASH_Unlock(void);
|
||||
void FLASH_Lock(void);
|
||||
FLASH_STS FLASH_EraseOnePage(uint32_t Page_Address);
|
||||
FLASH_STS FLASH_MassErase(void);
|
||||
FLASH_STS FLASH_EraseOB(void);
|
||||
FLASH_STS FLASH_ProgramWord(uint32_t Address, uint32_t Data);
|
||||
FLASH_STS FLASH_ProgramOBData(uint32_t Address, uint32_t Data);
|
||||
FLASH_STS FLASH_EnWriteProtection(uint32_t FLASH_Pages);
|
||||
FLASH_STS FLASH_ReadOutProtectionL1(FunctionalState Cmd);
|
||||
FLASH_STS FLASH_ReadOutProtectionL2(FunctionalState Cmd);
|
||||
FLASH_STS FLASH_ConfigUserOB(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
|
||||
uint32_t FLASH_GetUserOB(void);
|
||||
uint32_t FLASH_GetWriteProtectionOB(void);
|
||||
FlagStatus FLASH_GetReadOutProtectionSTS(void);
|
||||
FlagStatus FLASH_GetPrefetchBufSTS(void);
|
||||
FLASH_SMPSEL FLASH_GetSMPSELStatus(void);
|
||||
void FLASH_INTConfig(uint32_t FLASH_INT, FunctionalState Cmd);
|
||||
FlagStatus FLASH_GetFlagSTS(uint32_t FLASH_FLAG);
|
||||
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
|
||||
FLASH_STS FLASH_GetSTS(void);
|
||||
FLASH_STS FLASH_WaitForLastOpt(uint32_t Timeout);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __N32G45X_FLASH_H__ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,468 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_gpio.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_GPIO_H__
|
||||
#define __N32G45X_GPIO_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_GPIO_ALL_PERIPH(PERIPH) \
|
||||
(((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD) || ((PERIPH) == GPIOE) \
|
||||
|| ((PERIPH) == GPIOF) || ((PERIPH) == GPIOG))
|
||||
|
||||
/**
|
||||
* @brief Output Maximum frequency selection
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
GPIO_INPUT = 0,
|
||||
GPIO_Speed_2MHz = 1,
|
||||
GPIO_Speed_10MHz,
|
||||
GPIO_Speed_50MHz
|
||||
} GPIO_SpeedType;
|
||||
#define IS_GPIO_SPEED(SPEED) \
|
||||
(((SPEED) == GPIO_INPUT) || ((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) \
|
||||
|| ((SPEED) == GPIO_Speed_50MHz))
|
||||
|
||||
/**
|
||||
* @brief Configuration Mode enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Mode_AIN = 0x0,
|
||||
GPIO_Mode_IN_FLOATING = 0x04,
|
||||
GPIO_Mode_IPD = 0x28,
|
||||
GPIO_Mode_IPU = 0x48,
|
||||
GPIO_Mode_Out_OD = 0x14,
|
||||
GPIO_Mode_Out_PP = 0x10,
|
||||
GPIO_Mode_AF_OD = 0x1C,
|
||||
GPIO_Mode_AF_PP = 0x18
|
||||
} GPIO_ModeType;
|
||||
|
||||
#define IS_GPIO_MODE(MODE) \
|
||||
(((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || ((MODE) == GPIO_Mode_IPD) \
|
||||
|| ((MODE) == GPIO_Mode_IPU) || ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) \
|
||||
|| ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
GPIO_SpeedType GPIO_Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_SpeedType */
|
||||
|
||||
GPIO_ModeType GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_ModeType */
|
||||
} GPIO_InitType;
|
||||
|
||||
/**
|
||||
* @brief Bit_SET and Bit_RESET enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
Bit_RESET = 0,
|
||||
Bit_SET
|
||||
} Bit_OperateType;
|
||||
|
||||
#define IS_GPIO_BIT_OPERATE(OPERATE) (((OPERATE) == Bit_RESET) || ((OPERATE) == Bit_SET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_pins_define
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
|
||||
#define GPIO_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
|
||||
#define GPIO_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
|
||||
#define GPIO_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
|
||||
#define GPIO_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
|
||||
#define GPIO_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
|
||||
#define GPIO_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
|
||||
#define GPIO_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
|
||||
#define GPIO_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
|
||||
#define GPIO_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
|
||||
#define GPIO_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
|
||||
#define GPIO_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
|
||||
#define GPIO_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
|
||||
#define GPIO_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
|
||||
#define GPIO_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
|
||||
#define GPIO_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
|
||||
#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */
|
||||
|
||||
#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
|
||||
|
||||
#define IS_GET_GPIO_PIN(PIN) \
|
||||
(((PIN) == GPIO_PIN_0) || ((PIN) == GPIO_PIN_1) || ((PIN) == GPIO_PIN_2) || ((PIN) == GPIO_PIN_3) \
|
||||
|| ((PIN) == GPIO_PIN_4) || ((PIN) == GPIO_PIN_5) || ((PIN) == GPIO_PIN_6) || ((PIN) == GPIO_PIN_7) \
|
||||
|| ((PIN) == GPIO_PIN_8) || ((PIN) == GPIO_PIN_9) || ((PIN) == GPIO_PIN_10) || ((PIN) == GPIO_PIN_11) \
|
||||
|| ((PIN) == GPIO_PIN_12) || ((PIN) == GPIO_PIN_13) || ((PIN) == GPIO_PIN_14) || ((PIN) == GPIO_PIN_15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Remap_define
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_RMP_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */
|
||||
#define GPIO_RMP_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */
|
||||
#define GPIO_RMP_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */
|
||||
#define GPIO_RMP_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */
|
||||
#define GPIO_PART_RMP_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */
|
||||
#define GPIO_ALL_RMP_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */
|
||||
#define GPIO_PART1_RMP_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */
|
||||
#define GPIO_PART2_RMP_TIM1 ((uint32_t)0x00160080) /*!< TIM1 Partial Alternate Function mapping */
|
||||
#define GPIO_ALL_RMP_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */
|
||||
#define GPIO_PART2_RMP_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */
|
||||
#define GPIO_ALL_RMP_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */
|
||||
#define GPIO_PART1_RMP_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */
|
||||
#define GPIO_ALL_RMP_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */
|
||||
#define GPIO_RMP_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */
|
||||
#define GPIO_RMP1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */
|
||||
#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */
|
||||
#define GPIO_Remap3_CAN1 ((uint32_t)0x001D2000) /*!< CAN1 Alternate Function mapping */
|
||||
#define GPIO_RMP_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */
|
||||
#define GPIO_RMP_TIM5CH4 ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */
|
||||
#define GPIO_RMP_ADC1_ETRI ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */
|
||||
#define GPIO_RMP_ADC1_ETRR ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */
|
||||
#define GPIO_RMP_ADC2_ETRI ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */
|
||||
#define GPIO_RMP_ADC2_ETRR ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */
|
||||
#define GPIO_RMP_MII_RMII_SEL ((uint32_t)0x00200080) /*!< MII_RMII_SEL remapping */
|
||||
#define GPIO_RMP_SW_JTAG_NO_NJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
|
||||
#define GPIO_RMP_SW_JTAG_SW_ENABLE ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */
|
||||
#define GPIO_RMP_SW_JTAG_DISABLE ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */
|
||||
|
||||
/* AFIO_RMP_CFG2 */
|
||||
#define GPIO_Remap_XFMC_NADV ((uint32_t)0x80000400) /*!< XFMC_NADV Alternate Function mapping */
|
||||
|
||||
/* AFIO_RMP_CFG3 */
|
||||
#define GPIO_RMP_SDIO ((uint32_t)0x40000001) /*!< SDIO Alternate Function mapping */
|
||||
#define GPIO_RMP1_CAN2 ((uint32_t)0x40110002) /*!< CAN2 Alternate Function mapping */
|
||||
#define GPIO_RMP3_CAN2 ((uint32_t)0x40110006) /*!< CAN2 Alternate Function mapping */
|
||||
#define GPIO_RMP1_QSPI ((uint32_t)0x40140020) /*!< QSPI Alternate Function mapping */
|
||||
#define GPIO_RMP3_QSPI ((uint32_t)0x40140030) /*!< QSPI Alternate Function mapping */
|
||||
#define GPIO_RMP1_I2C2 ((uint32_t)0x40160040) /*!< I2C2 Alternate Function mapping */
|
||||
#define GPIO_RMP3_I2C2 ((uint32_t)0x401600C0) /*!< I2C2 Alternate Function mapping */
|
||||
#define GPIO_RMP2_I2C3 ((uint32_t)0x40180200) /*!< I2C3 Alternate Function mapping */
|
||||
#define GPIO_RMP3_I2C3 ((uint32_t)0x40180300) /*!< I2C3 Alternate Function mapping */
|
||||
#define GPIO_RMP1_I2C4 ((uint32_t)0x401A0400) /*!< I2C4 Alternate Function mapping */
|
||||
#define GPIO_RMP3_I2C4 ((uint32_t)0x401A0C00) /*!< I2C4 Alternate Function mapping */
|
||||
#define GPIO_RMP1_SPI2 ((uint32_t)0x401C1000) /*!< SPI2 Alternate Function mapping */
|
||||
#define GPIO_RMP2_SPI2 ((uint32_t)0x401C3000) /*!< SPI2 Alternate Function mapping */
|
||||
#define GPIO_RMP1_SPI3 ((uint32_t)0x401E4000) /*!< SPI3 Alternate Function mapping */
|
||||
#define GPIO_RMP2_SPI3 ((uint32_t)0x401E8000) /*!< SPI3 Alternate Function mapping */
|
||||
#define GPIO_RMP3_SPI3 ((uint32_t)0x401EC000) /*!< SPI3 Alternate Function mapping */
|
||||
#define GPIO_RMP1_ETH ((uint32_t)0x40300001) /*!< ETH Alternate Function mapping */
|
||||
#define GPIO_RMP2_ETH ((uint32_t)0x40300002) /*!< ETH Alternate Function mapping */
|
||||
#define GPIO_RMP3_ETH ((uint32_t)0x40300003) /*!< ETH Alternate Function mapping */
|
||||
#define GPIO_RMP1_SPI1 ((uint32_t)0x41200000) /*!< SPI1 Alternate Function mapping */
|
||||
#define GPIO_RMP2_SPI1 ((uint32_t)0x41200004) /*!< SPI1 Alternate Function mapping */
|
||||
#define GPIO_RMP3_SPI1 ((uint32_t)0x43200004) /*!< SPI1 Alternate Function mapping */
|
||||
#define GPIO_RMP1_USART2 ((uint32_t)0x44200000) /*!< USART2 Alternate Function mapping */
|
||||
#define GPIO_RMP2_USART2 ((uint32_t)0x44200008) /*!< USART2 Alternate Function mapping */
|
||||
#define GPIO_RMP3_USART2 ((uint32_t)0x46200008) /*!< USART2 Alternate Function mapping */
|
||||
#define GPIO_RMP1_UART4 ((uint32_t)0x40340010) /*!< UART4 Alternate Function mapping */
|
||||
#define GPIO_RMP2_UART4 ((uint32_t)0x40340020) /*!< UART4 Alternate Function mapping */
|
||||
#define GPIO_RMP3_UART4 ((uint32_t)0x40340030) /*!< UART4 Alternate Function mapping */
|
||||
#define GPIO_RMP1_UART5 ((uint32_t)0x40360040) /*!< UART5 Alternate Function mapping */
|
||||
#define GPIO_RMP2_UART5 ((uint32_t)0x40360080) /*!< UART5 Alternate Function mapping */
|
||||
#define GPIO_RMP3_UART5 ((uint32_t)0x403600C0) /*!< UART5 Alternate Function mapping */
|
||||
#define GPIO_RMP2_UART6 ((uint32_t)0x40380200) /*!< UART6 Alternate Function mapping */
|
||||
#define GPIO_RMP3_UART6 ((uint32_t)0x40380300) /*!< UART6 Alternate Function mapping */
|
||||
#define GPIO_RMP1_UART7 ((uint32_t)0x403A0400) /*!< UART7 Alternate Function mapping */
|
||||
#define GPIO_RMP3_UART7 ((uint32_t)0x403A0C00) /*!< UART7 Alternate Function mapping */
|
||||
#define GPIO_RMP1_XFMC ((uint32_t)0x403C1000) /*!< XFMC Alternate Function mapping */
|
||||
#define GPIO_RMP3_XFMC ((uint32_t)0x403C3000) /*!< XFMC Alternate Function mapping */
|
||||
#define GPIO_RMP1_TIM8 ((uint32_t)0x403E4000) /*!< TIM8 Alternate Function mapping */
|
||||
#define GPIO_RMP3_TIM8 ((uint32_t)0x403EC000) /*!< TIM8 Alternate Function mapping */
|
||||
|
||||
/* AFIO_RMP_CFG4 */
|
||||
#define GPIO_RMP1_COMP1 ((uint32_t)0x20100001) /*!< COMP1 Alternate Function mapping */
|
||||
#define GPIO_RMP2_COMP1 ((uint32_t)0x20100002) /*!< COMP1 Alternate Function mapping */
|
||||
#define GPIO_RMP3_COMP1 ((uint32_t)0x20100003) /*!< COMP1 Alternate Function mapping */
|
||||
#define GPIO_RMP1_COMP2 ((uint32_t)0x20120004) /*!< COMP2 Alternate Function mapping */
|
||||
#define GPIO_RMP2_COMP2 ((uint32_t)0x20120008) /*!< COMP2 Alternate Function mapping */
|
||||
#define GPIO_RMP3_COMP2 ((uint32_t)0x2012000C) /*!< COMP2 Alternate Function mapping */
|
||||
#define GPIO_RMP1_COMP3 ((uint32_t)0x20140010) /*!< COMP3 Alternate Function mapping */
|
||||
#define GPIO_RMP3_COMP3 ((uint32_t)0x20140030) /*!< COMP3 Alternate Function mapping */
|
||||
#define GPIO_RMP1_COMP4 ((uint32_t)0x20160040) /*!< COMP4 Alternate Function mapping */
|
||||
#define GPIO_RMP3_COMP4 ((uint32_t)0x201600C0) /*!< COMP4 Alternate Function mapping */
|
||||
#define GPIO_RMP1_COMP5 ((uint32_t)0x20180100) /*!< COMP5 Alternate Function mapping */
|
||||
#define GPIO_RMP2_COMP5 ((uint32_t)0x20180200) /*!< COMP5 Alternate Function mapping */
|
||||
#define GPIO_RMP3_COMP5 ((uint32_t)0x20180300) /*!< COMP5 Alternate Function mapping */
|
||||
#define GPIO_RMP1_COMP6 ((uint32_t)0x201A0400) /*!< COMP6 Alternate Function mapping */
|
||||
#define GPIO_RMP3_COMP6 ((uint32_t)0x201A0C00) /*!< COMP6 Alternate Function mapping */
|
||||
#define GPIO_RMP_COMP7 ((uint32_t)0x20001000) /*!< COMP7 Alternate Function mapping */
|
||||
#define GPIO_RMP_ADC3_ETRI ((uint32_t)0x20004000) /*!< ADC3_ETRGINJ Alternate Function mapping */
|
||||
#define GPIO_RMP_ADC3_ETRR ((uint32_t)0x20008000) /*!< ADC3_ETRGREG Alternate Function mapping */
|
||||
#define GPIO_RMP_ADC4_ETRI ((uint32_t)0x20200001) /*!< ADC4_ETRGINJ Alternate Function mapping */
|
||||
#define GPIO_RMP_ADC4_ETRR ((uint32_t)0x20200002) /*!< ADC4_ETRGREG Alternate Function mapping */
|
||||
#define GPIO_RMP_TSC_OUT_CTRL ((uint32_t)0x20200004) /*!< TSC_OUT_CTRL Alternate Function mapping */
|
||||
#define GPIO_RMP_QSPI_XIP_EN ((uint32_t)0x20200008) /*!< QSPI_XIP_EN Alternate Function mapping */
|
||||
#define GPIO_RMP1_DVP ((uint32_t)0x20340010) /*!< DVP Alternate Function mapping */
|
||||
#define GPIO_RMP3_DVP ((uint32_t)0x20340030) /*!< DVP Alternate Function mapping */
|
||||
#define GPIO_Remap_SPI1_NSS ((uint32_t)0x20200040) /*!< SPI1 NSS Alternate Function mapping */
|
||||
#define GPIO_Remap_SPI2_NSS ((uint32_t)0x20200080) /*!< SPI2 NSS Alternate Function mapping */
|
||||
#define GPIO_Remap_SPI3_NSS ((uint32_t)0x20200100) /*!< SPI3 NSS Alternate Function mapping */
|
||||
#define GPIO_Remap_QSPI_MISO ((uint32_t)0x20200200) /*!< QSPI MISO Alternate Function mapping */
|
||||
|
||||
/* AFIO_RMP_CFG5 */
|
||||
#define GPIO_Remap_DET_EN_EGB4 ((uint32_t)0x10200080) /*!< EGB4 Detect Alternate Function mapping*/
|
||||
#define GPIO_Remap_DET_EN_EGB3 ((uint32_t)0x10200040) /*!< EGB4 Detect Alternate Function mapping*/
|
||||
#define GPIO_Remap_DET_EN_EGB2 ((uint32_t)0x10200020) /*!< EGB4 Detect Alternate Function mapping*/
|
||||
#define GPIO_Remap_DET_EN_EGB1 ((uint32_t)0x10200010) /*!< EGB4 Detect Alternate Function mapping*/
|
||||
#define GPIO_Remap_DET_EN_EGBN4 ((uint32_t)0x10200008) /*!< EGBN4 Detect Alternate Function mapping*/
|
||||
#define GPIO_Remap_DET_EN_EGBN3 ((uint32_t)0x10200004) /*!< EGBN3 Detect Alternate Function mapping*/
|
||||
#define GPIO_Remap_DET_EN_EGBN2 ((uint32_t)0x10200002) /*!< EGBN2 Detect Alternate Function mapping*/
|
||||
#define GPIO_Remap_DET_EN_EGBN1 ((uint32_t)0x10200001) /*!< EGBN1 Detect Alternate Function mapping*/
|
||||
#define GPIO_Remap_DET_EN_ECLAMP4 ((uint32_t)0x10008000) /*!< ECLAMP4 Detect Alternate Function mapping*/
|
||||
#define GPIO_Remap_DET_EN_ECLAMP3 ((uint32_t)0x10004000) /*!< ECLAMP3 Detect Alternate Function mapping*/
|
||||
#define GPIO_Remap_DET_EN_ECLAMP2 ((uint32_t)0x10002000) /*!< ECLAMP2 Detect Alternate Function mapping*/
|
||||
#define GPIO_Remap_DET_EN_ECLAMP1 ((uint32_t)0x10001000) /*!< ECLAMP1 Detect Alternate Function mapping*/
|
||||
#define GPIO_Remap_RST_EN_EGB4 ((uint32_t)0x10000800) /*!< EGB4 Reset Alternate Function mapping*/
|
||||
#define GPIO_Remap_RST_EN_EGB3 ((uint32_t)0x10000400) /*!< EGB3 Reset Alternate Function mapping*/
|
||||
#define GPIO_Remap_RST_EN_EGB2 ((uint32_t)0x10000200) /*!< EGB2 Reset Alternate Function mapping*/
|
||||
#define GPIO_Remap_RST_EN_EGB1 ((uint32_t)0x10000100) /*!< EGB1 Reset Alternate Function mapping*/
|
||||
#define GPIO_Remap_RST_EN_EGBN4 ((uint32_t)0x10000080) /*!< EGBN4 Reset Alternate Function mapping*/
|
||||
#define GPIO_Remap_RST_EN_EGBN3 ((uint32_t)0x10000040) /*!< EGBN3 Reset Alternate Function mapping*/
|
||||
#define GPIO_Remap_RST_EN_EGBN2 ((uint32_t)0x10000020) /*!< EGBN2 Reset Alternate Function mapping*/
|
||||
#define GPIO_Remap_RST_EN_EGBN1 ((uint32_t)0x10000010) /*!< EGBN1 Reset Alternate Function mapping*/
|
||||
#define GPIO_Remap_RST_EN_ECLAMP4 ((uint32_t)0x10000008) /*!< ECLAMP4 Reset Alternate Function mapping*/
|
||||
#define GPIO_Remap_RST_EN_ECLAMP3 ((uint32_t)0x10000004) /*!< ECLAMP3 Reset Alternate Function mapping*/
|
||||
#define GPIO_Remap_RST_EN_ECLAMP2 ((uint32_t)0x10000002) /*!< ECLAMP2 Reset Alternate Function mapping*/
|
||||
#define GPIO_Remap_RST_EN_ECLAMP1 ((uint32_t)0x10000001) /*!< ECLAMP1 Reset Alternate Function mapping*/
|
||||
|
||||
#define IS_GPIO_REMAP(REMAP) \
|
||||
(((REMAP) == GPIO_RMP_SPI1) || ((REMAP) == GPIO_RMP_I2C1) || ((REMAP) == GPIO_RMP_USART1) \
|
||||
|| ((REMAP) == GPIO_RMP_USART2) || ((REMAP) == GPIO_PART_RMP_USART3) || ((REMAP) == GPIO_ALL_RMP_USART3) \
|
||||
|| ((REMAP) == GPIO_PART1_RMP_TIM1) || ((REMAP) == GPIO_ALL_RMP_TIM1) || ((REMAP) == GPIO_PartialRemap1_TIM2) \
|
||||
|| ((REMAP) == GPIO_PART2_RMP_TIM2) || ((REMAP) == GPIO_ALL_RMP_TIM2) || ((REMAP) == GPIO_PART1_RMP_TIM3) \
|
||||
|| ((REMAP) == GPIO_ALL_RMP_TIM3) || ((REMAP) == GPIO_RMP_TIM4) || ((REMAP) == GPIO_RMP1_CAN1) \
|
||||
|| ((REMAP) == GPIO_Remap2_CAN1) || ((REMAP) == GPIO_RMP_PD01) || ((REMAP) == GPIO_RMP_TIM5CH4) \
|
||||
|| ((REMAP) == GPIO_RMP_ADC1_ETRI) || ((REMAP) == GPIO_RMP_ADC1_ETRR) || ((REMAP) == GPIO_RMP_ADC2_ETRI) \
|
||||
|| ((REMAP) == GPIO_RMP_ADC2_ETRR) || ((REMAP) == GPIO_RMP_SW_JTAG_NO_NJTRST) \
|
||||
|| ((REMAP) == GPIO_RMP_SW_JTAG_SW_ENABLE) || ((REMAP) == GPIO_RMP_SW_JTAG_DISABLE) \
|
||||
|| ((REMAP) == GPIO_Remap_XFMC_NADV) || ((REMAP) == GPIO_RMP_SDIO) || ((REMAP) == GPIO_RMP1_CAN2) \
|
||||
|| ((REMAP) == GPIO_RMP3_CAN2) || ((REMAP) == GPIO_RMP1_QSPI) || ((REMAP) == GPIO_RMP3_QSPI) \
|
||||
|| ((REMAP) == GPIO_RMP1_I2C2) || ((REMAP) == GPIO_RMP3_I2C2) || ((REMAP) == GPIO_RMP2_I2C3) \
|
||||
|| ((REMAP) == GPIO_RMP3_I2C3) || ((REMAP) == GPIO_RMP1_I2C4) || ((REMAP) == GPIO_RMP3_I2C4) \
|
||||
|| ((REMAP) == GPIO_RMP1_SPI2) || ((REMAP) == GPIO_RMP2_SPI2) || ((REMAP) == GPIO_RMP1_SPI3) \
|
||||
|| ((REMAP) == GPIO_RMP2_SPI3) || ((REMAP) == GPIO_RMP3_SPI3) || ((REMAP) == GPIO_RMP1_ETH) \
|
||||
|| ((REMAP) == GPIO_RMP2_ETH) || ((REMAP) == GPIO_RMP3_ETH) || ((REMAP) == GPIO_RMP1_SPI1) \
|
||||
|| ((REMAP) == GPIO_RMP2_SPI1) || ((REMAP) == GPIO_RMP3_SPI1) || ((REMAP) == GPIO_RMP1_USART2) \
|
||||
|| ((REMAP) == GPIO_RMP2_USART2) || ((REMAP) == GPIO_RMP3_USART2) || ((REMAP) == GPIO_RMP1_UART4) \
|
||||
|| ((REMAP) == GPIO_RMP2_UART4) || ((REMAP) == GPIO_RMP3_UART4) || ((REMAP) == GPIO_RMP1_UART5) \
|
||||
|| ((REMAP) == GPIO_RMP2_UART5) || ((REMAP) == GPIO_RMP3_UART5) || ((REMAP) == GPIO_RMP2_UART6) \
|
||||
|| ((REMAP) == GPIO_RMP3_UART6) || ((REMAP) == GPIO_RMP1_UART7) || ((REMAP) == GPIO_RMP3_UART7) \
|
||||
|| ((REMAP) == GPIO_RMP1_XFMC) || ((REMAP) == GPIO_RMP3_XFMC) || ((REMAP) == GPIO_RMP1_TIM8) \
|
||||
|| ((REMAP) == GPIO_RMP3_TIM8) || ((REMAP) == GPIO_RMP1_COMP1) || ((REMAP) == GPIO_RMP2_COMP1) \
|
||||
|| ((REMAP) == GPIO_RMP3_COMP1) || ((REMAP) == GPIO_RMP1_COMP2) || ((REMAP) == GPIO_RMP2_COMP2) \
|
||||
|| ((REMAP) == GPIO_RMP3_COMP2) || ((REMAP) == GPIO_RMP1_COMP3) || ((REMAP) == GPIO_RMP3_COMP3) \
|
||||
|| ((REMAP) == GPIO_RMP1_COMP4) || ((REMAP) == GPIO_RMP3_COMP4) || ((REMAP) == GPIO_RMP1_COMP5) \
|
||||
|| ((REMAP) == GPIO_RMP2_COMP5) || ((REMAP) == GPIO_RMP3_COMP5) || ((REMAP) == GPIO_RMP1_COMP6) \
|
||||
|| ((REMAP) == GPIO_RMP3_COMP6) || ((REMAP) == GPIO_RMP_COMP7) || ((REMAP) == GPIO_RMP_ADC3_ETRI) \
|
||||
|| ((REMAP) == GPIO_RMP_ADC3_ETRR) || ((REMAP) == GPIO_RMP_ADC4_ETRI) || ((REMAP) == GPIO_RMP_ADC4_ETRR) \
|
||||
|| ((REMAP) == GPIO_RMP_TSC_OUT_CTRL) || ((REMAP) == GPIO_RMP_QSPI_XIP_EN) || ((REMAP) == GPIO_RMP1_DVP) \
|
||||
|| ((REMAP) == GPIO_RMP3_DVP) || ((REMAP) == GPIO_Remap_SPI1_NSS) || ((REMAP) == GPIO_Remap_SPI2_NSS) \
|
||||
|| ((REMAP) == GPIO_Remap_SPI3_NSS) || ((REMAP) == GPIO_Remap_QSPI_MISO) || ((REMAP) == GPIO_RMP_MII_RMII_SEL) \
|
||||
|| ((REMAP) == GPIO_PART2_RMP_TIM1) || ((REMAP) == GPIO_Remap_DET_EN_EGB4) || ((REMAP) == GPIO_Remap_DET_EN_EGB3) \
|
||||
|| ((REMAP) == GPIO_Remap_DET_EN_EGB2) || ((REMAP) == GPIO_Remap_DET_EN_EGB1) \
|
||||
|| ((REMAP) == GPIO_Remap_DET_EN_EGBN4) || ((REMAP) == GPIO_Remap_DET_EN_EGBN3) \
|
||||
|| ((REMAP) == GPIO_Remap_DET_EN_EGBN2) || ((REMAP) == GPIO_Remap_DET_EN_EGBN1) \
|
||||
|| ((REMAP) == GPIO_Remap_DET_EN_ECLAMP4) || ((REMAP) == GPIO_Remap_DET_EN_ECLAMP3) \
|
||||
|| ((REMAP) == GPIO_Remap_DET_EN_ECLAMP2) || ((REMAP) == GPIO_Remap_DET_EN_ECLAMP1) \
|
||||
|| ((REMAP) == GPIO_Remap_RST_EN_EGB4) || ((REMAP) == GPIO_Remap_RST_EN_EGB3) \
|
||||
|| ((REMAP) == GPIO_Remap_RST_EN_EGB2) || ((REMAP) == GPIO_Remap_RST_EN_EGB1) \
|
||||
|| ((REMAP) == GPIO_Remap_RST_EN_EGBN4) || ((REMAP) == GPIO_Remap_RST_EN_EGBN3) \
|
||||
|| ((REMAP) == GPIO_Remap_RST_EN_EGBN2) || ((REMAP) == GPIO_Remap_RST_EN_EGBN1) \
|
||||
|| ((REMAP) == GPIO_Remap_RST_EN_ECLAMP4) || ((REMAP) == GPIO_Remap_RST_EN_ECLAMP3) \
|
||||
|| ((REMAP) == GPIO_Remap_RST_EN_ECLAMP2) || ((REMAP) == GPIO_Remap_RST_EN_ECLAMP1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Port_Sources
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIOA_PORT_SOURCE ((uint8_t)0x00)
|
||||
#define GPIOB_PORT_SOURCE ((uint8_t)0x01)
|
||||
#define GPIOC_PORT_SOURCE ((uint8_t)0x02)
|
||||
#define GPIOD_PORT_SOURCE ((uint8_t)0x03)
|
||||
#define GPIOE_PORT_SOURCE ((uint8_t)0x04)
|
||||
#define GPIOF_PORT_SOURCE ((uint8_t)0x05)
|
||||
#define GPIOG_PORT_SOURCE ((uint8_t)0x06)
|
||||
#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) \
|
||||
(((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \
|
||||
|| ((PORTSOURCE) == GPIOD_PORT_SOURCE) || ((PORTSOURCE) == GPIOE_PORT_SOURCE))
|
||||
|
||||
#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) \
|
||||
(((PORTSOURCE) == GPIOA_PORT_SOURCE) || ((PORTSOURCE) == GPIOB_PORT_SOURCE) || ((PORTSOURCE) == GPIOC_PORT_SOURCE) \
|
||||
|| ((PORTSOURCE) == GPIOD_PORT_SOURCE) || ((PORTSOURCE) == GPIOE_PORT_SOURCE) \
|
||||
|| ((PORTSOURCE) == GPIOF_PORT_SOURCE) || ((PORTSOURCE) == GPIOG_PORT_SOURCE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Pin_sources
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_PIN_SOURCE0 ((uint8_t)0x00)
|
||||
#define GPIO_PIN_SOURCE1 ((uint8_t)0x01)
|
||||
#define GPIO_PIN_SOURCE2 ((uint8_t)0x02)
|
||||
#define GPIO_PIN_SOURCE3 ((uint8_t)0x03)
|
||||
#define GPIO_PIN_SOURCE4 ((uint8_t)0x04)
|
||||
#define GPIO_PIN_SOURCE5 ((uint8_t)0x05)
|
||||
#define GPIO_PIN_SOURCE6 ((uint8_t)0x06)
|
||||
#define GPIO_PIN_SOURCE7 ((uint8_t)0x07)
|
||||
#define GPIO_PIN_SOURCE8 ((uint8_t)0x08)
|
||||
#define GPIO_PIN_SOURCE9 ((uint8_t)0x09)
|
||||
#define GPIO_PIN_SOURCE10 ((uint8_t)0x0A)
|
||||
#define GPIO_PIN_SOURCE11 ((uint8_t)0x0B)
|
||||
#define GPIO_PIN_SOURCE12 ((uint8_t)0x0C)
|
||||
#define GPIO_PIN_SOURCE13 ((uint8_t)0x0D)
|
||||
#define GPIO_PIN_SOURCE14 ((uint8_t)0x0E)
|
||||
#define GPIO_PIN_SOURCE15 ((uint8_t)0x0F)
|
||||
|
||||
#define IS_GPIO_PIN_SOURCE(PINSOURCE) \
|
||||
(((PINSOURCE) == GPIO_PIN_SOURCE0) || ((PINSOURCE) == GPIO_PIN_SOURCE1) || ((PINSOURCE) == GPIO_PIN_SOURCE2) \
|
||||
|| ((PINSOURCE) == GPIO_PIN_SOURCE3) || ((PINSOURCE) == GPIO_PIN_SOURCE4) || ((PINSOURCE) == GPIO_PIN_SOURCE5) \
|
||||
|| ((PINSOURCE) == GPIO_PIN_SOURCE6) || ((PINSOURCE) == GPIO_PIN_SOURCE7) || ((PINSOURCE) == GPIO_PIN_SOURCE8) \
|
||||
|| ((PINSOURCE) == GPIO_PIN_SOURCE9) || ((PINSOURCE) == GPIO_PIN_SOURCE10) || ((PINSOURCE) == GPIO_PIN_SOURCE11) \
|
||||
|| ((PINSOURCE) == GPIO_PIN_SOURCE12) || ((PINSOURCE) == GPIO_PIN_SOURCE13) || ((PINSOURCE) == GPIO_PIN_SOURCE14) \
|
||||
|| ((PINSOURCE) == GPIO_PIN_SOURCE15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Ethernet_Media_Interface
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_ETH_MII_CFG ((uint32_t)0x00000000)
|
||||
#define GPIO_ETH_RMII_CFG ((uint32_t)0x00800000)
|
||||
|
||||
#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MII_CFG) || ((INTERFACE) == GPIO_ETH_RMII_CFG))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void GPIO_DeInit(GPIO_Module* GPIOx);
|
||||
void GPIO_AFIOInitDefault(void);
|
||||
void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStruct);
|
||||
void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct);
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin);
|
||||
uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx);
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin);
|
||||
uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx);
|
||||
void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin);
|
||||
void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin);
|
||||
void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd);
|
||||
void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal);
|
||||
void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin);
|
||||
void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource);
|
||||
void GPIO_CtrlEventOutput(FunctionalState Cmd);
|
||||
void GPIO_ConfigPinRemap(uint32_t RmpPin, FunctionalState Cmd);
|
||||
void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource);
|
||||
void GPIO_ETH_ConfigMediaInterface(uint32_t ETH_ConfigSel);
|
||||
void GPIO_SetBitsHigh16(GPIO_Module* GPIOx, uint32_t Pin);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __N32G45X_GPIO_H__ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,665 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_i2c.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_I2C_H__
|
||||
#define __N32G45X_I2C_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief I2C Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClkSpeed; /*!< Specifies the clock frequency.
|
||||
This parameter must be set to a value lower than 400kHz */
|
||||
|
||||
uint16_t BusMode; /*!< Specifies the I2C mode.
|
||||
This parameter can be a value of @ref I2C_BusMode */
|
||||
|
||||
uint16_t FmDutyCycle; /*!< Specifies the I2C fast mode duty cycle.
|
||||
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
|
||||
|
||||
uint16_t OwnAddr1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint16_t AckEnable; /*!< Enables or disables the acknowledgement.
|
||||
This parameter can be a value of @ref I2C_acknowledgement */
|
||||
|
||||
uint16_t AddrMode; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
|
||||
This parameter can be a value of @ref I2C_acknowledged_address */
|
||||
} I2C_InitType;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_PERIPH(PERIPH) (((PERIPH) == I2C1) || ((PERIPH) == I2C2) || ((PERIPH) == I2C3) || ((PERIPH) == I2C4))
|
||||
/** @addtogroup I2C_BusMode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_BUSMODE_I2C ((uint16_t)0x0000)
|
||||
#define I2C_BUSMODE_SMBDEVICE ((uint16_t)0x0002)
|
||||
#define I2C_BUSMODE_SMBHOST ((uint16_t)0x000A)
|
||||
#define IS_I2C_BUS_MODE(MODE) \
|
||||
(((MODE) == I2C_BUSMODE_I2C) || ((MODE) == I2C_BUSMODE_SMBDEVICE) || ((MODE) == I2C_BUSMODE_SMBHOST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_duty_cycle_in_fast_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_FMDUTYCYCLE_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
|
||||
#define I2C_FMDUTYCYCLE_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
|
||||
#define IS_I2C_FM_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_FMDUTYCYCLE_16_9) || ((CYCLE) == I2C_FMDUTYCYCLE_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_acknowledgement
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_ACKEN ((uint16_t)0x0400)
|
||||
#define I2C_ACKDIS ((uint16_t)0x0000)
|
||||
#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_ACKEN) || ((STATE) == I2C_ACKDIS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_DIRECTION_SEND ((uint8_t)0x00)
|
||||
#define I2C_DIRECTION_RECV ((uint8_t)0x01)
|
||||
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_DIRECTION_SEND) || ((DIRECTION) == I2C_DIRECTION_RECV))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_acknowledged_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_ADDR_MODE_7BIT ((uint16_t)0x4000)
|
||||
#define I2C_ADDR_MODE_10BIT ((uint16_t)0xC000)
|
||||
#define IS_I2C_ADDR_MODE(ADDRESS) (((ADDRESS) == I2C_ADDR_MODE_7BIT) || ((ADDRESS) == I2C_ADDR_MODE_10BIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_REG_CTRL1 ((uint8_t)0x00)
|
||||
#define I2C_REG_CTRL2 ((uint8_t)0x04)
|
||||
#define I2C_REG_OADDR1 ((uint8_t)0x08)
|
||||
#define I2C_REG_OADDR2 ((uint8_t)0x0C)
|
||||
#define I2C_REG_DAT ((uint8_t)0x10)
|
||||
#define I2C_REG_STS1 ((uint8_t)0x14)
|
||||
#define I2C_REG_STS2 ((uint8_t)0x18)
|
||||
#define I2C_REG_CLKCTRL ((uint8_t)0x1C)
|
||||
#define I2C_REG_TMRISE ((uint8_t)0x20)
|
||||
#define IS_I2C_REG(REGISTER) \
|
||||
(((REGISTER) == I2C_REG_CTRL1) || ((REGISTER) == I2C_REG_CTRL2) || ((REGISTER) == I2C_REG_OADDR1) \
|
||||
|| ((REGISTER) == I2C_REG_OADDR2) || ((REGISTER) == I2C_REG_DAT) || ((REGISTER) == I2C_REG_STS1) \
|
||||
|| ((REGISTER) == I2C_REG_STS2) || ((REGISTER) == I2C_REG_CLKCTRL) || ((REGISTER) == I2C_REG_TMRISE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_SMBus_alert_pin_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_SMBALERT_LOW ((uint16_t)0x2000)
|
||||
#define I2C_SMBALERT_HIGH ((uint16_t)0xDFFF)
|
||||
#define IS_I2C_SMB_ALERT(ALERT) (((ALERT) == I2C_SMBALERT_LOW) || ((ALERT) == I2C_SMBALERT_HIGH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_PEC_position
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_PEC_POS_NEXT ((uint16_t)0x0800)
|
||||
#define I2C_PEC_POS_CURRENT ((uint16_t)0xF7FF)
|
||||
#define IS_I2C_PEC_POS(POSITION) (((POSITION) == I2C_PEC_POS_NEXT) || ((POSITION) == I2C_PEC_POS_CURRENT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_NCAK_position
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_NACK_POS_NEXT ((uint16_t)0x0800)
|
||||
#define I2C_NACK_POS_CURRENT ((uint16_t)0xF7FF)
|
||||
#define IS_I2C_NACK_POS(POSITION) (((POSITION) == I2C_NACK_POS_NEXT) || ((POSITION) == I2C_NACK_POS_CURRENT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_INT_BUF ((uint16_t)0x0400)
|
||||
#define I2C_INT_EVENT ((uint16_t)0x0200)
|
||||
#define I2C_INT_ERR ((uint16_t)0x0100)
|
||||
#define IS_I2C_CFG_INT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_INT_SMBALERT ((uint32_t)0x01008000)
|
||||
#define I2C_INT_TIMOUT ((uint32_t)0x01004000)
|
||||
#define I2C_INT_PECERR ((uint32_t)0x01001000)
|
||||
#define I2C_INT_OVERRUN ((uint32_t)0x01000800)
|
||||
#define I2C_INT_ACKFAIL ((uint32_t)0x01000400)
|
||||
#define I2C_INT_ARLOST ((uint32_t)0x01000200)
|
||||
#define I2C_INT_BUSERR ((uint32_t)0x01000100)
|
||||
#define I2C_INT_TXDATE ((uint32_t)0x06000080)
|
||||
#define I2C_INT_RXDATNE ((uint32_t)0x06000040)
|
||||
#define I2C_INT_STOPF ((uint32_t)0x02000010)
|
||||
#define I2C_INT_ADDR10F ((uint32_t)0x02000008)
|
||||
#define I2C_INT_BYTEF ((uint32_t)0x02000004)
|
||||
#define I2C_INT_ADDRF ((uint32_t)0x02000002)
|
||||
#define I2C_INT_STARTBF ((uint32_t)0x02000001)
|
||||
|
||||
#define IS_I2C_CLR_INT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
|
||||
|
||||
#define IS_I2C_GET_INT(IT) \
|
||||
(((IT) == I2C_INT_SMBALERT) || ((IT) == I2C_INT_TIMOUT) || ((IT) == I2C_INT_PECERR) || ((IT) == I2C_INT_OVERRUN) \
|
||||
|| ((IT) == I2C_INT_ACKFAIL) || ((IT) == I2C_INT_ARLOST) || ((IT) == I2C_INT_BUSERR) || ((IT) == I2C_INT_TXDATE) \
|
||||
|| ((IT) == I2C_INT_RXDATNE) || ((IT) == I2C_INT_STOPF) || ((IT) == I2C_INT_ADDR10F) || ((IT) == I2C_INT_BYTEF) \
|
||||
|| ((IT) == I2C_INT_ADDRF) || ((IT) == I2C_INT_STARTBF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief STS2 register flags
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_DUALFLAG ((uint32_t)0x00800000)
|
||||
#define I2C_FLAG_SMBHADDR ((uint32_t)0x00400000)
|
||||
#define I2C_FLAG_SMBDADDR ((uint32_t)0x00200000)
|
||||
#define I2C_FLAG_GCALLADDR ((uint32_t)0x00100000)
|
||||
#define I2C_FLAG_TRF ((uint32_t)0x00040000)
|
||||
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
|
||||
#define I2C_FLAG_MSMODE ((uint32_t)0x00010000)
|
||||
|
||||
/**
|
||||
* @brief STS1 register flags
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
|
||||
#define I2C_FLAG_TIMOUT ((uint32_t)0x10004000)
|
||||
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
|
||||
#define I2C_FLAG_OVERRUN ((uint32_t)0x10000800)
|
||||
#define I2C_FLAG_ACKFAIL ((uint32_t)0x10000400)
|
||||
#define I2C_FLAG_ARLOST ((uint32_t)0x10000200)
|
||||
#define I2C_FLAG_BUSERR ((uint32_t)0x10000100)
|
||||
#define I2C_FLAG_TXDATE ((uint32_t)0x10000080)
|
||||
#define I2C_FLAG_RXDATNE ((uint32_t)0x10000040)
|
||||
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
|
||||
#define I2C_FLAG_ADDR10F ((uint32_t)0x10000008)
|
||||
#define I2C_FLAG_BYTEF ((uint32_t)0x10000004)
|
||||
#define I2C_FLAG_ADDRF ((uint32_t)0x10000002)
|
||||
#define I2C_FLAG_STARTBF ((uint32_t)0x10000001)
|
||||
|
||||
#define IS_I2C_CLR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
|
||||
|
||||
#define IS_I2C_GET_FLAG(FLAG) \
|
||||
(((FLAG) == I2C_FLAG_DUALFLAG) || ((FLAG) == I2C_FLAG_SMBHADDR) || ((FLAG) == I2C_FLAG_SMBDADDR) \
|
||||
|| ((FLAG) == I2C_FLAG_GCALLADDR) || ((FLAG) == I2C_FLAG_TRF) || ((FLAG) == I2C_FLAG_BUSY) \
|
||||
|| ((FLAG) == I2C_FLAG_MSMODE) || ((FLAG) == I2C_FLAG_SMBALERT) || ((FLAG) == I2C_FLAG_TIMOUT) \
|
||||
|| ((FLAG) == I2C_FLAG_PECERR) || ((FLAG) == I2C_FLAG_OVERRUN) || ((FLAG) == I2C_FLAG_ACKFAIL) \
|
||||
|| ((FLAG) == I2C_FLAG_ARLOST) || ((FLAG) == I2C_FLAG_BUSERR) || ((FLAG) == I2C_FLAG_TXDATE) \
|
||||
|| ((FLAG) == I2C_FLAG_RXDATNE) || ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADDR10F) \
|
||||
|| ((FLAG) == I2C_FLAG_BYTEF) || ((FLAG) == I2C_FLAG_ADDRF) || ((FLAG) == I2C_FLAG_STARTBF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Events
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*========================================
|
||||
|
||||
I2C Master Events (Events grouped in order of communication)
|
||||
==========================================*/
|
||||
/**
|
||||
* @brief Communication start
|
||||
*
|
||||
* After sending the START condition (I2C_GenerateStart() function) the master
|
||||
* has to wait for this event. It means that the Start condition has been correctly
|
||||
* released on the I2C bus (the bus is free, no other devices is communicating).
|
||||
*
|
||||
*/
|
||||
/* --EV5 */
|
||||
#define I2C_EVT_MASTER_MODE_FLAG ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
|
||||
|
||||
/**
|
||||
* @brief Address Acknowledge
|
||||
*
|
||||
* After checking on EV5 (start condition correctly released on the bus), the
|
||||
* master sends the address of the slave(s) with which it will communicate
|
||||
* (I2C_SendAddr7bit() function, it also determines the direction of the communication:
|
||||
* Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
|
||||
* his address. If an acknowledge is sent on the bus, one of the following events will
|
||||
* be set:
|
||||
*
|
||||
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVT_MASTER_RXMODE_FLAG
|
||||
* event is set.
|
||||
*
|
||||
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVT_MASTER_TXMODE_FLAG
|
||||
* is set
|
||||
*
|
||||
* 3) In case of 10-Bit addressing mode, the master (just after generating the START
|
||||
* and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
|
||||
* function). Then master should wait on EV9. It means that the 10-bit addressing
|
||||
* header has been correctly sent on the bus. Then master should send the second part of
|
||||
* the 10-bit address (LSB) using the function I2C_SendAddr7bit(). Then master
|
||||
* should wait for event EV6.
|
||||
*
|
||||
*/
|
||||
|
||||
/* --EV6 */
|
||||
#define I2C_EVT_MASTER_TXMODE_FLAG ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
|
||||
#define I2C_EVT_MASTER_RXMODE_FLAG ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
|
||||
/* --EV9 */
|
||||
#define I2C_EVT_MASTER_MODE_ADDRESS10_FLAG ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
|
||||
|
||||
/**
|
||||
* @brief Communication events
|
||||
*
|
||||
* If a communication is established (START condition generated and slave address
|
||||
* acknowledged) then the master has to check on one of the following events for
|
||||
* communication procedures:
|
||||
*
|
||||
* 1) Master Receiver mode: The master has to wait on the event EV7 then to read
|
||||
* the data received from the slave (I2C_RecvData() function).
|
||||
*
|
||||
* 2) Master Transmitter mode: The master has to send data (I2C_SendData()
|
||||
* function) then to wait on event EV8 or EV8_2.
|
||||
* These two events are similar:
|
||||
* - EV8 means that the data has been written in the data register and is
|
||||
* being shifted out.
|
||||
* - EV8_2 means that the data has been physically shifted out and output
|
||||
* on the bus.
|
||||
* In most cases, using EV8 is sufficient for the application.
|
||||
* Using EV8_2 leads to a slower communication but ensure more reliable test.
|
||||
* EV8_2 is also more suitable than EV8 for testing on the last data transmission
|
||||
* (before Stop condition generation).
|
||||
*
|
||||
* @note In case the user software does not guarantee that this event EV7 is
|
||||
* managed before the current byte end of transfer, then user may check on EV7
|
||||
* and BTF flag at the same time (ie. (I2C_EVT_MASTER_DATA_RECVD_FLAG | I2C_FLAG_BYTEF)).
|
||||
* In this case the communication may be slower.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Master RECEIVER mode -----------------------------*/
|
||||
/* --EV7 */
|
||||
#define I2C_EVT_MASTER_DATA_RECVD_FLAG ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
|
||||
|
||||
/* Master TRANSMITTER mode --------------------------*/
|
||||
/* --EV8 */
|
||||
#define I2C_EVT_MASTER_DATA_SENDING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
|
||||
/* --EV8_2 */
|
||||
#define I2C_EVT_MASTER_DATA_SENDED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
|
||||
|
||||
/*========================================
|
||||
|
||||
I2C Slave Events (Events grouped in order of communication)
|
||||
==========================================*/
|
||||
|
||||
/**
|
||||
* @brief Communication start events
|
||||
*
|
||||
* Wait on one of these events at the start of the communication. It means that
|
||||
* the I2C peripheral detected a Start condition on the bus (generated by master
|
||||
* device) followed by the peripheral address. The peripheral generates an ACK
|
||||
* condition on the bus (if the acknowledge feature is enabled through function
|
||||
* I2C_ConfigAck()) and the events listed above are set :
|
||||
*
|
||||
* 1) In normal case (only one address managed by the slave), when the address
|
||||
* sent by the master matches the own address of the peripheral (configured by
|
||||
* OwnAddr1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
|
||||
* (where XXX could be TRANSMITTER or RECEIVER).
|
||||
*
|
||||
* 2) In case the address sent by the master matches the second address of the
|
||||
* peripheral (configured by the function I2C_ConfigOwnAddr2() and enabled
|
||||
* by the function I2C_EnableDualAddr()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
|
||||
* (where XXX could be TRANSMITTER or RECEIVER) are set.
|
||||
*
|
||||
* 3) In case the address sent by the master is General Call (address 0x00) and
|
||||
* if the General Call is enabled for the peripheral (using function I2C_EnableGeneralCall())
|
||||
* the following event is set I2C_EVT_SLAVE_GCALLADDR_MATCHED.
|
||||
*
|
||||
*/
|
||||
|
||||
/* --EV1 (all the events below are variants of EV1) */
|
||||
/* 1) Case of One Single Address managed by the slave */
|
||||
#define I2C_EVT_SLAVE_RECV_ADDR_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
|
||||
#define I2C_EVT_SLAVE_SEND_ADDR_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
|
||||
|
||||
/* 2) Case of Dual address managed by the slave */
|
||||
#define I2C_EVT_SLAVE_RECV_ADDR2_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
|
||||
#define I2C_EVT_SLAVE_SEND_ADDR2_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
|
||||
|
||||
/* 3) Case of General Call enabled for the slave */
|
||||
#define I2C_EVT_SLAVE_GCALLADDR_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
|
||||
|
||||
/**
|
||||
* @brief Communication events
|
||||
*
|
||||
* Wait on one of these events when EV1 has already been checked and:
|
||||
*
|
||||
* - Slave RECEIVER mode:
|
||||
* - EV2: When the application is expecting a data byte to be received.
|
||||
* - EV4: When the application is expecting the end of the communication: master
|
||||
* sends a stop condition and data transmission is stopped.
|
||||
*
|
||||
* - Slave Transmitter mode:
|
||||
* - EV3: When a byte has been transmitted by the slave and the application is expecting
|
||||
* the end of the byte transmission. The two events I2C_EVT_SLAVE_DATA_SENDED and
|
||||
* I2C_EVT_SLAVE_DATA_SENDING are similar. The second one can optionally be
|
||||
* used when the user software doesn't guarantee the EV3 is managed before the
|
||||
* current byte end of transfer.
|
||||
* - EV3_2: When the master sends a NACK in order to tell slave that data transmission
|
||||
* shall end (before sending the STOP condition). In this case slave has to stop sending
|
||||
* data bytes and expect a Stop condition on the bus.
|
||||
*
|
||||
* @note In case the user software does not guarantee that the event EV2 is
|
||||
* managed before the current byte end of transfer, then user may check on EV2
|
||||
* and BTF flag at the same time (ie. (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_BYTEF)).
|
||||
* In this case the communication may be slower.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Slave RECEIVER mode --------------------------*/
|
||||
/* --EV2 */
|
||||
#define I2C_EVT_SLAVE_DATA_RECVD ((uint32_t)0x00020040) /* BUSY and RXNE flags */
|
||||
/* --EV4 */
|
||||
#define I2C_EVT_SLAVE_STOP_RECVD ((uint32_t)0x00000010) /* STOPF flag */
|
||||
|
||||
/* Slave TRANSMITTER mode -----------------------*/
|
||||
/* --EV3 */
|
||||
#define I2C_EVT_SLAVE_DATA_SENDED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
|
||||
#define I2C_EVT_SLAVE_DATA_SENDING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
|
||||
/* --EV3_2 */
|
||||
#define I2C_EVT_SLAVE_ACK_MISS ((uint32_t)0x00000400) /* AF flag */
|
||||
|
||||
/*=========================== End of Events Description ==========================================*/
|
||||
|
||||
#define IS_I2C_EVT(EVENT) \
|
||||
(((EVENT) == I2C_EVT_SLAVE_SEND_ADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR_MATCHED) \
|
||||
|| ((EVENT) == I2C_EVT_SLAVE_SEND_ADDR2_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_RECV_ADDR2_MATCHED) \
|
||||
|| ((EVENT) == I2C_EVT_SLAVE_GCALLADDR_MATCHED) || ((EVENT) == I2C_EVT_SLAVE_DATA_RECVD) \
|
||||
|| ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG)) \
|
||||
|| ((EVENT) == (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_DATA_SENDED) \
|
||||
|| ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG)) \
|
||||
|| ((EVENT) == (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR)) || ((EVENT) == I2C_EVT_SLAVE_STOP_RECVD) \
|
||||
|| ((EVENT) == I2C_EVT_MASTER_MODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_TXMODE_FLAG) \
|
||||
|| ((EVENT) == I2C_EVT_MASTER_RXMODE_FLAG) || ((EVENT) == I2C_EVT_MASTER_DATA_RECVD_FLAG) \
|
||||
|| ((EVENT) == I2C_EVT_MASTER_DATA_SENDED) || ((EVENT) == I2C_EVT_MASTER_DATA_SENDING) \
|
||||
|| ((EVENT) == I2C_EVT_MASTER_MODE_ADDRESS10_FLAG) || ((EVENT) == I2C_EVT_SLAVE_ACK_MISS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_own_address1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_OWN_ADDR1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_clock_speed
|
||||
* @{
|
||||
*/
|
||||
|
||||
//#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
|
||||
#define IS_I2C_CLK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 1000000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void I2C_DeInit(I2C_Module* I2Cx);
|
||||
void I2C_Init(I2C_Module* I2Cx, I2C_InitType* I2C_InitStruct);
|
||||
void I2C_InitStruct(I2C_InitType* I2C_InitStruct);
|
||||
void I2C_Enable(I2C_Module* I2Cx, FunctionalState Cmd);
|
||||
void I2C_EnableDMA(I2C_Module* I2Cx, FunctionalState Cmd);
|
||||
void I2C_EnableDmaLastSend(I2C_Module* I2Cx, FunctionalState Cmd);
|
||||
void I2C_GenerateStart(I2C_Module* I2Cx, FunctionalState Cmd);
|
||||
void I2C_GenerateStop(I2C_Module* I2Cx, FunctionalState Cmd);
|
||||
void I2C_ConfigAck(I2C_Module* I2Cx, FunctionalState Cmd);
|
||||
void I2C_ConfigOwnAddr2(I2C_Module* I2Cx, uint8_t Address);
|
||||
void I2C_EnableDualAddr(I2C_Module* I2Cx, FunctionalState Cmd);
|
||||
void I2C_EnableGeneralCall(I2C_Module* I2Cx, FunctionalState Cmd);
|
||||
void I2C_ConfigInt(I2C_Module* I2Cx, uint16_t I2C_IT, FunctionalState Cmd);
|
||||
void I2C_SendData(I2C_Module* I2Cx, uint8_t Data);
|
||||
uint8_t I2C_RecvData(I2C_Module* I2Cx);
|
||||
void I2C_SendAddr7bit(I2C_Module* I2Cx, uint8_t Address, uint8_t I2C_Direction);
|
||||
uint16_t I2C_GetRegister(I2C_Module* I2Cx, uint8_t I2C_Register);
|
||||
void I2C_EnableSoftwareReset(I2C_Module* I2Cx, FunctionalState Cmd);
|
||||
void I2C_ConfigNackLocation(I2C_Module* I2Cx, uint16_t I2C_NACKPosition);
|
||||
void I2C_ConfigSmbusAlert(I2C_Module* I2Cx, uint16_t I2C_SMBusAlert);
|
||||
void I2C_SendPEC(I2C_Module* I2Cx, FunctionalState Cmd);
|
||||
void I2C_ConfigPecLocation(I2C_Module* I2Cx, uint16_t I2C_PECPosition);
|
||||
void I2C_ComputePec(I2C_Module* I2Cx, FunctionalState Cmd);
|
||||
uint8_t I2C_GetPec(I2C_Module* I2Cx);
|
||||
void I2C_EnableArp(I2C_Module* I2Cx, FunctionalState Cmd);
|
||||
void I2C_EnableExtendClk(I2C_Module* I2Cx, FunctionalState Cmd);
|
||||
void I2C_ConfigFastModeDutyCycle(I2C_Module* I2Cx, uint16_t FmDutyCycle);
|
||||
|
||||
/**
|
||||
* @brief
|
||||
****************************************************************************************
|
||||
*
|
||||
* I2C State Monitoring Functions
|
||||
*
|
||||
****************************************************************************************
|
||||
* This I2C driver provides three different ways for I2C state monitoring
|
||||
* depending on the application requirements and constraints:
|
||||
*
|
||||
*
|
||||
* 1) Basic state monitoring:
|
||||
* Using I2C_CheckEvent() function:
|
||||
* It compares the status registers (STS1 and STS2) content to a given event
|
||||
* (can be the combination of one or more flags).
|
||||
* It returns SUCCESS if the current status includes the given flags
|
||||
* and returns ERROR if one or more flags are missing in the current status.
|
||||
* - When to use:
|
||||
* - This function is suitable for most applications as well as for startup
|
||||
* activity since the events are fully described in the product reference manual
|
||||
* (RM0008).
|
||||
* - It is also suitable for users who need to define their own events.
|
||||
* - Limitations:
|
||||
* - If an error occurs (ie. error flags are set besides to the monitored flags),
|
||||
* the I2C_CheckEvent() function may return SUCCESS despite the communication
|
||||
* hold or corrupted real state.
|
||||
* In this case, it is advised to use error interrupts to monitor the error
|
||||
* events and handle them in the interrupt IRQ handler.
|
||||
*
|
||||
* @note
|
||||
* For error management, it is advised to use the following functions:
|
||||
* - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR).
|
||||
* - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
|
||||
* Where x is the peripheral instance (I2C1, I2C2 ...)
|
||||
* - I2C_GetFlag() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler()
|
||||
* in order to determine which error occurred.
|
||||
* - I2C_ClrFlag() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset()
|
||||
* and/or I2C_GenerateStop() in order to clear the error flag and source,
|
||||
* and return to correct communication status.
|
||||
*
|
||||
*
|
||||
* 2) Advanced state monitoring:
|
||||
* Using the function I2C_GetLastEvent() which returns the image of both status
|
||||
* registers in a single word (uint32_t) (Status Register 2 value is shifted left
|
||||
* by 16 bits and concatenated to Status Register 1).
|
||||
* - When to use:
|
||||
* - This function is suitable for the same applications above but it allows to
|
||||
* overcome the limitations of I2C_GetFlag() function (see below).
|
||||
* The returned value could be compared to events already defined in the
|
||||
* library (n32g45x_i2c.h) or to custom values defined by user.
|
||||
* - This function is suitable when multiple flags are monitored at the same time.
|
||||
* - At the opposite of I2C_CheckEvent() function, this function allows user to
|
||||
* choose when an event is accepted (when all events flags are set and no
|
||||
* other flags are set or just when the needed flags are set like
|
||||
* I2C_CheckEvent() function).
|
||||
* - Limitations:
|
||||
* - User may need to define his own events.
|
||||
* - Same remark concerning the error management is applicable for this
|
||||
* function if user decides to check only regular communication flags (and
|
||||
* ignores error flags).
|
||||
*
|
||||
*
|
||||
* 3) Flag-based state monitoring:
|
||||
* Using the function I2C_GetFlag() which simply returns the status of
|
||||
* one single flag (ie. I2C_FLAG_RXDATNE ...).
|
||||
* - When to use:
|
||||
* - This function could be used for specific applications or in debug phase.
|
||||
* - It is suitable when only one flag checking is needed (most I2C events
|
||||
* are monitored through multiple flags).
|
||||
* - Limitations:
|
||||
* - When calling this function, the Status register is accessed. Some flags are
|
||||
* cleared when the status register is accessed. So checking the status
|
||||
* of one Flag, may clear other ones.
|
||||
* - Function may need to be called twice or more in order to monitor one
|
||||
* single event.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
*
|
||||
* 1) Basic state monitoring
|
||||
*******************************************************************************
|
||||
*/
|
||||
ErrorStatus I2C_CheckEvent(I2C_Module* I2Cx, uint32_t I2C_EVENT);
|
||||
/**
|
||||
*
|
||||
* 2) Advanced state monitoring
|
||||
*******************************************************************************
|
||||
*/
|
||||
uint32_t I2C_GetLastEvent(I2C_Module* I2Cx);
|
||||
/**
|
||||
*
|
||||
* 3) Flag-based state monitoring
|
||||
*******************************************************************************
|
||||
*/
|
||||
FlagStatus I2C_GetFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG);
|
||||
/**
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
void I2C_ClrFlag(I2C_Module* I2Cx, uint32_t I2C_FLAG);
|
||||
INTStatus I2C_GetIntStatus(I2C_Module* I2Cx, uint32_t I2C_IT);
|
||||
void I2C_ClrIntPendingBit(I2C_Module* I2Cx, uint32_t I2C_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__N32G45X_I2C_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_iwdg.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_IWDG_H__
|
||||
#define __N32G45X_IWDG_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_WriteAccess
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_WRITE_ENABLE ((uint16_t)0x5555)
|
||||
#define IWDG_WRITE_DISABLE ((uint16_t)0x0000)
|
||||
#define IS_IWDG_WRITE(ACCESS) (((ACCESS) == IWDG_WRITE_ENABLE) || ((ACCESS) == IWDG_WRITE_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_PRESCALER_DIV4 ((uint8_t)0x00)
|
||||
#define IWDG_PRESCALER_DIV8 ((uint8_t)0x01)
|
||||
#define IWDG_PRESCALER_DIV16 ((uint8_t)0x02)
|
||||
#define IWDG_PRESCALER_DIV32 ((uint8_t)0x03)
|
||||
#define IWDG_PRESCALER_DIV64 ((uint8_t)0x04)
|
||||
#define IWDG_PRESCALER_DIV128 ((uint8_t)0x05)
|
||||
#define IWDG_PRESCALER_DIV256 ((uint8_t)0x06)
|
||||
#define IS_IWDG_PRESCALER_DIV(PRESCALER) \
|
||||
(((PRESCALER) == IWDG_PRESCALER_DIV4) || ((PRESCALER) == IWDG_PRESCALER_DIV8) \
|
||||
|| ((PRESCALER) == IWDG_PRESCALER_DIV16) || ((PRESCALER) == IWDG_PRESCALER_DIV32) \
|
||||
|| ((PRESCALER) == IWDG_PRESCALER_DIV64) || ((PRESCALER) == IWDG_PRESCALER_DIV128) \
|
||||
|| ((PRESCALER) == IWDG_PRESCALER_DIV256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_PVU_FLAG ((uint16_t)0x0001)
|
||||
#define IWDG_CRVU_FLAG ((uint16_t)0x0002)
|
||||
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_PVU_FLAG) || ((FLAG) == IWDG_CRVU_FLAG))
|
||||
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void IWDG_WriteConfig(uint16_t IWDG_WriteAccess);
|
||||
void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler);
|
||||
void IWDG_CntReload(uint16_t Reload);
|
||||
void IWDG_ReloadKey(void);
|
||||
void IWDG_Enable(void);
|
||||
FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __N32G45X_IWDG_H__ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,214 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_opamp.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_OPAMPMP_H__
|
||||
#define __N32G45X_OPAMPMP_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
#include <stdbool.h>
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup OPAMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup OPAMP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
OPAMP1 = 0,
|
||||
OPAMP2 = 4,
|
||||
OPAMP3 = 8,
|
||||
OPAMP4 = 12,
|
||||
} OPAMPX;
|
||||
|
||||
// OPAMP_CS
|
||||
typedef enum
|
||||
{
|
||||
OPAMP1_CS_VPSSEL_PA1 = (0x00L << 19),
|
||||
OPAMP1_CS_VPSSEL_PA3 = (0x01L << 19),
|
||||
OPAMP1_CS_VPSSEL_DAC2_PA5 = (0x02L << 19),
|
||||
OPAMP1_CS_VPSSEL_PC3 = (0x03L << 19),
|
||||
OPAMP1_CS_VPSSEL_PA7 = (0x04L << 19),
|
||||
OPAMP2_CS_VPSSEL_PA7 = (0x00L << 19),
|
||||
OPAMP2_CS_VPSSEL_PB0 = (0x01L << 19),
|
||||
OPAMP2_CS_VPSSEL_PE8 = (0x02L << 19),
|
||||
OPAMP3_CS_VPSSEL_PC9 = (0x00L << 19),
|
||||
OPAMP3_CS_VPSSEL_PA1 = (0x01L << 19),
|
||||
OPAMP3_CS_VPSSEL_DAC2_PA5 = (0x02L << 19),
|
||||
OPAMP3_CS_VPSSEL_PC3 = (0x03L << 19),
|
||||
OPAMP4_CS_VPSSEL_PC3 = (0x00L << 19),
|
||||
OPAMP4_CS_VPSSEL_DAC1_PA4 = (0x01L << 19),
|
||||
OPAMP4_CS_VPSSEL_PC5 = (0x02L << 19),
|
||||
} OPAMP_CS_VPSSEL;
|
||||
typedef enum
|
||||
{
|
||||
OPAMP1_CS_VMSSEL_PA3 = (0x00L << 17),
|
||||
OPAMP1_CS_VMSSEL_PA2 = (0x01L << 17),
|
||||
OPAMPx_CS_VMSSEL_FLOAT = (0x03L << 17),
|
||||
OPAMP2_CS_VMSSEL_PA2 = (0x00L << 17),
|
||||
OPAMP2_CS_VMSSEL_PA5 = (0x01L << 17),
|
||||
OPAMP3_CS_VMSSEL_PC4 = (0x00L << 17),
|
||||
OPAMP3_CS_VMSSEL_PB10 = (0x01L << 17),
|
||||
OPAMP4_CS_VMSSEL_PB10 = (0x00L << 17),
|
||||
OPAMP4_CS_VMSSEL_PC9 = (0x01L << 17),
|
||||
} OPAMP_CS_VMSSEL;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
OPAMP1_CS_VPSEL_PA1 = (0x00L << 8),
|
||||
OPAMP1_CS_VPSEL_PA3 = (0x01L << 8),
|
||||
OPAMP1_CS_VPSEL_DAC2_PA5 = (0x02L << 8),
|
||||
OPAMP1_CS_VPSEL_PC3 = (0x03L << 8),
|
||||
OPAMP1_CS_VPSEL_PA7 = (0x04L << 8),
|
||||
OPAMP2_CS_VPSEL_PA7 = (0x00L << 8),
|
||||
OPAMP2_CS_VPSEL_PB0 = (0x01L << 8),
|
||||
OPAMP2_CS_VPSEL_PE8 = (0x02L << 8),
|
||||
OPAMP3_CS_VPSEL_PC9 = (0x00L << 8),
|
||||
OPAMP3_CS_VPSEL_PA1 = (0x01L << 8),
|
||||
OPAMP3_CS_VPSEL_DAC2_PA5 = (0x02L << 8),
|
||||
OPAMP3_CS_VPSEL_PC3 = (0x03L << 8),
|
||||
OPAMP4_CS_VPSEL_PC3 = (0x00L << 8),
|
||||
OPAMP4_CS_VPSEL_DAC1_PA4 = (0x01L << 8),
|
||||
OPAMP4_CS_VPSEL_PC5 = (0x02L << 8),
|
||||
} OPAMP_CS_VPSEL;
|
||||
typedef enum
|
||||
{
|
||||
OPAMP1_CS_VMSEL_PA3 = (0x00L << 6),
|
||||
OPAMP1_CS_VMSEL_PA2 = (0x01L << 6),
|
||||
OPAMPx_CS_VMSEL_FLOAT = (0x03L << 6),
|
||||
OPAMP2_CS_VMSEL_PA2 = (0x00L << 6),
|
||||
OPAMP2_CS_VMSEL_PA5 = (0x01L << 6),
|
||||
OPAMP3_CS_VMSEL_PC4 = (0x00L << 6),
|
||||
OPAMP3_CS_VMSEL_PB10 = (0x01L << 6),
|
||||
OPAMP4_CS_VMSEL_PB10 = (0x00L << 6),
|
||||
OPAMP4_CS_VMSEL_PC9 = (0x01L << 6),
|
||||
} OPAMP_CS_VMSEL;
|
||||
typedef enum
|
||||
{
|
||||
OPAMP_CS_PGA_GAIN_2 = (0x00 << 3),
|
||||
OPAMP_CS_PGA_GAIN_4 = (0x01 << 3),
|
||||
OPAMP_CS_PGA_GAIN_8 = (0x02 << 3),
|
||||
OPAMP_CS_PGA_GAIN_16 = (0x03 << 3),
|
||||
OPAMP_CS_PGA_GAIN_32 = (0x04 << 3),
|
||||
} OPAMP_CS_PGA_GAIN;
|
||||
typedef enum
|
||||
{
|
||||
OPAMP_CS_EXT_OPAMP = (0x00 << 1),
|
||||
OPAMP_CS_PGA_EN = (0x02 << 1),
|
||||
OPAMP_CS_FOLLOW = (0x03 << 1),
|
||||
} OPAMP_CS_MOD;
|
||||
|
||||
// bit mask
|
||||
#define OPAMP_CS_EN_MASK (0x01L << 0)
|
||||
#define OPAMP_CS_MOD_MASK (0x03L << 1)
|
||||
#define OPAMP_CS_PGA_GAIN_MASK (0x07L << 3)
|
||||
#define OPAMP_CS_VMSEL_MASK (0x03L << 6)
|
||||
#define OPAMP_CS_VPSEL_MASK (0x07L << 8)
|
||||
#define OPAMP_CS_CALON_MASK (0x01L << 11)
|
||||
#define OPAMP_CS_TSTREF_MASK (0x01L << 13)
|
||||
#define OPAMP_CS_CALOUT_MASK (0x01L << 14)
|
||||
#define OPAMP_CS_RANGE_MASK (0x01L << 15)
|
||||
#define OPAMP_CS_TCMEN_MASK (0x01L << 16)
|
||||
#define OPAMP_CS_VMSEL_SECOND_MASK (0x03L << 17)
|
||||
#define OPAMP_CS_VPSEL_SECOND_MASK (0x07L << 19)
|
||||
#define OPAMP_CS_VREFOPT_MASK (0x03L << 22)
|
||||
/** @addtogroup OPAMP_LOCK
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_LOCK_1 0x01L
|
||||
#define OPAMP_LOCK_2 0x02L
|
||||
#define OPAMP_LOCK_3 0x04L
|
||||
#define OPAMP_LOCK_4 0x08L
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief OPAMP Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
FunctionalState TimeAutoMuxEn; /*call ENABLE or DISABLE */
|
||||
|
||||
FunctionalState HighVolRangeEn; /*call ENABLE or DISABLE ,low range VDDA < 2.4V,high range VDDA >= 2.4V*/
|
||||
|
||||
OPAMP_CS_PGA_GAIN Gain; /*see @EM_PGA_GAIN */
|
||||
|
||||
OPAMP_CS_MOD Mod; /*see @EM_OPAMP_MOD*/
|
||||
} OPAMP_InitType;
|
||||
|
||||
/** @addtogroup OPAMP_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void OPAMP_DeInit(void);
|
||||
void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct);
|
||||
void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct);
|
||||
void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en);
|
||||
void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain);
|
||||
void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel);
|
||||
void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel);
|
||||
void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel);
|
||||
void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel);
|
||||
bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx);
|
||||
void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en);
|
||||
void OPAMP_SetLock(uint32_t Lock); // see @OPAMP_LOCK
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__N32G45X_ADC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,188 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_pwr.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_PWR_H__
|
||||
#define __N32G45X_PWR_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PVD_detection_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_PVDRANGRE_2V2 ((uint32_t)0x00000000)
|
||||
#define PWR_PVDRANGRE_2V3 ((uint32_t)0x00000020)
|
||||
#define PWR_PVDRANGRE_2V4 ((uint32_t)0x00000040)
|
||||
#define PWR_PVDRANGRE_2V5 ((uint32_t)0x00000060)
|
||||
#define PWR_PVDRANGRE_2V6 ((uint32_t)0x00000080)
|
||||
#define PWR_PVDRANGRE_2V7 ((uint32_t)0x000000A0)
|
||||
#define PWR_PVDRANGRE_2V8 ((uint32_t)0x000000C0)
|
||||
#define PWR_PVDRANGRE_2V9 ((uint32_t)0x000000E0)
|
||||
|
||||
#define PWR_PVDRANGE_2V18 ((uint32_t)0x00000000)
|
||||
#define PWR_PVDRANGE_2V28 ((uint32_t)0x00000020)
|
||||
#define PWR_PVDRANGE_2V38 ((uint32_t)0x00000040)
|
||||
#define PWR_PVDRANGE_2V48 ((uint32_t)0x00000060)
|
||||
#define PWR_PVDRANGE_2V58 ((uint32_t)0x00000080)
|
||||
#define PWR_PVDRANGE_2V68 ((uint32_t)0x000000A0)
|
||||
#define PWR_PVDRANGE_2V78 ((uint32_t)0x000000C0)
|
||||
#define PWR_PVDRANGE_2V88 ((uint32_t)0x000000E0)
|
||||
|
||||
#define PWR_PVDRANGE_1V78 ((uint32_t)0x00000200)
|
||||
#define PWR_PVDRANGE_1V88 ((uint32_t)0x00000220)
|
||||
#define PWR_PVDRANGE_1V98 ((uint32_t)0x00000240)
|
||||
#define PWR_PVDRANGE_2V08 ((uint32_t)0x00000260)
|
||||
#define PWR_PVDRANGE_3V06 ((uint32_t)0x00000280)
|
||||
#define PWR_PVDRANGE_3V24 ((uint32_t)0x000002A0)
|
||||
#define PWR_PVDRANGE_3V42 ((uint32_t)0x000002C0)
|
||||
#define PWR_PVDRANGE_3V60 ((uint32_t)0x000002E0)
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) \
|
||||
(((LEVEL) == PWR_PVDRANGRE_2V2) || ((LEVEL) == PWR_PVDRANGRE_2V3) || ((LEVEL) == PWR_PVDRANGRE_2V4) \
|
||||
|| ((LEVEL) == PWR_PVDRANGRE_2V5) || ((LEVEL) == PWR_PVDRANGRE_2V6) || ((LEVEL) == PWR_PVDRANGRE_2V7) \
|
||||
|| ((LEVEL) == PWR_PVDRANGRE_2V8) || ((LEVEL) == PWR_PVDRANGRE_2V9) || ((LEVEL) == PWR_PVDRANGE_1V78) \
|
||||
|| ((LEVEL) == PWR_PVDRANGE_1V88) || ((LEVEL) == PWR_PVDRANGE_1V98) || ((LEVEL) == PWR_PVDRANGE_2V08) \
|
||||
|| ((LEVEL) == PWR_PVDRANGE_3V06) || ((LEVEL) == PWR_PVDRANGE_3V24) || ((LEVEL) == PWR_PVDRANGE_3V42) \
|
||||
|| ((LEVEL) == PWR_PVDRANGE_3V60))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Regulator_state_is_STOP_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_REGULATOR_ON ((uint32_t)0x00000000)
|
||||
#define PWR_REGULATOR_LOWPOWER ((uint32_t)0x00000001)
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_REGULATOR_ON) || ((REGULATOR) == PWR_REGULATOR_LOWPOWER))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STOP_mode_entry
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
|
||||
#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_WU_FLAG ((uint32_t)0x00000001)
|
||||
#define PWR_SB_FLAG ((uint32_t)0x00000002)
|
||||
#define PWR_PVDO_FLAG ((uint32_t)0x00000004)
|
||||
#define PWR_VBATF_FLAG ((uint32_t)0x00000008)
|
||||
#define IS_PWR_GET_FLAG(FLAG) \
|
||||
(((FLAG) == PWR_WU_FLAG) || ((FLAG) == PWR_SB_FLAG) || ((FLAG) == PWR_PVDO_FLAG) || ((FLAG) == PWR_VBATF_FLAG))
|
||||
|
||||
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_WU_FLAG) || ((FLAG) == PWR_SB_FLAG) || ((FLAG) == PWR_VBATF_FLAG))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void PWR_DeInit(void);
|
||||
void PWR_BackupAccessEnable(FunctionalState Cmd);
|
||||
void PWR_PvdEnable(FunctionalState Cmd);
|
||||
void PWR_PvdRangeConfig(uint32_t PWR_PVDLevel);
|
||||
void PWR_WakeUpPinEnable(FunctionalState Cmd);
|
||||
void PWR_EnterStopState(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
|
||||
void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_STOPEntry);
|
||||
void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry);
|
||||
void PWR_EnterStandbyState(void);
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
|
||||
void PWR_ClearFlag(uint32_t PWR_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __N32G45X_PWR_H__ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,354 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_qspi.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_QSPI_H__
|
||||
#define __N32G45X_QSPI_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
#include <stdbool.h>
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI
|
||||
* @brief QSPI driver modules
|
||||
* @{
|
||||
*/
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
typedef enum
|
||||
{
|
||||
STANDARD_SPI_FORMAT_SEL = 0,
|
||||
DUAL_SPI_FORMAT_SEL,
|
||||
QUAD_SPI_FORMAT_SEL,
|
||||
XIP_SPI_FORMAT_SEL
|
||||
} QSPI_FORMAT_SEL;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
TX_AND_RX = 0,
|
||||
TX_ONLY,
|
||||
RX_ONLY
|
||||
} QSPI_DATA_DIR;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
QSPI_NSS_PORTA_SEL,
|
||||
QSPI_NSS_PORTC_SEL,
|
||||
QSPI_NSS_PORTF_SEL
|
||||
} QSPI_NSS_PORT_SEL;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
QSPI_NULL = 0,
|
||||
QSPI_SUCCESS,
|
||||
} QSPI_STATUS;
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
#define QSPI_AFIO_PORT_SEL QSPI_NSS_PORTA_SEL
|
||||
|
||||
#define ENSPI_WAIT_8CYCLES 0x4000
|
||||
#define ENSPI_WAIT_4CYCLES 0x2000
|
||||
#define ENSPI_WAIT_2CYCLES 0x1000
|
||||
#define ENSPI_INST_L_08BIT 0x200
|
||||
#define ENSPI_ADDR_24BIT 0x18
|
||||
#define CLOCK_DIVIDER 12
|
||||
#define TX_COUNT_EN 0x01
|
||||
#define CTRL1_NDF_CNT 1024
|
||||
|
||||
#define XIP_PREFETCH_EN 1
|
||||
#define SRAM_CFG_EN 0
|
||||
|
||||
#define DMA_TX 0x10
|
||||
#define DMA_RX 0x01
|
||||
|
||||
#define QSPI_DMAReq_TxEN 0x02
|
||||
#define QSPI_DMAReq_RxEN 0x01
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
/* QSPI_CTRL0 */
|
||||
#define QSPI_CTRL0_DFS_4_BIT ((uint32_t)0x03)
|
||||
#define QSPI_CTRL0_DFS_5_BIT ((uint32_t)0x04)
|
||||
#define QSPI_CTRL0_DFS_6_BIT ((uint32_t)0x05)
|
||||
#define QSPI_CTRL0_DFS_7_BIT ((uint32_t)0x06)
|
||||
#define QSPI_CTRL0_DFS_8_BIT ((uint32_t)0x07)
|
||||
#define QSPI_CTRL0_DFS_9_BIT ((uint32_t)0x08)
|
||||
#define QSPI_CTRL0_DFS_10_BIT ((uint32_t)0x09)
|
||||
#define QSPI_CTRL0_DFS_11_BIT ((uint32_t)0x0A)
|
||||
#define QSPI_CTRL0_DFS_12_BIT ((uint32_t)0x0B)
|
||||
#define QSPI_CTRL0_DFS_13_BIT ((uint32_t)0x0C)
|
||||
#define QSPI_CTRL0_DFS_14_BIT ((uint32_t)0x0D)
|
||||
#define QSPI_CTRL0_DFS_15_BIT ((uint32_t)0x0E)
|
||||
#define QSPI_CTRL0_DFS_16_BIT ((uint32_t)0x0F)
|
||||
#define QSPI_CTRL0_DFS_17_BIT ((uint32_t)0x10)
|
||||
#define QSPI_CTRL0_DFS_18_BIT ((uint32_t)0x11)
|
||||
#define QSPI_CTRL0_DFS_19_BIT ((uint32_t)0x12)
|
||||
#define QSPI_CTRL0_DFS_20_BIT ((uint32_t)0x13)
|
||||
#define QSPI_CTRL0_DFS_21_BIT ((uint32_t)0x14)
|
||||
#define QSPI_CTRL0_DFS_22_BIT ((uint32_t)0x15)
|
||||
#define QSPI_CTRL0_DFS_23_BIT ((uint32_t)0x16)
|
||||
#define QSPI_CTRL0_DFS_24_BIT ((uint32_t)0x17)
|
||||
#define QSPI_CTRL0_DFS_25_BIT ((uint32_t)0x18)
|
||||
#define QSPI_CTRL0_DFS_26_BIT ((uint32_t)0x19)
|
||||
#define QSPI_CTRL0_DFS_27_BIT ((uint32_t)0x1A)
|
||||
#define QSPI_CTRL0_DFS_28_BIT ((uint32_t)0x1B)
|
||||
#define QSPI_CTRL0_DFS_29_BIT ((uint32_t)0x1C)
|
||||
#define QSPI_CTRL0_DFS_30_BIT ((uint32_t)0x1D)
|
||||
#define QSPI_CTRL0_DFS_31_BIT ((uint32_t)0x1E)
|
||||
#define QSPI_CTRL0_DFS_32_BIT ((uint32_t)0x1F)
|
||||
#define QSPI_CTRL0_FRF_MOTOROLA ((uint32_t)0x00000000)
|
||||
#define QSPI_CTRL0_FRF_TI ((uint32_t)0x00000040)
|
||||
#define QSPI_CTRL0_FRF_MICROWIRE ((uint32_t)0x00000080)
|
||||
#define QSPI_CTRL0_SCPH_FIRST_EDGE ((uint32_t)0x00000000)
|
||||
#define QSPI_CTRL0_SCPH_SECOND_EDGE ((uint32_t)0x00000100)
|
||||
#define QSPI_CTRL0_SCPOL_LOW ((uint32_t)0x00000000)
|
||||
#define QSPI_CTRL0_SCPOL_HIGH ((uint32_t)0x00000200)
|
||||
#define QSPI_CTRL0_TMOD_TX_AND_RX ((uint32_t)0x00000000)
|
||||
#define QSPI_CTRL0_TMOD_TX_ONLY ((uint32_t)0x00000400)
|
||||
#define QSPI_CTRL0_TMOD_RX_ONLY ((uint32_t)0x00000800)
|
||||
#define QSPI_CTRL0_TMOD_EEPROM_READ ((uint32_t)0x00000C00)
|
||||
#define QSPI_CTRL0_SRL_EN ((uint32_t)0x00002000)
|
||||
#define QSPI_CTRL0_SSTE_EN ((uint32_t)0x00004000)
|
||||
#define QSPI_CTRL0_CFS_1_BIT ((uint32_t)0x00000000)
|
||||
#define QSPI_CTRL0_CFS_2_BIT ((uint32_t)0x00010000)
|
||||
#define QSPI_CTRL0_CFS_3_BIT ((uint32_t)0x00020000)
|
||||
#define QSPI_CTRL0_CFS_4_BIT ((uint32_t)0x00030000)
|
||||
#define QSPI_CTRL0_CFS_5_BIT ((uint32_t)0x00040000)
|
||||
#define QSPI_CTRL0_CFS_6_BIT ((uint32_t)0x00050000)
|
||||
#define QSPI_CTRL0_CFS_7_BIT ((uint32_t)0x00060000)
|
||||
#define QSPI_CTRL0_CFS_8_BIT ((uint32_t)0x00070000)
|
||||
#define QSPI_CTRL0_CFS_9_BIT ((uint32_t)0x00080000)
|
||||
#define QSPI_CTRL0_CFS_10_BIT ((uint32_t)0x00090000)
|
||||
#define QSPI_CTRL0_CFS_11_BIT ((uint32_t)0x000A0000)
|
||||
#define QSPI_CTRL0_CFS_12_BIT ((uint32_t)0x000B0000)
|
||||
#define QSPI_CTRL0_CFS_13_BIT ((uint32_t)0x000C0000)
|
||||
#define QSPI_CTRL0_CFS_14_BIT ((uint32_t)0x000D0000)
|
||||
#define QSPI_CTRL0_CFS_15_BIT ((uint32_t)0x000E0000)
|
||||
#define QSPI_CTRL0_CFS_16_BIT ((uint32_t)0x000F0000)
|
||||
#define QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT ((uint32_t)0x00000000)
|
||||
#define QSPI_CTRL0_SPI_FRF_DUAL_FORMAT ((uint32_t)0x00400000)
|
||||
#define QSPI_CTRL0_SPI_FRF_QUAD_FORMAT ((uint32_t)0x00800000)
|
||||
|
||||
/* QSPI_EN */
|
||||
#define QSPI_EN_QEN ((uint32_t)0x01)
|
||||
/* QSPI_MW_CTRL */
|
||||
#define QSPI_MW_CTRL_MWMOD_SEQUENTIAL ((uint32_t)0x01)
|
||||
#define QSPI_MW_CTRL_MC_DIR_TX ((uint32_t)0x02)
|
||||
#define QSPI_MW_CTRL_MHS_EN ((uint32_t)0x04)
|
||||
|
||||
/* QSPI_SLAVE_EN */
|
||||
#define QSPI_SLAVE_EN_SEN ((uint32_t)0x01)
|
||||
|
||||
/* QSPI_STS */
|
||||
#define QSPI_STS_BUSY ((uint32_t)0x01)
|
||||
#define QSPI_STS_TXFNF_NOT_FULL ((uint32_t)0x02)
|
||||
#define QSPI_STS_TXFE_EMPTY ((uint32_t)0x04)
|
||||
#define QSPI_STS_RXFNE_NOT_EMPTY ((uint32_t)0x08)
|
||||
#define QSPI_STS_RXFF_FULL ((uint32_t)0x10)
|
||||
#define QSPI_STS_TX_ERR ((uint32_t)0x20)
|
||||
#define QSPI_STS_DC_ERR ((uint32_t)0x40)
|
||||
|
||||
/* QSPI_IMASK */
|
||||
#define QSPI_IMASK_TXFEIM ((uint32_t)0x01)
|
||||
#define QSPI_IMASK_TXFOIM ((uint32_t)0x02)
|
||||
#define QSPI_IMASK_RXFUIM ((uint32_t)0x04)
|
||||
#define QSPI_IMASK_RXFOIM ((uint32_t)0x08)
|
||||
#define QSPI_IMASK_RXFFIM ((uint32_t)0x10)
|
||||
#define QSPI_IMASK_MMCIM ((uint32_t)0x20)
|
||||
#define QSPI_IMASK_XRXOIMASK ((uint32_t)0x40)
|
||||
|
||||
/* QSPI_ISTS */
|
||||
#define QSPI_ISTS_TXFEIS ((uint32_t)0x01)
|
||||
#define QSPI_ISTS_TXFOIS ((uint32_t)0x02)
|
||||
#define QSPI_ISTS_RXFUIS ((uint32_t)0x04)
|
||||
#define QSPI_ISTS_RXFOIS ((uint32_t)0x08)
|
||||
#define QSPI_ISTS_RXFFIS ((uint32_t)0x10)
|
||||
#define QSPI_ISTS_MMCIS ((uint32_t)0x20)
|
||||
#define QSPI_ISTS_XRXOIS ((uint32_t)0x40)
|
||||
#define QSPI_ISTS_ICRS ((uint32_t)0xFF)
|
||||
|
||||
/* QSPI_RISTS */
|
||||
#define QSPI_RISTS_TXFERIS ((uint32_t)0x01)
|
||||
#define QSPI_RISTS_TXFORIS ((uint32_t)0x02)
|
||||
#define QSPI_RISTS_RXFURIS ((uint32_t)0x04)
|
||||
#define QSPI_RISTS_RXFORIS ((uint32_t)0x08)
|
||||
#define QSPI_RISTS_RXFFRIS ((uint32_t)0x10)
|
||||
#define QSPI_RISTS_MMCRIS ((uint32_t)0x20)
|
||||
#define QSPI_RISTS_XRXORIS ((uint32_t)0x40)
|
||||
|
||||
/* QSPI_TXFOI_CLR */
|
||||
#define QSPI_TXFOI_CLR_TXFOIC ((uint32_t)0x01)
|
||||
/* QSPI_RXFOI_CLR */
|
||||
#define QSPI_RXFOI_CLR_RXFOIC ((uint32_t)0x01)
|
||||
/* QSPI_RXFUI_CLR */
|
||||
#define QSPI_RXFUI_CLR_RXFUIC ((uint32_t)0x01)
|
||||
/* QSPI_MMC_CLR */
|
||||
#define QSPI_MMCI_CLR_MMCIC ((uint32_t)0x01)
|
||||
/* QSPI_ICLR */
|
||||
#define QSPI_ICLR_INTC ((uint32_t)0x01)
|
||||
/* QSPI_DMA_CTRL */
|
||||
#define QSPI_DMA_CTRL_RX_DAM_EN ((uint32_t)0x01)
|
||||
#define QSPI_DMA_CTRL_TX_DAM_EN ((uint32_t)0x02)
|
||||
|
||||
/* QSPI_RS_DELAY */
|
||||
#define QSPI_RS_DELAY_SDCN_0_CYCLES ((uint32_t)0x00)
|
||||
#define QSPI_RS_DELAY_SDCN_1_CYCLES ((uint32_t)0x01)
|
||||
#define QSPI_RS_DELAY_SDCN_2_CYCLES ((uint32_t)0x02)
|
||||
#define QSPI_RS_DELAY_SDCN_3_CYCLES ((uint32_t)0x03)
|
||||
#define QSPI_RS_DELAY_SDCN_4_CYCLES ((uint32_t)0x04)
|
||||
#define QSPI_RS_DELAY_SDCN_5_CYCLES ((uint32_t)0x05)
|
||||
#define QSPI_RS_DELAY_SDCN_6_CYCLES ((uint32_t)0x06)
|
||||
#define QSPI_RS_DELAY_SES_RISING_EDGE ((uint32_t)0x00)
|
||||
#define QSPI_RS_DELAY_SES_FALLING_EDGE ((uint32_t)0x01)
|
||||
|
||||
/* QSPI_ENH_CTRL0 */
|
||||
#define QSPI_ENH_CTRL0_TRANS_TYPE_STANDARD ((uint32_t)0x00000000)
|
||||
#define QSPI_ENH_CTRL0_TRANS_TYPE_ADDRESS_BY_FRF ((uint32_t)0x00000001)
|
||||
#define QSPI_ENH_CTRL0_TRANS_TYPE_ALL_BY_FRF ((uint32_t)0x00000002)
|
||||
#define QSPI_ENH_CTRL0_MD_BIT_EN ((uint32_t)0x00000080)
|
||||
#define QSPI_ENH_CTRL0_INST_L_0_LINE ((uint32_t)0x00000000)
|
||||
#define QSPI_ENH_CTRL0_INST_L_4_LINE ((uint32_t)0x00000100)
|
||||
#define QSPI_ENH_CTRL0_INST_L_8_LINE ((uint32_t)0x00000200)
|
||||
#define QSPI_ENH_CTRL0_INST_L_16_LINE ((uint32_t)0x00000300)
|
||||
#define QSPI_ENH_CTRL0_SPI_DDR_EN ((uint32_t)0x00010000)
|
||||
#define QSPI_ENH_CTRL0_INST_DDR_EN ((uint32_t)0x00020000)
|
||||
#define QSPI_ENH_CTRL0_XIP_DFS_HC ((uint32_t)0x00080000)
|
||||
#define QSPI_ENH_CTRL0_XIP_INST_EN ((uint32_t)0x00100000)
|
||||
#define QSPI_ENH_CTRL0_XIP_CT_EN ((uint32_t)0x00200000)
|
||||
#define QSPI_ENH_CTRL0_XIP_MBL_2_BIT ((uint32_t)0x00000000)
|
||||
#define QSPI_ENH_CTRL0_XIP_MBL_4_BIT ((uint32_t)0x04000000)
|
||||
#define QSPI_ENH_CTRL0_XIP_MBL_8_BIT ((uint32_t)0x08000000)
|
||||
#define QSPI_ENH_CTRL0_XIP_MBL_16_BIT ((uint32_t)0x0C000000)
|
||||
#define QSPI_ENH_CTRL0_CLK_STRETCH_EN ((uint32_t)0x40000000)
|
||||
|
||||
/* XIP_CTRL */
|
||||
#define XIP_CTRL_FRF_2_LINE ((uint32_t)0x00000001)
|
||||
#define XIP_CTRL_FRF_4_LINE ((uint32_t)0x00000002)
|
||||
#define XIP_CTRL_FRF_8_LINE ((uint32_t)0x00000003)
|
||||
#define XIP_CTRL_TRANS_TYPE_STANDARD_SPI ((uint32_t)0x00000000)
|
||||
#define XIP_CTRL_TRANS_TYPE_ADDRESS_BY_XIP_FRF ((uint32_t)0x00000004)
|
||||
#define XIP_CTRL_TRANS_TYPE_INSTRUCT_BY_XIP_FRF ((uint32_t)0x00000008)
|
||||
#define XIP_CTRL_INST_L_0_LINE ((uint32_t)0x00000000)
|
||||
#define XIP_CTRL_INST_L_4_LINE ((uint32_t)0x00000200)
|
||||
#define XIP_CTRL_INST_L_8_LINE ((uint32_t)0x00000400)
|
||||
#define XIP_CTRL_INST_L_16_LINE ((uint32_t)0x00000600)
|
||||
#define XIP_CTRL_MD_BITS_EN ((uint32_t)0x00001000)
|
||||
#define XIP_CTRL_DFS_HC ((uint32_t)0x00040000)
|
||||
#define XIP_CTRL_DDR_LEN ((uint32_t)0x00080000)
|
||||
#define XIP_CTRL_INST_DDR_EN ((uint32_t)0x00100000)
|
||||
#define XIP_CTRL_XIP_INST_EN ((uint32_t)0x00400000)
|
||||
#define XIP_CTRL_XIP_CT_EN ((uint32_t)0x00800000)
|
||||
#define XIP_CTRL_XIP_MBL_LEN_2_BIT ((uint32_t)0x00000000)
|
||||
#define XIP_CTRL_XIP_MBL_LEN_4_BIT ((uint32_t)0x04000000)
|
||||
#define XIP_CTRL_XIP_MBL_LEN_8_BIT ((uint32_t)0x08000000)
|
||||
#define XIP_CTRL_XIP_MBL_LEN_16_BIT ((uint32_t)0x0C000000)
|
||||
|
||||
/* XIP_SLAVE_EN */
|
||||
#define XIP_SLAVE_EN_SEN ((uint32_t)0x00000001)
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TRANS_TYPE;
|
||||
uint32_t SPI_FRF;
|
||||
uint32_t TMOD;
|
||||
uint32_t SCPOL;
|
||||
uint32_t SCPH;
|
||||
uint32_t CFS;
|
||||
uint32_t DFS;
|
||||
uint32_t SSTE;
|
||||
uint32_t SEN;
|
||||
uint32_t CLK_DIV;
|
||||
uint32_t WAIT_CYCLES;
|
||||
uint32_t INST_L;
|
||||
uint32_t ADDR_LEN;
|
||||
uint32_t NDF;
|
||||
uint32_t TXFT;
|
||||
uint32_t RXFT;
|
||||
|
||||
uint32_t ENHANCED_WAIT_CYCLES;
|
||||
uint32_t ENHANCED_CLK_STRETCH_EN;
|
||||
uint32_t ENHANCED_ADDR_LEN;
|
||||
uint32_t ENHANCED_INST_L;
|
||||
|
||||
uint32_t XIP_FRF;
|
||||
uint32_t XIP_TRANS_TYPE;
|
||||
uint32_t XIP_ADDR_LEN;
|
||||
uint32_t XIP_INST_L;
|
||||
uint32_t XIP_WAIT_CYCLES;
|
||||
uint32_t XIP_DFS_HC;
|
||||
uint32_t XIP_INST_EN;
|
||||
|
||||
} QSPI_InitType;
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
void QSPI_Cmd(bool cmd);
|
||||
void QspiInit(QSPI_FORMAT_SEL qspi_format_sel, QSPI_DATA_DIR data_dir, uint16_t count);
|
||||
void QSPI_DeInit(void);
|
||||
uint16_t QSPI_GetITStatus(uint16_t FLAG);
|
||||
void QSPI_ClearITFLAG(uint16_t FLAG);
|
||||
void QSPI_DMA_Config(uint32_t PeripheraAddr, uint32_t MemoryAddr, uint16_t Len, uint8_t TxRx);
|
||||
void QSPI_GPIO(QSPI_NSS_PORT_SEL qspi_nss_port_sel, bool IO1_Input, bool IO3_Output);
|
||||
//void QSPI_NVIC_Configuration(void);
|
||||
|
||||
bool GetQspiBusyStatus(void);
|
||||
bool GetQspiTxDataBusyStatus(void);
|
||||
bool GetQspiTxDataEmptyStatus(void);
|
||||
bool GetQspiRxHaveDataStatus(void);
|
||||
bool GetQspiRxDataFullStatus(void);
|
||||
bool GetQspiTransmitErrorStatus(void);
|
||||
bool GetQspiDataConflictErrorStatus(void);
|
||||
void QspiSendWord(uint32_t SendData);
|
||||
uint32_t QspiReadWord(void);
|
||||
uint32_t QspiGetDataPointer(void);
|
||||
uint32_t QspiReadRxFifoNum(void);
|
||||
void QspiSendAndGetWords(uint32_t* pSrcData, uint32_t* pDstData, uint32_t cnt);
|
||||
uint32_t QspiSendWordAndGetWords(uint32_t WrData, uint32_t* pRdData, uint8_t LastRd);
|
||||
void ClrFifo(void);
|
||||
uint32_t GetFifoData(uint32_t* pData, uint32_t Len);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__N32G45X_QSPI_H__ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,735 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_rcc.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_RCC_H__
|
||||
#define __N32G45X_RCC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SysclkFreq; /*!< returns SYSCLK clock frequency expressed in Hz */
|
||||
uint32_t HclkFreq; /*!< returns HCLK clock frequency expressed in Hz */
|
||||
uint32_t Pclk1Freq; /*!< returns PCLK1 clock frequency expressed in Hz */
|
||||
uint32_t Pclk2Freq; /*!< returns PCLK2 clock frequency expressed in Hz */
|
||||
uint32_t AdcPllClkFreq; /*!< returns ADCPLLCLK clock frequency expressed in Hz */
|
||||
uint32_t AdcHclkFreq; /*!< returns ADCHCLK clock frequency expressed in Hz */
|
||||
} RCC_ClocksType;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HSE_configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RC_HSE_DISABLE ((uint32_t)0x00000000)
|
||||
#define RCC_HSE_ENABLE ((uint32_t)0x00010000)
|
||||
#define RCC_HSE_BYPASS ((uint32_t)0x00040000)
|
||||
#define IS_RCC_HSE(HSE) (((HSE) == RC_HSE_DISABLE) || ((HSE) == RCC_HSE_ENABLE) || ((HSE) == RCC_HSE_BYPASS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PLL_entry_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PLL_SRC_HSI_DIV2 ((uint32_t)0x00000000)
|
||||
|
||||
#define RCC_PLL_SRC_HSE_DIV1 ((uint32_t)0x00010000)
|
||||
#define RCC_PLL_SRC_HSE_DIV2 ((uint32_t)0x00030000)
|
||||
#define IS_RCC_PLL_SRC(SOURCE) \
|
||||
(((SOURCE) == RCC_PLL_SRC_HSI_DIV2) || ((SOURCE) == RCC_PLL_SRC_HSE_DIV1) || ((SOURCE) == RCC_PLL_SRC_HSE_DIV2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PLL_multiplication_factor
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PLL_MUL_2 ((uint32_t)0x00000000)
|
||||
#define RCC_PLL_MUL_3 ((uint32_t)0x00040000)
|
||||
#define RCC_PLL_MUL_4 ((uint32_t)0x00080000)
|
||||
#define RCC_PLL_MUL_5 ((uint32_t)0x000C0000)
|
||||
#define RCC_PLL_MUL_6 ((uint32_t)0x00100000)
|
||||
#define RCC_PLL_MUL_7 ((uint32_t)0x00140000)
|
||||
#define RCC_PLL_MUL_8 ((uint32_t)0x00180000)
|
||||
#define RCC_PLL_MUL_9 ((uint32_t)0x001C0000)
|
||||
#define RCC_PLL_MUL_10 ((uint32_t)0x00200000)
|
||||
#define RCC_PLL_MUL_11 ((uint32_t)0x00240000)
|
||||
#define RCC_PLL_MUL_12 ((uint32_t)0x00280000)
|
||||
#define RCC_PLL_MUL_13 ((uint32_t)0x002C0000)
|
||||
#define RCC_PLL_MUL_14 ((uint32_t)0x00300000)
|
||||
#define RCC_PLL_MUL_15 ((uint32_t)0x00340000)
|
||||
#define RCC_PLL_MUL_16 ((uint32_t)0x00380000)
|
||||
#define RCC_PLL_MUL_17 ((uint32_t)0x08000000)
|
||||
#define RCC_PLL_MUL_18 ((uint32_t)0x08040000)
|
||||
#define RCC_PLL_MUL_19 ((uint32_t)0x08080000)
|
||||
#define RCC_PLL_MUL_20 ((uint32_t)0x080C0000)
|
||||
#define RCC_PLL_MUL_21 ((uint32_t)0x08100000)
|
||||
#define RCC_PLL_MUL_22 ((uint32_t)0x08140000)
|
||||
#define RCC_PLL_MUL_23 ((uint32_t)0x08180000)
|
||||
#define RCC_PLL_MUL_24 ((uint32_t)0x081C0000)
|
||||
#define RCC_PLL_MUL_25 ((uint32_t)0x08200000)
|
||||
#define RCC_PLL_MUL_26 ((uint32_t)0x08240000)
|
||||
#define RCC_PLL_MUL_27 ((uint32_t)0x08280000)
|
||||
#define RCC_PLL_MUL_28 ((uint32_t)0x082C0000)
|
||||
#define RCC_PLL_MUL_29 ((uint32_t)0x08300000)
|
||||
#define RCC_PLL_MUL_30 ((uint32_t)0x08340000)
|
||||
#define RCC_PLL_MUL_31 ((uint32_t)0x08380000)
|
||||
#define RCC_PLL_MUL_32 ((uint32_t)0x083C0000)
|
||||
#define IS_RCC_PLL_MUL(MUL) \
|
||||
(((MUL) == RCC_PLL_MUL_2) || ((MUL) == RCC_PLL_MUL_3) || ((MUL) == RCC_PLL_MUL_4) || ((MUL) == RCC_PLL_MUL_5) \
|
||||
|| ((MUL) == RCC_PLL_MUL_6) || ((MUL) == RCC_PLL_MUL_7) || ((MUL) == RCC_PLL_MUL_8) || ((MUL) == RCC_PLL_MUL_9) \
|
||||
|| ((MUL) == RCC_PLL_MUL_10) || ((MUL) == RCC_PLL_MUL_11) || ((MUL) == RCC_PLL_MUL_12) \
|
||||
|| ((MUL) == RCC_PLL_MUL_13) || ((MUL) == RCC_PLL_MUL_14) || ((MUL) == RCC_PLL_MUL_15) \
|
||||
|| ((MUL) == RCC_PLL_MUL_16) || ((MUL) == RCC_PLL_MUL_17) || ((MUL) == RCC_PLL_MUL_18) \
|
||||
|| ((MUL) == RCC_PLL_MUL_19) || ((MUL) == RCC_PLL_MUL_20) || ((MUL) == RCC_PLL_MUL_21) \
|
||||
|| ((MUL) == RCC_PLL_MUL_22) || ((MUL) == RCC_PLL_MUL_23) || ((MUL) == RCC_PLL_MUL_24) \
|
||||
|| ((MUL) == RCC_PLL_MUL_25) || ((MUL) == RCC_PLL_MUL_26) || ((MUL) == RCC_PLL_MUL_27) \
|
||||
|| ((MUL) == RCC_PLL_MUL_28) || ((MUL) == RCC_PLL_MUL_29) || ((MUL) == RCC_PLL_MUL_30) \
|
||||
|| ((MUL) == RCC_PLL_MUL_31) || ((MUL) == RCC_PLL_MUL_32))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup System_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_SYSCLK_SRC_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLK_SRC_HSE ((uint32_t)0x00000001)
|
||||
#define RCC_SYSCLK_SRC_PLLCLK ((uint32_t)0x00000002)
|
||||
#define IS_RCC_SYSCLK_SRC(SOURCE) \
|
||||
(((SOURCE) == RCC_SYSCLK_SRC_HSI) || ((SOURCE) == RCC_SYSCLK_SRC_HSE) || ((SOURCE) == RCC_SYSCLK_SRC_PLLCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup AHB_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_SYSCLK_DIV1 ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLK_DIV2 ((uint32_t)0x00000080)
|
||||
#define RCC_SYSCLK_DIV4 ((uint32_t)0x00000090)
|
||||
#define RCC_SYSCLK_DIV8 ((uint32_t)0x000000A0)
|
||||
#define RCC_SYSCLK_DIV16 ((uint32_t)0x000000B0)
|
||||
#define RCC_SYSCLK_DIV64 ((uint32_t)0x000000C0)
|
||||
#define RCC_SYSCLK_DIV128 ((uint32_t)0x000000D0)
|
||||
#define RCC_SYSCLK_DIV256 ((uint32_t)0x000000E0)
|
||||
#define RCC_SYSCLK_DIV512 ((uint32_t)0x000000F0)
|
||||
#define IS_RCC_SYSCLK_DIV(HCLK) \
|
||||
(((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || ((HCLK) == RCC_SYSCLK_DIV4) \
|
||||
|| ((HCLK) == RCC_SYSCLK_DIV8) || ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) \
|
||||
|| ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || ((HCLK) == RCC_SYSCLK_DIV512))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup APB1_APB2_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_HCLK_DIV1 ((uint32_t)0x00000000)
|
||||
#define RCC_HCLK_DIV2 ((uint32_t)0x00000400)
|
||||
#define RCC_HCLK_DIV4 ((uint32_t)0x00000500)
|
||||
#define RCC_HCLK_DIV8 ((uint32_t)0x00000600)
|
||||
#define RCC_HCLK_DIV16 ((uint32_t)0x00000700)
|
||||
#define IS_RCC_HCLK_DIV(PCLK) \
|
||||
(((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) \
|
||||
|| ((PCLK) == RCC_HCLK_DIV16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC_Interrupt_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_INT_LSIRDIF ((uint8_t)0x01)
|
||||
#define RCC_INT_LSERDIF ((uint8_t)0x02)
|
||||
#define RCC_INT_HSIRDIF ((uint8_t)0x04)
|
||||
#define RCC_INT_HSERDIF ((uint8_t)0x08)
|
||||
#define RCC_INT_PLLRDIF ((uint8_t)0x10)
|
||||
#define RCC_INT_CLKSSIF ((uint8_t)0x80)
|
||||
|
||||
#define IS_RCC_INT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))
|
||||
#define IS_RCC_GET_INT(IT) \
|
||||
(((IT) == RCC_INT_LSIRDIF) || ((IT) == RCC_INT_LSERDIF) || ((IT) == RCC_INT_HSIRDIF) || ((IT) == RCC_INT_HSERDIF) \
|
||||
|| ((IT) == RCC_INT_PLLRDIF) || ((IT) == RCC_INT_CLKSSIF))
|
||||
#define IS_RCC_CLR_INT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USB_Device_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_USBCLK_SRC_PLLCLK_DIV1_5 ((uint8_t)0x00)
|
||||
#define RCC_USBCLK_SRC_PLLCLK_DIV1 ((uint8_t)0x01)
|
||||
#define RCC_USBCLK_SRC_PLLCLK_DIV2 ((uint8_t)0x02)
|
||||
#define RCC_USBCLK_SRC_PLLCLK_DIV3 ((uint8_t)0x03)
|
||||
|
||||
#define IS_RCC_USBCLK_SRC(SOURCE) \
|
||||
(((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1_5) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV1) \
|
||||
|| ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV2) || ((SOURCE) == RCC_USBCLK_SRC_PLLCLK_DIV3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PCLK2_DIV2 ((uint32_t)0x00000000)
|
||||
#define RCC_PCLK2_DIV4 ((uint32_t)0x00004000)
|
||||
#define RCC_PCLK2_DIV6 ((uint32_t)0x00008000)
|
||||
#define RCC_PCLK2_DIV8 ((uint32_t)0x0000C000)
|
||||
#define IS_RCC_PCLK2_DIV(ADCCLK) \
|
||||
(((ADCCLK) == RCC_PCLK2_DIV2) || ((ADCCLK) == RCC_PCLK2_DIV4) || ((ADCCLK) == RCC_PCLK2_DIV6) \
|
||||
|| ((ADCCLK) == RCC_PCLK2_DIV8))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC_CFGR2_Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_TIM18CLK_SRC_TIM18CLK ((uint32_t)0x00000000)
|
||||
#define RCC_TIM18CLK_SRC_SYSCLK ((uint32_t)0x20000000)
|
||||
#define IS_RCC_TIM18CLKSRC(TIM18CLK) \
|
||||
(((TIM18CLK) == RCC_TIM18CLK_SRC_TIM18CLK) || ((TIM18CLK) == RCC_TIM18CLK_SRC_SYSCLK))
|
||||
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV1 ((uint32_t)0x00000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV2 ((uint32_t)0x01000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV3 ((uint32_t)0x02000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV4 ((uint32_t)0x03000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV5 ((uint32_t)0x04000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV6 ((uint32_t)0x05000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV7 ((uint32_t)0x06000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV8 ((uint32_t)0x07000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV9 ((uint32_t)0x08000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV10 ((uint32_t)0x09000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV11 ((uint32_t)0x0A000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV12 ((uint32_t)0x0B000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV13 ((uint32_t)0x0C000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV14 ((uint32_t)0x0D000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV15 ((uint32_t)0x0E000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV16 ((uint32_t)0x0F000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV17 ((uint32_t)0x10000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV18 ((uint32_t)0x11000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV19 ((uint32_t)0x12000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV20 ((uint32_t)0x13000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV21 ((uint32_t)0x14000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV22 ((uint32_t)0x15000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV23 ((uint32_t)0x16000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV24 ((uint32_t)0x17000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV25 ((uint32_t)0x18000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV26 ((uint32_t)0x19000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV27 ((uint32_t)0x1A000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV28 ((uint32_t)0x1B000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV29 ((uint32_t)0x1C000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV30 ((uint32_t)0x1D000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV31 ((uint32_t)0x1E000000)
|
||||
#define RCC_RNGCCLK_SYSCLK_DIV32 ((uint32_t)0x1F000000)
|
||||
#define IS_RCC_RNGCCLKPRE(DIV) \
|
||||
(((DIV) == RCC_RNGCCLK_SYSCLK_DIV1) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV2) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV3) \
|
||||
|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV4) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV5) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV6) \
|
||||
|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV7) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV8) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV9) \
|
||||
|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV10) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV11) \
|
||||
|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV12) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV13) \
|
||||
|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV14) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV15) \
|
||||
|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV16) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV17) \
|
||||
|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV18) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV19) \
|
||||
|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV20) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV21) \
|
||||
|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV22) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV23) \
|
||||
|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV24) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV25) \
|
||||
|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV26) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV27) \
|
||||
|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV28) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV29) \
|
||||
|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV30) || ((DIV) == RCC_RNGCCLK_SYSCLK_DIV31) \
|
||||
|| ((DIV) == RCC_RNGCCLK_SYSCLK_DIV32))
|
||||
|
||||
#define RCC_ETHCLK_SRC_IOINPUTCLK ((uint32_t)0x00000000)
|
||||
#define RCC_ETHCLK_SRC_INTERNALCLK ((uint32_t)0x00100000)
|
||||
#define IS_RCC_ETHCLK_SRC(ETHCLK) (((ETHCLK) == RCC_ETHCLK_SRC_IOINPUTCLK) || ((ETHCLK) == RCC_ETHCLK_SRC_INTERNALCLK))
|
||||
|
||||
#define RCC_ADC1MCLK_SRC_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_ADC1MCLK_SRC_HSE ((uint32_t)0x00020000)
|
||||
#define IS_RCC_ADC1MCLKSRC(ADC1MCLK) (((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSI) || ((ADC1MCLK) == RCC_ADC1MCLK_SRC_HSE))
|
||||
|
||||
#define RCC_ADC1MCLK_DIV1 ((uint32_t)0x00000000)
|
||||
#define RCC_ADC1MCLK_DIV2 ((uint32_t)0x00000800)
|
||||
#define RCC_ADC1MCLK_DIV3 ((uint32_t)0x00001000)
|
||||
#define RCC_ADC1MCLK_DIV4 ((uint32_t)0x00001800)
|
||||
#define RCC_ADC1MCLK_DIV5 ((uint32_t)0x00002000)
|
||||
#define RCC_ADC1MCLK_DIV6 ((uint32_t)0x00002800)
|
||||
#define RCC_ADC1MCLK_DIV7 ((uint32_t)0x00003000)
|
||||
#define RCC_ADC1MCLK_DIV8 ((uint32_t)0x00003800)
|
||||
#define RCC_ADC1MCLK_DIV9 ((uint32_t)0x00004000)
|
||||
#define RCC_ADC1MCLK_DIV10 ((uint32_t)0x00004800)
|
||||
#define RCC_ADC1MCLK_DIV11 ((uint32_t)0x00005000)
|
||||
#define RCC_ADC1MCLK_DIV12 ((uint32_t)0x00005800)
|
||||
#define RCC_ADC1MCLK_DIV13 ((uint32_t)0x00006000)
|
||||
#define RCC_ADC1MCLK_DIV14 ((uint32_t)0x00006800)
|
||||
#define RCC_ADC1MCLK_DIV15 ((uint32_t)0x00007000)
|
||||
#define RCC_ADC1MCLK_DIV16 ((uint32_t)0x00007800)
|
||||
#define RCC_ADC1MCLK_DIV17 ((uint32_t)0x00008000)
|
||||
#define RCC_ADC1MCLK_DIV18 ((uint32_t)0x00008800)
|
||||
#define RCC_ADC1MCLK_DIV19 ((uint32_t)0x00009000)
|
||||
#define RCC_ADC1MCLK_DIV20 ((uint32_t)0x00009800)
|
||||
#define RCC_ADC1MCLK_DIV21 ((uint32_t)0x0000A000)
|
||||
#define RCC_ADC1MCLK_DIV22 ((uint32_t)0x0000A800)
|
||||
#define RCC_ADC1MCLK_DIV23 ((uint32_t)0x0000B000)
|
||||
#define RCC_ADC1MCLK_DIV24 ((uint32_t)0x0000B800)
|
||||
#define RCC_ADC1MCLK_DIV25 ((uint32_t)0x0000C000)
|
||||
#define RCC_ADC1MCLK_DIV26 ((uint32_t)0x0000C800)
|
||||
#define RCC_ADC1MCLK_DIV27 ((uint32_t)0x0000D000)
|
||||
#define RCC_ADC1MCLK_DIV28 ((uint32_t)0x0000D800)
|
||||
#define RCC_ADC1MCLK_DIV29 ((uint32_t)0x0000E000)
|
||||
#define RCC_ADC1MCLK_DIV30 ((uint32_t)0x0000E800)
|
||||
#define RCC_ADC1MCLK_DIV31 ((uint32_t)0x0000F000)
|
||||
#define RCC_ADC1MCLK_DIV32 ((uint32_t)0x0000F800)
|
||||
#define IS_RCC_ADC1MCLKPRE(DIV) \
|
||||
(((DIV) == RCC_ADC1MCLK_DIV1) || ((DIV) == RCC_ADC1MCLK_DIV2) || ((DIV) == RCC_ADC1MCLK_DIV3) \
|
||||
|| ((DIV) == RCC_ADC1MCLK_DIV4) || ((DIV) == RCC_ADC1MCLK_DIV5) || ((DIV) == RCC_ADC1MCLK_DIV6) \
|
||||
|| ((DIV) == RCC_ADC1MCLK_DIV7) || ((DIV) == RCC_ADC1MCLK_DIV8) || ((DIV) == RCC_ADC1MCLK_DIV9) \
|
||||
|| ((DIV) == RCC_ADC1MCLK_DIV10) || ((DIV) == RCC_ADC1MCLK_DIV11) || ((DIV) == RCC_ADC1MCLK_DIV12) \
|
||||
|| ((DIV) == RCC_ADC1MCLK_DIV13) || ((DIV) == RCC_ADC1MCLK_DIV14) || ((DIV) == RCC_ADC1MCLK_DIV15) \
|
||||
|| ((DIV) == RCC_ADC1MCLK_DIV16) || ((DIV) == RCC_ADC1MCLK_DIV17) || ((DIV) == RCC_ADC1MCLK_DIV18) \
|
||||
|| ((DIV) == RCC_ADC1MCLK_DIV19) || ((DIV) == RCC_ADC1MCLK_DIV20) || ((DIV) == RCC_ADC1MCLK_DIV21) \
|
||||
|| ((DIV) == RCC_ADC1MCLK_DIV22) || ((DIV) == RCC_ADC1MCLK_DIV23) || ((DIV) == RCC_ADC1MCLK_DIV24) \
|
||||
|| ((DIV) == RCC_ADC1MCLK_DIV25) || ((DIV) == RCC_ADC1MCLK_DIV26) || ((DIV) == RCC_ADC1MCLK_DIV27) \
|
||||
|| ((DIV) == RCC_ADC1MCLK_DIV28) || ((DIV) == RCC_ADC1MCLK_DIV29) || ((DIV) == RCC_ADC1MCLK_DIV30) \
|
||||
|| ((DIV) == RCC_ADC1MCLK_DIV31) || ((DIV) == RCC_ADC1MCLK_DIV32))
|
||||
|
||||
#define RCC_ADCPLLCLK_DISABLE ((uint32_t)0xFFFFFEFF)
|
||||
#define RCC_ADCPLLCLK_DIV1 ((uint32_t)0x00000100)
|
||||
#define RCC_ADCPLLCLK_DIV2 ((uint32_t)0x00000110)
|
||||
#define RCC_ADCPLLCLK_DIV4 ((uint32_t)0x00000120)
|
||||
#define RCC_ADCPLLCLK_DIV6 ((uint32_t)0x00000130)
|
||||
#define RCC_ADCPLLCLK_DIV8 ((uint32_t)0x00000140)
|
||||
#define RCC_ADCPLLCLK_DIV10 ((uint32_t)0x00000150)
|
||||
#define RCC_ADCPLLCLK_DIV12 ((uint32_t)0x00000160)
|
||||
#define RCC_ADCPLLCLK_DIV16 ((uint32_t)0x00000170)
|
||||
#define RCC_ADCPLLCLK_DIV32 ((uint32_t)0x00000180)
|
||||
#define RCC_ADCPLLCLK_DIV64 ((uint32_t)0x00000190)
|
||||
#define RCC_ADCPLLCLK_DIV128 ((uint32_t)0x000001A0)
|
||||
#define RCC_ADCPLLCLK_DIV256 ((uint32_t)0x000001B0)
|
||||
#define RCC_ADCPLLCLK_DIV_OTHERS ((uint32_t)0x000001C0)
|
||||
#define IS_RCC_ADCPLLCLKPRE(DIV) \
|
||||
(((DIV) == RCC_ADCPLLCLK_DIV1) || ((DIV) == RCC_ADCPLLCLK_DIV2) || ((DIV) == RCC_ADCPLLCLK_DIV4) \
|
||||
|| ((DIV) == RCC_ADCPLLCLK_DIV6) || ((DIV) == RCC_ADCPLLCLK_DIV8) || ((DIV) == RCC_ADCPLLCLK_DIV10) \
|
||||
|| ((DIV) == RCC_ADCPLLCLK_DIV12) || ((DIV) == RCC_ADCPLLCLK_DIV16) || ((DIV) == RCC_ADCPLLCLK_DIV32) \
|
||||
|| ((DIV) == RCC_ADCPLLCLK_DIV64) || ((DIV) == RCC_ADCPLLCLK_DIV128) || ((DIV) == RCC_ADCPLLCLK_DIV256) \
|
||||
|| ((DIV) == RCC_ADC1MCLK_DIV15) || ((DIV) == RCC_ADCPLLCLK_DIV16) \
|
||||
|| (((DIV)&RCC_ADCPLLCLK_DIV_OTHERS) == 0x000001C0))
|
||||
|
||||
#define RCC_ADCHCLK_DIV1 ((uint32_t)0x00000000)
|
||||
#define RCC_ADCHCLK_DIV2 ((uint32_t)0x00000001)
|
||||
#define RCC_ADCHCLK_DIV4 ((uint32_t)0x00000002)
|
||||
#define RCC_ADCHCLK_DIV6 ((uint32_t)0x00000003)
|
||||
#define RCC_ADCHCLK_DIV8 ((uint32_t)0x00000004)
|
||||
#define RCC_ADCHCLK_DIV10 ((uint32_t)0x00000005)
|
||||
#define RCC_ADCHCLK_DIV12 ((uint32_t)0x00000006)
|
||||
#define RCC_ADCHCLK_DIV16 ((uint32_t)0x00000007)
|
||||
#define RCC_ADCHCLK_DIV32 ((uint32_t)0x00000008)
|
||||
#define RCC_ADCHCLK_DIV_OTHERS ((uint32_t)0x00000008)
|
||||
#define IS_RCC_ADCHCLKPRE(DIV) \
|
||||
(((DIV) == RCC_ADCHCLK_DIV1) || ((DIV) == RCC_ADCHCLK_DIV2) || ((DIV) == RCC_ADCHCLK_DIV4) \
|
||||
|| ((DIV) == RCC_ADCHCLK_DIV6) || ((DIV) == RCC_ADCHCLK_DIV8) || ((DIV) == RCC_ADCHCLK_DIV10) \
|
||||
|| ((DIV) == RCC_ADCHCLK_DIV12) || ((DIV) == RCC_ADCHCLK_DIV16) || ((DIV) == RCC_ADCHCLK_DIV32) \
|
||||
|| (((DIV)&RCC_ADCHCLK_DIV_OTHERS) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC_CFGR3_Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_BOR_RST_ENABLE ((uint32_t)0x00000040)
|
||||
|
||||
#define RCC_TRNG1MCLK_ENABLE ((uint32_t)0x00040000)
|
||||
#define RCC_TRNG1MCLK_DISABLE ((uint32_t)0xFFFBFFFF)
|
||||
|
||||
#define RCC_TRNG1MCLK_SRC_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_TRNG1MCLK_SRC_HSE ((uint32_t)0x00020000)
|
||||
#define IS_RCC_TRNG1MCLK_SRC(TRNG1MCLK) \
|
||||
(((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSI) || ((TRNG1MCLK) == RCC_TRNG1MCLK_SRC_HSE))
|
||||
|
||||
#define RCC_TRNG1MCLK_DIV1 ((uint32_t)0x00000000)
|
||||
#define RCC_TRNG1MCLK_DIV2 ((uint32_t)0x00000800)
|
||||
#define RCC_TRNG1MCLK_DIV3 ((uint32_t)0x00001000)
|
||||
#define RCC_TRNG1MCLK_DIV4 ((uint32_t)0x00001800)
|
||||
#define RCC_TRNG1MCLK_DIV5 ((uint32_t)0x00002000)
|
||||
#define RCC_TRNG1MCLK_DIV6 ((uint32_t)0x00002800)
|
||||
#define RCC_TRNG1MCLK_DIV7 ((uint32_t)0x00003000)
|
||||
#define RCC_TRNG1MCLK_DIV8 ((uint32_t)0x00003800)
|
||||
#define RCC_TRNG1MCLK_DIV9 ((uint32_t)0x00004000)
|
||||
#define RCC_TRNG1MCLK_DIV10 ((uint32_t)0x00004800)
|
||||
#define RCC_TRNG1MCLK_DIV11 ((uint32_t)0x00005000)
|
||||
#define RCC_TRNG1MCLK_DIV12 ((uint32_t)0x00005800)
|
||||
#define RCC_TRNG1MCLK_DIV13 ((uint32_t)0x00006000)
|
||||
#define RCC_TRNG1MCLK_DIV14 ((uint32_t)0x00006800)
|
||||
#define RCC_TRNG1MCLK_DIV15 ((uint32_t)0x00007000)
|
||||
#define RCC_TRNG1MCLK_DIV16 ((uint32_t)0x00007800)
|
||||
#define RCC_TRNG1MCLK_DIV17 ((uint32_t)0x00008000)
|
||||
#define RCC_TRNG1MCLK_DIV18 ((uint32_t)0x00008800)
|
||||
#define RCC_TRNG1MCLK_DIV19 ((uint32_t)0x00009000)
|
||||
#define RCC_TRNG1MCLK_DIV20 ((uint32_t)0x00009800)
|
||||
#define RCC_TRNG1MCLK_DIV21 ((uint32_t)0x0000A000)
|
||||
#define RCC_TRNG1MCLK_DIV22 ((uint32_t)0x0000A800)
|
||||
#define RCC_TRNG1MCLK_DIV23 ((uint32_t)0x0000B000)
|
||||
#define RCC_TRNG1MCLK_DIV24 ((uint32_t)0x0000B800)
|
||||
#define RCC_TRNG1MCLK_DIV25 ((uint32_t)0x0000C000)
|
||||
#define RCC_TRNG1MCLK_DIV26 ((uint32_t)0x0000C800)
|
||||
#define RCC_TRNG1MCLK_DIV27 ((uint32_t)0x0000D000)
|
||||
#define RCC_TRNG1MCLK_DIV28 ((uint32_t)0x0000D800)
|
||||
#define RCC_TRNG1MCLK_DIV29 ((uint32_t)0x0000E000)
|
||||
#define RCC_TRNG1MCLK_DIV30 ((uint32_t)0x0000E800)
|
||||
#define RCC_TRNG1MCLK_DIV31 ((uint32_t)0x0000F000)
|
||||
#define RCC_TRNG1MCLK_DIV32 ((uint32_t)0x0000F800)
|
||||
#define IS_RCC_TRNG1MCLKPRE(VAL) \
|
||||
(((VAL) == RCC_TRNG1MCLK_DIV1) || ((VAL) == RCC_TRNG1MCLK_DIV2) || ((VAL) == RCC_TRNG1MCLK_DIV3) \
|
||||
|| ((VAL) == RCC_TRNG1MCLK_DIV4) || ((VAL) == RCC_TRNG1MCLK_DIV5) || ((VAL) == RCC_TRNG1MCLK_DIV6) \
|
||||
|| ((VAL) == RCC_TRNG1MCLK_DIV7) || ((VAL) == RCC_TRNG1MCLK_DIV8) || ((VAL) == RCC_TRNG1MCLK_DIV9) \
|
||||
|| ((VAL) == RCC_TRNG1MCLK_DIV10) || ((VAL) == RCC_TRNG1MCLK_DIV11) || ((VAL) == RCC_TRNG1MCLK_DIV12) \
|
||||
|| ((VAL) == RCC_TRNG1MCLK_DIV13) || ((VAL) == RCC_TRNG1MCLK_DIV14) || ((VAL) == RCC_TRNG1MCLK_DIV15) \
|
||||
|| ((VAL) == RCC_TRNG1MCLK_DIV16) || ((VAL) == RCC_TRNG1MCLK_DIV17) || ((VAL) == RCC_TRNG1MCLK_DIV18) \
|
||||
|| ((VAL) == RCC_TRNG1MCLK_DIV19) || ((VAL) == RCC_TRNG1MCLK_DIV20) || ((VAL) == RCC_TRNG1MCLK_DIV21) \
|
||||
|| ((VAL) == RCC_TRNG1MCLK_DIV22) || ((VAL) == RCC_TRNG1MCLK_DIV23) || ((VAL) == RCC_TRNG1MCLK_DIV24) \
|
||||
|| ((VAL) == RCC_TRNG1MCLK_DIV25) || ((VAL) == RCC_TRNG1MCLK_DIV26) || ((VAL) == RCC_TRNG1MCLK_DIV27) \
|
||||
|| ((VAL) == RCC_TRNG1MCLK_DIV28) || ((VAL) == RCC_TRNG1MCLK_DIV29) || ((VAL) == RCC_TRNG1MCLK_DIV30) \
|
||||
|| ((VAL) == RCC_TRNG1MCLK_DIV31) || ((VAL) == RCC_TRNG1MCLK_DIV32))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup LSE_configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_LSE_DISABLE ((uint8_t)0x00)
|
||||
#define RCC_LSE_ENABLE ((uint8_t)0x01)
|
||||
#define RCC_LSE_BYPASS ((uint8_t)0x04)
|
||||
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_DISABLE) || ((LSE) == RCC_LSE_ENABLE) || ((LSE) == RCC_LSE_BYPASS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_RTCCLK_SRC_LSE ((uint32_t)0x00000100)
|
||||
#define RCC_RTCCLK_SRC_LSI ((uint32_t)0x00000200)
|
||||
#define RCC_RTCCLK_SRC_HSE_DIV128 ((uint32_t)0x00000300)
|
||||
#define IS_RCC_RTCCLK_SRC(SOURCE) \
|
||||
(((SOURCE) == RCC_RTCCLK_SRC_LSE) || ((SOURCE) == RCC_RTCCLK_SRC_LSI) || ((SOURCE) == RCC_RTCCLK_SRC_HSE_DIV128))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup AHB_peripheral
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_AHB_PERIPH_DMA1 ((uint32_t)0x00000001)
|
||||
#define RCC_AHB_PERIPH_DMA2 ((uint32_t)0x00000002)
|
||||
#define RCC_AHB_PERIPH_SRAM ((uint32_t)0x00000004)
|
||||
#define RCC_AHB_PERIPH_FLITF ((uint32_t)0x00000010)
|
||||
#define RCC_AHB_PERIPH_CRC ((uint32_t)0x00000040)
|
||||
#define RCC_AHB_PERIPH_XFMC ((uint32_t)0x00000100)
|
||||
#define RCC_AHB_PERIPH_RNGC ((uint32_t)0x00000200)
|
||||
#define RCC_AHB_PERIPH_SDIO ((uint32_t)0x00000400)
|
||||
#define RCC_AHB_PERIPH_SAC ((uint32_t)0x00000800)
|
||||
#define RCC_AHB_PERIPH_ADC1 ((uint32_t)0x00001000)
|
||||
#define RCC_AHB_PERIPH_ADC2 ((uint32_t)0x00002000)
|
||||
#define RCC_AHB_PERIPH_ADC3 ((uint32_t)0x00004000)
|
||||
#define RCC_AHB_PERIPH_ADC4 ((uint32_t)0x00008000)
|
||||
#define RCC_AHB_PERIPH_ETHMAC ((uint32_t)0x00010000)
|
||||
#define RCC_AHB_PERIPH_QSPI ((uint32_t)0x00020000)
|
||||
|
||||
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH)&0xFFFC02A8) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup APB2_peripheral
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_APB2_PERIPH_AFIO ((uint32_t)0x00000001)
|
||||
#define RCC_APB2_PERIPH_GPIOA ((uint32_t)0x00000004)
|
||||
#define RCC_APB2_PERIPH_GPIOB ((uint32_t)0x00000008)
|
||||
#define RCC_APB2_PERIPH_GPIOC ((uint32_t)0x00000010)
|
||||
#define RCC_APB2_PERIPH_GPIOD ((uint32_t)0x00000020)
|
||||
#define RCC_APB2_PERIPH_GPIOE ((uint32_t)0x00000040)
|
||||
#define RCC_APB2_PERIPH_GPIOF ((uint32_t)0x00000080)
|
||||
#define RCC_APB2_PERIPH_GPIOG ((uint32_t)0x00000100)
|
||||
#define RCC_APB2_PERIPH_TIM1 ((uint32_t)0x00000800)
|
||||
#define RCC_APB2_PERIPH_SPI1 ((uint32_t)0x00001000)
|
||||
#define RCC_APB2_PERIPH_TIM8 ((uint32_t)0x00002000)
|
||||
#define RCC_APB2_PERIPH_USART1 ((uint32_t)0x00004000)
|
||||
#define RCC_APB2_PERIPH_DVP ((uint32_t)0x00010000)
|
||||
#define RCC_APB2_PERIPH_UART6 ((uint32_t)0x00020000)
|
||||
#define RCC_APB2_PERIPH_UART7 ((uint32_t)0x00040000)
|
||||
#define RCC_APB2_PERIPH_I2C3 ((uint32_t)0x00080000)
|
||||
#define RCC_APB2_PERIPH_I2C4 ((uint32_t)0x00100000)
|
||||
|
||||
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH)&0xFFE08602) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup APB1_peripheral
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_APB1_PERIPH_TIM2 ((uint32_t)0x00000001)
|
||||
#define RCC_APB1_PERIPH_TIM3 ((uint32_t)0x00000002)
|
||||
#define RCC_APB1_PERIPH_TIM4 ((uint32_t)0x00000004)
|
||||
#define RCC_APB1_PERIPH_TIM5 ((uint32_t)0x00000008)
|
||||
#define RCC_APB1_PERIPH_TIM6 ((uint32_t)0x00000010)
|
||||
#define RCC_APB1_PERIPH_TIM7 ((uint32_t)0x00000020)
|
||||
#define RCC_APB1_PERIPH_COMP ((uint32_t)0x00000040)
|
||||
#define RCC_APB1_PERIPH_COMP_FILT ((uint32_t)0x00000080)
|
||||
#define RCC_APB1_PERIPH_TSC ((uint32_t)0x00000400)
|
||||
#define RCC_APB1_PERIPH_WWDG ((uint32_t)0x00000800)
|
||||
#define RCC_APB1_PERIPH_SPI2 ((uint32_t)0x00004000)
|
||||
#define RCC_APB1_PERIPH_SPI3 ((uint32_t)0x00008000)
|
||||
#define RCC_APB1_PERIPH_USART2 ((uint32_t)0x00020000)
|
||||
#define RCC_APB1_PERIPH_USART3 ((uint32_t)0x00040000)
|
||||
#define RCC_APB1_PERIPH_UART4 ((uint32_t)0x00080000)
|
||||
#define RCC_APB1_PERIPH_UART5 ((uint32_t)0x00100000)
|
||||
#define RCC_APB1_PERIPH_I2C1 ((uint32_t)0x00200000)
|
||||
#define RCC_APB1_PERIPH_I2C2 ((uint32_t)0x00400000)
|
||||
#define RCC_APB1_PERIPH_USB ((uint32_t)0x00800000)
|
||||
#define RCC_APB1_PERIPH_CAN1 ((uint32_t)0x02000000)
|
||||
#define RCC_APB1_PERIPH_CAN2 ((uint32_t)0x04000000)
|
||||
#define RCC_APB1_PERIPH_BKP ((uint32_t)0x08000000)
|
||||
#define RCC_APB1_PERIPH_PWR ((uint32_t)0x10000000)
|
||||
#define RCC_APB1_PERIPH_DAC ((uint32_t)0x20000000)
|
||||
#define RCC_APB1_PERIPH_OPAMP ((uint32_t)0x80000000)
|
||||
|
||||
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH)&0x41013300) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define RCC_MCO_PLLCLK_DIV2 ((uint32_t)0x20000000)
|
||||
#define RCC_MCO_PLLCLK_DIV3 ((uint32_t)0x30000000)
|
||||
#define RCC_MCO_PLLCLK_DIV4 ((uint32_t)0x40000000)
|
||||
#define RCC_MCO_PLLCLK_DIV5 ((uint32_t)0x50000000)
|
||||
#define RCC_MCO_PLLCLK_DIV6 ((uint32_t)0x60000000)
|
||||
#define RCC_MCO_PLLCLK_DIV7 ((uint32_t)0x70000000)
|
||||
#define RCC_MCO_PLLCLK_DIV8 ((uint32_t)0x80000000)
|
||||
#define RCC_MCO_PLLCLK_DIV9 ((uint32_t)0x90000000)
|
||||
#define RCC_MCO_PLLCLK_DIV10 ((uint32_t)0xA0000000)
|
||||
#define RCC_MCO_PLLCLK_DIV11 ((uint32_t)0xB0000000)
|
||||
#define RCC_MCO_PLLCLK_DIV12 ((uint32_t)0xC0000000)
|
||||
#define RCC_MCO_PLLCLK_DIV13 ((uint32_t)0xD0000000)
|
||||
#define RCC_MCO_PLLCLK_DIV14 ((uint32_t)0xE0000000)
|
||||
#define RCC_MCO_PLLCLK_DIV15 ((uint32_t)0xF0000000)
|
||||
#define IS_RCC_MCOPLLCLKPRE(DIV) \
|
||||
(((DIV) == RCC_MCO_PLLCLK_DIV2) || ((DIV) == RCC_MCO_PLLCLK_DIV3) || ((DIV) == RCC_MCO_PLLCLK_DIV4) \
|
||||
|| ((DIV) == RCC_MCO_PLLCLK_DIV5) || ((DIV) == RCC_MCO_PLLCLK_DIV6) || ((DIV) == RCC_MCO_PLLCLK_DIV7) \
|
||||
|| ((DIV) == RCC_MCO_PLLCLK_DIV8) || ((DIV) == RCC_MCO_PLLCLK_DIV9) || ((DIV) == RCC_MCO_PLLCLK_DIV10) \
|
||||
|| ((DIV) == RCC_MCO_PLLCLK_DIV11) || ((DIV) == RCC_MCO_PLLCLK_DIV12) || ((DIV) == RCC_MCO_PLLCLK_DIV13) \
|
||||
|| ((DIV) == RCC_MCO_PLLCLK_DIV14) || ((DIV) == RCC_MCO_PLLCLK_DIV15))
|
||||
|
||||
/** @addtogroup Clock_source_to_output_on_MCO_pin
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_MCO_NOCLK ((uint8_t)0x00)
|
||||
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
|
||||
#define RCC_MCO_HSI ((uint8_t)0x05)
|
||||
#define RCC_MCO_HSE ((uint8_t)0x06)
|
||||
#define RCC_MCO_PLLCLK ((uint8_t)0x07)
|
||||
|
||||
#define IS_RCC_MCO(MCO) \
|
||||
(((MCO) == RCC_MCO_NOCLK) || ((MCO) == RCC_MCO_HSI) || ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) \
|
||||
|| ((MCO) == RCC_MCO_PLLCLK))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC_Flag
|
||||
* @{
|
||||
*/
|
||||
#define RCC_FLAG_HSIRD ((uint8_t)0x21)
|
||||
#define RCC_FLAG_HSERD ((uint8_t)0x31)
|
||||
#define RCC_FLAG_PLLRD ((uint8_t)0x39)
|
||||
#define RCC_FLAG_LSERD ((uint8_t)0x41)
|
||||
#define RCC_FLAG_LSIRD ((uint8_t)0x61)
|
||||
#define RCC_FLAG_BORRST ((uint8_t)0x73)
|
||||
#define RCC_FLAG_RETEMC ((uint8_t)0x74)
|
||||
#define RCC_FLAG_BKPEMC ((uint8_t)0x75)
|
||||
#define RCC_FLAG_RAMRST ((uint8_t)0x77)
|
||||
#define RCC_FLAG_MMURST ((uint8_t)0x79)
|
||||
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
|
||||
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
|
||||
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
|
||||
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
|
||||
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
|
||||
|
||||
#define IS_RCC_FLAG(FLAG) \
|
||||
(((FLAG) == RCC_FLAG_HSIRD) || ((FLAG) == RCC_FLAG_HSERD) || ((FLAG) == RCC_FLAG_PLLRD) \
|
||||
|| ((FLAG) == RCC_FLAG_LSERD) || ((FLAG) == RCC_FLAG_LSIRD) || ((FLAG) == RCC_FLAG_BORRST) \
|
||||
|| ((FLAG) == RCC_FLAG_RETEMC) || ((FLAG) == RCC_FLAG_BKPEMC) || ((FLAG) == RCC_FLAG_RAMRST) \
|
||||
|| ((FLAG) == RCC_FLAG_MMURST) || ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) \
|
||||
|| ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST) || ((FLAG) == RCC_FLAG_WWDGRST) \
|
||||
|| ((FLAG) == RCC_FLAG_LPWRRST))
|
||||
|
||||
#define IS_RCC_CALIB_VALUE(VALUE) ((VALUE) <= 0x1F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void RCC_DeInit(void);
|
||||
void RCC_ConfigHse(uint32_t RCC_HSE);
|
||||
ErrorStatus RCC_WaitHseStable(void);
|
||||
void RCC_SetHsiCalibValue(uint8_t HSICalibrationValue);
|
||||
void RCC_EnableHsi(FunctionalState Cmd);
|
||||
void RCC_ConfigPll(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
|
||||
void RCC_EnablePll(FunctionalState Cmd);
|
||||
|
||||
void RCC_ConfigSysclk(uint32_t RCC_SYSCLKSource);
|
||||
uint8_t RCC_GetSysclkSrc(void);
|
||||
void RCC_ConfigHclk(uint32_t RCC_SYSCLK);
|
||||
void RCC_ConfigPclk1(uint32_t RCC_HCLK);
|
||||
void RCC_ConfigPclk2(uint32_t RCC_HCLK);
|
||||
void RCC_ConfigInt(uint8_t RccInt, FunctionalState Cmd);
|
||||
|
||||
void RCC_ConfigUsbClk(uint32_t RCC_USBCLKSource);
|
||||
|
||||
void RCC_ConfigTim18Clk(uint32_t RCC_TIM18CLKSource);
|
||||
void RCC_ConfigRngcClk(uint32_t RCC_RNGCCLKPrescaler);
|
||||
void RCC_ConfigEthClk(uint32_t RCC_ETHCLKSource);
|
||||
|
||||
void RCC_ConfigAdc1mClk(uint32_t RCC_ADC1MCLKSource, uint32_t RCC_ADC1MPrescaler);
|
||||
void RCC_ConfigAdcPllClk(uint32_t RCC_ADCPLLCLKPrescaler, FunctionalState Cmd);
|
||||
void RCC_ConfigAdcHclk(uint32_t RCC_ADCHCLKPrescaler);
|
||||
|
||||
void RCC_ConfigTrng1mClk(uint32_t RCC_TRNG1MCLKSource, uint32_t RCC_TRNG1MPrescaler);
|
||||
void RCC_EnableTrng1mClk(FunctionalState Cmd);
|
||||
|
||||
void RCC_ConfigLse(uint8_t RCC_LSE);
|
||||
void RCC_EnableLsi(FunctionalState Cmd);
|
||||
void RCC_ConfigRtcClk(uint32_t RCC_RTCCLKSource);
|
||||
void RCC_EnableRtcClk(FunctionalState Cmd);
|
||||
void RCC_GetClocksFreqValue(RCC_ClocksType* RCC_Clocks);
|
||||
void RCC_EnableAHBPeriphClk(uint32_t RCC_AHBPeriph, FunctionalState Cmd);
|
||||
void RCC_EnableAPB2PeriphClk(uint32_t RCC_APB2Periph, FunctionalState Cmd);
|
||||
void RCC_EnableAPB1PeriphClk(uint32_t RCC_APB1Periph, FunctionalState Cmd);
|
||||
|
||||
void RCC_EnableAHBPeriphReset(uint32_t RCC_AHBPeriph, FunctionalState Cmd);
|
||||
void RCC_EnableAPB2PeriphReset(uint32_t RCC_APB2Periph, FunctionalState Cmd);
|
||||
void RCC_EnableAPB1PeriphReset(uint32_t RCC_APB1Periph, FunctionalState Cmd);
|
||||
void RCC_EnableBORReset(FunctionalState Cmd);
|
||||
void RCC_EnableBackupReset(FunctionalState Cmd);
|
||||
void RCC_EnableClockSecuritySystem(FunctionalState Cmd);
|
||||
void RCC_ConfigMcoPllClk(uint32_t RCC_MCOPLLCLKPrescaler);
|
||||
void RCC_ConfigMco(uint8_t RCC_MCO);
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||
void RCC_ClrFlag(void);
|
||||
INTStatus RCC_GetIntStatus(uint8_t RccInt);
|
||||
void RCC_ClrIntPendingBit(uint8_t RccInt);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __N32G45X_RCC_H__ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,675 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_rtc.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_RTC_H__
|
||||
#define __N32G45X_RTC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief RTC Init structures definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
|
||||
This parameter can be a value of @ref RTC_Hour_Formats */
|
||||
|
||||
uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
|
||||
This parameter must be set to a value lower than 0x7F */
|
||||
|
||||
uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
|
||||
This parameter must be set to a value lower than 0x7FFF */
|
||||
} RTC_InitType;
|
||||
|
||||
/**
|
||||
* @brief RTC Time structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Hours; /*!< Specifies the RTC Time Hour.
|
||||
This parameter must be set to a value in the 0-12 range
|
||||
if the RTC_12HOUR_FORMAT is selected or 0-23 range if
|
||||
the RTC_24HOUR_FORMAT is selected. */
|
||||
|
||||
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
|
||||
This parameter must be set to a value in the 0-59 range. */
|
||||
|
||||
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
|
||||
This parameter must be set to a value in the 0-59 range. */
|
||||
|
||||
uint8_t H12; /*!< Specifies the RTC AM/PM Time.
|
||||
This parameter can be a value of @ref RTC_AM_PM_Definitions */
|
||||
} RTC_TimeType;
|
||||
|
||||
/**
|
||||
* @brief RTC Date structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
|
||||
This parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
|
||||
This parameter can be a value of @ref RTC_Month_Date_Definitions */
|
||||
|
||||
uint8_t Date; /*!< Specifies the RTC Date.
|
||||
This parameter must be set to a value in the 1-31 range. */
|
||||
|
||||
uint8_t Year; /*!< Specifies the RTC Date Year.
|
||||
This parameter must be set to a value in the 0-99 range. */
|
||||
} RTC_DateType;
|
||||
|
||||
/**
|
||||
* @brief RTC Alarm structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RTC_TimeType AlarmTime; /*!< Specifies the RTC Alarm Time members. */
|
||||
|
||||
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
|
||||
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
|
||||
|
||||
uint32_t DateWeekMode; /*!< Specifies the RTC Alarm is on Date or WeekDay.
|
||||
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
|
||||
|
||||
uint8_t DateWeekValue; /*!< Specifies the RTC Alarm Date/WeekDay.
|
||||
If the Alarm Date is selected, this parameter
|
||||
must be set to a value in the 1-31 range.
|
||||
If the Alarm WeekDay is selected, this
|
||||
parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
} RTC_AlarmType;
|
||||
|
||||
/** @addtogroup RTC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Hour_Formats
|
||||
* @{
|
||||
*/
|
||||
#define RTC_24HOUR_FORMAT ((uint32_t)0x00000000)
|
||||
#define RTC_12HOUR_FORMAT ((uint32_t)0x00000040)
|
||||
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_12HOUR_FORMAT) || ((FORMAT) == RTC_24HOUR_FORMAT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Asynchronous_Predivider
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_PREDIV_ASYNCH(PREDIV) ((PREDIV) <= 0x7F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Synchronous_Predivider
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_PREDIV_SYNCH(PREDIV) ((PREDIV) <= 0x7FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Time_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_12HOUR(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
|
||||
#define IS_RTC_24HOUR(HOUR) ((HOUR) <= 23)
|
||||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
|
||||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_AM_PM_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_AM_H12 ((uint8_t)0x00)
|
||||
#define RTC_PM_H12 ((uint8_t)0x40)
|
||||
#define IS_RTC_H12(PM) (((PM) == RTC_AM_H12) || ((PM) == RTC_PM_H12))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Year_Date_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Month_Date_Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Coded in BCD format */
|
||||
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
|
||||
#define RTC_MONTH_FEBRURY ((uint8_t)0x02)
|
||||
#define RTC_MONTH_MARCH ((uint8_t)0x03)
|
||||
#define RTC_MONTH_APRIL ((uint8_t)0x04)
|
||||
#define RTC_MONTH_MAY ((uint8_t)0x05)
|
||||
#define RTC_MONTH_JUNE ((uint8_t)0x06)
|
||||
#define RTC_MONTH_JULY ((uint8_t)0x07)
|
||||
#define RTC_MONTH_AUGUST ((uint8_t)0x08)
|
||||
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
|
||||
#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
|
||||
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
|
||||
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
|
||||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
|
||||
#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_WeekDay_Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
|
||||
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
|
||||
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
|
||||
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
|
||||
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
|
||||
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
|
||||
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
|
||||
#define IS_RTC_WEEKDAY(WEEKDAY) \
|
||||
(((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) \
|
||||
|| ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) \
|
||||
|| ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Alarm_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_ALARM_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
|
||||
#define IS_RTC_ALARM_WEEKDAY_WEEKDAY(WEEKDAY) \
|
||||
(((WEEKDAY) == RTC_WEEKDAY_MONDAY) || ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) \
|
||||
|| ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) \
|
||||
|| ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_AlarmDateWeekDay_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARM_SEL_WEEKDAY_DATE ((uint32_t)0x00000000)
|
||||
#define RTC_ALARM_SEL_WEEKDAY_WEEKDAY ((uint32_t)0x40000000)
|
||||
|
||||
#define IS_RTC_ALARM_WEEKDAY_SEL(SEL) \
|
||||
(((SEL) == RTC_ALARM_SEL_WEEKDAY_DATE) || ((SEL) == RTC_ALARM_SEL_WEEKDAY_WEEKDAY))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_AlarmMask_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
|
||||
#define RTC_ALARMMASK_WEEKDAY ((uint32_t)0x80000000)
|
||||
#define RTC_ALARMMASK_HOURS ((uint32_t)0x00800000)
|
||||
#define RTC_ALARMMASK_MINUTES ((uint32_t)0x00008000)
|
||||
#define RTC_ALARMMASK_SECONDS ((uint32_t)0x00000080)
|
||||
#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
|
||||
#define IS_ALARM_MASK(INTEN) (((INTEN)&0x7F7F7F7F) == (uint32_t)RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Alarms_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_A_ALARM ((uint32_t)0x00000100)
|
||||
#define RTC_B_ALARM ((uint32_t)0x00000200)
|
||||
#define IS_RTC_ALARM_SEL(ALARM) (((ALARM) == RTC_A_ALARM) || ((ALARM) == RTC_B_ALARM))
|
||||
#define IS_RTC_ALARM_ENABLE(ALARM) (((ALARM) & (RTC_A_ALARM | RTC_B_ALARM)) != (uint32_t)RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Alarm_Sub_Seconds_Masks_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SUBS_MASK_ALL \
|
||||
((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. \
|
||||
There is no comparison on sub seconds \
|
||||
for Alarm */
|
||||
#define RTC_SUBS_MASK_SS14_1 \
|
||||
((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm \
|
||||
comparison. Only SS[0] is compared. */
|
||||
#define RTC_SUBS_MASK_SS14_2 \
|
||||
((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm \
|
||||
comparison. Only SS[1:0] are compared */
|
||||
#define RTC_SUBS_MASK_SS14_3 \
|
||||
((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm \
|
||||
comparison. Only SS[2:0] are compared */
|
||||
#define RTC_SUBS_MASK_SS14_4 \
|
||||
((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm \
|
||||
comparison. Only SS[3:0] are compared */
|
||||
#define RTC_SUBS_MASK_SS14_5 \
|
||||
((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm \
|
||||
comparison. Only SS[4:0] are compared */
|
||||
#define RTC_SUBS_MASK_SS14_6 \
|
||||
((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm \
|
||||
comparison. Only SS[5:0] are compared */
|
||||
#define RTC_SUBS_MASK_SS14_7 \
|
||||
((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm \
|
||||
comparison. Only SS[6:0] are compared */
|
||||
#define RTC_SUBS_MASK_SS14_8 \
|
||||
((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm \
|
||||
comparison. Only SS[7:0] are compared */
|
||||
#define RTC_SUBS_MASK_SS14_9 \
|
||||
((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm \
|
||||
comparison. Only SS[8:0] are compared */
|
||||
#define RTC_SUBS_MASK_SS14_10 \
|
||||
((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm \
|
||||
comparison. Only SS[9:0] are compared */
|
||||
#define RTC_SUBS_MASK_SS14_11 \
|
||||
((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm \
|
||||
comparison. Only SS[10:0] are compared */
|
||||
#define RTC_SUBS_MASK_SS14_12 \
|
||||
((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm \
|
||||
comparison.Only SS[11:0] are compared */
|
||||
#define RTC_SUBS_MASK_SS14_13 \
|
||||
((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm \
|
||||
comparison. Only SS[12:0] are compared */
|
||||
#define RTC_SUBS_MASK_SS14_14 \
|
||||
((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm \
|
||||
comparison.Only SS[13:0] are compared */
|
||||
#define RTC_SUBS_MASK_NONE \
|
||||
((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match \
|
||||
to activate alarm. */
|
||||
#define IS_RTC_ALARM_SUB_SECOND_MASK_MODE(INTEN) \
|
||||
(((INTEN) == RTC_SUBS_MASK_ALL) || ((INTEN) == RTC_SUBS_MASK_SS14_1) || ((INTEN) == RTC_SUBS_MASK_SS14_2) \
|
||||
|| ((INTEN) == RTC_SUBS_MASK_SS14_3) || ((INTEN) == RTC_SUBS_MASK_SS14_4) || ((INTEN) == RTC_SUBS_MASK_SS14_5) \
|
||||
|| ((INTEN) == RTC_SUBS_MASK_SS14_6) || ((INTEN) == RTC_SUBS_MASK_SS14_7) || ((INTEN) == RTC_SUBS_MASK_SS14_8) \
|
||||
|| ((INTEN) == RTC_SUBS_MASK_SS14_9) || ((INTEN) == RTC_SUBS_MASK_SS14_10) || ((INTEN) == RTC_SUBS_MASK_SS14_11) \
|
||||
|| ((INTEN) == RTC_SUBS_MASK_SS14_12) || ((INTEN) == RTC_SUBS_MASK_SS14_13) || ((INTEN) == RTC_SUBS_MASK_SS14_14) \
|
||||
|| ((INTEN) == RTC_SUBS_MASK_NONE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Alarm_Sub_Seconds_Value
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Wakeup_Timer_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_WKUPCLK_RTCCLK_DIV16 ((uint32_t)0x00000000)
|
||||
#define RTC_WKUPCLK_RTCCLK_DIV8 ((uint32_t)0x00000001)
|
||||
#define RTC_WKUPCLK_RTCCLK_DIV4 ((uint32_t)0x00000002)
|
||||
#define RTC_WKUPCLK_RTCCLK_DIV2 ((uint32_t)0x00000003)
|
||||
#define RTC_WKUPCLK_CK_SPRE_16BITS ((uint32_t)0x00000004)
|
||||
#define RTC_WKUPCLK_CK_SPRE_17BITS ((uint32_t)0x00000006)
|
||||
#define IS_RTC_WKUP_CLOCK(CLOCK) \
|
||||
(((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV16) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV8) \
|
||||
|| ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV4) || ((CLOCK) == RTC_WKUPCLK_RTCCLK_DIV2) \
|
||||
|| ((CLOCK) == RTC_WKUPCLK_CK_SPRE_16BITS) || ((CLOCK) == RTC_WKUPCLK_CK_SPRE_17BITS))
|
||||
#define IS_RTC_WKUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Time_Stamp_Edges_definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TIMESTAMP_EDGE_RISING ((uint32_t)0x00000000)
|
||||
#define RTC_TIMESTAMP_EDGE_FALLING ((uint32_t)0x00000008)
|
||||
#define IS_RTC_TIMESTAMP_EDGE_MODE(EDGE) \
|
||||
(((EDGE) == RTC_TIMESTAMP_EDGE_RISING) || ((EDGE) == RTC_TIMESTAMP_EDGE_FALLING))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Output_selection_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_DIS ((uint32_t)0x00000000)
|
||||
#define RTC_OUTPUT_ALA ((uint32_t)0x00200000)
|
||||
#define RTC_OUTPUT_ALB ((uint32_t)0x00400000)
|
||||
#define RTC_OUTPUT_WKUP ((uint32_t)0x00600000)
|
||||
|
||||
#define IS_RTC_OUTPUT_MODE(OUTPUT) \
|
||||
(((OUTPUT) == RTC_OUTPUT_DIS) || ((OUTPUT) == RTC_OUTPUT_ALA) || ((OUTPUT) == RTC_OUTPUT_ALB) \
|
||||
|| ((OUTPUT) == RTC_OUTPUT_WKUP))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Output_Polarity_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPOL_HIGH ((uint32_t)0x00000000)
|
||||
#define RTC_OUTPOL_LOW ((uint32_t)0x00100000)
|
||||
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPOL_HIGH) || ((POL) == RTC_OUTPOL_LOW))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Coarse_Calibration_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_CALIB_POSITIVE ((uint32_t)0x00000000)
|
||||
#define RTC_CALIB_NEGATIVE ((uint32_t)0x00000080)
|
||||
#define IS_RTC_CALIB_DIR(SIGN) (((SIGN) == RTC_CALIB_POSITIVE) || ((SIGN) == RTC_CALIB_NEGATIVE))
|
||||
#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Calib_Output_selection_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_CALIB_OUTPUT_512HZ ((uint32_t)0x00000000)
|
||||
#define RTC_CALIB_OUTPUT_1HZ ((uint32_t)0x00080000)
|
||||
#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIB_OUTPUT_512HZ) || ((OUTPUT) == RTC_CALIB_OUTPUT_1HZ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Smooth_calib_period_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define SMOOTH_CALIB_32SEC \
|
||||
((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \
|
||||
period is 32s, else 2exp20 RTCCLK seconds */
|
||||
#define SMOOTH_CALIB_16SEC \
|
||||
((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \
|
||||
period is 16s, else 2exp19 RTCCLK seconds */
|
||||
#define SMOOTH_CALIB_8SEC \
|
||||
((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation \
|
||||
period is 8s, else 2exp18 RTCCLK seconds */
|
||||
#define IS_RTC_SMOOTH_CALIB_PERIOD_SEL(PERIOD) \
|
||||
(((PERIOD) == SMOOTH_CALIB_32SEC) || ((PERIOD) == SMOOTH_CALIB_16SEC) || ((PERIOD) == SMOOTH_CALIB_8SEC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Smooth_calib_Plus_pulses_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SMOOTH_CALIB_PLUS_PULSES_SET \
|
||||
((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added \
|
||||
during a X -second window = Y - CALM[8:0]. \
|
||||
with Y = 512, 256, 128 when X = 32, 16, 8 */
|
||||
#define RTC_SMOOTH_CALIB_PLUS_PULSES__RESET \
|
||||
((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited \
|
||||
during a 32-second window = CALM[8:0]. */
|
||||
#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) \
|
||||
(((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES_SET) || ((PLUS) == RTC_SMOOTH_CALIB_PLUS_PULSES__RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Smooth_calib_Minus_pulses_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_DayLightSaving_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DAYLIGHT_SAVING_SUB1H ((uint32_t)0x00020000)
|
||||
#define RTC_DAYLIGHT_SAVING_ADD1H ((uint32_t)0x00010000)
|
||||
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHT_SAVING_SUB1H) || ((SAVE) == RTC_DAYLIGHT_SAVING_ADD1H))
|
||||
|
||||
#define RTC_STORE_OPERATION_RESET ((uint32_t)0x00000000)
|
||||
#define RTC_STORE_OPERATION_SET ((uint32_t)0x00040000)
|
||||
#define IS_RTC_STORE_OPERATION(OPERATION) \
|
||||
(((OPERATION) == RTC_STORE_OPERATION_RESET) || ((OPERATION) == RTC_STORE_OPERATION_SET))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Output_Type_ALARM_OUT
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_OPENDRAIN ((uint32_t)0x00000000)
|
||||
#define RTC_OUTPUT_PUSHPULL ((uint32_t)0x00000001)
|
||||
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_OPENDRAIN) || ((TYPE) == RTC_OUTPUT_PUSHPULL))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Add_1_Second_Parameter_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SHIFT_ADD1S_DISABLE ((uint32_t)0x00000000)
|
||||
#define RTC_SHIFT_ADD1S_ENABLE ((uint32_t)0x80000000)
|
||||
#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFT_ADD1S_DISABLE) || ((SEL) == RTC_SHIFT_ADD1S_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Substract_Fraction_Of_Second_Value
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Input_parameter_format_definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FORMAT_BIN ((uint32_t)0x000000000)
|
||||
#define RTC_FORMAT_BCD ((uint32_t)0x000000001)
|
||||
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Flags_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_RECPF ((uint32_t)0x00010000)
|
||||
#define RTC_FLAG_TISOVF ((uint32_t)0x00001000)
|
||||
#define RTC_FLAG_TISF ((uint32_t)0x00000800)
|
||||
#define RTC_FLAG_WTF ((uint32_t)0x00000400)
|
||||
#define RTC_FLAG_ALBF ((uint32_t)0x00000200)
|
||||
#define RTC_FLAG_ALAF ((uint32_t)0x00000100)
|
||||
#define RTC_FLAG_INITF ((uint32_t)0x00000040)
|
||||
#define RTC_FLAG_RSYF ((uint32_t)0x00000020)
|
||||
#define RTC_FLAG_INITSF ((uint32_t)0x00000010)
|
||||
#define RTC_FLAG_SHOPF ((uint32_t)0x00000008)
|
||||
#define RTC_FLAG_WTWF ((uint32_t)0x00000004)
|
||||
#define RTC_FLAG_ALBWF ((uint32_t)0x00000002)
|
||||
#define RTC_FLAG_ALAWF ((uint32_t)0x00000001)
|
||||
#define IS_RTC_GET_FLAG(FLAG) \
|
||||
(((FLAG) == RTC_FLAG_TISOVF) || ((FLAG) == RTC_FLAG_TISF) || ((FLAG) == RTC_FLAG_WTF) || ((FLAG) == RTC_FLAG_ALBF) \
|
||||
|| ((FLAG) == RTC_FLAG_ALAF) || ((FLAG) == RTC_FLAG_INITF) || ((FLAG) == RTC_FLAG_RSYF) \
|
||||
|| ((FLAG) == RTC_FLAG_WTWF) || ((FLAG) == RTC_FLAG_ALBWF) || ((FLAG) == RTC_FLAG_ALAWF) \
|
||||
|| ((FLAG) == RTC_FLAG_RECPF) || ((FLAG) == RTC_FLAG_SHOPF) || ((FLAG) == RTC_FLAG_INITSF))
|
||||
#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG)&0xFFFF00DF) == (uint32_t)RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Interrupts_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_INT_TS ((uint32_t)0x00008000)
|
||||
#define RTC_INT_WUT ((uint32_t)0x00004000)
|
||||
#define RTC_INT_ALRB ((uint32_t)0x00002000)
|
||||
#define RTC_INT_ALRA ((uint32_t)0x00001000)
|
||||
|
||||
#define IS_RTC_CONFIG_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0xFFFF0FFB) == (uint32_t)RESET))
|
||||
#define IS_RTC_GET_INT(IT) \
|
||||
(((IT) == RTC_INT_TS) || ((IT) == RTC_INT_WUT) || ((IT) == RTC_INT_ALRB) || ((IT) == RTC_INT_ALRA))
|
||||
#define IS_RTC_CLEAR_INT(IT) (((IT) != (uint32_t)RESET) && (((IT)&0xFFF10FFF) == (uint32_t)RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC_Legacy
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig
|
||||
#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Function used to set the RTC configuration to the default reset state *****/
|
||||
ErrorStatus RTC_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
ErrorStatus RTC_Init(RTC_InitType* RTC_InitStruct);
|
||||
void RTC_StructInit(RTC_InitType* RTC_InitStruct);
|
||||
void RTC_EnableWriteProtection(FunctionalState Cmd);
|
||||
ErrorStatus RTC_EnterInitMode(void);
|
||||
void RTC_ExitInitMode(void);
|
||||
ErrorStatus RTC_WaitForSynchro(void);
|
||||
ErrorStatus RTC_EnableRefClock(FunctionalState Cmd);
|
||||
void RTC_EnableBypassShadow(FunctionalState Cmd);
|
||||
|
||||
/* Time and Date configuration functions **************************************/
|
||||
ErrorStatus RTC_ConfigTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct);
|
||||
void RTC_TimeStructInit(RTC_TimeType* RTC_TimeStruct);
|
||||
void RTC_GetTime(uint32_t RTC_Format, RTC_TimeType* RTC_TimeStruct);
|
||||
uint32_t RTC_GetSubSecond(void);
|
||||
ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct);
|
||||
void RTC_DateStructInit(RTC_DateType* RTC_DateStruct);
|
||||
void RTC_GetDate(uint32_t RTC_Format, RTC_DateType* RTC_DateStruct);
|
||||
|
||||
/* Alarms (Alarm A and Alarm B) configuration functions **********************/
|
||||
void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct);
|
||||
void RTC_AlarmStructInit(RTC_AlarmType* RTC_AlarmStruct);
|
||||
void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmType* RTC_AlarmStruct);
|
||||
ErrorStatus RTC_EnableAlarm(uint32_t RTC_Alarm, FunctionalState Cmd);
|
||||
void RTC_ConfigAlarmSubSecond(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
|
||||
uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
|
||||
|
||||
/* WakeUp Timer configuration functions ***************************************/
|
||||
void RTC_ConfigWakeUpClock(uint32_t RTC_WakeUpClock);
|
||||
void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
|
||||
uint32_t RTC_GetWakeUpCounter(void);
|
||||
ErrorStatus RTC_EnableWakeUp(FunctionalState Cmd);
|
||||
|
||||
/* Daylight Saving configuration functions ************************************/
|
||||
void RTC_ConfigDayLightSaving(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
|
||||
uint32_t RTC_GetStoreOperation(void);
|
||||
|
||||
/* Output pin Configuration function ******************************************/
|
||||
void RTC_ConfigOutput(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
|
||||
|
||||
/* Coarse and Smooth Calibration configuration functions **********************/
|
||||
void RTC_EnableCalibOutput(FunctionalState Cmd);
|
||||
void RTC_ConfigCalibOutput(uint32_t RTC_CalibOutput);
|
||||
ErrorStatus RTC_ConfigSmoothCalib(uint32_t RTC_SmoothCalibPeriod,
|
||||
uint32_t RTC_SmoothCalibPlusPulses,
|
||||
uint32_t RTC_SmouthCalibMinusPulsesValue);
|
||||
|
||||
/* TimeStamp configuration functions ******************************************/
|
||||
void RTC_EnableTimeStamp(uint32_t RTC_TimeStampEdge, FunctionalState Cmd);
|
||||
void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeType* RTC_StampTimeStruct, RTC_DateType* RTC_StampDateStruct);
|
||||
uint32_t RTC_GetTimeStampSubSecond(void);
|
||||
|
||||
/* Output Type Config configuration functions *********************************/
|
||||
void RTC_ConfigOutputType(uint32_t RTC_OutputType);
|
||||
|
||||
/* RTC_Shift_control_synchonisation_functions *********************************/
|
||||
ErrorStatus RTC_ConfigSynchroShift(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RTC_ConfigInt(uint32_t RTC_INT, FunctionalState Cmd);
|
||||
FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
|
||||
void RTC_ClrFlag(uint32_t RTC_FLAG);
|
||||
INTStatus RTC_GetITStatus(uint32_t RTC_INT);
|
||||
void RTC_ClrIntPendingBit(uint32_t RTC_INT);
|
||||
/* WakeUp TSC function **********************************/
|
||||
void RTC_EnableWakeUpTsc(uint32_t count);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__N32G45X_RTC_H__ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,494 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_sdio.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_SDIO_H__
|
||||
#define __N32G45X_SDIO_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClkEdge; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref SDIO_Clock_Edge */
|
||||
|
||||
uint32_t ClkBypass; /*!< Specifies whether the SDIO Clock divider bypass is
|
||||
enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_Clock_Bypass */
|
||||
|
||||
uint32_t ClkPwrSave; /*!< Specifies whether SDIO Clock output is enabled or
|
||||
disabled when the bus is idle.
|
||||
This parameter can be a value of @ref SDIO_Clock_Power_Save */
|
||||
|
||||
uint32_t BusWidth; /*!< Specifies the SDIO bus width.
|
||||
This parameter can be a value of @ref SDIO_Bus_Wide */
|
||||
|
||||
uint32_t HardwareClkCtrl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
|
||||
|
||||
uint8_t ClkDiv; /*!< Specifies the clock frequency of the SDIO controller.
|
||||
This parameter can be a value between 0x00 and 0xFF. */
|
||||
|
||||
} SDIO_InitType;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t CmdArgument; /*!< Specifies the SDIO command argument which is sent
|
||||
to a card as part of a command message. If a command
|
||||
contains an argument, it must be loaded into this register
|
||||
before writing the command to the command register */
|
||||
|
||||
uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
|
||||
|
||||
uint32_t ResponseType; /*!< Specifies the SDIO response type.
|
||||
This parameter can be a value of @ref SDIO_Response_Type */
|
||||
|
||||
uint32_t WaitType; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
|
||||
|
||||
uint32_t CPSMConfig; /*!< Specifies whether SDIO Command path state machine (CPSM)
|
||||
is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_CPSM_State */
|
||||
} SDIO_CmdInitType;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DatTimeout; /*!< Specifies the data timeout period in card bus clock periods. */
|
||||
|
||||
uint32_t DatLen; /*!< Specifies the number of data bytes to be transferred. */
|
||||
|
||||
uint32_t DatBlkSize; /*!< Specifies the data block size for block transfer.
|
||||
This parameter can be a value of @ref SDIO_Data_Block_Size */
|
||||
|
||||
uint32_t TransferDirection; /*!< Specifies the data transfer direction, whether the transfer
|
||||
is a read or write.
|
||||
This parameter can be a value of @ref SDIO_Transfer_Direction */
|
||||
|
||||
uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
|
||||
This parameter can be a value of @ref SDIO_Transfer_Type */
|
||||
|
||||
uint32_t DPSMConfig; /*!< Specifies whether SDIO Data path state machine (DPSM)
|
||||
is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_DPSM_State */
|
||||
} SDIO_DataInitType;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Clock_Edge
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_CLKEDGE_RISING ((uint32_t)0x00000000)
|
||||
#define SDIO_CLKEDGE_FALLING ((uint32_t)0x00002000)
|
||||
#define IS_SDIO_CLK_EDGE(EDGE) (((EDGE) == SDIO_CLKEDGE_RISING) || ((EDGE) == SDIO_CLKEDGE_FALLING))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Clock_Bypass
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_ClkBYPASS_DISABLE ((uint32_t)0x00000000)
|
||||
#define SDIO_ClkBYPASS_ENABLE ((uint32_t)0x00000400)
|
||||
#define IS_SDIO_CLK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClkBYPASS_DISABLE) || ((BYPASS) == SDIO_ClkBYPASS_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Clock_Power_Save
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_CLKPOWERSAVE_DISABLE ((uint32_t)0x00000000)
|
||||
#define SDIO_CLKPOWERSAVE_ENABLE ((uint32_t)0x00000200)
|
||||
#define IS_SDIO_CLK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLKPOWERSAVE_DISABLE) || ((SAVE) == SDIO_CLKPOWERSAVE_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Bus_Wide
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_BUSWIDTH_1B ((uint32_t)0x00000000)
|
||||
#define SDIO_BUSWIDTH_4B ((uint32_t)0x00000800)
|
||||
#define SDIO_BUSWIDTH_8B ((uint32_t)0x00001000)
|
||||
#define IS_SDIO_BUS_WIDTH(WIDE) \
|
||||
(((WIDE) == SDIO_BUSWIDTH_1B) || ((WIDE) == SDIO_BUSWIDTH_4B) || ((WIDE) == SDIO_BUSWIDTH_8B))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Hardware_Flow_Control
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_HARDWARE_CLKCTRL_DISABLE ((uint32_t)0x00000000)
|
||||
#define SDIO_HARDWARE_CLKCTRL_ENABLE ((uint32_t)0x00004000)
|
||||
#define IS_SDIO_HARDWARE_CLKCTRL(CONTROL) \
|
||||
(((CONTROL) == SDIO_HARDWARE_CLKCTRL_DISABLE) || ((CONTROL) == SDIO_HARDWARE_CLKCTRL_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Power_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_POWER_CTRL_OFF ((uint32_t)0x00000000)
|
||||
#define SDIO_POWER_CTRL_ON ((uint32_t)0x00000003)
|
||||
#define IS_SDIO_POWER_CTRL(STATE) (((STATE) == SDIO_POWER_CTRL_OFF) || ((STATE) == SDIO_POWER_CTRL_ON))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Interrupt_sources
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_INT_CCRCERR ((uint32_t)0x00000001)
|
||||
#define SDIO_INT_DCRCERR ((uint32_t)0x00000002)
|
||||
#define SDIO_INT_CMDTIMEOUT ((uint32_t)0x00000004)
|
||||
#define SDIO_INT_DATTIMEOUT ((uint32_t)0x00000008)
|
||||
#define SDIO_INT_TXURERR ((uint32_t)0x00000010)
|
||||
#define SDIO_INT_RXORERR ((uint32_t)0x00000020)
|
||||
#define SDIO_INT_CMDRESPRECV ((uint32_t)0x00000040)
|
||||
#define SDIO_INT_CMDSEND ((uint32_t)0x00000080)
|
||||
#define SDIO_INT_DATEND ((uint32_t)0x00000100)
|
||||
#define SDIO_INT_SBERR ((uint32_t)0x00000200)
|
||||
#define SDIO_INT_DATBLKEND ((uint32_t)0x00000400)
|
||||
#define SDIO_INT_CMDRUN ((uint32_t)0x00000800)
|
||||
#define SDIO_INT_TXRUN ((uint32_t)0x00001000)
|
||||
#define SDIO_INT_RXRUN ((uint32_t)0x00002000)
|
||||
#define SDIO_INT_TFIFOHE ((uint32_t)0x00004000)
|
||||
#define SDIO_INT_RFIFOHF ((uint32_t)0x00008000)
|
||||
#define SDIO_INT_TFIFOF ((uint32_t)0x00010000)
|
||||
#define SDIO_INT_RFIFOF ((uint32_t)0x00020000)
|
||||
#define SDIO_INT_TFIFOE ((uint32_t)0x00040000)
|
||||
#define SDIO_INT_RFIFOE ((uint32_t)0x00080000)
|
||||
#define SDIO_INT_TDATVALID ((uint32_t)0x00100000)
|
||||
#define SDIO_INT_RDATVALID ((uint32_t)0x00200000)
|
||||
#define SDIO_INT_SDIOINT ((uint32_t)0x00400000)
|
||||
#define SDIO_INT_CEATAF ((uint32_t)0x00800000)
|
||||
#define IS_SDIO_INT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Command_Index
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Response_Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_RESP_NO ((uint32_t)0x00000000)
|
||||
#define SDIO_RESP_SHORT ((uint32_t)0x00000040)
|
||||
#define SDIO_RESP_LONG ((uint32_t)0x000000C0)
|
||||
#define IS_SDIO_RESP(RESPONSE) \
|
||||
(((RESPONSE) == SDIO_RESP_NO) || ((RESPONSE) == SDIO_RESP_SHORT) || ((RESPONSE) == SDIO_RESP_LONG))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Wait_Interrupt_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_WAIT_NO ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
|
||||
#define SDIO_WAIT_INT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
|
||||
#define SDIO_WAIT_PEND ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
|
||||
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || ((WAIT) == SDIO_WAIT_INT) || ((WAIT) == SDIO_WAIT_PEND))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_CPSM_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
|
||||
#define SDIO_CPSM_ENABLE ((uint32_t)0x00000400)
|
||||
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_ENABLE) || ((CPSM) == SDIO_CPSM_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Response_Registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_RESPONSE_1 ((uint32_t)0x00000000)
|
||||
#define SDIO_RESPONSE_2 ((uint32_t)0x00000004)
|
||||
#define SDIO_RESPONSE_3 ((uint32_t)0x00000008)
|
||||
#define SDIO_RESPONSE_4 ((uint32_t)0x0000000C)
|
||||
#define IS_SDIO_RESPONSE(RESP) \
|
||||
(((RESP) == SDIO_RESPONSE_1) || ((RESP) == SDIO_RESPONSE_2) || ((RESP) == SDIO_RESPONSE_3) \
|
||||
|| ((RESP) == SDIO_RESPONSE_4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Data_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SDIO_DAT_LEN(LENGTH) ((LENGTH) <= 0x01FFFFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Data_Block_Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_DATBLK_SIZE_1B ((uint32_t)0x00000000)
|
||||
#define SDIO_DATBLK_SIZE_2B ((uint32_t)0x00000010)
|
||||
#define SDIO_DATBLK_SIZE_4B ((uint32_t)0x00000020)
|
||||
#define SDIO_DATBLK_SIZE_8B ((uint32_t)0x00000030)
|
||||
#define SDIO_DATBLK_SIZE_16B ((uint32_t)0x00000040)
|
||||
#define SDIO_DATBLK_SIZE_32B ((uint32_t)0x00000050)
|
||||
#define SDIO_DATBLK_SIZE_64B ((uint32_t)0x00000060)
|
||||
#define SDIO_DATBLK_SIZE_128B ((uint32_t)0x00000070)
|
||||
#define SDIO_DATBLK_SIZE_256B ((uint32_t)0x00000080)
|
||||
#define SDIO_DATBLK_SIZE_512B ((uint32_t)0x00000090)
|
||||
#define SDIO_DATBLK_SIZE_1024B ((uint32_t)0x000000A0)
|
||||
#define SDIO_DATBLK_SIZE_2048B ((uint32_t)0x000000B0)
|
||||
#define SDIO_DATBLK_SIZE_4096B ((uint32_t)0x000000C0)
|
||||
#define SDIO_DATBLK_SIZE_8192B ((uint32_t)0x000000D0)
|
||||
#define SDIO_DATBLK_SIZE_16384B ((uint32_t)0x000000E0)
|
||||
#define IS_SDIO_BLK_SIZE(SIZE) \
|
||||
(((SIZE) == SDIO_DATBLK_SIZE_1B) || ((SIZE) == SDIO_DATBLK_SIZE_2B) || ((SIZE) == SDIO_DATBLK_SIZE_4B) \
|
||||
|| ((SIZE) == SDIO_DATBLK_SIZE_8B) || ((SIZE) == SDIO_DATBLK_SIZE_16B) || ((SIZE) == SDIO_DATBLK_SIZE_32B) \
|
||||
|| ((SIZE) == SDIO_DATBLK_SIZE_64B) || ((SIZE) == SDIO_DATBLK_SIZE_128B) || ((SIZE) == SDIO_DATBLK_SIZE_256B) \
|
||||
|| ((SIZE) == SDIO_DATBLK_SIZE_512B) || ((SIZE) == SDIO_DATBLK_SIZE_1024B) || ((SIZE) == SDIO_DATBLK_SIZE_2048B) \
|
||||
|| ((SIZE) == SDIO_DATBLK_SIZE_4096B) || ((SIZE) == SDIO_DATBLK_SIZE_8192B) \
|
||||
|| ((SIZE) == SDIO_DATBLK_SIZE_16384B))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Transfer_Direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_TRANSDIR_TOCARD ((uint32_t)0x00000000)
|
||||
#define SDIO_TRANSDIR_TOSDIO ((uint32_t)0x00000002)
|
||||
#define IS_SDIO_TRANSFER_DIRECTION(DIR) (((DIR) == SDIO_TRANSDIR_TOCARD) || ((DIR) == SDIO_TRANSDIR_TOSDIO))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Transfer_Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_TRANSMODE_BLOCK ((uint32_t)0x00000000)
|
||||
#define SDIO_TRANSMODE_STREAM ((uint32_t)0x00000004)
|
||||
#define IS_SDIO_TRANS_MODE(MODE) (((MODE) == SDIO_TRANSMODE_STREAM) || ((MODE) == SDIO_TRANSMODE_BLOCK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_DPSM_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
|
||||
#define SDIO_DPSM_ENABLE ((uint32_t)0x00000001)
|
||||
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_ENABLE) || ((DPSM) == SDIO_DPSM_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_FLAG_CCRCERR ((uint32_t)0x00000001)
|
||||
#define SDIO_FLAG_DCRCERR ((uint32_t)0x00000002)
|
||||
#define SDIO_FLAG_CMDTIMEOUT ((uint32_t)0x00000004)
|
||||
#define SDIO_FLAG_DATTIMEOUT ((uint32_t)0x00000008)
|
||||
#define SDIO_FLAG_TXURERR ((uint32_t)0x00000010)
|
||||
#define SDIO_FLAG_RXORERR ((uint32_t)0x00000020)
|
||||
#define SDIO_FLAG_CMDRESPRECV ((uint32_t)0x00000040)
|
||||
#define SDIO_FLAG_CMDSEND ((uint32_t)0x00000080)
|
||||
#define SDIO_FLAG_DATEND ((uint32_t)0x00000100)
|
||||
#define SDIO_FLAG_SBERR ((uint32_t)0x00000200)
|
||||
#define SDIO_FLAG_DATBLKEND ((uint32_t)0x00000400)
|
||||
#define SDIO_FLAG_CMDRUN ((uint32_t)0x00000800)
|
||||
#define SDIO_FLAG_TXRUN ((uint32_t)0x00001000)
|
||||
#define SDIO_FLAG_RXRUN ((uint32_t)0x00002000)
|
||||
#define SDIO_FLAG_TFIFOHE ((uint32_t)0x00004000)
|
||||
#define SDIO_FLAG_RFIFOHF ((uint32_t)0x00008000)
|
||||
#define SDIO_FLAG_TFIFOF ((uint32_t)0x00010000)
|
||||
#define SDIO_FLAG_RFIFOF ((uint32_t)0x00020000)
|
||||
#define SDIO_FLAG_TFIFOE ((uint32_t)0x00040000)
|
||||
#define SDIO_FLAG_RFIFOE ((uint32_t)0x00080000)
|
||||
#define SDIO_FLAG_TDATVALID ((uint32_t)0x00100000)
|
||||
#define SDIO_FLAG_RDATVALID ((uint32_t)0x00200000)
|
||||
#define SDIO_FLAG_SDIOINT ((uint32_t)0x00400000)
|
||||
#define SDIO_FLAG_CEATAF ((uint32_t)0x00800000)
|
||||
#define IS_SDIO_FLAG(FLAG) \
|
||||
(((FLAG) == SDIO_FLAG_CCRCERR) || ((FLAG) == SDIO_FLAG_DCRCERR) || ((FLAG) == SDIO_FLAG_CMDTIMEOUT) \
|
||||
|| ((FLAG) == SDIO_FLAG_DATTIMEOUT) || ((FLAG) == SDIO_FLAG_TXURERR) || ((FLAG) == SDIO_FLAG_RXORERR) \
|
||||
|| ((FLAG) == SDIO_FLAG_CMDRESPRECV) || ((FLAG) == SDIO_FLAG_CMDSEND) || ((FLAG) == SDIO_FLAG_DATEND) \
|
||||
|| ((FLAG) == SDIO_FLAG_SBERR) || ((FLAG) == SDIO_FLAG_DATBLKEND) || ((FLAG) == SDIO_FLAG_CMDRUN) \
|
||||
|| ((FLAG) == SDIO_FLAG_TXRUN) || ((FLAG) == SDIO_FLAG_RXRUN) || ((FLAG) == SDIO_FLAG_TFIFOHE) \
|
||||
|| ((FLAG) == SDIO_FLAG_RFIFOHF) || ((FLAG) == SDIO_FLAG_TFIFOF) || ((FLAG) == SDIO_FLAG_RFIFOF) \
|
||||
|| ((FLAG) == SDIO_FLAG_TFIFOE) || ((FLAG) == SDIO_FLAG_RFIFOE) || ((FLAG) == SDIO_FLAG_TDATVALID) \
|
||||
|| ((FLAG) == SDIO_FLAG_RDATVALID) || ((FLAG) == SDIO_FLAG_SDIOINT) || ((FLAG) == SDIO_FLAG_CEATAF))
|
||||
|
||||
#define IS_SDIO_CLR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
|
||||
|
||||
#define IS_SDIO_GET_INT(IT) \
|
||||
(((IT) == SDIO_INT_CCRCERR) || ((IT) == SDIO_INT_DCRCERR) || ((IT) == SDIO_INT_CMDTIMEOUT) \
|
||||
|| ((IT) == SDIO_INT_DATTIMEOUT) || ((IT) == SDIO_INT_TXURERR) || ((IT) == SDIO_INT_RXORERR) \
|
||||
|| ((IT) == SDIO_INT_CMDRESPRECV) || ((IT) == SDIO_INT_CMDSEND) || ((IT) == SDIO_INT_DATEND) \
|
||||
|| ((IT) == SDIO_INT_SBERR) || ((IT) == SDIO_INT_DATBLKEND) || ((IT) == SDIO_INT_CMDRUN) \
|
||||
|| ((IT) == SDIO_INT_TXRUN) || ((IT) == SDIO_INT_RXRUN) || ((IT) == SDIO_INT_TFIFOHE) \
|
||||
|| ((IT) == SDIO_INT_RFIFOHF) || ((IT) == SDIO_INT_TFIFOF) || ((IT) == SDIO_INT_RFIFOF) \
|
||||
|| ((IT) == SDIO_INT_TFIFOE) || ((IT) == SDIO_INT_RFIFOE) || ((IT) == SDIO_INT_TDATVALID) \
|
||||
|| ((IT) == SDIO_INT_RDATVALID) || ((IT) == SDIO_INT_SDIOINT) || ((IT) == SDIO_INT_CEATAF))
|
||||
|
||||
#define IS_SDIO_CLR_INT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Read_Wait_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_RDWAIT_MODE_CLK ((uint32_t)0x00000001)
|
||||
#define SDIO_RDWAIT_MODE_DAT2 ((uint32_t)0x00000000)
|
||||
#define IS_SDIO_RDWAIT_MODE(MODE) (((MODE) == SDIO_RDWAIT_MODE_CLK) || ((MODE) == SDIO_RDWAIT_MODE_DAT2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void SDIO_DeInit(void);
|
||||
void SDIO_Init(SDIO_InitType* SDIO_InitStruct);
|
||||
void SDIO_InitStruct(SDIO_InitType* SDIO_InitStruct);
|
||||
void SDIO_EnableClock(FunctionalState Cmd);
|
||||
void SDIO_SetPower(uint32_t SDIO_PowerState);
|
||||
uint32_t SDIO_GetPower(void);
|
||||
void SDIO_ConfigInt(uint32_t SDIO_IT, FunctionalState Cmd);
|
||||
void SDIO_EnableCmd(FunctionalState Cmd);
|
||||
void SDIO_SendCmd(SDIO_CmdInitType* SDIO_CmdInitStruct);
|
||||
void SDIO_InitCmdStruct(SDIO_CmdInitType* SDIO_CmdInitStruct);
|
||||
uint8_t SDIO_GetCmdResp(void);
|
||||
uint32_t SDIO_GetResp(uint32_t SDIO_RESP);
|
||||
void SDIO_ConfigData(SDIO_DataInitType* SDIO_DataInitStruct);
|
||||
void SDIO_InitDataStruct(SDIO_DataInitType* SDIO_DataInitStruct);
|
||||
uint32_t SDIO_GetDataCountValue(void);
|
||||
uint32_t SDIO_ReadData(void);
|
||||
void SDIO_WriteData(uint32_t Data);
|
||||
uint32_t SDIO_GetFifoCounter(void);
|
||||
void SDIO_EnableReadWait(FunctionalState Cmd);
|
||||
void SDIO_DisableReadWait(FunctionalState Cmd);
|
||||
void SDIO_EnableSdioReadWaitMode(uint32_t SDIO_ReadWaitMode);
|
||||
void SDIO_EnableSdioOperation(FunctionalState Cmd);
|
||||
void SDIO_EnableSendSdioSuspend(FunctionalState Cmd);
|
||||
void SDIO_EnableCommandCompletion(FunctionalState Cmd);
|
||||
void SDIO_EnableCEATAInt(FunctionalState Cmd);
|
||||
void SDIO_EnableSendCEATA(FunctionalState Cmd);
|
||||
FlagStatus SDIO_GetFlag(uint32_t SDIO_FLAG);
|
||||
void SDIO_ClrFlag(uint32_t SDIO_FLAG);
|
||||
INTStatus SDIO_GetIntStatus(uint32_t SDIO_IT);
|
||||
void SDIO_ClrIntPendingBit(uint32_t SDIO_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __N32G45X_SDIO_H__ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,471 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_spi.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_SPI_H__
|
||||
#define __N32G45X_SPI_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SPI Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t DataDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
|
||||
This parameter can be a value of @ref SPI_data_direction */
|
||||
|
||||
uint16_t SpiMode; /*!< Specifies the SPI operating mode.
|
||||
This parameter can be a value of @ref SPI_mode */
|
||||
|
||||
uint16_t DataLen; /*!< Specifies the SPI data size.
|
||||
This parameter can be a value of @ref SPI_data_size */
|
||||
|
||||
uint16_t CLKPOL; /*!< Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||
|
||||
uint16_t CLKPHA; /*!< Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||
|
||||
uint16_t NSS; /*!< Specifies whether the NSS signal is managed by
|
||||
hardware (NSS pin) or by software using the SSI bit.
|
||||
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||
|
||||
uint16_t BaudRatePres; /*!< Specifies the Baud Rate prescaler value which will be
|
||||
used to configure the transmit and receive SCK clock.
|
||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
|
||||
@note The communication clock is derived from the master
|
||||
clock. The slave clock does not need to be set. */
|
||||
|
||||
uint16_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
||||
|
||||
uint16_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. */
|
||||
} SPI_InitType;
|
||||
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t I2sMode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref I2sMode */
|
||||
|
||||
uint16_t Standard; /*!< Specifies the standard used for the I2S communication.
|
||||
This parameter can be a value of @ref Standard */
|
||||
|
||||
uint16_t DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Data_Format */
|
||||
|
||||
uint16_t MCLKEnable; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||
|
||||
uint32_t AudioFrequency; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||
|
||||
uint16_t CLKPOL; /*!< Specifies the idle state of the I2S clock.
|
||||
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||
} I2S_InitType;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SPI_PERIPH(PERIPH) (((PERIPH) == SPI1) || ((PERIPH) == SPI2) || ((PERIPH) == SPI3))
|
||||
|
||||
#define IS_SPI_2OR3_PERIPH(PERIPH) (((PERIPH) == SPI2) || ((PERIPH) == SPI3))
|
||||
|
||||
/** @addtogroup SPI_data_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_DIR_DOUBLELINE_FULLDUPLEX ((uint16_t)0x0000)
|
||||
#define SPI_DIR_DOUBLELINE_RONLY ((uint16_t)0x0400)
|
||||
#define SPI_DIR_SINGLELINE_RX ((uint16_t)0x8000)
|
||||
#define SPI_DIR_SINGLELINE_TX ((uint16_t)0xC000)
|
||||
#define IS_SPI_DIR_MODE(MODE) \
|
||||
(((MODE) == SPI_DIR_DOUBLELINE_FULLDUPLEX) || ((MODE) == SPI_DIR_DOUBLELINE_RONLY) \
|
||||
|| ((MODE) == SPI_DIR_SINGLELINE_RX) || ((MODE) == SPI_DIR_SINGLELINE_TX))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_MODE_MASTER ((uint16_t)0x0104)
|
||||
#define SPI_MODE_SLAVE ((uint16_t)0x0000)
|
||||
#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_MASTER) || ((MODE) == SPI_MODE_SLAVE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_DATA_SIZE_16BITS ((uint16_t)0x0800)
|
||||
#define SPI_DATA_SIZE_8BITS ((uint16_t)0x0000)
|
||||
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATA_SIZE_16BITS) || ((DATASIZE) == SPI_DATA_SIZE_8BITS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CLKPOL_LOW ((uint16_t)0x0000)
|
||||
#define SPI_CLKPOL_HIGH ((uint16_t)0x0002)
|
||||
#define IS_SPI_CLKPOL(CPOL) (((CPOL) == SPI_CLKPOL_LOW) || ((CPOL) == SPI_CLKPOL_HIGH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CLKPHA_FIRST_EDGE ((uint16_t)0x0000)
|
||||
#define SPI_CLKPHA_SECOND_EDGE ((uint16_t)0x0001)
|
||||
#define IS_SPI_CLKPHA(CPHA) (((CPHA) == SPI_CLKPHA_FIRST_EDGE) || ((CPHA) == SPI_CLKPHA_SECOND_EDGE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Slave_Select_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSS_SOFT ((uint16_t)0x0200)
|
||||
#define SPI_NSS_HARD ((uint16_t)0x0000)
|
||||
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || ((NSS) == SPI_NSS_HARD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_BaudRate_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_BR_PRESCALER_2 ((uint16_t)0x0000)
|
||||
#define SPI_BR_PRESCALER_4 ((uint16_t)0x0008)
|
||||
#define SPI_BR_PRESCALER_8 ((uint16_t)0x0010)
|
||||
#define SPI_BR_PRESCALER_16 ((uint16_t)0x0018)
|
||||
#define SPI_BR_PRESCALER_32 ((uint16_t)0x0020)
|
||||
#define SPI_BR_PRESCALER_64 ((uint16_t)0x0028)
|
||||
#define SPI_BR_PRESCALER_128 ((uint16_t)0x0030)
|
||||
#define SPI_BR_PRESCALER_256 ((uint16_t)0x0038)
|
||||
#define IS_SPI_BR_PRESCALER(PRESCALER) \
|
||||
(((PRESCALER) == SPI_BR_PRESCALER_2) || ((PRESCALER) == SPI_BR_PRESCALER_4) || ((PRESCALER) == SPI_BR_PRESCALER_8) \
|
||||
|| ((PRESCALER) == SPI_BR_PRESCALER_16) || ((PRESCALER) == SPI_BR_PRESCALER_32) \
|
||||
|| ((PRESCALER) == SPI_BR_PRESCALER_64) || ((PRESCALER) == SPI_BR_PRESCALER_128) \
|
||||
|| ((PRESCALER) == SPI_BR_PRESCALER_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_MSB_LSB_transmission
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_FB_MSB ((uint16_t)0x0000)
|
||||
#define SPI_FB_LSB ((uint16_t)0x0080)
|
||||
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FB_MSB) || ((BIT) == SPI_FB_LSB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2sMode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_MODE_SlAVE_TX ((uint16_t)0x0000)
|
||||
#define I2S_MODE_SlAVE_RX ((uint16_t)0x0100)
|
||||
#define I2S_MODE_MASTER_TX ((uint16_t)0x0200)
|
||||
#define I2S_MODE_MASTER_RX ((uint16_t)0x0300)
|
||||
#define IS_I2S_MODE(MODE) \
|
||||
(((MODE) == I2S_MODE_SlAVE_TX) || ((MODE) == I2S_MODE_SlAVE_RX) || ((MODE) == I2S_MODE_MASTER_TX) \
|
||||
|| ((MODE) == I2S_MODE_MASTER_RX))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Standard
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_STD_PHILLIPS ((uint16_t)0x0000)
|
||||
#define I2S_STD_MSB_ALIGN ((uint16_t)0x0010)
|
||||
#define I2S_STD_LSB_ALIGN ((uint16_t)0x0020)
|
||||
#define I2S_STD_PCM_SHORTFRAME ((uint16_t)0x0030)
|
||||
#define I2S_STD_PCM_LONGFRAME ((uint16_t)0x00B0)
|
||||
#define IS_I2S_STANDARD(STANDARD) \
|
||||
(((STANDARD) == I2S_STD_PHILLIPS) || ((STANDARD) == I2S_STD_MSB_ALIGN) || ((STANDARD) == I2S_STD_LSB_ALIGN) \
|
||||
|| ((STANDARD) == I2S_STD_PCM_SHORTFRAME) || ((STANDARD) == I2S_STD_PCM_LONGFRAME))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Data_Format
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_DATA_FMT_16BITS ((uint16_t)0x0000)
|
||||
#define I2S_DATA_FMT_16BITS_EXTENDED ((uint16_t)0x0001)
|
||||
#define I2S_DATA_FMT_24BITS ((uint16_t)0x0003)
|
||||
#define I2S_DATA_FMT_32BITS ((uint16_t)0x0005)
|
||||
#define IS_I2S_DATA_FMT(FORMAT) \
|
||||
(((FORMAT) == I2S_DATA_FMT_16BITS) || ((FORMAT) == I2S_DATA_FMT_16BITS_EXTENDED) \
|
||||
|| ((FORMAT) == I2S_DATA_FMT_24BITS) || ((FORMAT) == I2S_DATA_FMT_32BITS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_MCLK_Output
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_MCLK_ENABLE ((uint16_t)0x0200)
|
||||
#define I2S_MCLK_DISABLE ((uint16_t)0x0000)
|
||||
#define IS_I2S_MCLK_ENABLE(OUTPUT) (((OUTPUT) == I2S_MCLK_ENABLE) || ((OUTPUT) == I2S_MCLK_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Audio_Frequency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_AUDIO_FREQ_192K ((uint32_t)192000)
|
||||
#define I2S_AUDIO_FREQ_96K ((uint32_t)96000)
|
||||
#define I2S_AUDIO_FREQ_48K ((uint32_t)48000)
|
||||
#define I2S_AUDIO_FREQ_44K ((uint32_t)44100)
|
||||
#define I2S_AUDIO_FREQ_32K ((uint32_t)32000)
|
||||
#define I2S_AUDIO_FREQ_22K ((uint32_t)22050)
|
||||
#define I2S_AUDIO_FREQ_16K ((uint32_t)16000)
|
||||
#define I2S_AUDIO_FREQ_11K ((uint32_t)11025)
|
||||
#define I2S_AUDIO_FREQ_8K ((uint32_t)8000)
|
||||
#define I2S_AUDIO_FREQ_DEFAULT ((uint32_t)2)
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(FREQ) \
|
||||
((((FREQ) >= I2S_AUDIO_FREQ_8K) && ((FREQ) <= I2S_AUDIO_FREQ_192K)) || ((FREQ) == I2S_AUDIO_FREQ_DEFAULT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2S_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_CLKPOL_LOW ((uint16_t)0x0000)
|
||||
#define I2S_CLKPOL_HIGH ((uint16_t)0x0008)
|
||||
#define IS_I2S_CLKPOL(CPOL) (((CPOL) == I2S_CLKPOL_LOW) || ((CPOL) == I2S_CLKPOL_HIGH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_I2S_DMA_transfer_requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_DMA_TX ((uint16_t)0x0002)
|
||||
#define SPI_I2S_DMA_RX ((uint16_t)0x0001)
|
||||
#define IS_SPI_I2S_DMA(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_NSS_internal_software_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSS_HIGH ((uint16_t)0x0100)
|
||||
#define SPI_NSS_LOW ((uint16_t)0xFEFF)
|
||||
#define IS_SPI_NSS_LEVEL(INTERNAL) (((INTERNAL) == SPI_NSS_HIGH) || ((INTERNAL) == SPI_NSS_LOW))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_CRC_Transmit_Receive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CRC_TX ((uint8_t)0x00)
|
||||
#define SPI_CRC_RX ((uint8_t)0x01)
|
||||
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_TX) || ((CRC) == SPI_CRC_RX))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_direction_transmit_receive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_BIDIRECTION_RX ((uint16_t)0xBFFF)
|
||||
#define SPI_BIDIRECTION_TX ((uint16_t)0x4000)
|
||||
#define IS_SPI_BIDIRECTION(DIRECTION) (((DIRECTION) == SPI_BIDIRECTION_RX) || ((DIRECTION) == SPI_BIDIRECTION_TX))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_I2S_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_INT_TE ((uint8_t)0x71)
|
||||
#define SPI_I2S_INT_RNE ((uint8_t)0x60)
|
||||
#define SPI_I2S_INT_ERR ((uint8_t)0x50)
|
||||
#define IS_SPI_I2S_CONFIG_INT(IT) (((IT) == SPI_I2S_INT_TE) || ((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_ERR))
|
||||
#define SPI_I2S_INT_OVER ((uint8_t)0x56)
|
||||
#define SPI_INT_MODERR ((uint8_t)0x55)
|
||||
#define SPI_INT_CRCERR ((uint8_t)0x54)
|
||||
#define I2S_INT_UNDER ((uint8_t)0x53)
|
||||
#define IS_SPI_I2S_CLR_INT(IT) (((IT) == SPI_INT_CRCERR))
|
||||
#define IS_SPI_I2S_GET_INT(IT) \
|
||||
(((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_TE) || ((IT) == I2S_INT_UNDER) || ((IT) == SPI_INT_CRCERR) \
|
||||
|| ((IT) == SPI_INT_MODERR) || ((IT) == SPI_I2S_INT_OVER))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_I2S_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_RNE_FLAG ((uint16_t)0x0001)
|
||||
#define SPI_I2S_TE_FLAG ((uint16_t)0x0002)
|
||||
#define I2S_CHSIDE_FLAG ((uint16_t)0x0004)
|
||||
#define I2S_UNDER_FLAG ((uint16_t)0x0008)
|
||||
#define SPI_CRCERR_FLAG ((uint16_t)0x0010)
|
||||
#define SPI_MODERR_FLAG ((uint16_t)0x0020)
|
||||
#define SPI_I2S_OVER_FLAG ((uint16_t)0x0040)
|
||||
#define SPI_I2S_BUSY_FLAG ((uint16_t)0x0080)
|
||||
#define IS_SPI_I2S_CLR_FLAG(FLAG) (((FLAG) == SPI_CRCERR_FLAG))
|
||||
#define IS_SPI_I2S_GET_FLAG(FLAG) \
|
||||
(((FLAG) == SPI_I2S_BUSY_FLAG) || ((FLAG) == SPI_I2S_OVER_FLAG) || ((FLAG) == SPI_MODERR_FLAG) \
|
||||
|| ((FLAG) == SPI_CRCERR_FLAG) || ((FLAG) == I2S_UNDER_FLAG) || ((FLAG) == I2S_CHSIDE_FLAG) \
|
||||
|| ((FLAG) == SPI_I2S_TE_FLAG) || ((FLAG) == SPI_I2S_RNE_FLAG))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_CRC_polynomial
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void SPI_I2S_DeInit(SPI_Module* SPIx);
|
||||
void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct);
|
||||
void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct);
|
||||
void SPI_InitStruct(SPI_InitType* SPI_InitStruct);
|
||||
void I2S_InitStruct(I2S_InitType* I2S_InitStruct);
|
||||
void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd);
|
||||
void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd);
|
||||
void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd);
|
||||
void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd);
|
||||
void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data);
|
||||
uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx);
|
||||
void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft);
|
||||
void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd);
|
||||
void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen);
|
||||
void SPI_TransmitCrcNext(SPI_Module* SPIx);
|
||||
void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd);
|
||||
uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC);
|
||||
uint16_t SPI_GetCRCPoly(SPI_Module* SPIx);
|
||||
void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection);
|
||||
FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG);
|
||||
void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG);
|
||||
INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT);
|
||||
void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__N32G45X_SPI_H__ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,253 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_tsc.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_TSC_H__
|
||||
#define __N32G45X_TSC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TSC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief detection period
|
||||
*/
|
||||
#define TSC_DET_PERIOD_MASK (0x0F) // period bit mask
|
||||
#define TSC_DET_PERIOD_OFFSET (0x00) // period offset
|
||||
#define TSC_DET_PERIOD_8_32KHZ (0x00) // 8 x 32KHz =244.1us
|
||||
#define TSC_DET_PERIOD_16_32KHZ (0x01) // 16 x 32KHz =488.28us
|
||||
#define TSC_DET_PERIOD_24_32KHZ (0x02) // 24 x 32KHz =732.42us
|
||||
#define TSC_DET_PERIOD_32_32KHZ (0x03) // 32 x 32KHz =976.56us(default)
|
||||
#define TSC_DET_PERIOD_40_32KHZ (0x04) // 40 x 32KHz =1220.7us
|
||||
#define TSC_DET_PERIOD_48_32KHZ (0x05) // 48 x 32KHz =1464.84us
|
||||
#define TSC_DET_PERIOD_56_32KHZ (0x06) // 56 x 32KHz =1708.98us
|
||||
#define TSC_DET_PERIOD_64_32KHZ (0x07) // 64 x 32KHz =1953.13us
|
||||
#define TSC_DET_PERIOD_72_32KHZ (0x08) // 72 x 32KHz =2197.27us
|
||||
#define TSC_DET_PERIOD_80_32KHZ (0x09) // 80 x 32KHz =2441.41us
|
||||
#define TSC_DET_PERIOD_88_32KHZ (0x0A) // 88 x 32KHz =2685.55us
|
||||
#define TSC_DET_PERIOD_96_32KHZ (0x0B) // 96 x 32KHz =2929.69us
|
||||
#define TSC_DET_PERIOD_104_32KHZ (0x0C) // 104 x 32KHz =3173.83us
|
||||
|
||||
// filter number
|
||||
#define TSC_HW_DET_BITS_MASK (0x03) // filter width bit mask
|
||||
#define TSC_HW_DET_OFFSET (0x04) // filter offset
|
||||
#define TSC_HW_DET_FILTER_1 (0x00) // interrupt over 1 time valid detect
|
||||
#define TSC_HW_DET_FILTER_2 (0x10) // interrupt over 2 times valid detect
|
||||
#define TSC_HW_DET_FILTER_3 (0x20) // interrupt over 3 times valid detect
|
||||
#define TSC_HW_DET_FILTER_4 (0x30) // interrupt over 4 times valid detect
|
||||
|
||||
// comparator speed configuration
|
||||
#define TSC_CMP_MASK (0x03) // comparator offset bit mask
|
||||
#define TSC_CMP_OFFSET (0x04) // offset of comparator speed configuration
|
||||
#define TSC_CMP_SPEED_0 (0x00) // 100KHZ~200KHZ
|
||||
#define TSC_CMP_SPEED_1 (0x10) // 300KHZ~700KHZ
|
||||
#define TSC_CMP_SPEED_2 (0x20) // 300KHZ~700KHZ
|
||||
#define TSC_CMP_SPEED_3 (0x30) // 300KHZ~700KHZ
|
||||
|
||||
// resistance selection
|
||||
#define TSC_RESIST_SEL_MASK (0x01) // resistance selection bit mask
|
||||
#define TSC_RESIST_SEL_OFFSET (0x06) // resistance selection offset
|
||||
#define TSC_INNER_RESIST (0x00) // internal resistance
|
||||
#define TSC_EXT_RESIST (0x04) // external resistance
|
||||
|
||||
// resistance value configuration
|
||||
#define TSC_RESIST_1M (0x00) // 1M
|
||||
#define TSC_RESIST_875K (0x01) // 875K
|
||||
#define TSC_RESIST_750K (0x02) // 750K
|
||||
#define TSC_RESIST_625K (0x03) // 625K
|
||||
#define TSC_RESIST_500K (0x04) // 500K
|
||||
#define TSC_RESIST_375K (0x05) // 375K
|
||||
#define TSC_RESIST_250K (0x06) // 250K
|
||||
#define TSC_RESIST_125K (0x07) // 125K
|
||||
|
||||
// hardware detection mode
|
||||
#define TSC_HW_DET_ENABLE (0x40)
|
||||
#define TSC_HW_CHN_MASK (0xFFFFFF)
|
||||
|
||||
// hardware detection status
|
||||
#define TSC_HW_DET_ST (0x80)
|
||||
|
||||
// Enable detection below threshold(BASE-DELTA)
|
||||
#define TSC_HW_LESS_DET_SEL (0x100)
|
||||
|
||||
// Enable detection above threshold(BASE+DELTA)
|
||||
#define TSC_HW_GREAT_DET_SEL (0x200)
|
||||
#define TSC_HW_BASE_BITS_OFFSET (0)
|
||||
#define TSC_HW_BASE_BITS_WIDTH (0x7FF)
|
||||
|
||||
#define TSC_HW_DELTA_BITS_OFFSET (16)
|
||||
#define TSC_HW_DELTA_BITS_WIDTH (0xFF)
|
||||
|
||||
// enable detection interrupt
|
||||
#define TSC_HW_DET_INTEN (0x400)
|
||||
|
||||
// tsc soft channel bit width
|
||||
#define TSC_SW_CHN_VAILD_WIDTH (0x1F)
|
||||
|
||||
// TSC channel addr width(4bytes)
|
||||
#define TSC_CHN_ADDR_WIDTH (4)
|
||||
|
||||
// TSC RESIS bit width
|
||||
#define TSC_RES_BIT_VALID_BITS (0x07)
|
||||
#define TSC_RES_BIT_OFFSET_WIDTH (4)
|
||||
|
||||
// ad_tsc_out mux to timer4 etr port
|
||||
#define TSC_SW_TIM_WIDTH (0x3)
|
||||
#define TSC_SW_TIM_OFFSET (12)
|
||||
#define TSC_SW_TM4_ETR_SEL (0x1000)
|
||||
|
||||
// ad_tsc_out mux to timer2 etr port
|
||||
#define TSC_SW_TM2_ETR_SEL (0x2000)
|
||||
|
||||
// Enable software mode
|
||||
#define TSC_SW_CHN_ENABLE (0x20)
|
||||
|
||||
// TSC status of hardware detection
|
||||
#define TSC_HW_CNT_VAL_OFFSET (0)
|
||||
#define TSC_HW_CNT_VAL_BITS_MASK (0x7FF)
|
||||
#define TSC_HW_LESS_DET_FLAG_OFFSET (12)
|
||||
#define TSC_HW_LESS_DET_FLAG_MASK (0x01)
|
||||
#define TSC_HW_GREAT_DET_FLAG_OFFSET (13)
|
||||
#define TSC_HW_GREAT_DET_FLAG_MASK (0x01)
|
||||
#define TSC_HW_CHN_NUM_OFFSET (16)
|
||||
#define TSC_HW_CHN_NUM_FLAG_MASK (0x1F)
|
||||
|
||||
// TSC maximum channels of hardware detection
|
||||
#define TSC_DET_MAX_CHN_COUNT (24)
|
||||
|
||||
/**
|
||||
* @brief define tsc channel num
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TSC_CHN0 = 0x00000001, ///< tsc channel 0
|
||||
TSC_CHN1 = 0x00000002, ///< tsc channel 1
|
||||
TSC_CHN2 = 0x00000004, ///< tsc channel 2
|
||||
TSC_CHN3 = 0x00000008, ///< tsc channel 3
|
||||
TSC_CHN4 = 0x00000010, ///< tsc channel 4
|
||||
TSC_CHN5 = 0x00000020, ///< tsc channel 5
|
||||
TSC_CHN6 = 0x00000040, ///< tsc channel 6
|
||||
TSC_CHN7 = 0x00000080, ///< tsc channel 7
|
||||
TSC_CHN8 = 0x00000100, ///< tsc channel 8
|
||||
TSC_CHN9 = 0x00000200, ///< tsc channel 9
|
||||
TSC_CHN10 = 0x00000400, ///< tsc channel 10
|
||||
TSC_CHN11 = 0x00000800, ///< tsc channel 11
|
||||
TSC_CHN12 = 0x00001000, ///< tsc channel 12
|
||||
TSC_CHN13 = 0x00002000, ///< tsc channel 13
|
||||
TSC_CHN14 = 0x00004000, ///< tsc channel 14
|
||||
TSC_CHN15 = 0x00008000, ///< tsc channel 15
|
||||
TSC_CHN16 = 0x00010000, ///< tsc channel 16
|
||||
TSC_CHN17 = 0x00020000, ///< tsc channel 17
|
||||
TSC_CHN18 = 0x00040000, ///< tsc channel 18
|
||||
TSC_CHN19 = 0x00080000, ///< tsc channel 19
|
||||
TSC_CHN20 = 0x00100000, ///< tsc channel 20
|
||||
TSC_CHN21 = 0x00200000, ///< tsc channel 21
|
||||
TSC_CHN22 = 0x00400000, ///< tsc channel 22
|
||||
TSC_CHN23 = 0x00800000 ///< tsc channel 23
|
||||
} TSC_Channel;
|
||||
|
||||
/**
|
||||
* @brief define tsc status type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TSC_STS_CNTVALUE = 0, ///< tsc count of hardware detect
|
||||
TSC_STS_LESS_DET = 1, ///< tsc less flag of hardware detect
|
||||
TSC_STS_GREAT_DET = 2, ///< tsc great flag of hardware detect
|
||||
TSC_STS_CHN_NUM = 3, ///< tsc chn number of hardware detect
|
||||
TSC_DET_DET_ST = 4, ///< tsc hw detect mode start status
|
||||
} TSC_Status;
|
||||
|
||||
/**
|
||||
* @brief TSC Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t TSC_DetIntEnable; // Enable interrupt by hardware detection or not
|
||||
uint8_t TSC_GreatEnable; // Enable detection above threshold.Interrupt if the pulse count is great than base+delta.
|
||||
uint8_t TSC_LessEnable; // Enable detection below threshold.Interrupt if the pulse count is less than base-delta.
|
||||
uint8_t TSC_FilterCount; // filter count of detection
|
||||
uint8_t TSC_DetPeriod; // detection period
|
||||
} TSC_InitType;
|
||||
|
||||
/**
|
||||
* @brief Channels setting of hardware detection
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t TSC_Base; // base value
|
||||
uint8_t TSC_Delta; // offset value
|
||||
uint8_t TSC_ResisValue; // resistance value configuration
|
||||
} TSC_ChnCfg;
|
||||
|
||||
/**
|
||||
* @brief Analog parameter configuration
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t TSC_AnaoptrSpeedOption; // speed option
|
||||
uint8_t TSC_AnaoptrResisOption; // internal or external resistance option select
|
||||
} TSC_AnaoCfg;
|
||||
|
||||
void TSC_Init(TSC_Module* TSC_Def, TSC_InitType* CtrlCfg);
|
||||
void TSC_SetChannelCfg(TSC_Module* TSC_Def, TSC_ChnCfg* ChnCfg, uint32_t Channels);
|
||||
void TSC_GetChannelCfg(TSC_Module* TSC_Def, TSC_ChnCfg* ChnCfg, uint32_t Channel);
|
||||
void TSC_SetAnaoCfg(TSC_Module* TSC_Def, TSC_AnaoCfg* AnaoCfg);
|
||||
void TSC_SW_SwtichChn(TSC_Module* TSC_Def, uint32_t Channel, TIM_Module* TIMx, FunctionalState Cmd);
|
||||
void TSC_Cmd(TSC_Module* TSC_Def, uint32_t Channels, FunctionalState Cmd);
|
||||
uint32_t TSC_GetStatus(TSC_Module* TSC_Def, TSC_Status type);
|
||||
void TSC_SW_SwtichChn_Skip(uint32_t Channel);
|
||||
void TSC_SW_Init_Skip(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __N32G45X_TSC_H__ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,400 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_usart.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_USART_H__
|
||||
#define __N32G45X_USART_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief USART Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the USART communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->BaudRate)))
|
||||
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
|
||||
|
||||
uint16_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref USART_Word_Length */
|
||||
|
||||
uint16_t StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref USART_Stop_Bits */
|
||||
|
||||
uint16_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref Mode */
|
||||
|
||||
uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
|
||||
or disabled.
|
||||
This parameter can be a value of @ref USART_Hardware_Flow_Control */
|
||||
} USART_InitType;
|
||||
|
||||
/**
|
||||
* @brief USART Clock Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t Clock; /*!< Specifies whether the USART clock is enabled or disabled.
|
||||
This parameter can be a value of @ref Clock */
|
||||
|
||||
uint16_t Polarity; /*!< Specifies the steady state value of the serial clock.
|
||||
This parameter can be a value of @ref USART_Clock_Polarity */
|
||||
|
||||
uint16_t Phase; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref USART_Clock_Phase */
|
||||
|
||||
uint16_t LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref USART_Last_Bit */
|
||||
} USART_ClockInitType;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_USART_ALL_PERIPH(PERIPH) \
|
||||
(((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4) \
|
||||
|| ((PERIPH) == UART5) || ((PERIPH) == UART6) || ((PERIPH) == UART7))
|
||||
|
||||
#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3))
|
||||
|
||||
#define IS_USART_1234_PERIPH(PERIPH) \
|
||||
(((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4))
|
||||
/** @addtogroup USART_Word_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WL_8B ((uint16_t)0x0000)
|
||||
#define USART_WL_9B ((uint16_t)0x1000)
|
||||
|
||||
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WL_8B) || ((LENGTH) == USART_WL_9B))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Stop_Bits
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_STPB_1 ((uint16_t)0x0000)
|
||||
#define USART_STPB_0_5 ((uint16_t)0x1000)
|
||||
#define USART_STPB_2 ((uint16_t)0x2000)
|
||||
#define USART_STPB_1_5 ((uint16_t)0x3000)
|
||||
#define IS_USART_STOPBITS(STOPBITS) \
|
||||
(((STOPBITS) == USART_STPB_1) || ((STOPBITS) == USART_STPB_0_5) || ((STOPBITS) == USART_STPB_2) \
|
||||
|| ((STOPBITS) == USART_STPB_1_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Parity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_PE_NO ((uint16_t)0x0000)
|
||||
#define USART_PE_EVEN ((uint16_t)0x0400)
|
||||
#define USART_PE_ODD ((uint16_t)0x0600)
|
||||
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PE_NO) || ((PARITY) == USART_PE_EVEN) || ((PARITY) == USART_PE_ODD))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_MODE_RX ((uint16_t)0x0004)
|
||||
#define USART_MODE_TX ((uint16_t)0x0008)
|
||||
#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Hardware_Flow_Control
|
||||
* @{
|
||||
*/
|
||||
#define USART_HFCTRL_NONE ((uint16_t)0x0000)
|
||||
#define USART_HFCTRL_RTS ((uint16_t)0x0100)
|
||||
#define USART_HFCTRL_CTS ((uint16_t)0x0200)
|
||||
#define USART_HFCTRL_RTS_CTS ((uint16_t)0x0300)
|
||||
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL) \
|
||||
(((CONTROL) == USART_HFCTRL_NONE) || ((CONTROL) == USART_HFCTRL_RTS) || ((CONTROL) == USART_HFCTRL_CTS) \
|
||||
|| ((CONTROL) == USART_HFCTRL_RTS_CTS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Clock
|
||||
* @{
|
||||
*/
|
||||
#define USART_CLK_DISABLE ((uint16_t)0x0000)
|
||||
#define USART_CLK_ENABLE ((uint16_t)0x0800)
|
||||
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLK_DISABLE) || ((CLOCK) == USART_CLK_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CLKPOL_LOW ((uint16_t)0x0000)
|
||||
#define USART_CLKPOL_HIGH ((uint16_t)0x0400)
|
||||
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CLKPOL_LOW) || ((CPOL) == USART_CLKPOL_HIGH))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CLKPHA_1EDGE ((uint16_t)0x0000)
|
||||
#define USART_CLKPHA_2EDGE ((uint16_t)0x0200)
|
||||
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CLKPHA_1EDGE) || ((CPHA) == USART_CLKPHA_2EDGE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Last_Bit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CLKLB_DISABLE ((uint16_t)0x0000)
|
||||
#define USART_CLKLB_ENABLE ((uint16_t)0x0100)
|
||||
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_CLKLB_DISABLE) || ((LASTBIT) == USART_CLKLB_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Interrupt_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_INT_PEF ((uint16_t)0x0028)
|
||||
#define USART_INT_TXDE ((uint16_t)0x0727)
|
||||
#define USART_INT_TXC ((uint16_t)0x0626)
|
||||
#define USART_INT_RXDNE ((uint16_t)0x0525)
|
||||
#define USART_INT_IDLEF ((uint16_t)0x0424)
|
||||
#define USART_INT_LINBD ((uint16_t)0x0846)
|
||||
#define USART_INT_CTSF ((uint16_t)0x096A)
|
||||
#define USART_INT_ERRF ((uint16_t)0x0060)
|
||||
#define USART_INT_OREF ((uint16_t)0x0360)
|
||||
#define USART_INT_NEF ((uint16_t)0x0260)
|
||||
#define USART_INT_FEF ((uint16_t)0x0160)
|
||||
#define IS_USART_CFG_INT(IT) \
|
||||
(((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \
|
||||
|| ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) \
|
||||
|| ((IT) == USART_INT_ERRF))
|
||||
#define IS_USART_GET_INT(IT) \
|
||||
(((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \
|
||||
|| ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) || ((IT) == USART_INT_OREF) \
|
||||
|| ((IT) == USART_INT_NEF) || ((IT) == USART_INT_FEF))
|
||||
#define IS_USART_CLR_INT(IT) \
|
||||
(((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_DMA_Requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_DMAREQ_TX ((uint16_t)0x0080)
|
||||
#define USART_DMAREQ_RX ((uint16_t)0x0040)
|
||||
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_WakeUp_methods
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WUM_IDLELINE ((uint16_t)0x0000)
|
||||
#define USART_WUM_ADDRMASK ((uint16_t)0x0800)
|
||||
#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WUM_IDLELINE) || ((WAKEUP) == USART_WUM_ADDRMASK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_LIN_Break_Detection_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LINBDL_10B ((uint16_t)0x0000)
|
||||
#define USART_LINBDL_11B ((uint16_t)0x0020)
|
||||
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == USART_LINBDL_10B) || ((LENGTH) == USART_LINBDL_11B))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_IrDA_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IRDAMODE_LOWPPWER ((uint16_t)0x0004)
|
||||
#define USART_IRDAMODE_NORMAL ((uint16_t)0x0000)
|
||||
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IRDAMODE_LOWPPWER) || ((MODE) == USART_IRDAMODE_NORMAL))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_FLAG_CTSF ((uint16_t)0x0200)
|
||||
#define USART_FLAG_LINBD ((uint16_t)0x0100)
|
||||
#define USART_FLAG_TXDE ((uint16_t)0x0080)
|
||||
#define USART_FLAG_TXC ((uint16_t)0x0040)
|
||||
#define USART_FLAG_RXDNE ((uint16_t)0x0020)
|
||||
#define USART_FLAG_IDLEF ((uint16_t)0x0010)
|
||||
#define USART_FLAG_OREF ((uint16_t)0x0008)
|
||||
#define USART_FLAG_NEF ((uint16_t)0x0004)
|
||||
#define USART_FLAG_FEF ((uint16_t)0x0002)
|
||||
#define USART_FLAG_PEF ((uint16_t)0x0001)
|
||||
#define IS_USART_FLAG(FLAG) \
|
||||
(((FLAG) == USART_FLAG_PEF) || ((FLAG) == USART_FLAG_TXDE) || ((FLAG) == USART_FLAG_TXC) \
|
||||
|| ((FLAG) == USART_FLAG_RXDNE) || ((FLAG) == USART_FLAG_IDLEF) || ((FLAG) == USART_FLAG_LINBD) \
|
||||
|| ((FLAG) == USART_FLAG_CTSF) || ((FLAG) == USART_FLAG_OREF) || ((FLAG) == USART_FLAG_NEF) \
|
||||
|| ((FLAG) == USART_FLAG_FEF))
|
||||
|
||||
#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
|
||||
#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) \
|
||||
((((*(uint32_t*)&(PERIPH)) != UART4_BASE) && ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
|
||||
|| ((USART_FLAG) != USART_FLAG_CTSF))
|
||||
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
|
||||
#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
|
||||
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void USART_DeInit(USART_Module* USARTx);
|
||||
void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct);
|
||||
void USART_StructInit(USART_InitType* USART_InitStruct);
|
||||
void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct);
|
||||
void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct);
|
||||
void USART_Enable(USART_Module* USARTx, FunctionalState Cmd);
|
||||
void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd);
|
||||
void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd);
|
||||
void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr);
|
||||
void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode);
|
||||
void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd);
|
||||
void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength);
|
||||
void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd);
|
||||
void USART_SendData(USART_Module* USARTx, uint16_t Data);
|
||||
uint16_t USART_ReceiveData(USART_Module* USARTx);
|
||||
void USART_SendBreak(USART_Module* USARTx);
|
||||
void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime);
|
||||
void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler);
|
||||
void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd);
|
||||
void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd);
|
||||
void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd);
|
||||
void USART_ConfigOverSampling8(USART_Module* USARTx, FunctionalState Cmd);
|
||||
void USART_ConfigOneBitMethod(USART_Module* USARTx, FunctionalState Cmd);
|
||||
void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode);
|
||||
void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd);
|
||||
FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG);
|
||||
void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG);
|
||||
INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT);
|
||||
void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __N32G45X_USART_H__ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_wwdg.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_WWDG_H__
|
||||
#define __N32G45X_WWDG_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define WWDG_PRESCALER_DIV1 ((uint32_t)0x00000000)
|
||||
#define WWDG_PRESCALER_DIV2 ((uint32_t)0x00000080)
|
||||
#define WWDG_PRESCALER_DIV4 ((uint32_t)0x00000100)
|
||||
#define WWDG_PRESCALER_DIV8 ((uint32_t)0x00000180)
|
||||
#define IS_WWDG_PRESCALER_DIV(PRESCALER) \
|
||||
(((PRESCALER) == WWDG_PRESCALER_DIV1) || ((PRESCALER) == WWDG_PRESCALER_DIV2) \
|
||||
|| ((PRESCALER) == WWDG_PRESCALER_DIV4) || ((PRESCALER) == WWDG_PRESCALER_DIV8))
|
||||
#define IS_WWDG_WVALUE(VALUE) ((VALUE) <= 0x7F)
|
||||
#define IS_WWDG_CNT(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void WWDG_DeInit(void);
|
||||
void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler);
|
||||
void WWDG_SetWValue(uint8_t WindowValue);
|
||||
void WWDG_EnableInt(void);
|
||||
void WWDG_SetCnt(uint8_t Counter);
|
||||
void WWDG_Enable(uint8_t Counter);
|
||||
FlagStatus WWDG_GetEWINTF(void);
|
||||
void WWDG_ClrEWINTF(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __N32G45X__WWDG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,683 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_xfmc.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __N32G45X_XFMC_H__
|
||||
#define __N32G45X_XFMC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Timing parameters For NOR/SRAM Banks
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AddrSetTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address setup time.
|
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note: It is not used with synchronous NOR Flash memories. */
|
||||
|
||||
uint32_t AddrHoldTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address hold time.
|
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note: It is not used with synchronous NOR Flash memories.*/
|
||||
|
||||
uint32_t
|
||||
DataSetTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the data setup time.
|
||||
This parameter can be a value between 0 and 0xFF.
|
||||
@note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
|
||||
|
||||
uint32_t BusRecoveryCycle; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the bus turnaround.
|
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note: It is only used for multiplexed NOR Flash memories. */
|
||||
|
||||
uint32_t
|
||||
ClkDiv; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
|
||||
This parameter can be a value between 1 and 0xF.
|
||||
@note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
|
||||
|
||||
uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
|
||||
to the memory before getting the first data.
|
||||
The value of this parameter depends on the memory type as shown below:
|
||||
- It must be set to 0 in case of a CRAM
|
||||
- It is don't care in asynchronous NOR, SRAM or ROM accesses
|
||||
- It may assume a value between 0 and 0xF in NOR Flash memories
|
||||
with synchronous burst mode enable */
|
||||
|
||||
uint32_t AccMode; /*!< Specifies the asynchronous access mode.
|
||||
This parameter can be a value of @ref XFMC_Access_Mode */
|
||||
} XFMC_NorSramTimingInitType;
|
||||
|
||||
/**
|
||||
* @brief XFMC NOR/SRAM Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
|
||||
This parameter can be a value of @ref XFMC_NORSRAM_Bank */
|
||||
|
||||
uint32_t DataAddrMux; /*!< Specifies whether the address and data values are
|
||||
multiplexed on the databus or not.
|
||||
This parameter can be a value of @ref XFMC_Data_Address_Bus_Multiplexing */
|
||||
|
||||
uint32_t MemType; /*!< Specifies the type of external memory attached to
|
||||
the corresponding memory bank.
|
||||
This parameter can be a value of @ref XFMC_Memory_Type */
|
||||
|
||||
uint32_t MemDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be a value of @ref XFMC_Data_Width */
|
||||
|
||||
uint32_t BurstAccMode; /*!< Enables or disables the burst access mode for Flash memory,
|
||||
valid only with synchronous burst Flash memories.
|
||||
This parameter can be a value of @ref XFMC_Burst_Access_Mode */
|
||||
|
||||
uint32_t AsynchroWait; /*!< Enables or disables wait signal during asynchronous transfers,
|
||||
valid only with asynchronous Flash memories.
|
||||
This parameter can be a value of @ref AsynchroWait */
|
||||
|
||||
uint32_t WaitSigPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
|
||||
the Flash memory in burst mode.
|
||||
This parameter can be a value of @ref XFMC_Wait_Signal_Polarity */
|
||||
|
||||
uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
|
||||
memory, valid only when accessing Flash memories in burst mode.
|
||||
This parameter can be a value of @ref XFMC_Wrap_Mode */
|
||||
|
||||
uint32_t WaitSigConfig; /*!< Specifies if the wait signal is asserted by the memory one
|
||||
clock cycle before the wait state or during the wait state,
|
||||
valid only when accessing memories in burst mode.
|
||||
This parameter can be a value of @ref XFMC_Wait_Timing */
|
||||
|
||||
uint32_t WriteEnable; /*!< Enables or disables the write operation in the selected bank by the XFMC.
|
||||
This parameter can be a value of @ref XFMC_Write_Operation */
|
||||
|
||||
uint32_t WaitSigEnable; /*!< Enables or disables the wait-state insertion via wait
|
||||
signal, valid for Flash memory access in burst mode.
|
||||
This parameter can be a value of @ref XFMC_Wait_Signal */
|
||||
|
||||
uint32_t ExtModeEnable; /*!< Enables or disables the extended mode.
|
||||
This parameter can be a value of @ref XFMC_Extended_Mode */
|
||||
|
||||
uint32_t WriteBurstEnable; /*!< Enables or disables the write burst operation.
|
||||
This parameter can be a value of @ref XFMC_Write_Burst */
|
||||
|
||||
XFMC_NorSramTimingInitType*
|
||||
RWTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
|
||||
|
||||
XFMC_NorSramTimingInitType* WTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
|
||||
} XFMC_NorSramInitTpye;
|
||||
|
||||
/**
|
||||
* @brief Timing parameters For XFMC NAND and PCCARD Banks
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SetTime; /*!< Defines the number of HCLK cycles to setup address before
|
||||
the command assertion for NAND-Flash read or write access
|
||||
to common/Attribute or I/O memory space (depending on
|
||||
the memory space timing to be configured).
|
||||
This parameter can be a value between 0 and 0xFF.*/
|
||||
|
||||
uint32_t WaitSetTime; /*!< Defines the minimum number of HCLK cycles to assert the
|
||||
command for NAND-Flash read or write access to
|
||||
common/Attribute or I/O memory space (depending on the
|
||||
memory space timing to be configured).
|
||||
This parameter can be a number between 0x00 and 0xFF */
|
||||
|
||||
uint32_t HoldSetTime; /*!< Defines the number of HCLK clock cycles to hold address
|
||||
(and data for write access) after the command deassertion
|
||||
for NAND-Flash read or write access to common/Attribute
|
||||
or I/O memory space (depending on the memory space timing
|
||||
to be configured).
|
||||
This parameter can be a number between 0x00 and 0xFF */
|
||||
|
||||
uint32_t HiZSetTime; /*!< Defines the number of HCLK clock cycles during which the
|
||||
databus is kept in HiZ after the start of a NAND-Flash
|
||||
write access to common/Attribute or I/O memory space (depending
|
||||
on the memory space timing to be configured).
|
||||
This parameter can be a number between 0x00 and 0xFF */
|
||||
} XFMC_NandTimingInitType;
|
||||
|
||||
/**
|
||||
* @brief XFMC NAND Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Bank; /*!< Specifies the NAND memory bank that will be used.
|
||||
This parameter can be a value of @ref XFMC_NAND_Bank */
|
||||
|
||||
uint32_t WaitFeatureEnable; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
|
||||
This parameter can be any value of @ref XFMC_Wait_feature */
|
||||
|
||||
uint32_t MemDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be any value of @ref XFMC_Data_Width */
|
||||
|
||||
uint32_t EccEnable; /*!< Enables or disables the ECC computation.
|
||||
This parameter can be any value of @ref XFMC_Ecc */
|
||||
|
||||
uint32_t EccPageSize; /*!< Defines the page size for the extended ECC.
|
||||
This parameter can be any value of @ref XFMC_ECC_Page_Size */
|
||||
|
||||
uint32_t TCLRSetTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low.
|
||||
This parameter can be a value between 0 and 0xFF. */
|
||||
|
||||
uint32_t TARSetTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between 0x0 and 0xFF */
|
||||
|
||||
XFMC_NandTimingInitType* CommSpaceTimingStruct; /*!< XFMC Common Space Timing */
|
||||
|
||||
XFMC_NandTimingInitType* AttrSpaceTimingStruct; /*!< XFMC Attribute Space Timing */
|
||||
} XFMC_NandInitType;
|
||||
|
||||
/**
|
||||
* @brief XFMC PCCARD Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t WaitFeatureEnable; /*!< Enables or disables the Wait feature for the Memory Bank.
|
||||
This parameter can be any value of @ref XFMC_Wait_feature */
|
||||
|
||||
uint32_t TCLRSetTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between CLE low and RE low.
|
||||
This parameter can be a value between 0 and 0xFF. */
|
||||
|
||||
uint32_t TARSetTime; /*!< Defines the number of HCLK cycles to configure the
|
||||
delay between ALE low and RE low.
|
||||
This parameter can be a number between 0x0 and 0xFF */
|
||||
|
||||
XFMC_NandTimingInitType* CommSpaceTimingStruct; /*!< XFMC Common Space Timing */
|
||||
|
||||
XFMC_NandTimingInitType* AttrSpaceTimingStruct; /*!< XFMC Attribute Space Timing */
|
||||
|
||||
XFMC_NandTimingInitType* XFMC_IOSpaceTimingStruct; /*!< XFMC IO Space Timing */
|
||||
} XFMC_PCCARDInitType;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_NORSRAM_Bank
|
||||
* @{
|
||||
*/
|
||||
#define XFMC_BANK1_NORSRAM1 ((uint32_t)0x00000000)
|
||||
#define XFMC_BANK1_NORSRAM2 ((uint32_t)0x00000002)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_NAND_Bank
|
||||
* @{
|
||||
*/
|
||||
#define XFMC_BANK2_NAND ((uint32_t)0x00000010)
|
||||
#define XFMC_BANK3_NAND ((uint32_t)0x00000100)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_XFMC_NORSRAM_BANK(BANK) (((BANK) == XFMC_BANK1_NORSRAM1) || ((BANK) == XFMC_BANK1_NORSRAM2))
|
||||
|
||||
#define IS_XFMC_NAND_BANK(BANK) (((BANK) == XFMC_BANK2_NAND) || ((BANK) == XFMC_BANK3_NAND))
|
||||
|
||||
#define IS_XFMC_GETFLAG_BANK(BANK) (((BANK) == XFMC_BANK2_NAND) || ((BANK) == XFMC_BANK3_NAND))
|
||||
|
||||
#define IS_XFMC_IT_BANK(BANK) (((BANK) == XFMC_BANK2_NAND) || ((BANK) == XFMC_BANK3_NAND))
|
||||
|
||||
/** @addtogroup NOR_SRAM_Controller
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Data_Address_Bus_Multiplexing
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XFMC_DATA_ADDR_MUX_DISABLE ((uint32_t)0x00000000)
|
||||
#define XFMC_DATA_ADDR_MUX_ENABLE ((uint32_t)0x00000002)
|
||||
#define IS_XFMC_MUX(MUX) (((MUX) == XFMC_DATA_ADDR_MUX_DISABLE) || ((MUX) == XFMC_DATA_ADDR_MUX_ENABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Memory_Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XFMC_MEM_TYPE_SRAM ((uint32_t)0x00000000)
|
||||
#define XFMC_MEM_TYPE_PSRAM ((uint32_t)0x00000004)
|
||||
#define XFMC_MEM_TYPE_NOR ((uint32_t)0x00000008)
|
||||
#define IS_XFMC_MEMORY(MEMORY) \
|
||||
(((MEMORY) == XFMC_MEM_TYPE_SRAM) || ((MEMORY) == XFMC_MEM_TYPE_PSRAM) || ((MEMORY) == XFMC_MEM_TYPE_NOR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Data_Width
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XFMC_MEM_DATA_WIDTH_8B ((uint32_t)0x00000000)
|
||||
#define XFMC_MEM_DATA_WIDTH_16B ((uint32_t)0x00000010)
|
||||
#define IS_XFMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == XFMC_MEM_DATA_WIDTH_8B) || ((WIDTH) == XFMC_MEM_DATA_WIDTH_16B))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Burst_Access_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XFMC_BURST_ACC_MODE_DISABLE ((uint32_t)0x00000000)
|
||||
#define XFMC_BURST_ACC_MODE_ENABLE ((uint32_t)0x00000100)
|
||||
#define IS_XFMC_BURSTMODE(STATE) (((STATE) == XFMC_BURST_ACC_MODE_DISABLE) || ((STATE) == XFMC_BURST_ACC_MODE_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup AsynchroWait
|
||||
* @{
|
||||
*/
|
||||
#define XFMC_ASYNCHRO_WAIT_DISABLE ((uint32_t)0x00000000)
|
||||
#define XFMC_ASYNCHRO_WAIT_ENABLE ((uint32_t)0x00008000)
|
||||
#define IS_XFMC_ASYNWAIT(STATE) (((STATE) == XFMC_ASYNCHRO_WAIT_DISABLE) || ((STATE) == XFMC_ASYNCHRO_WAIT_ENABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Wait_Signal_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XFMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
|
||||
#define XFMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
|
||||
#define IS_XFMC_WAIT_POLARITY(POLARITY) \
|
||||
(((POLARITY) == XFMC_WAIT_SIGNAL_POLARITY_LOW) || ((POLARITY) == XFMC_WAIT_SIGNAL_POLARITY_HIGH))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Wrap_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XFMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
|
||||
#define XFMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
|
||||
#define IS_XFMC_WRAP_MODE(MODE) (((MODE) == XFMC_WRAP_MODE_DISABLE) || ((MODE) == XFMC_WRAP_MODE_ENABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Wait_Timing
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XFMC_WAIT_SIG_ACTIVE_BEFORE_WAIT_STATE ((uint32_t)0x00000000)
|
||||
#define XFMC_WAIT_SIG_ACTIVE_DURING_WAIT_STATE ((uint32_t)0x00000800)
|
||||
#define IS_XFMC_WAIT_SIGNAL_ACTIVE(ACTIVE) \
|
||||
(((ACTIVE) == XFMC_WAIT_SIG_ACTIVE_BEFORE_WAIT_STATE) || ((ACTIVE) == XFMC_WAIT_SIG_ACTIVE_DURING_WAIT_STATE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Write_Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XFMC_WRITE_DISABLE ((uint32_t)0x00000000)
|
||||
#define XFMC_WRITE_ENABLE ((uint32_t)0x00001000)
|
||||
#define IS_XFMC_WRITE_OPERATION(OPERATION) (((OPERATION) == XFMC_WRITE_DISABLE) || ((OPERATION) == XFMC_WRITE_ENABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Wait_Signal
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XFMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
|
||||
#define XFMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
|
||||
#define IS_XFMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == XFMC_WAIT_SIGNAL_DISABLE) || ((SIGNAL) == XFMC_WAIT_SIGNAL_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Extended_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XFMC_EXTENDED_DISABLE ((uint32_t)0x00000000)
|
||||
#define XFMC_EXTENDED_ENABLE ((uint32_t)0x00004000)
|
||||
|
||||
#define IS_XFMC_EXTENDED_MODE(MODE) (((MODE) == XFMC_EXTENDED_DISABLE) || ((MODE) == XFMC_EXTENDED_ENABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Write_Burst
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XFMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
|
||||
#define XFMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
|
||||
#define IS_XFMC_WRITE_BURST(BURST) (((BURST) == XFMC_WRITE_BURST_DISABLE) || ((BURST) == XFMC_WRITE_BURST_ENABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Address_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_XFMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Address_Hold_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_XFMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Data_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_XFMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Bus_Turn_around_Duration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_XFMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_CLK_Division
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_XFMC_CLK_DIV(DIV) ((DIV) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Data_Latency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_XFMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Access_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XFMC_ACC_MODE_A ((uint32_t)0x00000000)
|
||||
#define XFMC_ACC_MODE_B ((uint32_t)0x10000000)
|
||||
#define XFMC_ACC_MODE_C ((uint32_t)0x20000000)
|
||||
#define XFMC_ACC_MODE_D ((uint32_t)0x30000000)
|
||||
#define IS_XFMC_ACCESS_MODE(MODE) \
|
||||
(((MODE) == XFMC_ACC_MODE_A) || ((MODE) == XFMC_ACC_MODE_B) || ((MODE) == XFMC_ACC_MODE_C) \
|
||||
|| ((MODE) == XFMC_ACC_MODE_D))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup NAND_PCCARD_Controller
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Wait_feature
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XFMC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
|
||||
#define XFMC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
|
||||
#define IS_XFMC_WAIT_FEATURE(FEATURE) \
|
||||
(((FEATURE) == XFMC_WAIT_FEATURE_DISABLE) || ((FEATURE) == XFMC_WAIT_FEATURE_ENABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Ecc
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XFMC_ECC_DISABLE ((uint32_t)0x00000000)
|
||||
#define XFMC_ECC_ENABLE ((uint32_t)0x00000040)
|
||||
#define IS_XFMC_ECC_STATE(STATE) (((STATE) == XFMC_ECC_DISABLE) || ((STATE) == XFMC_ECC_ENABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_ECC_Page_Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XFMC_ECC_PAGE_SIZE_256BYTES ((uint32_t)0x00000000)
|
||||
#define XFMC_ECC_PAGE_SIZE_512BYTES ((uint32_t)0x00020000)
|
||||
#define XFMC_ECC_PAGE_SIZE_1024BYTES ((uint32_t)0x00040000)
|
||||
#define XFMC_ECC_PAGE_SIZE_2048BYTES ((uint32_t)0x00060000)
|
||||
#define XFMC_ECC_PAGE_SIZE_4096BYTES ((uint32_t)0x00080000)
|
||||
#define XFMC_ECC_PAGE_SIZE_8192BYTES ((uint32_t)0x000A0000)
|
||||
#define IS_XFMC_ECCPAGE_SIZE(SIZE) \
|
||||
(((SIZE) == XFMC_ECC_PAGE_SIZE_256BYTES) || ((SIZE) == XFMC_ECC_PAGE_SIZE_512BYTES) \
|
||||
|| ((SIZE) == XFMC_ECC_PAGE_SIZE_1024BYTES) || ((SIZE) == XFMC_ECC_PAGE_SIZE_2048BYTES) \
|
||||
|| ((SIZE) == XFMC_ECC_PAGE_SIZE_4096BYTES) || ((SIZE) == XFMC_ECC_PAGE_SIZE_8192BYTES))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_TCLR_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_XFMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_TAR_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_XFMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_XFMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Wait_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_XFMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Hold_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_XFMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_HiZ_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_XFMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Flags
|
||||
* @{
|
||||
*/
|
||||
#define XFMC_FLAG_FEMPT ((uint32_t)0x00000040)
|
||||
#define IS_XFMC_GET_FLAG(FLAG) ((FLAG == XFMC_FLAG_FEMPT))
|
||||
|
||||
#define IS_XFMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void XFMC_DeInitNorSram(uint32_t Bank);
|
||||
void XFMC_DeInitNand(uint32_t Bank);
|
||||
void XFMC_PCCARDDeInit(void);
|
||||
void XFMC_InitNorSram(XFMC_NorSramInitTpye* XFMC_NORSRAMInitStruct);
|
||||
void XFMC_InitNand(XFMC_NandInitType* XFMC_NANDInitStruct);
|
||||
void XFMC_PCCARDInit(XFMC_PCCARDInitType* XFMC_PCCARDInitStruct);
|
||||
void XFMC_InitNorSramStruct(XFMC_NorSramInitTpye* XFMC_NORSRAMInitStruct);
|
||||
void XFMC_InitNandStruct(XFMC_NandInitType* XFMC_NANDInitStruct);
|
||||
// void XFMC_PCCARDStructInit(XFMC_PCCARDInitType* XFMC_PCCARDInitStruct);
|
||||
void XFMC_EnableNorSram(uint32_t Bank, FunctionalState Cmd);
|
||||
void XFMC_EnableNand(uint32_t Bank, FunctionalState Cmd);
|
||||
// void XFMC_PCCARDCmd(FunctionalState Cmd);
|
||||
void XFMC_EnableNandEcc(uint32_t Bank, FunctionalState Cmd);
|
||||
uint32_t XFMC_GetEcc(uint32_t Bank);
|
||||
FlagStatus XFMC_GetFlag(uint32_t Bank, uint32_t XFMC_FLAG);
|
||||
void XFMC_ClrFlag(uint32_t Bank, uint32_t XFMC_FLAG);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__N32G45X_XFMC_H__ */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,229 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file misc.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "misc.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC
|
||||
* @brief MISC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the priority grouping: pre-emption priority and subpriority.
|
||||
* @param NVIC_PriorityGroup specifies the priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PriorityGroup_0 0 bits for pre-emption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_1 1 bits for pre-emption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_2 2 bits for pre-emption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_3 3 bits for pre-emption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_4 4 bits for pre-emption priority
|
||||
* 0 bits for subpriority
|
||||
*/
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
|
||||
|
||||
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
|
||||
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the NVIC peripheral according to the specified
|
||||
* parameters in the NVIC_InitStruct.
|
||||
* @param NVIC_InitStruct pointer to a NVIC_InitType structure that contains
|
||||
* the configuration information for the specified NVIC peripheral.
|
||||
*/
|
||||
void NVIC_Init(NVIC_InitType* NVIC_InitStruct)
|
||||
{
|
||||
uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
|
||||
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
|
||||
|
||||
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
|
||||
{
|
||||
/* Compute the Corresponding IRQ Priority --------------------------------*/
|
||||
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700)) >> 0x08;
|
||||
tmppre = (0x4 - tmppriority);
|
||||
tmpsub = tmpsub >> tmppriority;
|
||||
|
||||
tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
|
||||
tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
|
||||
tmppriority = tmppriority << 0x04;
|
||||
|
||||
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
|
||||
|
||||
/* Enable the Selected IRQ Channels --------------------------------------*/
|
||||
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01
|
||||
<< (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Selected IRQ Channels -------------------------------------*/
|
||||
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01
|
||||
<< (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the vector table location and Offset.
|
||||
* @param NVIC_VectTab specifies if the vector table is in RAM or FLASH memory.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_VectTab_RAM
|
||||
* @arg NVIC_VectTab_FLASH
|
||||
* @param Offset Vector Table base offset field. This value must be a multiple
|
||||
* of 0x200.
|
||||
*/
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
|
||||
assert_param(IS_NVIC_OFFSET(Offset));
|
||||
|
||||
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the condition for the system to enter low power mode.
|
||||
* @param LowPowerMode Specifies the new mode for the system to enter low power mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_LP_SEVONPEND
|
||||
* @arg NVIC_LP_SLEEPDEEP
|
||||
* @arg NVIC_LP_SLEEPONEXIT
|
||||
* @param Cmd new state of LP condition. This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_LP(LowPowerMode));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
SCB->SCR |= LowPowerMode;
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param SysTick_CLKSource specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SysTick_CLKSource_HCLK_Div8 AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SysTick_CLKSource_HCLK AHB clock selected as SysTick clock source.
|
||||
*/
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
|
||||
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SysTick_CLKSource_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,302 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_bkp.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x_bkp.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup BKP
|
||||
* @brief BKP driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup BKP_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup BKP_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ------------ BKP registers bit address in the alias region --------------- */
|
||||
#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CTRL Register ----*/
|
||||
|
||||
/* Alias word address of TPAL bit */
|
||||
#define CTRL_OFFSET (BKP_OFFSET + 0x30)
|
||||
#define TP_ALEV_BIT 0x01
|
||||
#define CTRL_TP_ALEV_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (TP_ALEV_BIT * 4))
|
||||
|
||||
/* Alias word address of TPE bit */
|
||||
#define TP_EN_BIT 0x00
|
||||
#define CTRL_TP_EN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (TP_EN_BIT * 4))
|
||||
|
||||
/* --- CTRLSTS Register ---*/
|
||||
|
||||
/* Alias word address of TPIE bit */
|
||||
#define CTRLSTS_OFFSET (BKP_OFFSET + 0x34)
|
||||
#define TPINT_EN_BIT 0x02
|
||||
#define CTRLSTS_TPINT_EN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (TPINT_EN_BIT * 4))
|
||||
|
||||
/* Alias word address of TIF bit */
|
||||
#define TINTF_BIT 0x09
|
||||
#define CTRLSTS_TINTF_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (TINTF_BIT * 4))
|
||||
|
||||
/* Alias word address of TEF bit */
|
||||
#define TEF_BIT 0x08
|
||||
#define CTRLSTS_TEF_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (TEF_BIT * 4))
|
||||
|
||||
/* ---------------------- BKP registers bit mask ------------------------ */
|
||||
|
||||
/* RTCCTRL register bit mask */
|
||||
#define RTCCTRL_CALV_MASK ((uint16_t)0xFF80)
|
||||
#define RTCCTRL_MASK ((uint16_t)0xFC7F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup BKP_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup BKP_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup BKP_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup BKP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the BKP peripheral registers to their default reset values.
|
||||
*/
|
||||
void BKP_DeInit(void)
|
||||
{
|
||||
RCC_EnableBackupReset(ENABLE);
|
||||
RCC_EnableBackupReset(DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the Tamper Pin active level.
|
||||
* @param BKP_TamperPinLevel specifies the Tamper Pin active level.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg BKP_TP_HIGH Tamper pin active on high level
|
||||
* @arg BKP_TP_LOW Tamper pin active on low level
|
||||
*/
|
||||
void BKP_ConfigTPLevel(uint16_t BKP_TamperPinLevel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_TP_LEVEL(BKP_TamperPinLevel));
|
||||
*(__IO uint32_t*)CTRL_TP_ALEV_BB = BKP_TamperPinLevel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Tamper Pin activation.
|
||||
* @param Cmd new state of the Tamper Pin activation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void BKP_TPEnable(FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
*(__IO uint32_t*)CTRL_TP_EN_BB = (uint32_t)Cmd;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Tamper Pin Interrupt.
|
||||
* @param Cmd new state of the Tamper Pin Interrupt.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void BKP_TPIntEnable(FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
*(__IO uint32_t*)CTRLSTS_TPINT_EN_BB = (uint32_t)Cmd;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the RTC output source to output on the Tamper pin.
|
||||
* @param BKP_RTCOutputSource specifies the RTC output source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg BKP_RTCOUTPUT_NONE no RTC output on the Tamper pin.
|
||||
* @arg BKP_RTCOUTPUT_CALCLK output the RTC clock with frequency
|
||||
* divided by 64 on the Tamper pin.
|
||||
* @arg BKP_RTCOUTPUT_ALARM output the RTC Alarm pulse signal on
|
||||
* the Tamper pin.
|
||||
* @arg BKP_RTCOUTPUT_SECOND output the RTC Second pulse signal on
|
||||
* the Tamper pin.
|
||||
*/
|
||||
void BKP_ConfigRtcOutput(uint16_t BKP_RTCOutputSource)
|
||||
{
|
||||
uint16_t tmpregister = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_RTC_RTCOUTPUT(BKP_RTCOutputSource));
|
||||
tmpregister = BKP->RTCCTRL;
|
||||
/* Clear CALO, ASO_EN and ASO_SEL bits */
|
||||
tmpregister &= RTCCTRL_MASK;
|
||||
|
||||
/* Set CALO, ASO_EN and ASO_SEL bits according to BKP_RTCOutputSource value */
|
||||
tmpregister |= BKP_RTCOutputSource;
|
||||
/* Store the new value */
|
||||
BKP->RTCCTRL = tmpregister;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets RTC Clock Calibration value.
|
||||
* @param CalibrationValue specifies the RTC Clock Calibration value.
|
||||
* This parameter must be a number between 0 and 0x7F.
|
||||
*/
|
||||
void BKP_SetRtcCalValue(uint8_t CalibrationValue)
|
||||
{
|
||||
uint16_t tmpregister = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_CAL_VALUE(CalibrationValue));
|
||||
tmpregister = BKP->RTCCTRL;
|
||||
/* Clear CAL[6:0] bits */
|
||||
tmpregister &= RTCCTRL_CALV_MASK;
|
||||
/* Set CAL[6:0] bits according to CalibrationValue value */
|
||||
tmpregister |= CalibrationValue;
|
||||
/* Store the new value */
|
||||
BKP->RTCCTRL = tmpregister;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes user data to the specified Data Backup Register.
|
||||
* @param BKP_DAT specifies the Data Backup Register.
|
||||
* This parameter can be BKP_DATx where x:[1, 42]
|
||||
* @param Data data to write
|
||||
*/
|
||||
void BKP_WriteBkpData(uint16_t BKP_DAT, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_DAT(BKP_DAT));
|
||||
|
||||
tmp = (uint32_t)BKP_BASE;
|
||||
tmp += BKP_DAT;
|
||||
|
||||
*(__IO uint32_t*)tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads data from the specified Data Backup Register.
|
||||
* @param BKP_DAT specifies the Data Backup Register.
|
||||
* This parameter can be BKP_DATx where x:[1, 42]
|
||||
* @return The content of the specified Data Backup Register
|
||||
*/
|
||||
uint16_t BKP_ReadBkpData(uint16_t BKP_DAT)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_BKP_DAT(BKP_DAT));
|
||||
|
||||
tmp = (uint32_t)BKP_BASE;
|
||||
tmp += BKP_DAT;
|
||||
|
||||
return (*(__IO uint16_t*)tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the Tamper Pin Event flag is set or not.
|
||||
* @return The new state of the Tamper Pin Event flag (SET or RESET).
|
||||
*/
|
||||
FlagStatus BKP_GetTEFlag(void)
|
||||
{
|
||||
return (FlagStatus)(*(__IO uint32_t*)CTRLSTS_TEF_BB);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears Tamper Pin Event pending flag.
|
||||
*/
|
||||
void BKP_ClrTEFlag(void)
|
||||
{
|
||||
/* Set CTE bit to clear Tamper Pin Event flag */
|
||||
BKP->CTRLSTS |= BKP_CTRLSTS_CLRTE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the Tamper Pin Interrupt has occurred or not.
|
||||
* @return The new state of the Tamper Pin Interrupt (SET or RESET).
|
||||
*/
|
||||
INTStatus BKP_GetTINTFlag(void)
|
||||
{
|
||||
return (INTStatus)(*(__IO uint32_t*)CTRLSTS_TINTF_BB);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears Tamper Pin Interrupt pending bit.
|
||||
*/
|
||||
void BKP_ClrTINTFlag(void)
|
||||
{
|
||||
/* Set CTI bit to clear Tamper Pin Interrupt pending bit */
|
||||
BKP->CTRLSTS |= BKP_CTRLSTS_CLRTINT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,229 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_comp.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x_comp.h"
|
||||
#include "n32g45x_rcc.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP
|
||||
* @brief COMP driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
#define SetBitMsk(reg, bit, msk) ((reg) = ((reg) & ~(msk) | (bit)))
|
||||
#define ClrBit(reg, bit) ((reg) &= ~(bit))
|
||||
#define SetBit(reg, bit) ((reg) |= (bit))
|
||||
#define GetBit(reg, bit) ((reg) & (bit))
|
||||
/**
|
||||
* @brief Deinitializes the COMP peripheral registers to their default reset values.
|
||||
*/
|
||||
void COMP_DeInit(void)
|
||||
{
|
||||
;
|
||||
}
|
||||
void COMP_StructInit(COMP_InitType* COMP_InitStruct)
|
||||
{
|
||||
COMP_InitStruct->InpDacConnect = false; // only COMP1 have this bit
|
||||
|
||||
COMP_InitStruct->Blking = COMP_CTRL_BLKING_NO; /*see @ref COMP_CTRL_BLKING */
|
||||
|
||||
COMP_InitStruct->Hyst = COMP_CTRL_HYST_NO; // see @COMPx_CTRL_HYST_MASK
|
||||
|
||||
COMP_InitStruct->PolRev = false; // out polarity reverse
|
||||
|
||||
COMP_InitStruct->OutSel = COMPX_CTRL_OUTSEL_NC;
|
||||
COMP_InitStruct->InpSel = COMPX_CTRL_INPSEL_RES;
|
||||
COMP_InitStruct->InmSel = COMPX_CTRL_INMSEL_RES;
|
||||
|
||||
COMP_InitStruct->En = false;
|
||||
}
|
||||
void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct)
|
||||
{
|
||||
COMP_SingleType* pCS = &COMP->Cmp[COMPx];
|
||||
__IO uint32_t tmp;
|
||||
|
||||
// filter
|
||||
tmp = pCS->FILC;
|
||||
SetBitMsk(tmp, COMP_InitStruct->SampWindow << 6, COMP_FILC_SAMPW_MASK);
|
||||
SetBitMsk(tmp, COMP_InitStruct->Thresh << 1, COMP_FILC_THRESH_MASK);
|
||||
SetBitMsk(tmp, COMP_InitStruct->FilterEn << 0, COMP_FILC_FILEN_MASK);
|
||||
pCS->FILC = tmp;
|
||||
// filter psc
|
||||
pCS->FILP = COMP_InitStruct->ClkPsc;
|
||||
|
||||
// ctrl
|
||||
tmp = pCS->CTRL;
|
||||
if (COMPx == COMP1)
|
||||
{
|
||||
if (COMP_InitStruct->InpDacConnect)
|
||||
SetBit(tmp, COMP1_CTRL_INPDAC_MASK);
|
||||
else
|
||||
ClrBit(tmp, COMP1_CTRL_INPDAC_MASK);
|
||||
}
|
||||
SetBitMsk(tmp, COMP_InitStruct->Blking, COMP_CTRL_BLKING_MASK);
|
||||
SetBitMsk(tmp, COMP_InitStruct->Hyst, COMPx_CTRL_HYST_MASK);
|
||||
if (COMP_InitStruct->PolRev)
|
||||
SetBit(tmp, COMP_POL_MASK);
|
||||
else
|
||||
ClrBit(tmp, COMP_POL_MASK);
|
||||
SetBitMsk(tmp, COMP_InitStruct->OutSel, COMP_CTRL_OUTSEL_MASK);
|
||||
SetBitMsk(tmp, COMP_InitStruct->InpSel, COMP_CTRL_INPSEL_MASK);
|
||||
SetBitMsk(tmp, COMP_InitStruct->InmSel, COMP_CTRL_INMSEL_MASK);
|
||||
if (COMP_InitStruct->En)
|
||||
SetBit(tmp, COMP_CTRL_EN_MASK);
|
||||
else
|
||||
ClrBit(tmp, COMP_CTRL_EN_MASK);
|
||||
pCS->CTRL = tmp;
|
||||
}
|
||||
void COMP_Enable(COMPX COMPx, FunctionalState en)
|
||||
{
|
||||
if (en)
|
||||
SetBit(COMP->Cmp[COMPx].CTRL, COMP_CTRL_EN_MASK);
|
||||
else
|
||||
ClrBit(COMP->Cmp[COMPx].CTRL, COMP_CTRL_EN_MASK);
|
||||
}
|
||||
|
||||
void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel)
|
||||
{
|
||||
__IO uint32_t tmp = COMP->Cmp[COMPx].CTRL;
|
||||
SetBitMsk(tmp, VpSel, COMP_CTRL_INPSEL_MASK);
|
||||
COMP->Cmp[COMPx].CTRL = tmp;
|
||||
}
|
||||
void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel)
|
||||
{
|
||||
__IO uint32_t tmp = COMP->Cmp[COMPx].CTRL;
|
||||
SetBitMsk(tmp, VmSel, COMP_CTRL_INMSEL_MASK);
|
||||
COMP->Cmp[COMPx].CTRL = tmp;
|
||||
}
|
||||
void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig)
|
||||
{
|
||||
__IO uint32_t tmp = COMP->Cmp[COMPx].CTRL;
|
||||
SetBitMsk(tmp, OutTrig, COMP_CTRL_OUTSEL_MASK);
|
||||
COMP->Cmp[COMPx].CTRL = tmp;
|
||||
}
|
||||
// Lock see @COMP_LOCK
|
||||
void COMP_SetLock(uint32_t Lock)
|
||||
{
|
||||
COMP->LOCK = Lock;
|
||||
}
|
||||
// IntEn see @COMP_INTEN_CMPIEN
|
||||
void COMP_SetIntEn(uint32_t IntEn)
|
||||
{
|
||||
COMP->INTEN = IntEn;
|
||||
}
|
||||
// return see @COMP_INTSTS_CMPIS
|
||||
uint32_t COMP_GetIntSts(void)
|
||||
{
|
||||
return COMP->INTSTS;
|
||||
}
|
||||
// parma range see @COMP_VREFSCL
|
||||
// Vv2Trim,Vv1Trim max 63
|
||||
void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
SetBitMsk(tmp, Vv2Trim << 8, COMP_VREFSCL_VV2TRM_MSK);
|
||||
SetBitMsk(tmp, Vv2En << 7, COMP_VREFSCL_VV2EN_MSK);
|
||||
SetBitMsk(tmp, Vv1Trim << 1, COMP_VREFSCL_VV1TRM_MSK);
|
||||
SetBitMsk(tmp, Vv1En << 0, COMP_VREFSCL_VV1EN_MSK);
|
||||
|
||||
COMP->VREFSCL = tmp;
|
||||
}
|
||||
// SET when comp out 1
|
||||
// RESET when comp out 0
|
||||
FlagStatus COMP_GetOutStatus(COMPX COMPx)
|
||||
{
|
||||
return (COMP->Cmp[COMPx].CTRL & COMP_CTRL_OUTSEL_MASK) ? SET : RESET;
|
||||
}
|
||||
// get one comp interrupt flags
|
||||
FlagStatus COMP_GetIntStsOneComp(COMPX COMPx)
|
||||
{
|
||||
return (COMP_GetIntSts() & (0x01 << COMPx)) ? SET : RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,228 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_crc.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x_crc.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @brief CRC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Resets the CRC Data register (DAT).
|
||||
*/
|
||||
void CRC32_ResetCrc(void)
|
||||
{
|
||||
/* Reset CRC generator */
|
||||
CRC->CRC32CTRL = CRC32_CTRL_RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of a given data word(32-bit).
|
||||
* @param Data data word(32-bit) to compute its CRC
|
||||
* @return 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC32_CalcCrc(uint32_t Data)
|
||||
{
|
||||
CRC->CRC32DAT = Data;
|
||||
|
||||
return (CRC->CRC32DAT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
|
||||
* @param pBuffer pointer to the buffer containing the data to be computed
|
||||
* @param BufferLength length of the buffer to be computed
|
||||
* @return 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index = 0;
|
||||
|
||||
for (index = 0; index < BufferLength; index++)
|
||||
{
|
||||
CRC->CRC32DAT = pBuffer[index];
|
||||
}
|
||||
return (CRC->CRC32DAT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the current CRC value.
|
||||
* @return 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC32_GetCrc(void)
|
||||
{
|
||||
return (CRC->CRC32DAT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stores a 8-bit data in the Independent Data(ID) register.
|
||||
* @param IDValue 8-bit value to be stored in the ID register
|
||||
*/
|
||||
void CRC32_SetIDat(uint8_t IDValue)
|
||||
{
|
||||
CRC->CRC32IDAT = IDValue;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the 8-bit data stored in the Independent Data(ID) register
|
||||
* @return 8-bit value of the ID register
|
||||
*/
|
||||
uint8_t CRC32_GetIDat(void)
|
||||
{
|
||||
return (CRC->CRC32IDAT);
|
||||
}
|
||||
|
||||
// CRC16 add
|
||||
void __CRC16_SetLittleEndianFmt(void)
|
||||
{
|
||||
CRC->CRC16CTRL = CRC16_CTRL_LITTLE | CRC->CRC16CTRL;
|
||||
}
|
||||
void __CRC16_SetBigEndianFmt(void)
|
||||
{
|
||||
CRC->CRC16CTRL = CRC16_CTRL_BIG & CRC->CRC16CTRL;
|
||||
}
|
||||
void __CRC16_SetCleanEnable(void)
|
||||
{
|
||||
CRC->CRC16CTRL = CRC16_CTRL_RESET | CRC->CRC16CTRL;
|
||||
}
|
||||
void __CRC16_SetCleanDisable(void)
|
||||
{
|
||||
CRC->CRC16CTRL = CRC16_CTRL_NO_RESET & CRC->CRC16CTRL;
|
||||
}
|
||||
|
||||
uint16_t __CRC16_CalcCrc(uint8_t Data)
|
||||
{
|
||||
CRC->CRC16DAT = Data;
|
||||
return (CRC->CRC16D);
|
||||
}
|
||||
|
||||
void __CRC16_SetCrc(uint8_t Data)
|
||||
{
|
||||
CRC->CRC16DAT = Data;
|
||||
}
|
||||
|
||||
uint16_t __CRC16_GetCrc(void)
|
||||
{
|
||||
return (CRC->CRC16D);
|
||||
}
|
||||
|
||||
void __CRC16_SetLRC(uint8_t Data)
|
||||
{
|
||||
CRC->LRC = Data;
|
||||
}
|
||||
|
||||
uint8_t __CRC16_GetLRC(void)
|
||||
{
|
||||
return (CRC->LRC);
|
||||
}
|
||||
|
||||
uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index = 0;
|
||||
|
||||
CRC->CRC16D = 0x00;
|
||||
// CRC16_SetCleanEnable();
|
||||
for (index = 0; index < BufferLength; index++)
|
||||
{
|
||||
CRC->CRC16DAT = pBuffer[index];
|
||||
}
|
||||
return (CRC->CRC16D);
|
||||
}
|
||||
|
||||
uint16_t CRC16_CalcCRC(uint8_t Data)
|
||||
{
|
||||
CRC->CRC16DAT = Data;
|
||||
|
||||
return (CRC->CRC16D);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,421 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_dac.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x_dac.h"
|
||||
#include "n32g45x_rcc.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @brief DAC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* CTRL register Mask */
|
||||
#define CTRL_CLEAR_MASK ((uint32_t)0x00000FFE)
|
||||
|
||||
/* DAC Dual Channels SWTRIG masks */
|
||||
#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
|
||||
#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
|
||||
|
||||
/* DCH registers offsets */
|
||||
#define DR12CH1_OFFSET ((uint32_t)0x00000008)
|
||||
#define DR12CH2_OFFSET ((uint32_t)0x00000014)
|
||||
#define DR12DCH_OFFSET ((uint32_t)0x00000020)
|
||||
|
||||
/* DATO register offset */
|
||||
#define DATO1_OFFSET ((uint32_t)0x0000002C)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DAC peripheral registers to their default reset values.
|
||||
*/
|
||||
void DAC_DeInit(void)
|
||||
{
|
||||
/* Enable DAC reset state */
|
||||
RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, ENABLE);
|
||||
/* Release DAC from reset state */
|
||||
RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_DAC, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DAC peripheral according to the specified
|
||||
* parameters in the DAC_InitStruct.
|
||||
* @param DAC_Channel the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1 DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2 DAC Channel2 selected
|
||||
* @param DAC_InitStruct pointer to a DAC_InitType structure that
|
||||
* contains the configuration information for the specified DAC channel.
|
||||
*/
|
||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitType* DAC_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg1 = 0, tmpreg2 = 0;
|
||||
/* Check the DAC parameters */
|
||||
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->Trigger));
|
||||
assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->WaveGen));
|
||||
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->LfsrUnMaskTriAmp));
|
||||
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->BufferOutput));
|
||||
/*---------------------------- DAC CTRL Configuration --------------------------*/
|
||||
/* Get the DAC CTRL value */
|
||||
tmpreg1 = DAC->CTRL;
|
||||
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
|
||||
tmpreg1 &= ~(CTRL_CLEAR_MASK << DAC_Channel);
|
||||
/* Configure for the selected DAC channel: buffer output, trigger, wave generation,
|
||||
mask/amplitude for wave generation */
|
||||
/* Set TSELx and TENx bits according to Trigger value */
|
||||
/* Set WAVEx bits according to WaveGen value */
|
||||
/* Set MAMPx bits according to LfsrUnMaskTriAmp value */
|
||||
/* Set BOFFx bit according to BufferOutput value */
|
||||
tmpreg2 = (DAC_InitStruct->Trigger | DAC_InitStruct->WaveGen | DAC_InitStruct->LfsrUnMaskTriAmp
|
||||
| DAC_InitStruct->BufferOutput);
|
||||
/* Calculate CTRL register value depending on DAC_Channel */
|
||||
tmpreg1 |= tmpreg2 << DAC_Channel;
|
||||
/* Write to DAC CTRL */
|
||||
DAC->CTRL = tmpreg1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each DAC_InitStruct member with its default value.
|
||||
* @param DAC_InitStruct pointer to a DAC_InitType structure which will
|
||||
* be initialized.
|
||||
*/
|
||||
void DAC_ClearStruct(DAC_InitType* DAC_InitStruct)
|
||||
{
|
||||
/*--------------- Reset DAC init structure parameters values -----------------*/
|
||||
/* Initialize the Trigger member */
|
||||
DAC_InitStruct->Trigger = DAC_TRG_NONE;
|
||||
/* Initialize the WaveGen member */
|
||||
DAC_InitStruct->WaveGen = DAC_WAVEGEN_NONE;
|
||||
/* Initialize the LfsrUnMaskTriAmp member */
|
||||
DAC_InitStruct->LfsrUnMaskTriAmp = DAC_UNMASK_LFSRBIT0;
|
||||
/* Initialize the BufferOutput member */
|
||||
DAC_InitStruct->BufferOutput = DAC_BUFFOUTPUT_ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC channel.
|
||||
* @param DAC_Channel the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1 DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2 DAC Channel2 selected
|
||||
* @param Cmd new state of the DAC channel.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void DAC_Enable(uint32_t DAC_Channel, FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC channel */
|
||||
DAC->CTRL |= (DAC_CTRL_CH1EN << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC channel */
|
||||
DAC->CTRL &= ~(DAC_CTRL_CH1EN << DAC_Channel);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC channel DMA request.
|
||||
* @param DAC_Channel the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1 DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2 DAC Channel2 selected
|
||||
* @param Cmd new state of the selected DAC channel DMA request.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void DAC_DmaEnable(uint32_t DAC_Channel, FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC channel DMA request */
|
||||
DAC->CTRL |= (DAC_CTRL_DMA1EN << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC channel DMA request */
|
||||
DAC->CTRL &= ~(DAC_CTRL_DMA1EN << DAC_Channel);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel software trigger.
|
||||
* @param DAC_Channel the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1 DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2 DAC Channel2 selected
|
||||
* @param Cmd new state of the selected DAC channel software trigger.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void DAC_SoftTrgEnable(uint32_t DAC_Channel, FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
/* Enable software trigger for the selected DAC channel */
|
||||
DAC->SOTTR |= (uint32_t)DAC_SOTTR_TR1EN << (DAC_Channel >> 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable software trigger for the selected DAC channel */
|
||||
DAC->SOTTR &= ~((uint32_t)DAC_SOTTR_TR1EN << (DAC_Channel >> 4));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables simultaneously the two DAC channels software
|
||||
* triggers.
|
||||
* @param Cmd new state of the DAC channels software triggers.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void DAC_DualSoftwareTrgEnable(FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
/* Enable software trigger for both DAC channels */
|
||||
DAC->SOTTR |= DUAL_SWTRIG_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable software trigger for both DAC channels */
|
||||
DAC->SOTTR &= DUAL_SWTRIG_RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel wave generation.
|
||||
* @param DAC_Channel the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1 DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2 DAC Channel2 selected
|
||||
* @param DAC_Wave Specifies the wave type to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_WAVE_NOISE noise wave generation
|
||||
* @arg DAC_WAVE_TRIANGLE triangle wave generation
|
||||
* @param Cmd new state of the selected DAC channel wave generation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void DAC_WaveGenerationEnable(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_WAVE(DAC_Wave));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
/* Enable the selected wave generation for the selected DAC channel */
|
||||
DAC->CTRL |= DAC_Wave << DAC_Channel;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected wave generation for the selected DAC channel */
|
||||
DAC->CTRL &= ~(DAC_Wave << DAC_Channel);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel1.
|
||||
* @param DAC_Align Specifies the data alignment for DAC channel1.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_ALIGN_R_8BIT 8bit right data alignment selected
|
||||
* @arg DAC_ALIGN_L_12BIT 12bit left data alignment selected
|
||||
* @arg DAC_ALIGN_R_12BIT 12bit right data alignment selected
|
||||
* @param Data Data to be loaded in the selected data holding register.
|
||||
*/
|
||||
void DAC_SetCh1Data(uint32_t DAC_Align, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data));
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DR12CH1_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the DAC channel1 selected data holding register */
|
||||
*(__IO uint32_t*)tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel2.
|
||||
* @param DAC_Align Specifies the data alignment for DAC channel2.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_ALIGN_R_8BIT 8bit right data alignment selected
|
||||
* @arg DAC_ALIGN_L_12BIT 12bit left data alignment selected
|
||||
* @arg DAC_ALIGN_R_12BIT 12bit right data alignment selected
|
||||
* @param Data Data to be loaded in the selected data holding register.
|
||||
*/
|
||||
void DAC_SetCh2Data(uint32_t DAC_Align, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data));
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DR12CH2_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the DAC channel2 selected data holding register */
|
||||
*(__IO uint32_t*)tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for dual channel
|
||||
* DAC.
|
||||
* @param DAC_Align Specifies the data alignment for dual channel DAC.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_ALIGN_R_8BIT 8bit right data alignment selected
|
||||
* @arg DAC_ALIGN_L_12BIT 12bit left data alignment selected
|
||||
* @arg DAC_ALIGN_R_12BIT 12bit right data alignment selected
|
||||
* @param Data2 Data for DAC Channel2 to be loaded in the selected data
|
||||
* holding register.
|
||||
* @param Data1 Data for DAC Channel1 to be loaded in the selected data
|
||||
* holding register.
|
||||
*/
|
||||
void DAC_SetDualChData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
|
||||
{
|
||||
uint32_t data = 0, tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data1));
|
||||
assert_param(IS_DAC_DATA(Data2));
|
||||
|
||||
/* Calculate and set dual DAC data holding register value */
|
||||
if (DAC_Align == DAC_ALIGN_R_8BIT)
|
||||
{
|
||||
data = ((uint32_t)Data2 << 8) | Data1;
|
||||
}
|
||||
else
|
||||
{
|
||||
data = ((uint32_t)Data2 << 16) | Data1;
|
||||
}
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DR12DCH_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the dual DAC selected data holding register */
|
||||
*(__IO uint32_t*)tmp = data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param DAC_Channel the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_CHANNEL_1 DAC Channel1 selected
|
||||
* @arg DAC_CHANNEL_2 DAC Channel2 selected
|
||||
* @return The selected DAC channel data output value.
|
||||
*/
|
||||
uint16_t DAC_GetOutputDataVal(uint32_t DAC_Channel)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DATO1_OFFSET + ((uint32_t)DAC_Channel >> 2);
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
return (uint16_t)(*(__IO uint32_t*)tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,190 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_dbg.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x_dbg.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DBG
|
||||
* @brief DBG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the device revision number.
|
||||
* @return Device revision identifier
|
||||
*/
|
||||
uint32_t DBG_GetRevNum(void)
|
||||
{
|
||||
return (DBG->ID & 0x00FF);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device identifier.
|
||||
* @return Device identifier
|
||||
*/
|
||||
uint32_t DBG_GetDevNum(void)
|
||||
{
|
||||
uint32_t id = DBG->ID;
|
||||
return ((id & 0x00F00000) >> 20) | ((id & 0xFF00) >> 4);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the specified peripheral and low power mode behavior
|
||||
* when the MCU under Debug mode.
|
||||
* @param DBG_Periph specifies the peripheral and low power mode.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DBG_SLP Keep debugger connection during SLEEP mode
|
||||
* @arg DBG_STOP Keep debugger connection during STOP mode
|
||||
* @arg DBG_STDBY Keep debugger connection during STANDBY mode
|
||||
* @arg DBG_IWDG_STOP Debug IWDG stopped when Core is halted
|
||||
* @arg DBG_WWDG_STOP Debug WWDG stopped when Core is halted
|
||||
* @arg DBG_TIM1_STOP TIM1 counter stopped when Core is halted
|
||||
* @arg DBG_TIM2_STOP TIM2 counter stopped when Core is halted
|
||||
* @arg DBG_TIM3_STOP TIM3 counter stopped when Core is halted
|
||||
* @arg DBG_TIM4_STOP TIM4 counter stopped when Core is halted
|
||||
* @arg DBG_CAN1_STOP Debug CAN2 stopped when Core is halted
|
||||
* @arg DBG_I2C1SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when Core is halted
|
||||
* @arg DBG_I2C2SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when Core is halted
|
||||
* @arg DBG_TIM5_STOP TIM5 counter stopped when Core is halted
|
||||
* @arg DBG_TIM6_STOP TIM6 counter stopped when Core is halted
|
||||
* @arg DBG_TIM7_STOP TIM7 counter stopped when Core is halted
|
||||
* @arg DBG_TIM8_STOP TIM8 counter stopped when Core is halted
|
||||
* @arg DBG_CAN2_STOP Debug CAN2 stopped when Core is halted
|
||||
* @arg DBGMCU_TIM15_STOP TIM15 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM16_STOP TIM16 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM17_STOP TIM17 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM9_STOP TIM9 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM10_STOP TIM10 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM11_STOP TIM11 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM12_STOP TIM12 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM13_STOP TIM13 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM14_STOP TIM14 counter stopped when Core is halted
|
||||
* @param Cmd new state of the specified peripheral in Debug mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DBGMCU_PERIPH(DBG_Periph));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
DBG->CTRL |= DBG_Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
DBG->CTRL &= ~DBG_Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get FLASH size of this chip.
|
||||
*
|
||||
* @return FLASH size in bytes.
|
||||
*/
|
||||
uint32_t DBG_GetFlashSize(void)
|
||||
{
|
||||
return (DBG->ID & 0x000F0000);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get SRAM size of this chip.
|
||||
*
|
||||
* @return SRAM size in bytes.
|
||||
*/
|
||||
uint32_t DBG_GetSramSize(void)
|
||||
{
|
||||
return (((DBG->ID & 0xF0000000) >> 28) + 1) << 14;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,888 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_dma.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x_dma.h"
|
||||
#include "n32g45x_rcc.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @brief DMA driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* DMA1 Channelx interrupt pending bit masks */
|
||||
#define DMA1_CH1_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF1 | DMA_INTSTS_TXCF1 | DMA_INTSTS_HTXF1 | DMA_INTSTS_ERRF1))
|
||||
#define DMA1_CH2_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF2 | DMA_INTSTS_TXCF2 | DMA_INTSTS_HTXF2 | DMA_INTSTS_ERRF2))
|
||||
#define DMA1_CH3_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF3 | DMA_INTSTS_TXCF3 | DMA_INTSTS_HTXF3 | DMA_INTSTS_ERRF3))
|
||||
#define DMA1_CH4_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF4 | DMA_INTSTS_TXCF4 | DMA_INTSTS_HTXF4 | DMA_INTSTS_ERRF4))
|
||||
#define DMA1_CH5_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF5 | DMA_INTSTS_TXCF5 | DMA_INTSTS_HTXF5 | DMA_INTSTS_ERRF5))
|
||||
#define DMA1_CH6_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF6 | DMA_INTSTS_TXCF6 | DMA_INTSTS_HTXF6 | DMA_INTSTS_ERRF6))
|
||||
#define DMA1_CH7_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF7 | DMA_INTSTS_TXCF7 | DMA_INTSTS_HTXF7 | DMA_INTSTS_ERRF7))
|
||||
#define DMA1_CH8_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF8 | DMA_INTSTS_TXCF8 | DMA_INTSTS_HTXF8 | DMA_INTSTS_ERRF8))
|
||||
|
||||
/* DMA2 Channelx interrupt pending bit masks */
|
||||
#define DMA2_CH1_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF1 | DMA_INTSTS_TXCF1 | DMA_INTSTS_HTXF1 | DMA_INTSTS_ERRF1))
|
||||
#define DMA2_CH2_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF2 | DMA_INTSTS_TXCF2 | DMA_INTSTS_HTXF2 | DMA_INTSTS_ERRF2))
|
||||
#define DMA2_CH3_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF3 | DMA_INTSTS_TXCF3 | DMA_INTSTS_HTXF3 | DMA_INTSTS_ERRF3))
|
||||
#define DMA2_CH4_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF4 | DMA_INTSTS_TXCF4 | DMA_INTSTS_HTXF4 | DMA_INTSTS_ERRF4))
|
||||
#define DMA2_CH5_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF5 | DMA_INTSTS_TXCF5 | DMA_INTSTS_HTXF5 | DMA_INTSTS_ERRF5))
|
||||
#define DMA2_CH6_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF6 | DMA_INTSTS_TXCF6 | DMA_INTSTS_HTXF6 | DMA_INTSTS_ERRF6))
|
||||
#define DMA2_CH7_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF7 | DMA_INTSTS_TXCF7 | DMA_INTSTS_HTXF7 | DMA_INTSTS_ERRF7))
|
||||
#define DMA2_CH8_INT_MASK ((uint32_t)(DMA_INTSTS_GLBF8 | DMA_INTSTS_TXCF8 | DMA_INTSTS_HTXF8 | DMA_INTSTS_ERRF8))
|
||||
|
||||
/* DMA registers Masks */
|
||||
#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DMAy Channelx registers to their default reset
|
||||
* values.
|
||||
* @param DMAyChx where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel.
|
||||
*/
|
||||
void DMA_DeInit(DMA_ChannelType* DMAyChx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAyChx));
|
||||
|
||||
/* Disable the selected DMAy Channelx */
|
||||
DMAyChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN);
|
||||
|
||||
/* Reset DMAy Channelx control register */
|
||||
DMAyChx->CHCFG = 0;
|
||||
|
||||
/* Reset DMAy Channelx remaining bytes register */
|
||||
DMAyChx->TXNUM = 0;
|
||||
|
||||
/* Reset DMAy Channelx peripheral address register */
|
||||
DMAyChx->PADDR = 0;
|
||||
|
||||
/* Reset DMAy Channelx memory address register */
|
||||
DMAyChx->MADDR = 0;
|
||||
|
||||
if (DMAyChx == DMA1_CH1)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel1 */
|
||||
DMA1->INTCLR |= DMA1_CH1_INT_MASK;
|
||||
}
|
||||
else if (DMAyChx == DMA1_CH2)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel2 */
|
||||
DMA1->INTCLR |= DMA1_CH2_INT_MASK;
|
||||
}
|
||||
else if (DMAyChx == DMA1_CH3)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel3 */
|
||||
DMA1->INTCLR |= DMA1_CH3_INT_MASK;
|
||||
}
|
||||
else if (DMAyChx == DMA1_CH4)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel4 */
|
||||
DMA1->INTCLR |= DMA1_CH4_INT_MASK;
|
||||
}
|
||||
else if (DMAyChx == DMA1_CH5)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel5 */
|
||||
DMA1->INTCLR |= DMA1_CH5_INT_MASK;
|
||||
}
|
||||
else if (DMAyChx == DMA1_CH6)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel6 */
|
||||
DMA1->INTCLR |= DMA1_CH6_INT_MASK;
|
||||
}
|
||||
else if (DMAyChx == DMA1_CH7)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel7 */
|
||||
DMA1->INTCLR |= DMA1_CH7_INT_MASK;
|
||||
}
|
||||
else if (DMAyChx == DMA1_CH8)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel8 */
|
||||
DMA1->INTCLR |= DMA1_CH8_INT_MASK;
|
||||
}
|
||||
else if (DMAyChx == DMA2_CH1)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel1 */
|
||||
DMA2->INTCLR |= DMA2_CH1_INT_MASK;
|
||||
}
|
||||
else if (DMAyChx == DMA2_CH2)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel2 */
|
||||
DMA2->INTCLR |= DMA2_CH2_INT_MASK;
|
||||
}
|
||||
else if (DMAyChx == DMA2_CH3)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel3 */
|
||||
DMA2->INTCLR |= DMA2_CH3_INT_MASK;
|
||||
}
|
||||
else if (DMAyChx == DMA2_CH4)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel4 */
|
||||
DMA2->INTCLR |= DMA2_CH4_INT_MASK;
|
||||
}
|
||||
else if (DMAyChx == DMA2_CH5)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel5 */
|
||||
DMA2->INTCLR |= DMA2_CH5_INT_MASK;
|
||||
}
|
||||
else if (DMAyChx == DMA2_CH6)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel6 */
|
||||
DMA2->INTCLR |= DMA2_CH6_INT_MASK;
|
||||
}
|
||||
else if (DMAyChx == DMA2_CH7)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel7 */
|
||||
DMA2->INTCLR |= DMA2_CH7_INT_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (DMAyChx == DMA2_CH8)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel8 */
|
||||
DMA2->INTCLR |= DMA2_CH8_INT_MASK;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DMAy Channelx according to the specified
|
||||
* parameters in the DMA_InitParam.
|
||||
* @param DMAyChx where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel.
|
||||
* @param DMA_InitParam pointer to a DMA_InitType structure that
|
||||
* contains the configuration information for the specified DMA Channel.
|
||||
*/
|
||||
void DMA_Init(DMA_ChannelType* DMAyChx, DMA_InitType* DMA_InitParam)
|
||||
{
|
||||
uint32_t tmpregister = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAyChx));
|
||||
assert_param(IS_DMA_DIR(DMA_InitParam->Direction));
|
||||
assert_param(IS_DMA_BUF_SIZE(DMA_InitParam->BufSize));
|
||||
assert_param(IS_DMA_PERIPH_INC_STATE(DMA_InitParam->PeriphInc));
|
||||
assert_param(IS_DMA_MEM_INC_STATE(DMA_InitParam->DMA_MemoryInc));
|
||||
assert_param(IS_DMA_PERIPH_DATA_SIZE(DMA_InitParam->PeriphDataSize));
|
||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitParam->MemDataSize));
|
||||
assert_param(IS_DMA_MODE(DMA_InitParam->CircularMode));
|
||||
assert_param(IS_DMA_PRIORITY(DMA_InitParam->Priority));
|
||||
assert_param(IS_DMA_M2M_STATE(DMA_InitParam->Mem2Mem));
|
||||
|
||||
/*--------------------------- DMAy Channelx CHCFG Configuration -----------------*/
|
||||
/* Get the DMAyChx CHCFG value */
|
||||
tmpregister = DMAyChx->CHCFG;
|
||||
/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
|
||||
tmpregister &= CCR_CLEAR_Mask;
|
||||
/* Configure DMAy Channelx: data transfer, data size, priority level and mode */
|
||||
/* Set DIR bit according to Direction value */
|
||||
/* Set CIRC bit according to CircularMode value */
|
||||
/* Set PINC bit according to PeriphInc value */
|
||||
/* Set MINC bit according to DMA_MemoryInc value */
|
||||
/* Set PSIZE bits according to PeriphDataSize value */
|
||||
/* Set MSIZE bits according to MemDataSize value */
|
||||
/* Set PL bits according to Priority value */
|
||||
/* Set the MEM2MEM bit according to Mem2Mem value */
|
||||
tmpregister |= DMA_InitParam->Direction | DMA_InitParam->CircularMode | DMA_InitParam->PeriphInc
|
||||
| DMA_InitParam->DMA_MemoryInc | DMA_InitParam->PeriphDataSize | DMA_InitParam->MemDataSize
|
||||
| DMA_InitParam->Priority | DMA_InitParam->Mem2Mem;
|
||||
|
||||
/* Write to DMAy Channelx CHCFG */
|
||||
DMAyChx->CHCFG = tmpregister;
|
||||
|
||||
/*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/
|
||||
/* Write to DMAy Channelx TXNUM */
|
||||
DMAyChx->TXNUM = DMA_InitParam->BufSize;
|
||||
|
||||
/*--------------------------- DMAy Channelx PADDR Configuration ----------------*/
|
||||
/* Write to DMAy Channelx PADDR */
|
||||
DMAyChx->PADDR = DMA_InitParam->PeriphAddr;
|
||||
|
||||
/*--------------------------- DMAy Channelx MADDR Configuration ----------------*/
|
||||
/* Write to DMAy Channelx MADDR */
|
||||
DMAyChx->MADDR = DMA_InitParam->MemAddr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each DMA_InitParam member with its default value.
|
||||
* @param DMA_InitParam pointer to a DMA_InitType structure which will
|
||||
* be initialized.
|
||||
*/
|
||||
void DMA_StructInit(DMA_InitType* DMA_InitParam)
|
||||
{
|
||||
/*-------------- Reset DMA init structure parameters values ------------------*/
|
||||
/* Initialize the PeriphAddr member */
|
||||
DMA_InitParam->PeriphAddr = 0;
|
||||
/* Initialize the MemAddr member */
|
||||
DMA_InitParam->MemAddr = 0;
|
||||
/* Initialize the Direction member */
|
||||
DMA_InitParam->Direction = DMA_DIR_PERIPH_SRC;
|
||||
/* Initialize the BufSize member */
|
||||
DMA_InitParam->BufSize = 0;
|
||||
/* Initialize the PeriphInc member */
|
||||
DMA_InitParam->PeriphInc = DMA_PERIPH_INC_DISABLE;
|
||||
/* Initialize the DMA_MemoryInc member */
|
||||
DMA_InitParam->DMA_MemoryInc = DMA_MEM_INC_DISABLE;
|
||||
/* Initialize the PeriphDataSize member */
|
||||
DMA_InitParam->PeriphDataSize = DMA_PERIPH_DATA_SIZE_BYTE;
|
||||
/* Initialize the MemDataSize member */
|
||||
DMA_InitParam->MemDataSize = DMA_MemoryDataSize_Byte;
|
||||
/* Initialize the CircularMode member */
|
||||
DMA_InitParam->CircularMode = DMA_MODE_NORMAL;
|
||||
/* Initialize the Priority member */
|
||||
DMA_InitParam->Priority = DMA_PRIORITY_LOW;
|
||||
/* Initialize the Mem2Mem member */
|
||||
DMA_InitParam->Mem2Mem = DMA_M2M_DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DMAy Channelx.
|
||||
* @param DMAyChx where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel.
|
||||
* @param Cmd new state of the DMAy Channelx.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void DMA_EnableChannel(DMA_ChannelType* DMAyChx, FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAyChx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
/* Enable the selected DMAy Channelx */
|
||||
DMAyChx->CHCFG |= DMA_CHCFG1_CHEN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DMAy Channelx */
|
||||
DMAyChx->CHCFG &= (uint16_t)(~DMA_CHCFG1_CHEN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DMAy Channelx interrupts.
|
||||
* @param DMAyChx where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel.
|
||||
* @param DMAInt specifies the DMA interrupts sources to be enabled
|
||||
* or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_INT_TXC Transfer complete interrupt mask
|
||||
* @arg DMA_INT_HTX Half transfer interrupt mask
|
||||
* @arg DMA_INT_ERR Transfer error interrupt mask
|
||||
* @param Cmd new state of the specified DMA interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void CMA_ConfigInt(DMA_ChannelType* DMAyChx, uint32_t DMAInt, FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAyChx));
|
||||
assert_param(IS_DMA_CONFIG_INT(DMAInt));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
/* Enable the selected DMA interrupts */
|
||||
DMAyChx->CHCFG |= DMAInt;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DMA interrupts */
|
||||
DMAyChx->CHCFG &= ~DMAInt;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the number of data units in the current DMAy Channelx transfer.
|
||||
* @param DMAyChx where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel.
|
||||
* @param DataNumber The number of data units in the current DMAy Channelx
|
||||
* transfer.
|
||||
* @note This function can only be used when the DMAyChx is disabled.
|
||||
*/
|
||||
void DMA_SetCurrDataCounter(DMA_ChannelType* DMAyChx, uint16_t DataNumber)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAyChx));
|
||||
|
||||
/*--------------------------- DMAy Channelx TXNUM Configuration ---------------*/
|
||||
/* Write to DMAy Channelx TXNUM */
|
||||
DMAyChx->TXNUM = DataNumber;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the number of remaining data units in the current
|
||||
* DMAy Channelx transfer.
|
||||
* @param DMAyChx where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel.
|
||||
* @return The number of remaining data units in the current DMAy Channelx
|
||||
* transfer.
|
||||
*/
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAyChx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAyChx));
|
||||
/* Return the number of remaining data units for DMAy Channelx */
|
||||
return ((uint16_t)(DMAyChx->TXNUM));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMAy Channelx flag is set or not.
|
||||
* @param DMAyFlag specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1_FLAG_GL1 DMA1 Channel1 global flag.
|
||||
* @arg DMA1_FLAG_TC1 DMA1 Channel1 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT1 DMA1 Channel1 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE1 DMA1 Channel1 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL2 DMA1 Channel2 global flag.
|
||||
* @arg DMA1_FLAG_TC2 DMA1 Channel2 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT2 DMA1 Channel2 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE2 DMA1 Channel2 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL3 DMA1 Channel3 global flag.
|
||||
* @arg DMA1_FLAG_TC3 DMA1 Channel3 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT3 DMA1 Channel3 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE3 DMA1 Channel3 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL4 DMA1 Channel4 global flag.
|
||||
* @arg DMA1_FLAG_TC4 DMA1 Channel4 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT4 DMA1 Channel4 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE4 DMA1 Channel4 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL5 DMA1 Channel5 global flag.
|
||||
* @arg DMA1_FLAG_TC5 DMA1 Channel5 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT5 DMA1 Channel5 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE5 DMA1 Channel5 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL6 DMA1 Channel6 global flag.
|
||||
* @arg DMA1_FLAG_TC6 DMA1 Channel6 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT6 DMA1 Channel6 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE6 DMA1 Channel6 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL7 DMA1 Channel7 global flag.
|
||||
* @arg DMA1_FLAG_TC7 DMA1 Channel7 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT7 DMA1 Channel7 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE7 DMA1 Channel7 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL8 DMA1 Channel7 global flag.
|
||||
* @arg DMA1_FLAG_TC8 DMA1 Channel7 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT8 DMA1 Channel7 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE8 DMA1 Channel7 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL1 DMA2 Channel1 global flag.
|
||||
* @arg DMA2_FLAG_TC1 DMA2 Channel1 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT1 DMA2 Channel1 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE1 DMA2 Channel1 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL2 DMA2 Channel2 global flag.
|
||||
* @arg DMA2_FLAG_TC2 DMA2 Channel2 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT2 DMA2 Channel2 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE2 DMA2 Channel2 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL3 DMA2 Channel3 global flag.
|
||||
* @arg DMA2_FLAG_TC3 DMA2 Channel3 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT3 DMA2 Channel3 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE3 DMA2 Channel3 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL4 DMA2 Channel4 global flag.
|
||||
* @arg DMA2_FLAG_TC4 DMA2 Channel4 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT4 DMA2 Channel4 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE4 DMA2 Channel4 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL5 DMA2 Channel5 global flag.
|
||||
* @arg DMA2_FLAG_TC5 DMA2 Channel5 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT5 DMA2 Channel5 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE5 DMA2 Channel5 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL6 DMA1 Channel6 global flag.
|
||||
* @arg DMA2_FLAG_TC6 DMA1 Channel6 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT6 DMA1 Channel6 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE6 DMA1 Channel6 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL7 DMA1 Channel7 global flag.
|
||||
* @arg DMA2_FLAG_TC7 DMA1 Channel7 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT7 DMA1 Channel7 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE7 DMA1 Channel7 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL8 DMA1 Channel7 global flag.
|
||||
* @arg DMA2_FLAG_TC8 DMA1 Channel7 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT8 DMA1 Channel7 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE8 DMA1 Channel7 transfer error flag.
|
||||
* @param DMAy DMA1 or DMA2.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1 .
|
||||
* @arg DMA2 .
|
||||
* @return The new state of DMAyFlag (SET or RESET).
|
||||
*/
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAyFlag, DMA_Module* DMAy)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
uint32_t tmpregister = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_GET_FLAG(DMAyFlag));
|
||||
|
||||
/* Calculate the used DMAy */
|
||||
/* Get DMAy INTSTS register value */
|
||||
tmpregister = DMAy->INTSTS;
|
||||
|
||||
/* Check the status of the specified DMAy flag */
|
||||
if ((tmpregister & DMAyFlag) != (uint32_t)RESET)
|
||||
{
|
||||
/* DMAyFlag is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMAyFlag is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
/* Return the DMAyFlag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DMAy Channelx's pending flags.
|
||||
* @param DMAyFlag specifies the flag to clear.
|
||||
* This parameter can be any combination (for the same DMA) of the following values:
|
||||
* @arg DMA1_FLAG_GL1 DMA1 Channel1 global flag.
|
||||
* @arg DMA1_FLAG_TC1 DMA1 Channel1 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT1 DMA1 Channel1 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE1 DMA1 Channel1 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL2 DMA1 Channel2 global flag.
|
||||
* @arg DMA1_FLAG_TC2 DMA1 Channel2 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT2 DMA1 Channel2 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE2 DMA1 Channel2 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL3 DMA1 Channel3 global flag.
|
||||
* @arg DMA1_FLAG_TC3 DMA1 Channel3 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT3 DMA1 Channel3 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE3 DMA1 Channel3 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL4 DMA1 Channel4 global flag.
|
||||
* @arg DMA1_FLAG_TC4 DMA1 Channel4 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT4 DMA1 Channel4 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE4 DMA1 Channel4 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL5 DMA1 Channel5 global flag.
|
||||
* @arg DMA1_FLAG_TC5 DMA1 Channel5 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT5 DMA1 Channel5 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE5 DMA1 Channel5 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL6 DMA1 Channel6 global flag.
|
||||
* @arg DMA1_FLAG_TC6 DMA1 Channel6 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT6 DMA1 Channel6 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE6 DMA1 Channel6 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL7 DMA1 Channel7 global flag.
|
||||
* @arg DMA1_FLAG_TC7 DMA1 Channel7 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT7 DMA1 Channel7 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE7 DMA1 Channel7 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL8 DMA1 Channel8 global flag.
|
||||
* @arg DMA1_FLAG_TC8 DMA1 Channel8 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT8 DMA1 Channel8 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE8 DMA1 Channel8 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL1 DMA2 Channel1 global flag.
|
||||
* @arg DMA2_FLAG_TC1 DMA2 Channel1 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT1 DMA2 Channel1 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE1 DMA2 Channel1 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL2 DMA2 Channel2 global flag.
|
||||
* @arg DMA2_FLAG_TC2 DMA2 Channel2 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT2 DMA2 Channel2 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE2 DMA2 Channel2 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL3 DMA2 Channel3 global flag.
|
||||
* @arg DMA2_FLAG_TC3 DMA2 Channel3 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT3 DMA2 Channel3 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE3 DMA2 Channel3 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL4 DMA2 Channel4 global flag.
|
||||
* @arg DMA2_FLAG_TC4 DMA2 Channel4 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT4 DMA2 Channel4 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE4 DMA2 Channel4 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL5 DMA2 Channel5 global flag.
|
||||
* @arg DMA2_FLAG_TC5 DMA2 Channel5 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT5 DMA2 Channel5 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE5 DMA2 Channel5 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL6 DMA2 Channel6 global flag.
|
||||
* @arg DMA2_FLAG_TC6 DMA2 Channel6 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT6 DMA2 Channel6 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE6 DMA2 Channel6 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL7 DMA2 Channel7 global flag.
|
||||
* @arg DMA2_FLAG_TC7 DMA2 Channel7 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT7 DMA2 Channel7 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE7 DMA2 Channel7 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL8 DMA2 Channel8 global flag.
|
||||
* @arg DMA2_FLAG_TC8 DMA2 Channel8 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT8 DMA2 Channel8 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE8 DMA2 Channel8 transfer error flag.
|
||||
* @param DMAy DMA1 or DMA2.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1 .
|
||||
* @arg DMA2 .
|
||||
*/
|
||||
void DMA_ClearFlag(uint32_t DMAyFlag, DMA_Module* DMAy)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CLEAR_FLAG(DMAyFlag));
|
||||
|
||||
/* Calculate the used DMAy */
|
||||
/* Clear the selected DMAy flags */
|
||||
DMAy->INTCLR = DMAyFlag;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
|
||||
* @param DMAy_IT specifies the DMAy interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1_INT_GLB1 DMA1 Channel1 global interrupt.
|
||||
* @arg DMA1_INT_TXC1 DMA1 Channel1 transfer complete interrupt.
|
||||
* @arg DMA1_INT_HTX1 DMA1 Channel1 half transfer interrupt.
|
||||
* @arg DMA1_INT_ERR1 DMA1 Channel1 transfer error interrupt.
|
||||
* @arg DMA1_INT_GLB2 DMA1 Channel2 global interrupt.
|
||||
* @arg DMA1_INT_TXC2 DMA1 Channel2 transfer complete interrupt.
|
||||
* @arg DMA1_INT_HTX2 DMA1 Channel2 half transfer interrupt.
|
||||
* @arg DMA1_INT_ERR2 DMA1 Channel2 transfer error interrupt.
|
||||
* @arg DMA1_INT_GLB3 DMA1 Channel3 global interrupt.
|
||||
* @arg DMA1_INT_TXC3 DMA1 Channel3 transfer complete interrupt.
|
||||
* @arg DMA1_INT_HTX3 DMA1 Channel3 half transfer interrupt.
|
||||
* @arg DMA1_INT_ERR3 DMA1 Channel3 transfer error interrupt.
|
||||
* @arg DMA1_INT_GLB4 DMA1 Channel4 global interrupt.
|
||||
* @arg DMA1_INT_TXC4 DMA1 Channel4 transfer complete interrupt.
|
||||
* @arg DMA1_INT_HTX4 DMA1 Channel4 half transfer interrupt.
|
||||
* @arg DMA1_INT_ERR4 DMA1 Channel4 transfer error interrupt.
|
||||
* @arg DMA1_INT_GLB5 DMA1 Channel5 global interrupt.
|
||||
* @arg DMA1_INT_TXC5 DMA1 Channel5 transfer complete interrupt.
|
||||
* @arg DMA1_INT_HTX5 DMA1 Channel5 half transfer interrupt.
|
||||
* @arg DMA1_INT_ERR5 DMA1 Channel5 transfer error interrupt.
|
||||
* @arg DMA1_INT_GLB6 DMA1 Channel6 global interrupt.
|
||||
* @arg DMA1_INT_TXC6 DMA1 Channel6 transfer complete interrupt.
|
||||
* @arg DMA1_INT_HTX6 DMA1 Channel6 half transfer interrupt.
|
||||
* @arg DMA1_INT_ERR6 DMA1 Channel6 transfer error interrupt.
|
||||
* @arg DMA1_INT_GLB7 DMA1 Channel7 global interrupt.
|
||||
* @arg DMA1_INT_TXC7 DMA1 Channel7 transfer complete interrupt.
|
||||
* @arg DMA1_INT_HTX7 DMA1 Channel7 half transfer interrupt.
|
||||
* @arg DMA1_INT_ERR7 DMA1 Channel7 transfer error interrupt.
|
||||
* @arg DMA1_INT_GLB8 DMA1 Channel8 global interrupt.
|
||||
* @arg DMA1_INT_TXC8 DMA1 Channel8 transfer complete interrupt.
|
||||
* @arg DMA1_INT_HTX8 DMA1 Channel8 half transfer interrupt.
|
||||
* @arg DMA1_INT_ERR8 DMA1 Channel8 transfer error interrupt.
|
||||
* @arg DMA2_INT_GLB1 DMA2 Channel1 global interrupt.
|
||||
* @arg DMA2_INT_TXC1 DMA2 Channel1 transfer complete interrupt.
|
||||
* @arg DMA2_INT_HTX1 DMA2 Channel1 half transfer interrupt.
|
||||
* @arg DMA2_INT_ERR1 DMA2 Channel1 transfer error interrupt.
|
||||
* @arg DMA2_INT_GLB2 DMA2 Channel2 global interrupt.
|
||||
* @arg DMA2_INT_TXC2 DMA2 Channel2 transfer complete interrupt.
|
||||
* @arg DMA2_INT_HTX2 DMA2 Channel2 half transfer interrupt.
|
||||
* @arg DMA2_INT_ERR2 DMA2 Channel2 transfer error interrupt.
|
||||
* @arg DMA2_INT_GLB3 DMA2 Channel3 global interrupt.
|
||||
* @arg DMA2_INT_TXC3 DMA2 Channel3 transfer complete interrupt.
|
||||
* @arg DMA2_INT_HTX3 DMA2 Channel3 half transfer interrupt.
|
||||
* @arg DMA2_INT_ERR3 DMA2 Channel3 transfer error interrupt.
|
||||
* @arg DMA2_INT_GLB4 DMA2 Channel4 global interrupt.
|
||||
* @arg DMA2_INT_TXC4 DMA2 Channel4 transfer complete interrupt.
|
||||
* @arg DMA2_INT_HTX4 DMA2 Channel4 half transfer interrupt.
|
||||
* @arg DMA2_INT_ERR4 DMA2 Channel4 transfer error interrupt.
|
||||
* @arg DMA2_INT_GLB5 DMA2 Channel5 global interrupt.
|
||||
* @arg DMA2_INT_TXC5 DMA2 Channel5 transfer complete interrupt.
|
||||
* @arg DMA2_INT_HTX5 DMA2 Channel5 half transfer interrupt.
|
||||
* @arg DMA2_INT_ERR5 DMA2 Channel5 transfer error interrupt.
|
||||
* @arg DMA2_INT_GLB6 DMA2 Channel6 global interrupt.
|
||||
* @arg DMA2_INT_TXC6 DMA2 Channel6 transfer complete interrupt.
|
||||
* @arg DMA2_INT_HTX6 DMA2 Channel6 half transfer interrupt.
|
||||
* @arg DMA2_INT_ERR6 DMA2 Channel6 transfer error interrupt.
|
||||
* @arg DMA2_INT_GLB7 DMA2 Channel7 global interrupt.
|
||||
* @arg DMA2_INT_TXC7 DMA2 Channel7 transfer complete interrupt.
|
||||
* @arg DMA2_INT_HTX7 DMA2 Channel7 half transfer interrupt.
|
||||
* @arg DMA2_INT_ERR7 DMA2 Channel7 transfer error interrupt.
|
||||
* @arg DMA2_INT_GLB8 DMA2 Channel8 global interrupt.
|
||||
* @arg DMA2_INT_TXC8 DMA2 Channel8 transfer complete interrupt.
|
||||
* @arg DMA2_INT_HTX8 DMA2 Channel8 half transfer interrupt.
|
||||
* @arg DMA2_INT_ERR8 DMA2 Channel8 transfer error interrupt.
|
||||
* @param DMAy DMA1 or DMA2.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1 .
|
||||
* @arg DMA2 .
|
||||
* @return The new state of DMAy_IT (SET or RESET).
|
||||
*/
|
||||
INTStatus DMA_GetIntStatus(uint32_t DMAy_IT, DMA_Module* DMAy)
|
||||
{
|
||||
INTStatus bitstatus = RESET;
|
||||
uint32_t tmpregister = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_GET_IT(DMAy_IT));
|
||||
|
||||
/* Calculate the used DMA */
|
||||
/* Get DMAy INTSTS register value */
|
||||
tmpregister = DMAy->INTSTS;
|
||||
|
||||
/* Check the status of the specified DMAy interrupt */
|
||||
if ((tmpregister & DMAy_IT) != (uint32_t)RESET)
|
||||
{
|
||||
/* DMAy_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMAy_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DMAInt status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DMAy Channelx's interrupt pending bits.
|
||||
* @param DMAy_IT specifies the DMAy interrupt pending bit to clear.
|
||||
* This parameter can be any combination (for the same DMA) of the following values:
|
||||
* @arg DMA1_INT_GLB1 DMA1 Channel1 global interrupt.
|
||||
* @arg DMA1_INT_TXC1 DMA1 Channel1 transfer complete interrupt.
|
||||
* @arg DMA1_INT_HTX1 DMA1 Channel1 half transfer interrupt.
|
||||
* @arg DMA1_INT_ERR1 DMA1 Channel1 transfer error interrupt.
|
||||
* @arg DMA1_INT_GLB2 DMA1 Channel2 global interrupt.
|
||||
* @arg DMA1_INT_TXC2 DMA1 Channel2 transfer complete interrupt.
|
||||
* @arg DMA1_INT_HTX2 DMA1 Channel2 half transfer interrupt.
|
||||
* @arg DMA1_INT_ERR2 DMA1 Channel2 transfer error interrupt.
|
||||
* @arg DMA1_INT_GLB3 DMA1 Channel3 global interrupt.
|
||||
* @arg DMA1_INT_TXC3 DMA1 Channel3 transfer complete interrupt.
|
||||
* @arg DMA1_INT_HTX3 DMA1 Channel3 half transfer interrupt.
|
||||
* @arg DMA1_INT_ERR3 DMA1 Channel3 transfer error interrupt.
|
||||
* @arg DMA1_INT_GLB4 DMA1 Channel4 global interrupt.
|
||||
* @arg DMA1_INT_TXC4 DMA1 Channel4 transfer complete interrupt.
|
||||
* @arg DMA1_INT_HTX4 DMA1 Channel4 half transfer interrupt.
|
||||
* @arg DMA1_INT_ERR4 DMA1 Channel4 transfer error interrupt.
|
||||
* @arg DMA1_INT_GLB5 DMA1 Channel5 global interrupt.
|
||||
* @arg DMA1_INT_TXC5 DMA1 Channel5 transfer complete interrupt.
|
||||
* @arg DMA1_INT_HTX5 DMA1 Channel5 half transfer interrupt.
|
||||
* @arg DMA1_INT_ERR5 DMA1 Channel5 transfer error interrupt.
|
||||
* @arg DMA1_INT_GLB6 DMA1 Channel6 global interrupt.
|
||||
* @arg DMA1_INT_TXC6 DMA1 Channel6 transfer complete interrupt.
|
||||
* @arg DMA1_INT_HTX6 DMA1 Channel6 half transfer interrupt.
|
||||
* @arg DMA1_INT_ERR6 DMA1 Channel6 transfer error interrupt.
|
||||
* @arg DMA1_INT_GLB7 DMA1 Channel7 global interrupt.
|
||||
* @arg DMA1_INT_TXC7 DMA1 Channel7 transfer complete interrupt.
|
||||
* @arg DMA1_INT_HTX7 DMA1 Channel7 half transfer interrupt.
|
||||
* @arg DMA1_INT_ERR7 DMA1 Channel7 transfer error interrupt.
|
||||
* @arg DMA1_INT_GLB8 DMA1 Channel8 global interrupt.
|
||||
* @arg DMA1_INT_TXC8 DMA1 Channel8 transfer complete interrupt.
|
||||
* @arg DMA1_INT_HTX8 DMA1 Channel8 half transfer interrupt.
|
||||
* @arg DMA1_INT_ERR8 DMA1 Channel8 transfer error interrupt.
|
||||
* @arg DMA2_INT_GLB1 DMA2 Channel1 global interrupt.
|
||||
* @arg DMA2_INT_TXC1 DMA2 Channel1 transfer complete interrupt.
|
||||
* @arg DMA2_INT_HTX1 DMA2 Channel1 half transfer interrupt.
|
||||
* @arg DMA2_INT_ERR1 DMA2 Channel1 transfer error interrupt.
|
||||
* @arg DMA2_INT_GLB2 DMA2 Channel2 global interrupt.
|
||||
* @arg DMA2_INT_TXC2 DMA2 Channel2 transfer complete interrupt.
|
||||
* @arg DMA2_INT_HTX2 DMA2 Channel2 half transfer interrupt.
|
||||
* @arg DMA2_INT_ERR2 DMA2 Channel2 transfer error interrupt.
|
||||
* @arg DMA2_INT_GLB3 DMA2 Channel3 global interrupt.
|
||||
* @arg DMA2_INT_TXC3 DMA2 Channel3 transfer complete interrupt.
|
||||
* @arg DMA2_INT_HTX3 DMA2 Channel3 half transfer interrupt.
|
||||
* @arg DMA2_INT_ERR3 DMA2 Channel3 transfer error interrupt.
|
||||
* @arg DMA2_INT_GLB4 DMA2 Channel4 global interrupt.
|
||||
* @arg DMA2_INT_TXC4 DMA2 Channel4 transfer complete interrupt.
|
||||
* @arg DMA2_INT_HTX4 DMA2 Channel4 half transfer interrupt.
|
||||
* @arg DMA2_INT_ERR4 DMA2 Channel4 transfer error interrupt.
|
||||
* @arg DMA2_INT_GLB5 DMA2 Channel5 global interrupt.
|
||||
* @arg DMA2_INT_TXC5 DMA2 Channel5 transfer complete interrupt.
|
||||
* @arg DMA2_INT_HTX5 DMA2 Channel5 half transfer interrupt.
|
||||
* @arg DMA2_INT_ERR5 DMA2 Channel5 transfer error interrupt.
|
||||
* @arg DMA2_INT_GLB6 DMA2 Channel6 global interrupt.
|
||||
* @arg DMA2_INT_TXC6 DMA2 Channel6 transfer complete interrupt.
|
||||
* @arg DMA2_INT_HTX6 DMA2 Channel6 half transfer interrupt.
|
||||
* @arg DMA2_INT_ERR6 DMA2 Channel6 transfer error interrupt.
|
||||
* @arg DMA2_INT_GLB7 DMA2 Channel7 global interrupt.
|
||||
* @arg DMA2_INT_TXC7 DMA2 Channel7 transfer complete interrupt.
|
||||
* @arg DMA2_INT_HTX7 DMA2 Channel7 half transfer interrupt.
|
||||
* @arg DMA2_INT_ERR7 DMA2 Channel7 transfer error interrupt.
|
||||
* @arg DMA2_INT_GLB8 DMA2 Channel8 global interrupt.
|
||||
* @arg DMA2_INT_TXC8 DMA2 Channel8 transfer complete interrupt.
|
||||
* @arg DMA2_INT_HTX8 DMA2 Channel8 half transfer interrupt.
|
||||
* @arg DMA2_INT_ERR8 DMA2 Channel8 transfer error interrupt.
|
||||
* @param DMAy DMA1 or DMA2.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1 .
|
||||
* @arg DMA2 .
|
||||
*/
|
||||
void DMA_ClrIntPendingBit(uint32_t DMAy_IT, DMA_Module* DMAy)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CLR_INT(DMAy_IT));
|
||||
|
||||
/* Calculate the used DMAy */
|
||||
/* Clear the selected DMAy interrupt pending bits */
|
||||
DMAy->INTCLR = DMAy_IT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the DMAy Channelx's remap request.
|
||||
* @param DMAy_REMAP specifies the DMAy request.
|
||||
* This parameter can be set by the following values:
|
||||
* @arg DMA1_REMAP_ADC1 DMA1 Request For ADC1.
|
||||
* @arg DMA1_REMAP_UART5_TX DMA1 Request For UART5_TX.
|
||||
* @arg DMA1_REMAP_I2C3_TX DMA1 Request For I2C3_TX.
|
||||
* @arg DMA1_REMAP_TIM2_CH3 DMA1 Request For TIM2_CH3.
|
||||
* @arg DMA1_REMAP_TIM4_CH1 DMA1 Request For TIM4_CH1.
|
||||
* @arg DMA1_REMAP_USART3_TX DMA1 Request For USART3_TX.
|
||||
* @arg DMA1_REMAP_I2C3_RX DMA1 Request For I2C3_RX.
|
||||
* @arg DMA1_REMAP_TIM1_CH1 DMA1 Request For TIM1_CH1.
|
||||
* @arg DMA1_REMAP_TIM2_UP DMA1 Request For TIM2_UP.
|
||||
* @arg DMA1_REMAP_TIM3_CH3 DMA1 Request For TIM3_CH3.
|
||||
* @arg DMA1_REMAP_SPI1_RX DMA1 Request For SPI1_RX.
|
||||
* @arg DMA1_REMAP_USART3_RX DMA1 Request For USART3_RX.
|
||||
* @arg DMA1_REMAP_TIM1_CH2 DMA1 Request For TIM1_CH2.
|
||||
* @arg DMA1_REMAP_TIM3_CH4 DMA1 Request For TIM3_CH4.
|
||||
* @arg DMA1_REMAP_TIM3_UP DMA1 Request For TIM3_UP.
|
||||
* @arg DMA1_REMAP_SPI1_TX DMA1 Request For SPI1_TX.
|
||||
* @arg DMA1_REMAP_USART1_TX DMA1 Request For USART1_TX.
|
||||
* @arg DMA1_REMAP_TIM1_CH4 DMA1 Request For TIM1_CH4.
|
||||
* @arg DMA1_REMAP_TIM1_TRIG DMA1 Request For TIM1_TRIG.
|
||||
* @arg DMA1_REMAP_TIM1_COM DMA1 Request For TIM1_COM.
|
||||
* @arg DMA1_REMAP_TIM4_CH2 DMA1 Request For TIM4_CH2.
|
||||
* @arg DMA1_REMAP_SPI_I2S2_RX DMA1 Request For SPI_I2S2_RX.
|
||||
* @arg DMA1_REMAP_I2C2_TX DMA1 Request For I2C2_TX.
|
||||
* @arg DMA1_REMAP_USART1_RX DMA1 Request For USART1_RX.
|
||||
* @arg DMA1_REMAP_TIM1_UP DMA1 Request For TIM1_UP.
|
||||
* @arg DMA1_REMAP_SPI_I2S2_TX DMA1 Request For SPI_I2S2_TX.
|
||||
* @arg DMA1_REMAP_TIM4_CH3 DMA1 Request For TIM4_CH3.
|
||||
* @arg DMA1_REMAP_I2C2_RX DMA1 Request For I2C2_RX.
|
||||
* @arg DMA1_REMAP_TIM2_CH1 DMA1 Request For TIM2_CH1.
|
||||
* @arg DMA1_REMAP_USART2_RX DMA1 Request For USART2_RX.
|
||||
* @arg DMA1_REMAP_TIM1_CH3 DMA1 Request For TIM1_CH3.
|
||||
* @arg DMA1_REMAP_TIM3_CH1 DMA1 Request For TIM3_CH1.
|
||||
* @arg DMA1_REMAP_TIM3_TRIG DMA1 Request For TIM3_TRIG.
|
||||
* @arg DMA1_REMAP_I2C1_TX DMA1 Request For I2C1_TX.
|
||||
* @arg DMA1_REMAP_USART2_TX DMA1 Request For USART2_TX.
|
||||
* @arg DMA1_REMAP_TIM2_CH2 DMA1 Request For TIM2_CH2.
|
||||
* @arg DMA1_REMAP_TIM2_CH4 DMA1 Request For TIM2_CH4.
|
||||
* @arg DMA1_REMAP_TIM4_UP DMA1 Request For TIM4_UP.
|
||||
* @arg DMA1_REMAP_I2C1_RX DMA1 Request For I2C1_RX.
|
||||
* @arg DMA1_REMAP_ADC2 DMA1 Request For ADC2.
|
||||
* @arg DMA1_REMAP_UART5_RX DMA1 Request For UART5_RX.
|
||||
* @arg DMA2_REMAP_TIM5_CH4 DMA2 Request For TIM5_CH4.
|
||||
* @arg DMA2_REMAP_TIM5_TRIG DMA2 Request For TIM5_TRIG.
|
||||
* @arg DMA2_REMAP_TIM8_CH3 DMA2 Request For TIM8_CH3.
|
||||
* @arg DMA2_REMAP_TIM8_UP DMA2 Request For TIM8_UP.
|
||||
* @arg DMA2_REMAP_SPI_I2S3_RX DMA2 Request For SPI_I2S3_RX.
|
||||
* @arg DMA2_REMAP_UART6_RX DMA2 Request For UART6_RX.
|
||||
* @arg DMA2_REMAP_TIM8_CH4 DMA2 Request For TIM8_CH4.
|
||||
* @arg DMA2_REMAP_TIM8_TRIG DMA2 Request For TIM8_TRIG.
|
||||
* @arg DMA2_REMAP_TIM8_COM DMA2 Request For TIM8_COM.
|
||||
* @arg DMA2_REMAP_TIM5_CH3 DMA2 Request For TIM5_CH3.
|
||||
* @arg DMA2_REMAP_TIM5_UP DMA2 Request For TIM5_UP.
|
||||
* @arg DMA2_REMAP_SPI_I2S3_TX DMA2 Request For SPI_I2S3_TX.
|
||||
* @arg DMA2_REMAP_UART6_TX DMA2 Request For UART6_TX.
|
||||
* @arg DMA2_REMAP_TIM8_CH1 DMA2 Request For TIM8_CH1.
|
||||
* @arg DMA2_REMAP_UART4_RX DMA2 Request For UART4_RX.
|
||||
* @arg DMA2_REMAP_TIM6_UP DMA2 Request For TIM6_UP.
|
||||
* @arg DMA2_REMAP_DAC1 DMA2 Request For DAC1.
|
||||
* @arg DMA2_REMAP_TIM5_CH2 DMA2 Request For TIM5_CH2.
|
||||
* @arg DMA2_REMAP_SDIO DMA2 Request For SDIO.
|
||||
* @arg DMA2_REMAP_TIM7_UP DMA2 Request For TIM7_UP.
|
||||
* @arg DMA2_REMAP_DAC2 DMA2 Request For DAC2.
|
||||
* @arg DMA2_REMAP_ADC3 DMA2 Request For ADC3.
|
||||
* @arg DMA2_REMAP_TIM8_CH2 DMA2 Request For TIM8_CH2.
|
||||
* @arg DMA2_REMAP_TIM5_CH1 DMA2 Request For TIM5_CH1.
|
||||
* @arg DMA2_REMAP_UART4_TX DMA2 Request For UART4_TX.
|
||||
* @arg DMA2_REMAP_QSPI_RX DMA2 Request For QSPI_RX.
|
||||
* @arg DMA2_REMAP_I2C4_TX DMA2 Request For I2C4_TX.
|
||||
* @arg DMA2_REMAP_UART7_RX DMA2 Request For UART7_RX.
|
||||
* @arg DMA2_REMAP_QSPI_TX DMA2 Request For QSPI_TX.
|
||||
* @arg DMA2_REMAP_I2C4_RX DMA2 Request For I2C4_RX.
|
||||
* @arg DMA2_REMAP_UART7_TX DMA2 Request For UART7_TX.
|
||||
* @arg DMA2_REMAP_ADC4 DMA2 Request For ADC4.
|
||||
* @arg DMA2_REMAP_DVP DMA2 Request For DVP.
|
||||
* @param DMAy DMA1 or DMA2.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1 .
|
||||
* @arg DMA2 .
|
||||
* @param DMAyChx where y can be 1 or 2 to select the DMA and
|
||||
* x can be 1 to 8 for DMA1 and 1 to 8 for DMA2 to select the DMA Channel.
|
||||
* @param Cmd new state of the DMAy Channelx.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void DMA_RequestRemap(uint32_t DMAy_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAyChx, FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_REMAP(DMAy_REMAP));
|
||||
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
/* Calculate the used DMAy */
|
||||
/* Set the selected DMAy remap request */
|
||||
DMAyChx->CHSEL = DMAy_REMAP;
|
||||
DMAy->CHMAPEN = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
DMAy->CHMAPEN = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,384 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_dvp.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x_dvp.h"
|
||||
#include "n32g45x_rcc.h"
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DVPx peripheral registers to their default reset values.
|
||||
* @param DVPx Select the DVP peripheral.
|
||||
* This parameter can be one of the following values:
|
||||
* DVP
|
||||
*/
|
||||
void DVP_DeInit(DVP_Module* DVPx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DVP_ALL_PERIPH(DVPx));
|
||||
|
||||
if (DVPx == DVP)
|
||||
{
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_DVP, ENABLE);
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_DVP, DISABLE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DVP flag is set or not.
|
||||
* @param DVPx Select the DVP peripheral.
|
||||
* This parameter can be one of the following values:
|
||||
* DVP
|
||||
* @param DVP_FLAG specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DVP_FLAG_HERR Hsync error interrupt flag
|
||||
* @arg DVP_FLAG_VERR Vsync error interrupt flag
|
||||
* @arg DVP_FLAG_FO DATFIFO overflow intterrupt flag
|
||||
* @arg DVP_FLAG_FW DATFIFO watermark interrupt flag
|
||||
* @arg DVP_FLAG_FF DATFIFO full interrupt flag
|
||||
* @arg DVP_FLAG_FE DATFIFO empty interrupt flag
|
||||
* @arg DVP_FLAG_LE Line end interrupt flag
|
||||
* @arg DVP_FLAG_LS Line start interrupt flag
|
||||
* @arg DVP_FLAG_FME Frame end interrupt flag
|
||||
* @arg DVP_FLAG_FMS Frame start interrupt flag
|
||||
* @return The new state of DVP_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DVP_GetFlagStatus(DVP_Module* DVPx, uint16_t DVP_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DVP_ALL_PERIPH(DVPx));
|
||||
assert_param(IS_DVP_FLAG(DVP_FLAG));
|
||||
|
||||
if ((DVPx->INTSTS & DVP_FLAG) != (uint16_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DVPx's pending flags.
|
||||
* @param DVPx Select the DVP peripheral.
|
||||
* This parameter can be one of the following values:
|
||||
* DVP
|
||||
* @param DVP_FLAG specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DVP_FLAG_HERR Hsync error interrupt flag
|
||||
* @arg DVP_FLAG_VERR Vsync error interrupt flag
|
||||
* @arg DVP_FLAG_FO DATFIFO overflow intterrupt flag
|
||||
* @arg DVP_FLAG_FE DATFIFO empty interrupt flag
|
||||
* @arg DVP_FLAG_LE Line end interrupt flag
|
||||
* @arg DVP_FLAG_LS Line start interrupt flag
|
||||
* @arg DVP_FLAG_FME Frame end interrupt flag
|
||||
* @arg DVP_FLAG_FMS Frame start interrupt flag
|
||||
*/
|
||||
void DVP_ClrFlag(DVP_Module* DVPx, uint16_t DVP_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DVP_ALL_PERIPH(DVPx));
|
||||
assert_param(IS_DVP_CLEAR_FLAG(DVP_FLAG));
|
||||
|
||||
DVPx->INTSTS = (uint16_t)~DVP_FLAG;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DVP interrupt has occurred or not.
|
||||
* @param DVPx Select the DVP peripheral.
|
||||
* This parameter can be one of the following values:
|
||||
* DVP
|
||||
* @param DVP_IT specifies the DVP interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DVP_INT_HERR Hsync error interrupt
|
||||
* @arg DVP_INT_VERR Vsync error interrupt
|
||||
* @arg DVP_INT_FO DATFIFO overflow intterrupt
|
||||
* @arg DVP_INT_FW DATFIFO watermark interrupt
|
||||
* @arg DVP_INT_FF DATFIFO full interrupt
|
||||
* @arg DVP_INT_FE DATFIFO empty interrupt
|
||||
* @arg DVP_INT_LE Line end interrupt
|
||||
* @arg DVP_INT_LS Line start interrupt
|
||||
* @arg DVP_INT_FME Frame end interrupt
|
||||
* @arg DVP_INT_FMS Frame start interrupt
|
||||
* @return The new state of DVP_IT (SET or RESET).
|
||||
*/
|
||||
INTStatus DVP_GetIntStatus(DVP_Module* DVPx, uint16_t DVP_IT)
|
||||
{
|
||||
uint32_t bitpos = 0x00, itmask = 0x00;
|
||||
INTStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DVP_ALL_PERIPH(DVPx));
|
||||
assert_param(IS_DVP_INT(DVP_IT));
|
||||
|
||||
/* Get the interrupt position */
|
||||
itmask = DVP_IT & DVPx->INTEN;
|
||||
bitpos = DVP_IT & DVPx->INTSTS;
|
||||
if ((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DVP interrupt has occurred or not.
|
||||
* @param DVPx Select the DVP peripheral.
|
||||
* This parameter can be one of the following values:
|
||||
* DVP
|
||||
* @param DVP_IT specifies the DVP interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DVP_MINT_HERR Hsync error interrupt
|
||||
* @arg DVP_MINT_VERR Vsync error interrupt
|
||||
* @arg DVP_MINT_FO DATFIFO overflow intterrupt
|
||||
* @arg DVP_MINT_FW DATFIFO watermark interrupt
|
||||
* @arg DVP_MINT_FF DATFIFO full interrupt
|
||||
* @arg DVP_MINT_FE DATFIFO empty interrupt
|
||||
* @arg DVP_MINT_LE Line end interrupt
|
||||
* @arg DVP_MINT_LS Line start interrupt
|
||||
* @arg DVP_MINT_FME Frame end interrupt
|
||||
* @arg DVP_MINT_FMS Frame start interrupt
|
||||
* @return The new state of DVP_IT (SET or RESET).
|
||||
*/
|
||||
INTStatus DVP_GetITMarkedStatus(DVP_Module* DVPx, uint16_t DVP_IT)
|
||||
{
|
||||
uint32_t itmask = 0x00;
|
||||
INTStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DVP_ALL_PERIPH(DVPx));
|
||||
assert_param(IS_DVP_INT(DVP_IT));
|
||||
|
||||
/* Get the interrupt position */
|
||||
itmask = DVP_IT & DVPx->MINTSTS;
|
||||
if (itmask != (uint16_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DVPx peripheral according to the specified
|
||||
* parameters in the DVP_InitStruct .
|
||||
* @param DVPx Select the DVP or the UART peripheral.
|
||||
* This parameter can be one of the following values:
|
||||
* DVP, DVP2, DVP3, UART4 or UART5.
|
||||
* @param DVP_InitStruct pointer to a DVP_InitType structure
|
||||
* that contains the configuration information for the specified DVP
|
||||
* peripheral.
|
||||
*/
|
||||
void DVP_Init(DVP_Module* DVPx, DVP_InitType* DVP_InitStruct)
|
||||
{
|
||||
uint32_t tmpregister = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DVP_ALL_PERIPH(DVPx));
|
||||
assert_param(IS_DVP_ROW_CAPTURE(DVP_InitStruct->LineCapture));
|
||||
assert_param(IS_DVP_COLUMN_CAPTURE(DVP_InitStruct->ByteCapture));
|
||||
assert_param(IS_DVP_DATA_INVERT(DVP_InitStruct->DataInvert));
|
||||
assert_param(IS_DVP_PIXEL_POLARITY(DVP_InitStruct->PixelClkPolarity));
|
||||
assert_param(IS_DVP_VSYNC_POLARITY(DVP_InitStruct->VsyncPolarity));
|
||||
assert_param(IS_DVP_HSYNC_POLARITY(DVP_InitStruct->HsyncPolarity));
|
||||
assert_param(IS_DVP_CAPTURE_MODE(DVP_InitStruct->CaptureMode));
|
||||
assert_param(IS_DVP_FIFOWATERMARK(DVP_InitStruct->FifoWatermark));
|
||||
|
||||
/*---------------------------- DVP CTRL Configuration -----------------------*/
|
||||
tmpregister = DVPx->CTRL;
|
||||
tmpregister &= 0x0FFE;
|
||||
|
||||
tmpregister |= DVP_InitStruct->LineCapture | DVP_InitStruct->ByteCapture | DVP_InitStruct->DataInvert
|
||||
| DVP_InitStruct->PixelClkPolarity | DVP_InitStruct->VsyncPolarity | DVP_InitStruct->HsyncPolarity
|
||||
| DVP_InitStruct->CaptureMode | (DVP_InitStruct->FifoWatermark << DVP_WATER_MARK_POS);
|
||||
DVPx->CTRL = tmpregister;
|
||||
|
||||
/*---------------------------- DVP WST Configuration -----------------------*/
|
||||
if (DVP_InitStruct->RowStart == 0x0000)
|
||||
DVP_InitStruct->RowStart = 0x0001;
|
||||
if (DVP_InitStruct->ColumnStart == 0x0000)
|
||||
DVP_InitStruct->ColumnStart = 0x0001;
|
||||
DVPx->WST = ((DVP_InitStruct->RowStart - 1) << 13) | (DVP_InitStruct->ColumnStart - 1);
|
||||
|
||||
/*---------------------------- DVP WSIZE Configuration -----------------------*/
|
||||
|
||||
DVPx->WSIZE = ((DVP_InitStruct->ImageHeight - 1) << 13) | (DVP_InitStruct->ImageWidth - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each DVP_InitStruct member with its default value.
|
||||
* @param DVP_InitStruct pointer to a DVP_InitType structure
|
||||
* which will be initialized.
|
||||
*/
|
||||
void DVP_InitStruct(DVP_InitType* DVP_InitStruct)
|
||||
{
|
||||
/* DVP_InitStruct members default value */
|
||||
DVP_InitStruct->LineCapture = DVP_LINE_CAPTURE_ALL;
|
||||
DVP_InitStruct->ByteCapture = DVP_BYTE_CAPTURE_ALL;
|
||||
DVP_InitStruct->DataInvert = DVP_DATA_NOTINVERT;
|
||||
DVP_InitStruct->PixelClkPolarity = DVP_PIXEL_POLARITY_RISING;
|
||||
DVP_InitStruct->VsyncPolarity = DVP_VSYNC_POLARITY_HIGH;
|
||||
DVP_InitStruct->HsyncPolarity = DVP_HSYNC_POLARITY_HIGH;
|
||||
DVP_InitStruct->CaptureMode = DVP_CAPTURE_MODE_SINGLE;
|
||||
DVP_InitStruct->RowStart = 0;
|
||||
DVP_InitStruct->ColumnStart = 0;
|
||||
DVP_InitStruct->ImageHeight = 480;
|
||||
DVP_InitStruct->ImageWidth = 640;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the DVP interface.
|
||||
* @param DVPx Select the DVP peripheral.
|
||||
* This parameter can be one of the following values:
|
||||
* DVP
|
||||
* @param Cmd new state of the DMA Request sources.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void DVP_Enable(DVP_Module* DVPx, FunctionalState Cmd)
|
||||
{
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
DVPx->CTRL |= DVP_CAPTURE_ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
DVPx->CTRL &= (uint32_t)~DVP_CAPTURE_ENABLE;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the DVP DMA interface.
|
||||
* @param DVPx Select the DVP peripheral.
|
||||
* This parameter can be one of the following values:
|
||||
* DVP
|
||||
* @param Cmd new state of the DMA Request sources.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void DVP_EnableDma(DVP_Module* DVPx, FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DVP_ALL_PERIPH(DVPx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
DVPx->INTEN |= DVP_DMA_ENABLE;
|
||||
|
||||
/* When DMA is enable, the FWM in CTRL1 should be set 1*/
|
||||
DVPx->CTRL &= ~DVP_WATER_MARK_MASK;
|
||||
DVPx->CTRL |= (1 << DVP_WATER_MARK_POS);
|
||||
}
|
||||
else
|
||||
{
|
||||
DVPx->INTEN &= (uint32_t)~DVP_DMA_ENABLE;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the DVP interface.
|
||||
* @param DVPx Select the DVP peripheral.
|
||||
* This parameter can be one of the following values:
|
||||
* DVP
|
||||
* @param Watermark must be 1,2,3,4.
|
||||
*/
|
||||
void DVP_SetFifoWatermark(DVP_Module* DVPx, uint16_t Watermark)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DVP_ALL_PERIPH(DVPx));
|
||||
|
||||
DVPx->CTRL &= ~DVP_WATER_MARK_MASK;
|
||||
DVPx->CTRL |= Watermark << DVP_WATER_MARK_POS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the DVP interface.
|
||||
* @param DVPx Select the DVP peripheral.
|
||||
* This parameter can be one of the following values:
|
||||
* DVP
|
||||
*/
|
||||
uint32_t DVP_GetFifoCount(DVP_Module* DVPx)
|
||||
{
|
||||
uint32_t tempty = 0, tnums = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DVP_ALL_PERIPH(DVPx));
|
||||
|
||||
tempty = DVPx->STS & 0x0001;
|
||||
if (tempty == 0x0000)
|
||||
return 0x0000;
|
||||
else
|
||||
{
|
||||
tnums = (DVPx->STS & 0x001E) >> 1;
|
||||
return (tnums);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the DVP interface.
|
||||
* @param DVPx Select the DVP peripheral.
|
||||
* This parameter can be one of the following values:
|
||||
* DVP
|
||||
* @return Data in DATFIFO
|
||||
*/
|
||||
uint32_t DVP_ReadFifo(DVP_Module* DVPx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DVP_ALL_PERIPH(DVPx));
|
||||
|
||||
return DVPx->DATFIFO;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Software Reset DATFIFO
|
||||
*
|
||||
* @param DVPx Select the DVP peripheral.
|
||||
* This parameter can be one of the following values:
|
||||
* DVP
|
||||
*/
|
||||
void DVP_ResetFifo(DVP_Module* DVPx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DVP_ALL_PERIPH(DVPx));
|
||||
|
||||
DVP->CTRL |= DVP_FIFO_SOFT_RESET;
|
||||
while (DVP->CTRL & DVP_FIFO_SOFT_RESET)
|
||||
;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,286 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_exti.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x_exti.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @brief EXTI driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the EXTI peripheral registers to their default reset values.
|
||||
*/
|
||||
void EXTI_DeInit(void)
|
||||
{
|
||||
EXTI->IMASK = 0x00000000;
|
||||
EXTI->EMASK = 0x00000000;
|
||||
EXTI->RT_CFG = 0x00000000;
|
||||
EXTI->FT_CFG = 0x00000000;
|
||||
EXTI->PEND = 0x000FFFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the EXTI peripheral according to the specified
|
||||
* parameters in the EXTI_InitStruct.
|
||||
* @param EXTI_InitStruct pointer to a EXTI_InitType structure
|
||||
* that contains the configuration information for the EXTI peripheral.
|
||||
*/
|
||||
void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
|
||||
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
|
||||
assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
|
||||
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
|
||||
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
|
||||
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
|
||||
{
|
||||
/* Clear EXTI line configuration */
|
||||
EXTI->IMASK &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->EMASK &= ~EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
|
||||
*(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->RT_CFG &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FT_CFG &= ~EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
/* Select the trigger for the selected external interrupts */
|
||||
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
|
||||
{
|
||||
/* Rising Falling edge */
|
||||
EXTI->RT_CFG |= EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FT_CFG |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
tmp += EXTI_InitStruct->EXTI_Trigger;
|
||||
|
||||
*(__IO uint32_t*)tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
|
||||
/* Disable the selected external lines */
|
||||
*(__IO uint32_t*)tmp &= ~EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each EXTI_InitStruct member with its reset value.
|
||||
* @param EXTI_InitStruct pointer to a EXTI_InitType structure which will
|
||||
* be initialized.
|
||||
*/
|
||||
void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct)
|
||||
{
|
||||
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
|
||||
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
|
||||
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
|
||||
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt.
|
||||
* @param EXTI_Line specifies the EXTI lines to be enabled or disabled.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
|
||||
*/
|
||||
void EXTI_TriggerSWInt(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->SWIE |= EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
* @param EXTI_Line specifies the EXTI line flag to check.
|
||||
* This parameter can be:
|
||||
* @arg EXTI_Linex External interrupt line x where x(0..19)
|
||||
* @return The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||
|
||||
if ((EXTI->PEND & EXTI_Line) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
* @param EXTI_Line specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
|
||||
*/
|
||||
void EXTI_ClrStatusFlag(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->PEND = EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
* @param EXTI_Line specifies the EXTI line to check.
|
||||
* This parameter can be:
|
||||
* @arg EXTI_Linex External interrupt line x where x(0..19)
|
||||
* @return The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
INTStatus EXTI_GetITStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
INTStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||
|
||||
enablestatus = EXTI->IMASK & EXTI_Line;
|
||||
if (((EXTI->PEND & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
* @param EXTI_Line specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..19).
|
||||
*/
|
||||
void EXTI_ClrITPendBit(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->PEND = EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select one of EXTI inputs to the RTC TimeStamp event.
|
||||
* @param EXTI_TSSEL_Line specifies the EXTI lines to select.
|
||||
* This parameter can be any combination of EXTI_TSSEL_Line where x can be (0..15).
|
||||
*/
|
||||
void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_TSSEL_LINE(EXTI_TSSEL_Line));
|
||||
|
||||
EXTI->TSSEL &= EXTI_TSSEL_LINE_MASK;
|
||||
EXTI->TSSEL |= EXTI_TSSEL_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,870 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_gpio.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x_gpio.h"
|
||||
#include "n32g45x_rcc.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @brief GPIO driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ------------ RCC registers bit address in the alias region ----------------*/
|
||||
#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- Event control register -----*/
|
||||
|
||||
/* Alias word address of EVOE bit */
|
||||
#define EVCR_OFFSET (AFIO_OFFSET + 0x00)
|
||||
#define EVOE_BitNumber ((uint8_t)0x07)
|
||||
#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))
|
||||
|
||||
/* --- RMP_CFG Register ---*/
|
||||
/* Alias word address of MII_RMII_SEL bit */
|
||||
#define MAPR_OFFSET (AFIO_OFFSET + 0x04)
|
||||
#define MII_RMII_SEL_BitNumber ((u8)0x17)
|
||||
#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
|
||||
|
||||
#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
|
||||
#define LSB_MASK ((uint16_t)0xFFFF)
|
||||
#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
|
||||
#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
|
||||
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
|
||||
#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
|
||||
#define DBGAFR_NUMBITS_MAPR3_MASK ((uint32_t)0x40000000)
|
||||
#define DBGAFR_NUMBITS_MAPR4_MASK ((uint32_t)0x20000000)
|
||||
#define DBGAFR_NUMBITS_MAPR5_MASK ((uint32_t)0x10000000)
|
||||
#define DBGAFR_NUMBITS_SPI1_MASK ((uint32_t)0x01000000)
|
||||
#define DBGAFR_NUMBITS_USART2_MASK ((uint32_t)0x04000000)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the GPIOx peripheral registers to their default reset values.
|
||||
* @param GPIOx where x can be (A..G) to select the GPIO peripheral.
|
||||
*/
|
||||
void GPIO_DeInit(GPIO_Module* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
if (GPIOx == GPIOA)
|
||||
{
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, ENABLE);
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOA, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOB)
|
||||
{
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, ENABLE);
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOB, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOC)
|
||||
{
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, ENABLE);
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOC, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOD)
|
||||
{
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, ENABLE);
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOD, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOE)
|
||||
{
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOE, ENABLE);
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOE, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOF)
|
||||
{
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOF, ENABLE);
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOF, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOG)
|
||||
{
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOG, ENABLE);
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_GPIOG, DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the Alternate Functions (remap, event control
|
||||
* and EXTI configuration) registers to their default reset values.
|
||||
*/
|
||||
void GPIO_AFIOInitDefault(void)
|
||||
{
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, ENABLE);
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_AFIO, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified
|
||||
* parameters in the GPIO_InitStruct.
|
||||
* @param GPIOx where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param GPIO_InitStruct pointer to a GPIO_InitType structure that
|
||||
* contains the configuration information for the specified GPIO peripheral.
|
||||
*/
|
||||
void GPIO_InitPeripheral(GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStruct)
|
||||
{
|
||||
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
|
||||
uint32_t tmpregister = 0x00, pinmask = 0x00;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
|
||||
assert_param(IS_GPIO_PIN(GPIO_InitStruct->Pin));
|
||||
|
||||
/*---------------------------- GPIO Mode Configuration -----------------------*/
|
||||
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
|
||||
if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
|
||||
/* Output mode */
|
||||
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
|
||||
}
|
||||
/*---------------------------- GPIO PL_CFG Configuration ------------------------*/
|
||||
/* Configure the eight low port pins */
|
||||
if (((uint32_t)GPIO_InitStruct->Pin & ((uint32_t)0x00FF)) != 0x00)
|
||||
{
|
||||
tmpregister = GPIOx->PL_CFG;
|
||||
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||
{
|
||||
pos = ((uint32_t)0x01) << pinpos;
|
||||
/* Get the port pins position */
|
||||
currentpin = (GPIO_InitStruct->Pin) & pos;
|
||||
if (currentpin == pos)
|
||||
{
|
||||
pos = pinpos << 2;
|
||||
/* Clear the corresponding low control register bits */
|
||||
pinmask = ((uint32_t)0x0F) << pos;
|
||||
tmpregister &= ~pinmask;
|
||||
/* Write the mode configuration in the corresponding bits */
|
||||
tmpregister |= (currentmode << pos);
|
||||
/* Reset the corresponding POD bit */
|
||||
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||
{
|
||||
GPIOx->PBC = (((uint32_t)0x01) << pinpos);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the corresponding POD bit */
|
||||
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||
{
|
||||
GPIOx->PBSC = (((uint32_t)0x01) << pinpos);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
GPIOx->PL_CFG = tmpregister;
|
||||
}
|
||||
/*---------------------------- GPIO PH_CFG Configuration ------------------------*/
|
||||
/* Configure the eight high port pins */
|
||||
if (GPIO_InitStruct->Pin > 0x00FF)
|
||||
{
|
||||
tmpregister = GPIOx->PH_CFG;
|
||||
for (pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||
{
|
||||
pos = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
/* Get the port pins position */
|
||||
currentpin = ((GPIO_InitStruct->Pin) & pos);
|
||||
if (currentpin == pos)
|
||||
{
|
||||
pos = pinpos << 2;
|
||||
/* Clear the corresponding high control register bits */
|
||||
pinmask = ((uint32_t)0x0F) << pos;
|
||||
tmpregister &= ~pinmask;
|
||||
/* Write the mode configuration in the corresponding bits */
|
||||
tmpregister |= (currentmode << pos);
|
||||
/* Reset the corresponding POD bit */
|
||||
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||
{
|
||||
GPIOx->PBC = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
}
|
||||
/* Set the corresponding POD bit */
|
||||
if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||
{
|
||||
GPIOx->PBSC = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
}
|
||||
}
|
||||
}
|
||||
GPIOx->PH_CFG = tmpregister;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each GPIO_InitStruct member with its default value.
|
||||
* @param GPIO_InitStruct pointer to a GPIO_InitType structure which will
|
||||
* be initialized.
|
||||
*/
|
||||
void GPIO_InitStruct(GPIO_InitType* GPIO_InitStruct)
|
||||
{
|
||||
/* Reset GPIO init structure parameters values */
|
||||
GPIO_InitStruct->Pin = GPIO_PIN_ALL;
|
||||
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param Pin specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
* @return The input port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_Module* GPIOx, uint16_t Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(Pin));
|
||||
|
||||
if ((GPIOx->PID & Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO input data port.
|
||||
* @param GPIOx where x can be (A..G) to select the GPIO peripheral.
|
||||
* @return GPIO input data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadInputData(GPIO_Module* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->PID);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified output data port bit.
|
||||
* @param GPIOx where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param Pin specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
* @return The output port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_Module* GPIOx, uint16_t Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(Pin));
|
||||
|
||||
if ((GPIOx->POD & Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO output data port.
|
||||
* @param GPIOx where x can be (A..G) to select the GPIO peripheral.
|
||||
* @return GPIO output data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadOutputData(GPIO_Module* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->POD);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the selected data port bits.
|
||||
* @param GPIOx where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param Pin specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
*/
|
||||
void GPIO_SetBits(GPIO_Module* GPIOx, uint16_t Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(Pin));
|
||||
|
||||
GPIOx->PBSC = Pin;
|
||||
}
|
||||
void GPIO_SetBitsHigh16(GPIO_Module* GPIOx, uint32_t Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
// assert_param(IS_GPIO_PIN(Pin));
|
||||
|
||||
GPIOx->PBSC = Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the selected data port bits.
|
||||
* @param GPIOx where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param Pin specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
*/
|
||||
void GPIO_ResetBits(GPIO_Module* GPIOx, uint16_t Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(Pin));
|
||||
|
||||
GPIOx->PBC = Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
* @param GPIOx where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param Pin specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
|
||||
* @param BitCmd specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the Bit_OperateType enum values:
|
||||
* @arg Bit_RESET to clear the port pin
|
||||
* @arg Bit_SET to set the port pin
|
||||
*/
|
||||
void GPIO_WriteBit(GPIO_Module* GPIOx, uint16_t Pin, Bit_OperateType BitCmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(Pin));
|
||||
assert_param(IS_GPIO_BIT_OPERATE(BitCmd));
|
||||
|
||||
if (BitCmd != Bit_RESET)
|
||||
{
|
||||
GPIOx->PBSC = Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->PBC = Pin;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes data to the specified GPIO data port.
|
||||
* @param GPIOx where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param PortVal specifies the value to be written to the port output data register.
|
||||
*/
|
||||
void GPIO_Write(GPIO_Module* GPIOx, uint16_t PortVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
GPIOx->POD = PortVal;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* @param GPIOx where x can be (A..G) to select the GPIO peripheral.
|
||||
* @param Pin specifies the port bit to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
*/
|
||||
void GPIO_ConfigPinLock(GPIO_Module* GPIOx, uint16_t Pin)
|
||||
{
|
||||
uint32_t tmp = 0x00010000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(Pin));
|
||||
|
||||
tmp |= Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->PLOCK_CFG = tmp;
|
||||
/* Reset LCKK bit */
|
||||
GPIOx->PLOCK_CFG = Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->PLOCK_CFG = tmp;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->PLOCK_CFG;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->PLOCK_CFG;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the GPIO pin used as Event output.
|
||||
* @param PortSource selects the GPIO port to be used as source
|
||||
* for Event output.
|
||||
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
|
||||
* @param PinSource specifies the pin for the Event output.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
*/
|
||||
void GPIO_ConfigEventOutput(uint8_t PortSource, uint8_t PinSource)
|
||||
{
|
||||
uint32_t tmpregister = 0x00;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(PortSource));
|
||||
assert_param(IS_GPIO_PIN_SOURCE(PinSource));
|
||||
|
||||
tmpregister = AFIO->ECTRL;
|
||||
/* Clear the PORT[6:4] and PIN[3:0] bits */
|
||||
tmpregister &= EVCR_PORTPINCONFIG_MASK;
|
||||
tmpregister |= (uint32_t)PortSource << 0x04;
|
||||
tmpregister |= PinSource;
|
||||
AFIO->ECTRL = tmpregister;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Event Output.
|
||||
* @param Cmd new state of the Event output.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void GPIO_CtrlEventOutput(FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
*(__IO uint32_t*)EVCR_EVOE_BB = (uint32_t)Cmd;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Changes the mapping of the specified pin.
|
||||
* @param RmpPin selects the pin to remap.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_RMP_SPI1 SPI1 Alternate Function mapping
|
||||
* @arg GPIO_RMP_I2C1 I2C1 Alternate Function mapping
|
||||
* @arg GPIO_RMP_USART1 USART1 Alternate Function mapping
|
||||
* @arg GPIO_RMP_USART2 USART2 Alternate Function mapping
|
||||
* @arg GPIO_PART_RMP_USART3 USART3 Partial Alternate Function mapping
|
||||
* @arg GPIO_ALL_RMP_USART3 USART3 Full Alternate Function mapping
|
||||
* @arg GPIO_PART1_RMP_TIM1 TIM1 Partial Alternate Function mapping
|
||||
* @arg GPIO_PART2_RMP_TIM1 TIM1 Partial Alternate Function mapping
|
||||
* @arg GPIO_ALL_RMP_TIM1 TIM1 Full Alternate Function mapping
|
||||
* @arg GPIO_PartialRemap1_TIM2 TIM2 Partial1 Alternate Function mapping
|
||||
* @arg GPIO_PART2_RMP_TIM2 TIM2 Partial2 Alternate Function mapping
|
||||
* @arg GPIO_ALL_RMP_TIM2 TIM2 Full Alternate Function mapping
|
||||
* @arg GPIO_PART1_RMP_TIM3 TIM3 Partial Alternate Function mapping
|
||||
* @arg GPIO_ALL_RMP_TIM3 TIM3 Full Alternate Function mapping
|
||||
* @arg GPIO_RMP_TIM4 TIM4 Alternate Function mapping
|
||||
* @arg GPIO_RMP1_CAN1 CAN1 Alternate Function mapping
|
||||
* @arg GPIO_Remap2_CAN1 CAN1 Alternate Function mapping
|
||||
* @arg GPIO_RMP_PD01 PD01 Alternate Function mapping
|
||||
* @arg GPIO_RMP_TIM5CH4 LSI connected to TIM5 Channel4 input capture for calibration
|
||||
* @arg GPIO_RMP_ADC1_ETRI ADC1 External Trigger Injected Conversion remapping
|
||||
* @arg GPIO_RMP_ADC1_ETRR ADC1 External Trigger Regular Conversion remapping
|
||||
* @arg GPIO_RMP_ADC2_ETRI ADC2 External Trigger Injected Conversion remapping
|
||||
* @arg GPIO_RMP_ADC2_ETRR ADC2 External Trigger Regular Conversion remapping
|
||||
* @arg GPIO_RMP_SW_JTAG_NO_NJTRST Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
|
||||
* @arg GPIO_RMP_SW_JTAG_SW_ENABLE JTAG-DP Disabled and SW-DP Enabled
|
||||
* @arg GPIO_RMP_SW_JTAG_DISABLE Full SWJ Disabled (JTAG-DP + SW-DP)
|
||||
* @arg GPIO_Remap_XFMC_NADV XFMC NADV Alternate Function mapping
|
||||
* @arg GPIO_RMP_SDIO SDIO Alternate Function mapping
|
||||
* @arg GPIO_RMP1_CAN2 CAN2 Alternate Function mapping
|
||||
* @arg GPIO_RMP3_CAN2 CAN2 Alternate Function mapping
|
||||
* @arg GPIO_RMP1_QSPI QSPI Alternate Function mapping
|
||||
* @arg GPIO_RMP3_QSPI QSPI Alternate Function mapping
|
||||
* @arg GPIO_RMP1_I2C2 I2C2 Alternate Function mapping
|
||||
* @arg GPIO_RMP3_I2C2 I2C2 Alternate Function mapping
|
||||
* @arg GPIO_RMP2_I2C3 I2C3 Alternate Function mapping
|
||||
* @arg GPIO_RMP3_I2C3 I2C3 Alternate Function mapping
|
||||
* @arg GPIO_RMP1_I2C4 I2C4 Alternate Function mapping
|
||||
* @arg GPIO_RMP3_I2C4 I2C4 Alternate Function mapping
|
||||
* @arg GPIO_RMP1_SPI2 SPI2 Alternate Function mapping
|
||||
* @arg GPIO_RMP2_SPI2 SPI2 Alternate Function mapping
|
||||
* @arg GPIO_RMP1_SPI3 SPI3 Alternate Function mapping
|
||||
* @arg GPIO_RMP2_SPI3 SPI3 Alternate Function mapping
|
||||
* @arg GPIO_RMP1_ETH ETH Alternate Function mapping
|
||||
* @arg GPIO_RMP2_ETH ETH Alternate Function mapping
|
||||
* @arg GPIO_RMP3_ETH ETH Alternate Function mapping
|
||||
* @arg GPIO_RMP1_SPI1 SPI1 Alternate Function mapping
|
||||
* @arg GPIO_RMP2_SPI1 SPI1 Alternate Function mapping
|
||||
* @arg GPIO_RMP3_SPI1 SPI1 Alternate Function mapping
|
||||
* @arg GPIO_RMP1_USART2 USART2 Alternate Function mapping
|
||||
* @arg GPIO_RMP2_USART2 USART2 Alternate Function mapping
|
||||
* @arg GPIO_RMP3_USART2 USART2 Alternate Function mapping
|
||||
* @arg GPIO_RMP1_UART4 UART4 Alternate Function mapping
|
||||
* @arg GPIO_RMP2_UART4 UART4 Alternate Function mapping
|
||||
* @arg GPIO_RMP3_UART4 UART4 Alternate Function mapping
|
||||
* @arg GPIO_RMP1_UART5 UART5 Alternate Function mapping
|
||||
* @arg GPIO_RMP2_UART5 UART5 Alternate Function mapping
|
||||
* @arg GPIO_RMP3_UART5 UART5 Alternate Function mapping
|
||||
* @arg GPIO_RMP2_UART6 UART6 Alternate Function mapping
|
||||
* @arg GPIO_RMP3_UART6 UART6 Alternate Function mapping
|
||||
* @arg GPIO_RMP1_UART7 UART7 Alternate Function mapping
|
||||
* @arg GPIO_RMP3_UART7 UART7 Alternate Function mapping
|
||||
* @arg GPIO_RMP1_XFMC XFMC Alternate Function mapping
|
||||
* @arg GPIO_RMP3_XFMC XFMC Alternate Function mapping
|
||||
* @arg GPIO_RMP1_TIM8 TIM8 Alternate Function mapping
|
||||
* @arg GPIO_RMP3_TIM8 TIM8 Alternate Function mapping
|
||||
* @arg GPIO_RMP1_COMP1 COMP1 Alternate Function mapping
|
||||
* @arg GPIO_RMP2_COMP1 COMP1 Alternate Function mapping
|
||||
* @arg GPIO_RMP3_COMP1 COMP1 Alternate Function mapping
|
||||
* @arg GPIO_RMP1_COMP2 COMP2 Alternate Function mapping
|
||||
* @arg GPIO_RMP2_COMP2 COMP2 Alternate Function mapping
|
||||
* @arg GPIO_RMP3_COMP2 COMP2 Alternate Function mapping
|
||||
* @arg GPIO_RMP1_COMP3 COMP3 Alternate Function mapping
|
||||
* @arg GPIO_RMP3_COMP3 COMP3 Alternate Function mapping
|
||||
* @arg GPIO_RMP1_COMP4 COMP4 Alternate Function mapping
|
||||
* @arg GPIO_RMP3_COMP4 COMP4 Alternate Function mapping
|
||||
* @arg GPIO_RMP1_COMP5 COMP5 Alternate Function mapping
|
||||
* @arg GPIO_RMP2_COMP5 COMP5 Alternate Function mapping
|
||||
* @arg GPIO_RMP3_COMP5 COMP5 Alternate Function mapping
|
||||
* @arg GPIO_RMP3_UART5 UART5 Alternate Function mapping
|
||||
* @arg GPIO_RMP1_COMP6 COMP6 Alternate Function mapping
|
||||
* @arg GPIO_RMP3_COMP6 COMP6 Alternate Function mapping
|
||||
* @arg GPIO_RMP_COMP7 COMP7 Alternate Function mapping
|
||||
* @arg GPIO_RMP_ADC3_ETRI ADC3_ETRGINJ Alternate Function mapping
|
||||
* @arg GPIO_RMP_ADC3_ETRR ADC3_ETRGREG Alternate Function mapping
|
||||
* @arg GPIO_RMP_ADC4_ETRI ADC4_ETRGINJ Alternate Function mapping
|
||||
* @arg GPIO_RMP_ADC4_ETRR ADC4_ETRGREG Alternate Function mapping
|
||||
* @arg GPIO_RMP_TSC_OUT_CTRL TSC_OUT_CTRL Alternate Function mapping
|
||||
* @arg GPIO_RMP_QSPI_XIP_EN QSPI_XIP_EN Alternate Function mapping
|
||||
* @arg GPIO_RMP1_DVP DVP Alternate Function mapping
|
||||
* @arg GPIO_RMP3_DVP DVP Alternate Function mapping
|
||||
* @arg GPIO_Remap_SPI1_NSS SPI1 NSS Alternate Function mapping
|
||||
* @arg GPIO_Remap_SPI2_NSS SPI2 NSS Alternate Function mapping
|
||||
* @arg GPIO_Remap_SPI3_NSS SPI3 NSS Alternate Function mapping
|
||||
* @arg GPIO_Remap_QSPI_MISO QSPI MISO Alternate Function mapping
|
||||
* @arg GPIO_Remap_DET_EN_EGB4 EGB4 Detect Alternate Function mapping
|
||||
* @arg GPIO_Remap_DET_EN_EGB3 EGB3 Detect Alternate Function mapping
|
||||
* @arg GPIO_Remap_DET_EN_EGB2 EGB2 Detect Alternate Function mapping
|
||||
* @arg GPIO_Remap_DET_EN_EGB1 EGB1 Detect Alternate Function mapping
|
||||
* @arg GPIO_Remap_DET_EN_EGBN4 EGBN4 Detect Alternate Function mapping
|
||||
* @arg GPIO_Remap_DET_EN_EGBN3 EGBN3 Detect Alternate Function mapping
|
||||
* @arg GPIO_Remap_DET_EN_EGBN2 EGBN2 Detect Alternate Function mapping
|
||||
* @arg GPIO_Remap_DET_EN_EGBN1 EGBN1 Detect Alternate Function mapping
|
||||
* @arg GPIO_Remap_DET_EN_ECLAMP4 ECLAMP4 Detect Alternate Function mapping
|
||||
* @arg GPIO_Remap_DET_EN_ECLAMP3 ECLAMP3 Detect Alternate Function mapping
|
||||
* @arg GPIO_Remap_DET_EN_ECLAMP2 ECLAMP2 Detect Alternate Function mapping
|
||||
* @arg GPIO_Remap_DET_EN_ECLAMP1 ECLAMP1 Detect Alternate Function mapping
|
||||
* @arg GPIO_Remap_RST_EN_EGB4 EGB4 Reset Alternate Function mapping
|
||||
* @arg GPIO_Remap_RST_EN_EGB3 EGB3 Reset Alternate Function mapping
|
||||
* @arg GPIO_Remap_RST_EN_EGB2 EGB2 Reset Alternate Function mapping
|
||||
* @arg GPIO_Remap_RST_EN_EGB1 EGB1 Reset Alternate Function mapping
|
||||
* @arg GPIO_Remap_RST_EN_EGBN4 EGBN4 Reset Alternate Function mapping
|
||||
* @arg GPIO_Remap_RST_EN_EGBN3 EGBN3 Reset Alternate Function mapping
|
||||
* @arg GPIO_Remap_RST_EN_EGBN2 EGBN2 Reset Alternate Function mapping
|
||||
* @arg GPIO_Remap_RST_EN_EGBN1 EGBN1 Reset Alternate Function mapping
|
||||
* @arg GPIO_Remap_RST_EN_ECLAMP4 ECLAMP4 Reset Alternate Function mapping
|
||||
* @arg GPIO_Remap_RST_EN_ECLAMP3 ECLAMP3 Reset Alternate Function mapping
|
||||
* @arg GPIO_Remap_RST_EN_ECLAMP2 ECLAMP2 Reset Alternate Function mapping
|
||||
* @arg GPIO_Remap_RST_EN_ECLAMP1 ECLAMP1 Reset Alternate Function mapping
|
||||
* @param Cmd new state of the port pin remapping.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void GPIO_ConfigPinRemap(uint32_t RmpPin, FunctionalState Cmd)
|
||||
{
|
||||
uint32_t tmp = 0x00, tmp1 = 0x00, tmpregister = 0x00, tmpmask = 0x00, tmp2 = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_REMAP(RmpPin));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
if ((RmpPin & 0x80000000) == 0x80000000)
|
||||
{
|
||||
tmpregister = AFIO->RMP_CFG2;
|
||||
}
|
||||
else if ((RmpPin & 0x40000000) == 0x40000000)
|
||||
{
|
||||
tmpregister = AFIO->RMP_CFG3;
|
||||
}
|
||||
else if ((RmpPin & 0x20000000) == 0x20000000)
|
||||
{
|
||||
tmpregister = AFIO->RMP_CFG4;
|
||||
}
|
||||
else if ((RmpPin & 0x10000000) == 0x10000000)
|
||||
{
|
||||
tmpregister = AFIO->RMP_CFG5;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmpregister = AFIO->RMP_CFG;
|
||||
}
|
||||
|
||||
tmpmask = (RmpPin & DBGAFR_POSITION_MASK) >> 16;
|
||||
tmp = RmpPin & LSB_MASK;
|
||||
|
||||
if ((RmpPin
|
||||
& (DBGAFR_NUMBITS_MAPR5_MASK | DBGAFR_NUMBITS_MAPR4_MASK | DBGAFR_NUMBITS_MAPR3_MASK | DBGAFR_LOCATION_MASK
|
||||
| DBGAFR_NUMBITS_MASK))
|
||||
== (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
|
||||
{
|
||||
tmpregister &= DBGAFR_SWJCFG_MASK;
|
||||
AFIO->RMP_CFG &= DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
else if ((RmpPin & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
|
||||
{
|
||||
if ((RmpPin & DBGAFR_LOCATION_MASK) == DBGAFR_LOCATION_MASK)
|
||||
{
|
||||
tmp1 = (((uint32_t)0x03) << tmpmask) << 16;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp1 = ((uint32_t)0x03) << tmpmask;
|
||||
}
|
||||
tmpregister &= ~tmp1;
|
||||
if ((RmpPin & 0x70000000) == 0x00000000)
|
||||
{
|
||||
tmpregister |= ~DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((RmpPin & DBGAFR_NUMBITS_SPI1_MASK) == DBGAFR_NUMBITS_SPI1_MASK)
|
||||
{
|
||||
if ((RmpPin & 0x00000004) == 0x00000004)
|
||||
{
|
||||
if ((RmpPin & 0x02000000) == 0x02000000) // GPIO_RMP3_SPI1
|
||||
{
|
||||
tmpregister &= ~(tmp << (((RmpPin & 0x00200000) >> 21) * 16));
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
tmp2 = AFIO->RMP_CFG;
|
||||
tmp2 |= 0x00000001;
|
||||
tmp2 |= ~DBGAFR_SWJCFG_MASK;
|
||||
AFIO->RMP_CFG = tmp2; // Remap_SPI1 ENABLE
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp2 = AFIO->RMP_CFG;
|
||||
tmp2 &= 0xFFFFFFFE;
|
||||
tmp2 |= ~DBGAFR_SWJCFG_MASK;
|
||||
AFIO->RMP_CFG = tmp2; // Remap_SPI1 DISABLE
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tmpregister &= ~(tmp << (((RmpPin & 0x00200000) >> 21) * 16)); // GPIO_RMP2_SPI1
|
||||
|
||||
tmp2 = AFIO->RMP_CFG;
|
||||
tmp2 &= 0xFFFFFFFE;
|
||||
tmp2 |= ~DBGAFR_SWJCFG_MASK;
|
||||
AFIO->RMP_CFG = tmp2; // Remap_SPI1 DISABLE
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tmpregister &= ~((tmp | 0x00000004) << (((RmpPin & 0x00200000) >> 21) * 16)); // clear
|
||||
if (Cmd != DISABLE) // GPIO_RMP1_SPI1
|
||||
{
|
||||
tmp2 = AFIO->RMP_CFG;
|
||||
tmp2 |= 0x00000001;
|
||||
tmp2 |= ~DBGAFR_SWJCFG_MASK;
|
||||
AFIO->RMP_CFG = tmp2; // Remap_SPI1 ENABLE
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp2 = AFIO->RMP_CFG;
|
||||
tmp2 &= 0xFFFFFFFE;
|
||||
tmp2 |= ~DBGAFR_SWJCFG_MASK;
|
||||
AFIO->RMP_CFG = tmp2; // Remap_SPI1 DISABLE
|
||||
}
|
||||
}
|
||||
}
|
||||
else if ((RmpPin & DBGAFR_NUMBITS_USART2_MASK) == DBGAFR_NUMBITS_USART2_MASK)
|
||||
{
|
||||
if ((RmpPin & 0x00000008) == 0x00000008)
|
||||
{
|
||||
if ((RmpPin & 0x02000000) == 0x02000000) // GPIO_RMP3_USART2
|
||||
{
|
||||
tmpregister &= ~(tmp << (((RmpPin & 0x00200000) >> 21) * 16));
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
tmp2 = AFIO->RMP_CFG;
|
||||
tmp2 |= 0x00000008;
|
||||
tmp2 |= ~DBGAFR_SWJCFG_MASK;
|
||||
AFIO->RMP_CFG = tmp2; // Remap_USART2 ENABLE
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp2 = AFIO->RMP_CFG;
|
||||
tmp2 &= 0xFFFFFFF7;
|
||||
tmp2 |= ~DBGAFR_SWJCFG_MASK;
|
||||
AFIO->RMP_CFG = tmp2; // Remap_USART2 DISABLE
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tmpregister &= ~(tmp << (((RmpPin & 0x00200000) >> 21) * 16)); // GPIO_RMP2_USART2
|
||||
|
||||
tmp2 = AFIO->RMP_CFG;
|
||||
tmp2 &= 0xFFFFFFF7;
|
||||
tmp2 |= ~DBGAFR_SWJCFG_MASK;
|
||||
AFIO->RMP_CFG = tmp2; // Remap_USART2 DISABLE
|
||||
}
|
||||
}
|
||||
else // GPIO_RMP1_USART2
|
||||
{
|
||||
tmpregister &= ~((tmp | 0x00000008) << (((RmpPin & 0x00200000) >> 21) * 16)); // clear
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
tmp2 = AFIO->RMP_CFG;
|
||||
tmp2 |= 0x00000008;
|
||||
tmp2 |= ~DBGAFR_SWJCFG_MASK;
|
||||
AFIO->RMP_CFG = tmp2; // Remap_USART2 ENABLE
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp2 = AFIO->RMP_CFG;
|
||||
tmp2 &= 0xFFFFFFF7;
|
||||
tmp2 |= ~DBGAFR_SWJCFG_MASK;
|
||||
AFIO->RMP_CFG = tmp2; // Remap_USART2 DISABLE
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tmpregister &= ~(tmp << (((RmpPin & 0x00200000) >> 21) * 16));
|
||||
if ((RmpPin & 0x70000000) == 0x00000000)
|
||||
{
|
||||
tmpregister |= ~DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
tmpregister |= (tmp << (((RmpPin & 0x00200000) >> 21) * 16));
|
||||
}
|
||||
|
||||
if ((RmpPin & 0x80000000) == 0x80000000)
|
||||
{
|
||||
AFIO->RMP_CFG2 = tmpregister;
|
||||
}
|
||||
else if ((RmpPin & 0x40000000) == 0x40000000)
|
||||
{
|
||||
AFIO->RMP_CFG3 = tmpregister;
|
||||
}
|
||||
else if ((RmpPin & 0x20000000) == 0x20000000)
|
||||
{
|
||||
AFIO->RMP_CFG4 = tmpregister;
|
||||
}
|
||||
else if ((RmpPin & 0x10000000) == 0x10000000)
|
||||
{
|
||||
AFIO->RMP_CFG5 = tmpregister;
|
||||
}
|
||||
else
|
||||
{
|
||||
AFIO->RMP_CFG = tmpregister;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the GPIO pin used as EXTI Line.
|
||||
* @param PortSource selects the GPIO port to be used as source for EXTI lines.
|
||||
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
|
||||
* @param PinSource specifies the EXTI line to be configured.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
*/
|
||||
void GPIO_ConfigEXTILine(uint8_t PortSource, uint8_t PinSource)
|
||||
{
|
||||
uint32_t tmp = 0x00;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_EXTI_PORT_SOURCE(PortSource));
|
||||
assert_param(IS_GPIO_PIN_SOURCE(PinSource));
|
||||
|
||||
tmp = ((uint32_t)0x0F) << (0x04 * (PinSource & (uint8_t)0x03));
|
||||
AFIO->EXTI_CFG[PinSource >> 0x02] &= ~tmp;
|
||||
AFIO->EXTI_CFG[PinSource >> 0x02] |= (((uint32_t)PortSource) << (0x04 * (PinSource & (uint8_t)0x03)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the Ethernet media interface.
|
||||
* @note This function applies only to N32G45x Connectivity line devices.
|
||||
* @param ETH_ConfigSel specifies the Media Interface mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_ETH_MII_CFG MII mode
|
||||
* @arg GPIO_ETH_RMII_CFG RMII mode
|
||||
*/
|
||||
void GPIO_ETH_ConfigMediaInterface(uint32_t ETH_ConfigSel)
|
||||
{
|
||||
assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(ETH_ConfigSel));
|
||||
|
||||
AFIO->RMP_CFG &= (uint32_t)(~0x00800000);
|
||||
AFIO->RMP_CFG |= ETH_ConfigSel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,193 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_iwdg.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x_iwdg.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG
|
||||
* @brief IWDG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ---------------------- IWDG registers bit mask ----------------------------*/
|
||||
|
||||
/* KEY register bit mask */
|
||||
#define KEY_ReloadKey ((uint16_t)0xAAAA)
|
||||
#define KEY_EnableKey ((uint16_t)0xCCCC)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
|
||||
* @param IWDG_WriteAccess new state of write access to IWDG_PR and IWDG_RLR registers.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_WRITE_ENABLE Enable write access to IWDG_PR and IWDG_RLR registers
|
||||
* @arg IWDG_WRITE_DISABLE Disable write access to IWDG_PR and IWDG_RLR registers
|
||||
*/
|
||||
void IWDG_WriteConfig(uint16_t IWDG_WriteAccess)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_WRITE(IWDG_WriteAccess));
|
||||
IWDG->KEY = IWDG_WriteAccess;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets IWDG Prescaler value.
|
||||
* @param IWDG_Prescaler specifies the IWDG Prescaler value.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_PRESCALER_DIV4 IWDG prescaler set to 4
|
||||
* @arg IWDG_PRESCALER_DIV8 IWDG prescaler set to 8
|
||||
* @arg IWDG_PRESCALER_DIV16 IWDG prescaler set to 16
|
||||
* @arg IWDG_PRESCALER_DIV32 IWDG prescaler set to 32
|
||||
* @arg IWDG_PRESCALER_DIV64 IWDG prescaler set to 64
|
||||
* @arg IWDG_PRESCALER_DIV128 IWDG prescaler set to 128
|
||||
* @arg IWDG_PRESCALER_DIV256 IWDG prescaler set to 256
|
||||
*/
|
||||
void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_PRESCALER_DIV(IWDG_Prescaler));
|
||||
IWDG->PREDIV = IWDG_Prescaler;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets IWDG Reload value.
|
||||
* @param Reload specifies the IWDG Reload value.
|
||||
* This parameter must be a number between 0 and 0x0FFF.
|
||||
*/
|
||||
void IWDG_CntReload(uint16_t Reload)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_RELOAD(Reload));
|
||||
IWDG->RELV = Reload;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reloads IWDG counter with value defined in the reload register
|
||||
* (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||
*/
|
||||
void IWDG_ReloadKey(void)
|
||||
{
|
||||
IWDG->KEY = KEY_ReloadKey;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||
*/
|
||||
void IWDG_Enable(void)
|
||||
{
|
||||
IWDG->KEY = KEY_EnableKey;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified IWDG flag is set or not.
|
||||
* @param IWDG_FLAG specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_PVU_FLAG Prescaler Value Update on going
|
||||
* @arg IWDG_CRVU_FLAG Reload Value Update on going
|
||||
* @return The new state of IWDG_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_FLAG(IWDG_FLAG));
|
||||
if ((IWDG->STS & IWDG_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,187 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_opamp.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x_opamp.h"
|
||||
#include "n32g45x_rcc.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup OPAMP
|
||||
* @brief OPAMP driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup OPAMP_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup OPAMP_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup OPAMP_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup OPAMP_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup OPAMP_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup OPAMP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
#define SetBitMsk(reg, bit, msk) ((reg) = ((reg) & ~(msk) | (bit)))
|
||||
#define ClrBit(reg, bit) ((reg) &= ~(bit))
|
||||
#define SetBit(reg, bit) ((reg) |= (bit))
|
||||
#define GetBit(reg, bit) ((reg) & (bit))
|
||||
/**
|
||||
* @brief Deinitializes the OPAMP peripheral registers to their default reset values.
|
||||
*/
|
||||
void OPAMP_DeInit(void)
|
||||
{
|
||||
}
|
||||
void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct)
|
||||
{
|
||||
OPAMP_InitStruct->Gain = OPAMP_CS_PGA_GAIN_2;
|
||||
OPAMP_InitStruct->HighVolRangeEn = ENABLE;
|
||||
OPAMP_InitStruct->TimeAutoMuxEn = DISABLE;
|
||||
OPAMP_InitStruct->Mod = OPAMP_CS_PGA_EN;
|
||||
}
|
||||
void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct)
|
||||
{
|
||||
__IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
|
||||
__IO uint32_t tmp = *pCs;
|
||||
SetBitMsk(tmp, OPAMP_InitStruct->Gain, OPAMP_CS_PGA_GAIN_MASK);
|
||||
SetBitMsk(tmp, OPAMP_InitStruct->HighVolRangeEn, OPAMP_CS_RANGE_MASK);
|
||||
SetBitMsk(tmp, OPAMP_InitStruct->TimeAutoMuxEn, OPAMP_CS_TCMEN_MASK);
|
||||
SetBitMsk(tmp, OPAMP_InitStruct->Mod, OPAMP_CS_MOD_MASK);
|
||||
*pCs = tmp;
|
||||
}
|
||||
void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en)
|
||||
{
|
||||
__IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
|
||||
if (en)
|
||||
SetBit(*pCs, OPAMP_CS_EN_MASK);
|
||||
else
|
||||
ClrBit(*pCs, OPAMP_CS_EN_MASK);
|
||||
}
|
||||
|
||||
void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain)
|
||||
{
|
||||
__IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
|
||||
__IO uint32_t tmp = *pCs;
|
||||
SetBitMsk(tmp, Gain, OPAMP_CS_PGA_GAIN_MASK);
|
||||
*pCs = tmp;
|
||||
}
|
||||
void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel)
|
||||
{
|
||||
__IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
|
||||
__IO uint32_t tmp = *pCs;
|
||||
SetBitMsk(tmp, VpSSel, OPAMP_CS_VPSEL_SECOND_MASK);
|
||||
*pCs = tmp;
|
||||
}
|
||||
void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel)
|
||||
{
|
||||
__IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
|
||||
__IO uint32_t tmp = *pCs;
|
||||
SetBitMsk(tmp, VmSSel, OPAMP_CS_VMSEL_SECOND_MASK);
|
||||
*pCs = tmp;
|
||||
}
|
||||
void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel)
|
||||
{
|
||||
__IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
|
||||
__IO uint32_t tmp = *pCs;
|
||||
SetBitMsk(tmp, VpSel, OPAMP_CS_VPSEL_MASK);
|
||||
*pCs = tmp;
|
||||
}
|
||||
void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel)
|
||||
{
|
||||
__IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
|
||||
__IO uint32_t tmp = *pCs;
|
||||
SetBitMsk(tmp, VmSel, OPAMP_CS_VMSEL_MASK);
|
||||
*pCs = tmp;
|
||||
}
|
||||
bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx)
|
||||
{
|
||||
__IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
|
||||
return (GetBit(*pCs, OPAMP_CS_CALOUT_MASK)) ? true : false;
|
||||
}
|
||||
void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en)
|
||||
{
|
||||
__IO uint32_t* pCs = &OPAMP->CS1 + OPAMPx;
|
||||
if (en)
|
||||
SetBit(*pCs, OPAMP_CS_CALON_MASK);
|
||||
else
|
||||
ClrBit(*pCs, OPAMP_CS_CALON_MASK);
|
||||
}
|
||||
// Lock see @OPAMP_LOCK
|
||||
void OPAMP_SetLock(uint32_t Lock)
|
||||
{
|
||||
OPAMP->LOCK = Lock;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,403 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_pwr.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x_pwr.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @brief PWR driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* --------- PWR registers bit address in the alias region ---------- */
|
||||
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CTRL Register ---*/
|
||||
|
||||
/* Alias word address of DBKP bit */
|
||||
#define CTRL_OFFSET (PWR_OFFSET + 0x00)
|
||||
#define DBKP_BITN 0x08
|
||||
#define CTRL_DBKP_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (DBKP_BITN * 4))
|
||||
|
||||
/* Alias word address of PVDEN bit */
|
||||
#define PVDEN_BITN 0x04
|
||||
#define CTRL_PVDEN_BB (PERIPH_BB_BASE + (CTRL_OFFSET * 32) + (PVDEN_BITN * 4))
|
||||
|
||||
/* --- CTRLSTS Register ---*/
|
||||
|
||||
/* Alias word address of WKUPEN bit */
|
||||
#define CTRLSTS_OFFSET (PWR_OFFSET + 0x04)
|
||||
#define WKUPEN_BITN 0x08
|
||||
#define CTRLSTS_WKUPEN_BB (PERIPH_BB_BASE + (CTRLSTS_OFFSET * 32) + (WKUPEN_BITN * 4))
|
||||
|
||||
/* ------------------ PWR registers bit mask ------------------------ */
|
||||
|
||||
/* CTRL register bit mask */
|
||||
#define CTRL_DS_MASK ((uint32_t)0xFFFFFFFC)
|
||||
#define CTRL_PRS_MASK ((uint32_t)0xFFFFFF1F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the PWR peripheral registers to their default reset values.
|
||||
*/
|
||||
void PWR_DeInit(void)
|
||||
{
|
||||
RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, ENABLE);
|
||||
RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_PWR, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables access to the RTC and backup registers.
|
||||
* @param Cmd new state of the access to the RTC and backup registers.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void PWR_BackupAccessEnable(FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
*(__IO uint32_t*)CTRL_DBKP_BB = (uint32_t)Cmd;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Power Voltage Detector(PVD).
|
||||
* @param Cmd new state of the PVD.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void PWR_PvdEnable(FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
*(__IO uint32_t*)CTRL_PVDEN_BB = (uint32_t)Cmd;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
|
||||
* @param PWR_PVDLevel specifies the PVD detection level
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_PVDRANGRE_2V2 PVD detection level set to 2.2V
|
||||
* @arg PWR_PVDRANGRE_2V3 PVD detection level set to 2.3V
|
||||
* @arg PWR_PVDRANGRE_2V4 PVD detection level set to 2.4V
|
||||
* @arg PWR_PVDRANGRE_2V5 PVD detection level set to 2.5V
|
||||
* @arg PWR_PVDRANGRE_2V6 PVD detection level set to 2.6V
|
||||
* @arg PWR_PVDRANGRE_2V7 PVD detection level set to 2.7V
|
||||
* @arg PWR_PVDRANGRE_2V8 PVD detection level set to 2.8V
|
||||
* @arg PWR_PVDRANGRE_2V9 PVD detection level set to 2.9V
|
||||
*/
|
||||
void PWR_PvdRangeConfig(uint32_t PWR_PVDLevel)
|
||||
{
|
||||
uint32_t tmpregister = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
|
||||
tmpregister = PWR->CTRL;
|
||||
/* Clear PRS[7:5] bits */
|
||||
tmpregister &= CTRL_PRS_MASK;
|
||||
/* Set PRS[7:5] bits according to PWR_PVDLevel value */
|
||||
tmpregister |= PWR_PVDLevel;
|
||||
/* Store the new value */
|
||||
PWR->CTRL = tmpregister;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the WakeUp Pin functionality.
|
||||
* @param Cmd new state of the WakeUp Pin functionality.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void PWR_WakeUpPinEnable(FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
*(__IO uint32_t*)CTRLSTS_WKUPEN_BB = (uint32_t)Cmd;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters SLEEP mode.
|
||||
* @param SLEEPONEXIT specifies the SLEEPONEXIT state in SLEEP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg 0 SLEEP mode with SLEEPONEXIT disable
|
||||
* @arg 1 SLEEP mode with SLEEPONEXIT enable
|
||||
* @param PWR_STOPEntry specifies if SLEEP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_STOPENTRY_WFI enter SLEEP mode with WFI instruction
|
||||
* @arg PWR_STOPENTRY_WFE enter SLEEP mode with WFE instruction
|
||||
*/
|
||||
void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_STOPEntry)
|
||||
{
|
||||
// uint32_t tmpregister = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
|
||||
|
||||
/* CLEAR SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPDEEP);
|
||||
|
||||
/* Select SLEEPONEXIT mode entry --------------------------------------------------*/
|
||||
if (SLEEPONEXIT == 1)
|
||||
{
|
||||
/* the MCU enters Sleep mode as soon as it exits the lowest priority INTSTS */
|
||||
SCB->SCR |= SCB_SCR_SLEEPONEXIT;
|
||||
}
|
||||
else if (SLEEPONEXIT == 0)
|
||||
{
|
||||
/* Sleep-now */
|
||||
SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPONEXIT);
|
||||
}
|
||||
|
||||
/* Select SLEEP mode entry --------------------------------------------------*/
|
||||
if (PWR_STOPEntry == PWR_STOPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STOP mode.
|
||||
* @param PWR_Regulator specifies the regulator state in STOP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_REGULATOR_ON STOP mode with regulator ON
|
||||
* @arg PWR_REGULATOR_LOWPOWER STOP mode with regulator in low power mode
|
||||
* @param PWR_STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_STOPENTRY_WFI enter STOP mode with WFI instruction
|
||||
* @arg PWR_STOPENTRY_WFE enter STOP mode with WFE instruction
|
||||
*/
|
||||
void PWR_EnterStopState(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
|
||||
{
|
||||
uint32_t tmpregister = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
|
||||
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
|
||||
|
||||
/* Select the regulator state in STOP mode ---------------------------------*/
|
||||
tmpregister = PWR->CTRL;
|
||||
/* Clear PDS and LPS bits */
|
||||
tmpregister &= CTRL_DS_MASK;
|
||||
/* Set LPS bit according to PWR_Regulator value */
|
||||
tmpregister |= PWR_Regulator;
|
||||
/* Store the new value */
|
||||
PWR->CTRL = tmpregister;
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP;
|
||||
|
||||
/* Select STOP mode entry --------------------------------------------------*/
|
||||
if (PWR_STOPEntry == PWR_STOPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPDEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STOP2 mode.
|
||||
* @param PWR_STOPEntry specifies if STOP2 mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_STOPENTRY_WFI enter STOP2 mode with WFI instruction
|
||||
* @arg PWR_STOPENTRY_WFE enter STOP2 mode with WFE instruction
|
||||
*/
|
||||
void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry)
|
||||
{
|
||||
uint32_t tmpregister = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
|
||||
|
||||
/* Select the regulator state in STOP2 mode ---------------------------------*/
|
||||
tmpregister = PWR->CTRL;
|
||||
/* Clear PDS and LPS bits */
|
||||
tmpregister &= CTRL_DS_MASK;
|
||||
/* Set PWR_CTRL.9 bit */
|
||||
tmpregister |= PWR_CTRL_MSB;
|
||||
/* Store the new value */
|
||||
PWR->CTRL = tmpregister;
|
||||
/*STOP2 sleep mode control-stop2s*/
|
||||
PWR->CTRL2 |= PWR_CTRL2_STOP2;
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP;
|
||||
// PWR_CTRL2.BIT0 STOP2S need?
|
||||
/* Select STOP mode entry --------------------------------------------------*/
|
||||
if (PWR_STOPEntry == PWR_STOPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t) ~((uint32_t)SCB_SCR_SLEEPDEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STANDBY mode.
|
||||
*/
|
||||
void PWR_EnterStandbyState(void)
|
||||
{
|
||||
/* Clear Wake-up flag */
|
||||
PWR->CTRL |= PWR_CTRL_CWKUP;
|
||||
/* Set PWR_CTRL.9 bit */
|
||||
PWR->CTRL &= ~(PWR_CTRL_MSB);
|
||||
/* Clear PDS and LPS bits */
|
||||
PWR->CTRL &= CTRL_DS_MASK;
|
||||
/* Select STANDBY mode */
|
||||
PWR->CTRL |= PWR_CTRL_PDS;
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP;
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined(__CC_ARM)
|
||||
__force_stores();
|
||||
#endif
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified PWR flag is set or not.
|
||||
* @param PWR_FLAG specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WU_FLAG Wake Up flag
|
||||
* @arg PWR_SB_FLAG StandBy flag
|
||||
* @arg PWR_PVDO_FLAG PVD Output
|
||||
* @arg PWR_VBATF_FLAG VBAT flag
|
||||
* @return The new state of PWR_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
|
||||
|
||||
if ((PWR->CTRLSTS & PWR_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the PWR's pending flags.
|
||||
* @param PWR_FLAG specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WU_FLAG Wake Up flag
|
||||
* @arg PWR_SB_FLAG StandBy and VBAT flag
|
||||
*/
|
||||
void PWR_ClearFlag(uint32_t PWR_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
|
||||
|
||||
PWR->CTRL |= PWR_FLAG << 2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,768 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_qspi.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x_qspi.h"
|
||||
|
||||
/**
|
||||
* @brief Merge configuration from the buffer of QSPI para struct, then write it into related registers.
|
||||
* @param QSPI_InitStruct pointer to buffer of QSPI para struct.
|
||||
*/
|
||||
void QspiConfigInit(QSPI_InitType* QSPI_InitStruct)
|
||||
{
|
||||
uint32_t tmpregister = 0;
|
||||
|
||||
if ((QSPI_InitStruct->SPI_FRF) == QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT)
|
||||
{
|
||||
tmpregister |= (uint32_t)(QSPI_InitStruct->SPI_FRF | QSPI_InitStruct->TMOD | QSPI_InitStruct->SCPOL
|
||||
| QSPI_InitStruct->SCPH | QSPI_InitStruct->DFS);
|
||||
QSPI->CTRL0 = tmpregister;
|
||||
QSPI->CTRL1 = QSPI_InitStruct->NDF;
|
||||
QSPI->BAUD = QSPI_InitStruct->CLK_DIV;
|
||||
QSPI->TXFT = QSPI_InitStruct->TXFT;
|
||||
QSPI->RXFT = QSPI_InitStruct->RXFT;
|
||||
}
|
||||
else if ((QSPI_InitStruct->SPI_FRF) == QSPI_CTRL0_SPI_FRF_DUAL_FORMAT)
|
||||
{
|
||||
tmpregister |= (uint32_t)(QSPI_InitStruct->SPI_FRF | QSPI_InitStruct->TMOD | QSPI_InitStruct->SCPOL
|
||||
| QSPI_InitStruct->SCPH | QSPI_InitStruct->DFS | QSPI_InitStruct->CFS);
|
||||
QSPI->CTRL0 = tmpregister;
|
||||
if ((QSPI_InitStruct->TMOD) == QSPI_CTRL0_TMOD_TX_ONLY)
|
||||
{
|
||||
QSPI_InitStruct->ENHANCED_WAIT_CYCLES = 0;
|
||||
}
|
||||
tmpregister = 0;
|
||||
tmpregister |=
|
||||
(uint32_t)(QSPI_InitStruct->ENHANCED_CLK_STRETCH_EN | QSPI_InitStruct->ENHANCED_ADDR_LEN
|
||||
| QSPI_InitStruct->ENHANCED_INST_L | QSPI_InitStruct->ENHANCED_WAIT_CYCLES | QSPI_InitStruct->TRANS_TYPE);
|
||||
QSPI->ENH_CTRL0 = tmpregister;
|
||||
QSPI->BAUD = QSPI_InitStruct->CLK_DIV;
|
||||
QSPI->TXFT = QSPI_InitStruct->TXFT;
|
||||
QSPI->RXFT = QSPI_InitStruct->RXFT;
|
||||
if ((QSPI_InitStruct->TMOD) == QSPI_CTRL0_TMOD_TX_ONLY)
|
||||
{
|
||||
QSPI->CTRL1 = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
QSPI->CTRL1 = QSPI_InitStruct->NDF;
|
||||
}
|
||||
}
|
||||
else if ((QSPI_InitStruct->SPI_FRF) == QSPI_CTRL0_SPI_FRF_QUAD_FORMAT)
|
||||
{
|
||||
tmpregister |= (uint32_t)(QSPI_InitStruct->SPI_FRF | QSPI_InitStruct->TMOD | QSPI_InitStruct->SCPOL
|
||||
| QSPI_InitStruct->SCPH | QSPI_InitStruct->DFS | QSPI_InitStruct->CFS);
|
||||
QSPI->CTRL0 = tmpregister;
|
||||
if ((QSPI_InitStruct->TMOD) == QSPI_CTRL0_TMOD_TX_ONLY)
|
||||
{
|
||||
QSPI_InitStruct->ENHANCED_WAIT_CYCLES = 0;
|
||||
}
|
||||
tmpregister = 0;
|
||||
tmpregister |=
|
||||
(uint32_t)(QSPI_InitStruct->ENHANCED_CLK_STRETCH_EN | QSPI_InitStruct->ENHANCED_ADDR_LEN
|
||||
| QSPI_InitStruct->ENHANCED_INST_L | QSPI_InitStruct->ENHANCED_WAIT_CYCLES | QSPI_InitStruct->TRANS_TYPE);
|
||||
QSPI->ENH_CTRL0 = tmpregister;
|
||||
QSPI->BAUD = QSPI_InitStruct->CLK_DIV;
|
||||
QSPI->TXFT = QSPI_InitStruct->TXFT;
|
||||
QSPI->RXFT = QSPI_InitStruct->RXFT;
|
||||
if ((QSPI_InitStruct->TMOD) == QSPI_CTRL0_TMOD_TX_ONLY)
|
||||
{
|
||||
QSPI->CTRL1 = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
QSPI->CTRL1 = QSPI_InitStruct->NDF;
|
||||
}
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @brief Configure single GPIO port as GPIO_Mode_AF_PP.
|
||||
* @param GPIOx x can be A to G to select the GPIO port.
|
||||
* @param Pin This parameter can be GPIO_PIN_0~GPIO_PIN_15.
|
||||
*/
|
||||
static void QSPI_SingleGpioConfig(GPIO_Module* GPIOx, uint16_t Pin)
|
||||
{
|
||||
GPIO_InitType GPIO_InitStructure;
|
||||
|
||||
GPIO_InitStructure.Pin = Pin;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitPeripheral(GPIOx, &GPIO_InitStructure);
|
||||
}
|
||||
/**
|
||||
* @brief Remap QSPI AFIO group by selecting the pin of NSS.
|
||||
* @param qspi_nss_port_sel select the pin of NSS.
|
||||
QSPI_NSS_PORTA_SEL:QSPI remap by PA4~PA7 and PC4~PC5.
|
||||
QSPI_NSS_PORTC_SEL:QSPI remap by PC10~PC12 and PD0~PD2.
|
||||
QSPI_NSS_PORTF_SEL:QSPI remap by PF0~PF5.
|
||||
* @param IO1_Input IO1 Configure as input or not.
|
||||
* @param IO3_Output IO3 Configure as output or not.
|
||||
*/
|
||||
void QSPI_GPIO(QSPI_NSS_PORT_SEL qspi_nss_port_sel, bool IO1_Input, bool IO3_Output)
|
||||
{
|
||||
GPIO_InitType GPIO_InitStructure;
|
||||
|
||||
switch (qspi_nss_port_sel)
|
||||
{
|
||||
case QSPI_NSS_PORTA_SEL:
|
||||
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOA | RCC_APB2_PERIPH_GPIOC | RCC_APB2_PERIPH_AFIO, ENABLE);
|
||||
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_QSPI, ENABLE);
|
||||
GPIO_ConfigPinRemap(GPIO_RMP3_QSPI, DISABLE); //clear two bits of qspi
|
||||
|
||||
QSPI_SingleGpioConfig(GPIOA, GPIO_PIN_4); // NSS
|
||||
QSPI_SingleGpioConfig(GPIOA, GPIO_PIN_5); // SCK
|
||||
QSPI_SingleGpioConfig(GPIOA, GPIO_PIN_6); // IO0
|
||||
if (IO1_Input)
|
||||
{
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_7; // IO1
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_INPUT;
|
||||
GPIO_InitPeripheral(GPIOC, &GPIO_InitStructure);
|
||||
}
|
||||
else
|
||||
{
|
||||
QSPI_SingleGpioConfig(GPIOA, GPIO_PIN_7); // IO1
|
||||
}
|
||||
QSPI_SingleGpioConfig(GPIOC, GPIO_PIN_4); // IO2
|
||||
if (IO3_Output)
|
||||
{
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_5; // IO3
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitPeripheral(GPIOC, &GPIO_InitStructure);
|
||||
}
|
||||
else
|
||||
{
|
||||
QSPI_SingleGpioConfig(GPIOC, GPIO_PIN_5); // IO3
|
||||
}
|
||||
break;
|
||||
case QSPI_NSS_PORTC_SEL:
|
||||
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC | RCC_APB2_PERIPH_GPIOD | RCC_APB2_PERIPH_AFIO, ENABLE);
|
||||
|
||||
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_QSPI, ENABLE);
|
||||
GPIO_ConfigPinRemap(GPIO_RMP3_QSPI, ENABLE);
|
||||
GPIO_ConfigPinRemap(GPIO_RMP_QSPI_XIP_EN, ENABLE);
|
||||
|
||||
QSPI_SingleGpioConfig(GPIOC, GPIO_PIN_10); // NSS
|
||||
QSPI_SingleGpioConfig(GPIOC, GPIO_PIN_11); // SCK
|
||||
QSPI_SingleGpioConfig(GPIOC, GPIO_PIN_12); // IO0
|
||||
if (IO1_Input)
|
||||
{
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_0; // IO1
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_INPUT;
|
||||
GPIO_InitPeripheral(GPIOD, &GPIO_InitStructure);
|
||||
}
|
||||
else
|
||||
{
|
||||
QSPI_SingleGpioConfig(GPIOD, GPIO_PIN_0); // IO1
|
||||
}
|
||||
QSPI_SingleGpioConfig(GPIOD, GPIO_PIN_1); // IO2
|
||||
if (IO3_Output)
|
||||
{
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_2; // IO3
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitPeripheral(GPIOD, &GPIO_InitStructure);
|
||||
}
|
||||
else
|
||||
{
|
||||
QSPI_SingleGpioConfig(GPIOD, GPIO_PIN_2); // IO3
|
||||
}
|
||||
break;
|
||||
case QSPI_NSS_PORTF_SEL:
|
||||
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOF | RCC_APB2_PERIPH_AFIO, ENABLE);
|
||||
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_QSPI, ENABLE);
|
||||
GPIO_ConfigPinRemap(GPIO_RMP1_QSPI, ENABLE);
|
||||
|
||||
QSPI_SingleGpioConfig(GPIOF, GPIO_PIN_0); // NSS
|
||||
QSPI_SingleGpioConfig(GPIOF, GPIO_PIN_1); // SCK
|
||||
QSPI_SingleGpioConfig(GPIOF, GPIO_PIN_2); // IO0
|
||||
if (IO1_Input)
|
||||
{
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_3; // IO1
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_INPUT;
|
||||
GPIO_InitPeripheral(GPIOF, &GPIO_InitStructure);
|
||||
}
|
||||
else
|
||||
{
|
||||
QSPI_SingleGpioConfig(GPIOF, GPIO_PIN_3); // IO1
|
||||
}
|
||||
QSPI_SingleGpioConfig(GPIOF, GPIO_PIN_4); // IO2
|
||||
if (IO3_Output)
|
||||
{
|
||||
GPIO_InitStructure.Pin = GPIO_PIN_5; // IO3
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitPeripheral(GPIOF, &GPIO_InitStructure);
|
||||
}
|
||||
else
|
||||
{
|
||||
QSPI_SingleGpioConfig(GPIOF, GPIO_PIN_5); // IO3
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @brief Control QSPI function switch.
|
||||
* @param cmd select enable or disable QSPI.
|
||||
*/
|
||||
void QSPI_Cmd(bool cmd)
|
||||
{
|
||||
if (cmd != DISABLE)
|
||||
{
|
||||
QSPI->SLAVE_EN = QSPI_SLAVE_EN_SEN;
|
||||
QSPI->EN = QSPI_EN_QEN;
|
||||
}
|
||||
else
|
||||
{
|
||||
QSPI->SLAVE_EN &= ~QSPI_SLAVE_EN_SEN;
|
||||
QSPI->EN &= ~QSPI_EN_QEN;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @brief Configuration of QSPI interrupt.
|
||||
*/
|
||||
void QSPI_NVIC_Configuration(void)
|
||||
{
|
||||
NVIC_InitType NVIC_InitStructure;
|
||||
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_0);
|
||||
NVIC_InitStructure.NVIC_IRQChannel = QSPI_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
}
|
||||
/**
|
||||
* @brief Configuration of QSPI DMA.
|
||||
* @param PeripheraAddr start address of periphera.
|
||||
* @param MemoryAddr start address of memory.
|
||||
* @param Len size of buffer.
|
||||
* @param TxRx transmit or receive data.
|
||||
DMA_TX:transmit data
|
||||
DMA_TX:receive data
|
||||
*/
|
||||
void QSPI_DMA_Config(uint32_t PeripheraAddr, uint32_t MemoryAddr, uint16_t Len, uint8_t TxRx)
|
||||
{
|
||||
DMA_InitType DMA_InitStructure;
|
||||
DMA_ChannelType* DMAyChx;
|
||||
uint32_t Direction;
|
||||
uint8_t QSPI_DMAReq;
|
||||
uint8_t QSPI_DMADL;
|
||||
|
||||
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_AFIO, ENABLE);
|
||||
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_DMA2, ENABLE);
|
||||
|
||||
if (TxRx == DMA_TX) // DMA send enable
|
||||
{
|
||||
DMAyChx = DMA2_CH7;
|
||||
Direction = DMA_DIR_PERIPH_DST;
|
||||
QSPI_DMADL = 0x01;
|
||||
QSPI_DMAReq = QSPI_DMAReq_TxEN;
|
||||
DMA_RequestRemap(DMA2_REMAP_QSPI_TX, DMA2, DMAyChx, ENABLE);
|
||||
}
|
||||
else if (TxRx == DMA_RX) // DMA receive enable
|
||||
{
|
||||
DMAyChx = DMA2_CH8;
|
||||
Direction = DMA_DIR_PERIPH_SRC;
|
||||
QSPI_DMADL = 0x01;
|
||||
QSPI_DMAReq = QSPI_DMAReq_RxEN;
|
||||
DMA_RequestRemap(DMA2_REMAP_QSPI_RX, DMA2, DMAyChx, ENABLE);
|
||||
}
|
||||
|
||||
DMA_DeInit(DMAyChx);
|
||||
DMA_InitStructure.PeriphAddr = PeripheraAddr; // Peripheral data address
|
||||
DMA_InitStructure.MemAddr = MemoryAddr; // memory address
|
||||
DMA_InitStructure.Direction = Direction; //
|
||||
DMA_InitStructure.BufSize = Len;
|
||||
DMA_InitStructure.PeriphInc = DMA_PERIPH_INC_DISABLE; // Peripheral address not increment
|
||||
DMA_InitStructure.DMA_MemoryInc = DMA_MEM_INC_ENABLE; // DMA memory auto increment
|
||||
DMA_InitStructure.PeriphDataSize = DMA_PERIPH_DATA_SIZE_WORD; // Peripheral data In word
|
||||
DMA_InitStructure.MemDataSize = 0x800; // memory data In word
|
||||
DMA_InitStructure.CircularMode = DMA_MODE_NORMAL;
|
||||
DMA_InitStructure.Priority = DMA_PRIORITY_HIGH; // DMA channel High Priority
|
||||
DMA_InitStructure.Mem2Mem = DMA_M2M_DISABLE; // not memory-to-memory mode
|
||||
DMA_Init(DMAyChx, &DMA_InitStructure); //
|
||||
|
||||
if (TxRx == DMA_TX)
|
||||
{
|
||||
QSPI->DMA_CTRL = 0x00;
|
||||
QSPI->DMATDL_CTRL = QSPI_DMADL; // 1
|
||||
QSPI->DMA_CTRL = QSPI_DMAReq; ////QSPI_DMAReq_TxEN
|
||||
}
|
||||
else if (TxRx == DMA_RX)
|
||||
{
|
||||
QSPI->DMA_CTRL = 0x00;
|
||||
QSPI->DMARDL_CTRL = QSPI_DMADL;
|
||||
QSPI->DMA_CTRL = QSPI_DMAReq;
|
||||
}
|
||||
|
||||
DMA_EnableChannel(DMAyChx, ENABLE); // Enable DMA
|
||||
}
|
||||
/**
|
||||
* @brief Select format of QSPI.
|
||||
* @param qspi_format_sel Select format of QSPI.
|
||||
STANDARD_SPI_FORMAT_SEL:Standard spi
|
||||
DUAL_SPI_FORMAT_SEL:Dual spi
|
||||
QUAD_SPI_FORMAT_SEL:Quad spi
|
||||
XIP_SPI_FORMAT_SEL: Memory mapping mode
|
||||
* @param data_dir The direction of transferring data.
|
||||
TX_AND_RX:Transmit and receive data.
|
||||
RX_ONLY:Receive data only.
|
||||
TX_ONLY:Transmit data only.
|
||||
* @param count Number of data frames. It is valid only in RX_ONLY mode of DUAL_SPI_FORMAT_SEL or QUAD_SPI_FORMAT_SEL.
|
||||
*/
|
||||
void QspiInit(QSPI_FORMAT_SEL qspi_format_sel, QSPI_DATA_DIR data_dir, uint16_t count)
|
||||
{
|
||||
QSPI_InitType QSPI_InitStruct;
|
||||
|
||||
switch (qspi_format_sel)
|
||||
{
|
||||
case STANDARD_SPI_FORMAT_SEL:
|
||||
////QSPI_GPIO(QSPI_NSS_PORTA_SEL,1,1);
|
||||
QSPI_GPIO(QSPI_AFIO_PORT_SEL, 0, 0);
|
||||
|
||||
QSPI_DeInit();
|
||||
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_QSPI, ENABLE);
|
||||
QSPI_InitStruct.SPI_FRF = QSPI_CTRL0_SPI_FRF_STANDARD_FORMAT;
|
||||
QSPI_InitStruct.TMOD = QSPI_CTRL0_TMOD_TX_AND_RX;
|
||||
QSPI_InitStruct.SSTE = 0;
|
||||
QSPI_InitStruct.SCPOL = QSPI_CTRL0_SCPOL_LOW;
|
||||
QSPI_InitStruct.SCPH = QSPI_CTRL0_SCPH_FIRST_EDGE;
|
||||
QSPI_InitStruct.DFS = QSPI_CTRL0_DFS_8_BIT;
|
||||
QSPI_InitStruct.CLK_DIV = CLOCK_DIVIDER;
|
||||
QSPI_InitStruct.TXFT = TX_COUNT_EN;
|
||||
QSPI_InitStruct.NDF = CTRL1_NDF_CNT; // not affect by count in standard spi mode
|
||||
|
||||
QspiConfigInit(&QSPI_InitStruct);
|
||||
QSPI_Cmd(ENABLE);
|
||||
|
||||
if (QSPI_AFIO_PORT_SEL == QSPI_NSS_PORTA_SEL)
|
||||
{
|
||||
GPIOC->PBSC = GPIO_PIN_5; // HOLD ON when select QSPI_NSS_PORTA_SEL
|
||||
}
|
||||
else if (QSPI_AFIO_PORT_SEL == QSPI_NSS_PORTC_SEL)
|
||||
{
|
||||
GPIOD->PBSC = GPIO_PIN_2; // HOLD ON when select QSPI_NSS_PORTC_SEL
|
||||
}
|
||||
else if (QSPI_AFIO_PORT_SEL == QSPI_NSS_PORTF_SEL)
|
||||
{
|
||||
GPIOF->PBSC = GPIO_PIN_5; // HOLD ON when select QSPI_NSS_PORTF_SEL
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
break;
|
||||
case DUAL_SPI_FORMAT_SEL:
|
||||
QSPI_GPIO(QSPI_AFIO_PORT_SEL, 0, 0);
|
||||
|
||||
QSPI_DeInit();
|
||||
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_QSPI, ENABLE);
|
||||
|
||||
GPIO_ConfigPinRemap(GPIO_RMP_QSPI_XIP_EN, DISABLE);
|
||||
QSPI_InitStruct.SPI_FRF = QSPI_CTRL0_SPI_FRF_DUAL_FORMAT;
|
||||
if (data_dir == TX_AND_RX)
|
||||
QSPI_InitStruct.TMOD = QSPI_CTRL0_TMOD_TX_AND_RX;
|
||||
else if (data_dir == TX_ONLY)
|
||||
QSPI_InitStruct.TMOD = QSPI_CTRL0_TMOD_TX_ONLY;
|
||||
else if (data_dir == RX_ONLY)
|
||||
QSPI_InitStruct.TMOD = QSPI_CTRL0_TMOD_RX_ONLY;
|
||||
QSPI_InitStruct.SSTE = 0;
|
||||
QSPI_InitStruct.SCPOL = QSPI_CTRL0_SCPOL_LOW;
|
||||
QSPI_InitStruct.SCPH = QSPI_CTRL0_SCPH_FIRST_EDGE;
|
||||
QSPI_InitStruct.DFS = QSPI_CTRL0_DFS_8_BIT;
|
||||
QSPI_InitStruct.CLK_DIV = CLOCK_DIVIDER;
|
||||
QSPI_InitStruct.TXFT = TX_COUNT_EN;
|
||||
QSPI_InitStruct.NDF = count; // only be valid in Rx mode
|
||||
QSPI_InitStruct.ENHANCED_CLK_STRETCH_EN = QSPI_ENH_CTRL0_CLK_STRETCH_EN;
|
||||
QSPI_InitStruct.ENHANCED_WAIT_CYCLES = ENSPI_WAIT_2CYCLES;
|
||||
QSPI_InitStruct.ENHANCED_ADDR_LEN = ENSPI_ADDR_24BIT;
|
||||
QSPI_InitStruct.ENHANCED_INST_L = QSPI_ENH_CTRL0_INST_L_8_LINE;
|
||||
if (SRAM_CFG_EN == 1)
|
||||
QSPI_InitStruct.TRANS_TYPE = QSPI_ENH_CTRL0_TRANS_TYPE_ALL_BY_FRF;
|
||||
else
|
||||
QSPI_InitStruct.TRANS_TYPE = QSPI_ENH_CTRL0_TRANS_TYPE_STANDARD;
|
||||
|
||||
QspiConfigInit(&QSPI_InitStruct);
|
||||
QSPI_Cmd(ENABLE);
|
||||
if (QSPI_AFIO_PORT_SEL == QSPI_NSS_PORTA_SEL)
|
||||
{
|
||||
GPIOC->PBSC = GPIO_PIN_5; // HOLD ON when select QSPI_NSS_PORTA_SEL
|
||||
}
|
||||
else if (QSPI_AFIO_PORT_SEL == QSPI_NSS_PORTC_SEL)
|
||||
{
|
||||
GPIOD->PBSC = GPIO_PIN_2; // HOLD ON when select QSPI_NSS_PORTC_SEL
|
||||
}
|
||||
else if (QSPI_AFIO_PORT_SEL == QSPI_NSS_PORTF_SEL)
|
||||
{
|
||||
GPIOF->PBSC = GPIO_PIN_5; // HOLD ON when select QSPI_NSS_PORTF_SEL
|
||||
}
|
||||
else
|
||||
{
|
||||
}
|
||||
break;
|
||||
case QUAD_SPI_FORMAT_SEL:
|
||||
QSPI_GPIO(QSPI_AFIO_PORT_SEL, 0, 0);
|
||||
|
||||
QSPI_DeInit();
|
||||
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_QSPI, ENABLE);
|
||||
|
||||
GPIO_ConfigPinRemap(GPIO_RMP_QSPI_XIP_EN, DISABLE);
|
||||
QSPI_InitStruct.SPI_FRF = QSPI_CTRL0_SPI_FRF_QUAD_FORMAT;
|
||||
if (data_dir == TX_AND_RX)
|
||||
QSPI_InitStruct.TMOD = QSPI_CTRL0_TMOD_TX_AND_RX;
|
||||
else if (data_dir == TX_ONLY)
|
||||
QSPI_InitStruct.TMOD = QSPI_CTRL0_TMOD_TX_ONLY;
|
||||
else if (data_dir == RX_ONLY)
|
||||
QSPI_InitStruct.TMOD = QSPI_CTRL0_TMOD_RX_ONLY;
|
||||
QSPI_InitStruct.SSTE = 0;
|
||||
QSPI_InitStruct.SCPOL = QSPI_CTRL0_SCPOL_LOW;
|
||||
QSPI_InitStruct.SCPH = QSPI_CTRL0_SCPH_FIRST_EDGE;
|
||||
QSPI_InitStruct.DFS = QSPI_CTRL0_DFS_8_BIT;
|
||||
QSPI_InitStruct.CLK_DIV = CLOCK_DIVIDER;
|
||||
QSPI_InitStruct.TXFT = TX_COUNT_EN;
|
||||
QSPI_InitStruct.NDF = count; // only be valid in Rx mode
|
||||
QSPI_InitStruct.ENHANCED_CLK_STRETCH_EN = QSPI_ENH_CTRL0_CLK_STRETCH_EN;
|
||||
QSPI_InitStruct.ENHANCED_WAIT_CYCLES = ENSPI_WAIT_2CYCLES;
|
||||
QSPI_InitStruct.ENHANCED_ADDR_LEN = ENSPI_ADDR_24BIT;
|
||||
QSPI_InitStruct.ENHANCED_INST_L = QSPI_ENH_CTRL0_INST_L_8_LINE;
|
||||
if (SRAM_CFG_EN == 1)
|
||||
QSPI_InitStruct.TRANS_TYPE = QSPI_ENH_CTRL0_TRANS_TYPE_ALL_BY_FRF;
|
||||
else
|
||||
QSPI_InitStruct.TRANS_TYPE = QSPI_ENH_CTRL0_TRANS_TYPE_STANDARD;
|
||||
QspiConfigInit(&QSPI_InitStruct);
|
||||
QSPI_Cmd(ENABLE);
|
||||
break;
|
||||
case XIP_SPI_FORMAT_SEL:
|
||||
QSPI_GPIO(QSPI_NSS_PORTA_SEL, 0, 0);
|
||||
|
||||
QSPI_DeInit();
|
||||
RCC_EnableAHBPeriphClk(RCC_AHB_PERIPH_QSPI, ENABLE);
|
||||
|
||||
QSPI->SLAVE_EN = 0;
|
||||
QSPI->EN = 0;
|
||||
QSPI->XIP_SLAVE_EN = 0;
|
||||
|
||||
QSPI->XIP_INCR_TOC = 0x6B; // ITOC
|
||||
QSPI->XIP_WRAP_TOC = 0x6B; // WTOC
|
||||
|
||||
if (data_dir == RX_ONLY)
|
||||
{
|
||||
if (XIP_PREFETCH_EN)
|
||||
QSPI->ENH_CTRL0 = 0x20180218;
|
||||
else
|
||||
QSPI->ENH_CTRL0 = 0x180218;
|
||||
|
||||
QSPI->XIP_CTRL = 0x450462;
|
||||
}
|
||||
else
|
||||
{
|
||||
QSPI->XIP_CTRL = 0x451462;
|
||||
QSPI->XIP_MODE = 0x11aa;
|
||||
}
|
||||
QSPI->CTRL1 = 16; //
|
||||
QSPI->BAUD = 0x08;
|
||||
QSPI->CTRL0 = 0x800807;
|
||||
|
||||
QSPI->SLAVE_EN = 1;
|
||||
QSPI->EN = 1;
|
||||
QSPI->XIP_SLAVE_EN = XIP_SLAVE_EN_SEN;
|
||||
|
||||
GPIO_ConfigPinRemap(GPIO_RMP_QSPI_XIP_EN, ENABLE);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @brief Deinitializes the QSPI peripheral registers to its default reset values.
|
||||
*/
|
||||
void QSPI_DeInit(void)
|
||||
{
|
||||
RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_QSPI, ENABLE);
|
||||
RCC_EnableAHBPeriphReset(RCC_AHB_PERIPH_QSPI, DISABLE);
|
||||
}
|
||||
/**
|
||||
* @brief Get the flag of interrupt status register.
|
||||
* @param FLAG Flag of related interrupt register.
|
||||
*/
|
||||
uint16_t QSPI_GetITStatus(uint16_t FLAG)
|
||||
{
|
||||
uint16_t tmp = 0;
|
||||
tmp = QSPI->ISTS & FLAG;
|
||||
if (tmp)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
* @brief Clear the flag of related interrupt register.
|
||||
* @param FLAG Flag of related interrupt register.
|
||||
*/
|
||||
void QSPI_ClearITFLAG(uint16_t FLAG)
|
||||
{
|
||||
volatile uint16_t tmp = 0;
|
||||
|
||||
if (FLAG == QSPI_ISTS_TXFOIS)
|
||||
tmp = QSPI->TXFOI_CLR;
|
||||
if (FLAG == QSPI_ISTS_RXFOIS)
|
||||
tmp = QSPI->RXFOI_CLR;
|
||||
if (FLAG == QSPI_ISTS_RXFUIS)
|
||||
tmp = QSPI->RXFUI_CLR;
|
||||
if (FLAG == QSPI_ISTS_MMCIS)
|
||||
tmp = QSPI->MMC_CLR;
|
||||
if (FLAG == QSPI_ISTS_ICRS)
|
||||
tmp = QSPI->ICLR;
|
||||
}
|
||||
/**
|
||||
* @brief Get QSPI status,busy or not.
|
||||
* @return 1:QSPI busy;0:QSPI idle.
|
||||
*/
|
||||
bool GetQspiBusyStatus(void)
|
||||
{
|
||||
if ((QSPI->STS & 0x01) == 0x01)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
* @brief Check transmit fifo full or not.
|
||||
* @return 1: Transmit fifo full;0: Transmit fifo not full.
|
||||
*/
|
||||
bool GetQspiTxDataBusyStatus(void)
|
||||
{
|
||||
if ((QSPI->STS & 0x02) == 0x00)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
* @brief Check transmit fifo empty or not.
|
||||
* @return 1: Transmit fifo empty;0: Transmit fifo not empty.
|
||||
*/
|
||||
bool GetQspiTxDataEmptyStatus(void)
|
||||
{
|
||||
if ((QSPI->STS & 0x04) == 0x04)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
* @brief Check receive fifo have data or not.
|
||||
* @return 1:Receive fifo have data;0:Receive fifo empty.
|
||||
*/
|
||||
bool GetQspiRxHaveDataStatus(void)
|
||||
{
|
||||
if ((QSPI->STS & 0x08) == 0x08)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
* @brief Check receive fifo full or not.
|
||||
* @return 1: Receive fifo full;0: Receive fifo not full.
|
||||
*/
|
||||
bool GetQspiRxDataFullStatus(void)
|
||||
{
|
||||
if ((QSPI->STS & 0x10) == 0x10)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
* @brief Check transmit error or not.
|
||||
* @return 1: Transmit error;0: No transmit error.
|
||||
*/
|
||||
bool GetQspiTransmitErrorStatus(void)
|
||||
{
|
||||
if ((QSPI->STS & 0x20) == 0x20)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
* @brief Check data conflict error or not.
|
||||
* @return 1: Data conflict error;0: No data conflict error.
|
||||
*/
|
||||
bool GetQspiDataConflictErrorStatus(void)
|
||||
{
|
||||
if ((QSPI->STS & 0x40) == 0x40)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
* @brief Write one data direct to QSPI DAT0 register to send.
|
||||
* @param SendData: data to be send.
|
||||
*/
|
||||
void QspiSendWord(uint32_t SendData)
|
||||
{
|
||||
QSPI->DAT0 = SendData;
|
||||
}
|
||||
/**
|
||||
* @brief Read one data from QSPI DAT0 register.
|
||||
* @return the value of QSPI DAT0 register.
|
||||
*/
|
||||
uint32_t QspiReadWord(void)
|
||||
{
|
||||
return QSPI->DAT0;
|
||||
}
|
||||
/**
|
||||
* @brief Get Pointer of QSPI DAT0 register.
|
||||
* @return the pointer of QSPI DAT0 register.
|
||||
*/
|
||||
uint32_t QspiGetDataPointer(void)
|
||||
{
|
||||
return (uint32_t)&QSPI->DAT0;
|
||||
}
|
||||
/**
|
||||
* @brief Read value from QSPI RXFN register which shows the number of the data from receive fifo.
|
||||
* @return the number of the data from receive fifo.
|
||||
*/
|
||||
uint32_t QspiReadRxFifoNum(void)
|
||||
{
|
||||
return QSPI->RXFN;
|
||||
}
|
||||
/**
|
||||
* @brief Send words out from source data buffer and get returned datas into destination data buffer.
|
||||
* @param pSrcData pointer to buffer of sending datas.
|
||||
* @param pDstData pointer to buffer of getting returned datas.
|
||||
* @param cnt number of sending datas.
|
||||
*/
|
||||
void QspiSendAndGetWords(uint32_t* pSrcData, uint32_t* pDstData, uint32_t cnt)
|
||||
{
|
||||
uint32_t num = 0;
|
||||
uint32_t timeout = 0;
|
||||
|
||||
while (num < cnt)
|
||||
{
|
||||
QspiSendWord(*(pSrcData++));
|
||||
num++;
|
||||
}
|
||||
while (!GetQspiRxHaveDataStatus())
|
||||
{
|
||||
if(++timeout >= 200)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
timeout = 0;
|
||||
while (QSPI->RXFN < cnt)
|
||||
{
|
||||
if(++timeout >= 200)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
num = 0;
|
||||
while (num < cnt)
|
||||
{
|
||||
*(pDstData++) = QspiReadWord();
|
||||
num++;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @brief Send one word data and get returned words into destination data buffer.
|
||||
* @param WrData one word to be sent.
|
||||
* @param pRdData pointer to buffer of getting returned datas.
|
||||
* @param LastRd whether go on to get returned datas.
|
||||
1:go on to get returned datas.
|
||||
0:end to get returned datas.
|
||||
*/
|
||||
uint32_t QspiSendWordAndGetWords(uint32_t WrData, uint32_t* pRdData, uint8_t LastRd)
|
||||
{
|
||||
uint32_t sr = QSPI_NULL;
|
||||
uint32_t timeout1 = 0,timeout2 =0;
|
||||
|
||||
QspiSendWord(WrData);
|
||||
*pRdData = QspiReadWord();
|
||||
sr = QSPI_SUCCESS;
|
||||
if (LastRd != 0)
|
||||
{
|
||||
do
|
||||
{
|
||||
while (GetQspiRxHaveDataStatus())
|
||||
{
|
||||
*pRdData = QspiReadWord();
|
||||
sr = QSPI_SUCCESS;
|
||||
if(++timeout2 >= 200)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(++timeout1 >= 200)
|
||||
{
|
||||
break;
|
||||
}
|
||||
} while (GetQspiBusyStatus());
|
||||
}
|
||||
|
||||
return sr;
|
||||
}
|
||||
/**
|
||||
* @brief Read DAT0 register to clear fifo.
|
||||
*/
|
||||
void ClrFifo(void)
|
||||
{
|
||||
uint32_t data;
|
||||
uint32_t timeout = 0;
|
||||
|
||||
while (GetQspiRxHaveDataStatus())
|
||||
{
|
||||
data = QspiReadWord();
|
||||
if(++timeout >= 200)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @brief Get data from fifo.
|
||||
* @param pData pointer to buffer of getting fifo data.
|
||||
* @param Len length of getting fifo data.
|
||||
*/
|
||||
uint32_t GetFifoData(uint32_t* pData, uint32_t Len)
|
||||
{
|
||||
uint32_t cnt;
|
||||
for (cnt = 0; cnt < Len; cnt++)
|
||||
{
|
||||
if (GetQspiRxHaveDataStatus())
|
||||
{
|
||||
*pData++ = QspiReadWord();
|
||||
}
|
||||
else
|
||||
{
|
||||
return QSPI_NULL;
|
||||
}
|
||||
}
|
||||
|
||||
return QSPI_SUCCESS;
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,789 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_sdio.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x_sdio.h"
|
||||
#include "n32g45x_rcc.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO
|
||||
* @brief SDIO driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ------------ SDIO registers bit address in the alias region ----------- */
|
||||
#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CLKCTRL Register ---*/
|
||||
|
||||
/* Alias word address of CLKEN bit */
|
||||
#define CLKCTRL_OFFSET (SDIO_OFFSET + 0x04)
|
||||
#define CLKEN_BIT_NUMBER 0x08
|
||||
#define CLKCTRL_CLKEN_BB (PERIPH_BB_BASE + (CLKCTRL_OFFSET * 32) + (CLKEN_BIT_NUMBER * 4))
|
||||
|
||||
/* --- CMDCTRL Register ---*/
|
||||
|
||||
/* Alias word address of SDIOSUSPEND bit */
|
||||
#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
|
||||
#define SDIO_SUSPEND_BIT_NUMBER 0x0B
|
||||
#define CMD_SDIO_SUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIO_SUSPEND_BIT_NUMBER * 4))
|
||||
|
||||
/* Alias word address of ENCMDCOMPL bit */
|
||||
#define EN_CMD_COMPL_BIT_NUMBER 0x0C
|
||||
#define EN_CMD_COMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (EN_CMD_COMPL_BIT_NUMBER * 4))
|
||||
|
||||
/* Alias word address of NIEN bit */
|
||||
#define NIEN_BIT_NUMBER 0x0D
|
||||
#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BIT_NUMBER * 4))
|
||||
|
||||
/* Alias word address of ATACMD bit */
|
||||
#define ATACMD_BIT_NUMBER 0x0E
|
||||
#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BIT_NUMBER * 4))
|
||||
|
||||
/* --- DATCTRL Register ---*/
|
||||
|
||||
/* Alias word address of DMAEN bit */
|
||||
#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
|
||||
#define DMAEN_BIT_NUMBER 0x03
|
||||
#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BIT_NUMBER * 4))
|
||||
|
||||
/* Alias word address of RWSTART bit */
|
||||
#define RWSTART_BIT_NUMBER 0x08
|
||||
#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BIT_NUMBER * 4))
|
||||
|
||||
/* Alias word address of RWSTOP bit */
|
||||
#define RWSTOP_BIT_NUMBER 0x09
|
||||
#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BIT_NUMBER * 4))
|
||||
|
||||
/* Alias word address of RWMOD bit */
|
||||
#define RWMOD_BIT_NUMBER 0x0A
|
||||
#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BIT_NUMBER * 4))
|
||||
|
||||
/* Alias word address of SDIOEN bit */
|
||||
#define SDIOEN_BIT_NUMBER 0x0B
|
||||
#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BIT_NUMBER * 4))
|
||||
|
||||
/* ---------------------- SDIO registers bit mask ------------------------ */
|
||||
|
||||
/* --- CLKCTRL Register ---*/
|
||||
|
||||
/* CLKCTRL register clear mask */
|
||||
#define CLKCTRL_CLR_MASK ((uint32_t)0xFFFF8100)
|
||||
|
||||
/* --- PWRCTRL Register ---*/
|
||||
|
||||
/* SDIO PWRCTRL Mask */
|
||||
#define POWER_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
|
||||
|
||||
/* --- DATCTRL Register ---*/
|
||||
|
||||
/* SDIO DATCTRL Clear Mask */
|
||||
#define DATCTRL_CLR_MASK ((uint32_t)0xFFFFFF08)
|
||||
|
||||
/* --- CMDCTRL Register ---*/
|
||||
|
||||
/* CMDCTRL Register clear mask */
|
||||
#define CMD_CLR_MASK ((uint32_t)0xFFFFF800)
|
||||
|
||||
/* SDIO RESP Registers Address */
|
||||
#define SDID_RESPONSE_ADDR ((uint32_t)(SDIO_BASE + 0x14))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the SDIO peripheral registers to their default reset values.
|
||||
*/
|
||||
void SDIO_DeInit(void)
|
||||
{
|
||||
SDIO->PWRCTRL = 0x00000000;
|
||||
SDIO->CLKCTRL = 0x00000000;
|
||||
SDIO->CMDARG = 0x00000000;
|
||||
SDIO->CMDCTRL = 0x00000000;
|
||||
SDIO->DATTIMEOUT = 0x00000000;
|
||||
SDIO->DATLEN = 0x00000000;
|
||||
SDIO->DATCTRL = 0x00000000;
|
||||
SDIO->INTCLR = 0x00C007FF;
|
||||
SDIO->INTEN = 0x00000000;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the SDIO peripheral according to the specified
|
||||
* parameters in the SDIO_InitStruct.
|
||||
* @param SDIO_InitStruct pointer to a SDIO_InitType structure
|
||||
* that contains the configuration information for the SDIO peripheral.
|
||||
*/
|
||||
void SDIO_Init(SDIO_InitType* SDIO_InitStruct)
|
||||
{
|
||||
uint32_t tmpregister = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_CLK_EDGE(SDIO_InitStruct->ClkEdge));
|
||||
assert_param(IS_SDIO_CLK_BYPASS(SDIO_InitStruct->ClkBypass));
|
||||
assert_param(IS_SDIO_CLK_POWER_SAVE(SDIO_InitStruct->ClkPwrSave));
|
||||
assert_param(IS_SDIO_BUS_WIDTH(SDIO_InitStruct->BusWidth));
|
||||
assert_param(IS_SDIO_HARDWARE_CLKCTRL(SDIO_InitStruct->HardwareClkCtrl));
|
||||
|
||||
/*---------------------------- SDIO CLKCTRL Configuration ------------------------*/
|
||||
/* Get the SDIO CLKCTRL value */
|
||||
tmpregister = SDIO->CLKCTRL;
|
||||
|
||||
/* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
|
||||
tmpregister &= CLKCTRL_CLR_MASK;
|
||||
|
||||
/* Set CLKDIV bits according to ClkDiv value */
|
||||
/* Set PWRSAV bit according to ClkPwrSave value */
|
||||
/* Set BYPASS bit according to ClkBypass value */
|
||||
/* Set WIDBUS bits according to BusWidth value */
|
||||
/* Set NEGEDGE bits according to ClkEdge value */
|
||||
/* Set HWFC_EN bits according to HardwareClkCtrl value */
|
||||
tmpregister |= (SDIO_InitStruct->ClkDiv | SDIO_InitStruct->ClkPwrSave | SDIO_InitStruct->ClkBypass
|
||||
| SDIO_InitStruct->BusWidth | SDIO_InitStruct->ClkEdge | SDIO_InitStruct->HardwareClkCtrl);
|
||||
|
||||
/* Write to SDIO CLKCTRL */
|
||||
SDIO->CLKCTRL = tmpregister;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each SDIO_InitStruct member with its default value.
|
||||
* @param SDIO_InitStruct pointer to an SDIO_InitType structure which
|
||||
* will be initialized.
|
||||
*/
|
||||
void SDIO_InitStruct(SDIO_InitType* SDIO_InitStruct)
|
||||
{
|
||||
/* SDIO_InitStruct members default value */
|
||||
SDIO_InitStruct->ClkDiv = 0x00;
|
||||
SDIO_InitStruct->ClkEdge = SDIO_CLKEDGE_RISING;
|
||||
SDIO_InitStruct->ClkBypass = SDIO_ClkBYPASS_DISABLE;
|
||||
SDIO_InitStruct->ClkPwrSave = SDIO_CLKPOWERSAVE_DISABLE;
|
||||
SDIO_InitStruct->BusWidth = SDIO_BUSWIDTH_1B;
|
||||
SDIO_InitStruct->HardwareClkCtrl = SDIO_HARDWARE_CLKCTRL_DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SDIO Clock.
|
||||
* @param Cmd new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void SDIO_EnableClock(FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
*(__IO uint32_t*)CLKCTRL_CLKEN_BB = (uint32_t)Cmd;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the power status of the controller.
|
||||
* @param SDIO_PowerState new state of the Power state.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_POWER_CTRL_OFF
|
||||
* @arg SDIO_POWER_CTRL_ON
|
||||
*/
|
||||
void SDIO_SetPower(uint32_t SDIO_PowerState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_POWER_CTRL(SDIO_PowerState));
|
||||
|
||||
SDIO->PWRCTRL &= POWER_PWRCTRL_MASK;
|
||||
SDIO->PWRCTRL |= SDIO_PowerState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the power status of the controller.
|
||||
* @return Power status of the controller. The returned value can
|
||||
* be one of the following:
|
||||
* - 0x00: Power OFF
|
||||
* - 0x02: Power UP
|
||||
* - 0x03: Power ON
|
||||
*/
|
||||
uint32_t SDIO_GetPower(void)
|
||||
{
|
||||
return (SDIO->PWRCTRL & (~POWER_PWRCTRL_MASK));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SDIO interrupts.
|
||||
* @param SDIO_IT specifies the SDIO interrupt sources to be enabled or disabled.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_INT_CCRCERR Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_INT_DCRCERR Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_INT_CMDTIMEOUT Command response timeout interrupt
|
||||
* @arg SDIO_INT_DATTIMEOUT Data timeout interrupt
|
||||
* @arg SDIO_INT_TXURERR Transmit DATFIFO underrun error interrupt
|
||||
* @arg SDIO_INT_RXORERR Received DATFIFO overrun error interrupt
|
||||
* @arg SDIO_INT_CMDRESPRECV Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_INT_CMDSEND Command sent (no response required) interrupt
|
||||
* @arg SDIO_INT_DATEND Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDIO_INT_SBERR Start bit not detected on all data signals in wide
|
||||
* bus mode interrupt
|
||||
* @arg SDIO_INT_DATBLKEND Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDIO_INT_CMDRUN Command transfer in progress interrupt
|
||||
* @arg SDIO_INT_TXRUN Data transmit in progress interrupt
|
||||
* @arg SDIO_INT_RXRUN Data receive in progress interrupt
|
||||
* @arg SDIO_INT_TFIFOHE Transmit DATFIFO Half Empty interrupt
|
||||
* @arg SDIO_INT_RFIFOHF Receive DATFIFO Half Full interrupt
|
||||
* @arg SDIO_INT_TFIFOF Transmit DATFIFO full interrupt
|
||||
* @arg SDIO_INT_RFIFOF Receive DATFIFO full interrupt
|
||||
* @arg SDIO_INT_TFIFOE Transmit DATFIFO empty interrupt
|
||||
* @arg SDIO_INT_RFIFOE Receive DATFIFO empty interrupt
|
||||
* @arg SDIO_INT_TDATVALID Data available in transmit DATFIFO interrupt
|
||||
* @arg SDIO_INT_RDATVALID Data available in receive DATFIFO interrupt
|
||||
* @arg SDIO_INT_SDIOINT SD I/O interrupt received interrupt
|
||||
* @arg SDIO_INT_CEATAF CE-ATA command completion signal received for CMD61 interrupt
|
||||
* @param Cmd new state of the specified SDIO interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void SDIO_ConfigInt(uint32_t SDIO_IT, FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_INT(SDIO_IT));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
/* Enable the SDIO interrupts */
|
||||
SDIO->INTEN |= SDIO_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the SDIO interrupts */
|
||||
SDIO->INTEN &= ~SDIO_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SDIO DMA request.
|
||||
* @param Cmd new state of the selected SDIO DMA request.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void SDIO_EnableCmd(FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
*(__IO uint32_t*)DCTRL_DMAEN_BB = (uint32_t)Cmd;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the SDIO Command according to the specified
|
||||
* parameters in the SDIO_CmdInitStruct and send the command.
|
||||
* @param SDIO_CmdInitStruct pointer to a SDIO_CmdInitType
|
||||
* structure that contains the configuration information for the SDIO command.
|
||||
*/
|
||||
void SDIO_SendCmd(SDIO_CmdInitType* SDIO_CmdInitStruct)
|
||||
{
|
||||
uint32_t tmpregister = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->CmdIndex));
|
||||
assert_param(IS_SDIO_RESP(SDIO_CmdInitStruct->ResponseType));
|
||||
assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->WaitType));
|
||||
assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->CPSMConfig));
|
||||
|
||||
/*---------------------------- SDIO CMDARG Configuration ------------------------*/
|
||||
/* Set the SDIO Argument value */
|
||||
SDIO->CMDARG = SDIO_CmdInitStruct->CmdArgument;
|
||||
|
||||
/*---------------------------- SDIO CMDCTRL Configuration ------------------------*/
|
||||
/* Get the SDIO CMDCTRL value */
|
||||
tmpregister = SDIO->CMDCTRL;
|
||||
/* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
|
||||
tmpregister &= CMD_CLR_MASK;
|
||||
/* Set CMDINDEX bits according to CmdIndex value */
|
||||
/* Set WAITRESP bits according to ResponseType value */
|
||||
/* Set WAITINT and WAITPEND bits according to WaitType value */
|
||||
/* Set CPSMEN bits according to CPSMConfig value */
|
||||
tmpregister |= (uint32_t)SDIO_CmdInitStruct->CmdIndex | SDIO_CmdInitStruct->ResponseType
|
||||
| SDIO_CmdInitStruct->WaitType | SDIO_CmdInitStruct->CPSMConfig;
|
||||
|
||||
/* Write to SDIO CMDCTRL */
|
||||
SDIO->CMDCTRL = tmpregister;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each SDIO_CmdInitStruct member with its default value.
|
||||
* @param SDIO_CmdInitStruct pointer to an SDIO_CmdInitType
|
||||
* structure which will be initialized.
|
||||
*/
|
||||
void SDIO_InitCmdStruct(SDIO_CmdInitType* SDIO_CmdInitStruct)
|
||||
{
|
||||
/* SDIO_CmdInitStruct members default value */
|
||||
SDIO_CmdInitStruct->CmdArgument = 0x00;
|
||||
SDIO_CmdInitStruct->CmdIndex = 0x00;
|
||||
SDIO_CmdInitStruct->ResponseType = SDIO_RESP_NO;
|
||||
SDIO_CmdInitStruct->WaitType = SDIO_WAIT_NO;
|
||||
SDIO_CmdInitStruct->CPSMConfig = SDIO_CPSM_DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns command index of last command for which response received.
|
||||
* @return Returns the command index of the last command response received.
|
||||
*/
|
||||
uint8_t SDIO_GetCmdResp(void)
|
||||
{
|
||||
return (uint8_t)(SDIO->CMDRESP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns response received from the card for the last command.
|
||||
* @param SDIO_RESP Specifies the SDIO response register.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_RESPONSE_1 Response Register 1
|
||||
* @arg SDIO_RESPONSE_2 Response Register 2
|
||||
* @arg SDIO_RESPONSE_3 Response Register 3
|
||||
* @arg SDIO_RESPONSE_4 Response Register 4
|
||||
* @return The Corresponding response register value.
|
||||
*/
|
||||
uint32_t SDIO_GetResp(uint32_t SDIO_RESP)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_RESPONSE(SDIO_RESP));
|
||||
|
||||
tmp = SDID_RESPONSE_ADDR + SDIO_RESP;
|
||||
|
||||
return (*(__IO uint32_t*)tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the SDIO data path according to the specified
|
||||
* parameters in the SDIO_DataInitStruct.
|
||||
* @param SDIO_DataInitStruct pointer to a SDIO_DataInitType structure that
|
||||
* contains the configuration information for the SDIO command.
|
||||
*/
|
||||
void SDIO_ConfigData(SDIO_DataInitType* SDIO_DataInitStruct)
|
||||
{
|
||||
uint32_t tmpregister = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_DAT_LEN(SDIO_DataInitStruct->DatLen));
|
||||
assert_param(IS_SDIO_BLK_SIZE(SDIO_DataInitStruct->DatBlkSize));
|
||||
assert_param(IS_SDIO_TRANSFER_DIRECTION(SDIO_DataInitStruct->TransferDirection));
|
||||
assert_param(IS_SDIO_TRANS_MODE(SDIO_DataInitStruct->TransferMode));
|
||||
assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSMConfig));
|
||||
|
||||
/*---------------------------- SDIO DATTIMEOUT Configuration ---------------------*/
|
||||
/* Set the SDIO Data TimeOut value */
|
||||
SDIO->DATTIMEOUT = SDIO_DataInitStruct->DatTimeout;
|
||||
|
||||
/*---------------------------- SDIO DATLEN Configuration -----------------------*/
|
||||
/* Set the SDIO DataLength value */
|
||||
SDIO->DATLEN = SDIO_DataInitStruct->DatLen;
|
||||
|
||||
/*---------------------------- SDIO DATCTRL Configuration ----------------------*/
|
||||
/* Get the SDIO DATCTRL value */
|
||||
tmpregister = SDIO->DATCTRL;
|
||||
/* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
|
||||
tmpregister &= DATCTRL_CLR_MASK;
|
||||
/* Set DEN bit according to DPSMConfig value */
|
||||
/* Set DTMODE bit according to TransferMode value */
|
||||
/* Set DTDIR bit according to TransferDirection value */
|
||||
/* Set DBCKSIZE bits according to DatBlkSize value */
|
||||
tmpregister |= (uint32_t)SDIO_DataInitStruct->DatBlkSize | SDIO_DataInitStruct->TransferDirection
|
||||
| SDIO_DataInitStruct->TransferMode | SDIO_DataInitStruct->DPSMConfig;
|
||||
|
||||
if(SDIO_DataInitStruct->TransferDirection)
|
||||
{
|
||||
tmpregister &= ~(1<<12);
|
||||
}
|
||||
else
|
||||
{
|
||||
tmpregister |= 1<<12;
|
||||
}
|
||||
|
||||
/* Write to SDIO DATCTRL */
|
||||
SDIO->DATCTRL = tmpregister;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each SDIO_DataInitStruct member with its default value.
|
||||
* @param SDIO_DataInitStruct pointer to an SDIO_DataInitType structure which
|
||||
* will be initialized.
|
||||
*/
|
||||
void SDIO_InitDataStruct(SDIO_DataInitType* SDIO_DataInitStruct)
|
||||
{
|
||||
/* SDIO_DataInitStruct members default value */
|
||||
SDIO_DataInitStruct->DatTimeout = 0xFFFFFFFF;
|
||||
SDIO_DataInitStruct->DatLen = 0x00;
|
||||
SDIO_DataInitStruct->DatBlkSize = SDIO_DATBLK_SIZE_1B;
|
||||
SDIO_DataInitStruct->TransferDirection = SDIO_TRANSDIR_TOCARD;
|
||||
SDIO_DataInitStruct->TransferMode = SDIO_TRANSMODE_BLOCK;
|
||||
SDIO_DataInitStruct->DPSMConfig = SDIO_DPSM_DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns number of remaining data bytes to be transferred.
|
||||
* @return Number of remaining data bytes to be transferred
|
||||
*/
|
||||
uint32_t SDIO_GetDataCountValue(void)
|
||||
{
|
||||
return SDIO->DATCOUNT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read one data word from Rx DATFIFO.
|
||||
* @return Data received
|
||||
*/
|
||||
uint32_t SDIO_ReadData(void)
|
||||
{
|
||||
return SDIO->DATFIFO;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write one data word to Tx DATFIFO.
|
||||
* @param Data 32-bit data word to write.
|
||||
*/
|
||||
void SDIO_WriteData(uint32_t Data)
|
||||
{
|
||||
SDIO->DATFIFO = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the number of words left to be written to or read from DATFIFO.
|
||||
* @return Remaining number of words.
|
||||
*/
|
||||
uint32_t SDIO_GetFifoCounter(void)
|
||||
{
|
||||
return SDIO->FIFOCOUNT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Starts the SD I/O Read Wait operation.
|
||||
* @param Cmd new state of the Start SDIO Read Wait operation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void SDIO_EnableReadWait(FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
*(__IO uint32_t*)DCTRL_RWSTART_BB = (uint32_t)Cmd;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stops the SD I/O Read Wait operation.
|
||||
* @param Cmd new state of the Stop SDIO Read Wait operation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void SDIO_DisableReadWait(FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
*(__IO uint32_t*)DCTRL_RWSTOP_BB = (uint32_t)Cmd;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets one of the two options of inserting read wait interval.
|
||||
* @param SDIO_ReadWaitMode SD I/O Read Wait operation mode.
|
||||
* This parameter can be:
|
||||
* @arg SDIO_RDWAIT_MODE_CLK Read Wait control by stopping SDIOCLK
|
||||
* @arg SDIO_RDWAIT_MODE_DAT2 Read Wait control using SDIO_DATA2
|
||||
*/
|
||||
void SDIO_EnableSdioReadWaitMode(uint32_t SDIO_ReadWaitMode)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_RDWAIT_MODE(SDIO_ReadWaitMode));
|
||||
|
||||
*(__IO uint32_t*)DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SD I/O Mode Operation.
|
||||
* @param Cmd new state of SDIO specific operation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void SDIO_EnableSdioOperation(FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
*(__IO uint32_t*)DCTRL_SDIOEN_BB = (uint32_t)Cmd;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SD I/O Mode suspend command sending.
|
||||
* @param Cmd new state of the SD I/O Mode suspend command.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void SDIO_EnableSendSdioSuspend(FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
*(__IO uint32_t*)CMD_SDIO_SUSPEND_BB = (uint32_t)Cmd;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the command completion signal.
|
||||
* @param Cmd new state of command completion signal.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void SDIO_EnableCommandCompletion(FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
*(__IO uint32_t*)EN_CMD_COMPL_BB = (uint32_t)Cmd;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the CE-ATA interrupt.
|
||||
* @param Cmd new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void SDIO_EnableCEATAInt(FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
*(__IO uint32_t*)CMD_NIEN_BB = (uint32_t)((~((uint32_t)Cmd)) & ((uint32_t)0x1));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sends CE-ATA command (CMD61).
|
||||
* @param Cmd new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void SDIO_EnableSendCEATA(FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
*(__IO uint32_t*)CMD_ATACMD_BB = (uint32_t)Cmd;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified SDIO flag is set or not.
|
||||
* @param SDIO_FLAG specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_FLAG_CCRCERR Command response received (CRC check failed)
|
||||
* @arg SDIO_FLAG_DCRCERR Data block sent/received (CRC check failed)
|
||||
* @arg SDIO_FLAG_CMDTIMEOUT Command response timeout
|
||||
* @arg SDIO_FLAG_DATTIMEOUT Data timeout
|
||||
* @arg SDIO_FLAG_TXURERR Transmit DATFIFO underrun error
|
||||
* @arg SDIO_FLAG_RXORERR Received DATFIFO overrun error
|
||||
* @arg SDIO_FLAG_CMDRESPRECV Command response received (CRC check passed)
|
||||
* @arg SDIO_FLAG_CMDSEND Command sent (no response required)
|
||||
* @arg SDIO_FLAG_DATEND Data end (data counter, SDIDCOUNT, is zero)
|
||||
* @arg SDIO_FLAG_SBERR Start bit not detected on all data signals in wide
|
||||
* bus mode.
|
||||
* @arg SDIO_FLAG_DATBLKEND Data block sent/received (CRC check passed)
|
||||
* @arg SDIO_FLAG_CMDRUN Command transfer in progress
|
||||
* @arg SDIO_FLAG_TXRUN Data transmit in progress
|
||||
* @arg SDIO_FLAG_RXRUN Data receive in progress
|
||||
* @arg SDIO_FLAG_TFIFOHE Transmit DATFIFO Half Empty
|
||||
* @arg SDIO_FLAG_RFIFOHF Receive DATFIFO Half Full
|
||||
* @arg SDIO_FLAG_TFIFOF Transmit DATFIFO full
|
||||
* @arg SDIO_FLAG_RFIFOF Receive DATFIFO full
|
||||
* @arg SDIO_FLAG_TFIFOE Transmit DATFIFO empty
|
||||
* @arg SDIO_FLAG_RFIFOE Receive DATFIFO empty
|
||||
* @arg SDIO_FLAG_TDATVALID Data available in transmit DATFIFO
|
||||
* @arg SDIO_FLAG_RDATVALID Data available in receive DATFIFO
|
||||
* @arg SDIO_FLAG_SDIOINT SD I/O interrupt received
|
||||
* @arg SDIO_FLAG_CEATAF CE-ATA command completion signal received for CMD61
|
||||
* @return The new state of SDIO_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus SDIO_GetFlag(uint32_t SDIO_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_FLAG(SDIO_FLAG));
|
||||
|
||||
if ((SDIO->STS & SDIO_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the SDIO's pending flags.
|
||||
* @param SDIO_FLAG specifies the flag to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_FLAG_CCRCERR Command response received (CRC check failed)
|
||||
* @arg SDIO_FLAG_DCRCERR Data block sent/received (CRC check failed)
|
||||
* @arg SDIO_FLAG_CMDTIMEOUT Command response timeout
|
||||
* @arg SDIO_FLAG_DATTIMEOUT Data timeout
|
||||
* @arg SDIO_FLAG_TXURERR Transmit DATFIFO underrun error
|
||||
* @arg SDIO_FLAG_RXORERR Received DATFIFO overrun error
|
||||
* @arg SDIO_FLAG_CMDRESPRECV Command response received (CRC check passed)
|
||||
* @arg SDIO_FLAG_CMDSEND Command sent (no response required)
|
||||
* @arg SDIO_FLAG_DATEND Data end (data counter, SDIDCOUNT, is zero)
|
||||
* @arg SDIO_FLAG_SBERR Start bit not detected on all data signals in wide
|
||||
* bus mode
|
||||
* @arg SDIO_FLAG_DATBLKEND Data block sent/received (CRC check passed)
|
||||
* @arg SDIO_FLAG_SDIOINT SD I/O interrupt received
|
||||
* @arg SDIO_FLAG_CEATAF CE-ATA command completion signal received for CMD61
|
||||
*/
|
||||
void SDIO_ClrFlag(uint32_t SDIO_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_CLR_FLAG(SDIO_FLAG));
|
||||
|
||||
SDIO->INTCLR = SDIO_FLAG;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified SDIO interrupt has occurred or not.
|
||||
* @param SDIO_IT specifies the SDIO interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_INT_CCRCERR Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_INT_DCRCERR Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_INT_CMDTIMEOUT Command response timeout interrupt
|
||||
* @arg SDIO_INT_DATTIMEOUT Data timeout interrupt
|
||||
* @arg SDIO_INT_TXURERR Transmit DATFIFO underrun error interrupt
|
||||
* @arg SDIO_INT_RXORERR Received DATFIFO overrun error interrupt
|
||||
* @arg SDIO_INT_CMDRESPRECV Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_INT_CMDSEND Command sent (no response required) interrupt
|
||||
* @arg SDIO_INT_DATEND Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDIO_INT_SBERR Start bit not detected on all data signals in wide
|
||||
* bus mode interrupt
|
||||
* @arg SDIO_INT_DATBLKEND Data block sent/received (CRC check passed) interrupt
|
||||
* @arg SDIO_INT_CMDRUN Command transfer in progress interrupt
|
||||
* @arg SDIO_INT_TXRUN Data transmit in progress interrupt
|
||||
* @arg SDIO_INT_RXRUN Data receive in progress interrupt
|
||||
* @arg SDIO_INT_TFIFOHE Transmit DATFIFO Half Empty interrupt
|
||||
* @arg SDIO_INT_RFIFOHF Receive DATFIFO Half Full interrupt
|
||||
* @arg SDIO_INT_TFIFOF Transmit DATFIFO full interrupt
|
||||
* @arg SDIO_INT_RFIFOF Receive DATFIFO full interrupt
|
||||
* @arg SDIO_INT_TFIFOE Transmit DATFIFO empty interrupt
|
||||
* @arg SDIO_INT_RFIFOE Receive DATFIFO empty interrupt
|
||||
* @arg SDIO_INT_TDATVALID Data available in transmit DATFIFO interrupt
|
||||
* @arg SDIO_INT_RDATVALID Data available in receive DATFIFO interrupt
|
||||
* @arg SDIO_INT_SDIOINT SD I/O interrupt received interrupt
|
||||
* @arg SDIO_INT_CEATAF CE-ATA command completion signal received for CMD61 interrupt
|
||||
* @return The new state of SDIO_IT (SET or RESET).
|
||||
*/
|
||||
INTStatus SDIO_GetIntStatus(uint32_t SDIO_IT)
|
||||
{
|
||||
INTStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_GET_INT(SDIO_IT));
|
||||
if ((SDIO->STS & SDIO_IT) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the SDIO's interrupt pending bits.
|
||||
* @param SDIO_IT specifies the interrupt pending bit to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_INT_CCRCERR Command response received (CRC check failed) interrupt
|
||||
* @arg SDIO_INT_DCRCERR Data block sent/received (CRC check failed) interrupt
|
||||
* @arg SDIO_INT_CMDTIMEOUT Command response timeout interrupt
|
||||
* @arg SDIO_INT_DATTIMEOUT Data timeout interrupt
|
||||
* @arg SDIO_INT_TXURERR Transmit DATFIFO underrun error interrupt
|
||||
* @arg SDIO_INT_RXORERR Received DATFIFO overrun error interrupt
|
||||
* @arg SDIO_INT_CMDRESPRECV Command response received (CRC check passed) interrupt
|
||||
* @arg SDIO_INT_CMDSEND Command sent (no response required) interrupt
|
||||
* @arg SDIO_INT_DATEND Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||
* @arg SDIO_INT_SBERR Start bit not detected on all data signals in wide
|
||||
* bus mode interrupt
|
||||
* @arg SDIO_INT_SDIOINT SD I/O interrupt received interrupt
|
||||
* @arg SDIO_INT_CEATAF CE-ATA command completion signal received for CMD61
|
||||
*/
|
||||
void SDIO_ClrIntPendingBit(uint32_t SDIO_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_CLR_INT(SDIO_IT));
|
||||
|
||||
SDIO->INTCLR = SDIO_IT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,862 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_spi.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x_spi.h"
|
||||
#include "n32g45x_rcc.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @brief SPI driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SPI SPE mask */
|
||||
#define CTRL1_SPIEN_ENABLE ((uint16_t)0x0040)
|
||||
#define CTRL1_SPIEN_DISABLE ((uint16_t)0xFFBF)
|
||||
|
||||
/* I2S I2SE mask */
|
||||
#define I2SCFG_I2SEN_ENABLE ((uint16_t)0x0400)
|
||||
#define I2SCFG_I2SEN_DISABLE ((uint16_t)0xFBFF)
|
||||
|
||||
/* SPI CRCNext mask */
|
||||
#define CTRL1_CRCNEXT_ENABLE ((uint16_t)0x1000)
|
||||
|
||||
/* SPI CRCEN mask */
|
||||
#define CTRL1_CRCEN_ENABLE ((uint16_t)0x2000)
|
||||
#define CTRL1_CRCEN_DISABLE ((uint16_t)0xDFFF)
|
||||
|
||||
/* SPI SSOE mask */
|
||||
#define CTRL2_SSOEN_ENABLE ((uint16_t)0x0004)
|
||||
#define CTRL2_SSOEN_DISABLE ((uint16_t)0xFFFB)
|
||||
|
||||
/* SPI registers Masks */
|
||||
#define CTRL1_CLR_MASK ((uint16_t)0x3040)
|
||||
#define I2SCFG_CLR_MASK ((uint16_t)0xF040)
|
||||
|
||||
/* SPI or I2S mode selection masks */
|
||||
#define SPI_MODE_ENABLE ((uint16_t)0xF7FF)
|
||||
#define I2S_MODE_ENABLE ((uint16_t)0x0800)
|
||||
|
||||
/* I2S clock source selection masks */
|
||||
#define I2S2_CLKSRC ((uint32_t)(0x00020000))
|
||||
#define I2S3_CLKSRC ((uint32_t)(0x00040000))
|
||||
#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
|
||||
#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the SPIx peripheral registers to their default
|
||||
* reset values (Affects also the I2Ss).
|
||||
* @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
*/
|
||||
void SPI_I2S_DeInit(SPI_Module* SPIx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
|
||||
if (SPIx == SPI1)
|
||||
{
|
||||
/* Enable SPI1 reset state */
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, ENABLE);
|
||||
/* Release SPI1 from reset state */
|
||||
RCC_EnableAPB2PeriphReset(RCC_APB2_PERIPH_SPI1, DISABLE);
|
||||
}
|
||||
else if (SPIx == SPI2)
|
||||
{
|
||||
/* Enable SPI2 reset state */
|
||||
RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_SPI2, ENABLE);
|
||||
/* Release SPI2 from reset state */
|
||||
RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_SPI2, DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (SPIx == SPI3)
|
||||
{
|
||||
/* Enable SPI3 reset state */
|
||||
RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_SPI3, ENABLE);
|
||||
/* Release SPI3 from reset state */
|
||||
RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_SPI3, DISABLE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the SPIx peripheral according to the specified
|
||||
* parameters in the SPI_InitStruct.
|
||||
* @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param SPI_InitStruct pointer to a SPI_InitType structure that
|
||||
* contains the configuration information for the specified SPI peripheral.
|
||||
*/
|
||||
void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct)
|
||||
{
|
||||
uint16_t tmpregister = 0;
|
||||
|
||||
/* check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
|
||||
/* Check the SPI parameters */
|
||||
assert_param(IS_SPI_DIR_MODE(SPI_InitStruct->DataDirection));
|
||||
assert_param(IS_SPI_MODE(SPI_InitStruct->SpiMode));
|
||||
assert_param(IS_SPI_DATASIZE(SPI_InitStruct->DataLen));
|
||||
assert_param(IS_SPI_CLKPOL(SPI_InitStruct->CLKPOL));
|
||||
assert_param(IS_SPI_CLKPHA(SPI_InitStruct->CLKPHA));
|
||||
assert_param(IS_SPI_NSS(SPI_InitStruct->NSS));
|
||||
assert_param(IS_SPI_BR_PRESCALER(SPI_InitStruct->BaudRatePres));
|
||||
assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->FirstBit));
|
||||
assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
|
||||
|
||||
/*---------------------------- SPIx CTRL1 Configuration ------------------------*/
|
||||
/* Get the SPIx CTRL1 value */
|
||||
tmpregister = SPIx->CTRL1;
|
||||
/* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
|
||||
tmpregister &= CTRL1_CLR_MASK;
|
||||
/* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
|
||||
master/salve mode, CPOL and CPHA */
|
||||
/* Set BIDImode, BIDIOE and RxONLY bits according to DataDirection value */
|
||||
/* Set SSM, SSI and MSTR bits according to SpiMode and NSS values */
|
||||
/* Set LSBFirst bit according to FirstBit value */
|
||||
/* Set BR bits according to BaudRatePres value */
|
||||
/* Set CPOL bit according to CLKPOL value */
|
||||
/* Set CPHA bit according to CLKPHA value */
|
||||
tmpregister |= (uint16_t)((uint32_t)SPI_InitStruct->DataDirection | SPI_InitStruct->SpiMode
|
||||
| SPI_InitStruct->DataLen | SPI_InitStruct->CLKPOL | SPI_InitStruct->CLKPHA
|
||||
| SPI_InitStruct->NSS | SPI_InitStruct->BaudRatePres | SPI_InitStruct->FirstBit);
|
||||
/* Write to SPIx CTRL1 */
|
||||
SPIx->CTRL1 = tmpregister;
|
||||
|
||||
/* Activate the SPI mode (Reset I2SMOD bit in I2SCFG register) */
|
||||
SPIx->I2SCFG &= SPI_MODE_ENABLE;
|
||||
|
||||
/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
|
||||
/* Write to SPIx CRCPOLY */
|
||||
SPIx->CRCPOLY = SPI_InitStruct->CRCPoly;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the SPIx peripheral according to the specified
|
||||
* parameters in the I2S_InitStruct.
|
||||
* @param SPIx where x can be 2 or 3 to select the SPI peripheral
|
||||
* (configured in I2S mode).
|
||||
* @param I2S_InitStruct pointer to an I2S_InitType structure that
|
||||
* contains the configuration information for the specified SPI peripheral
|
||||
* configured in I2S mode.
|
||||
* @note
|
||||
* The function calculates the optimal prescaler needed to obtain the most
|
||||
* accurate audio frequency (depending on the I2S clock source, the PLL values
|
||||
* and the product configuration). But in case the prescaler value is greater
|
||||
* than 511, the default value (0x02) will be configured instead. *
|
||||
*/
|
||||
void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct)
|
||||
{
|
||||
uint16_t tmpregister = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
|
||||
uint32_t tmp = 0;
|
||||
RCC_ClocksType RCC_Clocks;
|
||||
uint32_t sourceclock = 0;
|
||||
|
||||
/* Check the I2S parameters */
|
||||
assert_param(IS_SPI_2OR3_PERIPH(SPIx));
|
||||
assert_param(IS_I2S_MODE(I2S_InitStruct->I2sMode));
|
||||
assert_param(IS_I2S_STANDARD(I2S_InitStruct->Standard));
|
||||
assert_param(IS_I2S_DATA_FMT(I2S_InitStruct->DataFormat));
|
||||
assert_param(IS_I2S_MCLK_ENABLE(I2S_InitStruct->MCLKEnable));
|
||||
assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFrequency));
|
||||
assert_param(IS_I2S_CLKPOL(I2S_InitStruct->CLKPOL));
|
||||
|
||||
/*----------------------- SPIx I2SCFG & I2SPREDIV Configuration -----------------*/
|
||||
/* Clear I2SMOD, I2SE, MODCFG, PCMSYNC, STDSEL, CKPOL, TDATLEN and CHLEN bits */
|
||||
SPIx->I2SCFG &= I2SCFG_CLR_MASK;
|
||||
SPIx->I2SPREDIV = 0x0002;
|
||||
|
||||
/* Get the I2SCFG register value */
|
||||
tmpregister = SPIx->I2SCFG;
|
||||
|
||||
/* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
|
||||
if (I2S_InitStruct->AudioFrequency == I2S_AUDIO_FREQ_DEFAULT)
|
||||
{
|
||||
i2sodd = (uint16_t)0;
|
||||
i2sdiv = (uint16_t)2;
|
||||
}
|
||||
/* If the requested audio frequency is not the default, compute the prescaler */
|
||||
else
|
||||
{
|
||||
/* Check the frame length (For the Prescaler computing) */
|
||||
if (I2S_InitStruct->DataFormat == I2S_DATA_FMT_16BITS)
|
||||
{
|
||||
/* Packet length is 16 bits */
|
||||
packetlength = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Packet length is 32 bits */
|
||||
packetlength = 2;
|
||||
}
|
||||
|
||||
/* Get the I2S clock source mask depending on the peripheral number */
|
||||
if (((uint32_t)SPIx) == SPI2_BASE)
|
||||
{
|
||||
/* The mask is relative to I2S2 */
|
||||
tmp = I2S2_CLKSRC;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The mask is relative to I2S3 */
|
||||
tmp = I2S3_CLKSRC;
|
||||
}
|
||||
|
||||
/* I2S Clock source is System clock: Get System Clock frequency */
|
||||
RCC_GetClocksFreqValue(&RCC_Clocks);
|
||||
|
||||
/* Get the source clock value: based on System Clock value */
|
||||
sourceclock = RCC_Clocks.SysclkFreq;
|
||||
|
||||
/* Compute the Real divider depending on the MCLK output state with a floating point */
|
||||
if (I2S_InitStruct->MCLKEnable == I2S_MCLK_ENABLE)
|
||||
{
|
||||
/* MCLK output is enabled */
|
||||
tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->AudioFrequency)) + 5);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* MCLK output is disabled */
|
||||
tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->AudioFrequency)) + 5);
|
||||
}
|
||||
|
||||
/* Remove the floating point */
|
||||
tmp = tmp / 10;
|
||||
|
||||
/* Check the parity of the divider */
|
||||
i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
|
||||
|
||||
/* Compute the i2sdiv prescaler */
|
||||
i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
|
||||
|
||||
/* Get the Mask for the Odd bit (SPI_I2SPREDIV[8]) register */
|
||||
i2sodd = (uint16_t)(i2sodd << 8);
|
||||
}
|
||||
|
||||
/* Test if the divider is 1 or 0 or greater than 0xFF */
|
||||
if ((i2sdiv < 2) || (i2sdiv > 0xFF))
|
||||
{
|
||||
/* Set the default values */
|
||||
i2sdiv = 2;
|
||||
i2sodd = 0;
|
||||
}
|
||||
|
||||
/* Write to SPIx I2SPREDIV register the computed value */
|
||||
SPIx->I2SPREDIV = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->MCLKEnable));
|
||||
|
||||
/* Configure the I2S with the SPI_InitStruct values */
|
||||
tmpregister |= (uint16_t)(
|
||||
I2S_MODE_ENABLE
|
||||
| (uint16_t)(I2S_InitStruct->I2sMode
|
||||
| (uint16_t)(I2S_InitStruct->Standard
|
||||
| (uint16_t)(I2S_InitStruct->DataFormat | (uint16_t)I2S_InitStruct->CLKPOL))));
|
||||
|
||||
/* Write to SPIx I2SCFG */
|
||||
SPIx->I2SCFG = tmpregister;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each SPI_InitStruct member with its default value.
|
||||
* @param SPI_InitStruct pointer to a SPI_InitType structure which will be initialized.
|
||||
*/
|
||||
void SPI_InitStruct(SPI_InitType* SPI_InitStruct)
|
||||
{
|
||||
/*--------------- Reset SPI init structure parameters values -----------------*/
|
||||
/* Initialize the DataDirection member */
|
||||
SPI_InitStruct->DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX;
|
||||
/* initialize the SpiMode member */
|
||||
SPI_InitStruct->SpiMode = SPI_MODE_SLAVE;
|
||||
/* initialize the DataLen member */
|
||||
SPI_InitStruct->DataLen = SPI_DATA_SIZE_8BITS;
|
||||
/* Initialize the CLKPOL member */
|
||||
SPI_InitStruct->CLKPOL = SPI_CLKPOL_LOW;
|
||||
/* Initialize the CLKPHA member */
|
||||
SPI_InitStruct->CLKPHA = SPI_CLKPHA_FIRST_EDGE;
|
||||
/* Initialize the NSS member */
|
||||
SPI_InitStruct->NSS = SPI_NSS_HARD;
|
||||
/* Initialize the BaudRatePres member */
|
||||
SPI_InitStruct->BaudRatePres = SPI_BR_PRESCALER_2;
|
||||
/* Initialize the FirstBit member */
|
||||
SPI_InitStruct->FirstBit = SPI_FB_MSB;
|
||||
/* Initialize the CRCPoly member */
|
||||
SPI_InitStruct->CRCPoly = 7;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each I2S_InitStruct member with its default value.
|
||||
* @param I2S_InitStruct pointer to a I2S_InitType structure which will be initialized.
|
||||
*/
|
||||
void I2S_InitStruct(I2S_InitType* I2S_InitStruct)
|
||||
{
|
||||
/*--------------- Reset I2S init structure parameters values -----------------*/
|
||||
/* Initialize the I2sMode member */
|
||||
I2S_InitStruct->I2sMode = I2S_MODE_SlAVE_TX;
|
||||
|
||||
/* Initialize the Standard member */
|
||||
I2S_InitStruct->Standard = I2S_STD_PHILLIPS;
|
||||
|
||||
/* Initialize the DataFormat member */
|
||||
I2S_InitStruct->DataFormat = I2S_DATA_FMT_16BITS;
|
||||
|
||||
/* Initialize the MCLKEnable member */
|
||||
I2S_InitStruct->MCLKEnable = I2S_MCLK_DISABLE;
|
||||
|
||||
/* Initialize the AudioFrequency member */
|
||||
I2S_InitStruct->AudioFrequency = I2S_AUDIO_FREQ_DEFAULT;
|
||||
|
||||
/* Initialize the CLKPOL member */
|
||||
I2S_InitStruct->CLKPOL = I2S_CLKPOL_LOW;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified SPI peripheral.
|
||||
* @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param Cmd new state of the SPIx peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI peripheral */
|
||||
SPIx->CTRL1 |= CTRL1_SPIEN_ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI peripheral */
|
||||
SPIx->CTRL1 &= CTRL1_SPIEN_DISABLE;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified SPI peripheral (in I2S mode).
|
||||
* @param SPIx where x can be 2 or 3 to select the SPI peripheral.
|
||||
* @param Cmd new state of the SPIx peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_2OR3_PERIPH(SPIx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI peripheral (in I2S mode) */
|
||||
SPIx->I2SCFG |= I2SCFG_I2SEN_ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI peripheral (in I2S mode) */
|
||||
SPIx->I2SCFG &= I2SCFG_I2SEN_DISABLE;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified SPI/I2S interrupts.
|
||||
* @param SPIx where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* - 2 or 3 in I2S mode
|
||||
* @param SPI_I2S_IT specifies the SPI/I2S interrupt source to be enabled or disabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_I2S_INT_TE Tx buffer empty interrupt mask
|
||||
* @arg SPI_I2S_INT_RNE Rx buffer not empty interrupt mask
|
||||
* @arg SPI_I2S_INT_ERR Error interrupt mask
|
||||
* @param Cmd new state of the specified SPI/I2S interrupt.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd)
|
||||
{
|
||||
uint16_t itpos = 0, itmask = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
assert_param(IS_SPI_I2S_CONFIG_INT(SPI_I2S_IT));
|
||||
|
||||
/* Get the SPI/I2S IT index */
|
||||
itpos = SPI_I2S_IT >> 4;
|
||||
|
||||
/* Set the IT mask */
|
||||
itmask = (uint16_t)1 << (uint16_t)itpos;
|
||||
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI/I2S interrupt */
|
||||
SPIx->CTRL2 |= itmask;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI/I2S interrupt */
|
||||
SPIx->CTRL2 &= (uint16_t)~itmask;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SPIx/I2Sx DMA interface.
|
||||
* @param SPIx where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* - 2 or 3 in I2S mode
|
||||
* @param SPI_I2S_DMAReq specifies the SPI/I2S DMA transfer request to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg SPI_I2S_DMA_TX Tx buffer DMA transfer request
|
||||
* @arg SPI_I2S_DMA_RX Rx buffer DMA transfer request
|
||||
* @param Cmd new state of the selected SPI/I2S DMA transfer request.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
assert_param(IS_SPI_I2S_DMA(SPI_I2S_DMAReq));
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI/I2S DMA requests */
|
||||
SPIx->CTRL2 |= SPI_I2S_DMAReq;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI/I2S DMA requests */
|
||||
SPIx->CTRL2 &= (uint16_t)~SPI_I2S_DMAReq;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Transmits a Data through the SPIx/I2Sx peripheral.
|
||||
* @param SPIx where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* - 2 or 3 in I2S mode
|
||||
* @param Data Data to be transmitted.
|
||||
*/
|
||||
void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
|
||||
/* Write in the DAT register the data to be sent */
|
||||
SPIx->DAT = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
|
||||
* @param SPIx where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* - 2 or 3 in I2S mode
|
||||
* @return The value of the received data.
|
||||
*/
|
||||
uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
|
||||
/* Return the data in the DAT register */
|
||||
return SPIx->DAT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures internally by software the NSS pin for the selected SPI.
|
||||
* @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param SPI_NSSInternalSoft specifies the SPI NSS internal state.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_NSS_HIGH Set NSS pin internally
|
||||
* @arg SPI_NSS_LOW Reset NSS pin internally
|
||||
*/
|
||||
void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_NSS_LEVEL(SPI_NSSInternalSoft));
|
||||
if (SPI_NSSInternalSoft != SPI_NSS_LOW)
|
||||
{
|
||||
/* Set NSS pin internally by software */
|
||||
SPIx->CTRL1 |= SPI_NSS_HIGH;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Reset NSS pin internally by software */
|
||||
SPIx->CTRL1 &= SPI_NSS_LOW;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SS output for the selected SPI.
|
||||
* @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param Cmd new state of the SPIx SS output.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI SS output */
|
||||
SPIx->CTRL2 |= CTRL2_SSOEN_ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI SS output */
|
||||
SPIx->CTRL2 &= CTRL2_SSOEN_DISABLE;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the data size for the selected SPI.
|
||||
* @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param DataLen specifies the SPI data size.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_DATA_SIZE_16BITS Set data frame format to 16bit
|
||||
* @arg SPI_DATA_SIZE_8BITS Set data frame format to 8bit
|
||||
*/
|
||||
void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_DATASIZE(DataLen));
|
||||
/* Clear DFF bit */
|
||||
SPIx->CTRL1 &= (uint16_t)~SPI_DATA_SIZE_16BITS;
|
||||
/* Set new DFF bit value */
|
||||
SPIx->CTRL1 |= DataLen;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Transmit the SPIx CRC value.
|
||||
* @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
*/
|
||||
void SPI_TransmitCrcNext(SPI_Module* SPIx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
|
||||
/* Enable the selected SPI CRC transmission */
|
||||
SPIx->CTRL1 |= CTRL1_CRCNEXT_ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the CRC value calculation of the transferred bytes.
|
||||
* @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param Cmd new state of the SPIx CRC value calculation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
/* Enable the selected SPI CRC calculation */
|
||||
SPIx->CTRL1 |= CTRL1_CRCEN_ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected SPI CRC calculation */
|
||||
SPIx->CTRL1 &= CTRL1_CRCEN_DISABLE;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the transmit or the receive CRC register value for the specified SPI.
|
||||
* @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param SPI_CRC specifies the CRC register to be read.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_CRC_TX Selects Tx CRC register
|
||||
* @arg SPI_CRC_RX Selects Rx CRC register
|
||||
* @return The selected CRC register value..
|
||||
*/
|
||||
uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC)
|
||||
{
|
||||
uint16_t crcreg = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_CRC(SPI_CRC));
|
||||
if (SPI_CRC != SPI_CRC_RX)
|
||||
{
|
||||
/* Get the Tx CRC register */
|
||||
crcreg = SPIx->CRCTDAT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get the Rx CRC register */
|
||||
crcreg = SPIx->CRCRDAT;
|
||||
}
|
||||
/* Return the selected CRC register */
|
||||
return crcreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the CRC Polynomial register value for the specified SPI.
|
||||
* @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @return The CRC Polynomial register value.
|
||||
*/
|
||||
uint16_t SPI_GetCRCPoly(SPI_Module* SPIx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
|
||||
/* Return the CRC polynomial register */
|
||||
return SPIx->CRCPOLY;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the data transfer direction in bi-directional mode for the specified SPI.
|
||||
* @param SPIx where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||
* @param DataDirection specifies the data transfer direction in bi-directional mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_BIDIRECTION_TX Selects Tx transmission direction
|
||||
* @arg SPI_BIDIRECTION_RX Selects Rx receive direction
|
||||
*/
|
||||
void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_BIDIRECTION(DataDirection));
|
||||
if (DataDirection == SPI_BIDIRECTION_TX)
|
||||
{
|
||||
/* Set the Tx only mode */
|
||||
SPIx->CTRL1 |= SPI_BIDIRECTION_TX;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the Rx only mode */
|
||||
SPIx->CTRL1 &= SPI_BIDIRECTION_RX;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified SPI/I2S flag is set or not.
|
||||
* @param SPIx where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* - 2 or 3 in I2S mode
|
||||
* @param SPI_I2S_FLAG specifies the SPI/I2S flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_I2S_TE_FLAG Transmit buffer empty flag.
|
||||
* @arg SPI_I2S_RNE_FLAG Receive buffer not empty flag.
|
||||
* @arg SPI_I2S_BUSY_FLAG Busy flag.
|
||||
* @arg SPI_I2S_OVER_FLAG Overrun flag.
|
||||
* @arg SPI_MODERR_FLAG Mode Fault flag.
|
||||
* @arg SPI_CRCERR_FLAG CRC Error flag.
|
||||
* @arg I2S_UNDER_FLAG Underrun Error flag.
|
||||
* @arg I2S_CHSIDE_FLAG Channel Side flag.
|
||||
* @return The new state of SPI_I2S_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
|
||||
/* Check the status of the specified SPI/I2S flag */
|
||||
if ((SPIx->STS & SPI_I2S_FLAG) != (uint16_t)RESET)
|
||||
{
|
||||
/* SPI_I2S_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* SPI_I2S_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the SPI_I2S_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the SPIx CRC Error (CRCERR) flag.
|
||||
* @param SPIx where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* @param SPI_I2S_FLAG specifies the SPI flag to clear.
|
||||
* This function clears only CRCERR flag.
|
||||
* @note
|
||||
* - OVR (OverRun error) flag is cleared by software sequence: a read
|
||||
* operation to SPI_DAT register (SPI_I2S_ReceiveData()) followed by a read
|
||||
* operation to SPI_STS register (SPI_I2S_GetStatus()).
|
||||
* - UDR (UnderRun error) flag is cleared by a read operation to
|
||||
* SPI_STS register (SPI_I2S_GetStatus()).
|
||||
* - MODF (Mode Fault) flag is cleared by software sequence: a read/write
|
||||
* operation to SPI_STS register (SPI_I2S_GetStatus()) followed by a
|
||||
* write operation to SPI_CTRL1 register (SPI_Enable() to enable the SPI).
|
||||
*/
|
||||
void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_I2S_CLR_FLAG(SPI_I2S_FLAG));
|
||||
|
||||
/* Clear the selected SPI CRC Error (CRCERR) flag */
|
||||
SPIx->STS = (uint16_t)~SPI_I2S_FLAG;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
|
||||
* @param SPIx where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* - 2 or 3 in I2S mode
|
||||
* @param SPI_I2S_IT specifies the SPI/I2S interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SPI_I2S_INT_TE Transmit buffer empty interrupt.
|
||||
* @arg SPI_I2S_INT_RNE Receive buffer not empty interrupt.
|
||||
* @arg SPI_I2S_INT_OVER Overrun interrupt.
|
||||
* @arg SPI_INT_MODERR Mode Fault interrupt.
|
||||
* @arg SPI_INT_CRCERR CRC Error interrupt.
|
||||
* @arg I2S_INT_UNDER Underrun Error interrupt.
|
||||
* @return The new state of SPI_I2S_IT (SET or RESET).
|
||||
*/
|
||||
INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT)
|
||||
{
|
||||
INTStatus bitstatus = RESET;
|
||||
uint16_t itpos = 0, itmask = 0, enablestatus = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_I2S_GET_INT(SPI_I2S_IT));
|
||||
|
||||
/* Get the SPI/I2S IT index */
|
||||
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
|
||||
|
||||
/* Get the SPI/I2S IT mask */
|
||||
itmask = SPI_I2S_IT >> 4;
|
||||
|
||||
/* Set the IT mask */
|
||||
itmask = 0x01 << itmask;
|
||||
|
||||
/* Get the SPI_I2S_IT enable bit status */
|
||||
enablestatus = (SPIx->CTRL2 & itmask);
|
||||
|
||||
/* Check the status of the specified SPI/I2S interrupt */
|
||||
if (((SPIx->STS & itpos) != (uint16_t)RESET) && enablestatus)
|
||||
{
|
||||
/* SPI_I2S_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* SPI_I2S_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the SPI_I2S_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
|
||||
* @param SPIx where x can be
|
||||
* - 1, 2 or 3 in SPI mode
|
||||
* @param SPI_I2S_IT specifies the SPI interrupt pending bit to clear.
|
||||
* This function clears only CRCERR interrupt pending bit.
|
||||
* @note
|
||||
* - OVR (OverRun Error) interrupt pending bit is cleared by software
|
||||
* sequence: a read operation to SPI_DAT register (SPI_I2S_ReceiveData())
|
||||
* followed by a read operation to SPI_STS register (SPI_I2S_GetIntStatus()).
|
||||
* - UDR (UnderRun Error) interrupt pending bit is cleared by a read
|
||||
* operation to SPI_STS register (SPI_I2S_GetIntStatus()).
|
||||
* - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
|
||||
* a read/write operation to SPI_STS register (SPI_I2S_GetIntStatus())
|
||||
* followed by a write operation to SPI_CTRL1 register (SPI_Enable() to enable
|
||||
* the SPI).
|
||||
*/
|
||||
void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT)
|
||||
{
|
||||
uint16_t itpos = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SPI_PERIPH(SPIx));
|
||||
assert_param(IS_SPI_I2S_CLR_INT(SPI_I2S_IT));
|
||||
|
||||
/* Get the SPI IT index */
|
||||
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
|
||||
|
||||
/* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
|
||||
SPIx->STS = (uint16_t)~itpos;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,367 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_tsc.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x.h"
|
||||
#include "n32g45x_tsc.h"
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the TSC hardware detect init.
|
||||
* @param TSC_Def Pointer of TSC register.
|
||||
* @param CtrlCfg configurations.
|
||||
*/
|
||||
void TSC_Init(TSC_Module* TSC_Def, TSC_InitType* CtrlCfg)
|
||||
{
|
||||
while (TSC_Def->CTRL & TSC_HW_DET_ST)
|
||||
{
|
||||
TSC_Def->CTRL &= (~TSC_HW_DET_ENABLE);
|
||||
};
|
||||
|
||||
// waiting tsc hw for idle status.
|
||||
if (CtrlCfg->TSC_DetIntEnable)
|
||||
{
|
||||
TSC_Def->CTRL |= TSC_HW_DET_INTEN;
|
||||
}
|
||||
else
|
||||
{
|
||||
TSC_Def->CTRL &= (~TSC_HW_DET_INTEN);
|
||||
}
|
||||
|
||||
if (CtrlCfg->TSC_GreatEnable)
|
||||
{
|
||||
TSC_Def->CTRL |= TSC_HW_GREAT_DET_SEL;
|
||||
}
|
||||
else
|
||||
{
|
||||
TSC_Def->CTRL &= (~TSC_HW_GREAT_DET_SEL);
|
||||
}
|
||||
|
||||
if (CtrlCfg->TSC_LessEnable)
|
||||
{
|
||||
TSC_Def->CTRL |= TSC_HW_LESS_DET_SEL;
|
||||
}
|
||||
else
|
||||
{
|
||||
TSC_Def->CTRL &= (~TSC_HW_LESS_DET_SEL);
|
||||
}
|
||||
|
||||
TSC_Def->CTRL &= (~(TSC_HW_DET_BITS_MASK << TSC_HW_DET_OFFSET));
|
||||
TSC_Def->CTRL |= CtrlCfg->TSC_FilterCount;
|
||||
|
||||
TSC_Def->CTRL &= (~(TSC_DET_PERIOD_MASK << TSC_DET_PERIOD_OFFSET));
|
||||
TSC_Def->CTRL |= CtrlCfg->TSC_DetPeriod;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure analog signal parameters.
|
||||
* @param TSC_Def Pointer of TSC register.
|
||||
* @param AnaoCfg Pointer of analog parameter structure.
|
||||
*/
|
||||
void TSC_SetAnaoCfg(TSC_Module* TSC_Def, TSC_AnaoCfg* AnaoCfg)
|
||||
{
|
||||
if (AnaoCfg && TSC_Def)
|
||||
{
|
||||
TSC_Def->ANA_SEL &= (~(TSC_CMP_MASK << TSC_CMP_OFFSET));
|
||||
TSC_Def->ANA_SEL |= AnaoCfg->TSC_AnaoptrSpeedOption; // speed option
|
||||
|
||||
TSC_Def->ANA_SEL &= (~(TSC_RESIST_SEL_MASK << TSC_RESIST_SEL_OFFSET));
|
||||
TSC_Def->ANA_SEL |= AnaoCfg->TSC_AnaoptrResisOption; // speed option
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure channel parameters by channel or operation.Support configure several channels at the same time.
|
||||
* @param TSC_Def Pointer of TSC register.
|
||||
* @param ChnCfg Channel parameters.
|
||||
* @param Channels Set the channels.
|
||||
*/
|
||||
void TSC_SetChannelCfg(TSC_Module* TSC_Def, TSC_ChnCfg* ChnCfg, uint32_t Channels)
|
||||
{
|
||||
uint32_t i, j;
|
||||
uint32_t chn;
|
||||
|
||||
while (TSC_Def->CTRL & TSC_HW_DET_ST)
|
||||
{
|
||||
TSC_Def->CTRL &= (~TSC_HW_DET_ENABLE);
|
||||
};
|
||||
|
||||
// waiting tsc hw for idle status.
|
||||
// Set resistance
|
||||
for (i = TSC_CHN0, j = 0, chn = Channels; i <= TSC_CHN23; i <<= 1, j++)
|
||||
{
|
||||
if (chn & 0x00000001)
|
||||
{
|
||||
if ((i >= TSC_CHN0) && (i <= TSC_CHN7))
|
||||
{
|
||||
TSC_Def->RESR0 = (TSC_Def->RESR0 & (~(TSC_RES_BIT_VALID_BITS << (j * TSC_RES_BIT_OFFSET_WIDTH))))
|
||||
| (ChnCfg->TSC_ResisValue << (j * TSC_RES_BIT_OFFSET_WIDTH));
|
||||
}
|
||||
else if ((i >= TSC_CHN8) && (i <= TSC_CHN15))
|
||||
{
|
||||
TSC_Def->RESR1 = (TSC_Def->RESR1 & (~(TSC_RES_BIT_VALID_BITS << (j * TSC_RES_BIT_OFFSET_WIDTH - 32))))
|
||||
| (ChnCfg->TSC_ResisValue << (j * TSC_RES_BIT_OFFSET_WIDTH - 32));
|
||||
}
|
||||
else if ((i >= TSC_CHN16) && (i <= TSC_CHN23))
|
||||
{
|
||||
TSC_Def->RESR2 = (TSC_Def->RESR2 & (~(TSC_RES_BIT_VALID_BITS << (j * TSC_RES_BIT_OFFSET_WIDTH - 64))))
|
||||
| (ChnCfg->TSC_ResisValue << (j * TSC_RES_BIT_OFFSET_WIDTH - 64));
|
||||
}
|
||||
}
|
||||
|
||||
chn >>= 1;
|
||||
}
|
||||
|
||||
// Set the threshold of base and delta.
|
||||
for (i = TSC_CHN0, j = 0, chn = Channels; i <= TSC_CHN23; i <<= 1, j++)
|
||||
{
|
||||
if (chn & 0x00000001)
|
||||
{
|
||||
*(__IO uint32_t*)((uint32_t)&TSC_Def->THRHD0 + TSC_CHN_ADDR_WIDTH * j) =
|
||||
(ChnCfg->TSC_Base << TSC_HW_BASE_BITS_OFFSET) | (ChnCfg->TSC_Delta << TSC_HW_DELTA_BITS_OFFSET);
|
||||
}
|
||||
|
||||
chn >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get parameters of one channel.
|
||||
* @param TSC_Def Pointer of TSC register.
|
||||
* @param ChnCfg Channel parameters.
|
||||
* @param Channel Set the channel.
|
||||
*/
|
||||
void TSC_GetChannelCfg(TSC_Module* TSC_Def, TSC_ChnCfg* ChnCfg, uint32_t Channel)
|
||||
{
|
||||
uint32_t i, j;
|
||||
uint32_t chn, value;
|
||||
|
||||
// waiting tsc hw for idle status.
|
||||
// Set resistance
|
||||
for (i = TSC_CHN0, j = 0, chn = Channel; i <= TSC_CHN23; i <<= 1, j++)
|
||||
{
|
||||
if (chn & 0x00000001)
|
||||
{
|
||||
if ((i >= TSC_CHN0) && (i <= TSC_CHN7))
|
||||
{
|
||||
ChnCfg->TSC_ResisValue =
|
||||
(TSC_Def->RESR0 >> (j * TSC_RES_BIT_OFFSET_WIDTH)) & TSC_RES_BIT_VALID_BITS;
|
||||
}
|
||||
else if ((i >= TSC_CHN8) && (i <= TSC_CHN15))
|
||||
{
|
||||
ChnCfg->TSC_ResisValue =
|
||||
(TSC_Def->RESR1 >> (j * TSC_RES_BIT_OFFSET_WIDTH - 32)) & TSC_RES_BIT_VALID_BITS;
|
||||
}
|
||||
else if ((i >= TSC_CHN16) && (i <= TSC_CHN23))
|
||||
{
|
||||
ChnCfg->TSC_ResisValue =
|
||||
(TSC_Def->RESR2 >> (j * TSC_RES_BIT_OFFSET_WIDTH - 64)) & TSC_RES_BIT_VALID_BITS;
|
||||
}
|
||||
break; // You can only get the resistance of one channel at a time.
|
||||
}
|
||||
chn >>= 1;
|
||||
}
|
||||
|
||||
// Set the threshold of base and delta.
|
||||
for (i = TSC_CHN0, j = 0, chn = Channel; i <= TSC_CHN23; i <<= 1, j++)
|
||||
{
|
||||
if (chn & 0x00000001)
|
||||
{
|
||||
value = *(__IO uint32_t*)((uint32_t)&TSC_Def->THRHD0 + TSC_CHN_ADDR_WIDTH * j);
|
||||
ChnCfg->TSC_Base = (value >> TSC_HW_BASE_BITS_OFFSET) & TSC_HW_BASE_BITS_WIDTH;
|
||||
ChnCfg->TSC_Delta = (value >> TSC_HW_DELTA_BITS_OFFSET) & TSC_HW_DELTA_BITS_WIDTH;
|
||||
break; // You can only get the parameter of one channel at a time.
|
||||
}
|
||||
chn >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get TSC status value.
|
||||
* @param TSC_Def Pointer of TSC register.
|
||||
* @param type TSC status type.
|
||||
*/
|
||||
uint32_t TSC_GetStatus(TSC_Module* TSC_Def, TSC_Status type)
|
||||
{
|
||||
uint32_t value = 0;
|
||||
|
||||
if (TSC_Def)
|
||||
{
|
||||
switch (type)
|
||||
{
|
||||
case TSC_STS_CNTVALUE:
|
||||
value = (TSC_Def->STS >> TSC_HW_CNT_VAL_OFFSET) & TSC_HW_CNT_VAL_BITS_MASK;
|
||||
break;
|
||||
|
||||
case TSC_STS_LESS_DET:
|
||||
value = (TSC_Def->STS >> TSC_HW_LESS_DET_FLAG_OFFSET) & TSC_HW_LESS_DET_FLAG_MASK;
|
||||
break;
|
||||
|
||||
case TSC_STS_GREAT_DET:
|
||||
value = (TSC_Def->STS >> TSC_HW_GREAT_DET_FLAG_OFFSET) & TSC_HW_GREAT_DET_FLAG_MASK;
|
||||
break;
|
||||
|
||||
case TSC_STS_CHN_NUM:
|
||||
value = (TSC_Def->STS >> TSC_HW_CHN_NUM_OFFSET) & TSC_HW_CHN_NUM_FLAG_MASK;
|
||||
break;
|
||||
|
||||
case TSC_DET_DET_ST:
|
||||
value = TSC_Def->CTRL & TSC_HW_DET_ST;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable hardware detection.
|
||||
* @param TSC_Def Pointer of TSC register.
|
||||
* @param Channels Set the channel.
|
||||
* @param Cmd ENABLE:Enable hardware detection,DISALBE:Disable hardware detection.
|
||||
* @note You can only output one channel at a time.
|
||||
*/
|
||||
void TSC_Cmd(TSC_Module* TSC_Def, uint32_t Channels, FunctionalState Cmd)
|
||||
{
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
// enable tsc channel
|
||||
TSC_Def->CHNEN = Channels & TSC_HW_CHN_MASK;
|
||||
|
||||
/* Enable the TSC */
|
||||
TSC_Def->CTRL |= TSC_HW_DET_ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the TSC */
|
||||
while (TSC_Def->CTRL & TSC_HW_DET_ST)
|
||||
{
|
||||
// waiting tsc hw for idle status.
|
||||
TSC_Def->CTRL &= (~TSC_HW_DET_ENABLE);
|
||||
};
|
||||
TSC_Def->CHNEN &= (~TSC_HW_CHN_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggle channels to output to TIMER2/TIMER4 by software mode.
|
||||
* @param TSC_Def Pointer of TSC register.
|
||||
* @param Channel Set the channel.
|
||||
* @param TIMx Select timer.
|
||||
* @param Cmd ENABLE:Enable hardware detection,DISALBE:Disable hardware detection.
|
||||
* @note It can only output to TIMER2/TIMER4 by software mode.Other channels are not valid.
|
||||
*/
|
||||
void TSC_SW_SwtichChn(TSC_Module* TSC_Def, uint32_t Channel, TIM_Module* TIMx, FunctionalState Cmd)
|
||||
{
|
||||
uint32_t i, j;
|
||||
|
||||
/* Disable the TSC HW MODE */
|
||||
while (TSC_Def->CTRL & TSC_HW_DET_ST)
|
||||
{
|
||||
TSC_Def->CTRL &= (~TSC_HW_DET_ENABLE);
|
||||
};
|
||||
|
||||
// waiting tsc hw for idle status.
|
||||
if ((TIMx != TIM2) && (TIMx != TIM4))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = TSC_CHN0, j = 0; i <= TSC_CHN23; i <<= 1, j++)
|
||||
{
|
||||
if (Channel & 0x00000001)
|
||||
{
|
||||
TSC_Def->ANA_CTRL = (TSC_Def->ANA_CTRL & (~TSC_SW_CHN_VAILD_WIDTH)) | j;
|
||||
break;
|
||||
}
|
||||
|
||||
Channel >>= 1;
|
||||
}
|
||||
|
||||
/* Enable the TSC SW MODE */
|
||||
if (Cmd == ENABLE)
|
||||
{
|
||||
// Select to output to specified TIMER.
|
||||
if (TIMx == TIM4)
|
||||
{
|
||||
TSC_Def->CTRL = (TSC_Def->CTRL & (~(TSC_SW_TIM_WIDTH << TSC_SW_TIM_OFFSET))) | TSC_SW_TM4_ETR_SEL;
|
||||
}
|
||||
else
|
||||
{
|
||||
TSC_Def->CTRL = (TSC_Def->CTRL & (~(TSC_SW_TIM_WIDTH << TSC_SW_TIM_OFFSET))) | TSC_SW_TM2_ETR_SEL;
|
||||
}
|
||||
|
||||
TSC_Def->ANA_CTRL |= TSC_SW_CHN_ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
// Close output by software mode.Then all the channels output to TIM2 and TIM4 are closed.
|
||||
TSC_Def->CTRL &= (~(TSC_SW_TIM_WIDTH << TSC_SW_TIM_OFFSET));
|
||||
TSC_Def->ANA_CTRL &= (~TSC_SW_CHN_ENABLE);
|
||||
}
|
||||
|
||||
// delay time for tsc channel stabilize output
|
||||
for (i = 0; i < 2000; i++)
|
||||
{
|
||||
}
|
||||
}
|
||||
/******************************************************************/
|
||||
/**
|
||||
* @brief Configure the software detection mode quickly.Samples start from channel 10,
|
||||
And toggle channels periodically later.
|
||||
*/
|
||||
void TSC_SW_Init_Skip(void)
|
||||
{
|
||||
while ((TSC->CTRL & 0x80) == TSC_CTRL_HW_DET_ST)
|
||||
{
|
||||
TSC->CTRL &= ~TSC_CTRL_HW_DET_MODE;
|
||||
}
|
||||
TSC->CTRL |= 0x00002000; // bit13 set 1,channels output to TIMER2.
|
||||
TSC->CHNEN |= 0xFFCC00; // select hardware channels,include TSC10-11 and TSC14-23.
|
||||
TSC->ANA_CTRL |= 0x00000020; // enable software detection.
|
||||
TSC->ANA_CTRL |= 10; // select software channel 10,Samples start from channel 10,and toggle channels periodically later.
|
||||
TSC->RESR1 = 0x77007700; // Select the internal resistance of the corresponding channel as 126K.
|
||||
TSC->RESR2 = 0x77777777; // Select the internal resistance of the corresponding channel as 126K.
|
||||
}
|
||||
/**
|
||||
* @brief Toggle channels by software mode quickly.Note it has been configured hardware detection disable,channels
|
||||
output to TIMER2 or TIMER4 in advance and never changed. In addition,toggle channels must delay at least 30us.
|
||||
* @param Channel Select the channel.
|
||||
*/
|
||||
void TSC_SW_SwtichChn_Skip(uint32_t Channel)
|
||||
{
|
||||
// Toggle to new channel quickly.
|
||||
TSC->ANA_CTRL = 0x20 | Channel;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,223 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_wwdg.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x_wwdg.h"
|
||||
#include "n32g45x_rcc.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG
|
||||
* @brief WWDG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ----------- WWDG registers bit address in the alias region ----------- */
|
||||
#define WWDG_OFFADDR (WWDG_BASE - PERIPH_BASE)
|
||||
|
||||
/* Alias word address of EWI bit */
|
||||
#define CFG_OFFADDR (WWDG_OFFADDR + 0x04)
|
||||
#define EWINT_BIT 0x09
|
||||
#define CFG_EWINT_BB (PERIPH_BB_BASE + (CFG_OFFADDR * 32) + (EWINT_BIT * 4))
|
||||
|
||||
/* --------------------- WWDG registers bit mask ------------------------ */
|
||||
|
||||
/* CTRL register bit mask */
|
||||
#define CTRL_ACTB_SET ((uint32_t)0x00000080)
|
||||
|
||||
/* CFG register bit mask */
|
||||
#define CFG_TIMERB_MASK ((uint32_t)0xFFFFFE7F)
|
||||
#define CFG_W_MASK ((uint32_t)0xFFFFFF80)
|
||||
#define BIT_MASK ((uint8_t)0x7F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the WWDG peripheral registers to their default reset values.
|
||||
*/
|
||||
void WWDG_DeInit(void)
|
||||
{
|
||||
RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, ENABLE);
|
||||
RCC_EnableAPB1PeriphReset(RCC_APB1_PERIPH_WWDG, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG Prescaler.
|
||||
* @param WWDG_Prescaler specifies the WWDG Prescaler.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_PRESCALER_DIV1 WWDG counter clock = (PCLK1/4096)/1
|
||||
* @arg WWDG_PRESCALER_DIV2 WWDG counter clock = (PCLK1/4096)/2
|
||||
* @arg WWDG_PRESCALER_DIV4 WWDG counter clock = (PCLK1/4096)/4
|
||||
* @arg WWDG_PRESCALER_DIV8 WWDG counter clock = (PCLK1/4096)/8
|
||||
*/
|
||||
void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler)
|
||||
{
|
||||
uint32_t tmpregister = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_PRESCALER_DIV(WWDG_Prescaler));
|
||||
/* Clear WDGTB[1:0] bits */
|
||||
tmpregister = WWDG->CFG & CFG_TIMERB_MASK;
|
||||
/* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
|
||||
tmpregister |= WWDG_Prescaler;
|
||||
/* Store the new value */
|
||||
WWDG->CFG = tmpregister;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG window value.
|
||||
* @param WindowValue specifies the window value to be compared to the downcounter.
|
||||
* This parameter value must be lower than 0x80.
|
||||
*/
|
||||
void WWDG_SetWValue(uint8_t WindowValue)
|
||||
{
|
||||
__IO uint32_t tmpregister = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_WVALUE(WindowValue));
|
||||
/* Clear W[6:0] bits */
|
||||
|
||||
tmpregister = WWDG->CFG & CFG_W_MASK;
|
||||
|
||||
/* Set W[6:0] bits according to WindowValue value */
|
||||
tmpregister |= WindowValue & (uint32_t)BIT_MASK;
|
||||
|
||||
/* Store the new value */
|
||||
WWDG->CFG = tmpregister;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the WWDG Early Wakeup interrupt(EWI).
|
||||
*/
|
||||
void WWDG_EnableInt(void)
|
||||
{
|
||||
*(__IO uint32_t*)CFG_EWINT_BB = (uint32_t)ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG counter value.
|
||||
* @param Counter specifies the watchdog counter value.
|
||||
* This parameter must be a number between 0x40 and 0x7F.
|
||||
*/
|
||||
void WWDG_SetCnt(uint8_t Counter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_CNT(Counter));
|
||||
/* Write to T[6:0] bits to configure the counter value, no need to do
|
||||
a read-modify-write; writing a 0 to WDGA bit does nothing */
|
||||
WWDG->CTRL = Counter & BIT_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables WWDG and load the counter value.
|
||||
* @param Counter specifies the watchdog counter value.
|
||||
* This parameter must be a number between 0x40 and 0x7F.
|
||||
*/
|
||||
void WWDG_Enable(uint8_t Counter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_CNT(Counter));
|
||||
WWDG->CTRL = CTRL_ACTB_SET | Counter;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the Early Wakeup interrupt flag is set or not.
|
||||
* @return The new state of the Early Wakeup interrupt flag (SET or RESET)
|
||||
*/
|
||||
FlagStatus WWDG_GetEWINTF(void)
|
||||
{
|
||||
return (FlagStatus)(WWDG->STS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears Early Wakeup interrupt flag.
|
||||
*/
|
||||
void WWDG_ClrEWINTF(void)
|
||||
{
|
||||
WWDG->STS = (uint32_t)RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,570 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file n32g45x_xfmc.c
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#include "n32g45x_xfmc.h"
|
||||
#include "n32g45x_rcc.h"
|
||||
|
||||
/** @addtogroup N32G45X_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC
|
||||
* @brief XFMC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* --------------------- XFMC registers bit mask ---------------------------- */
|
||||
|
||||
/* XFMC BCRx Mask */
|
||||
#define BCR_MBKEN_Set ((uint32_t)0x00000001)
|
||||
#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
|
||||
#define BCR_FACCEN_Set ((uint32_t)0x00000040)
|
||||
|
||||
/* XFMC PCRx Mask */
|
||||
#define PCR_PBKEN_Set ((uint32_t)0x00000004)
|
||||
#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
|
||||
#define PCR_ECCEN_Set ((uint32_t)0x00000040)
|
||||
#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
|
||||
#define PCR_MemoryType_NAND ((uint32_t)0x00000008)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup XFMC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the XFMC NOR/SRAM Banks registers to their default
|
||||
* reset values.
|
||||
* @param Bank specifies the XFMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg XFMC_BANK1_NORSRAM1 XFMC Bank1 NOR/SRAM1
|
||||
* @arg XFMC_BANK1_NORSRAM2 XFMC Bank1 NOR/SRAM2
|
||||
*/
|
||||
void XFMC_DeInitNorSram(uint32_t Bank)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_XFMC_NORSRAM_BANK(Bank));
|
||||
|
||||
/* XFMC_BANK1_NORSRAM1 */
|
||||
if (Bank == XFMC_BANK1_NORSRAM1)
|
||||
{
|
||||
XFMC_BANK1->BK1CSTCTRL[Bank] = 0x000030DB;
|
||||
}
|
||||
/* XFMC_BANK1_NORSRAM2, XFMC_BANK1_NORSRAM3 or XFMC_BANK1_NORSRAM4 */
|
||||
else
|
||||
{
|
||||
XFMC_BANK1->BK1CSTCTRL[Bank] = 0x000030D2;
|
||||
}
|
||||
XFMC_BANK1->BK1CSTCTRL[Bank + 1] = 0x0FFFFFFF;
|
||||
XFMC_BANK1E->BK1WRT[Bank] = 0x0FFFFFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the XFMC NAND Banks registers to their default reset values.
|
||||
* @param Bank specifies the XFMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg XFMC_BANK2_NAND XFMC Bank2 NAND
|
||||
* @arg XFMC_BANK3_NAND XFMC Bank3 NAND
|
||||
*/
|
||||
void XFMC_DeInitNand(uint32_t Bank)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_XFMC_NAND_BANK(Bank));
|
||||
|
||||
if (Bank == XFMC_BANK2_NAND)
|
||||
{
|
||||
/* Set the XFMC_BANK2 registers to their reset values */
|
||||
XFMC_BANK2->BK2CTRL = 0x00000018;
|
||||
XFMC_BANK2->STS2 = 0x00000040;
|
||||
XFMC_BANK2->CMEM2 = 0xFCFCFCFC;
|
||||
XFMC_BANK2->ATTR2 = 0xFCFCFCFC;
|
||||
}
|
||||
/* XFMC_BANK3_NAND */
|
||||
else
|
||||
{
|
||||
/* Set the XFMC_BANK3 registers to their reset values */
|
||||
XFMC_BANK3->BK3CTRL = 0x00000018;
|
||||
XFMC_BANK3->STS3 = 0x00000040;
|
||||
XFMC_BANK3->CMEM3 = 0xFCFCFCFC;
|
||||
XFMC_BANK3->ATTR3 = 0xFCFCFCFC;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the XFMC NOR/SRAM Banks according to the specified
|
||||
* parameters in the XFMC_NORSRAMInitStruct.
|
||||
* @param XFMC_NORSRAMInitStruct pointer to a XFMC_NorSramInitTpye
|
||||
* structure that contains the configuration information for
|
||||
* the XFMC NOR/SRAM specified Banks.
|
||||
*/
|
||||
void XFMC_InitNorSram(XFMC_NorSramInitTpye* XFMC_NORSRAMInitStruct)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_XFMC_NORSRAM_BANK(XFMC_NORSRAMInitStruct->Bank));
|
||||
assert_param(IS_XFMC_MUX(XFMC_NORSRAMInitStruct->DataAddrMux));
|
||||
assert_param(IS_XFMC_MEMORY(XFMC_NORSRAMInitStruct->MemType));
|
||||
assert_param(IS_XFMC_MEMORY_WIDTH(XFMC_NORSRAMInitStruct->MemDataWidth));
|
||||
assert_param(IS_XFMC_BURSTMODE(XFMC_NORSRAMInitStruct->BurstAccMode));
|
||||
assert_param(IS_XFMC_ASYNWAIT(XFMC_NORSRAMInitStruct->AsynchroWait));
|
||||
assert_param(IS_XFMC_WAIT_POLARITY(XFMC_NORSRAMInitStruct->WaitSigPolarity));
|
||||
assert_param(IS_XFMC_WRAP_MODE(XFMC_NORSRAMInitStruct->WrapMode));
|
||||
assert_param(IS_XFMC_WAIT_SIGNAL_ACTIVE(XFMC_NORSRAMInitStruct->WaitSigConfig));
|
||||
assert_param(IS_XFMC_WRITE_OPERATION(XFMC_NORSRAMInitStruct->WriteEnable));
|
||||
assert_param(IS_XFMC_WAITE_SIGNAL(XFMC_NORSRAMInitStruct->WaitSigEnable));
|
||||
assert_param(IS_XFMC_EXTENDED_MODE(XFMC_NORSRAMInitStruct->ExtModeEnable));
|
||||
assert_param(IS_XFMC_WRITE_BURST(XFMC_NORSRAMInitStruct->WriteBurstEnable));
|
||||
assert_param(IS_XFMC_ADDRESS_SETUP_TIME(XFMC_NORSRAMInitStruct->RWTimingStruct->AddrSetTime));
|
||||
assert_param(IS_XFMC_ADDRESS_HOLD_TIME(XFMC_NORSRAMInitStruct->RWTimingStruct->AddrHoldTime));
|
||||
assert_param(IS_XFMC_DATASETUP_TIME(XFMC_NORSRAMInitStruct->RWTimingStruct->DataSetTime));
|
||||
assert_param(IS_XFMC_TURNAROUND_TIME(XFMC_NORSRAMInitStruct->RWTimingStruct->BusRecoveryCycle));
|
||||
assert_param(IS_XFMC_CLK_DIV(XFMC_NORSRAMInitStruct->RWTimingStruct->ClkDiv));
|
||||
assert_param(IS_XFMC_DATA_LATENCY(XFMC_NORSRAMInitStruct->RWTimingStruct->DataLatency));
|
||||
assert_param(IS_XFMC_ACCESS_MODE(XFMC_NORSRAMInitStruct->RWTimingStruct->AccMode));
|
||||
|
||||
/* Bank1 NOR/SRAM control register configuration */
|
||||
XFMC_BANK1->BK1CSTCTRL[XFMC_NORSRAMInitStruct->Bank] =
|
||||
(uint32_t)XFMC_NORSRAMInitStruct->DataAddrMux | XFMC_NORSRAMInitStruct->MemType
|
||||
| XFMC_NORSRAMInitStruct->MemDataWidth | XFMC_NORSRAMInitStruct->BurstAccMode
|
||||
| XFMC_NORSRAMInitStruct->AsynchroWait | XFMC_NORSRAMInitStruct->WaitSigPolarity
|
||||
| XFMC_NORSRAMInitStruct->WrapMode | XFMC_NORSRAMInitStruct->WaitSigConfig | XFMC_NORSRAMInitStruct->WriteEnable
|
||||
| XFMC_NORSRAMInitStruct->WaitSigEnable | XFMC_NORSRAMInitStruct->ExtModeEnable
|
||||
| XFMC_NORSRAMInitStruct->WriteBurstEnable;
|
||||
|
||||
if (XFMC_NORSRAMInitStruct->MemType == XFMC_MEM_TYPE_NOR)
|
||||
{
|
||||
XFMC_BANK1->BK1CSTCTRL[XFMC_NORSRAMInitStruct->Bank] |= (uint32_t)BCR_FACCEN_Set;
|
||||
}
|
||||
|
||||
/* Bank1 NOR/SRAM timing register configuration */
|
||||
XFMC_BANK1->BK1CSTCTRL[XFMC_NORSRAMInitStruct->Bank + 1] =
|
||||
(uint32_t)XFMC_NORSRAMInitStruct->RWTimingStruct->AddrSetTime
|
||||
| (XFMC_NORSRAMInitStruct->RWTimingStruct->AddrHoldTime << 4)
|
||||
| (XFMC_NORSRAMInitStruct->RWTimingStruct->DataSetTime << 8)
|
||||
| (XFMC_NORSRAMInitStruct->RWTimingStruct->BusRecoveryCycle << 16)
|
||||
| (XFMC_NORSRAMInitStruct->RWTimingStruct->ClkDiv << 20)
|
||||
| (XFMC_NORSRAMInitStruct->RWTimingStruct->DataLatency << 24) | XFMC_NORSRAMInitStruct->RWTimingStruct->AccMode;
|
||||
|
||||
/* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
|
||||
if (XFMC_NORSRAMInitStruct->ExtModeEnable == XFMC_EXTENDED_ENABLE)
|
||||
{
|
||||
assert_param(IS_XFMC_ADDRESS_SETUP_TIME(XFMC_NORSRAMInitStruct->WTimingStruct->AddrSetTime));
|
||||
assert_param(IS_XFMC_ADDRESS_HOLD_TIME(XFMC_NORSRAMInitStruct->WTimingStruct->AddrHoldTime));
|
||||
assert_param(IS_XFMC_DATASETUP_TIME(XFMC_NORSRAMInitStruct->WTimingStruct->DataSetTime));
|
||||
assert_param(IS_XFMC_CLK_DIV(XFMC_NORSRAMInitStruct->WTimingStruct->ClkDiv));
|
||||
assert_param(IS_XFMC_DATA_LATENCY(XFMC_NORSRAMInitStruct->WTimingStruct->DataLatency));
|
||||
assert_param(IS_XFMC_ACCESS_MODE(XFMC_NORSRAMInitStruct->WTimingStruct->AccMode));
|
||||
XFMC_BANK1E->BK1WRT[XFMC_NORSRAMInitStruct->Bank] = (uint32_t)XFMC_NORSRAMInitStruct->WTimingStruct->AddrSetTime
|
||||
| (XFMC_NORSRAMInitStruct->WTimingStruct->AddrHoldTime << 4)
|
||||
| (XFMC_NORSRAMInitStruct->WTimingStruct->DataSetTime << 8)
|
||||
| (XFMC_NORSRAMInitStruct->WTimingStruct->ClkDiv << 20)
|
||||
| (XFMC_NORSRAMInitStruct->WTimingStruct->DataLatency << 24)
|
||||
| XFMC_NORSRAMInitStruct->WTimingStruct->AccMode;
|
||||
}
|
||||
else
|
||||
{
|
||||
XFMC_BANK1E->BK1WRT[XFMC_NORSRAMInitStruct->Bank] = 0x0FFFFFFF;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the XFMC NAND Banks according to the specified
|
||||
* parameters in the XFMC_NANDInitStruct.
|
||||
* @param XFMC_NANDInitStruct pointer to a XFMC_NandInitType
|
||||
* structure that contains the configuration information for the XFMC
|
||||
* NAND specified Banks.
|
||||
*/
|
||||
void XFMC_InitNand(XFMC_NandInitType* XFMC_NANDInitStruct)
|
||||
{
|
||||
uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_XFMC_NAND_BANK(XFMC_NANDInitStruct->Bank));
|
||||
assert_param(IS_XFMC_WAIT_FEATURE(XFMC_NANDInitStruct->WaitFeatureEnable));
|
||||
assert_param(IS_XFMC_MEMORY_WIDTH(XFMC_NANDInitStruct->MemDataWidth));
|
||||
assert_param(IS_XFMC_ECC_STATE(XFMC_NANDInitStruct->EccEnable));
|
||||
assert_param(IS_XFMC_ECCPAGE_SIZE(XFMC_NANDInitStruct->EccPageSize));
|
||||
assert_param(IS_XFMC_TCLR_TIME(XFMC_NANDInitStruct->TCLRSetTime));
|
||||
assert_param(IS_XFMC_TAR_TIME(XFMC_NANDInitStruct->TARSetTime));
|
||||
assert_param(IS_XFMC_SETUP_TIME(XFMC_NANDInitStruct->CommSpaceTimingStruct->SetTime));
|
||||
assert_param(IS_XFMC_WAIT_TIME(XFMC_NANDInitStruct->CommSpaceTimingStruct->WaitSetTime));
|
||||
assert_param(IS_XFMC_HOLD_TIME(XFMC_NANDInitStruct->CommSpaceTimingStruct->HoldSetTime));
|
||||
assert_param(IS_XFMC_HIZ_TIME(XFMC_NANDInitStruct->CommSpaceTimingStruct->HiZSetTime));
|
||||
assert_param(IS_XFMC_SETUP_TIME(XFMC_NANDInitStruct->AttrSpaceTimingStruct->SetTime));
|
||||
assert_param(IS_XFMC_WAIT_TIME(XFMC_NANDInitStruct->AttrSpaceTimingStruct->WaitSetTime));
|
||||
assert_param(IS_XFMC_HOLD_TIME(XFMC_NANDInitStruct->AttrSpaceTimingStruct->HoldSetTime));
|
||||
assert_param(IS_XFMC_HIZ_TIME(XFMC_NANDInitStruct->AttrSpaceTimingStruct->HiZSetTime));
|
||||
|
||||
/* Set the tmppcr value according to XFMC_NANDInitStruct parameters */
|
||||
tmppcr = (uint32_t)XFMC_NANDInitStruct->WaitFeatureEnable | PCR_MemoryType_NAND | XFMC_NANDInitStruct->MemDataWidth
|
||||
| XFMC_NANDInitStruct->EccEnable | XFMC_NANDInitStruct->EccPageSize
|
||||
| (XFMC_NANDInitStruct->TCLRSetTime << 9) | (XFMC_NANDInitStruct->TARSetTime << 13);
|
||||
|
||||
/* Set tmppmem value according to XFMC_CommonSpaceTimingStructure parameters */
|
||||
tmppmem = (uint32_t)XFMC_NANDInitStruct->CommSpaceTimingStruct->SetTime
|
||||
| (XFMC_NANDInitStruct->CommSpaceTimingStruct->WaitSetTime << 8)
|
||||
| (XFMC_NANDInitStruct->CommSpaceTimingStruct->HoldSetTime << 16)
|
||||
| (XFMC_NANDInitStruct->CommSpaceTimingStruct->HiZSetTime << 24);
|
||||
|
||||
/* Set tmppatt value according to XFMC_AttributeSpaceTimingStructure parameters */
|
||||
tmppatt = (uint32_t)XFMC_NANDInitStruct->AttrSpaceTimingStruct->SetTime
|
||||
| (XFMC_NANDInitStruct->AttrSpaceTimingStruct->WaitSetTime << 8)
|
||||
| (XFMC_NANDInitStruct->AttrSpaceTimingStruct->HoldSetTime << 16)
|
||||
| (XFMC_NANDInitStruct->AttrSpaceTimingStruct->HiZSetTime << 24);
|
||||
|
||||
if (XFMC_NANDInitStruct->Bank == XFMC_BANK2_NAND)
|
||||
{
|
||||
/* XFMC_BANK2_NAND registers configuration */
|
||||
XFMC_BANK2->BK2CTRL = tmppcr;
|
||||
XFMC_BANK2->CMEM2 = tmppmem;
|
||||
XFMC_BANK2->ATTR2 = tmppatt;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* XFMC_BANK3_NAND registers configuration */
|
||||
XFMC_BANK3->BK3CTRL = tmppcr;
|
||||
XFMC_BANK3->CMEM3 = tmppmem;
|
||||
XFMC_BANK3->ATTR3 = tmppatt;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each XFMC_NORSRAMInitStruct member with its default value.
|
||||
* @param XFMC_NORSRAMInitStruct pointer to a XFMC_NorSramInitTpye
|
||||
* structure which will be initialized.
|
||||
*/
|
||||
void XFMC_InitNorSramStruct(XFMC_NorSramInitTpye* XFMC_NORSRAMInitStruct)
|
||||
{
|
||||
/* Reset NOR/SRAM Init structure parameters values */
|
||||
XFMC_NORSRAMInitStruct->Bank = XFMC_BANK1_NORSRAM1;
|
||||
XFMC_NORSRAMInitStruct->DataAddrMux = XFMC_DATA_ADDR_MUX_ENABLE;
|
||||
XFMC_NORSRAMInitStruct->MemType = XFMC_MEM_TYPE_SRAM;
|
||||
XFMC_NORSRAMInitStruct->MemDataWidth = XFMC_MEM_DATA_WIDTH_8B;
|
||||
XFMC_NORSRAMInitStruct->BurstAccMode = XFMC_BURST_ACC_MODE_DISABLE;
|
||||
XFMC_NORSRAMInitStruct->AsynchroWait = XFMC_ASYNCHRO_WAIT_DISABLE;
|
||||
XFMC_NORSRAMInitStruct->WaitSigPolarity = XFMC_WAIT_SIGNAL_POLARITY_LOW;
|
||||
XFMC_NORSRAMInitStruct->WrapMode = XFMC_WRAP_MODE_DISABLE;
|
||||
XFMC_NORSRAMInitStruct->WaitSigConfig = XFMC_WAIT_SIG_ACTIVE_BEFORE_WAIT_STATE;
|
||||
XFMC_NORSRAMInitStruct->WriteEnable = XFMC_WRITE_ENABLE;
|
||||
XFMC_NORSRAMInitStruct->WaitSigEnable = XFMC_WAIT_SIGNAL_ENABLE;
|
||||
XFMC_NORSRAMInitStruct->ExtModeEnable = XFMC_EXTENDED_DISABLE;
|
||||
XFMC_NORSRAMInitStruct->WriteBurstEnable = XFMC_WRITE_BURST_DISABLE;
|
||||
XFMC_NORSRAMInitStruct->RWTimingStruct->AddrSetTime = 0xF;
|
||||
XFMC_NORSRAMInitStruct->RWTimingStruct->AddrHoldTime = 0xF;
|
||||
XFMC_NORSRAMInitStruct->RWTimingStruct->DataSetTime = 0xFF;
|
||||
XFMC_NORSRAMInitStruct->RWTimingStruct->BusRecoveryCycle = 0xF;
|
||||
XFMC_NORSRAMInitStruct->RWTimingStruct->ClkDiv = 0xF;
|
||||
XFMC_NORSRAMInitStruct->RWTimingStruct->DataLatency = 0xF;
|
||||
XFMC_NORSRAMInitStruct->RWTimingStruct->AccMode = XFMC_ACC_MODE_A;
|
||||
XFMC_NORSRAMInitStruct->WTimingStruct->AddrSetTime = 0xF;
|
||||
XFMC_NORSRAMInitStruct->WTimingStruct->AddrHoldTime = 0xF;
|
||||
XFMC_NORSRAMInitStruct->WTimingStruct->DataSetTime = 0xFF;
|
||||
XFMC_NORSRAMInitStruct->WTimingStruct->BusRecoveryCycle = 0xF;
|
||||
XFMC_NORSRAMInitStruct->WTimingStruct->ClkDiv = 0xF;
|
||||
XFMC_NORSRAMInitStruct->WTimingStruct->DataLatency = 0xF;
|
||||
XFMC_NORSRAMInitStruct->WTimingStruct->AccMode = XFMC_ACC_MODE_A;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each XFMC_NANDInitStruct member with its default value.
|
||||
* @param XFMC_NANDInitStruct pointer to a XFMC_NandInitType
|
||||
* structure which will be initialized.
|
||||
*/
|
||||
void XFMC_InitNandStruct(XFMC_NandInitType* XFMC_NANDInitStruct)
|
||||
{
|
||||
/* Reset NAND Init structure parameters values */
|
||||
XFMC_NANDInitStruct->Bank = XFMC_BANK2_NAND;
|
||||
XFMC_NANDInitStruct->WaitFeatureEnable = XFMC_WAIT_FEATURE_DISABLE;
|
||||
XFMC_NANDInitStruct->MemDataWidth = XFMC_MEM_DATA_WIDTH_8B;
|
||||
XFMC_NANDInitStruct->EccEnable = XFMC_ECC_DISABLE;
|
||||
XFMC_NANDInitStruct->EccPageSize = XFMC_ECC_PAGE_SIZE_256BYTES;
|
||||
XFMC_NANDInitStruct->TCLRSetTime = 0x0;
|
||||
XFMC_NANDInitStruct->TARSetTime = 0x0;
|
||||
XFMC_NANDInitStruct->CommSpaceTimingStruct->SetTime = 0xFC;
|
||||
XFMC_NANDInitStruct->CommSpaceTimingStruct->WaitSetTime = 0xFC;
|
||||
XFMC_NANDInitStruct->CommSpaceTimingStruct->HoldSetTime = 0xFC;
|
||||
XFMC_NANDInitStruct->CommSpaceTimingStruct->HiZSetTime = 0xFC;
|
||||
XFMC_NANDInitStruct->AttrSpaceTimingStruct->SetTime = 0xFC;
|
||||
XFMC_NANDInitStruct->AttrSpaceTimingStruct->WaitSetTime = 0xFC;
|
||||
XFMC_NANDInitStruct->AttrSpaceTimingStruct->HoldSetTime = 0xFC;
|
||||
XFMC_NANDInitStruct->AttrSpaceTimingStruct->HiZSetTime = 0xFC;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified NOR/SRAM Memory Bank.
|
||||
* @param Bank specifies the XFMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg XFMC_BANK1_NORSRAM1 XFMC Bank1 NOR/SRAM1
|
||||
* @arg XFMC_BANK1_NORSRAM2 XFMC Bank1 NOR/SRAM2
|
||||
* @arg XFMC_BANK1_NORSRAM3 XFMC Bank1 NOR/SRAM3
|
||||
* @arg XFMC_BANK1_NORSRAM4 XFMC Bank1 NOR/SRAM4
|
||||
* @param Cmd new state of the Bank. This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void XFMC_EnableNorSram(uint32_t Bank, FunctionalState Cmd)
|
||||
{
|
||||
assert_param(IS_XFMC_NORSRAM_BANK(Bank));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
/* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
|
||||
XFMC_BANK1->BK1CSTCTRL[Bank] |= BCR_MBKEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
|
||||
XFMC_BANK1->BK1CSTCTRL[Bank] &= BCR_MBKEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified NAND Memory Bank.
|
||||
* @param Bank specifies the XFMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg XFMC_BANK2_NAND XFMC Bank2 NAND
|
||||
* @arg XFMC_BANK3_NAND XFMC Bank3 NAND
|
||||
* @param Cmd new state of the Bank. This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void XFMC_EnableNand(uint32_t Bank, FunctionalState Cmd)
|
||||
{
|
||||
assert_param(IS_XFMC_NAND_BANK(Bank));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
/* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
|
||||
if (Bank == XFMC_BANK2_NAND)
|
||||
{
|
||||
XFMC_BANK2->BK2CTRL |= PCR_PBKEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
XFMC_BANK3->BK3CTRL |= PCR_PBKEN_Set;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
|
||||
if (Bank == XFMC_BANK2_NAND)
|
||||
{
|
||||
XFMC_BANK2->BK2CTRL &= PCR_PBKEN_Reset;
|
||||
}
|
||||
else
|
||||
{
|
||||
XFMC_BANK3->BK3CTRL &= PCR_PBKEN_Reset;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the XFMC NAND ECC feature.
|
||||
* @param Bank specifies the XFMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg XFMC_BANK2_NAND XFMC Bank2 NAND
|
||||
* @arg XFMC_BANK3_NAND XFMC Bank3 NAND
|
||||
* @param Cmd new state of the XFMC NAND ECC feature.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
*/
|
||||
void XFMC_EnableNandEcc(uint32_t Bank, FunctionalState Cmd)
|
||||
{
|
||||
assert_param(IS_XFMC_NAND_BANK(Bank));
|
||||
assert_param(IS_FUNCTIONAL_STATE(Cmd));
|
||||
|
||||
if (Cmd != DISABLE)
|
||||
{
|
||||
/* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
|
||||
if (Bank == XFMC_BANK2_NAND)
|
||||
{
|
||||
XFMC_BANK2->BK2CTRL |= PCR_ECCEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
XFMC_BANK3->BK3CTRL |= PCR_ECCEN_Set;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
|
||||
if (Bank == XFMC_BANK2_NAND)
|
||||
{
|
||||
XFMC_BANK2->BK2CTRL &= PCR_ECCEN_Reset;
|
||||
}
|
||||
else
|
||||
{
|
||||
XFMC_BANK3->BK3CTRL &= PCR_ECCEN_Reset;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the error correction code register value.
|
||||
* @param Bank specifies the XFMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg XFMC_BANK2_NAND XFMC Bank2 NAND
|
||||
* @arg XFMC_BANK3_NAND XFMC Bank3 NAND
|
||||
* @return The Error Correction Code (ECC) value.
|
||||
*/
|
||||
uint32_t XFMC_GetEcc(uint32_t Bank)
|
||||
{
|
||||
uint32_t eccval = 0x00000000;
|
||||
|
||||
if (Bank == XFMC_BANK2_NAND)
|
||||
{
|
||||
/* Get the ECC2 register value */
|
||||
eccval = XFMC_BANK2->ECC2;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get the ECC3 register value */
|
||||
eccval = XFMC_BANK3->ECC3;
|
||||
}
|
||||
/* Return the error correction code value */
|
||||
return (eccval);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified XFMC flag is set or not.
|
||||
* @param Bank specifies the XFMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg XFMC_BANK2_NAND XFMC Bank2 NAND
|
||||
* @arg XFMC_BANK3_NAND XFMC Bank3 NAND
|
||||
* @arg XFMC_Bank4_PCCARD XFMC Bank4 PCCARD
|
||||
* @param XFMC_FLAG specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg XFMC_FLAG_RisingEdge Rising egde detection Flag.
|
||||
* @arg XFMC_FLAG_Level Level detection Flag.
|
||||
* @arg XFMC_FLAG_FallingEdge Falling egde detection Flag.
|
||||
* @arg XFMC_FLAG_FEMPT Fifo empty Flag.
|
||||
* @return The new state of XFMC_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus XFMC_GetFlag(uint32_t Bank, uint32_t XFMC_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
uint32_t tmpsr = 0x00000000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_XFMC_GETFLAG_BANK(Bank));
|
||||
assert_param(IS_XFMC_GET_FLAG(XFMC_FLAG));
|
||||
|
||||
if (Bank == XFMC_BANK2_NAND)
|
||||
{
|
||||
tmpsr = XFMC_BANK2->STS2;
|
||||
}
|
||||
else if (Bank == XFMC_BANK3_NAND)
|
||||
{
|
||||
tmpsr = XFMC_BANK3->STS3;
|
||||
}
|
||||
|
||||
/* Get the flag status */
|
||||
if ((tmpsr & XFMC_FLAG) != (uint16_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the XFMC's pending flags.
|
||||
* @param Bank specifies the XFMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg XFMC_BANK2_NAND XFMC Bank2 NAND
|
||||
* @arg XFMC_BANK3_NAND XFMC Bank3 NAND
|
||||
* @param XFMC_FLAG specifies the flag to clear.
|
||||
*/
|
||||
void XFMC_ClrFlag(uint32_t Bank, uint32_t XFMC_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_XFMC_GETFLAG_BANK(Bank));
|
||||
assert_param(IS_XFMC_CLEAR_FLAG(XFMC_FLAG));
|
||||
|
||||
if (Bank == XFMC_BANK2_NAND)
|
||||
{
|
||||
XFMC_BANK2->STS2 &= ~XFMC_FLAG;
|
||||
}
|
||||
else if (Bank == XFMC_BANK3_NAND)
|
||||
{
|
||||
XFMC_BANK3->STS3 &= ~XFMC_FLAG;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,264 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file usb_core.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __USB_CORE_H__
|
||||
#define __USB_CORE_H__
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/**
|
||||
* @addtogroup N32G45X_USB_Driver
|
||||
* @brief N32G45x USB low level driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum _CONTROL_STATE
|
||||
{
|
||||
WaitSetup, /* 0 */
|
||||
SettingUp, /* 1 */
|
||||
InData, /* 2 */
|
||||
OutData, /* 3 */
|
||||
LastInData, /* 4 */
|
||||
LastOutData, /* 5 */
|
||||
WaitStatusIn, /* 7 */
|
||||
WaitStatusOut, /* 8 */
|
||||
Stalled, /* 9 */
|
||||
Pause /* 10 */
|
||||
} USB_ControlState; /* The state machine states of a control pipe */
|
||||
|
||||
typedef struct OneDescriptor
|
||||
{
|
||||
uint8_t* Descriptor;
|
||||
uint16_t Descriptor_Size;
|
||||
} USB_OneDescriptor, *PONE_DESCRIPTOR;
|
||||
/* All the request process routines return a value of this type
|
||||
If the return value is not SUCCESS or NOT_READY,
|
||||
the software will STALL the correspond endpoint */
|
||||
typedef enum _RESULT
|
||||
{
|
||||
Success = 0, /* Process successfully */
|
||||
Error,
|
||||
UnSupport,
|
||||
Not_Ready /* The process has not been finished, endpoint will be
|
||||
NAK to further request */
|
||||
} USB_Result;
|
||||
|
||||
/*-*-*-*-*-*-*-*-*-*-* Definitions for endpoint level -*-*-*-*-*-*-*-*-*-*-*-*/
|
||||
typedef struct _ENDPOINT_INFO
|
||||
{
|
||||
/* When send data out of the device,
|
||||
CopyData() is used to get data buffer 'Length' bytes data
|
||||
if Length is 0,
|
||||
CopyData() returns the total length of the data
|
||||
if the request is not supported, returns 0
|
||||
(NEW Feature )
|
||||
if CopyData() returns -1, the calling routine should not proceed
|
||||
further and will resume the SETUP process by the class device
|
||||
if Length is not 0,
|
||||
CopyData() returns a pointer to indicate the data location
|
||||
Usb_wLength is the data remain to be sent,
|
||||
Usb_wOffset is the Offset of original data
|
||||
When receive data from the host,
|
||||
CopyData() is used to get user data buffer which is capable
|
||||
of Length bytes data to copy data from the endpoint buffer.
|
||||
if Length is 0,
|
||||
CopyData() returns the available data length,
|
||||
if Length is not 0,
|
||||
CopyData() returns user buffer address
|
||||
Usb_rLength is the data remain to be received,
|
||||
Usb_rPointer is the Offset of data buffer
|
||||
*/
|
||||
uint16_t Usb_wLength;
|
||||
uint16_t Usb_wOffset;
|
||||
uint16_t PacketSize;
|
||||
uint8_t* (*CopyData)(uint16_t Length);
|
||||
} USB_EndpointMess;
|
||||
|
||||
/*-*-*-*-*-*-*-*-*-*-*-* Definitions for device level -*-*-*-*-*-*-*-*-*-*-*-*/
|
||||
|
||||
typedef struct _DEVICE
|
||||
{
|
||||
uint8_t TotalEndpoint; /* Number of endpoints that are used */
|
||||
uint8_t TotalConfiguration; /* Number of configuration available */
|
||||
} USB_Device;
|
||||
|
||||
typedef union
|
||||
{
|
||||
uint16_t w;
|
||||
struct BW
|
||||
{
|
||||
uint8_t bb1;
|
||||
uint8_t bb0;
|
||||
} bw;
|
||||
} uint16_t_uint8_t;
|
||||
|
||||
typedef struct _DEVICE_INFO
|
||||
{
|
||||
uint8_t bmRequestType; /* bmRequestType */
|
||||
uint8_t bRequest; /* bRequest */
|
||||
uint16_t_uint8_t wValues; /* wValue */
|
||||
uint16_t_uint8_t wIndexs; /* wIndex */
|
||||
uint16_t_uint8_t wLengths; /* wLength */
|
||||
|
||||
uint8_t CtrlState; /* of type USB_ControlState */
|
||||
uint8_t CurrentFeature;
|
||||
uint8_t CurrentConfiguration; /* Selected configuration */
|
||||
uint8_t CurrentInterface; /* Selected interface of current configuration */
|
||||
uint8_t CurrentAlternateSetting; /* Selected Alternate Setting of current
|
||||
interface*/
|
||||
|
||||
USB_EndpointMess Ctrl_Info;
|
||||
} USB_DeviceMess;
|
||||
|
||||
typedef struct _DEVICE_PROP
|
||||
{
|
||||
void (*Init)(void); /* Initialize the device */
|
||||
void (*Reset)(void); /* Reset routine of this device */
|
||||
|
||||
/* Device dependent process after the status stage */
|
||||
void (*Process_Status_IN)(void);
|
||||
void (*Process_Status_OUT)(void);
|
||||
|
||||
/* Procedure of process on setup stage of a class specified request with data stage */
|
||||
/* All class specified requests with data stage are processed in Class_Data_Setup
|
||||
Class_Data_Setup()
|
||||
responses to check all special requests and fills USB_EndpointMess
|
||||
according to the request
|
||||
If IN tokens are expected, then wLength & wOffset will be filled
|
||||
with the total transferring bytes and the starting position
|
||||
If OUT tokens are expected, then rLength & rOffset will be filled
|
||||
with the total expected bytes and the starting position in the buffer
|
||||
|
||||
If the request is valid, Class_Data_Setup returns SUCCESS, else UNSUPPORT
|
||||
|
||||
CAUTION:
|
||||
Since GET_CONFIGURATION & GET_INTERFACE are highly related to
|
||||
the individual classes, they will be checked and processed here.
|
||||
*/
|
||||
USB_Result (*Class_Data_Setup)(uint8_t RequestNo);
|
||||
|
||||
/* Procedure of process on setup stage of a class specified request without data stage */
|
||||
/* All class specified requests without data stage are processed in Class_NoData_Setup
|
||||
Class_NoData_Setup
|
||||
responses to check all special requests and perform the request
|
||||
|
||||
CAUTION:
|
||||
Since SET_CONFIGURATION & SET_INTERFACE are highly related to
|
||||
the individual classes, they will be checked and processed here.
|
||||
*/
|
||||
USB_Result (*Class_NoData_Setup)(uint8_t RequestNo);
|
||||
|
||||
/*Class_Get_Interface_Setting
|
||||
This function is used by the file usb_core.c to test if the selected Interface
|
||||
and Alternate Setting (uint8_t Interface, uint8_t AlternateSetting) are supported by
|
||||
the application.
|
||||
This function is writing by user. It should return "SUCCESS" if the Interface
|
||||
and Alternate Setting are supported by the application or "UNSUPPORT" if they
|
||||
are not supported. */
|
||||
|
||||
USB_Result (*Class_Get_Interface_Setting)(uint8_t Interface, uint8_t AlternateSetting);
|
||||
|
||||
uint8_t* (*GetDeviceDescriptor)(uint16_t Length);
|
||||
uint8_t* (*GetConfigDescriptor)(uint16_t Length);
|
||||
uint8_t* (*GetStringDescriptor)(uint16_t Length);
|
||||
|
||||
/* This field is not used in current library version. It is kept only for
|
||||
compatibility with previous versions */
|
||||
void* RxEP_buffer;
|
||||
|
||||
uint8_t MaxPacketSize;
|
||||
|
||||
} DEVICE_PROP;
|
||||
|
||||
typedef struct _USER_STANDARD_REQUESTS
|
||||
{
|
||||
void (*User_GetConfiguration)(void); /* Get Configuration */
|
||||
void (*User_SetConfiguration)(void); /* Set Configuration */
|
||||
void (*User_GetInterface)(void); /* Get Interface */
|
||||
void (*User_SetInterface)(void); /* Set Interface */
|
||||
void (*User_GetStatus)(void); /* Get Status */
|
||||
void (*User_ClearFeature)(void); /* Clear Feature */
|
||||
void (*User_SetEndPointFeature)(void); /* Set Endpoint Feature */
|
||||
void (*User_SetDeviceFeature)(void); /* Set Device Feature */
|
||||
void (*User_SetDeviceAddress)(void); /* Set Device Address */
|
||||
} USER_STANDARD_REQUESTS;
|
||||
|
||||
#define Type_Recipient (pInformation->bmRequestType & (REQUEST_TYPE | RECIPIENT))
|
||||
|
||||
#define Usb_rLength Usb_wLength
|
||||
#define Usb_rOffset Usb_wOffset
|
||||
|
||||
#define USBwValue wValues.w
|
||||
#define USBwValue0 wValues.bw.bb0
|
||||
#define USBwValue1 wValues.bw.bb1
|
||||
#define USBwIndex wIndexs.w
|
||||
#define USBwIndex0 wIndexs.bw.bb0
|
||||
#define USBwIndex1 wIndexs.bw.bb1
|
||||
#define USBwLength wLengths.w
|
||||
#define USBwLength0 wLengths.bw.bb0
|
||||
#define USBwLength1 wLengths.bw.bb1
|
||||
|
||||
uint8_t USB_ProcessSetup0(void);
|
||||
uint8_t USB_ProcessPost0(void);
|
||||
uint8_t USB_ProcessOut0(void);
|
||||
uint8_t USB_ProcessIn0(void);
|
||||
|
||||
USB_Result Standard_SetEndPointFeature(void);
|
||||
USB_Result Standard_SetDeviceFeature(void);
|
||||
|
||||
uint8_t* Standard_GetConfiguration(uint16_t Length);
|
||||
USB_Result Standard_SetConfiguration(void);
|
||||
uint8_t* Standard_GetInterface(uint16_t Length);
|
||||
USB_Result Standard_SetInterface(void);
|
||||
uint8_t* Standard_GetDescriptorData(uint16_t Length, PONE_DESCRIPTOR pDesc);
|
||||
|
||||
uint8_t* Standard_GetStatus(uint16_t Length);
|
||||
USB_Result Standard_ClearFeature(void);
|
||||
void USB_SetDeviceAddress(uint8_t);
|
||||
void USB_ProcessNop(void);
|
||||
|
||||
extern DEVICE_PROP Device_Property;
|
||||
extern USER_STANDARD_REQUESTS User_Standard_Requests;
|
||||
extern USB_Device Device_Table;
|
||||
extern USB_DeviceMess Device_Info;
|
||||
|
||||
/* cells saving status during interrupt servicing */
|
||||
extern __IO uint16_t SaveRState;
|
||||
extern __IO uint16_t SaveTState;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __USB_CORE_H__ */
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file usb_def.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __USB_DEF_H__
|
||||
#define __USB_DEF_H__
|
||||
|
||||
/**
|
||||
* @addtogroup N32G45X_USB_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum _RECIPIENT_TYPE
|
||||
{
|
||||
DEVICE_RECIPIENT, /* Recipient device */
|
||||
INTERFACE_RECIPIENT, /* Recipient interface */
|
||||
ENDPOINT_RECIPIENT, /* Recipient endpoint */
|
||||
OTHER_RECIPIENT
|
||||
} RECIPIENT_TYPE;
|
||||
|
||||
typedef enum _STANDARD_REQUESTS
|
||||
{
|
||||
GET_STATUS = 0,
|
||||
CLR_FEATURE,
|
||||
RESERVED1,
|
||||
SET_FEATURE,
|
||||
RESERVED2,
|
||||
SET_ADDRESS,
|
||||
GET_DESCRIPTOR,
|
||||
SET_DESCRIPTOR,
|
||||
GET_CONFIGURATION,
|
||||
SET_CONFIGURATION,
|
||||
GET_INTERFACE,
|
||||
SET_INTERFACE,
|
||||
TOTAL_SREQUEST, /* Total number of Standard request */
|
||||
SYNCH_FRAME = 12
|
||||
} STANDARD_REQUESTS;
|
||||
|
||||
/* Definition of "USBwValue" */
|
||||
typedef enum _DESCRIPTOR_TYPE
|
||||
{
|
||||
DEVICE_DESCRIPTOR = 1,
|
||||
CONFIG_DESCRIPTOR,
|
||||
STRING_DESCRIPTOR,
|
||||
INTERFACE_DESCRIPTOR,
|
||||
ENDPOINT_DESCRIPTOR
|
||||
} DESCRIPTOR_TYPE;
|
||||
|
||||
/* Feature selector of a SET_FEATURE or CLR_FEATURE */
|
||||
typedef enum _FEATURE_SELECTOR
|
||||
{
|
||||
ENDPOINT_STALL,
|
||||
DEVICE_REMOTE_WAKEUP
|
||||
} FEATURE_SELECTOR;
|
||||
|
||||
/* Definition of "bmRequestType" */
|
||||
#define REQUEST_TYPE 0x60 /* Mask to get request type */
|
||||
#define STANDARD_REQUEST 0x00 /* Standard request */
|
||||
#define CLASS_REQUEST 0x20 /* Class request */
|
||||
#define VENDOR_REQUEST 0x40 /* Vendor request */
|
||||
|
||||
#define RECIPIENT 0x1F /* Mask to get recipient */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __USB_DEF_H__ */
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file usb_init.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __USB_INIT_H__
|
||||
#define __USB_INIT_H__
|
||||
|
||||
#include "n32g45x.h"
|
||||
#include "usb_core.h"
|
||||
|
||||
/**
|
||||
* @addtogroup N32G45X_USB_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
void USB_Init(void);
|
||||
|
||||
/* The number of current endpoint, it will be used to specify an endpoint */
|
||||
extern uint8_t EPindex;
|
||||
/* The number of current device, it is an index to the Device_Table */
|
||||
/*extern uint8_t Device_no; */
|
||||
/* Points to the USB_DeviceMess structure of current device */
|
||||
/* The purpose of this register is to speed up the execution */
|
||||
extern USB_DeviceMess* pInformation;
|
||||
/* Points to the DEVICE_PROP structure of current device */
|
||||
/* The purpose of this register is to speed up the execution */
|
||||
extern DEVICE_PROP* pProperty;
|
||||
/* Temporary save the state of Rx & Tx status. */
|
||||
/* Whenever the Rx or Tx state is changed, its value is saved */
|
||||
/* in this variable first and will be set to the EPRB or EPRA */
|
||||
/* at the end of interrupt process */
|
||||
extern USER_STANDARD_REQUESTS* pUser_Standard_Requests;
|
||||
|
||||
extern uint16_t SaveState;
|
||||
extern uint16_t wInterrupt_Mask;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __USB_INIT_H__ */
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file usb_int.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __USB_INT_H__
|
||||
#define __USB_INT_H__
|
||||
|
||||
/**
|
||||
* @addtogroup N32G45X_USB_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
void USB_CorrectTransferLp(void);
|
||||
void USB_CorrectTransferHp(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __USB_INT_H__ */
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file usb_lib.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __USB_LIB_H__
|
||||
#define __USB_LIB_H__
|
||||
|
||||
#include "usb_type.h"
|
||||
#include "usb_regs.h"
|
||||
#include "usb_def.h"
|
||||
#include "usb_core.h"
|
||||
#include "usb_init.h"
|
||||
#include "usb_sil.h"
|
||||
#include "usb_mem.h"
|
||||
#include "usb_int.h"
|
||||
|
||||
#endif /* __USB_LIB_H__ */
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file usb_mem.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __USB_MEM_H__
|
||||
#define __USB_MEM_H__
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/**
|
||||
* @addtogroup N32G45X_USB_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
void USB_CopyUserToPMABuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||
void USB_CopyPMAToUserBuf(uint8_t* pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /*__USB_MEM_H__*/
|
||||
|
|
@ -0,0 +1,706 @@
|
|||
/*****************************************************************************
|
||||
* Copyright (c) 2019, Nations Technologies Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
* ****************************************************************************
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* - Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the disclaimer below.
|
||||
*
|
||||
* Nations' name may not be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
|
||||
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* ****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file usb_regs.h
|
||||
* @author Nations Solution Team
|
||||
* @version v1.0.0
|
||||
*
|
||||
* @copyright Copyright (c) 2019, Nations Technologies Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __USB_REGS_H__
|
||||
#define __USB_REGS_H__
|
||||
|
||||
#include "n32g45x.h"
|
||||
|
||||
/**
|
||||
* @addtogroup N32G45X_USB_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum _EP_DBUF_DIR
|
||||
{
|
||||
/* double buffered endpoint direction */
|
||||
EP_DBUF_ERR,
|
||||
EP_DBUF_OUT,
|
||||
EP_DBUF_IN
|
||||
} EP_DBUF_DIR;
|
||||
|
||||
/* endpoint buffer number */
|
||||
enum EP_BUF_NUM
|
||||
{
|
||||
EP_NOBUF,
|
||||
EP_BUF0,
|
||||
EP_BUF1
|
||||
};
|
||||
|
||||
#define RegBase (0x40005C00L) /* USB_IP Peripheral Registers base address */
|
||||
#define PMAAddr (0x40006000L) /* USB_IP Packet Memory Area base address */
|
||||
|
||||
/******************************************************************************/
|
||||
/* General registers */
|
||||
/******************************************************************************/
|
||||
|
||||
/* Control register */
|
||||
#define USB_CTRL ((__IO unsigned*)(RegBase + 0x40))
|
||||
/* Interrupt status register */
|
||||
#define USB_STS ((__IO unsigned*)(RegBase + 0x44))
|
||||
/* Frame number register */
|
||||
#define USB_FN ((__IO unsigned*)(RegBase + 0x48))
|
||||
/* Device address register */
|
||||
#define USB_ADDR ((__IO unsigned*)(RegBase + 0x4C))
|
||||
/* Buffer Table address register */
|
||||
#define USB_BUFTAB ((__IO unsigned*)(RegBase + 0x50))
|
||||
/******************************************************************************/
|
||||
/* Endpoint registers */
|
||||
/******************************************************************************/
|
||||
#define EP0REG ((__IO unsigned*)(RegBase)) /* endpoint 0 register address */
|
||||
|
||||
/* Endpoint Addresses (w/direction) */
|
||||
#define EP0_OUT ((uint8_t)0x00)
|
||||
#define EP0_IN ((uint8_t)0x80)
|
||||
#define EP1_OUT ((uint8_t)0x01)
|
||||
#define EP1_IN ((uint8_t)0x81)
|
||||
#define EP2_OUT ((uint8_t)0x02)
|
||||
#define EP2_IN ((uint8_t)0x82)
|
||||
#define EP3_OUT ((uint8_t)0x03)
|
||||
#define EP3_IN ((uint8_t)0x83)
|
||||
#define EP4_OUT ((uint8_t)0x04)
|
||||
#define EP4_IN ((uint8_t)0x84)
|
||||
#define EP5_OUT ((uint8_t)0x05)
|
||||
#define EP5_IN ((uint8_t)0x85)
|
||||
#define EP6_OUT ((uint8_t)0x06)
|
||||
#define EP6_IN ((uint8_t)0x86)
|
||||
#define EP7_OUT ((uint8_t)0x07)
|
||||
#define EP7_IN ((uint8_t)0x87)
|
||||
|
||||
/* endpoints enumeration */
|
||||
#define ENDP0 ((uint8_t)0)
|
||||
#define ENDP1 ((uint8_t)1)
|
||||
#define ENDP2 ((uint8_t)2)
|
||||
#define ENDP3 ((uint8_t)3)
|
||||
#define ENDP4 ((uint8_t)4)
|
||||
#define ENDP5 ((uint8_t)5)
|
||||
#define ENDP6 ((uint8_t)6)
|
||||
#define ENDP7 ((uint8_t)7)
|
||||
|
||||
/******************************************************************************/
|
||||
/* USB_STS interrupt events */
|
||||
/******************************************************************************/
|
||||
#define STS_CTRS (0x8000) /* Correct TRansfer (clear-only bit) */
|
||||
#define STS_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */
|
||||
#define STS_ERROR (0x2000) /* ERRor (clear-only bit) */
|
||||
#define STS_WKUP (0x1000) /* WaKe UP (clear-only bit) */
|
||||
#define STS_SUSPD (0x0800) /* SUSPend (clear-only bit) */
|
||||
#define STS_RST (0x0400) /* RESET (clear-only bit) */
|
||||
#define STS_SOF (0x0200) /* Start Of Frame (clear-only bit) */
|
||||
#define STS_ESOF (0x0100) /* Expected Start Of Frame (clear-only bit) */
|
||||
|
||||
#define STS_DIR (0x0010) /* DIRection of transaction (read-only bit) */
|
||||
#define STS_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */
|
||||
|
||||
#define CLR_CTRS (~STS_CTRS) /* clear Correct TRansfer bit */
|
||||
#define CLR_DOVR (~STS_DOVR) /* clear DMA OVeR/underrun bit*/
|
||||
#define CLR_ERROR (~STS_ERROR) /* clear ERRor bit */
|
||||
#define CLR_WKUP (~STS_WKUP) /* clear WaKe UP bit */
|
||||
#define CLR_SUSPD (~STS_SUSPD) /* clear SUSPend bit */
|
||||
#define CLR_RST (~STS_RST) /* clear RESET bit */
|
||||
#define CLR_SOF (~STS_SOF) /* clear Start Of Frame bit */
|
||||
#define CLR_ESOF (~STS_ESOF) /* clear Expected Start Of Frame bit */
|
||||
|
||||
/******************************************************************************/
|
||||
/* USB_CTRL control register bits definitions */
|
||||
/******************************************************************************/
|
||||
#define CTRL_CTRSM (0x8000) /* Correct TRansfer Mask */
|
||||
#define CTRL_DOVRM (0x4000) /* DMA OVeR/underrun Mask */
|
||||
#define CTRL_ERRORM (0x2000) /* ERRor Mask */
|
||||
#define CTRL_WKUPM (0x1000) /* WaKe UP Mask */
|
||||
#define CTRL_SUSPDM (0x0800) /* SUSPend Mask */
|
||||
#define CTRL_RSTM (0x0400) /* RESET Mask */
|
||||
#define CTRL_SOFM (0x0200) /* Start Of Frame Mask */
|
||||
#define CTRL_ESOFM (0x0100) /* Expected Start Of Frame Mask */
|
||||
|
||||
#define CTRL_RESUM (0x0010) /* RESUME request */
|
||||
#define CTRL_FSUSPD (0x0008) /* Force SUSPend */
|
||||
#define CTRL_LP_MODE (0x0004) /* Low-power MODE */
|
||||
#define CTRL_PD (0x0002) /* Power DoWN */
|
||||
#define CTRL_FRST (0x0001) /* Force USB RESet */
|
||||
|
||||
/******************************************************************************/
|
||||
/* USB_FN Frame Number Register bit definitions */
|
||||
/******************************************************************************/
|
||||
#define FN_RXDP (0x8000) /* status of D+ data line */
|
||||
#define FN_RXDM (0x4000) /* status of D- data line */
|
||||
#define FN_LCK (0x2000) /* LoCKed */
|
||||
#define FN_LSOF (0x1800) /* Lost SOF */
|
||||
#define FN_FNUM (0x07FF) /* Frame Number */
|
||||
/******************************************************************************/
|
||||
/* USB_ADDR Device ADDRess bit definitions */
|
||||
/******************************************************************************/
|
||||
#define ADDR_EFUC (0x80)
|
||||
#define ADDR_ADDR (0x7F)
|
||||
/******************************************************************************/
|
||||
/* Endpoint register */
|
||||
/******************************************************************************/
|
||||
/* bit positions */
|
||||
#define EP_CTRS_RX (0x8000) /* EndPoint Correct TRansfer RX */
|
||||
#define EP_DATTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */
|
||||
#define EPRX_STS (0x3000) /* EndPoint RX STATus bit field */
|
||||
#define EP_SETUP (0x0800) /* EndPoint SETUP */
|
||||
#define EP_T_FIELD (0x0600) /* EndPoint TYPE */
|
||||
#define EP_KIND (0x0100) /* EndPoint KIND */
|
||||
#define EP_CTRS_TX (0x0080) /* EndPoint Correct TRansfer TX */
|
||||
#define EP_DATTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */
|
||||
#define EPTX_STS (0x0030) /* EndPoint TX STATus bit field */
|
||||
#define EPADDR_FIELD (0x000F) /* EndPoint ADDRess FIELD */
|
||||
|
||||
/* EndPoint REGister INTEN (no toggle fields) */
|
||||
#define EPREG_MASK (EP_CTRS_RX | EP_SETUP | EP_T_FIELD | EP_KIND | EP_CTRS_TX | EPADDR_FIELD)
|
||||
|
||||
/* EP_TYPE[1:0] EndPoint TYPE */
|
||||
#define EP_TYPE_MASK (0x0600) /* EndPoint TYPE Mask */
|
||||
#define EP_BULK (0x0000) /* EndPoint BULK */
|
||||
#define EP_CONTROL (0x0200) /* EndPoint CONTROL */
|
||||
#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */
|
||||
#define EP_INTERRUPT (0x0600) /* EndPoint INTERRUPT */
|
||||
#define EP_T_MASK (~EP_T_FIELD & EPREG_MASK)
|
||||
|
||||
/* EP_KIND EndPoint KIND */
|
||||
#define EPKIND_MASK (~EP_KIND & EPREG_MASK)
|
||||
|
||||
/* STAT_TX[1:0] STATus for TX transfer */
|
||||
#define EP_TX_DIS (0x0000) /* EndPoint TX DISabled */
|
||||
#define EP_TX_STALL (0x0010) /* EndPoint TX STALLed */
|
||||
#define EP_TX_NAK (0x0020) /* EndPoint TX NAKed */
|
||||
#define EP_TX_VALID (0x0030) /* EndPoint TX VALID */
|
||||
#define EPTX_DATTOG1 (0x0010) /* EndPoint TX Data TOGgle bit1 */
|
||||
#define EPTX_DATTOG2 (0x0020) /* EndPoint TX Data TOGgle bit2 */
|
||||
#define EPTX_DATTOGMASK (EPTX_STS | EPREG_MASK)
|
||||
|
||||
/* STAT_RX[1:0] STATus for RX transfer */
|
||||
#define EP_RX_DIS (0x0000) /* EndPoint RX DISabled */
|
||||
#define EP_RX_STALL (0x1000) /* EndPoint RX STALLed */
|
||||
#define EP_RX_NAK (0x2000) /* EndPoint RX NAKed */
|
||||
#define EP_RX_VALID (0x3000) /* EndPoint RX VALID */
|
||||
#define EPRX_DATTOG1 (0x1000) /* EndPoint RX Data TOGgle bit1 */
|
||||
#define EPRX_DATTOG2 (0x2000) /* EndPoint RX Data TOGgle bit1 */
|
||||
#define EPRX_DATTOGMASK (EPRX_STS | EPREG_MASK)
|
||||
|
||||
/* USB_SetCtrl */
|
||||
#define _SetCNTR(wRegValue) (*USB_CTRL = (uint16_t)wRegValue)
|
||||
|
||||
/* USB_SetSts */
|
||||
#define _SetISTR(wRegValue) (*USB_STS = (uint16_t)wRegValue)
|
||||
|
||||
/* USB_SetAddr */
|
||||
#define _SetDADDR(wRegValue) (*USB_ADDR = (uint16_t)wRegValue)
|
||||
|
||||
/* USB_SetBuftab */
|
||||
#define _SetBTABLE(wRegValue) (*USB_BUFTAB = (uint16_t)(wRegValue & 0xFFF8))
|
||||
|
||||
/* USB_GetCtrl */
|
||||
#define _GetCNTR() ((uint16_t)*USB_CTRL)
|
||||
|
||||
/* USB_GetSts */
|
||||
#define _GetISTR() ((uint16_t)*USB_STS)
|
||||
|
||||
/* USB_GetFn */
|
||||
#define _GetFNR() ((uint16_t)*USB_FN)
|
||||
|
||||
/* USB_GetAddr */
|
||||
#define _GetDADDR() ((uint16_t)*USB_ADDR)
|
||||
|
||||
/* USB_GetBTABLE */
|
||||
#define _GetBTABLE() ((uint16_t)*USB_BUFTAB)
|
||||
|
||||
/* USB_SetEndPoint */
|
||||
#define _SetENDPOINT(bEpNum, wRegValue) (*(EP0REG + bEpNum) = (uint16_t)wRegValue)
|
||||
|
||||
/* USB_GetEndPoint */
|
||||
#define _GetENDPOINT(bEpNum) ((uint16_t)(*(EP0REG + bEpNum)))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_SetEpType
|
||||
* Description : sets the type in the endpoint register(bits EP_TYPE[1:0])
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* wType
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPType(bEpNum, wType) (_SetENDPOINT(bEpNum, ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType)))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_GetEpType
|
||||
* Description : gets the type in the endpoint register(bits EP_TYPE[1:0])
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : Endpoint Type
|
||||
*******************************************************************************/
|
||||
#define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD)
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : SetEPTxStatus
|
||||
* Description : sets the status for tx transfer (bits STAT_TX[1:0]).
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* wState: new state
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPTxStatus(bEpNum, wState) \
|
||||
{ \
|
||||
register uint16_t _wRegVal; \
|
||||
_wRegVal = _GetENDPOINT(bEpNum) & EPTX_DATTOGMASK; \
|
||||
/* toggle first bit ? */ \
|
||||
if ((EPTX_DATTOG1 & wState) != 0) \
|
||||
_wRegVal ^= EPTX_DATTOG1; \
|
||||
/* toggle second bit ? */ \
|
||||
if ((EPTX_DATTOG2 & wState) != 0) \
|
||||
_wRegVal ^= EPTX_DATTOG2; \
|
||||
_SetENDPOINT(bEpNum, (_wRegVal | EP_CTRS_RX | EP_CTRS_TX)); \
|
||||
} /* _SetEPTxStatus */
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : SetEPRxStatus
|
||||
* Description : sets the status for rx transfer (bits STAT_TX[1:0])
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* wState: new state.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPRxStatus(bEpNum, wState) \
|
||||
{ \
|
||||
register uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = _GetENDPOINT(bEpNum) & EPRX_DATTOGMASK; \
|
||||
/* toggle first bit ? */ \
|
||||
if ((EPRX_DATTOG1 & wState) != 0) \
|
||||
_wRegVal ^= EPRX_DATTOG1; \
|
||||
/* toggle second bit ? */ \
|
||||
if ((EPRX_DATTOG2 & wState) != 0) \
|
||||
_wRegVal ^= EPRX_DATTOG2; \
|
||||
_SetENDPOINT(bEpNum, (_wRegVal | EP_CTRS_RX | EP_CTRS_TX)); \
|
||||
} /* _SetEPRxStatus */
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : SetEPRxTxStatus
|
||||
* Description : sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* wStaterx: new state.
|
||||
* wStatetx: new state.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPRxTxStatus(bEpNum, wStaterx, wStatetx) \
|
||||
{ \
|
||||
register uint32_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = _GetENDPOINT(bEpNum) & (EPRX_DATTOGMASK | EPTX_STS); \
|
||||
/* toggle first bit ? */ \
|
||||
if ((EPRX_DATTOG1 & wStaterx) != 0) \
|
||||
_wRegVal ^= EPRX_DATTOG1; \
|
||||
/* toggle second bit ? */ \
|
||||
if ((EPRX_DATTOG2 & wStaterx) != 0) \
|
||||
_wRegVal ^= EPRX_DATTOG2; \
|
||||
/* toggle first bit ? */ \
|
||||
if ((EPTX_DATTOG1 & wStatetx) != 0) \
|
||||
_wRegVal ^= EPTX_DATTOG1; \
|
||||
/* toggle second bit ? */ \
|
||||
if ((EPTX_DATTOG2 & wStatetx) != 0) \
|
||||
_wRegVal ^= EPTX_DATTOG2; \
|
||||
_SetENDPOINT(bEpNum, _wRegVal | EP_CTRS_RX | EP_CTRS_TX); \
|
||||
} /* _SetEPRxTxStatus */
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_GetEpTxSts / USB_GetEpRxSts
|
||||
* Description : gets the status for tx/rx transfer (bits STAT_TX[1:0]
|
||||
* /STAT_RX[1:0])
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : status .
|
||||
*******************************************************************************/
|
||||
#define _GetEPTxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPTX_STS)
|
||||
|
||||
#define _GetEPRxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPRX_STS)
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_SetEpTxValid / USB_SetEpRxValid
|
||||
* Description : sets directly the VALID tx/rx-status into the enpoint register
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID))
|
||||
|
||||
#define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_GetTxStallSts / USB_GetRxStallSts.
|
||||
* Description : checks stall condition in an endpoint.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : TRUE = endpoint in stall condition.
|
||||
*******************************************************************************/
|
||||
#define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) == EP_TX_STALL)
|
||||
#define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) == EP_RX_STALL)
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_SetEpKind / USB_ClrEpKind.
|
||||
* Description : set & clear EP_KIND bit.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEP_KIND(bEpNum) \
|
||||
(_SetENDPOINT(bEpNum, (EP_CTRS_RX | EP_CTRS_TX | ((_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK))))
|
||||
#define _ClearEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, (EP_CTRS_RX | EP_CTRS_TX | (_GetENDPOINT(bEpNum) & EPKIND_MASK))))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_SetStsOut / USB_ClrStsOut.
|
||||
* Description : Sets/clears directly STATUS_OUT bit in the endpoint register.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _Set_Status_Out(bEpNum) _SetEP_KIND(bEpNum)
|
||||
#define _Clear_Status_Out(bEpNum) _ClearEP_KIND(bEpNum)
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_SetEpDoubleBufer / USB_ClrEpDoubleBufer.
|
||||
* Description : Sets/clears directly EP_KIND bit in the endpoint register.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPDoubleBuff(bEpNum) _SetEP_KIND(bEpNum)
|
||||
#define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum)
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_ClrEpCtrsRx / USB_ClrEpCtrsTx.
|
||||
* Description : Clears bit CTR_RX / CTR_TX in the endpoint register.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _ClearEP_CTR_RX(bEpNum) (_SetENDPOINT(bEpNum, _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK))
|
||||
#define _ClearEP_CTR_TX(bEpNum) (_SetENDPOINT(bEpNum, _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_DattogRx / USB_DattogTx .
|
||||
* Description : Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _ToggleDTOG_RX(bEpNum) \
|
||||
(_SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | EP_DATTOG_RX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
|
||||
#define _ToggleDTOG_TX(bEpNum) \
|
||||
(_SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | EP_DATTOG_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_ClrDattogRx / USB_ClrDattogTx.
|
||||
* Description : Clears DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _ClearDTOG_RX(bEpNum) \
|
||||
if ((_GetENDPOINT(bEpNum) & EP_DATTOG_RX) != 0) \
|
||||
_ToggleDTOG_RX(bEpNum)
|
||||
#define _ClearDTOG_TX(bEpNum) \
|
||||
if ((_GetENDPOINT(bEpNum) & EP_DATTOG_TX) != 0) \
|
||||
_ToggleDTOG_TX(bEpNum)
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_SetEpAddress.
|
||||
* Description : Sets address in an endpoint register.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* bAddr: Address.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPAddress(bEpNum, bAddr) \
|
||||
_SetENDPOINT(bEpNum, EP_CTRS_RX | EP_CTRS_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK) | bAddr)
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_GetEpAddress.
|
||||
* Description : Gets address in an endpoint register.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _GetEPAddress(bEpNum) ((uint8_t)(_GetENDPOINT(bEpNum) & EPADDR_FIELD))
|
||||
|
||||
#define _pEPTxAddr(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8) * 2 + PMAAddr))
|
||||
#define _pEPTxCount(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 2) * 2 + PMAAddr))
|
||||
#define _pEPRxAddr(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 4) * 2 + PMAAddr))
|
||||
#define _pEPRxCount(bEpNum) ((uint32_t*)((_GetBTABLE() + bEpNum * 8 + 6) * 2 + PMAAddr))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_SetEpTxAddr / USB_SetEpRxAddr.
|
||||
* Description : sets address of the tx/rx buffer.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* wAddr: address to be set (must be word aligned).
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPTxAddr(bEpNum, wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1))
|
||||
#define _SetEPRxAddr(bEpNum, wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_GetEpTxAddr / USB_GetEpRxAddr.
|
||||
* Description : Gets address of the tx/rx buffer.
|
||||
* Input : bEpNum: Endpoint Number.
|
||||
* Output : None.
|
||||
* Return : address of the buffer.
|
||||
*******************************************************************************/
|
||||
#define _GetEPTxAddr(bEpNum) ((uint16_t)*_pEPTxAddr(bEpNum))
|
||||
#define _GetEPRxAddr(bEpNum) ((uint16_t)*_pEPRxAddr(bEpNum))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_SetEpCntRxReg.
|
||||
* Description : Sets counter of rx buffer with no. of blocks.
|
||||
* Input : pdwReg: pointer to counter.
|
||||
* wCount: Counter.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _BlocksOf32(dwReg, wCount, wNBlocks) \
|
||||
{ \
|
||||
wNBlocks = wCount >> 5; \
|
||||
if ((wCount & 0x1f) == 0) \
|
||||
wNBlocks--; \
|
||||
*pdwReg = (uint32_t)((wNBlocks << 11) | 0x8000); \
|
||||
} /* _BlocksOf32 */
|
||||
|
||||
#define _BlocksOf2(dwReg, wCount, wNBlocks) \
|
||||
{ \
|
||||
wNBlocks = wCount >> 1; \
|
||||
if ((wCount & 0x1) != 0) \
|
||||
wNBlocks++; \
|
||||
*pdwReg = (uint32_t)(wNBlocks << 10); \
|
||||
} /* _BlocksOf2 */
|
||||
|
||||
#define _SetEPCountRxReg(dwReg, wCount) \
|
||||
{ \
|
||||
uint16_t wNBlocks; \
|
||||
if (wCount > 62) \
|
||||
{ \
|
||||
_BlocksOf32(dwReg, wCount, wNBlocks); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
_BlocksOf2(dwReg, wCount, wNBlocks); \
|
||||
} \
|
||||
} /* _SetEPCountRxReg */
|
||||
|
||||
#define _SetEPRxDblBuf0Count(bEpNum, wCount) \
|
||||
{ \
|
||||
uint32_t* pdwReg = _pEPTxCount(bEpNum); \
|
||||
_SetEPCountRxReg(pdwReg, wCount); \
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_SetEpTxCnt / USB_SetEpRxCnt.
|
||||
* Description : sets counter for the tx/rx buffer.
|
||||
* Input : bEpNum: endpoint number.
|
||||
* wCount: Counter value.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPTxCount(bEpNum, wCount) (*_pEPTxCount(bEpNum) = wCount)
|
||||
#define _SetEPRxCount(bEpNum, wCount) \
|
||||
{ \
|
||||
uint32_t* pdwReg = _pEPRxCount(bEpNum); \
|
||||
_SetEPCountRxReg(pdwReg, wCount); \
|
||||
}
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_GetEpTxCnt / USB_GetEpRxCnt.
|
||||
* Description : gets counter of the tx buffer.
|
||||
* Input : bEpNum: endpoint number.
|
||||
* Output : None.
|
||||
* Return : Counter value.
|
||||
*******************************************************************************/
|
||||
#define _GetEPTxCount(bEpNum) ((uint16_t)(*_pEPTxCount(bEpNum)) & 0x3ff)
|
||||
#define _GetEPRxCount(bEpNum) ((uint16_t)(*_pEPRxCount(bEpNum)) & 0x3ff)
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_SetEpDblBuf0Addr / USB_SetEpDblBuf1Addr.
|
||||
* Description : Sets buffer 0/1 address in a double buffer endpoint.
|
||||
* Input : bEpNum: endpoint number.
|
||||
* : wBuf0Addr: buffer 0 address.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPDblBuf0Addr(bEpNum, wBuf0Addr) \
|
||||
{ \
|
||||
_SetEPTxAddr(bEpNum, wBuf0Addr); \
|
||||
}
|
||||
#define _SetEPDblBuf1Addr(bEpNum, wBuf1Addr) \
|
||||
{ \
|
||||
_SetEPRxAddr(bEpNum, wBuf1Addr); \
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_SetEpDblBuferAddr.
|
||||
* Description : Sets addresses in a double buffer endpoint.
|
||||
* Input : bEpNum: endpoint number.
|
||||
* : wBuf0Addr: buffer 0 address.
|
||||
* : wBuf1Addr = buffer 1 address.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr) \
|
||||
{ \
|
||||
_SetEPDblBuf0Addr(bEpNum, wBuf0Addr); \
|
||||
_SetEPDblBuf1Addr(bEpNum, wBuf1Addr); \
|
||||
} /* _SetEPDblBuffAddr */
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_GetEpDblBuf0Addr / USB_GetEpDblBuf1Addr.
|
||||
* Description : Gets buffer 0/1 address of a double buffer endpoint.
|
||||
* Input : bEpNum: endpoint number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum))
|
||||
#define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum))
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_SetEpDblBuferCnt / USB_SetEpDblBuf0Cnt / USB_SetEpDblBuf1Cnt.
|
||||
* Description : Gets buffer 0/1 address of a double buffer endpoint.
|
||||
* Input : bEpNum: endpoint number.
|
||||
* : bDir: endpoint dir EP_DBUF_OUT = OUT
|
||||
* EP_DBUF_IN = IN
|
||||
* : wCount: Counter value
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _SetEPDblBuf0Count(bEpNum, bDir, wCount) \
|
||||
{ \
|
||||
if (bDir == EP_DBUF_OUT) \
|
||||
/* OUT endpoint */ \
|
||||
{ \
|
||||
_SetEPRxDblBuf0Count(bEpNum, wCount); \
|
||||
} \
|
||||
else if (bDir == EP_DBUF_IN) \
|
||||
/* IN endpoint */ \
|
||||
*_pEPTxCount(bEpNum) = (uint32_t)wCount; \
|
||||
} /* USB_SetEpDblBuf0Cnt*/
|
||||
|
||||
#define _SetEPDblBuf1Count(bEpNum, bDir, wCount) \
|
||||
{ \
|
||||
if (bDir == EP_DBUF_OUT) \
|
||||
/* OUT endpoint */ \
|
||||
{ \
|
||||
_SetEPRxCount(bEpNum, wCount); \
|
||||
} \
|
||||
else if (bDir == EP_DBUF_IN) \
|
||||
/* IN endpoint */ \
|
||||
*_pEPRxCount(bEpNum) = (uint32_t)wCount; \
|
||||
} /* USB_SetEpDblBuf1Cnt */
|
||||
|
||||
#define _SetEPDblBuffCount(bEpNum, bDir, wCount) \
|
||||
{ \
|
||||
_SetEPDblBuf0Count(bEpNum, bDir, wCount); \
|
||||
_SetEPDblBuf1Count(bEpNum, bDir, wCount); \
|
||||
} /* _SetEPDblBuffCount */
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro Name : USB_GetEpDblBuf0Cnt / USB_GetEpDblBuf1Cnt.
|
||||
* Description : Gets buffer 0/1 rx/tx counter for double buffering.
|
||||
* Input : bEpNum: endpoint number.
|
||||
* Output : None.
|
||||
* Return : None.
|
||||
*******************************************************************************/
|
||||
#define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum))
|
||||
#define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum))
|
||||
|
||||
extern __IO uint16_t wIstr; /* USB_STS register last read value */
|
||||
|
||||
void USB_SetCtrl(uint16_t /*wRegValue*/);
|
||||
void USB_SetSts(uint16_t /*wRegValue*/);
|
||||
void USB_SetAddr(uint16_t /*wRegValue*/);
|
||||
void USB_SetBuftab(uint16_t /*wRegValue*/);
|
||||
void USB_SetBuftab(uint16_t /*wRegValue*/);
|
||||
uint16_t USB_GetCtrl(void);
|
||||
uint16_t USB_GetSts(void);
|
||||
uint16_t USB_GetFn(void);
|
||||
uint16_t USB_GetAddr(void);
|
||||
uint16_t USB_GetBTABLE(void);
|
||||
void USB_SetEndPoint(uint8_t /*bEpNum*/, uint16_t /*wRegValue*/);
|
||||
uint16_t USB_GetEndPoint(uint8_t /*bEpNum*/);
|
||||
void USB_SetEpType(uint8_t /*bEpNum*/, uint16_t /*wType*/);
|
||||
uint16_t USB_GetEpType(uint8_t /*bEpNum*/);
|
||||
void SetEPTxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
|
||||
void SetEPRxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
|
||||
void USB_SetDouBleBuferEpStall(uint8_t /*bEpNum*/, uint8_t bDir);
|
||||
uint16_t USB_GetEpTxSts(uint8_t /*bEpNum*/);
|
||||
uint16_t USB_GetEpRxSts(uint8_t /*bEpNum*/);
|
||||
void USB_SetEpTxValid(uint8_t /*bEpNum*/);
|
||||
void USB_SetEpRxValid(uint8_t /*bEpNum*/);
|
||||
uint16_t USB_GetTxStallSts(uint8_t /*bEpNum*/);
|
||||
uint16_t USB_GetRxStallSts(uint8_t /*bEpNum*/);
|
||||
void USB_SetEpKind(uint8_t /*bEpNum*/);
|
||||
void USB_ClrEpKind(uint8_t /*bEpNum*/);
|
||||
void USB_SetStsOut(uint8_t /*bEpNum*/);
|
||||
void USB_ClrStsOut(uint8_t /*bEpNum*/);
|
||||
void USB_SetEpDoubleBufer(uint8_t /*bEpNum*/);
|
||||
void USB_ClrEpDoubleBufer(uint8_t /*bEpNum*/);
|
||||
void USB_ClrEpCtrsRx(uint8_t /*bEpNum*/);
|
||||
void USB_ClrEpCtrsTx(uint8_t /*bEpNum*/);
|
||||
void USB_DattogRx(uint8_t /*bEpNum*/);
|
||||
void USB_DattogTx(uint8_t /*bEpNum*/);
|
||||
void USB_ClrDattogRx(uint8_t /*bEpNum*/);
|
||||
void USB_ClrDattogTx(uint8_t /*bEpNum*/);
|
||||
void USB_SetEpAddress(uint8_t /*bEpNum*/, uint8_t /*bAddr*/);
|
||||
uint8_t USB_GetEpAddress(uint8_t /*bEpNum*/);
|
||||
void USB_SetEpTxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
|
||||
void USB_SetEpRxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
|
||||
uint16_t USB_GetEpTxAddr(uint8_t /*bEpNum*/);
|
||||
uint16_t USB_GetEpRxAddr(uint8_t /*bEpNum*/);
|
||||
void USB_SetEpCntRxReg(uint32_t* /*pdwReg*/, uint16_t /*wCount*/);
|
||||
void USB_SetEpTxCnt(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
|
||||
void USB_SetEpRxCnt(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
|
||||
uint16_t USB_GetEpTxCnt(uint8_t /*bEpNum*/);
|
||||
uint16_t USB_GetEpRxCnt(uint8_t /*bEpNum*/);
|
||||
void USB_SetEpDblBuf0Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/);
|
||||
void USB_SetEpDblBuf1Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf1Addr*/);
|
||||
void USB_SetEpDblBuferAddr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/, uint16_t /*wBuf1Addr*/);
|
||||
uint16_t USB_GetEpDblBuf0Addr(uint8_t /*bEpNum*/);
|
||||
uint16_t USB_GetEpDblBuf1Addr(uint8_t /*bEpNum*/);
|
||||
void USB_SetEpDblBuferCnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
|
||||
void USB_SetEpDblBuf0Cnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
|
||||
void USB_SetEpDblBuf1Cnt(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
|
||||
uint16_t USB_GetEpDblBuf0Cnt(uint8_t /*bEpNum*/);
|
||||
uint16_t USB_GetEpDblBuf1Cnt(uint8_t /*bEpNum*/);
|
||||
EP_DBUF_DIR GetEPDblBufDir(uint8_t /*bEpNum*/);
|
||||
void USB_FreeUserBuf(uint8_t bEpNum /*bEpNum*/, uint8_t bDir);
|
||||
uint16_t USB_ToWord(uint8_t, uint8_t);
|
||||
uint16_t USB_ByteSwap(uint16_t);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __USB_REGS_H__ */
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue