diff --git a/board/ALIENTEK_W601/BSP/Inc/beep.h b/board/ALIENTEK_W601/BSP/Inc/beep.h new file mode 100644 index 00000000..595a9bbb --- /dev/null +++ b/board/ALIENTEK_W601/BSP/Inc/beep.h @@ -0,0 +1,34 @@ +#ifndef __BEEP_H +#define __BEEP_H + +/********************************************************************************* + ___ _ _____ _____ _ _ _____ _____ _ __ + / _ \ | | |_ _|| ___|| \ | ||_ _|| ___|| | / / + / /_\ \| | | | | |__ | \| | | | | |__ | |/ / + | _ || | | | | __| | . ` | | | | __| | \ + | | | || |_____| |_ | |___ | |\ | | | | |___ | |\ \ + \_| |_/\_____/\___/ \____/ \_| \_/ \_/ \____/ \_| \_/ + + * ****************************************************************************** + * 本程序只供学习使用，未经作者许可，不得用于其它任何用途 + * ALIENTEK W601开发板 + * 蜂鸣器驱动代码 + * 正点原子@ALIENTEK + * 技术论坛:www.openedv.com + * 创建日期:2019/7/10 + * 版本：V1.0 + * 版权所有，盗版必究。 + * Copyright(C) 广州市星翼电子科技有限公司 2019-2029 + * All rights reserved + * ****************************************************************************** + * 初始版本 + * ******************************************************************************/ + + +#define BEEP PBout(15) + +void BEEP_Init(void); + +#endif + + diff --git a/board/ALIENTEK_W601/BSP/Inc/dwt.h b/board/ALIENTEK_W601/BSP/Inc/dwt.h new file mode 100644 index 00000000..c5d5c4ef --- /dev/null +++ b/board/ALIENTEK_W601/BSP/Inc/dwt.h @@ -0,0 +1,21 @@ +#ifndef __DWT_H_ +#define __DWT_H_ + +#include "sys.h" + +#define DWT_CR *(volatile uint32_t *)0xE0001000 + +#define DWT_CYCCNT *(volatile uint32_t *)0xE0001004 + +#define DEM_CR *(volatile uint32_t *)0xE000EDFC + +#define DEM_CR_TRCENA (1 << 24) + +#define DWT_CR_CYCCNTENA (1 << 0) + +#define delayms(msec) delayus(msec*1000) + +void dwt_delay_init(uint32_t clk); +void delay_us(uint32_t usec); +void delay_ms(__IO uint32_t nTime); +#endif diff --git a/board/ALIENTEK_W601/BSP/Inc/key.h b/board/ALIENTEK_W601/BSP/Inc/key.h new file mode 100644 index 00000000..84fb2e07 --- /dev/null +++ b/board/ALIENTEK_W601/BSP/Inc/key.h @@ -0,0 +1,43 @@ +#ifndef _KEY_H +#define _KEY_H +#include "sys.h" + +/********************************************************************************* + ___ _ _____ _____ _ _ _____ _____ _ __ + / _ \ | | |_ _|| ___|| \ | ||_ _|| ___|| | / / + / /_\ \| | | | | |__ | \| | | | | |__ | |/ / + | _ || | | | | __| | . ` | | | | __| | \ + | | | || |_____| |_ | |___ | |\ | | | | |___ | |\ \ + \_| |_/\_____/\___/ \____/ \_| \_/ \_/ \____/ \_| \_/ + + * ****************************************************************************** + * 本程序只供学习使用，未经作者许可，不得用于其它任何用途 + * ALIENTEK W601开发板 + * KEY驱动代码 + * 正点原子@ALIENTEK + * 技术论坛:www.openedv.com + * 创建日期:2019/7/10 + * 版本：V1.0 + * 版权所有，盗版必究。 + * Copyright(C) 广州市星翼电子科技有限公司 2019-2029 + * All rights reserved + * ****************************************************************************** + * 初始版本 + * ******************************************************************************/ + +/* + KEY0 - PA7 + KEY1 - PA6 + KEY_UP - PA8 +*/ +#define KEY0 PAin(7) +#define KEY1 PAin(6) +#define KEY_UP PAin(8) + +#define KEY0_PRES 1 +#define KEY1_PRES 2 +#define WKUP_PRES 3 + +void KEY_Init(void); +u8 KEY_Scan(u8 mode); +#endif diff --git a/board/ALIENTEK_W601/BSP/Inc/led.h b/board/ALIENTEK_W601/BSP/Inc/led.h new file mode 100644 index 00000000..2a269fac --- /dev/null +++ b/board/ALIENTEK_W601/BSP/Inc/led.h @@ -0,0 +1,40 @@ +#ifndef _LED_H +#define _LED_H +#include "sys.h" + +/********************************************************************************* + ___ _ _____ _____ _ _ _____ _____ _ __ + / _ \ | | |_ _|| ___|| \ | ||_ _|| ___|| | / / + / /_\ \| | | | | |__ | \| | | | | |__ | |/ / + | _ || | | | | __| | . ` | | | | __| | \ + | | | || |_____| |_ | |___ | |\ | | | | |___ | |\ \ + \_| |_/\_____/\___/ \____/ \_| \_/ \_/ \____/ \_| \_/ + + * ****************************************************************************** + * 本程序只供学习使用，未经作者许可，不得用于其它任何用途 + * ALIENTEK W601开发板 + * LED驱动代码 + * 正点原子@ALIENTEK + * 技术论坛:www.openedv.com + * 创建日期:2018/10/27 + * 版本：V1.0 + * 版权所有，盗版必究。 + * Copyright(C) 广州市星翼电子科技有限公司 2014-2024 + * All rights reserved + * ****************************************************************************** + * 初始版本 + * ******************************************************************************/ + +//RGB接口定义 +#define LED_R PAout(13) +#define LED_G PAout(14) +#define LED_B PAout(15) + + +void LED_Init(void); + +#endif + + + + diff --git a/board/ALIENTEK_W601/BSP/Inc/sys.h b/board/ALIENTEK_W601/BSP/Inc/sys.h new file mode 100644 index 00000000..70cb133e --- /dev/null +++ b/board/ALIENTEK_W601/BSP/Inc/sys.h @@ -0,0 +1,78 @@ +#ifndef __SYS_H +#define __SYS_H + +/********************************************************************************* + ___ _ _____ _____ _ _ _____ _____ _ __ + / _ \ | | |_ _|| ___|| \ | ||_ _|| ___|| | / / + / /_\ \| | | | | |__ | \| | | | | |__ | |/ / + | _ || | | | | __| | . ` | | | | __| | \ + | | | || |_____| |_ | |___ | |\ | | | | |___ | |\ \ + \_| |_/\_____/\___/ \____/ \_| \_/ \_/ \____/ \_| \_/ + + * ****************************************************************************** + * 本程序只供学习使用，未经作者许可，不得用于其它任何用途 + * ALIENTEK W601开发板 + * 系统时钟初始化 + * 包括时钟设置/中断管理等 + * 正点原子@ALIENTEK + * 技术论坛:www.openedv.com + * 创建日期:2019/7/10 + * 版本：V1.0 + * 版权所有，盗版必究。 + * Copyright(C) 广州市星翼电子科技有限公司 2019-2029 + * All rights reserved + * ****************************************************************************** + * 版本修改说明 + * 无 + * ******************************************************************************/ + + +#include "misc.h" +#include "wm_type_def.h" +#include "wm_cpu.h" +#include "wm_ram_config.h" +#include "wm_gpio.h" +#include "wm_regs.h" +#include "wm_gpio_afsel.h" +#include "wm_uart_new.h" +#include "wm_uart.h" +#include "wm_pmu.h" + + + + +//位带操作,实现51类似的GPIO控制功能 +//具体实现思想,参考<>第五章(87页~92页).M4同M3类似,只是寄存器地址变了. +//IO口操作宏定义 +#define BITBAND(addr, bitnum) ((addr & 0xF0000000)+0x2000000+((addr &0xFFFFF)<<5)+(bitnum<<2)) +#define MEM_ADDR(addr) *((volatile unsigned long *)(addr)) +#define BIT_ADDR(addr, bitnum) MEM_ADDR(BITBAND(addr, bitnum)) + + +//IO口操作,只对单一的IO口! +//确保n的值小于32! +#define PAout(n) BIT_ADDR(HR_GPIOA_DATA,n) //输出 +#define PAin(n) BIT_ADDR(HR_GPIOA_DATA,n) //输入 + +#define PBout(n) BIT_ADDR(HR_GPIOB_DATA,n) //输出 +#define PBin(n) BIT_ADDR(HR_GPIOB_DATA,n) //输入 + + +//以下为汇编函数 +void WFI_SET(void); //执行WFI指令 +void INTX_DISABLE(void);//关闭所有中断 +void INTX_ENABLE(void); //开启所有中断 +void MSR_MSP(u32 addr); //设置堆栈地址 + +#endif + + + + + + + + + + + diff --git a/board/ALIENTEK_W601/BSP/Inc/usart.h b/board/ALIENTEK_W601/BSP/Inc/usart.h new file mode 100644 index 00000000..d3d3ecd6 --- /dev/null +++ b/board/ALIENTEK_W601/BSP/Inc/usart.h @@ -0,0 +1,38 @@ +#ifndef __USART_H +#define __USART_H +#include "stdio.h" +#include "sys.h" + +/********************************************************************************* + ___ _ _____ _____ _ _ _____ _____ _ __ + / _ \ | | |_ _|| ___|| \ | ||_ _|| ___|| | / / + / /_\ \| | | | | |__ | \| | | | | |__ | |/ / + | _ || | | | | __| | . ` | | | | __| | \ + | | | || |_____| |_ | |___ | |\ | | | | |___ | |\ \ + \_| |_/\_____/\___/ \____/ \_| \_/ \_/ \____/ \_| \_/ + + * ****************************************************************************** + * 本程序只供学习使用，未经作者许可，不得用于其它任何用途 + * ALIENTEK W601开发板 + * 串口0初始化 + * 正点原子@ALIENTEK + * 技术论坛:www.openedv.com + * 创建日期:2019/7/10 + * 版本：V1.0 + * 版权所有，盗版必究。 + * Copyright(C) 广州市星翼电子科技有限公司 2019-2029 + * All rights reserved + * ****************************************************************************** + * 修改说明 + * ******************************************************************************/ + +#define USART_REC_LEN 200 //定义最大接收字节数 200 +#define EN_USART1_RX 1 //使能（1）/禁止（0）串口1接收 + +extern u8 USART_RX_BUF[USART_REC_LEN]; //接收缓冲,最大USART_REC_LEN个字节.末字节为换行符 +extern u16 USART_RX_STA; //接收状态标记 +//如果想串口中断接收，请不要注释以下宏定义 +void uart_init(u32 bound); +#endif + + diff --git a/board/ALIENTEK_W601/BSP/Src/beep.c b/board/ALIENTEK_W601/BSP/Src/beep.c new file mode 100644 index 00000000..b0b0e2f7 --- /dev/null +++ b/board/ALIENTEK_W601/BSP/Src/beep.c @@ -0,0 +1,56 @@ +#include "sys.h" +#include "beep.h" + +/********************************************************************************* + ___ _ _____ _____ _ _ _____ _____ _ __ + / _ \ | | |_ _|| ___|| \ | ||_ _|| ___|| | / / + / /_\ \| | | | | |__ | \| | | | | |__ | |/ / + | _ || | | | | __| | . ` | | | | __| | \ + | | | || |_____| |_ | |___ | |\ | | | | |___ | |\ \ + \_| |_/\_____/\___/ \____/ \_| \_/ \_/ \____/ \_| \_/ + + * ****************************************************************************** + * 本程序只供学习使用，未经作者许可，不得用于其它任何用途 + * ALIENTEK W601开发板 + * 蜂鸣器驱动代码 + * 正点原子@ALIENTEK + * 技术论坛:www.openedv.com + * 创建日期:2019/7/10 + * 版本：V1.0 + * 版权所有，盗版必究。 + * Copyright(C) 广州市星翼电子科技有限公司 2019-2029 + * All rights reserved + * ****************************************************************************** + * 初始版本 + * ******************************************************************************/ + +/** + * @brief 蜂鸣器 IO初始化函数 + * + * @param void + * + * @return void + */ +void BEEP_Init(void) +{ + /* + BEEP PB15 + */ + + tls_gpio_cfg(WM_IO_PB_15, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_PULLLOW); + + BEEP = 0; +} + + + + + + + + + + + + + diff --git a/board/ALIENTEK_W601/BSP/Src/dwt.c b/board/ALIENTEK_W601/BSP/Src/dwt.c new file mode 100644 index 00000000..9241d3a4 --- /dev/null +++ b/board/ALIENTEK_W601/BSP/Src/dwt.c @@ -0,0 +1,36 @@ +#include "dwt.h" + +static uint32_t cpuclkfeq; + +void dwt_delay_init(uint32_t clk) +{ + cpuclkfeq = clk; + DEM_CR |= DEM_CR_TRCENA; + DWT_CYCCNT = 0u; + DWT_CR |= DWT_CR_CYCCNTENA; +} + +void delay_us(uint32_t usec) + +{ + uint32_t startts, endts, ts; + + startts = DWT_CYCCNT; + + ts = usec * (cpuclkfeq / (1000 * 1000)); + endts = startts + ts; + if(endts > startts) + { + while(DWT_CYCCNT < endts); + } + else + { + while(DWT_CYCCNT > endts); + while(DWT_CYCCNT < endts); + } +} + +void delay_ms(__IO uint32_t nTime) +{ + delay_us(1000 * nTime); +} diff --git a/board/ALIENTEK_W601/BSP/Src/key.c b/board/ALIENTEK_W601/BSP/Src/key.c new file mode 100644 index 00000000..c345981f --- /dev/null +++ b/board/ALIENTEK_W601/BSP/Src/key.c @@ -0,0 +1,77 @@ +#include "key.h" +#include "dwt.h" +/********************************************************************************* + ___ _ _____ _____ _ _ _____ _____ _ __ + / _ \ | | |_ _|| ___|| \ | ||_ _|| ___|| | / / + / /_\ \| | | | | |__ | \| | | | | |__ | |/ / + | _ || | | | | __| | . ` | | | | __| | \ + | | | || |_____| |_ | |___ | |\ | | | | |___ | |\ \ + \_| |_/\_____/\___/ \____/ \_| \_/ \_/ \____/ \_| \_/ + + * ****************************************************************************** + * 本程序只供学习使用，未经作者许可，不得用于其它任何用途 + * ALIENTEK W601开发板 + * KEY驱动代码 + * 正点原子@ALIENTEK + * 技术论坛:www.openedv.com + * 创建日期:2019/7/10 + * 版本：V1.0 + * 版权所有，盗版必究。 + * Copyright(C) 广州市星翼电子科技有限公司 2019-2029 + * All rights reserved + * ****************************************************************************** + * 初始版本 + * ******************************************************************************/ + +/** + * @brief 按键初始化函数 + * + * @param void + * + * @return void + */ +void KEY_Init(void) +{ + /* + KEY0 - PA7 + KEY1 - PA6 + KEY_UP - PA8 高电平有效 + */ + + tls_gpio_cfg(WM_IO_PA_06, WM_GPIO_DIR_INPUT, WM_GPIO_ATTR_FLOATING); + tls_gpio_cfg(WM_IO_PA_07, WM_GPIO_DIR_INPUT, WM_GPIO_ATTR_FLOATING); + tls_gpio_cfg(WM_IO_PA_08, WM_GPIO_DIR_INPUT, WM_GPIO_ATTR_PULLLOW); +} + +/** + * @brief 按键处理函数 + * + * @remark 注意此函数有响应优先级,KEY0>KEY1>KEY2>KEY_UP!! + * + * @param mode 0:不支持连续按,1:支持连续按 + * + * @return u8 返回按键值 +* 0:没有任何按键按下,1:KEY0按下,2:KEY1按下,3:KEY2按下,4:KEY_UP按下 + */ +u8 KEY_Scan(u8 mode) +{ + static u8 key_up = 1; //按键松开标志 + + if(mode == 1)key_up = 1; //支持连按 + + if(key_up && (KEY0 == 0 || KEY1 == 0 || KEY_UP == 1)) + { + delay_ms(10); + key_up = 0; + + if(KEY0 == 0) return KEY0_PRES; + + else if(KEY1 == 0) return KEY1_PRES; + + else if(KEY_UP == 1) return WKUP_PRES; + } + + else if(KEY0 == 1 && KEY1 == 1 && KEY_UP == 0)key_up = 1; + + return 0; //无按键按下 +} diff --git a/board/ALIENTEK_W601/BSP/Src/led.c b/board/ALIENTEK_W601/BSP/Src/led.c new file mode 100644 index 00000000..37c049de --- /dev/null +++ b/board/ALIENTEK_W601/BSP/Src/led.c @@ -0,0 +1,54 @@ +#include "led.h" + +/********************************************************************************* + ___ _ _____ _____ _ _ _____ _____ _ __ + / _ \ | | |_ _|| ___|| \ | ||_ _|| ___|| | / / + / /_\ \| | | | | |__ | \| | | | | |__ | |/ / + | _ || | | | | __| | . ` | | | | __| | \ + | | | || |_____| |_ | |___ | |\ | | | | |___ | |\ \ + \_| |_/\_____/\___/ \____/ \_| \_/ \_/ \____/ \_| \_/ + + * ****************************************************************************** + * 本程序只供学习使用，未经作者许可，不得用于其它任何用途 + * ALIENTEK W601开发板 + * LED驱动代码 + * 正点原子@ALIENTEK + * 技术论坛:www.openedv.com + * 创建日期:2019/7/10 + * 版本：V1.0 + * 版权所有，盗版必究。 + * Copyright(C) 广州市星翼电子科技有限公司 2019-2029 + * All rights reserved + * ****************************************************************************** + * 初始版本 + * ******************************************************************************/ + + +/** + * @brief LED IO初始化函数 + * + * @param void + * + * @return void + */ +void LED_Init(void) +{ + /* + LED-B PA13 + LED-G PA14 + LED-R PA15 + */ + + tls_gpio_cfg(WM_IO_PA_13, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_PULLHIGH); + tls_gpio_cfg(WM_IO_PA_14, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_PULLHIGH); + tls_gpio_cfg(WM_IO_PA_15, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_PULLHIGH); + + LED_R = 1; + LED_G = 1; + LED_B = 1; +} + + + + + diff --git a/board/ALIENTEK_W601/BSP/Src/main.c b/board/ALIENTEK_W601/BSP/Src/main.c new file mode 100644 index 00000000..c9013908 --- /dev/null +++ b/board/ALIENTEK_W601/BSP/Src/main.c @@ -0,0 +1,48 @@ +#include "sys.h" +#include "usart.h" +#include "led.h" +#include "beep.h" +#include "key.h" +#include "dwt.h" +#include "cmsis_os.h" + +#define APPLICATION_TASK_STK_SIZE 1024 +extern void application_entry(void *arg); +osThreadDef(application_entry, osPriorityNormal, 1, APPLICATION_TASK_STK_SIZE); + + +void board_init(void) +{ + dwt_delay_init(80000000); + uart_init(115200); //串口初始化 + LED_Init(); //LED接口初始化 +} + +void OS_CPU_SysTickHandler(void) +{ + if (tos_knl_is_running()) + { + tos_knl_irq_enter(); + tos_tick_handler(); + tos_knl_irq_leave(); + } +} + +__weak void application_entry(void *arg) +{ + while (1) { + printf("This is a demo task,please use your task entry!\r\n"); + tos_task_delay(1000); + } +} + + +int main(void) +{ + board_init(); + printf("Welcome to TencentOS tiny\r\n"); + osKernelInitialize(); // TOS Tiny kernel initialize + osThreadCreate(osThread(application_entry), NULL); // Create TOS Tiny task + osKernelStart(); // Start TOS Tiny +} + diff --git a/board/ALIENTEK_W601/BSP/Src/sys.c b/board/ALIENTEK_W601/BSP/Src/sys.c new file mode 100644 index 00000000..7356a8fb --- /dev/null +++ b/board/ALIENTEK_W601/BSP/Src/sys.c @@ -0,0 +1,122 @@ +#include "sys.h" +#include "tos_config.h" +/********************************************************************************* + ___ _ _____ _____ _ _ _____ _____ _ __ + / _ \ | | |_ _|| ___|| \ | ||_ _|| ___|| | / / + / /_\ \| | | | | |__ | \| | | | | |__ | |/ / + | _ || | | | | __| | . ` | | | | __| | \ + | | | || |_____| |_ | |___ | |\ | | | | |___ | |\ \ + \_| |_/\_____/\___/ \____/ \_| \_/ \_/ \____/ \_| \_/ + + * ****************************************************************************** + * 本程序只供学习使用，未经作者许可，不得用于其它任何用途 + * ALIENTEK W601开发板 + * 系统时钟初始化 + * 包括时钟设置/中断管理等 + * 正点原子@ALIENTEK + * 技术论坛:www.openedv.com + * 创建日期:2019/7/10 + * 版本：V1.0 + * 版权所有，盗版必究。 + * Copyright(C) 广州市星翼电子科技有限公司 2019-2029 + * All rights reserved + * ****************************************************************************** + * 版本修改说明 + * 无 + * ******************************************************************************/ + + +/** + * @brief 系统配置函数 + * + * @remark 该函数在startup.s中调用,W601系统时钟初始化为80MHz + * + * @param void + * + * @return void + */ +void SystemInit(void) +{ + tls_sys_clk sysclk; + /*系统时钟设置为80MHz*/ + tls_sys_clk_set(CPU_CLK_80M); + + /*关闭所有IO的复用功能，只开启SWD复用功能*/ + wm_gpio_af_disable(); + tls_sys_clk_get(&sysclk); + SysTick_Config(sysclk.cpuclk * UNIT_MHZ / TOS_CFG_CPU_TICK_PER_SECOND); + /*中断优先级组配置*/ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); + + /*配置深度睡眠低功耗模式*/ + NVIC_SystemLPConfig(NVIC_LP_SLEEPDEEP, ENABLE); + + /*选择PMU时钟*/ + tls_pmu_clk_select(0); +} + + +/** + * @brief THUMB指令不支持汇编内联、 + * 采用如下方法实现执行汇编指令WFI + * + * @param void + * + * @return __asm + */ +__asm void WFI_SET(void) +{ + WFI; +} +/** + * @brief 关闭所有中断(但是不包括fault和NMI中断) + * + * @param void + * + * @return __asm + */ +__asm void INTX_DISABLE(void) +{ + CPSID I + BX LR +} +/** + * @brief 开启所有中断 + * + * @param void + * + * @return __asm + */ +__asm void INTX_ENABLE(void) +{ + CPSIE I + BX LR +} +/** + * @brief 设置栈顶地址 + * + * @param addr 栈顶地址 + * + * @return __asm + */ +__asm void MSR_MSP(u32 addr) +{ + MSR MSP, r0 //set Main Stack value + BX r14 +} + + + + + + + + + + + + + + + + diff --git a/board/ALIENTEK_W601/BSP/Src/usart.c b/board/ALIENTEK_W601/BSP/Src/usart.c new file mode 100644 index 00000000..414ff592 --- /dev/null +++ b/board/ALIENTEK_W601/BSP/Src/usart.c @@ -0,0 +1,176 @@ +#include "sys.h" +#include "usart.h" + +/********************************************************************************* + ___ _ _____ _____ _ _ _____ _____ _ __ + / _ \ | | |_ _|| ___|| \ | ||_ _|| ___|| | / / + / /_\ \| | | | | |__ | \| | | | | |__ | |/ / + | _ || | | | | __| | . ` | | | | __| | \ + | | | || |_____| |_ | |___ | |\ | | | | |___ | |\ \ + \_| |_/\_____/\___/ \____/ \_| \_/ \_/ \____/ \_| \_/ + + * ****************************************************************************** + * 本程序只供学习使用，未经作者许可，不得用于其它任何用途 + * ALIENTEK W601开发板 + * 串口0初始化 + * 正点原子@ALIENTEK + * 技术论坛:www.openedv.com + * 创建日期:2019/7/10 + * 版本：V1.0 + * 版权所有，盗版必究。 + * Copyright(C) 广州市星翼电子科技有限公司 2019-2029 + * All rights reserved + * ****************************************************************************** + * 修改说明 + * ******************************************************************************/ + + +////////////////////////////////////////////////////////////// +//加入以下代码,支持printf函数,而不需要选择use MicroLIB +#if 1 +#pragma import(__use_no_semihosting) +//标准库需要的支持函数 +struct __FILE +{ + int handle; +}; + +FILE __stdout; +/** + * @brief 定义_sys_exit()以避免使用半主机模式 + * + * @param void + * + * @return void + */ +void _sys_exit(int x) +{ + x = x; +} +/** + * @brief 重定义fputc函数 + * + * @param ch 输出字符量 + * @param f 文件指针 + * + * @return void + */ +int fputc(int ch, FILE *f) +{ + while(tls_reg_read32(HR_UART0_FIFO_STATUS) & 0x3F); //等待发送完毕 + + tls_reg_write32(HR_UART0_TX_WIN, (u8) ch); + return ch; +} +#endif + +#if EN_USART1_RX //如果使能了接收 +//串口1中断服务程序 +//注意,读取USARTx->SR能避免莫名其妙的错误 +u8 USART_RX_BUF[USART_REC_LEN]; //接收缓冲,最大USART_REC_LEN个字节. +//接收状态 +//bit15， 接收完成标志 +//bit14， 接收到0x0d +//bit13~0， 接收到的有效字节数目 +u16 USART_RX_STA = 0; //接收状态标记 + + +/** + * @brief 初始化串口0函数 + * + * @param bound 串口波特率 + * + * @return void + */ +void uart_init(u32 bound) +{ + u32 bd; + u32 apbclk; + tls_sys_clk sysclk; + + /* 1.配置IO */ + wm_uart0_tx_config(WM_IO_PA_04); + wm_uart0_rx_config(WM_IO_PA_05); + + /* 2.波特率设置: + ubdiv = (apbclk / (16 * bound) - 1) + ubdiv_frac = ((apbclk % (bound * 16)) / (bound)) */ + tls_sys_clk_get(&sysclk); + apbclk = sysclk.apbclk * 1000000; + bd = (apbclk / (16 * bound) - 1) | (((apbclk % (bound * 16)) / (bound)) << 16); + tls_reg_write32(HR_UART0_BAUD_RATE_CTRL, bd); + + /* 2.串口参数设置：8位数据位/1位停止位/无奇偶校验位/发送使能/接收使能 */ + tls_reg_write32(HR_UART0_LINE_CTRL, ULCON_WL8 | ULCON_TX_EN | ULCON_RX_EN); + /* 3.硬件流控关闭 */ + tls_reg_write32(HR_UART0_FLOW_CTRL, 0); + /* 3.不使能DMA */ + tls_reg_write32(HR_UART0_DMA_CTRL, 0); + /* 4.FIFO触发设置：1个字节 */ + tls_reg_write32(HR_UART0_FIFO_CTRL, 0); + /* 5.开启RX中断:接收触发中断和接收超时中断*/ + tls_reg_write32(HR_UART0_INT_MASK, 0xFF & (~(UIS_RX_FIFO | UIS_RX_FIFO_TIMEOUT))); + + /* 6.串口接收中断配置 */ + NVIC_ClearPendingIRQ(UART0_IRQn); + + NVIC_InitTypeDef NVIC_InitStruct; + NVIC_InitStruct.NVIC_IRQChannel = UART0_IRQn; + NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 7; + NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStruct.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStruct); +} + +/** + * @brief 串口0中断服务程序 + * + * @param void + * + * @return void + */ +void UART0_IRQHandler(void) +{ + u8 res; + + if(tls_reg_read32(HR_UART0_INT_SRC) & UIS_RX_FIFO) //接收到数据 + { + res = (u8)tls_reg_read32(HR_UART0_RX_WIN); + + if((USART_RX_STA & 0x8000) == 0) //接收未完成 + { + if(USART_RX_STA & 0x4000) //接收到了0x0d + { + if(res != 0x0a)USART_RX_STA = 0; //接收错误,重新开始 + + else USART_RX_STA |= 0x8000; //接收完成了 + } + + else //还没收到0X0D + { + if(res == 0x0d)USART_RX_STA |= 0x4000; + + else + { + USART_RX_BUF[USART_RX_STA & 0X3FFF] = res; + USART_RX_STA++; + + if(USART_RX_STA > (USART_REC_LEN - 1))USART_RX_STA = 0; //接收数据错误,重新开始接收 + } + } + } + + tls_reg_write32(HR_UART0_INT_SRC, UIS_RX_FIFO); //清除状态标志位 + } + + if(tls_reg_read32(HR_UART0_INT_SRC) & UIS_RX_FIFO_TIMEOUT) //接收到数据 + { + tls_reg_write32(HR_UART0_INT_SRC, UIS_RX_FIFO_TIMEOUT); //清除状态标志位 + } +} +#endif + + + + + diff --git a/board/ALIENTEK_W601/KEIL/BIN/secboot.img b/board/ALIENTEK_W601/KEIL/BIN/secboot.img new file mode 100644 index 00000000..c2bbd777 Binary files /dev/null and b/board/ALIENTEK_W601/KEIL/BIN/secboot.img differ diff --git a/board/ALIENTEK_W601/KEIL/BIN/version.txt b/board/ALIENTEK_W601/KEIL/BIN/version.txt new file mode 100644 index 00000000..2b4a2545 --- /dev/null +++ b/board/ALIENTEK_W601/KEIL/BIN/version.txt @@ -0,0 +1 @@ +1.0.06 diff --git a/board/ALIENTEK_W601/KEIL/BIN/version_bk.txt b/board/ALIENTEK_W601/KEIL/BIN/version_bk.txt new file mode 100644 index 00000000..2b4a2545 --- /dev/null +++ b/board/ALIENTEK_W601/KEIL/BIN/version_bk.txt @@ -0,0 +1 @@ +1.0.06 diff --git a/board/ALIENTEK_W601/KEIL/TOOLS/makeimg.exe b/board/ALIENTEK_W601/KEIL/TOOLS/makeimg.exe new file mode 100644 index 00000000..80601572 Binary files /dev/null and b/board/ALIENTEK_W601/KEIL/TOOLS/makeimg.exe differ diff --git a/board/ALIENTEK_W601/KEIL/TOOLS/makeimg_all.exe b/board/ALIENTEK_W601/KEIL/TOOLS/makeimg_all.exe new file mode 100644 index 00000000..aae1aedb Binary files /dev/null and b/board/ALIENTEK_W601/KEIL/TOOLS/makeimg_all.exe differ diff --git a/board/ALIENTEK_W601/KEIL/hello_world/TencentOS_tiny.uvoptx b/board/ALIENTEK_W601/KEIL/hello_world/TencentOS_tiny.uvoptx new file mode 100644 index 00000000..059f328e --- /dev/null +++ b/board/ALIENTEK_W601/KEIL/hello_world/TencentOS_tiny.uvoptx @@ -0,0 +1,686 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + TencentOS_tiny + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + ..\OBJ\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 6 + + + + + + + + + + + STLink\ST-LINKIII-KEIL_SWO.dll + + + + 0 + ST-LINKIII-KEIL_SWO + -U003900513137510B39383538 -O206 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P1 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0W60X_QFlash -FS08000000 -FL0100000 + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC2000 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### uVision Project, (C) Keil Software
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..\..\..\..\platform\vendor_bsp\WinnerMicro\w601\WMLIB\include;..\..\..\..\platform\vendor_bsp\WinnerMicro\w601\WMLIB\include\armcc;..\..\..\..\platform\vendor_bsp\WinnerMicro\w601\WMLIB\include\driver;..\..\..\..\platform\vendor_bsp\WinnerMicro\w601\WMLIB\include\platform;..\..\..\..\platform\vendor_bsp\WinnerMicro\w601\WMLIB\platform\inc;..\..\BSP\Inc;..\..\..\..\arch\arm\arm-v7m\common\include;..\..\..\..\arch\arm\arm-v7m\cortex-m3\armcc;..\..\..\..\kernel\core\include;..\..\..\..\kernel\pm\include;..\..\..\..\osal\cmsis_os;..\..\TOS_CONFIG + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + + + + + + + + + + USER + + + beep.c + 1 + ..\..\BSP\Src\beep.c + + + key.c + 1 + ..\..\BSP\Src\key.c + + + led.c + 1 + ..\..\BSP\Src\led.c + + + main.c + 1 + ..\..\BSP\Src\main.c + + + sys.c + 1 + ..\..\BSP\Src\sys.c + + + usart.c + 1 + ..\..\BSP\Src\usart.c + + + dwt.c + 1 + ..\..\BSP\Src\dwt.c + + + + + WMLIB + + + misc.c + 1 + ..\..\..\..\platform\vendor_bsp\WinnerMicro\w601\WMLIB\platform\boot\armcc\misc.c + + + startup.s + 2 + ..\..\..\..\platform\vendor_bsp\WinnerMicro\w601\WMLIB\platform\boot\armcc\startup.s + + + wm_cpu.c + 1 + ..\..\..\..\platform\vendor_bsp\WinnerMicro\w601\WMLIB\platform\drivers\wm_cpu.c + + + wm_gpio.c + 1 + ..\..\..\..\platform\vendor_bsp\WinnerMicro\w601\WMLIB\platform\drivers\wm_gpio.c + + + wm_gpio_afsel.c + 1 + ..\..\..\..\platform\vendor_bsp\WinnerMicro\w601\WMLIB\platform\drivers\wm_gpio_afsel.c + + + wm_io.c + 1 + ..\..\..\..\platform\vendor_bsp\WinnerMicro\w601\WMLIB\platform\drivers\wm_io.c + + + wm_irq.c + 1 + ..\..\..\..\platform\vendor_bsp\WinnerMicro\w601\WMLIB\platform\drivers\wm_irq.c + + + wm_pmu.c + 1 + ..\..\..\..\platform\vendor_bsp\WinnerMicro\w601\WMLIB\platform\drivers\wm_pmu.c + + + wm_timer.c + 1 + ..\..\..\..\platform\vendor_bsp\WinnerMicro\w601\WMLIB\platform\drivers\wm_timer.c + + + + + tos/arch + + + tos_cpu.c + 1 + ..\..\..\..\arch\arm\arm-v7m\common\tos_cpu.c + + + port_c.c + 1 + ..\..\..\..\arch\arm\arm-v7m\cortex-m3\armcc\port_c.c + + + port_s.S + 2 + ..\..\..\..\arch\arm\arm-v7m\cortex-m3\armcc\port_s.S + + + + + tos/kernel + + + tos_event.c + 1 + ..\..\..\..\kernel\core\tos_event.c + + + tos_fifo.c + 1 + ..\..\..\..\kernel\core\tos_fifo.c + + + tos_global.c + 1 + ..\..\..\..\kernel\core\tos_global.c + + + tos_mmblk.c + 1 + ..\..\..\..\kernel\core\tos_mmblk.c + + + tos_mmheap.c + 1 + ..\..\..\..\kernel\core\tos_mmheap.c + + + tos_msg.c + 1 + ..\..\..\..\kernel\core\tos_msg.c + + + tos_mutex.c + 1 + ..\..\..\..\kernel\core\tos_mutex.c + + + tos_pend.c + 1 + ..\..\..\..\kernel\core\tos_pend.c + + + tos_queue.c + 1 + ..\..\..\..\kernel\core\tos_queue.c + + + tos_robin.c + 1 + ..\..\..\..\kernel\core\tos_robin.c + + + tos_sched.c + 1 + ..\..\..\..\kernel\core\tos_sched.c + + + tos_sem.c + 1 + ..\..\..\..\kernel\core\tos_sem.c + + + tos_sys.c + 1 + ..\..\..\..\kernel\core\tos_sys.c + + + tos_task.c + 1 + ..\..\..\..\kernel\core\tos_task.c + + + tos_tick.c + 1 + ..\..\..\..\kernel\core\tos_tick.c + + + tos_time.c + 1 + ..\..\..\..\kernel\core\tos_time.c + + + tos_timer.c + 1 + ..\..\..\..\kernel\core\tos_timer.c + + + + + tos/cmsis + + + cmsis_os.c + 1 + ..\..\..\..\osal\cmsis_os\cmsis_os.c + + + + + examples + + + hello_world.c + 1 + ..\..\..\..\examples\hello_world\hello_world.c + + + + + + + + + + + + + + diff --git a/board/ALIENTEK_W601/KEIL/hello_world/makeimg.bat b/board/ALIENTEK_W601/KEIL/hello_world/makeimg.bat new file mode 100644 index 00000000..ccfe30b9 --- /dev/null +++ b/board/ALIENTEK_W601/KEIL/hello_world/makeimg.bat @@ -0,0 +1,31 @@ +@rem 参数0: exe +@rem 参数1: 输入bin文件 ,原始文件或者压缩档文件 +@rem 参数2: 输出文件(目标生成文件） +@rem 参数3: 输入文件类型,0是旧参数布局的image文件，3是新参数布局的image文件 +@rem 参数4: 是否压缩文件：0：plain文件，1：压缩类型文件 +@rem 参数5: 版本号文件 +@rem 参数6：升级文件再FLASH里的存放位置（相对位置） +@rem 参数7：升级后的文件启动位置（相对位置） +@rem 参数8：原始bin文件 + +@echo off + +@rem 设置bin文件名字（这个名字由MDK魔术棒下->Output->Name of Executable决定） +set PATH_NAME=TencentOS_tiny +@rem 设置bin文件编译路径 +set PATH_OUT=..\OBJ +@rem 设置TOOLS路径 +set PATH_TOOLS=..\TOOLS +@rem 设置BIN存放路径(给W601升级用的文件路径) +set PATH_BIN=..\BIN + +copy %PATH_OUT%\%PATH_NAME%.bin %PATH_BIN% +cd %PATH_TOOLS% + +copy %PATH_BIN%\version.txt %PATH_BIN%\version_bk.txt + +makeimg.exe "%PATH_BIN%\%PATH_NAME%.bin" "%PATH_BIN%\%PATH_NAME%.img" 0 0 "%PATH_BIN%\version.txt" 90000 10100 +makeimg_all.exe "%PATH_BIN%\secboot.img" "%PATH_BIN%\%PATH_NAME%.img" "%PATH_BIN%\%PATH_NAME%.FLS" +@del "%PATH_BIN%\%PATH_NAME%.img" + + diff --git a/board/ALIENTEK_W601/TOS_CONFIG/tos_config.h b/board/ALIENTEK_W601/TOS_CONFIG/tos_config.h new file mode 100644 index 00000000..1995e174 --- /dev/null +++ b/board/ALIENTEK_W601/TOS_CONFIG/tos_config.h @@ -0,0 +1,47 @@ +#ifndef _TOS_CONFIG_H_ +#define _TOS_CONFIG_H_ + +#include "sys.h" + +#define TOS_CFG_TICKLESS_EN 0u + +#define TOS_CFG_TASK_PRIO_MAX 10u + +#define TOS_CFG_ROUND_ROBIN_EN 1u + +#define TOS_CFG_OBJECT_VERIFY_EN 0u + +#define TOS_CFG_EVENT_EN 1u + +#define TOS_CFG_MMBLK_EN 1u + +#define TOS_CFG_MMHEAP_EN 1u + +#define TOS_CFG_MMHEAP_POOL_SIZE 0x1000 + +#define TOS_CFG_MUTEX_EN 1u + +#define TOS_CFG_QUEUE_EN 1u + +#define TOS_CFG_TIMER_EN 1u + +#define TOS_CFG_SEM_EN 1u + +#if (TOS_CFG_QUEUE_EN > 0u) +#define TOS_CFG_MSG_EN 1u +#else +#define TOS_CFG_MSG_EN 0u +#endif + +#define TOS_CFG_MSG_POOL_SIZE 10u + +#define TOS_CFG_IDLE_TASK_STK_SIZE 80u + +#define TOS_CFG_CPU_TICK_PER_SECOND 1000u + +#define TOS_CFG_CPU_CLOCK (80000000) + +#define TOS_CFG_TIMER_AS_PROC 1u + +#endif + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/arm_common_tables.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/arm_common_tables.h new file mode 100644 index 00000000..9732b43c --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/arm_common_tables.h @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 16. October 2013 +* $Revision: V1.4.2 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const q31_t realCoefAQ31[1024]; +extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoefQ31[6144]; +extern const q15_t twiddleCoefQ15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/arm_const_structs.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/arm_const_structs.h new file mode 100644 index 00000000..2ca2cd9c --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/arm_const_structs.h @@ -0,0 +1,59 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 16. October 2013 +* $Revision: V1.4.2 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + +#endif diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/arm_math.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/arm_math.h new file mode 100644 index 00000000..0ff36d8f --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/arm_math.h @@ -0,0 +1,7355 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 17. January 2014 +* $Revision: V1.4.2 +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * + * The library has been developed and tested with MDK-ARM version 4.60. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvproj + * + * + * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + * Copyright Notice + * + * Copyright (C) 2010-2013 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined (ARM_MATH_CM4) +#include "core_cm4.h" +#elif defined (ARM_MATH_CM3) +#include "core_cm3.h" +#elif defined (ARM_MATH_CM0) +#include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" +#define ARM_MATH_CM0_FAMILY +#else +#include "ARMCM4.h" +#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __ICCARM__ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t __packed +#elif defined __GNUC__ +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __CSMC__ /* Cosmic */ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) + +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) + +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + + static __INLINE uint32_t __CLZ( + q31_t data); + + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (short) x; + s = (short) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((short) x * (short) (y >> 16)) - + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((short) x * (short) (y >> 16)) + + ((short) (x >> 16) * (short) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((short) (x >> 16) * (short) y)) + + ((short) x * (short) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE q31_t __SXTB16( + q31_t x) + { + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in > 0) + { + +// #if __FPU_USED +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + +#if defined ( __CC_ARM ) //Keil +//SMMLAR + #define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR + #define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//Enter low optimization region - place directly above function definition + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR + //SMMLA + #define multAcc_32x32_keep32_R(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + + //SMMLS + #define multSub_32x32_keep32_R(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + +//Enter low optimization region - place directly above function definition + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + //SMMLA + #define multAcc_32x32_keep32_R(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + + //SMMLS + #define multSub_32x32_keep32_R(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL + #define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + + #define LOW_OPTIMIZATION_EXIT + + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) // Cosmic + +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + + +/** + * + * End of file. + */ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cm0.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cm0.h new file mode 100644 index 00000000..f1a47a9d --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cm0.h @@ -0,0 +1,702 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cm0plus.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cm0plus.h new file mode 100644 index 00000000..53929718 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cm0plus.h @@ -0,0 +1,813 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cm3.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cm3.h new file mode 100644 index 00000000..938b2404 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cm3.h @@ -0,0 +1,1638 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cm4.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cm4.h new file mode 100644 index 00000000..d8284144 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cm4.h @@ -0,0 +1,1790 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cm4_simd.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cm4_simd.h new file mode 100644 index 00000000..f9bceff1 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cm4_simd.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* not yet supported */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_SIMD_H */ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cmFunc.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cmFunc.h new file mode 100644 index 00000000..2c2af69c --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cmFunc.h @@ -0,0 +1,637 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cmInstr.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cmInstr.h new file mode 100644 index 00000000..d2ec262f --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_cmInstr.h @@ -0,0 +1,687 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_sc000.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_sc000.h new file mode 100644 index 00000000..9e11dfe8 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_sc000.h @@ -0,0 +1,833 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000 + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1]; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154]; + __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/* SCB Security Features Register Definitions */ +#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ +#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ + +#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ +#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2]; + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_sc300.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_sc300.h new file mode 100644 index 00000000..ea855b00 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/armcc/core_sc300.h @@ -0,0 +1,1618 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000 + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/VS10XX.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/VS10XX.h new file mode 100644 index 00000000..ed15dea4 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/VS10XX.h @@ -0,0 +1,342 @@ +/** + * @file VS10XX.h + * + * @brief VS10XX driver + * + * @author dave + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ +#ifndef __VS10XX_H__ +#define __VS10XX_H__ +//#include "sys.h" +#include "wm_type_def.h" + +/** VS10XX ID list*/ +#define VS1001 0 +#define VS1011 1 +#define VS1002 2 +#define VS1003 3 +#define VS1053 4 +#define VS1033 5 +#define VS1103 7 +extern u8 VS10XX_ID; /** VS10XX id */ +/**command */ +#define VS_WRITE_COMMAND 0x02 /** write command */ +#define VS_READ_COMMAND 0x03 /** read command */ + +/** VS10XX register definition */ +#define SPI_MODE 0x00 /** mode control */ +#define SPI_STATUS 0x01 /** VS10XX status register */ +#define SPI_BASS 0x02 /** bass control */ +#define SPI_CLOCKF 0x03 /** Clock frequency multiplier register */ +#define SPI_DECODE_TIME 0x04 /** Decoding time length */ +#define SPI_AUDATA 0x05 /** Audio data */ +#define SPI_WRAM 0x06 /** RAM write/read */ +#define SPI_WRAMADDR 0x07 /** RAM write/read start addr */ +#define SPI_HDAT0 0x08 /** The data stream header 0 */ +#define SPI_HDAT1 0x09 /** The data stream header 1 */ + +#define SPI_AIADDR 0x0a /** application start addr */ +#define SPI_VOL 0x0b /** volumn control */ +#define SPI_AICTRL0 0x0c /** Application control register 0 */ +#define SPI_AICTRL1 0x0d /** Application control register 1 */ +#define SPI_AICTRL2 0x0e /** Application control register 2 */ +#define SPI_AICTRL3 0x0f /** Application control register 3 */ +//SPI_MODE鐨勫悇浣嶅姛鑳,涓嬭〃鏍规嵁VS1053鐨勬墜鍐屾爣娉 +#define SM_DIFF 0x01 /**宸垎 */ +#define SM_LAYER12 0x02 /**鍏佽MPEG 1,2瑙ｇ爜 FOR vs1053 */ +#define SM_RESET 0x04 /**杞欢澶嶄綅 */ +#define SM_CANCEL 0x08 /**鍙栨秷褰撳墠瑙ｇ爜 */ +#define SM_EARSPEAKER_LO 0x10 /**EarSpeaker浣庤瀹 */ +#define SM_TESTS 0x20 /**鍏佽SDI娴嬭瘯 */ +#define SM_STREAM 0x40 /**娴佹ā寮 */ +#define SM_EARSPEAKER_HI 0x80 /**EarSpeaker楂樿瀹 */ +#define SM_DACT 0x100 /**DCLK鐨勬湁鏁堣竟娌 */ +#define SM_SDIORD 0x200 /**SDI浣嶉『搴 */ +#define SM_SDISHARE 0x400 /**鍏变韩SPI鐗囬 */ +#define SM_SDINEW 0x800 /**VS1002 鏈湴SPI妯″紡 */ +#define SM_ADPCM 0x1000/**ADPCM褰曢煶婵娲 */ +#define SM_LINE1 0x4000/**鍜/绾胯矾1 閫夋嫨 */ +#define SM_CLK_RANGE 0x8000/**杈撳叆鏃堕挓鑼冨洿 */ + +//VS10xx涓庡閮ㄦ帴鍙ｅ畾涔(鏈寘鍚玀ISO,MOSI,SCK) +//#define VS_DQ PAin(12) //DREQ +//#define VS_RST PAout(11) //RST +//#define VS_XCS PAout(8) //XCS +//#define VS_XDCS PAout(4) //XDCS + +//#define VS_DQ 3//13 +//#define VS_RST 11 +//#define VS_XCS 12 +//#define VS_XDCS 2//18 + +#define VS_DQ WM_GPIO_A_PIN_12 +#define VS_RST WM_GPIO_A_PIN_13 +#define VS_XCS WM_GPIO_A_PIN_11 +#define VS_XDCS WM_GPIO_A_PIN_9 + +#define VS_SPI_CLK_LOW 250000 +#define VS_SPI_CLK_HIGH 5000000 +#define VS_REC_PKG_SIZE 512 + +/** + * @brief pull cs low + * + * @param[in] None + * + * @return None + * + * @note None + */ +void codec_data_cs_low(void); + +/** + * @brief pull cs high + * + * @param[in] None + * + * @return None + * + * @note None + */ +void codec_data_cs_high(void); + +/** + * @brief read register + * + * @param[in] address + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +u16 VS_RD_Reg(u8 address); + +/** + * @brief write command + * + * @param[in] address + * @param[in] data + * + * @return None + * + * @note None + */ +void VS_WR_Cmd(u8 address,u16 data); + +/** + * @brief write data + * + * @param[in] data + * + * @return None + * + * @note None + */ +void VS_WR_Data(u8 data); + +/** + * @brief read ram + * + * @param[in] addr + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +u16 VS_RD_Wram(u16 addr); + +/** + * @brief initial VS10XX + * + * @param[in] None + * + * @return None + * + * @note None + */ +void VS_Init(void); + +/** + * @brief hardware reset + * + * @param[in] None + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +u8 VS_HD_Reset(void); + +/** + * @brief software reset + * + * @param[in] None + * + * @return None + * + * @note None + */ +void VS_Soft_Reset(void); + +/** + * @brief ram test + * + * @param[in] None + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +u16 VS_Ram_Test(void); + +/** + * @brief sine test + * + * @param[in] None + * + * @return None + * + * @note None + */ +void VS_Sine_Test(void); + +/** + * @brief get decode time + * + * @param[in] None + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +u16 VS_Get_DecodeTime(void); + +/** + * @brief get bitrate + * + * @param[in] None + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +u16 VS_Get_HeadInfo(void); + +/** + * @brief set decode time + * + * @param[in] None + * + * @return None + * + * @note None + */ +void VS_Rst_DecodeTime(void); + +/** + * @brief set VS10XX + * + * @param[in] None + * + * @return None + * + * @note None + */ +void set10XX(void); + +/** + * @brief load FLAC decode code + * + * @param[in] *patch + * @param[in] len + * + * @return None + * + * @note None + */ +void VS_Load_Patch(u16 *patch,u16 len); + +/** + * @brief set volumn + * + * @param[in] vol + * + * @return None + * + * @note None + */ +void vs_set_vol(int vol); + +/** + * @brief mute + * + * @param[in] None + * + * @return None + * + * @note None + */ +void vs_mute(void); + +/** + * @brief set record mode + * + * @param[in] agc + * + * @return None + * + * @note None + */ +void VS_Rec_Mode(u16 agc); + +/** + * @brief get record data + * + * @param[in] recbuf + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +int VS_Rec_GetData(char* recbuf); +#endif + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_7816.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_7816.h new file mode 100644 index 00000000..9149f4b9 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_7816.h @@ -0,0 +1,242 @@ +/**************************************************************************//** + * @file wm_7816.h + * @author + * @version + * @date + * @brief + * @copyright (c) 2014 Winner Microelectronics Co., Ltd. All rights reserved. + *****************************************************************************/ +#ifndef WM_7816_H_ +#define WM_7816_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "wm_regs.h" +#include "wm_type_def.h" +#include "wm_io.h" + +#define WM_SC_RST_PIN WM_IO_PB_23 //(23) +#define WM_SC_PWR_PIN WM_IO_PB_29 //(29) + +#define WM_SC_DEFAULT_FD (372) + +typedef struct sc_io_map_ { + enum tls_io_name clk_pin_num; + uint32_t clk_opt; + enum tls_io_name io_pin_num; + uint32_t io_opt; + uint8_t initialed; +} sc_io_map; + +extern sc_io_map sc_io; + +/** + * @brief + * This function is used to config the pin in gpio or 7816 mode for the 7816 power on timing + * + * @param[in] mode : 1--gpio mode ; 0--7816 mode + * + * @retval + */ +void wm_sc_io_clk_config(uint8_t mode); + +/** + * @brief + * close af to use as gpio + * @retval + */ +void wm_sc_powerInit(void); + +/** + * @brief + * power on the 7816 device if power is controled by GPIO + * @retval + */ +void wm_sc_poweron(void); + +/** + * @brief + * power off the 7816 device if power is controled by GPIO + * @retval + */ +void wm_sc_poweroff(void); + +/** + * @brief + * driver the reset gpio in low level + * @retval + */ +void wm_sc_rst_low(void); + +/** + * @brief + * driver the reset gpio in high level + * @retval + */ +void wm_sc_rst_high(void); + +/** + * @brief + * hotrest the 7816 device obey the 7816-3 timing + * @retval + */ +void wm_sc_hotreset(void); + +/** + * @brief + * colreset the 7816 device obey the 7816-3 timing + * @retval + */ +void wm_sc_colreset(void); + +/** + * @brief + * deactive the 7816 device obey the 7816-3 timing + * @retval + */ +void wm_sc_deactive(void); + +/** + * @brief + * This function is used to config the block guard time param in 7816 mode + * @param[in] bgt : the value of blcok guard time will be set + * @retval + */ +void wm_sc_set_bgt(uint8_t bgt); + +/** + * @brief + * This function is used to config the tx retry count when detect err signal + * @param[in] count : the value of retry time will be set 7 for max + * @retval + */ +void wm_sc_tx_retry_times(uint8_t count); + +/** + * @brief + * This function is used to config the rx retry count when detect parity error + * @param[in] count : the value of retry time will be set 7 for max + * @retval + */ +void wm_sc_rx_retry_times(uint8_t count); + +/** + * @brief + * This function is used to config the etu param + * @param[in] etu : the value of etu will be set + * @retval + */ +void wm_sc_set_etu(uint16_t etu); + +/** + * @brief + * This function config the module clock freq + * @param[in] freq : the value of clock freq + * @retval + */ +void wm_sc_set_frequency(uint32_t freq); + +/** + * @brief + * config recv or not when parity error + * @param[in] bl : 1--- recv + * 0--- don't recv + * @retval + */ +static inline void wm_sc_parity_recv(bool bl) +{ + tls_bitband_write(HR_UART2_LINE_CTRL, 9, bl); +} + +/** + * @brief + * select the model in 7816 or uart function + * @param[in] bl : 1---7816 mode + * 0---uart mode + * @retval + */ +static inline void wm_sc_7816_mode(bool bl) +{ + tls_bitband_write(HR_UART2_LINE_CTRL, 24, bl); +} + +/** + * @brief + * This function is used to config the guard time param + * @param[in] bwt : the value of the guard time will be set + * @retval + */ +static inline void wm_sc_set_guardtime(uint8_t gt) +{ + tls_reg_write32(HR_UART2_GUARD_TIME, gt); +} + +/** + * @brief + * This function is used to config the CWT or BWT param + * @param[in] bwt : the value of CWT or BWT will be set + * @retval + */ +static inline void wm_sc_set_bcwt(uint32_t bwt) +{ + bwt = (bwt > 0xFFFFFF) ? 0xFFFFFF : bwt; + tls_reg_write32(HR_UART2_WAIT_TIME, bwt); +} + +/** + * @brief + * module errsignal int enable or disable + * @param[in] bl : 1---enable + * 0---disable + * @retval + */ +static inline void wm_sc_tx_errsignal_mask(bool bl) +{ + tls_bitband_write(HR_UART2_INT_MASK, 9, bl); +} + +/** + * @brief + * config the module protol + * @param[in] bl : 1--- T1 protocol + * 0--- T0 protocol + * @retval + */ +static inline void wm_sc_set_protocol(bool bl) +{ + tls_bitband_write(HR_UART2_LINE_CTRL, 8, bl); +} + +/** + * @brief + * get the module protol + * @retval + * 1--- T1 protocol + * 0--- T0 protocol + */ +static inline uint8_t wm_sc_get_protocol() +{ + return tls_bitband_read(HR_UART2_LINE_CTRL, 8); +} + +/** + * @brief + * smart card clock output enable or disable + * @param[in] bl : 0---enable; + * 1---disable; + * @retval + */ +static inline void wm_sc_clk_enable(bool bl) +{ + tls_bitband_write(HR_UART2_LINE_CTRL, 10, bl); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_adc.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_adc.h new file mode 100644 index 00000000..9338c18a --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_adc.h @@ -0,0 +1,297 @@ +/** + * @file wm_adc.h + * + * @brief ADC Driver Module + * + * @author + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ + + +#ifndef WM_ADC_H +#define WM_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "wm_type_def.h" + +/** ADC MACRO */ +//姣忔鍚姩dma涔嬪悗锛岄渶瑕佷竴娈电ǔ瀹氭椂闂达紝鎵浠ラ噰闆嗗埌鐨勬暟鎹墠闈㈢殑12涓猙yte涓嶇ǔ瀹氾紝瑕佽垗鍘 +#define ADC_DEST_BUFFER_DMA (u32)0x20028000 +#define ADC_DEST_BUFFER_SIZE 65532 +#define SAMPLE_NUM_PER_CHANNEL 20 + + + +#define CONFIG_ADC_CAL_OFFSET_TEMP12 (1<<23) +#define CONFIG_ADC_G_CTRL12 (1<<22) +#define CONFIG_ADC_CMP_POL (1<<21) +#define CONFIG_ADC_REF_SEL (1<<20) +#define CONFIG_ADC_BUF_BYPASS (1<<19) +#define CONFIG_ADC_DMA_MASK (0xFF<<11) +#define CONFIG_ADC_EN_CAL (1<<10) +#define CONFIG_ADC_INT_CMP (1<<9) +#define CONFIG_ADC_INT (1<<8) +#define CONFIG_ADC_CMP_INT_MASK (1<<7) +#define CONFIG_ADC_INT_MASK (1<<6) +#define CONFIG_ADC_TEMP_ON (1<<5) +#define CONFIG_ADC_START (1<<4) +#define CONFIG_ADC_CHL_MASK (0xF) + +#define CONFIG_ADC_CHL_OFFSET (0x0E) +#define CONFIG_ADC_CHL_VOLT (0x0D) +#define CONFIG_ADC_CHL_TEMP (0x0C) + + + + +#define CONFIG_ADC_INPUT_CMP_VAL(n) ((n&0x3FFF)<<14) +#define CONFIG_ADC_VCM(n) (((u32)n&0x3F)<<26) +#define CONFIG_ADC_G_TEMP12(n) ((n&0x03)<<24) + + + +#define ADC_INT_TYPE_ADC 0 +#define ADC_INT_TYPE_DMA 1 +#define ADC_INT_TYPE_ADC_COMP 2 + +#define ADC_REFERENCE_EXTERNAL 0 //澶栭儴鍙傝 +#define ADC_REFERENCE_INTERNAL 1 //鍐呴儴鍙傝 + +typedef struct adc_st{ + u8 dmachannel; + void (*adc_cb)(u16 *buf, u16 len); + void (*adc_bigger_cb)(u16 *buf, u16 len); + void (*adc_dma_cb)(u16 *buf,u16 len); + u16 valuelen; /*dma 閲囨牱鏁版嵁闀垮害*/ + u16 offset; +}ST_ADC; + +/** + * @defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** + * @addtogroup Driver_APIs + * @{ + */ + +/** + * @defgroup ADC_Driver_APIs ADC Driver APIs + * @brief ADC driver APIs + */ + +/** + * @addtogroup ADC_Driver_APIs + * @{ + */ + +/** + * @brief This function is used to init ADC + * + * @param[in] ifusedma if use dma + * @param[in] dmachannel dma channel + * + * @return None + * + * @note If the requested dma channel is already used by other task, system will auto use other dma channel. + */ +void tls_adc_init(u8 ifusedma,u8 dmachannel); + + +/** + * @brief This function is used to register interrupt callback function + * + * @param[in] inttype interrupt type + * ADC_INT_TYPE_ADC adc interrupt,user get adc result from the callback function. + * ADC_INT_TYPE_DMA dma interrupt,dma transfer the adc result to the user's buffer. + * @param[in] callback interrupt callback function + * + * @return None + * + * @note None + */ +void tls_adc_irq_register(int inttype, void (*callback)(u16 *buf, u16 len)); + +/** + * @brief This function is used to clear the interrupt source + * + * @param[in] inttype interrupt type + * ADC_INT_TYPE_ADC adc interrupt,user get adc result from the callback function. + * ADC_INT_TYPE_DMA dma interrupt,dma transfer the adc result to the user's buffer. + * ADC_INT_TYPE_ADC_COMP adc compare with setting data + * + * @return None + * + * @note None + */ +void tls_adc_clear_irq(int inttype); + +/** + * @brief This function is used to start adc,use dma for transfer data + * + * @param[in] channel adc channel,from 0 to 3 is single input;4 and 5 is differential input + * + * @param[in] length byte data length,is an integer multiple of half word,need <= 0x500 + * + * @return None + * + * @note None + */ +void tls_adc_start_with_dma(int Channel, int Length); + +/** + * @brief This function is used to start adc,use cpu + * + * @param[in] channel adc channel,from 0 to 3 is single input;4 and 5 is differential input + * + * @return None + * + * @note None + */ +void tls_adc_start_with_cpu(int Channel); + +/** + * @brief This function is used to enable input buffer calibration + * + * @param[in] None + * + * @return None + * + * @note None + */ +void tls_adc_enable_calibration_buffer_offset(void); + +/** + * @brief This function is used to sample voltage using cpu + * + * @param[in] None + * + * @return None + * + * @note None + */ +void tls_adc_voltage_start_with_cpu(void); + +/** + * @brief This function is used to sample temperature using cpu + * + * @param[in] calenflag 1:enable calibration , 0: disable calibration + * + * @return None + * + * @note None + */ +void tls_adc_temp_offset_with_cpu(u8 calenflag); + +/** + * @brief This function is used to read adc result + * + * @param[in] None + * + * @return None + * + * @note None + */ +u16 tls_read_adc_result(void); + +/** + * @brief This function is used to stop the adc + * + * @param[in] ifusedma 1:use dma, 0:not use dma + * + * @return None + * + * @note None + */ +void tls_adc_stop(int ifusedma); + +/** + * @brief This function is used to config adc compare register + * + * @param[in] cmp_data compare data + * + * @param[in] cmp_pol compare polarity + * + * @return None + * + * @note None + */ +void tls_adc_config_cmp_reg(int cmp_data, int cmp_pol); + +/** + * @brief This function is used to set adc reference source + * + * @param[in] ref + * ADC_REFERENCE_EXTERNAL + * ADC_REFERENCE_INTERNAL + * + * @return None + * + * @note None + */ +void tls_adc_reference_sel(int ref); + +/** + * @brief This function is used to set clock division + * + * @param[in] div + * + * @return None + * + * @note None + */ +void tls_adc_set_clk(int div); + +void signedToUnsignedData(u16 *adcValue, u16 *offset); + +/** + * @brief This function is used to set buffer bypass + * + * @param[in] isset 1: buffer bypass, 0: buffer work + * + * @return None + * + * @note None + */ +void tls_adc_buffer_bypass_set(u8 isset); + +/** + * @brief This function is used to start compare + * + * @param[in] Channel sample channel + * + * @param[in] cmp_data compare data + * + * @param[in] cmp_pol compare polarity + * + * @return None + * + * @note None + */ + void tls_adc_cmp_start(int Channel, int cmp_data, int cmp_pol); + +u16 adc_get_offset(void); +u32 adc_get_interTemp(void); +u16 adc_get_inputVolt(u8 channel); +u16 adc_get_interVolt(void); +u32 adc_temp(void); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif +#endif /* end of WM_ADC_H */ + +/*** (C) COPYRIGHT 2014 Winner Microelectronics Co., Ltd. ***/ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_cpu.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_cpu.h new file mode 100644 index 00000000..f86e70da --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_cpu.h @@ -0,0 +1,94 @@ +/** + * @file wm_cpu.h + * + * @brief cpu driver module + * + * @author dave + * + * @copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#ifndef WM_CPU_H +#define WM_CPU_H +#ifdef __cplusplus +extern "C" { +#endif + +/** cpu clock: 80Mhz */ +#define CPU_CLK_80M 0 +/** cpu clock: 40Mhz */ +#define CPU_CLK_40M 1 +#define CPU_CLK_16M 2 + +#define W600_PLL_CLK_MHZ 160 + + + +#define UNIT_MHZ (1000000) + + +typedef struct{ + u32 apbclk; + u32 cpuclk; + u32 wlanclk; +}tls_sys_clk; + +/** + * @defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** + * @addtogroup Driver_APIs + * @{ + */ + +/** + * @defgroup CPU_CLOCK_Driver_APIs CPU_CLOCK Driver APIs + * @brief CPU_CLOCK driver APIs + */ + +/** + * @addtogroup CPU_CLOCK_Driver_APIs + * @{ + */ + +/** + * @brief This function is used to set cpu clock + * + * @param[in] clk select cpu clock + * clk == CPU_CLK_80M 80M + * clk == CPU_CLK_40M 40M + * + * @return None + * + * @note None + */ +void tls_sys_clk_set(u32 clk); + + +/** + * @brief This function is used to get cpu clock + * + * @param[out] *sysclk point to the addr for system clk output + * + * @return None + * + * @note None + */ +void tls_sys_clk_get(tls_sys_clk *sysclk); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif +#endif /* end of WM_CPU_H */ + +/*** (C) COPYRIGHT 2014 Winner Microelectronics Co., Ltd. ***/ + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_dma.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_dma.h new file mode 100644 index 00000000..659acf14 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_dma.h @@ -0,0 +1,245 @@ +/** + * @file wm_dma.h + * + * @brief DMA Driver Module + * + * @author dave + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#ifndef __WM_DMA_H_ +#define __WM_DMA_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define TLS_DMA_SEL_UART_RX 0 +#define TLS_DMA_SEL_UART_TX 1 +#define TLS_DMA_SEL_PWM_CAP0 2 +#define TLS_DMA_SEL_PWM_CAP1 3 +#define TLS_DMA_SEL_LSSPI_RX 4 +#define TLS_DMA_SEL_LSSPI_TX 5 +#define TLS_DMA_SEL_SDADC_CH0 6 +#define TLS_DMA_SEL_SDADC_CH1 7 +#define TLS_DMA_SEL_SDADC_CH2 8 +#define TLS_DMA_SEL_SDADC_CH3 9 +#define TLS_DMA_SEL_SDADC_CH4 10 +#define TLS_DMA_SEL_SDADC_CH5 11 +#define TLS_DMA_SEL_SDADC_CH6 12 +#define TLS_DMA_SEL_SDADC_CH7 13 +#define TLS_DMA_SEL_I2S_RX 14 +#define TLS_DMA_SEL_I2S_TX 15 + + +#define TLS_DMA_FLAGS_HARD_MODE (1 << 0) +#define TLS_DMA_FLAGS_CHAIN_MODE (1 << 1) +#define TLS_DMA_FLAGS_CHANNEL_SEL(n) ((n) << 2) +#define TLS_DMA_FLAGS_CHAIN_LINK_EN (1 << 6) +#define TLS_DMA_FLAGS_CHANNEL_VALID (1 << 7) + + +#define TLS_DMA_DESC_VALID (1U << 31) +#define TLS_DMA_DESC_CTRL_SRC_ADD_INC (1 << 0) +#define TLS_DMA_DESC_CTRL_DEST_ADD_INC (1 << 2) +#define TLS_DMA_DESC_CTRL_DATA_SIZE_BYTE (0 << 4) +#define TLS_DMA_DESC_CTRL_DATA_SIZE_SHORT (1 << 4) +#define TLS_DMA_DESC_CTRL_DATA_SIZE_WORD (2 << 4) +#define TLS_DMA_DESC_CTRL_BURST_SIZE1 (0 << 6) +#define TLS_DMA_DESC_CTRL_BURST_SIZE4 (1 << 6) +#define TLS_DMA_DESC_CTRL_TOTAL_BYTES(n) ((n) << 7) + + +/* dma interrupt flags */ +#define TLS_DMA_IRQ_BURST_DONE (1 << 0) +#define TLS_DMA_IRQ_TRANSFER_DONE (1 << 1) +#define TLS_DMA_IRQ_BOTH_DONE (TLS_DMA_IRQ_BURST_DONE | TLS_DMA_IRQ_TRANSFER_DONE) + +struct tls_dma_descriptor { + unsigned int valid; + unsigned int dma_ctrl; + unsigned int src_addr; + unsigned int dest_addr; + struct tls_dma_descriptor *next; /**< next dms descriptor */ +}; + +/** + * @defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** + * @addtogroup Driver_APIs + * @{ + */ + +/** + * @defgroup DMA_Driver_APIs DMA Driver APIs + * @brief DMA driver APIs + */ + +/** + * @addtogroup DMA_Driver_APIs + * @{ + */ + +/** + * @brief This function is used to clear dma interrupt flag. + * + * @param[in] ch Channel no.[0~7] + * @param[in] flags Flags setted to TLS_DMA_IRQ_BURST_DONE, TLS_DMA_IRQ_TRANSFER_DONE, TLS_DMA_IRQ_BOTH_DONE. + * + * @return None + * + * @note None + */ +void tls_dma_irq_clr(unsigned char ch, unsigned char flags); + + +/** + * @brief This function is used to register dma interrupt callback function. + * + * @param[in] ch Channel no.[0~7] + * @param[in] callback is the dma interrupt call back function. + * @param[in] arg the param of the callback function. + * @param[in] flags Flags setted to TLS_DMA_IRQ_BURST_DONE, TLS_DMA_IRQ_TRANSFER_DONE, TLS_DMA_IRQ_BOTH_DONE. + * + * @return None + * + * @note None + */ +void tls_dma_irq_register(unsigned char ch, void (*callback)(void *p), void *arg, unsigned char flags); + + +/** + * @brief This function is used to register dma interrupt + * + * @param[in] ch DMA channel no.[0~7] + * + * @return None + * + * @note None + */ +int tls_dma_wait_complt(unsigned char ch); + + +/** + * @brief This function is used to Start the DMA controller by Wrap + * + * @param[in] autoReload Does restart when current transfer complete? + * @param[in] ch Channel no.[0~7] + * @param[in] pDmaDesc Pointer to DMA channel descriptor structure. + * + * @retval Always STATUS_SUCCESS. + * + * @note + * DMA Descriptor: + * +--------------------------------------------------------------+ + * |Vld[31] | RSV | + * +--------------------------------------------------------------+ + * | RSV | Dma_Ctrl[16:0] | + * +--------------------------------------------------------------+ + * | Src_Addr[31:0] | + * +--------------------------------------------------------------+ + * | Dest_Addr[31:0] | + * +--------------------------------------------------------------+ + * | Next_Desc_Add[31:0] | + * +--------------------------------------------------------------+ + */ +unsigned char tls_dma_start_by_wrap(unsigned char ch, struct tls_dma_descriptor *dma_desc, + unsigned char auto_reload, unsigned short src_zize, + unsigned short dest_zize); + + +/** + * @brief This function is used to Wait until DMA operation completes + * + * @param[in] autoReload Does restart when current transfer complete? + * @param[in] ch Channel no.[0~7] + * @param[in] pDmaDesc Pointer to DMA channel descriptor structure. + * + * @retval Always STATUS_SUCCESS. + * + * @note + * DMA Descriptor: + * +--------------------------------------------------------------+ + * |Vld[31] | RSV | + * +--------------------------------------------------------------+ + * | RSV | Dma_Ctrl[16:0] | + * +--------------------------------------------------------------+ + * | Src_Addr[31:0] | + * +--------------------------------------------------------------+ + * | Dest_Addr[31:0] | + * +--------------------------------------------------------------+ + * | Next_Desc_Add[31:0] | + * +--------------------------------------------------------------+ + */ +unsigned char tls_dma_start(unsigned char ch, struct tls_dma_descriptor *dma_desc, + unsigned char auto_reload); + +/** + * @brief This function is used to To stop current DMA channel transfer + * + * @param[in] ch channel no. to be stopped + * + * @retval Always STATUS_SUCCESS + * + * @note If channel stop, DMA_CHNL_CTRL_CHNL_ON bit in DMA_CHNLCTRL_REG is cleared. + */ +unsigned char tls_dma_stop(unsigned char ch); + + +/** + * @brief This function is used to Request a free dma channel. + * If ch is 0, the function will select a random free channel, + * else return the selected channel no. if free. + * + * @param[in] ch channel no. + * @param[in] flags flags setted to selected channel + * + * @return Channel no. that is free now + * + * @note Channel no. that is free now + */ +unsigned char tls_dma_request(unsigned char ch, unsigned char flags); + + +/** + * @brief This function is used to Free the DMA channel when not use + * + * @param[in] ch channel no. that is ready to free + * + * @return None + * + * @note None + */ +void tls_dma_free(unsigned char ch); + + +/** + * @brief This function is used to Initialize DMA Control + * + * @param[in] None + * + * @return None + * + * @note None + */ +void tls_dma_init(void); + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif +#endif /* end of __WM_DMA_H_ */ + +/*** (C) COPYRIGHT 2014 Winner Microelectronics Co., Ltd. ***/ + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_efuse.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_efuse.h new file mode 100644 index 00000000..ad150dc2 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_efuse.h @@ -0,0 +1,269 @@ +/** + * @file wm_efuse.h + * + * @brief virtual efuse Driver Module + * + * @author dave + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#ifndef WM_EFUSE_H +#define WM_EFUSE_H + +#define TLS_EFUSE_STATUS_OK (0) +#define TLS_EFUSE_STATUS_EINVALID (1) +#define TLS_EFUSE_STATUS_EIO (2) + +enum { + CMD_MAC = 0x01, + CMD_TX_DC, + CMD_RX_DC, + CMD_TX_IQ_GAIN, + CMD_RX_IQ_GAIN, + CMD_TX_IQ_PHASE, + CMD_RX_IQ_PHASE, + CMD_TX_GAIN, + CMD_ALL, +}; + +#define VCG_ADDR (FT_MAGICNUM_ADDR + sizeof(FT_PARAM_ST)+4) +#define VCG_LEN (4) +//#define TX_GAIN_NEW_ADDR (VCG_ADDR+VCG_LEN) +#define TX_GAIN_LEN (28*3) + +/** +* @brief This function is used to init ft param. +* +* @param[in] None +* +* @retval TRUE init success +* @retval FALSE init failed +*/ +int tls_ft_param_init(void); + + +/** +* @brief This function is used to write ft_param. +* +* @param[in] opnum ft cmd +* @param[in] data data pointer +* @param[in] len len to write data +* +* @retval TLS_EFUSE_STATUS_OK set success +* @retval TLS_EFUSE_STATUS_EIO set failed +*/ +int tls_ft_param_set(unsigned int opnum, void *data, unsigned int len); + +/** +* @brief This function is used to read ft_param. +* +* @param[in] opnum ft cmd +* @param[in] data data pointer +* @param[in] len len to read data +* +* @retval TLS_EFUSE_STATUS_OK get success +* @retval TLS_EFUSE_STATUS_EIO get failed +*/ +int tls_ft_param_get(unsigned int opnum, void *data, unsigned int rdlen); + + +/** +* @brief This function is used to get mac addr +* +* @param[in] mac mac addr,6 byte +* +* @retval TLS_EFUSE_STATUS_OK get success +* @retval TLS_EFUSE_STATUS_EIO get failed +*/ +int tls_get_mac_addr(u8 *mac); + +/** +* @brief This function is used to set mac addr +* +* @param[in] mac mac addr,6 byte +* +* @retval TLS_EFUSE_STATUS_OK set success +* @retval TLS_EFUSE_STATUS_EIO set failed +*/ +int tls_set_mac_addr(u8 *mac); + +/** +* @brief This function is used to get tx gain +* +* @param[in] txgain tx gain,12 byte +* +* @retval TLS_EFUSE_STATUS_OK get success +* @retval TLS_EFUSE_STATUS_EIO get failed +*/ +int tls_get_tx_gain(u8 *txgain); + +/** +* @brief This function is used to set tx gain +* +* @param[in] txgain tx gain,12 byte +* +* @retval TLS_EFUSE_STATUS_OK set success +* @retval TLS_EFUSE_STATUS_EIO set failed +*/ +int tls_set_tx_gain(u8 *txgain); + +/** +* @brief This function is used to get tx lod +* +* @param[in] txlo tx lod +* +* @retval TLS_EFUSE_STATUS_OK get success +* @retval TLS_EFUSE_STATUS_EIO get failed +*/ +int tls_get_tx_lo(u8 *txlo); + +/** +* @brief This function is used to set tx lod +* +* @param[in] txlo tx lod +* +* @retval TLS_EFUSE_STATUS_OK set success +* @retval TLS_EFUSE_STATUS_EIO set failed +*/ + +int tls_set_tx_lo(u8 *txlo); + +/** +* @brief This function is used to get tx iq gain +* +* @param[in] txGain +* +* @retval TLS_EFUSE_STATUS_OK get success +* @retval TLS_EFUSE_STATUS_EIO get failed +*/ +int tls_get_tx_iq_gain(u8 *txGain); + +/** +* @brief This function is used to set tx iq gain +* +* @param[in] txGain +* +* @retval TLS_EFUSE_STATUS_OK set success +* @retval TLS_EFUSE_STATUS_EIO set failed +*/ +int tls_set_tx_iq_gain(u8 *txGain); + +/** +* @brief This function is used to get rx iq gain +* +* @param[in] rxGain +* +* @retval TLS_EFUSE_STATUS_OK get success +* @retval TLS_EFUSE_STATUS_EIO get failed +*/ +int tls_get_rx_iq_gain(u8 *rxGain); + +/** +* @brief This function is used to get rx iq gain +* +* @param[in] rxGain +* +* @retval TLS_EFUSE_STATUS_OK set success +* @retval TLS_EFUSE_STATUS_EIO set failed +*/ +int tls_set_rx_iq_gain(u8 *rxGain); + +/** +* @brief This function is used to get tx iq phase +* +* @param[in] txPhase +* +* @retval TLS_EFUSE_STATUS_OK get success +* @retval TLS_EFUSE_STATUS_EIO get failed +*/ +int tls_get_tx_iq_phase(u8 *txPhase); + +/** +* @brief This function is used to set tx iq phase +* +* @param[in] txPhase +* +* @retval TLS_EFUSE_STATUS_OK set success +* @retval TLS_EFUSE_STATUS_EIO set failed +*/ +int tls_set_tx_iq_phase(u8 *txPhase); + +/** +* @brief This function is used to get rx iq phase +* +* @param[in] rxPhase +* +* @retval TLS_EFUSE_STATUS_OK get success +* @retval TLS_EFUSE_STATUS_EIO get failed +*/ +int tls_get_rx_iq_phase(u8 *rxPhase); + +/** +* @brief This function is used to set rx iq phase +* +* @param[in] rxPhase +* +* @retval TLS_EFUSE_STATUS_OK set success +* @retval TLS_EFUSE_STATUS_EIO set failed +*/ +int tls_set_rx_iq_phase(u8 *rxPhase); + +/** +* @brief This function is used to set/get freq err +* +* @param[in] freqerr +* @param[in] flag 1-set 0-get +* @retval TLS_EFUSE_STATUS_OK set/get success +* @retval TLS_EFUSE_STATUS_EIO set/get failed +*/ +int tls_freq_err_op(u8 *freqerr, u8 flag); + +/** +* @brief This function is used to set/get vcg ctrl +* +* @param[in] vcg +* @param[in] flag 1-set 0-get +* +* @retval TLS_EFUSE_STATUS_OK set/get success +* @retval TLS_EFUSE_STATUS_EIO set/get failed +*/ +int tls_rf_vcg_ctrl_op(u8 *vcg, u8 flag); + +/** +* @brief This function is used to get chip ID +* +* @param[out] chip_id +* +* @retval TLS_EFUSE_STATUS_OK get success +* @retval TLS_FLS_STATUS_EPERM flash driver module not beed installed +*/ +int tls_get_chipid(u8 chip_id[16]); + +/** +* @brief This function is used to get chip ID +* +* @param[in] seconds +* +* @retval TLS_EFUSE_STATUS_OK success +*/ +unsigned int tls_sleep(unsigned int seconds); + +/** +* @brief This function is used to get chip ID +* +* @param[in] msec +* +* @retval TLS_EFUSE_STATUS_OK success +*/ +int tls_msleep(unsigned int msec); +/** +* @brief This function is used to get chip ID +* +* @param[in] usec +* +* @retval TLS_EFUSE_STATUS_OK success +*/ +int tls_usleep(unsigned int usec); + +#endif /* WM_EFUSE_H */ + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_flash.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_flash.h new file mode 100644 index 00000000..b3e7ffb9 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_flash.h @@ -0,0 +1,159 @@ +/** + * @file wm_flash.h + * + * @brief flash Driver module + * + * @author dave + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ +#ifndef WM_FLASH_H +#define WM_FLASH_H + +#include "wm_type_def.h" +#include "wm_osal.h" + +#define TLS_FLS_STATUS_OK (0) +#define TLS_FLS_STATUS_EINVAL (1) +#define TLS_FLS_STATUS_EBUSY (2) +#define TLS_FLS_STATUS_EPERM (3) +#define TLS_FLS_STATUS_ENOSUPPORT (4) +#define TLS_FLS_STATUS_EEXIST (5) +#define TLS_FLS_STATUS_ENOMEM (6) +#define TLS_FLS_STATUS_EOVERFLOW (7) +#define TLS_FLS_STATUS_ENODEV (8) +#define TLS_FLS_STATUS_EDEV (9) +#define TLS_FLS_STATUS_EIO (10) +#define TLS_FLS_STATUS_ENODRV (11) + +#define TLS_FLS_PARAM_TYPE_ID (0) +#define TLS_FLS_PARAM_TYPE_SIZE (1) +#define TLS_FLS_PARAM_TYPE_PAGE_SIZE (2) +#define TLS_FLS_PARAM_TYPE_PROG_SIZE (3) +#define TLS_FLS_PARAM_TYPE_SECTOR_SIZE (4) + +#define TLS_FLS_FLAG_UNDER_PROTECT (1<<0) +#define TLS_FLS_FLAG_FAST_READ (1<<1) +#define TLS_FLS_FLAG_AAAI (1<<2) + +#define FLS_CMD_READ_DEV_ID (0x9F) // read device id //(0x9f) + +/** + * @struct fls_list list + */ +struct fls_list +{ + struct fls_list *next; + struct fls_list *prev; +}; + + +/** + * @struct tls_fls_drv flash driver + */ +struct tls_fls_drv +{ + struct fls_list drv_list; + u32 id; + u32 total_size; + u32 page_size; + u32 program_size; + u32 sector_size; + u32 clock; + u8 mode; + u8 cs_active; + u8 flags; + int (*read) (u32, u8 *, u32); + int (*fast_read) (u32, u8 *, u32); + int (*page_write) (u32, u8 *); + int (*erase) (u32); + int (*chip_erase) (void); + int (*probe)(u32 id); + void (*remove) (void); +}; + +/** + * @struct tls_fls flash + */ +struct tls_fls +{ + struct fls_list fls_drvs; + struct tls_fls_drv *current_drv; + tls_os_sem_t *fls_lock; +}; + +/** + * @defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** + * @addtogroup Driver_APIs + * @{ + */ + +/** + * @defgroup SPIFLASH_Driver_APIs SPIFLASH Driver APIs + * @brief SPIFLASH driver APIs + */ + +/** + * @addtogroup SPIFLASH_Driver_APIs + * @{ + */ + +/** + * @brief This function is used to initial flash module structer. + * + * @param[in] None + * + * @retval TLS_FLS_STATUS_OK if init sucsess + * @retval TLS_FLS_STATUS_EBUSY already inited + * @retval TLS_FLS_STATUS_ENOMEM memory error + * + * @note None + */ +int tls_spifls_init(void); + + +/** + * @brief This function is used to read data from the flash. + * + * @param[in] addr Specifies the starting address to read from + * @param[in] buf Pointer to a byte array that is to be written. + * @param[in] len length to read. + * + * @retval TLS_FLS_STATUS_OK if read sucsess + * @retval TLS_FLS_STATUS_EIO if read fail + * + * @note None + */ +int tls_spifls_read(u32 addr, u8 * buf, u32 len); + + +/** + * @brief This function is used to write data into the flash. + * + * @param[in] addr Specifies the starting address to write to. + * @param[in] buf Pointer to a byte array that holds the data to be written. + * @param[in] len length to write. + * + * @retval TLS_FLS_STATUS_OK if write flash success + * @retval TLS_FLS_STATUS_EPERM if flash struct point is null + * @retval TLS_FLS_STATUS_ENODRV if flash driver is not installed + * @retval TLS_FLS_STATUS_EINVAL if argument is invalid + * @retval TLS_FLS_STATUS_EIO if io error + * + * @note None + */ +int tls_spifls_write(u32 addr, u8 * buf, u32 len); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WM_FLASH_H */ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_flash_map.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_flash_map.h new file mode 100644 index 00000000..b0ce8b57 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_flash_map.h @@ -0,0 +1,84 @@ +/** + * @file wm_flash_map.h + * + * @brief flash zone map + * + * @author dave + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#ifndef __WM_FLASH_MAP_H__ +#define __WM_FLASH_MAP_H__ + +/**FLASH MAP**/ + +/**Flash Base Address */ +#define FLASH_BASE_ADDR (0x08000000UL) + +#define FLASH_1M_END_ADDR (0x08100000UL) + +/**Run-time image header area*/ +#define CODE_RUN_HEADER_ADDR (0x08010000UL) +#define CODE_RUN_HEADER_AREA_LEN (0x100) + +/**Run-time image area*/ +#define CODE_RUN_START_ADDR (0x08010100UL) + +/******************************************************** +******************LAYOUT For 1M Flash********************** + *Reserved 0x8000000-0x8010000 64Kbyte + *Code 0x8010100-0x808FFFF 512Kbyte - 256 byte + *Update 0x8090000-0x80EFFFF 384Kbyte + *User 0x80F0000-0x80FBFFF 48Kbyte + *Parameter 0x80FC000-0x80FFFFF 16Kbyte +********************************************************* + +**************LAYOUT For 2M Flash as 1M LAYOUT************** + *Reserved 0x8000000-0x8010000 64Kbyte + *Code 0x8010100-0x80FFFFF 896Kbyte -256byte + *Old User Area 0x80F0000-0x80FBFFF 48Kbyte + *Parameter 0x80FC000-0x80FFFFF 16Kbyte + *Update 0x8100000-0x81AFFFF 704Kbyte + *EXT User 0x81B0000-0x81FFFFF 320Kbyte +********************************************************* + +******************LAYOUT For 2M Flash********************* + *Reserved 0x8000000-0x8010000 64Kbyte + *Code 0x8010100-0x80FFFFF 960Kbyte -256byte + *Update 0x8100000-0x81BFFFF 768Kbyte + *User 0x81C0000-0x81FBFFF 240Kbyte + *Parameter 0x81FC000-0x81FFFFF 16Kbyte +********************************************************* +*********************************************************/ + +/**Run-time image area size*/ +extern unsigned int CODE_RUN_AREA_LEN; + +/**Area can be used by User in 1M position*/ +extern unsigned int USER_ADDR_START; +extern unsigned int TLS_FLASH_PARAM_DEFAULT; +extern unsigned int USER_AREA_LEN; +extern unsigned int USER_ADDR_END; + + +/**Upgrade image header area & System parameter area */ +extern unsigned int CODE_UPD_HEADER_ADDR; +extern unsigned int TLS_FLASH_PARAM1_ADDR; +extern unsigned int TLS_FLASH_PARAM2_ADDR; +extern unsigned int TLS_FLASH_PARAM_RESTORE_ADDR; + +/**Upgrade image area*/ +extern unsigned int CODE_UPD_START_ADDR; +extern unsigned int CODE_UPD_AREA_LEN; + +/**Area can be used by User in 2M position*/ +extern unsigned int EX_USER_ADDR_START; +extern unsigned int EX_USER_AREA_LEN; +extern unsigned int EX_USER_ADDR_END; + +extern unsigned int TLS_FLASH_END_ADDR; + +#define SIGNATURE_WORD 0xa0ffff9f + +#endif /*__WM_CONFIG_H__*/ + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_fls_gd25qxx.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_fls_gd25qxx.h new file mode 100644 index 00000000..6407e156 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_fls_gd25qxx.h @@ -0,0 +1,60 @@ +/** + * @file wm_fls_gd25qxx.h + * + * @brief wm gd25qxx flash driver + * + * @author dave + * + * @copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ + +#ifndef TLS_EXSPIFLS_H +#define TLS_EXSPIFLS_H + +#define SPI_SCLK (10000000) /** 10MHz. */ +#define FLASH_TOTAL_SIZE (1024*1024) +#define PAGE_SIZE 256 +#define PROGRAM_SIZE 256 +#define PAGE_ADDR_OFFSET 8 +#define SECTOR_SIZE 4096 + + +/** + * command code define. + */ +#define EXSPIFLASH_WRITE_ENABLE (0x06) /** Global write enable */ +#define EXSPIFLASH_WRITE_DISABLE (0x04) /** Global write disable */ +#define EXSPIFLASH_READ_SR1 (0x05) /** Read flash status register s0~s7 */ +#define EXSPIFLASH_READ_SR2 (0x35) /** Read flash status register s8~s15 */ +#define EXSPIFLASH_WRITE_SR (0x01) /** Write flash status register s0~s15 */ +#define EXSPIFLASH_PAGE_PROGRAM (0x02) /** program one page */ +#define EXSPIFLASH_DATA_READ (0x03) /** read data from specified address */ +#define EXSPIFLASH_DATA_FAST_READ (0x0b) /** fast read data from specified address */ +#define EXSPIFLASH_SECTOR_ERASE (0x20) /** Sector erase */ +#define EXSPIFLASH_BLOCK32_ERASE (0x52) /** 32KB Block erase(128 pages) */ +#define EXSPIFLASH_BLOCK64_ERASE (0xd8) /** 64kb Block erase(256 pages) */ +#define EXSPIFLASH_CHIP_ERASE (0xc7) /** Chip erase */ +#define EXSPIFLASH_FLASH_DEVICEID (0x90) /** Read flash manufacturer/device ID */ +#define EXSPIFLASH_FLASH_ID (0x9f) /** Read flash ID */ + + +#define FLASH_STATUS_BUSY (1 << 0) +#define FLASH_STATUS_WEL (1 << 1) + +/** + * @brief This function is used to install gd25qxx driver. + * + * @param[in] None + * + * @retval TLS_FLS_STATUS_OK if write flash success + * @retval TLS_FLS_STATUS_EPERM if flash struct point is null + * @retval TLS_FLS_STATUS_ENODRV if flash driver is not installed + * @retval TLS_FLS_STATUS_EINVAL if argument is invalid + * @retval TLS_FLS_STATUS_EIO if io error + * @retval TLS_FLS_STATUS_EEXIST if driver is already existed + * + * @note None + */ +int tls_spifls_drv_install(void); + +#endif /* TLS_FLS_GD25QXX_H */ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_gpio.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_gpio.h new file mode 100644 index 00000000..17f7bb71 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_gpio.h @@ -0,0 +1,189 @@ +/** + * @file wm_gpio.h + * + * @brief GPIO Driver Module + * + * @author dave + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#ifndef WM_GPIO_H +#define WM_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "wm_type_def.h" +#include "wm_io.h" + +/** gpio interrupte callback function */ +typedef void (*tls_gpio_irq_callback)(void *arg); + +/** Indicating gpio direction */ +enum tls_gpio_dir { + WM_GPIO_DIR_OUTPUT, /**< output */ + WM_GPIO_DIR_INPUT /**< input */ +}; + +/** Indicating gpio attribute */ +enum tls_gpio_attr { + WM_GPIO_ATTR_FLOATING, /**< floating status */ + WM_GPIO_ATTR_PULLHIGH, /**< pull high */ + WM_GPIO_ATTR_PULLLOW /**< pull low */ +}; + +/** Indicating gpio interrupt trigger type */ +enum tls_gpio_irq_trig { + WM_GPIO_IRQ_TRIG_RISING_EDGE, /**< rising edge arises the interrupt */ + WM_GPIO_IRQ_TRIG_FALLING_EDGE, /**< falling edge arises the interrupt */ + WM_GPIO_IRQ_TRIG_DOUBLE_EDGE, /**< both rising edge and falling edge arise the interrupt */ + WM_GPIO_IRQ_TRIG_HIGH_LEVEL, /**< high power level arises the interrupt */ + WM_GPIO_IRQ_TRIG_LOW_LEVEL /**< low power level arises the interrupt */ +}; + +/** + * @defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** + * @addtogroup Driver_APIs + * @{ + */ + +/** + * @defgroup GPIO_Driver_APIs GPIO Driver APIs + * @brief GPIO driver APIs + */ + +/** + * @addtogroup GPIO_Driver_APIs + * @{ + */ + + +/** + * @brief This function is used to config gpio function + * + * @param[in] gpio_pin gpio pin num + * @param[in] dir gpio direction + * @param[in] attr gpio attribute + * + * @return None + * + * @note None + */ +void tls_gpio_cfg(enum tls_io_name gpio_pin, enum tls_gpio_dir dir, enum tls_gpio_attr attr); + + +/** + * @brief This function is used to read gpio status + * + * @param[in] gpio_pin gpio pin num + * + * @retval 0 power level is low + * @retval 1 power level is high + * + * @note None + */ +u8 tls_gpio_read(enum tls_io_name gpio_pin); + + +/** + * @brief This function is used to modify gpio status + * + * @param[in] gpio_pin gpio pin num + * @param[in] value power level + * 0: low power level + * 1: high power level + * + * @return None + * + * @note None + */ +void tls_gpio_write(enum tls_io_name gpio_pin, u8 value); + + +/** + * @brief This function is used to config gpio interrupt + * + * @param[in] gpio_pin gpio pin num + * @param[in] mode interrupt trigger type + * + * @return None + * + * @note None + */ +void tls_gpio_irq_enable(enum tls_io_name gpio_pin, enum tls_gpio_irq_trig mode); + + +/** + * @brief This function is used to disable gpio interrupt + * + * @param[in] gpio_pin gpio pin num + * + * @return None + * + * @note None + */ +void tls_gpio_irq_disable(enum tls_io_name gpio_pin); + + +/** + * @brief This function is used to get gpio interrupt status + * + * @param[in] gpio_pin gpio pin num + * + * @retval 0 no interrupt happened + * @retval 1 interrupt happened + * + * @note None + */ +u8 tls_get_gpio_irq_status(enum tls_io_name gpio_pin); + + +/** + * @brief This function is used to clear gpio interrupt flag + * + * @param[in] gpio_pin gpio pin num + * + * @return None + * + * @note None + */ +void tls_clr_gpio_irq_status(enum tls_io_name gpio_pin); + + +/** + * @brief This function is used to register gpio interrupt + * + * @param[in] gpio_pin gpio pin num + * @param[in] callback the gpio interrupt call back function + * @param[in] arg parammeter for the callback + * + * @return None + * + * @note + * gpio callback function is called in interrupt, + * so can not operate the critical data in the callback fuuction, + * recommendation to send messages to other tasks to operate it. + */ +void tls_gpio_isr_register(enum tls_io_name gpio_pin, + tls_gpio_irq_callback callback, + void *arg); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif +#endif /* end of WM_GPIO_H */ + +/*** (C) COPYRIGHT 2014 Winner Microelectronics Co., Ltd. ***/ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_gpio_afsel.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_gpio_afsel.h new file mode 100644 index 00000000..5f2cbf78 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_gpio_afsel.h @@ -0,0 +1,506 @@ +/** + * @file wm_gpio_afsel.h + * + * @brief GPIO Driver Module + * + * @author dave + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#ifndef WM_IO_MUX_H +#define WM_IO_MUX_H + +#ifdef __cplusplus +extern "C" { +#endif +#include "wm_gpio.h" +#include "wm_regs.h" +#include "wm_irq.h" +#include "tls_common.h" + +/** + * @defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** + * @addtogroup Driver_APIs + * @{ + */ + +/** + * @defgroup IOMUX_Driver_APIs IOMUX Driver APIs + * @brief IOMUX driver APIs + */ + +/** + * @addtogroup IOMUX_Driver_APIs + * @{ + */ + +/** + * @brief config the pins used for highspeed spi + * @param numsel: config highspeed spi pins multiplex relation,valid para 0,1 + * 0: hspi0 + * hspi_int PB14 + * hspi_cs PB15 + * hspi_ck PB16 + * hspi_di PB17 + * hspi_do PB18 + * 1: hspi1 + * hspi_int PB08 + * hspi_cs PB09 + * hspi_ck PB10 + * hspi_di PB11 + * hspi_do PB12 + * @return None + */ +void wm_hspi_gpio_config(uint8_t numsel); + +/** + * @brief config the pins used for spi ck + * @param io_name: config spi ck pins name + * WM_IO_PA_01 + * WM_IO_PB_16 + * WM_IO_PB_27 + * WM_IO_PA_11 + * + * @return None + */ +void wm_spi_ck_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for spi cs + * @param io_name: config spi cs pins name + * WM_IO_PA_02 + * WM_IO_PB_15 + * WM_IO_PB_00 + * WM_IO_PB_07 + * WM_IO_PA_12 + * + * @return None + */ +void wm_spi_cs_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for spi di + * @param io_name: config spi di pins name + * WM_IO_PA_03 + * WM_IO_PB_17 + * WM_IO_PB_01 + * WM_IO_PA_05 + * WM_IO_PA_10 + * + * @return None + */ +void wm_spi_di_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for spi do + * @param io_name: config spi do pins name + * WM_IO_PB_18 + * WM_IO_PB_02 + * WM_IO_PB_04 + * WM_IO_PA_09 + * WM_IO_PA_10 + * + * @return None + */ +void wm_spi_do_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for sdio ck dat0 dat1 dat2 dat3 + * @param numsel: config sdio ck dat0 dat1 dat2 dat3 pins multiplex relation,valid para 0 + * 0: + * sdio_ck PB08 + * sdio_dat0 PB09 + * sdio_dat1 PB10 + * sdio_dat2 PB11 + * sdio_dat3 PB12 + * + * @return None + */ +void wm_sdio_config(uint8_t numsel); + +/** + * @brief config the pins used for sdio cmd + * @param io_name: config sdio cmd pins name + * WM_IO_PA_06 + * WM_IO_PB_07 + * WM_IO_PB_13 + * + * @return None + */ +void wm_sdio_cmd_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for uart0 tx + * @param io_name: config uart0 tx pins name + * WM_IO_PA_04 + * WM_IO_PA_08 + * WM_IO_PB_07 + * WM_IO_PB_26 + * + * @return None + */ +void wm_uart0_tx_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for uart0 rx + * @param io_name: config uart0 rx pins name + * WM_IO_PA_05 + * WM_IO_PA_09 + * WM_IO_PB_06 + * WM_IO_PB_25 + * + * @return None + */ +void wm_uart0_rx_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for uart0 rts + * @param io_name: config uart0 rts pins name + * WM_IO_PA_13 + * WM_IO_PB_04 + * WM_IO_PB_24 + * + * @return None + */ +void wm_uart0_rts_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for uart0 cts + * @param io_name: config uart0 cts pins name + * WM_IO_PA_14 + * WM_IO_PB_05 + * WM_IO_PB_23 + * + * @return None + */ +void wm_uart0_cts_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for uart1 tx + * @param io_name: config uart1 tx pins name + * WM_IO_PB_12 + * WM_IO_PB_18 + * + * @return None + */ +void wm_uart1_tx_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for uart1 rx + * @param io_name: config uart1 rx pins name + * WM_IO_PB_11 + * WM_IO_PB_17 + * + * @return None + */ +void wm_uart1_rx_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for uart1 rts + * @param io_name: config uart1 rts pins name + * WM_IO_PB_10 + * + * @return None + */ +void wm_uart1_rts_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for uart1 cts + * @param io_name: config uart1 cts pins name + * WM_IO_PB_09 + * + * @return None + */ +void wm_uart1_cts_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for uart2 tx or 7816-io + * @param io_name: config uart2 tx or 7816-io pins name + * WM_IO_PA_01 + * WM_IO_PA_11 + * WM_IO_PB_02 + * WM_IO_PB_20 + * + * @return None + */ +void wm_uart2_tx_scio_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for uart2 rx + * @param io_name: config uart2 rx pins name + * WM_IO_PA_00 + * WM_IO_PA_10 + * WM_IO_PB_03 + * WM_IO_PB_19 + * WM_IO_PB_30 + * + * @return None + */ +void wm_uart2_rx_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for uart2 rts or 7816-clk + * @param io_name: config uart2 rts or 7816-clk pins name + * WM_IO_PA_02 + * WM_IO_PA_12 + * WM_IO_PB_01 + * WM_IO_PB_21 + * WM_IO_PB_06 + * + * @return None + */ +void wm_uart2_rts_scclk_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for uart2 cts + * @param io_name: config uart2 cts pins name + * WM_IO_PA_03 + * WM_IO_PB_28 + * WM_IO_PB_00 + * + * @return None + */ +void wm_uart2_cts_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for i2s master ck + * @param io_name: config i2s master ck pins name + * WM_IO_PA_04 + * WM_IO_PA_08 + * WM_IO_PB_08 + * + * @return None + */ +void wm_i2s_m_ck_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for i2s master ws + * @param io_name: config i2s master ws pins name + * WM_IO_PA_13 + * WM_IO_PA_09 + * WM_IO_PB_10 + * + * @return None + */ +void wm_i2s_m_ws_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for i2s master do + * @param io_name: config i2s master do pins name + * WM_IO_PA_03 + * WM_IO_PA_07 + * WM_IO_PB_09 + * + * @return None + */ +void wm_i2s_m_do_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for i2s slave ck + * @param io_name: config i2s slave ck pins name + * WM_IO_PA_15 + * WM_IO_PA_11 + * WM_IO_PB_15 + * WM_IO_PB_04 + * + * @return None + */ +void wm_i2s_s_ck_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for i2s slave ws + * @param io_name: config i2s slave ws pins name + * WM_IO_PA_06 + * WM_IO_PA_12 + * WM_IO_PB_16 + * WM_IO_PB_05 + * + * @return None + */ +void wm_i2s_s_ws_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for i2s slave di + * @param io_name: config i2s slave di pins name + * WM_IO_PA_14 + * WM_IO_PA_10 + * WM_IO_PB_14 + * WM_IO_PB_03 + * + * @return None + */ +void wm_i2s_s_di_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for i2s mclk + * @param io_name: config i2s mclk pins name + * WM_IO_PA_02 + * WM_IO_PB_28 + * WM_IO_PB_31 + * + * @return None + */ +void wm_i2s_mclk_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for i2s extclk + * @param io_name: config i2s extclk pins name + * WM_IO_PA_05 + * + * @return None + */ +void wm_i2s_extclk_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for i2c scl + * @param io_name: config i2c scl pins name + * WM_IO_PA_06 + * WM_IO_PA_08 + * WM_IO_PB_13 + * WM_IO_PB_11 + * WM_IO_PB_21 + * + * @return None + */ +void wm_i2c_scl_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for i2c sda + * @param io_name: config i2c sda pins name + * WM_IO_PA_15 + * WM_IO_PA_07 + * WM_IO_PB_14 + * WM_IO_PB_12 + * WM_IO_PB_22 + * + * @return None + */ +void wm_i2c_sda_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for pwm1 + * @param io_name: config pwm1 pins name + * WM_IO_PA_00 + * WM_IO_PB_18 + * WM_IO_PB_05 + * WM_IO_PA_05 + * WM_IO_PB_19 + * WM_IO_PB_30 + * + * @return None + */ +void wm_pwm1_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for pwm1 + * @param io_name: config pwm1 pins name + * WM_IO_PA_01 + * WM_IO_PB_11 + * WM_IO_PB_04 + * WM_IO_PA_07 + * WM_IO_PB_13 + * WM_IO_PB_20 + * + * @return None + */ +void wm_pwm2_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for pwm3 + * @param io_name: config pwm3 pins name + * WM_IO_PA_02 + * WM_IO_PB_16 + * WM_IO_PB_03 + * WM_IO_PA_08 + * WM_IO_PB_21 + * + * @return None + */ +void wm_pwm3_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for pwm4 + * @param io_name: config pwm4 pins name + * WM_IO_PA_03 + * WM_IO_PB_15 + * WM_IO_PB_02 + * WM_IO_PA_09 + * WM_IO_PB_22 + * + * @return None + */ +void wm_pwm4_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for pwm5 + * @param io_name: config pwm5 pins name + * WM_IO_PA_04 + * WM_IO_PB_14 + * WM_IO_PB_01 + * WM_IO_PA_10 + * WM_IO_PB_23 + * + * @return None + */ +void wm_pwm5_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for pwm break + * @param io_name: config pwm break pins name + * WM_IO_PB_24 + * WM_IO_PB_29 + * WM_IO_PB_00 + * WM_IO_PA_11 + * + * @return None + */ +void wm_pwmbrk_config(enum tls_io_name io_name); + +/** + * @brief config the pins used for swd + * @param enable: enable or disable chip swd function + * 1: enable + * 0: disable + * + * @return None + */ +void wm_swd_config(bool enable); + +/** + * @brief config the pins used for adc + * @param Channel: the channel that shall be used + * 0~07: single-ended input + * 8~11: differential input + * + * @return None + */ +void wm_adc_config(u8 Channel); + +/** + * @brief disable all the gpio af + * + * @return None + * + * @note This function must call before anyothers for configure + * gpio Alternate functions + */ +void wm_gpio_af_disable(void); +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif +#endif /* end of WM_IO_MUX_H */ + +/*** (C) COPYRIGHT 2014 Winner Microelectronics Co., Ltd. ***/ + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_hostspi.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_hostspi.h new file mode 100644 index 00000000..ce2380be --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_hostspi.h @@ -0,0 +1,296 @@ +/** + * @file wm_hostspi.h + * + * @brief host spi Driver Module + * + * @author dave + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ +#ifndef WM_HOST_SPI_H +#define WM_HOST_SPI_H + +#include "wm_type_def.h" +#include "list.h" +//#include "wm_osal.h" +#include "wm_ram_config.h" + + +#define SPI_USE_DMA + +#define SPI_TX_DMA_MASK 0x01 +#define SPI_RX_DMA_MASK 0x02 + +#define SPI_DMA_CMD_ADDR ((u32)(MASTER_SPI_DMA_ADDR)) +#define SPI_DMA_CMD_MAX_SIZE (0x20) + +#define SPI_DMA_BUF_ADDR ((u32)(SPI_DMA_CMD_ADDR + SPI_DMA_CMD_MAX_SIZE)) +#define SPI_DMA_BUF_MAX_SIZE 8160 + +#define SPI_DMA_MAX_TRANS_SIZE 4092 + +/** + * error code. + */ +#define TLS_SPI_STATUS_OK (0) +#define TLS_SPI_STATUS_EINVAL (-1) +#define TLS_SPI_STATUS_ENOMEM (-2) +#define TLS_SPI_STATUS_EBUSY (-3) +#define TLS_SPI_STATUS_ESHUTDOWN (-4) +#define TLS_SPI_STATUS_EPERM (-5) +#define TLS_SPI_STATUS_ECLKNOSUPPORT (-6) +#define TLS_SPI_STATUS_EMODENOSUPPORT (-7) + +#define SPI_MASTER_FIFO_SIZE (32) + +/** + * the SPI master controller's configuration data. + */ + /** configuration data. */ +#define SPI_CPHA (0x01) /** clock phase. */ +#define SPI_CPOL (0x02) /** clock polarity. */ +#define TLS_SPI_MODE_0 (0|0) /** motorola mode. */ +#define TLS_SPI_MODE_1 (0|SPI_CPHA) +#define TLS_SPI_MODE_2 (SPI_CPOL|0) +#define TLS_SPI_MODE_3 (SPI_CPOL|SPI_CPHA) +#define TLS_SPI_CS_LOW 0x00 /** chipselect active low. */ +#define TLS_SPI_CS_HIGH 0x01 /** chipselect active high. */ +#define TLS_SPI_FCLK_MIN (1000) /** minimum work clock rate(Hz). */ +#define TLS_SPI_FCLK_MAX (APB_CLK/2) /** maximum work clock rate(Hz). */ + + +/** default configuration data. */ +#define SPI_DEFAULT_SPEED (2000000) /** default clock rate is 2MHz. */ +#define SPI_DEFAULT_MODE (TLS_SPI_MODE_0) /** default mode MODE_0. */ +#define SPI_CS_ACTIVE_MODE (TLS_SPI_CS_LOW) /** default chipselect mode is active low. */ +#define SPI_CS_INACTIVE_MODE (TLS_SPI_CS_HIGH) + +/** SPI transaction message status. */ +#define SPI_MESSAGE_STATUS_IDLE (0) +#define SPI_MESSAGE_STATUS_INPROGRESS (1) +#define SPI_MESSAGE_STATUS_DONE (2) + +/**slave type*/ +#define SPI_SLAVE_FLASH 0 /**flash */ +#define SPI_SLAVE_CARD 1 /** SD card */ +#define SPI_SLAVE_CONTROL_PIN 0 +/**transfer type*/ +#define SPI_BYTE_TRANSFER 0 /**byte transfer*/ +#define SPI_WORD_TRANSFER 1 /**word transfer*/ +#define SPI_DMA_TRANSFER 2 /** DMA transfer */ + +/** + * a read/write buffer pair + * + * SPI transfers always write the same number of bytes as they read. + * If the transmit buffer is null, zeroes will be shifted out while + * filling rx_buf. If the receive buffer is null, the data shifted in + * will be discarded. + */ +struct tls_spi_transfer +{ + struct dl_list transfer_list; /**< transfers are sequenced through + tls_spi_message.transfers. */ + + const void *tx_buf; /**< data to be written, or NULL. */ + void *rx_buf; /**< data to be read, or NULL. */ + u32 len; /**< size of rx and tx buffers (in bytes). */ + u32 delay_usecs; /**< microseconds to delay after this transfer. */ +}; + + +/** + * one multi-segment SPI transaction + * + * A struct tls_spi_message is used to execute an atomic sequence of data + * transfers, each represented by a struct tls_spi_transfer. The sequence + * is "atomic" in the sense that no other spi_message may use that SPI bus + * until that sequence completes. + */ +struct tls_spi_message +{ + struct dl_list queue; /**< transaction messages are sequenced through + tls_spi_port.wait_queue. */ + + struct dl_list transfers; /**< list of transfer segments in this transaction. */ + void (*complete) (void *); /**< called to report transaction completions. */ + void *context; /**< the argument to complete() when it's called. */ + u32 status; /**< transaction message status. */ +}; + +/** + * driver structure to SPI master controller + * + * This data structure presents the SPI master controller's configuration + * data. The device attached to this SPI master controller share the same + * transfer mode, chipselect mode and clock rate. And this structure maintains + * a queue of tls_spi_message transactions and uses this tls_spi_message transaction + * to access to the SPI device. For each such message it queues, it calls the message's + * completion function when the transaction completes. + */ +struct tls_spi_port +{ + u32 speed_hz; /**< clock rate to be used. */ + u8 cs_active; /**< chipselect mode, maybe active low or active + high. */ + u8 mode; /**< SPI transfer mode: mode_0(CPHA=0, CHOL=0), + mode_1(CPHA=0, CHOL=1), mode_2(CPHA=1, + CHOL=0), mode_3(CPHA=1, CHOL=1). */ + u8 reconfig; + + struct dl_list wait_queue; /**< wait list of transaction messages. */ + tls_os_queue_t *lock; + + tls_os_queue_t *msg_queue; /**< notify the schedule thread that there's + transaction message queued. */ + struct tls_spi_message *current_message; /**< current transaction message + in-progressing. */ + u32 current_remaining_transfer; /**< remaining transfer segments count in + current transaction message. */ + + struct tls_spi_transfer *current_transfer; /**< current transfer segment + in-progressing. */ + u32 current_remaining_bytes; /**< remaining data length in current + transfer segment. */ + + u8 transtype; /**< transfer type */ +}; + +/** + * @defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** + * @addtogroup Driver_APIs + * @{ + */ + +/** + * @defgroup HOSTSPI_Driver_APIs HOSTSPI Driver APIs + * @brief HOSTSPI driver APIs + */ + +/** + * @addtogroup HOSTSPI_Driver_APIs + * @{ + */ + +/** + * @brief This function is used to initialize the SPI master driver. + * + * @param[in] None + * + * @retval TLS_SPI_STATUS_OK if initialize success + * @retval TLS_SPI_STATUS_EBUSY if SPI is already initialized + * @retval TLS_SPI_STATUS_ENOMEM if malloc SPI memory fail + * + * @note None + */ +int tls_spi_init(void); + + +/** + * @brief This function is used to setup the spi controller. + * + * @param[in] mode is CPOL and CPHA type defined in TLS_SPI_MODE_0 to TLS_SPI_MODE_3 + * @param[in] cs_active is cs mode, defined as TLS_SPI_CS_LOW or TLS_SPI_CS_HIGH + * @param[in] fclk is spi clock,the unit is HZ. + * + * @retval TLS_SPI_STATUS_OK if setup success + * @retval TLS_SPI_STATUS_EMODENOSUPPORT if mode is not support + * @retval TLS_SPI_STATUS_EINVAL if cs_active is not support + * @retval TLS_SPI_STATUS_ECLKNOSUPPORT if fclk is not support + * + * @note None + */ +int tls_spi_setup(u8 mode, u8 cs_active, u32 fclk); + +/** + * @brief This function is used to synchronous write data by SPI. + * + * @param[in] buf data to be sent. + * @param[in] len data length. + * + * @retval TLS_SPI_STATUS_OK if write success. + * @retval TLS_SPI_STATUS_EINVAL if argument is invalid. + * @retval TLS_SPI_STATUS_ENOMEM if there is no enough memory. + * @retval TLS_SPI_STATUS_ESHUTDOWN if SPI driver does not installed. + * + * @note None + */ +int tls_spi_write(const u8 * buf, u32 len); + +/** + * @brief This function is used to synchronously read data from SPI. + * + * @param[in] buf is the buffer for saving SPI data. + * @param[in] len is the data length. + * + * @retval TLS_SPI_STATUS_OK if write success. + * @retval TLS_SPI_STATUS_EINVAL if argument is invalid. + * @retval TLS_SPI_STATUS_ENOMEM if there is no enough memory. + * @retval TLS_SPI_STATUS_ESHUTDOWN if SPI driver does not installed. + * + * @note None + */ +int tls_spi_read(u8 * buf, u32 len); + +/** + * @brief This function is used to synchronously write command and then read data from SPI. + * + * @param[in] txbuf is the write data buffer. + * @param[in] n_tx is the write data length. + * @param[in] rxbuf is the read data buffer. + * @param[in] n_rx is the read data length. + * + * @retval TLS_SPI_STATUS_OK if write success. + * @retval TLS_SPI_STATUS_EINVAL if argument is invalid. + * @retval TLS_SPI_STATUS_ENOMEM if there is no enough memory. + * @retval TLS_SPI_STATUS_ESHUTDOWN if SPI driver has not been installed. + * + * @note None + */ +int tls_spi_read_with_cmd(const u8 * txbuf, u32 n_tx, u8 * rxbuf, u32 n_rx); + +/** + * @brief This function is used to synchronous write 32bit command then write data from SPI. + * + * @param[in] cmd is the command data. + * @param[in] n_cmd is the command len,can not bigger than four + * @param[in] txbuf is the write data buffer. + * @param[in] n_tx is the write data length. + * + * @retval TLS_SPI_STATUS_OK if write success. + * @retval TLS_SPI_STATUS_EINVAL if argument is invalid. + * @retval TLS_SPI_STATUS_ENOMEM if there is no enough memory. + * @retval TLS_SPI_STATUS_ESHUTDOWN if SPI driver does not installed. + * + * @note None + */ +int tls_spi_write_with_cmd(const u8 * cmd, u32 n_cmd, const u8 * txbuf, u32 n_tx); + +/** + * @brief This function is used to set SPI transfer mode. + * + * @param[in] type is the transfer type. + * SPI_BYTE_TRANSFER ->byte transfer; + * SPI_WORD_TRANSFER ->word transfer; + * SPI_DMA_TRANSFER ->DMA transfer; + + * + * @return None + * + * @note None + */ +void tls_spi_trans_type(u8 type); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WM_HOST_SPI_H */ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_hspi.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_hspi.h new file mode 100644 index 00000000..98261240 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_hspi.h @@ -0,0 +1,264 @@ +/** + * @file wm_hspi.h + * + * + * @brief High speed spi slave Module + * + * @author dave + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ + +#ifndef WM_HSPI_H +#define WM_HSPI_H + +#include "wm_type_def.h" +#include "wm_ram_config.h" + +#define HSPI_TX_MEM_MALLOC 0 /** tx mem dynamic malloc*/ + +#define HSPI_IO_REUSE_NUM 0 +#define SDIO_IO_REUSE_NUM 2 +#define HSPI_INTERFACE_SPI 2 /** spi interface*/ +#define HSPI_INTERFACE_SDIO 3 /** sdio interface*/ + +/**rx message*/ +#define HSPI_RX_CMD_MSG 1 +#define HSPI_RX_DATA_MSG 2 + +/**spi/sdio buffer, Wraper controller can only access the address after the 0x60000*/ +#define HSPI_TXBUF_NUM 2 +#define HSPI_TX_DESC_NUM HSPI_TXBUF_NUM +#define HSPI_RXBUF_NUM 3//10 +#define HSPI_RX_DESC_NUM HSPI_RXBUF_NUM +#define HSPI_TXBUF_SIZE 1500 +#define HSPI_RXBUF_SIZE 1500 + +#define HSPI_TX_DESC_SIZE sizeof(struct tls_hspi_tx_desc) +#define HSPI_RX_DESC_SIZE sizeof(struct tls_hspi_rx_desc) + +/***************************************************************************** + * sdio/hspi sram partition + * total size : 0x61800 - 0x67FFFF (26KB) + ******************************************************************************/ +/* HSPI txbuf zone */ +#define HSPI_TXBUF_BASE_ADDR ((u32)(SLAVE_HSPI_SDIO_ADDR)) + +#if HSPI_TX_MEM_MALLOC +#define HSPI_TXBUF_TOTAL_SIZE 0 +#else +#define HSPI_TXBUF_TOTAL_SIZE (HSPI_TXBUF_SIZE * HSPI_TXBUF_NUM) +#endif +/** HSPI tx desc zone */ +#define HSPI_TX_DESC_BASE_ADDR ((u32)(HSPI_TXBUF_BASE_ADDR + HSPI_TXBUF_TOTAL_SIZE)) +#define HSPI_TX_DESC_TOTAL_SIZE (HSPI_TX_DESC_SIZE * HSPI_TX_DESC_NUM) //28*3=84 +/** HSPI rxbuf zone */ +#define HSPI_RXBUF_BASE_ADDR ((u32)(HSPI_TX_DESC_BASE_ADDR + HSPI_TX_DESC_TOTAL_SIZE)) +#define HSPI_RXBUF_TOTAL_SIZE (HSPI_RXBUF_NUM * HSPI_RXBUF_SIZE) //4500 +/** HSPI rx desc zone */ +#define HSPI_RX_DESC_BASE_ADDR ((u32)(HSPI_RXBUF_BASE_ADDR + HSPI_RXBUF_TOTAL_SIZE)) +#define HSPI_RX_DESC_TOTAL_SIZE (HSPI_RX_DESC_SIZE * HSPI_RX_DESC_NUM) //36 + +#if 0 +#define SDIO_CMD_RXBUF_SIZE (0x100) +#define SDIO_CMD_RXBUF_ADDR (0x00068000 - SDIO_CMD_RXBUF_SIZE) +#define SDIO_CIS1_ADDR (SDIO_CMD_RXBUF_ADDR - 0x80) +#define SDIO_CIS0_ADDR (SDIO_CIS1_ADDR - 0x80) +#else +#define SDIO_CIS0_ADDR (HSPI_RX_DESC_BASE_ADDR + HSPI_RX_DESC_TOTAL_SIZE) //128 +#define SDIO_CIS1_ADDR (SDIO_CIS0_ADDR + 0x80) //128 +#define SDIO_CMD_RXBUF_ADDR (SDIO_CIS1_ADDR + 0x80) +#define SDIO_CMD_RXBUF_SIZE 256//(1500) //256 +#endif +#define CIS_FUN0_ADDR SDIO_CIS0_ADDR +#define CIS_FUN1_ADDR SDIO_CIS1_ADDR + +#define FN0_TPL_FUNCID (CIS_FUN0_ADDR + 0x00) +#define FN0_TPL_FUNCE (CIS_FUN0_ADDR + 0x04) +#define FN0_TPL_FUNCE_MAXBLK (CIS_FUN0_ADDR + 0x08) +#define FN0_TPL_MANFID_MID (CIS_FUN0_ADDR + 0x0C) +#define FN0_TPL_END (CIS_FUN0_ADDR + 0x10) + +#define FN1_TPL_FUNCID (CIS_FUN1_ADDR + 0x00) +#define FN1_TPL_FUNCE (CIS_FUN1_ADDR + 0x04) +#define FN1_TPL_FUNCE_VER (CIS_FUN1_ADDR + 0x08) +#define FN1_TPL_FUNCE_NSN (CIS_FUN1_ADDR + 0x0C) +#define FN1_TPL_FUNCE_CSASIZE (CIS_FUN1_ADDR + 0x10) +#define FN1_TPL_FUNCE_OCR (CIS_FUN1_ADDR + 0x14) +#define FN1_TPL_FUNCE_MINPWR (CIS_FUN1_ADDR + 0x18) +#define FN1_TPL_FUNCE_STANDBY (CIS_FUN1_ADDR + 0x1C) +#define FN1_TPL_FUNCE_OPTBW (CIS_FUN1_ADDR + 0x20) +#define FN1_TPL_FUNCE_NTIMEOUT (CIS_FUN1_ADDR + 0x24) +#define FN1_TPL_FUNCE_AVGPWR (CIS_FUN1_ADDR + 0x28) +#define FN1_TPL_END (CIS_FUN1_ADDR + 0x30) + +/**Definition of SDIO interrupt in the system*/ +#define SDIO_RX_DATA_INT (0UL) +#define SDIO_TX_DATA_INT (1UL) +#define SDIO_RX_CMD_INT (2UL) +#define SDIO_TX_CMD_INT (3UL) + +/**IO control register*/ +#define HR_IOCTL_GP_SDIO HR_IOCTL_GP_SDIO_I2C + + +/** SDIO interrupt bit definition */ +#define SDIO_WP_INT_SRC_CMD_DOWN (1UL<<3) +#define SDIO_WP_INT_SRC_CMD_UP (1UL<<2) +#define SDIO_WP_INT_SRC_DATA_DOWN (1UL<<1) +#define SDIO_WP_INT_SRC_DATA_UP (1UL<<0) + + +/** Definition of send data descriptor structure */ +struct tls_hspi_tx_desc { + volatile u32 valid_ctrl; + u32 buf_info; + u32 buf_addr[3]; + u32 next_desc_addr; +#if HSPI_TX_MEM_MALLOC + u32 txbuf_addr; /**< txbuf addr, pbuf and buf_addr[0] are different */ +#endif +}; + +/** Definition of receive data descriptor structure */ +struct tls_hspi_rx_desc { + u32 valid_ctrl; + u32 buf_addr; + u32 next_desc_addr; +}; + + +/** struct tls_slave_hspi */ +struct tls_slave_hspi { + u8 ifusermode; + + s16 (*rx_cmd_callback)(char *buf); + + s16 (*rx_data_callback)(char *buf); + + s16 (*tx_data_callback)(char *buf); + + struct tls_hspi_tx_desc *curr_tx_desc; /**< Upstream data management */ + + struct tls_hspi_rx_desc *curr_rx_desc; /**< Downlink data management */ + +#if HSPI_TX_MEM_MALLOC + u8 txdoneflag; /**< tx done falg*/ +#endif +}; + +/** + * @defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** + * @addtogroup Driver_APIs + * @{ + */ + +/** + * @defgroup HSPI_Driver_APIs HSPI Driver APIs + * @brief HSPI driver APIs + */ + +/** + * @addtogroup HSPI_Driver_APIs + * @{ + */ + +/** + * @brief This function is used to initial HSPI register. + * + * @param[in] None + * + * @retval 0 success + * @retval other failed + * + * @note When the system is initialized, the function has been called, so users can not call this function. + */ +int tls_slave_spi_init(void); + +/** + * @brief This function is used to enable or disable user mode. + * + * @param[in] ifenable TRUE or FALSE + * + * @return None + * + * @note If the user enables the user mode, RICM instruction in the system will not be used by SPI. + * If the user wants to use the SPI interface as other use, need to enable the user mode. + * This function must be called before the register function. + */ +void tls_set_hspi_user_mode(u8 ifenable); + + +/** + * @brief This function is used to set high speed interface type. + * + * @param[in] type is the interface type. HSPI_INTERFACE_SPI or HSPI_INTERFACE_SDIO + * + * @return None + * + * @note None + */ +void tls_set_high_speed_interface_type(int type); + + +/** + * @brief This function is used to register hspi rx command interrupt. + * + * @param[in] rx_cmd_callback is the hspi rx interrupt call back function. + * + * @return None + * + * @note None + */ +void tls_hspi_rx_cmd_callback_register(s16 (*rx_cmd_callback)(char *buf)); + + +/** + * @brief This function is used to register hspi rx data interrupt. + * + * @param[in] rx_data_callback is the hspi rx interrupt call back function. + * + * @return None + * + * @note None + */ +void tls_hspi_rx_data_callback_register(s16 (*rx_data_callback)(char *buf)); + +/** + * @brief This function is used to register hspi tx data interrupt. + * + * @param[in] tx_data_callback is the hspi tx interrupt call back function. + * + * @return None + * + * @note None + */ +void tls_hspi_tx_data_callback_register(s16 (*tx_data_callback)(char *buf)); + + +/** + * @brief This function is used to transfer data. + * + * @param[in] txbuf is a buf for saving user data. + * @param[in] len is the data length. + * + * @retval transfer data len success + * @retval 0 failed + * + * @note None + */ +int tls_hspi_tx_data(char *txbuf, int len); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WM_HSPI_H */ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_i2c.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_i2c.h new file mode 100644 index 00000000..7ec3475b --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_i2c.h @@ -0,0 +1,136 @@ +/**************************************************************************//** + * @file wm_i2c.h + * @author + * @version + * @date + * @brief + * @copyright (c) 2014 Winner Microelectronics Co., Ltd. All rights reserved. + *****************************************************************************/ + +#ifndef __WM_I2C_H +#define __WM_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "wm_regs.h" +#include "wm_type_def.h" +typedef struct +{ + __IO uint32_t PRER_LO; + __IO uint32_t PRER_HI; + __IO uint32_t CTRL; + __O uint32_t TX_RX; + __O uint32_t CR_SR; + __I uint32_t TXR; + __I uint32_t CR; +}I2C_T; +#define I2C ((I2C_T *)(HR_I2C_BASE_ADDR)) + +/** + * @defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** + * @addtogroup Driver_APIs + * @{ + */ + +/** + * @defgroup I2C_Driver_APIs I2C Driver APIs + * @brief I2C driver APIs + */ + +/** + * @addtogroup I2C_Driver_APIs + * @{ + */ + +/** + * @brief Init the I2C module + * @param freq I2C reference clock frequency in Hz that will be used + * @note + * the value must be between 100k and 400k + */ +void tls_i2c_init(u32 freq); + +#define wm_i2c_int_mask(bl) do { tls_bitband_write(HR_I2C_CTRL, 6, bl);}while(0); + +/** + * @brief send stop signal + * + */ +void tls_i2c_stop(void); + +/** + * @brief Waiting for ack signal + * @retval + * - \ref WM_FAILED + * - \ref WM_SUCCESS + */ +int tls_i2c_wait_ack(void); + +/** + * @brief Writes the data to data register of I2C module + * when ifstart one the start signal will be sent followed by the data + * when ifstart zero only the data will be send + * @param[in] data the data will be write to the data register of I2C module + * @param[in] ifstart when one send start signal, when zero don't + * @retval + * + */ +void tls_i2c_write_byte(u8 data, u8 ifstart); + +/** + * @brief Get the data stored in data register of I2C module + * @param[in] ifack when one send ack after reading the data register,when zero don't + * @param[in] ifstop when one send stop signal after read, when zero do not send stop + * @retval + * the received data + */ +u8 tls_i2c_read_byte(u8 ifack, u8 ifstop); + +/** + * @brief This function is used to register i2c transfer done callback function. + * @param[in] done is the i2c transfer done callback function. + * @retval None + * @note None + */ +void wm_i2c_transfer_done_register(void (*done)(void)); + +/** + * @brief Start writing through int mode + * @param[in] devaddr the device address + * @param[in] wordaddr when one send stop signal after read, when zero do not send stop + * @param[in] buf the address point where data shoule be stored + * @param[in] len the length of data will be received + * @retval + * - \ref WM_FAILED + * - \ref WM_SUCCESS + */ +int wm_i2c_start_write_it(uint8_t devaddr, uint8_t wordaddr, uint8_t * buf, uint16_t len); + +/** + * @brief Get the data stored in data register of I2C module + * @param[in] ifack when one send ack after reading the data register,when zero don't + * @param[in] ifstop when one send stop signal after read, when zero do not send stop + * @retval the received data + */ +int wm_i2c_start_read_it(uint8_t devaddr, uint8_t wordaddr, uint8_t * buf, uint16_t len); +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2014 Winner Microelectronics Co., Ltd. ***/ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_i2s.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_i2s.h new file mode 100644 index 00000000..52539fc7 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_i2s.h @@ -0,0 +1,584 @@ +/**************************************************************************//** + * @file wm_i2s.h + * @author + * @version + * @date + * @brief + * + * @copyright (c) 2014 Winner Microelectronics Co., Ltd. All rights reserved. + *****************************************************************************/ + +#ifndef __WM_I2S_H +#define __WM_I2S_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "wm_type_def.h" +#include "wm_regs.h" +#include "wm_osal.h" +#include "misc.h" +#include "wm_dma.h" + +#define I2S_CTRL_FORMAT_Pos (24) /*!< CTRL : FORMAT Position */ +#define I2S_CTRL_FORMAT_MASK (3UL<CTRL |= I2S_CTRL_EN_MASK) + +/** + * @brief Disable I2S module + * + */ +#define TLS_I2S_DISABLE() (I2S->CTRL &= ~I2S_CTRL_EN_MASK) + +/** + * @brief Enable clock of I2S module + * + */ +#define TLS_I2S_CLK_ENABLE() \ + do { \ + tls_bitband_write(HR_CLK_I2S_CTL, HR_CLK_I2S_GATE_Pos , 1); \ + } while(0) + +/** + * @brief Disnable clock of I2S module + * + */ +#define TLS_I2S_CLK_DISABLE() \ + do { \ + tls_bitband_write(HR_CLK_I2S_CTL, HR_CLK_I2S_GATE_Pos , 0); \ + } while(0) + +/** + * @brief Enable transmit of I2S module + * + */ +#define TLS_I2S_TX_ENABLE() \ + do { \ + tls_bitband_write(HR_I2S_CTRL, I2S_CTRL_TXE_Pos, 1); \ + } while(0) + +/** + * @brief Disable transmit of I2S module + * + */ +#define TLS_I2S_TX_DISABLE() \ + do { \ + tls_bitband_write(HR_I2S_CTRL, I2S_CTRL_TXE_Pos, 0); \ + } while(0) + +/** + * @brief Enable receive of I2S module + * + */ +#define TLS_I2S_RX_ENABLE() \ + do { \ + tls_bitband_write(HR_I2S_CTRL, I2S_CTRL_RXE_Pos, 1); \ + } while(0) + +/** + * @brief Disable receive of I2S module + * + */ +#define TLS_I2S_RX_DISABLE() \ + do { \ + tls_bitband_write(HR_I2S_CTRL, I2S_CTRL_RXE_Pos, 0); \ + } while(0) + +/** + * @brief Clear receive FIFO + * + */ +#define TLS_I2S_RX_FIFO_CLEAR() \ + do { \ + tls_bitband_write(HR_I2S_CTRL, I2S_CTRL_RX_CLR_Pos, 1); \ + } while(0) + +/** + * @brief Clear transmit FIFO + * + */ +#define TLS_I2S_TX_FIFO_CLEAR() \ + do { \ + tls_bitband_write(HR_I2S_CTRL, I2S_CTRL_TX_CLR_Pos, 1); \ + } while(0) + +/** + * @brief Enable transmit DMA request + * + */ +#define TLS_I2S_TXDMA_ENABLE() (I2S->CTRL |= I2S_CTRL_TXDMA_MASK) + +/** + * @brief Disnable transmit DMA request + * + */ +#define TLS_I2S_TXDMA_DISABLE() (I2S->CTRL &= ~I2S_CTRL_TXDMA_MASK) + +/** + * @brief Enable receive DMA request + * + */ +#define TLS_I2S_RXDMA_ENABLE() (I2S->CTRL |= I2S_CTRL_RXDMA_MASK) + +/** + * @brief Disnable receive DMA request + * + */ +#define TLS_I2S_RXDMA_DISABLE() (I2S->CTRL &= ~I2S_CTRL_RXDMA_MASK) + +/** + * @brief Left channel zero-cross detection enable + * + */ +#define TLS_I2S_LZC_ENABLE() (I2S->CTRL |= I2S_CTRL_LZCEN_MASK) + +/** + * @brief Left channel zero-cross detection disable + * + */ +#define TLS_I2S_LZC_DISABLE() (I2S->CTRL &= ~I2S_CTRL_LZCEN_MASK) + +/** + * @brief Right channel zero-cross detection enable + * + */ +#define TLS_I2S_RZC_ENABLE() (I2S->CTRL |= I2S_CTRL_RZCEN_MASK) + +/** + * @brief Right channel zero-cross detection disable + * + */ +#define TLS_I2S_RZC_DISABLE() (I2S->CTRL &= ~I2S_CTRL_RZCEN_MASK) + +/** @brief Enable transmit mute + * + */ +#define TLS_I2S_TX_MUTE_ENABLE() (I2S->CTRL |= I2S_CTRL_MUTE_MASK) + +/** + * @brief Disable transmit mute + * + */ +#define TLS_I2S_TX_MUTE_DISABLE() (I2S->CTRL &= ~ I2S_CTRL_MUTE_MASK) + +/** + * @brief Set receive FIFO threshold level + * @param[in] level The value set to Rx threshold level + * + */ +static __inline__ void tls_i2s_set_rxth(uint8_t level) +{ + if (level > 8) + { + level = 3; + } + I2S->CTRL &= ~ I2S_CTRL_RXTH_MASK; + I2S->CTRL |= ((level - 1)< 8) + level = 4; + I2S->CTRL &= ~ I2S_CTRL_TXTH_MASK; + I2S->CTRL |= (level<CTRL &= ~ I2S_CTRL_CHSEL_MASK; + I2S->CTRL |= channel_sel; +} + +/** + * @brief Enables or disables the specified I2S interrupts + * @param[in] i2s_int_mask specifies the I2S interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * - \ref I2S_INT_MASK_LZC + * - \ref I2S_INT_MASK_RZC + * - \ref I2S_INT_MASK_TXDONE + * - \ref I2S_INT_MASK_TXTH + * - \ref I2S_INT_MASK_TXOV + * - \ref I2S_INT_MASK_TXUD + * - \ref I2S_INT_MASK_RXDONE + * - \ref I2S_INT_MASK_RXTH + * - \ref I2S_INT_MASK_RXOV + * - \ref I2S_INT_MASK_RXUD + * @param[in] enable when set ,enable interrupt, zero disabled + * @retval None + */ +static __inline__ void tls_i2s_int_config(uint32_t i2s_int_mask, uint8_t enable) +{ + if(enable) + { + I2S->INT_MASK &= ~i2s_int_mask; + } + else + { + I2S->INT_MASK |= i2s_int_mask; + } +} + +/** + * @brief Enable master clock (MCLK). + * @param[in] clock The target MCLK clock rate. + * @retval actual MCLK clock rate + * @details Set the master clock rate according to u32BusClock parameter and enable master clock output. + * The actual master clock rate may be different from the target master clock rate. + * The real master clock rate will be returned for reference. + */ +uint32_t tls_i2s_mclk_enable(uint32_t clock); + +/** + * @brief disable master clock (MCLK). + * + */ +void tls_i2s_mclk_disable(void); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /** __WM_I2S_H*/ + + +/*** (C) COPYRIGHT 2014 Winner Microelectronics Co., Ltd. ***/ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_internal_flash.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_internal_flash.h new file mode 100644 index 00000000..7e8309ef --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_internal_flash.h @@ -0,0 +1,234 @@ +/** + * @file wm_internal_flash.h + * + * @brief inter flash driver + * + * @author dave + * + * @copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ + +#ifndef WM_INTERNAL_FLASH_H +#define WM_INTERNAL_FLASH_H + +#include "wm_type_def.h" +#include "wm_osal.h" + +typedef volatile unsigned char vu8; +typedef volatile unsigned short vu16; +typedef volatile unsigned long vu32; + +#define M8(adr) (*((vu8 *) (adr))) +#define M16(adr) (*((vu16*) (adr))) +#define M32(adr) (*((vu32*) (adr))) + +#define INSIDE_FLS_BLOCK_SIZE (0x10000UL) +#define INSIDE_FLS_SECTOR_SIZE (0x1000UL) +#define INSIDE_FLS_PAGE_SIZE 256 + + +#define INSIDE_FLS_BASE_ADDR 0x8000000UL +#define INSIDE_FLS_SECBOOT_ADDR (INSIDE_FLS_BASE_ADDR + 0x02000) + + + +enum TYPE_FLASH_ID{ + SPIFLASH_MID_GD = 0xC8, + SPIFLASH_MID_ESMT = 0x1C, + SPIFLASH_MID_PUYA = 0x85, + SPIFLASH_MID_WINBOND = 0xEF, +}; + + +/** + * @typedef struct Flash Registers + */ +typedef struct +{ + vu32 ACR; /**< offset 0x000 */ + vu32 KEYR; /**< offset 0x004 */ + vu32 SR; /**< offset 0x008 */ + vu32 CR; /**< offset 0x00C */ + vu32 AR; /**< offset 0x010 */ +} FLASH_TypeDef; + +#define FLASH_HS 0x00000001 + + /** Flash Keys */ +#define RDPRT_KEY 0x5AA5 +#define FLASH_KEY1 0x57696E6E +#define FLASH_KEY2 0x65724D69 +#define FLASH_KEY3 0x63726F21 + + /** Flash Control Register definitions */ +#define FLASH_PG 0x00000001 +#define FLASH_PER 0x00000002 +#define FLASH_MER 0x00000004 +#define FLASH_STRT 0x00000008 +#define FLASH_LOCK 0x00000020 +#define FLASH_ERRIE 0x00000040 +#define FLASH_EOPIE 0x00000080 + + /** Flash Status Register definitions */ +#define FLASH_BSY 0x00000001 +#define FLASH_PGERR 0x00000002 +#define FLASH_EOP 0x00000004 + + +#define TLS_FLS_STATUS_OK (0) +#define TLS_FLS_STATUS_EINVAL (1) +#define TLS_FLS_STATUS_EBUSY (2) +#define TLS_FLS_STATUS_EPERM (3) +#define TLS_FLS_STATUS_ENOSUPPORT (4) +#define TLS_FLS_STATUS_EEXIST (5) +#define TLS_FLS_STATUS_ENOMEM (6) +#define TLS_FLS_STATUS_EOVERFLOW (7) +#define TLS_FLS_STATUS_ENODEV (8) +#define TLS_FLS_STATUS_EDEV (9) +#define TLS_FLS_STATUS_EIO (10) +#define TLS_FLS_STATUS_ENODRV (11) + +#define TLS_FLS_PARAM_TYPE_ID (0) +#define TLS_FLS_PARAM_TYPE_SIZE (1) +#define TLS_FLS_PARAM_TYPE_PAGE_SIZE (2) +#define TLS_FLS_PARAM_TYPE_PROG_SIZE (3) +#define TLS_FLS_PARAM_TYPE_SECTOR_SIZE (4) + +#define TLS_FLS_FLAG_UNDER_PROTECT (1<<0) +#define TLS_FLS_FLAG_FAST_READ (1<<1) +#define TLS_FLS_FLAG_AAAI (1<<2) + +/** + * @struct tls_inside_fls + */ +struct tls_inside_fls +{ + tls_os_sem_t *fls_lock; +}; + +/** + * @defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** + * @addtogroup Driver_APIs + * @{ + */ + +/** + * @defgroup INTERNAL_FLASH_Driver_APIs INTERNAL_FLASH Driver APIs + * @brief INTERNAL_FLASH driver APIs + */ + +/** + * @addtogroup INTERNAL_FLASH_Driver_APIs + * @{ + */ + + +/** + * @brief This function is used to unlock flash protect area [0x0~0x2000]. + * + * @param None + * + * @return None + * + * @note None + */ +int tls_flash_unlock(void); + +/** + * @brief This function is used to lock flash protect area [0x0~0x2000]. + * + * @param None + * + * @return None + * + * @note None + */ +int tls_flash_lock(void); + + +/** + * @brief This function is used to get the flash semaphore. + * + * @param None + * + * @return None + * + * @note None + */ +void tls_fls_sem_lock(void); + +/** + * @brief This function is used to release the flash semaphore. + * + * @param None + * + * @return None + * + * @note None + */ +void tls_fls_sem_unlock(void); + + +/** + * @brief This function is used to initial flash module structer. + * + * @param[in] None + * + * @retval TLS_FLS_STATUS_OK if init sucsess + * @retval TLS_FLS_STATUS_EBUSY already inited + * @retval TLS_FLS_STATUS_ENOMEM memory error + * + * @note None + */ +int tls_fls_init(void); + +/** + * @brief This function is used to read data from the flash. + * + * @param[in] addr Specifies the starting address to read from. + * @param[in] buf Specified the address to save the readback data. + * @param[in] len Specifies the length of the data to read. + * + * @retval TLS_FLS_STATUS_OK if read sucsess + * @retval TLS_FLS_STATUS_EIO if read fail + * + * @note None + */ +int tls_fls_read(u32 addr, u8 * buf, u32 len); + + +/** + * @brief This function is used to write data into the flash. + * + * @param[in] addr Specifies the starting address to write to + * @param[in] buf Pointer to a byte array that is to be written + * @param[in] len Specifies the length of the data to be written + * + * @retval TLS_FLS_STATUS_OK if write flash success + * @retval TLS_FLS_STATUS_EPERM if flash struct point is null + * @retval TLS_FLS_STATUS_ENODRV if flash driver is not installed + * @retval TLS_FLS_STATUS_EINVAL if argument is invalid + * @retval TLS_FLS_STATUS_EIO if io error + * + * @note None + */ +int tls_fls_write(u32 addr, u8 * buf, u32 len); + + +/** + * @brief This function is used to erase the appointed sector + * + * @param[in] sector sector num of the flash, 4K bytes every sector + * + * @retval TLS_FLS_STATUS_OK if read sucsess + * @retval other if read fail + * + * @note None + */ +int tls_fls_erase(u32 sector); + +#endif /* WM_INTERNAL_FLASH_H */ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_io.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_io.h new file mode 100644 index 00000000..77558fa4 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_io.h @@ -0,0 +1,196 @@ +/** + * @file wm_io.h + * + * @brief IO Driver Module + * + * @author lilm + * + * @copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ +#ifndef WM_IO_H +#define WM_IO_H + +#include "wm_type_def.h" + +#define TLS_IO_AB_OFFSET (0x40011200 - 0x40010C00) + +/** io name */ +enum tls_io_name { + WM_IO_PA_00 = 0, /**< gpio a0 */ + WM_IO_PA_01, /**< gpio a1 */ + WM_IO_PA_02, /**< gpio a2 */ + WM_IO_PA_03, /**< gpio a3 */ + WM_IO_PA_04, /**< gpio a4 */ + WM_IO_PA_05, /**< gpio a5 */ + WM_IO_PA_06, /**< gpio a6 */ + WM_IO_PA_07, /**< gpio a7 */ + WM_IO_PA_08, /**< gpio a8 */ + WM_IO_PA_09, /**< gpio a9 */ + WM_IO_PA_10, /**< gpio a10 */ + WM_IO_PA_11, /**< gpio a11 */ + WM_IO_PA_12, /**< gpio a12 */ + WM_IO_PA_13, /**< gpio a13 */ + WM_IO_PA_14, /**< gpio a14 */ + WM_IO_PA_15, /**< gpio a15 */ + + WM_IO_PB_00, /**< gpio b0 */ + WM_IO_PB_01, /**< gpio b1 */ + WM_IO_PB_02, /**< gpio b2 */ + WM_IO_PB_03, /**< gpio b3 */ + WM_IO_PB_04, /**< gpio b4 */ + WM_IO_PB_05, /**< gpio b5 */ + WM_IO_PB_06, /**< gpio b6 */ + WM_IO_PB_07, /**< gpio b7 */ + WM_IO_PB_08, /**< gpio b8 */ + WM_IO_PB_09, /**< gpio b9 */ + WM_IO_PB_10, /**< gpio b10 */ + WM_IO_PB_11, /**< gpio b11 */ + WM_IO_PB_12, /**< gpio b12 */ + WM_IO_PB_13, /**< gpio b13 */ + WM_IO_PB_14, /**< gpio b14 */ + WM_IO_PB_15, /**< gpio b15 */ + WM_IO_PB_16, /**< gpio b16 */ + WM_IO_PB_17, /**< gpio b17 */ + WM_IO_PB_18, /**< gpio b18 */ + WM_IO_PB_19, /**< gpio b19 */ + WM_IO_PB_20, /**< gpio b20 */ + WM_IO_PB_21, /**< gpio b21 */ + WM_IO_PB_22, /**< gpio b22 */ + WM_IO_PB_23, /**< gpio b23 */ + WM_IO_PB_24, /**< gpio b24 */ + WM_IO_PB_25, /**< gpio b25 */ + WM_IO_PB_26, /**< gpio b26 */ + WM_IO_PB_27, /**< gpio b27 */ + WM_IO_PB_28, /**< gpio b28 */ + WM_IO_PB_29, /**< gpio b29 */ + WM_IO_PB_30, /**< gpio b30 */ + WM_IO_PB_31 /**< gpio b31 */ +}; + +/** option 1 of the io */ +#define WM_IO_OPTION1 1 +/** option 2 of the io */ +#define WM_IO_OPTION2 2 +/** option 3 of the io */ +#define WM_IO_OPTION3 3 +/** option 4 of the io */ +#define WM_IO_OPTION4 4 +/** option 5 of the io */ +#define WM_IO_OPTION5 5 +/** option 6 of the io */ +#define WM_IO_OPTION6 6 + + +/* io option1 */ +#define WM_IO_OPT1_I2C_DAT WM_IO_OPTION1 +#define WM_IO_OPT1_PWM1 WM_IO_OPTION1 +#define WM_IO_OPT1_PWM2 WM_IO_OPTION1 +#define WM_IO_OPT1_PWM3 WM_IO_OPTION1 +#define WM_IO_OPT1_PWM4 WM_IO_OPTION1 +#define WM_IO_OPT1_PWM5 WM_IO_OPTION1 +#define WM_IO_OPT1_UART0_RXD WM_IO_OPTION1 +#define WM_IO_OPT1_UART0_TXD WM_IO_OPTION1 +#define WM_IO_OPT1_PWM_BRAKE WM_IO_OPTION1 +#define WM_IO_OPT1_I2S_M_EXTCLK WM_IO_OPTION1 +#define WM_IO_OPT1_SPI_M_DO WM_IO_OPTION1 +#define WM_IO_OPT1_SPI_M_DI WM_IO_OPTION1 +#define WM_IO_OPT1_SPI_M_CS WM_IO_OPTION1 +#define WM_IO_OPT1_SPI_M_CK WM_IO_OPTION1 +#define WM_IO_OPT1_I2S_S_RL WM_IO_OPTION1 +#define WM_IO_OPT1_I2S_S_SCL WM_IO_OPTION1 +#define WM_IO_OPT1_I2S_S_SDA WM_IO_OPTION1 +#define WM_IO_OPT1_I2S_M_RL WM_IO_OPTION1 +#define WM_IO_OPT1_I2S_M_SCL WM_IO_OPTION1 +#define WM_IO_OPT1_I2S_M_SDA WM_IO_OPTION1 +#define WM_IO_OPT1_JTAG_RST WM_IO_OPTION1 +#define WM_IO_OPT1_JTAG_TDO WM_IO_OPTION1 +#define WM_IO_OPT1_JTAG_TDI WM_IO_OPTION1 +#define WM_IO_OPT1_JTAG_TCK_SWDCK WM_IO_OPTION1 +#define WM_IO_OPT1_JTAG_TMS_SWDAT WM_IO_OPTION1 +#define WM_IO_OPT1_UART1_RXD WM_IO_OPTION1 +#define WM_IO_OPT1_UART1_TXD WM_IO_OPTION1 +#define WM_IO_OPT1_UART1_RTS WM_IO_OPTION1 +#define WM_IO_OPT1_UART1_CTS WM_IO_OPTION1 +#define WM_IO_OPT1_SDIO_DAT WM_IO_OPTION1 + +/* io option2 */ +#define WM_IO_OPT2_PWM1 WM_IO_OPTION2 +#define WM_IO_OPT2_PWM2 WM_IO_OPTION2 +#define WM_IO_OPT2_PWM3 WM_IO_OPTION2 +#define WM_IO_OPT2_PWM4 WM_IO_OPTION2 +#define WM_IO_OPT2_PWM5 WM_IO_OPTION2 +#define WM_IO_OPT2_SPI_M_DO WM_IO_OPTION2 +#define WM_IO_OPT2_SPI_M_DI WM_IO_OPTION2 +#define WM_IO_OPT2_SPI_M_CS WM_IO_OPTION2 +#define WM_IO_OPT2_SPI_M_CK WM_IO_OPTION2 +#define WM_IO_OPT2_I2C_SCL WM_IO_OPTION2 +#define WM_IO_OPT2_I2S_M_EXTCLK WM_IO_OPTION2 +#define WM_IO_OPT2_UART1_RXD WM_IO_OPTION2 +#define WM_IO_OPT2_UART1_TXD WM_IO_OPTION2 +#define WM_IO_OPT2_UART1_RTS WM_IO_OPTION2 +#define WM_IO_OPT2_UART1_CTS WM_IO_OPTION2 +#define WM_IO_OPT2_I2C_DAT WM_IO_OPTION2 +#define WM_IO_OPT2_PWM_BRAKE WM_IO_OPTION2 +#define WM_IO_OPT2_UART0_RTS WM_IO_OPTION2 +#define WM_IO_OPT2_UART0_CTS WM_IO_OPTION2 +#define WM_IO_OPT2_SDIO_DAT WM_IO_OPTION2 +#define WM_IO_OPT2_HSPI_CK WM_IO_OPTION2 +#define WM_IO_OPT2_HSPI_INT WM_IO_OPTION2 +#define WM_IO_OPT2_HSPI_CS WM_IO_OPTION2 +#define WM_IO_OPT2_HSPI_DI WM_IO_OPTION2 +#define WM_IO_OPT2_HSPI_DO WM_IO_OPTION2 + +/* io option3 */ +#define WM_IO_OPT3_UART0_RXD WM_IO_OPTION3 +#define WM_IO_OPT3_UART0_TXD WM_IO_OPTION3 +#define WM_IO_OPT3_UART0_RTS WM_IO_OPTION3 +#define WM_IO_OPT3_UART0_CTS WM_IO_OPTION3 +#define WM_IO_OPT3_SPI_M_DO WM_IO_OPTION3 +#define WM_IO_OPT3_SPI_M_DI WM_IO_OPTION3 +#define WM_IO_OPT3_SPI_M_CS WM_IO_OPTION3 +#define WM_IO_OPT3_SDIO_CK WM_IO_OPTION3 +#define WM_IO_OPT3_SDIO_CMD WM_IO_OPTION3 +#define WM_IO_OPT3_SDIO_DAT WM_IO_OPTION3 + +/* io option4 */ +#define WM_IO_OPT4_I2S_M_MCLK WM_IO_OPTION4 +#define WM_IO_OPT4_I2S_M_RL WM_IO_OPTION4 +#define WM_IO_OPT4_I2S_M_SCL WM_IO_OPTION4 +#define WM_IO_OPT4_I2S_M_SDA WM_IO_OPTION4 + +/* io option5 */ +#define WM_IO_OPT5_GPIO WM_IO_OPTION5 + +/* io option6 */ +#define WM_IO_OPT6_ADC WM_IO_OPTION6 +#define WM_IO_OPT6_LCD_COM WM_IO_OPTION6 +#define WM_IO_OPT6_LCD_SEG WM_IO_OPTION6 + + +/** + * @brief This function is used to config io function + * + * @param[in] name io name + * @param[in] option io function option, value is WM_IO_OPT*_*, also is WM_IO_OPTION1~6 + * + * @return None + * + * @note None + */ +void tls_io_cfg_set(enum tls_io_name name, u8 option); + + +/** + * @brief This function is used to get io function config + * + * @param[in] name io name + * + * @retval WM_IO_OPTION1~6 Mapping io function + * + * @note None + */ +int tls_io_cfg_get(enum tls_io_name name); + + +#endif /* end of WM_IO_H */ + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_irq.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_irq.h new file mode 100644 index 00000000..f9eb5898 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_irq.h @@ -0,0 +1,163 @@ +/** + * @file wm_irq.h + * + * @brief interupt driver module + * + * @author dave + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ + +#ifndef WM_IRQ_H +#define WM_IRQ_H + +#include "wm_type_def.h" + +/* Number of interrupts. */ + +#define INTR_CNT 41 + +#define SDIO_UP_DATA_INT (0UL) +#define SDIO_DOWN_DATA_INT (1UL) +#define SDIO_UP_CMD_INT (2UL) +#define SDIO_DOWN_CMD_INT (3UL) +#define MAC_INT (4UL) + +#define RX_INT (6UL) +#define TX_MGMT_COMPLETE_INT (7UL) +#define TX_DATA_COMPLETE_INT (8UL) +#define PMU_TIMER1_INT (9UL) +#define PMU_TIMER0_INT (10UL) +#define PMU_GPIO_WAKEUP_INT (11UL) +#define PMU_SDIO_WAKEUP_INT (12UL) +#define DMA0_INT (13UL) +#define DMA1_INT (14UL) +#define DMA2_INT (15UL) +#define DMA3_INT (16UL) +#define DMA4_INT (17UL) +#define DMA_BURST_INT (18UL) +#define I2C_INT (19UL) +#define ADC_INT (20UL) +#define SPI0_INT (21UL) +#define SPI1_INT (22UL) +#define UART0_INT (23UL) +#define UART1_INT (24UL) +#define GPIO_INT (25UL) +#define TIMER0_INT (26UL) +#define TIMER1_INT (27UL) +#define TIMER2_INT (28UL) +#define TIMER3_INT (29UL) +#define TIMER4_INT (30UL) +#define TIMER5_INT (31UL) +#define WATCHDOG_INT (32UL) +#define PMU_BOD_INT (33UL) +#define FLASH_INT (34UL) +#define PWM_INT (35UL) +#define I2S_INT (36UL) +#define PMU_RTC_INT (37UL) +#define RSA_INT (38UL) +#define CRYPTION_INT (39UL) +#define GPIOB_INT (40UL) +#define UART2_INT (41UL) + +typedef void (*intr_handler_func) (void *); + +/** + * @typedef struct tls_irq_handler + */ +typedef struct tls_irq_handler +{ + void (*handler) (void *); + void *data; +// const char *name; + u32 counter; +} tls_irq_handler_t; + +/** + * @defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** + * @addtogroup Driver_APIs + * @{ + */ + +/** + * @defgroup IRQ_Driver_APIs IRQ Driver APIs + * @brief IRQ driver APIs + */ + +/** + * @addtogroup IRQ_Driver_APIs + * @{ + */ + +/** + * @brief This function is used to initial system interrupt. + * + * @param[in] None + * + * @return None + * + * @note None + */ +void tls_irq_init(void); + +/** + * @brief This function is used to register interrupt handler function. + * + * @param[in] vec_no interrupt NO + * @param[in] handler + * @param[in] *data + * + * @return None + * + * @note None + */ +void tls_irq_register_handler(u8 vec_no, intr_handler_func handler, void *data); + + +/** + * @brief This function is used to enable interrupt. + * + * @param[in] vec_no interrupt NO + * + * @return None + * + * @note None + */ +void tls_irq_enable(u8 vec_no); + +/** + * @brief This function is used to disable interrupt. + * + * @param[in] vec_no interrupt NO + * + * @return None + * + * @note None + */ +void tls_irq_disable(u8 vec_no); + + +/** + * @brief This function is used to get the isr count. + * + * @param[in] None + * + * @retval count + * + * @note None + */ +u8 tls_get_isr_count(void); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WM_IRQ_H */ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_lcd.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_lcd.h new file mode 100644 index 00000000..c4792317 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_lcd.h @@ -0,0 +1,245 @@ +/** + * @file wm_lcd.h + * + * @brief LCD Driver Module + * + * @author dave + * + * @copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ + +#ifndef __WM_LCD_H +#define __WM_LCD_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "wm_regs.h" +#include + +/** + * @brief LCD Register Declaration + * + */ +typedef struct +{ + /** Control Register */ + __IO uint32_t CTRL; + /** Refresh Rate Prescaler Register */ + __IO uint32_t FRAMECNT; + /** Data Register */ + __IO uint32_t COM01; + /** Data Register */ + __IO uint32_t COM23; + /** Data Register */ + __IO uint32_t COM45; + /** Data Register */ + __IO uint32_t COM67; + /** LCD IO Control Register */ + __IO uint32_t IO_EN; + +} LCD_T; +/** LCD base pointer */ +#define LCD ((LCD_T *)HR_LCD_REG_BASE) + +typedef enum +{ + /** Static (2 levels) */ + BIAS_STATIC = LCD_BIAS_STATIC, + /** 1/2 Bias (3 levels) */ + BIAS_ONEHALF = LCD_BIAS_ONEHALF, + /** 1/3 Bias (4 levels) */ + BIAS_ONETHIRD = LCD_BIAS_ONETHIRD, + /** 1/4 Bias (4 levels) */ + BIAS_ONEFOURTH = LCD_BIAS_ONEFOURTH, +} LCD_BiasDef; + +typedef enum +{ + /** VLCD 2.7v */ + VLCD27 = LCD_VLCD_27, + /** VLCD 2.9v */ + VLCD29 = LCD_VLCD_29, + /** VLCD 3.1v */ + VLCD31 = LCD_VLCD_31, + /** VLCD 3.3v */ + VLCD33 = LCD_VLCD_33, +} LCD_VlcdDef; + +typedef enum +{ + /** max configuration is 8x16 */ + MODE8x16 = LCD_CR_MODE_8X16, + /** max configuration is 4x20 */ + MODE4x20 = LCD_CR_MODE_4x20, +} LCD_ModeDef; + +typedef enum +{ + /** Static (segments can be multiplexed with LCD_COM[0]) */ + DUTY_STATIC = LCD_DUTY_STATIC, + /** 1/2 Duty cycle (segments can be multiplexed with LCD_COM[0:1]) */ + DUTY_ONEHALF = LCD_DUTY_ONEHALF, + /** 1/3 Duty cycle (segments can be multiplexed with LCD_COM[0:2]) */ + DUTY_ONETHIRD = LCD_DUTY_ONETHIRD, + /** 1/4 Duty cycle (segments can be multiplexed with LCD_COM[0:3]) */ + DUTY_ONEFOURTH = LCD_DUTY_ONEFOURTH, + /** 1/5 Duty cycle (segments can be multiplexed with LCD_COM[0:4]) */ + DUTY_ONEFIFTH = LCD_DUTY_ONEFIFTH, + /** 1/6 Duty cycle (segments can be multiplexed with LCD_COM[0:5]) */ + DUTY_ONESIXTH = LCD_DUTY_ONESIXTH, + /** 1/7 Duty cycle (segments can be multiplexed with LCD_COM[0:6]) */ + DUTY_ONESEVENTH = LCD_DUTY_ONESEVENTH, + /** 1/8 Duty cycle (segments can be multiplexed with LCD_COM[0:7]) */ + DUTY_ONEEIGHTH = LCD_DUTY_ONEEIGHTH, +} LCD_DutyDef; + +typedef struct tls_lcd_options +{ + bool enable; + /** 8x16 or 4x20*/ + LCD_ModeDef mode; + /** Bias configuration */ + LCD_BiasDef bias; + /** Duty configuration */ + LCD_DutyDef duty; + /** Vlcd configuration */ + LCD_VlcdDef vlcd; + /** Fresh rate configuration */ + uint16_t fresh_rate; +} tls_lcd_options_t; + + +/** + * @defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** + * @addtogroup Driver_APIs + * @{ + */ + +/** + * @defgroup LCD_Driver_APIs LCD Driver APIs + * @brief LCD driver APIs + */ + +/** + * @addtogroup LCD_Driver_APIs + * @{ + */ + +/** + * @brief initialize the LCD module + * + */ +void tls_lcd_init(tls_lcd_options_t *opts); + +/** + * @brief Initialize LCD Frame Counter + * @param[in] freq LCD reference refresh frequency in Hz that will be used + * + */ +void tls_lcd_fresh_rate(uint16_t freq); + +/** + * @brief Turn on or clear a segment + * @param[in] com Which COM line to update + * @param[in] bit Bit index of which field to change + * @param[in] enable When one will set segment, when zero will clear segment + * @note Before this function be called, the module must have been intialized + */ +void tls_lcd_seg_set(int com, int bit, int on_off); + +/** + * @brief Select the voltage of LCD module + * @param[in] vlcd This parameter can be one of the following values: + * - \ref VLCD27 + * - \ref VLCD29 + * - \ref VLCD31 + * - \ref VLCD33 + */ +void tls_lcd_vlcd_sel(LCD_VlcdDef vlcd); + +/** + * @brief Set the duty of LCD module + * @param[in] duty This parameter can be one of the following values: + * - \ref DUTY_STATIC + * - \ref DUTY_ONEHALF + * - \ref DUTY_ONETHIRD + * - \ref DUTY_ONEFOURTH + * - \ref DUTY_ONEFIFTH + * - \ref DUTY_ONESIXTH + * - \ref DUTY_ONESEVENTH + * - \ref DUTY_ONEEIGHTH + * + */ +void tls_lcd_duty_set(LCD_DutyDef duty); + +/** + * @brief Set the bias of LCD module + * @param[in] duty This parameter can be one of the following values: + * - \ref BIAS_STATIC + * - \ref BIAS_ONEHALF + * - \ref BIAS_ONETHIRD + * - \ref BIAS_ONEFOURTH + * + */ +void tls_lcd_bias_set(LCD_BiasDef bias); + +/** + * @brief Enable or disable the LCD module gpio + * + * @param[in] the config value per bit for one LCD gpio, set enable gpio output ,clear disabled + * + */ +void tls_lcd_io_config(unsigned int val); + +/** + * @brief Enable or disable clock of LCD module + * @param[in] enable When one enable the clock of LCD module, when zero disable + */ +#define TLS_LCD_CLK_ENABLE(enable) \ + do { \ + tls_bitband_write(HR_CLK_BASE_ADDR, HR_CLK_LCD_GATE_Pos, enable); \ + } while(0) + + +/** + * @brief Enable or disable the LCD module + * @param[in] enable When one enable the LCD module, when zero disable + * + */ +#define TLS_LCD_ENABLE(enable) \ + do { \ + tls_bitband_write(HR_LCD_CR, LCD_CR_EN_Pos, enable); \ + } while(0) + +/** + * @brief Enable or disable the LCD module + * @param[in] enable When one close LCD module, when zero open the LCD module + * + */ +#define TLS_LCD_POWERDOWM(enable) \ + do { \ + tls_bitband_write(HR_LCD_CR, LCD_CR_PD_Pos, enable); \ + } while(0) + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif + + +/*** (C) COPYRIGHT 2014 Winner Microelectronics Co., Ltd. ***/ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_pmu.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_pmu.h new file mode 100644 index 00000000..15abae7f --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_pmu.h @@ -0,0 +1,239 @@ +/** + * @file wm_pmu.h + * + * @brief pmu driver module + * + * @author dave + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#ifndef WM_PMU_H +#define WM_PMU_H +#ifdef __cplusplus +extern "C" { +#endif + +#include "wm_type_def.h" + +typedef void (*tls_pmu_irq_callback)(void *arg); + +/** + * @defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** + * @addtogroup Driver_APIs + * @{ + */ + +/** + * @defgroup PMU_Driver_APIs PMU Driver APIs + * @brief PMU driver APIs + */ + +/** + * @addtogroup PMU_Driver_APIs + * @{ + */ + +/** + * @brief This function is used to register pmu timer1 interrupt + * + * @param[in] callback the pmu timer1 interrupt call back function + * @param[in] arg parameter of call back function + * + * @return None + * + * @note + * user not need clear interrupt flag. + * pmu timer1 callback function is called in interrupt, + * so can not operate the critical data in the callback fuuction, + * recommendation to send messages to other tasks to operate it. + */ +void tls_pmu_timer1_isr_register(tls_pmu_irq_callback callback, void *arg); + + +/** + * @brief This function is used to register pmu timer0 interrupt + * + * @param[in] callback the pmu timer0 interrupt call back function + * @param[in] arg parameter of call back function + * + * @return None + * + * @note + * user not need clear interrupt flag. + * pmu timer0 callback function is called in interrupt, + * so can not operate the critical data in the callback fuuction, + * recommendation to send messages to other tasks to operate it. + */ +void tls_pmu_timer0_isr_register(tls_pmu_irq_callback callback, void *arg); + + +/** + * @brief This function is used to register pmu gpio interrupt + * + * @param[in] callback the pmu gpio interrupt call back function + * @param[in] arg parameter of call back function + * + * @return None + * + * @note + * user not need clear interrupt flag. + * pmu gpio callback function is called in interrupt, + * so can not operate the critical data in the callback fuuction, + * recommendation to send messages to other tasks to operate it. + */ +void tls_pmu_gpio_isr_register(tls_pmu_irq_callback callback, void *arg); + + +/** + * @brief This function is used to register pmu sdio interrupt + * + * @param[in] callback the pmu sdio interrupt call back function + * @param[in] arg parameter of call back function + * + * @return None + * + * @note + * user not need clear interrupt flag. + * pmu sdio callback function is called in interrupt, + * so can not operate the critical data in the callback fuuction, + * recommendation to send messages to other tasks to operate it. + */ +void tls_pmu_sdio_isr_register(tls_pmu_irq_callback callback, void *arg); + + +/** + * @brief This function is used to select pmu clk + * + * @param[in] bypass pmu clk whether or not use bypass mode + * 1 pmu clk use 32K by 40MHZ + * other pmu clk 32K by calibration circuit + * + * @return None + * + * @note None + */ +void tls_pmu_clk_select(u8 bypass); + + +/** + * @brief This function is used to start pmu timer0 + * + * @param[in] second vlaue of timer0 count[s] + * + * @return None + * + * @note None + */ +void tls_pmu_timer0_start(u16 second); + + +/** + * @brief This function is used to stop pmu timer0 + * + * @param None + * + * @return None + * + * @note None + */ +void tls_pmu_timer0_stop(void); + + + +/** + * @brief This function is used to start pmu timer1 + * + * @param[in] second vlaue of timer1 count[ms] + * + * @return None + * + * @note None + */ +void tls_pmu_timer1_start(u16 msec); + + +/** + * @brief This function is used to stop pmu timer1 + * + * @param None + * + * @return None + * + * @note None + */ +void tls_pmu_timer1_stop(void); + + + +/** + * @brief This function is used to start pmu goto standby + * + * @param None + * + * @return None + * + * @note None + */ +void tls_pmu_standby_start(void); + + +typedef enum { + TLS_PERIPHERAL_TYPE_I2C = (1 << 0), + TLS_PERIPHERAL_TYPE_UART0 = (1 << 1), + TLS_PERIPHERAL_TYPE_UART1 = (1 << 2), + TLS_PERIPHERAL_TYPE_LSPI = (1 << 3), + TLS_PERIPHERAL_TYPE_DMA = (1 << 4), + TLS_PERIPHERAL_TYPE_RFCFG = (1 << 5), + TLS_PERIPHERAL_TYPE_TIMER = (1 << 6), + TLS_PERIPHERAL_TYPE_GPIO = (1 << 7), + TLS_PERIPHERAL_TYPE_SDADC = (1 << 8), + TLS_PERIPHERAL_TYPE_PWM = (1 << 9), + TLS_PERIPHERAL_TYPE_LCD = (1 << 10), + TLS_PERIPHERAL_TYPE_I2S = (1 << 11), + TLS_PERIPHERAL_TYPE_RSA = (1 << 12), + TLS_PERIPHERAL_TYPE_GPSEC = (1 << 13), + TLS_PERIPHERAL_TYPE_7816 = (1 << 14) +}tls_peripheral_type_s; + +/** + * @brief This function is used to close peripheral's clock + * + * @param[in] devices peripherals + * + * @return None + * + * @note None + */ +void tls_close_peripheral_clock(tls_peripheral_type_s devices); + +/** + * @brief This function is used to open peripheral's clock + * + * @param[in] devices peripherals + * + * @return None + * + * @note None + */ +void tls_open_peripheral_clock(tls_peripheral_type_s devices); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif +#endif /* end of WM_PMU_H */ + +/*** (C) COPYRIGHT 2014 Winner Microelectronics Co., Ltd. ***/ + + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_pwm.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_pwm.h new file mode 100644 index 00000000..8af99506 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_pwm.h @@ -0,0 +1,400 @@ +/** + * @file wm_pwm.h + * + * @brief pwm driver module + * + * @author dave + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#ifndef WM_PWM_H +#define WM_PWM_H + +#include "wm_type_def.h" + + +/** pwm channel's maximum number */ +#define PWM_CHANNEL_MAX_NUM 5 + +/** pwm work mode for signal generate */ +enum tls_pwm_out_mode +{ + WM_PWM_OUT_MODE_BRAKE = 0, /**< brake mode */ + WM_PWM_OUT_MODE_ALLSYC, /**< all synchronous mode */ + WM_PWM_OUT_MODE_2SYC, /**< two channel synchronous mode */ + WM_PWM_OUT_MODE_MC, /**< complementary mode */ + WM_PWM_OUT_MODE_INDPT /**< independent mode */ +}; + +/** interrupt type for capture mode */ +enum tls_pwm_cap_int_type{ + WM_PWM_CAP_RISING_EDGE_INT, /**< rising edge arises the interrupt */ + WM_PWM_CAP_FALLING_EDGE_INT, /**< falling edge arises the interrupt */ + WM_PWM_CAP_RISING_FALLING_EDGE_INT, /**< both rising edge and falling edge arise the interrupt */ + WM_PWM_CAP_DMA_INT /**< dma request */ +}; + +/** pwm output status */ +enum tls_pwm_out_en_state{ + WM_PWM_OUT_EN_STATE_TRI, /**< set tristate status */ + WM_PWM_OUT_EN_STATE_OUT /**< set output status */ +}; + +/** pwm count mode */ +enum tls_pwm_cnt_type{ + WM_PWM_CNT_TYPE_EDGE_ALLGN_CAP, /**< edge alignment(only capture mode) */ + WM_PWM_CNT_TYPE_EDGE_ALIGN_OUT, /**< edge alignment(only output mode) */ + WM_PWM_CNT_TYPE_CENTER_ALIGN /**< central alignment */ +}; + +/** pwm cycle type */ +enum tls_pwm_loop_type{ + WM_PWM_LOOP_TYPE_SINGLE, /**< single mode */ + WM_PWM_LOOP_TYPE_LOOP /**< auto load */ +}; + +/** pwm waveform inversion mode */ +enum tls_pwm_waveform_inversion{ + WM_PWM_WAVEFORM_NOINVERSION, /**< not inverse */ + WM_PWM_WAVEFORM_INVERSION /**< inversion */ +}; + +/** pwm output level in the brake mode */ +enum tls_pwm_brake_out_level{ + WM_PWM_BRAKE_OUT_HIGH, /**< output high level */ + WM_PWM_BRAKE_OUT_LOW /**< output low level */ +}; + +/** pwm initial parameters */ +typedef struct _pwm_init_param{ + enum tls_pwm_out_mode mode; /**< work mode */ + u8 channel; /**< channel id 0~4 */ + u16 clkdiv; /**< clock divided value */ + u8 period; /**< period value(output frequency F = CLK/CLK_DIV/PERIOD) */ + u8 duty; /**< duty radio (range 0~255, high level or low level by out_inversion decided */ + bool dten; /**< enable dead zone time (ENABLE or DISABLE) */ + u8 dtclkdiv; /**< dead zone clock divided value (0~3) */ + u8 dtcnt; /**< period number of dead zone time (0~255) */ + enum tls_pwm_cnt_type cnt_type; /**< count type */ + enum tls_pwm_loop_type loop_type; /**< cycle type */ + bool inverse_en; /**< output is inverse */ + u8 pnum; /**< generate interrupt after pnum period */ + bool pnum_int; /**< period interrupt is enable */ +}pwm_init_param; + +/** + * @defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** + * @addtogroup Driver_APIs + * @{ + */ + +/** + * @defgroup PWM_Driver_APIs PWM Driver APIs + * @brief PWM driver APIs + */ + +/** + * @addtogroup PWM_Driver_APIs + * @{ + */ + +/** + * @brief This function is used to register the pwm interrupt callback function + * + * @param[in] callback the pwm interrupt callback function + * + * @return None + * + * @note None + */ +void tls_pwm_isr_register(void (*callback)(void)); + +/** + * @brief This function is used to set duty radio + * + * @param[in] channel pwm channel NO.,range form 0 to 4 + * @param[in] duty Number of active levels + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_duty_config(u8 channel, u8 duty); + +/** + * @brief This function is used to set frequency + * + * @param[in] channel pwm channel NO., range form 0 to 4 + * @param[in] clkdiv clock divider, range 0 to 65535 + * @param[in] period the number of the counting clock cycle + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_freq_config(u8 channel, u16 clkdiv, u8 period); + +/** + * @brief This function is used to set the output mode + * + * @param[in] channel pwm channel NO., range form 0 to 4 + * @param[in] mode pwm work mode for signal generate + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_out_mode_config(u8 channel, enum tls_pwm_out_mode mode); + +/** + * @brief This function is used to set the counting mode + * + * @param[in] channel pwm channel NO.,range form 0 to 4 + * @param[in] cnt_type counting mode + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_cnt_type_config(u8 channel, enum tls_pwm_cnt_type cnt_type); + +/** + * @brief This function is used to set whether to loop + * + * @param[in] channel pwm channel NO.,range form 0 to 4 + * @param[in] loop_mode whether to loop + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_loop_mode_config(u8 channel, enum tls_pwm_loop_type loop_mode); + +/** + * @brief This function is used to set whether to inverse the output + + * + * @param[in] channel pwm channel NO.,range form 0 to 4 + * @param[in] en ENABLE or DISABLE + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_out_inverse_cmd(u8 channel, bool en); + +/** + * @brief This function is used to set the number of period to be generated + * + * @param[in] channel pwm channel NO.,range form 0 to 4 + * @param[in] pnum the number of period to be generated,range from 0 to 255 + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_stoptime_by_period_config(u8 channel, u8 pnum); + +/** + * @brief This function is used to set output enable + * + * @param[in] channel pwm channel NO.,channel 0 or channel 4 + * @param[in] en ENABLE or DISABLE + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_output_en_cmd(u8 channel, bool en); + +/** + * @brief This function is used to set the dead time + * + * @param[in] channel pwm channel NO.,channel 0 or channel 2 + * @param[in] dten whether enalbe the deat time, ENABLE or DISABLE + * @param[in] dtclkdiv dead zone clock divider, range 0 to 3 + * @param[in] dtcnt the number of the counting clock cycle, range 0 to 255 + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_deadzone_config(u8 channel, bool dten, u8 dtclkdiv, u8 dtcnt); + +/** + * @brief This function is used to set whether to inverse the capture input + * + * @param[in] channel pwm channel NO.,channel 0 or channel 4 + * @param[in] en ENABLE or DISABLE + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_capture_inverse_cmd(u8 channel, bool en); + +/** + * @brief This function is used to set break mode + * + * @param[in] channel pwm channel NO.,channel 0 or channel 4 + * @param[in] en whether enable the break mode,ENABLE or DISABLE + * @param[in] brok when break + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_brake_mode_config(u8 channel, bool en, enum tls_pwm_brake_out_level brok); + +/** + * @brief This function is used to enable the capture mode + * + * @param[in] channel pwm channel NO.,channel 0 or channel 4 + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_capture_mode_config(u8 channel); + +/** + * @brief This function is used to set the interrupt about the number of period + * + * @param[in] channel pwm channel,range from 0 to 4 + * @param[in] en enble or disable + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_stoptime_irq_cmd(u8 channel, bool en); + +/** + * @brief This function is used to set the interrupt about the + capture + * + * @param[in] channel pwm channel,channel 0 or channel 4 + * @param[in] int_type interrupt type + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_capture_irq_type_config(u8 channel, enum tls_pwm_cap_int_type int_type); + +/** + * @brief This function is used to initial pwm(out mode) + * + * @param[in] pwm_param structure containing the initialization parameters + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_out_init(pwm_init_param pwm_param); + +/** + * @brief This function is used to initial pwm(capture mode) + * + * @param[in] channel pwm channel, channel 0 or channel 4 + * @param[in] clkdiv clock divider, range 0 to 65535 + * @param[in] inverse_en whether the input signal is reversed + * @param[in] int_type interrupt type + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_cap_init(u8 channel, u16 clkdiv, bool inverse_en, enum tls_pwm_cap_int_type int_type); + +/** + * @brief This function is used to start pwm + * + * @param[in] channel pwm channel, range from 0 to 4 + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_start(u8 channel); + +/** + * @brief This function is used to stop pwm + * + * @param[in] channel pwm channel no, range form 0 to 4 + * @param[in] freq frequency, range from 1 to 156250 + * + * @return None + * + * @note None + */ +void tls_pwm_freq_set(u8 channel, u32 freq); + +/** + * @brief This function is used to set duty radio + * + * @param[in] channel pwm channel NO., range form 0 to 4 + * @param[in] duty duty radio, range from 0 to 255 + * + * @return None + * + * @note None + */ +void tls_pwm_duty_set(u8 channel, u8 duty); + +/** + * @brief This function is used to initial pwm + * + * @param[in] channel pwm channel, range from 0 to 4 + * @param[in] freq is a pointer to frequency, freq range from 1 to 156250 + * @param[in] duty is a pointer to duty radio, duty range from 0 to 255 + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_init(u8 channel,u32 freq, u8 duty, u8 pnum); + +/** + * @brief This function is used to stop pwm + * + * @param[in] channel pwm channel, range from 0 to 4 + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_stop(u8 channel); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WM_PWM_H */ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_reflector.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_reflector.h new file mode 100644 index 00000000..44d63811 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_reflector.h @@ -0,0 +1,50 @@ +/** + * @file wm_reflector.h + * + * @brief reflector driver module + * + * @author dave + * + * Copyright (c) 2016 Winner Microelectronics Co., Ltd. + */ + +#ifndef WM_REFLECTOR_H +#define WM_REFLECTOR_H + +#include "wm_type_def.h" + +/** + * @brief This function is used to initial the reflector. + * + * @param[in] ctr_io ctrl io + * + * @return None + * + * @note None + */ +void tls_reflector_open(int ctr_io); + +/** + * @brief This function is used to close the reflector. + * + * @param[in] ctr_io ctrl io + * + * @return None + * + * @note None + */ +void tls_reflector_close(int ctr_io); + +/** + * @brief This function is used to read reflector output status. + * + * @param[in] out_io output io + * + * @retval output status + * + * @note None + */ +int tls_reflector_output_status(int out_io); + +#endif + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_rtc.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_rtc.h new file mode 100644 index 00000000..513f21be --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_rtc.h @@ -0,0 +1,109 @@ +/** + * @file wm_rtc.h + * + * @brief rtc Driver Module + * + * @author dave + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#ifndef WM_RTC_H +#define WM_RTC_H + +#include +#include "wm_type_def.h" + +/** rtc interrupt callback */ +typedef void (*tls_rtc_irq_callback)(void *arg); + +/** + * @defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** + * @addtogroup Driver_APIs + * @{ + */ + +/** + * @defgroup RTC_Driver_APIs RTC Driver APIs + * @brief RTC driver APIs + */ + +/** + * @addtogroup RTC_Driver_APIs + * @{ + */ + +/** + * @brief This function is used to set pmu rtc time + * + * @param[in] tblock time value + * + * @return None + * + * @note None + */ +void tls_set_rtc(struct tm *tblock); + +/** + * @brief This function is used to get pmu rtc time + * + * @param[out] tblock time value + * + * @return None + * + * @note None + */ +void tls_get_rtc(struct tm *tblock); + +/** + * @brief This function is used to register pmu rtc interrupt + * + * @param[in] callback the rtc interrupt call back function + * @param[in] arg parameter of call back function + * + * @return None + * + * @note + * User does not need to clear the interrupt flag. + * Rtc callback function is called in interrupt, + * so do not operate the critical data in the callback fuuction. + * Sending messages to other tasks to handle is recommended. + */ +void tls_rtc_isr_register(tls_rtc_irq_callback callback, void *arg); + +/** + * @brief This function is used to start pmu rtc timer + * + * @param[in] tblock timer value + * + * @return None + * + * @note None + */ +void tls_rtc_timer_start(struct tm *tblock); + +/** + * @brief This function is used to stop pmu rtc timer + * + * @param None + * + * @return None + * + * @note This function also is used to clear rtc timer interrupt + */ +void tls_rtc_timer_stop(void); + + +/** + * @} + */ + +/** + * @} + */ + +#endif + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_spi_hal.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_spi_hal.h new file mode 100644 index 00000000..2672151f --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_spi_hal.h @@ -0,0 +1,295 @@ +/***************************************************************************** +* +* File Name : wm_spi_hal.h +* +* Description: host spi Driver Module +* +* Copyright (c) 2014 Winner Microelectronics Co., Ltd. +* All rights reserved. +* +* Author : dave +* +* Date : 2014-6-6 +*****************************************************************************/ +#include "wm_regs.h" +#include "list.h" +#include "wm_hostspi.h" +#include "wm_cpu.h" + + +static __inline void spi_set_mode(u8 mode); + + +static __inline void spi_set_mode(u8 mode) +{ + u32 reg_val; + + reg_val = tls_reg_read32(HR_SPI_SPICFG_REG); + + switch (mode) { + case TLS_SPI_MODE_0: + reg_val &= ~(0x03U); + reg_val |= (SPI_SET_CPOL(0) | SPI_SET_CPHA(0)); + break; + + case TLS_SPI_MODE_1: + reg_val &= ~(0x03U); + reg_val |= (SPI_SET_CPOL(0) | SPI_SET_CPHA(1)); + break; + + case TLS_SPI_MODE_2: + reg_val &= ~(0x03U); + reg_val |= (SPI_SET_CPOL(1) | SPI_SET_CPHA(0)); + break; + + case TLS_SPI_MODE_3: + reg_val &= ~(0x03U); + reg_val |= (SPI_SET_CPOL(1) | SPI_SET_CPHA(1)); + break; + + default: + break; + } + + tls_reg_write32(HR_SPI_SPICFG_REG, reg_val); +} + +static __inline void spi_set_endian(u8 endian) +{ + u32 reg_val; + + reg_val = tls_reg_read32(HR_SPI_SPICFG_REG); + + if (endian == 0) { + reg_val &= ~(0x01U << 3); + reg_val |= SPI_LITTLE_ENDIAN; + } else if(endian == 1) { + reg_val &= ~(0x01U << 3); + reg_val |= SPI_BIG_ENDIAN; + } + + tls_reg_write32(HR_SPI_SPICFG_REG, reg_val); +} + +static __inline void spi_set_chipselect_mode(u8 cs_active) +{ + u32 reg_val; + + reg_val = tls_reg_read32(HR_SPI_CHCFG_REG); + + if (cs_active == 0) { + reg_val &= ~(0x01U << 2); + reg_val |= SPI_CS_LOW; + } else if(cs_active == 1) { + reg_val &= ~(0x01U << 2); + reg_val |= SPI_CS_HIGH; + } + + tls_reg_write32(HR_SPI_CHCFG_REG, reg_val); +} + +static __inline void spi_clear_fifo(void) +{ + u32 reg_val; + + reg_val = tls_reg_read32(HR_SPI_CHCFG_REG); + + reg_val |= SPI_CLEAR_FIFOS; + + tls_reg_write32(HR_SPI_CHCFG_REG, reg_val); +} + +static __inline void spi_set_rx_channel(u8 on_off) +{ + u32 reg_val; + + reg_val = tls_reg_read32(HR_SPI_CHCFG_REG); + + if (on_off == 0) { + reg_val &= ~(0x01U << 20); + reg_val |= SPI_RX_CHANNEL_OFF; + } else if(on_off == 1) { + reg_val &= ~(0x01U << 20); + reg_val |= SPI_RX_CHANNEL_ON; + } + + tls_reg_write32(HR_SPI_CHCFG_REG, reg_val); +} + +static __inline void spi_set_tx_channel(u8 on_off) +{ + u32 reg_val; + + reg_val = tls_reg_read32(HR_SPI_CHCFG_REG); + + if (on_off == 0) { + reg_val &= ~(0x01U << 19); + reg_val |= SPI_TX_CHANNEL_OFF; + } else if(on_off == 1) { + reg_val &= ~(0x01U << 19); + reg_val |= SPI_TX_CHANNEL_ON; + } + + tls_reg_write32(HR_SPI_CHCFG_REG, reg_val); +} + +static __inline void spi_set_sclk_length(u16 sclk_num, u8 invalid_rx_sclk_num) +{ + u32 reg_val; + + reg_val = tls_reg_read32(HR_SPI_CHCFG_REG); + + reg_val &= ~((0xffU << 23) | (0xffff << 3)); + reg_val |= SPI_VALID_CLKS_NUM(sclk_num) | SPI_RX_INVALID_BITS(invalid_rx_sclk_num); + + tls_reg_write32(HR_SPI_CHCFG_REG, reg_val); +} + +static __inline void spi_force_cs_out(u8 enable) +{ + u32 reg_val; + + reg_val = tls_reg_read32(HR_SPI_CHCFG_REG); + + if (enable) { + reg_val |= SPI_FORCE_SPI_CS_OUT; + } else { + reg_val &= ~SPI_FORCE_SPI_CS_OUT; + } + + tls_reg_write32(HR_SPI_CHCFG_REG, reg_val); +} + +static __inline void spi_sclk_start(void) +{ + u32 reg_val; + + reg_val = tls_reg_read32(HR_SPI_CHCFG_REG); + + reg_val |= SPI_START; + + tls_reg_write32(HR_SPI_CHCFG_REG, reg_val); +} + +static __inline void spi_set_sclk(u32 fclk) +{ + u32 reg_val; + tls_sys_clk sysclk; + + tls_sys_clk_get(&sysclk); + + reg_val = tls_reg_read32(HR_SPI_CLKCFG_REG); + + reg_val &= ~(0xffffU); + reg_val |= sysclk.apbclk*UNIT_MHZ/(fclk*2) - 1; + + tls_reg_write32(HR_SPI_CLKCFG_REG, reg_val); +} + +static __inline void spi_set_tx_trigger_level(u8 level) +{ + u32 reg_val; + + reg_val = tls_reg_read32(HR_SPI_MODECFG_REG); + + reg_val &= ~(0x07U << 2); + reg_val |= SPI_TX_TRIGGER_LEVEL(level); + + tls_reg_write32(HR_SPI_MODECFG_REG, reg_val); +} + +static __inline void spi_set_rx_trigger_level(u8 level) +{ + u32 reg_val; + + reg_val = tls_reg_read32(HR_SPI_MODECFG_REG); + + reg_val &= ~(0x07U << 6); + reg_val |= SPI_RX_TRIGGER_LEVEL(level); + + tls_reg_write32(HR_SPI_MODECFG_REG, reg_val); +} + +static __inline void spi_set_timeout(u32 timeout, u8 enable) +{ + u32 reg_val; + + reg_val = SPI_TIME_OUT(timeout); + reg_val |= enable ? SPI_TIMER_EN : 0; + + tls_reg_write32(HR_SPI_TIMEOUT_REG, reg_val); +} + +static __inline void spi_get_status(u8 *busy, u8 *rx_fifo_level, u8 *tx_fifo_level) +{ + u32 reg_val; + + reg_val = tls_reg_read32(HR_SPI_STATUS_REG); + + if (busy) {*busy = SPI_IS_BUSY(reg_val);} + if (rx_fifo_level) {*rx_fifo_level = SPI_GET_RX_FIFO_CNT(reg_val);} + if (tx_fifo_level) {*tx_fifo_level = 32 - SPI_GET_TX_FIFO_CNT(reg_val);} +} + +static __inline u32 spi_int_mask(void) +{ + u32 reg_val; + + reg_val = tls_reg_read32(HR_SPI_INT_MASK_REG); + + return reg_val & SPI_INT_MASK_ALL; +} + +static __inline void spi_mask_int(u32 mask) +{ + u32 reg_val; + + reg_val = tls_reg_read32(HR_SPI_INT_MASK_REG); + + reg_val |= mask & SPI_INT_MASK_ALL; + + tls_reg_write32(HR_SPI_INT_MASK_REG, reg_val); +} + +static __inline void spi_unmask_int(u32 mask) +{ + u32 reg_val; + + reg_val = tls_reg_read32(HR_SPI_INT_MASK_REG); + + reg_val &= ~(mask & SPI_INT_MASK_ALL); + + tls_reg_write32(HR_SPI_INT_MASK_REG, reg_val); +} + +static __inline u32 spi_get_int_status(void) +{ + u32 reg_val; + + reg_val = tls_reg_read32(HR_SPI_INT_STATUS_REG); + + return reg_val; +} + +static __inline void spi_clear_int_status(u32 int_srcs) +{ + u32 reg_val; + + reg_val = tls_reg_read32(HR_SPI_INT_STATUS_REG); + + reg_val &= ~(int_srcs & SPI_INT_CLEAR_ALL); + reg_val |= int_srcs & SPI_INT_CLEAR_ALL; + + tls_reg_write32(HR_SPI_INT_STATUS_REG, reg_val); +} + +static __inline void spi_data_put(u32 data) +{ + tls_reg_write32(HR_SPI_TXDATA_REG, data); +} + +static __inline u32 spi_data_get(void) +{ + return tls_reg_read32(HR_SPI_RXDATA_REG); +} + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_timer.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_timer.h new file mode 100644 index 00000000..aefd3491 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_timer.h @@ -0,0 +1,141 @@ +/** + * @file wm_timer.h + * + * @brief Timer Driver Module + * + * @author dave + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#ifndef WM_TIMER_H +#define WM_TIMER_H + +#include "wm_type_def.h" + +/** invalid timer id */ +#define WM_TIMER_ID_INVALID 0xFF +#define TIMER_MS_UNIT_FLAG 1 +#define TIMER_US_UNIT_FLAG 0 + +/** timer interrupt callback */ +typedef void (*tls_timer_irq_callback)(void *arg); + +/** timer unit */ +enum tls_timer_unit{ + TLS_TIMER_UNIT_US = 0, /**< microsecond level(us) */ + TLS_TIMER_UNIT_MS /**< millisecond level(ms) */ +}; + +/** timer configuration */ +struct tls_timer_cfg { + enum tls_timer_unit unit; /**< timer accuracy */ + u32 timeout; /**< timeout period */ + bool is_repeat; /**< cycle timer */ + tls_timer_irq_callback callback; /**< timeout callback function */ + void *arg; /**< parameter fot the timeout callback function */ +}; + +/** + * @defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** + * @addtogroup Driver_APIs + * @{ + */ + +/** + * @defgroup TIMER_Driver_APIs TIMER Driver APIs + * @brief TIMER driver APIs + */ + +/** + * @addtogroup TIMER_Driver_APIs + * @{ + */ + +/** + * @brief This function is used to create a timer + * + * @param[in] cfg timer configuration + * + * @retval WM_TIMER_ID_INVALID failed + * @retval other timer id + * + * @note + * User does not need to clear the interrupt flag. + * Rtc callback function is called in interrupt, + * so do not operate the critical data in the callback fuuction. + * Sending messages to other tasks to handle is recommended. + */ +u8 tls_timer_create(struct tls_timer_cfg *cfg); + +/** + * @brief This function is used to start a timer + * + * @param[in] timer_id timer id + * + * @return None + * + * @note None + */ +void tls_timer_start(u8 timer_id); + +/** + * @brief This function is used to stop a timer + * + * @param[in] timer_id timer id + * + * @return None + * + * @note None + */ +void tls_timer_stop(u8 timer_id); + +/** + * @brief This function is used to change a timer wait time + * + * @param[in] timer_id timer id[0~5] + * + * @param[in] newtime new wait time + * + * @retval None + * + * @note If the timer does not start, this function will start the timer + */ +void tls_timer_change(u8 timer_id, u32 newtime); + +/** + * @brief This function is used to delete a timer + * + * @param[in] timer_id timer id + * + * @return None + * + * @note None + */ +void tls_timer_destroy(u8 timer_id); + +/** + * @brief This function is create a delay to elapse + * + * @param[timeout] timeout the value writed into TMR0_PRD + * @param[in] m_flag millisecond flag in TIMER0 + * + * @return None + * + * @note None + */ +int tls_delay_via_timer(unsigned int timeout, unsigned int m_flag); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WM_TIMER_H */ + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_uart.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_uart.h new file mode 100644 index 00000000..1d435bd8 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_uart.h @@ -0,0 +1,451 @@ +/** + * @file wm_uart.h + * + * @brief uart Driver Module + * + * @author dave + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ +#ifndef WM_UART_H +#define WM_UART_H +#include "list.h" +//#include "wm_regs.h" +#include "wm_type_def.h" +//#include "wm_osal.h" + +#define TLS_UART_RX_BUF_SIZE 4096 +#define TLS_UART_TX_BUF_SIZE 4096 +#define WAKEUP_CHARS 256 + +#define MBOX_MSG_UART_RX 1 +#define MBOX_MSG_UART_TX 2 + + +/** baud rate definition */ +#define UART_BAUDRATE_B600 600 +#define UART_BAUDRATE_B1200 1200 +#define UART_BAUDRATE_B1800 1800 +#define UART_BAUDRATE_B2400 2400 +#define UART_BAUDRATE_B4800 4800 +#define UART_BAUDRATE_B9600 9600 +#define UART_BAUDRATE_B19200 19200 +#define UART_BAUDRATE_B38400 38400 +#define UART_BAUDRATE_B57600 57600 +#define UART_BAUDRATE_B115200 115200 +#define UART_BAUDRATE_B230400 230400 +#define UART_BAUDRATE_B460800 460800 +#define UART_BAUDRATE_B921600 921600 +#define UART_BAUDRATE_B1000000 1000000 +#define UART_BAUDRATE_B1250000 1250000 +#define UART_BAUDRATE_B1500000 1500000 +#define UART_BAUDRATE_B2000000 2000000 + +#define UART_RX_INT_FLAG (UIS_RX_FIFO | UIS_RX_FIFO_TIMEOUT | UIS_BREAK |\ + UIS_OVERRUN | UIS_FRM_ERR | UIS_PARITY_ERR) +#define UART_RX_ERR_INT_FLAG (UIS_BREAK | UIS_FRM_ERR | \ + UIS_PARITY_ERR) + +#define UART_TX_INT_FLAG (UIS_TX_FIFO | UIS_TX_FIFO_EMPTY) + + +#ifndef UART0_INT +#define UART0_INT (23UL) +#endif +#ifndef UART1_INT +#define UART1_INT (24UL) +#endif + +/** return count in buffer. */ +#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1)) + +/** Return space available, 0..size-1. We always leave one free char + as a completely full buffer has head == tail, which is the same as + empty. */ +#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size)) + +/** Return count up to the end of the buffer. Carefully avoid + accessing head and tail more than once, so they can change + underneath us without returning inconsistent results. */ +#define CIRC_CNT_TO_END(head,tail,size) \ + ({int end = (size) - (tail); \ + int n = ((head) + end) & ((size)-1); \ + n < end ? n : end;}) + +/** Return space available up to the end of the buffer. */ +#define CIRC_SPACE_TO_END(head,tail,size) \ + ({int end = (size) - 1 - (head); \ + int n = (end + (tail)) & ((size)-1); \ + n <= end ? n : end+1;}) + +#define CIRC_SPACE_TO_END_FULL(head,tail,size) \ + ({int end = (size) - 1 - (head); \ + int n = (end + (tail)) & ((size)-1); \ + n < end ? n : end+1;}) + +#define uart_circ_empty(circ) ((circ)->head == (circ)->tail) +#define uart_circ_chars_pending(circ) \ + (CIRC_CNT((circ)->head, (circ)->tail, TLS_UART_TX_BUF_SIZE)) + +/** + * @struct tls_uart_baud_rate baudrate define + */ +struct tls_uart_baud_rate +{ + u32 baud_rate; + u16 ubdiv; + u16 ubdiv_frac; +}; + + +/** + * @enum uart number enum + */ +enum +{ + TLS_UART_0 = 0, + TLS_UART_1 = 1, + TLS_UART_2 = 2, +}; + + +/** + * @typedef enum TLS_UART_PMODE Parity Mode + */ +typedef enum TLS_UART_PMODE +{ + TLS_UART_PMODE_DISABLED = 0, /**< No Parity */ + TLS_UART_PMODE_ODD = 1, /**< Odd Parity */ + TLS_UART_PMODE_EVEN = 2, /**< Even Parity */ + TLS_UART_PMODE_MARK = 3, /**< The parity bit is always 1. */ + TLS_UART_PMODE_SPACE = 4, /**< The parity bit is always 0. */ +} TLS_UART_PMODE_T; + +/** + * @typedef enum TLS_UART_CHSIZE Character Size + */ +typedef enum TLS_UART_CHSIZE +{ + TLS_UART_CHSIZE_5BIT = (0x00 << 0), /**< Character size: 5 bit */ + TLS_UART_CHSIZE_6BIT = (0x01 << 0), /**< Character size: 6 bit */ + TLS_UART_CHSIZE_7BIT = (0x02 << 0), /**< Character size: 7 bit */ + TLS_UART_CHSIZE_8BIT = (0x03 << 0), /**< Character size: 8 bit */ +} TLS_UART_CHSIZE_T; + +/** + * @typedef enum TLS_UART_FLOW_CTRL_MODE flow control mode + */ +typedef enum TLS_UART_FLOW_CTRL_MODE +{ + TLS_UART_FLOW_CTRL_NONE, + TLS_UART_FLOW_CTRL_HARDWARE, +} TLS_UART_FLOW_CTRL_MODE_T; + +/** + * @typedef enum TLS_UART_RX_FLOW_CTRL_FLAG flow control rx flag + */ +typedef enum TLS_UART_RX_FLOW_CTRL_FLAG +{ + TLS_UART_RX_DISABLE, + TLS_UART_RX_ENABLE, +} TLS_UART_RX_FLOW_CTRL_FLAG_T; + +/** + * @typedef enum TLS_UART_STOPBITS + */ +typedef enum TLS_UART_STOPBITS +{ + TLS_UART_ONE_STOPBITS, + TLS_UART_TWO_STOPBITS, +} TLS_UART_STOPBITS_T; + + +/** + * @typedef enum TLS_UART_STATUS + */ +typedef enum TLS_UART_STATUS +{ + TLS_UART_STATUS_OK, + TLS_UART_STATUS_ERROR, +} TLS_UART_STATUS_T; + + +/** + * @typedef enum TLS_UART_MODE operation mode + */ +typedef enum TLS_UART_MODE +{ + TLS_UART_MODE_POLL, /**< uart operation mode: poll */ + TLS_UART_MODE_INT, /**< uart operation mode: interrupt mode */ +} TLS_UART_MODE_T; + +/** + * @struct tls_uart_icount + */ +struct tls_uart_icount +{ + u32 cts; + u32 dsr; + u32 rng; + u32 dcd; + u32 rx; + u32 tx; + u32 frame; + u32 overrun; + u32 parity; + u32 brk; + u32 buf_overrun; +}; + + + +/** + * @typedef struct tls_uart_options + */ +typedef struct tls_uart_options +{ + u32 baudrate; /**< Set baud rate of the UART */ + + TLS_UART_CHSIZE_T charlength; /**< Number of bits to transmit as a character (5 to 8). */ + + TLS_UART_PMODE_T paritytype; /**< Parity type */ + + TLS_UART_FLOW_CTRL_MODE_T flow_ctrl; /**< Flow control type */ + + TLS_UART_STOPBITS_T stopbits; /**< Number of stop bits */ + +} tls_uart_options_t; + + +/** + * @typedef struct tls_uart_circ_buf + */ +typedef struct tls_uart_circ_buf +{ + u8 *buf; + u32 head; + u32 tail; +} tls_uart_circ_buf_t; + +/** + * @typedef struct TLS_UART_REGS + */ +typedef struct TLS_UART_REGS +{ + u32 UR_LC; /**< line control register */ + u32 UR_FC; /**< flow control register */ + u32 UR_DMAC; /**< dma control register */ + u32 UR_FIFOC; /**< fifo control register */ + u32 UR_BD; /**< baud rate register */ + u32 UR_INTM; /**< interrupt mask register */ + u32 UR_INTS; /**< interrupt source register */ + u32 UR_FIFOS; /**< fifo status register */ + u32 UR_TXW; /**< tx windows register */ + u32 UR_RES0; + u32 UR_RES1; + u32 UR_RES2; + u32 UR_RXW; /**< rx windows register */ +} TLS_UART_REGS_T; + + +/** + * @typedef struct tls_uart_port + */ +typedef struct tls_uart_port +{ + u32 uart_no; /**< uart number: 0 or 1 */ + + u32 uart_irq_no; /**< uart interrupt number */ + + u32 plus_char_cnt; + + TLS_UART_MODE_T uart_mode; /**< uart work mode: interrupt mode or poll mode */ + + struct tls_uart_options opts; /**< uart config parameters */ + + int fcStatus; /**< flow ctrl status,0 closed ,1 opened */ + + enum TLS_UART_RX_FLOW_CTRL_FLAG rxstatus; + + u32 tx_fifofull; /**< uart tx fifo trigger level */ + + TLS_UART_REGS_T volatile *regs; /**< uart registers struct pointer */ + + struct tls_uart_icount icount; /**< uart statistics information */ + + struct tls_uart_circ_buf recv; /**< uart ring buffer */ + +// struct tls_uart_circ_buf xmit; + + struct dl_list tx_msg_pending_list; + + struct dl_list tx_msg_to_be_freed_list; + + u8 hw_stopped; + + //tls_os_sem_t *tx_sem; + + char *buf_ptr; + + u16 buf_len; + + s16(*rx_callback) (u16 len); + + s16(*tx_callback) (struct tls_uart_port * port); + + bool tx_dma_on; +} tls_uart_port_t; + +/** + * @typedef struct tls_uart_tx_msg + */ +typedef struct tls_uart_tx_msg +{ + struct dl_list list; + char *buf; + u16 buflen; + u16 offset; + void (*finish_callback) (void *arg); + void *callback_arg; +} tls_uart_tx_msg_t; + +/** + * @defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** + * @addtogroup Driver_APIs + * @{ + */ + +/** + * @defgroup UART_Driver_APIs UART Driver APIs + * @brief UART driver APIs + */ + +/** + * @addtogroup UART_Driver_APIs + * @{ + */ + +/** + * @brief This function is used to initial uart port. + * + * @param[in] uart_no is the uart number. TLS_UART_0 or TLS_UART_1 + * @param[in] opts is the uart setting options,if this param is NULL,this function will use the default options. + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note When the system is initialized, the function has been called, so users can not call the function. + */ +int tls_uart_port_init(u16 uart_no, tls_uart_options_t * opts, u8 modeChoose); + + +/** + * @brief This function is used to register uart rx interrupt. + * + * @param[in] uart_no TLS_UART_0 or TLS_UART_1 + * @param[in] rx_callback is the uart rx interrupt call back function. + * + * @return None + * + * @note None + */ +void tls_uart_rx_callback_register(u16 uart_no, s16(*rx_callback) (u16 len)); + + +/** + * @brief This function is used to copy circular buffer data to user buffer. + * + * @param[in] uart_no is the uart numer + * @param[in] buf is the user buffer + * @param[in] readsize is the user read size + * + * @retval copy data size + * + * @note None + */ +int tls_uart_read(u16 uart_no, u8 * buf, u16 readsize); + + +/** + * @brief This function is used to transfer data synchronously. + * + * @param[in] uart_no is the uart number + * @param[in] buf is a buf for saving user data + * @param[in] writesize is the user data length + * + * @retval WM_SUCCESS tx success + * @retval WM_FAILED tx failed + * + * @note None + */ +int tls_uart_write(u16 uart_no, char *buf, u16 writesize); + + +/** + * @brief This function is used to transfer data with DMA. + * + * @param[in] buf is a buf for saving user data + * @param[in] writesize is the user data length + * @param[in] cmpl_callback function point,when the transfer is completed, the function will be called. + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note Only uart1 support DMA transfer. + */ +int tls_uart_dma_write(char *buf, u16 writesize, void (*cmpl_callback) (void *p), u16 uart_no); + + +/** + * @brief This function is used to set uart parity. + * + * @param[in] uart_no is the uart number + * @param[in] paritytype is a parity type defined in TLS_UART_PMODE_T + * + * @retval WM_SUCCESS if setting success + * @retval WM_FAILED if setting fail + * + * @note None + */ +int tls_uart_set_parity(u16 uart_no, TLS_UART_PMODE_T paritytype); + + +/** + * @brief This function is used to set uart baudrate. + * + * @param[in] uart_no is the uart number + * @param[in] baudrate is the baudrate user want used,the unit is HZ. + * + * @retval WM_SUCCESS if setting success + * @retval WM_FAILED if setting fail + * + * @note None + */ +int tls_uart_set_baud_rate(u16 uart_no, u32 baudrate); + +/** + * @brief This function is used to set uart stop bits. + * + * @param[in] uart_no is the uart number + * @param[in] stopbits is a stop bit type defined in TLS_UART_STOPBITS_T + * + * @retval WM_SUCCESS if setting success + * @retval WM_FAILED if setting fail + * + * @note None + */ +int tls_uart_set_stop_bits(u16 uart_no, TLS_UART_STOPBITS_T stopbits); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WM_UART_H */ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_uart_new.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_uart_new.h new file mode 100644 index 00000000..f6ec8f18 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_uart_new.h @@ -0,0 +1,297 @@ +/* + * ESPRSSIF MIT License + * + * Copyright (c) 2015 + * + * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case, + * it is free of charge, to any person obtaining a copy of this software and associated + * documentation files (the "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the Software is furnished + * to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __UART_H__ +#define __UART_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define ETS_UART_INTR_ENABLE() _xt_isr_unmask(1 << ETS_UART_INUM) +#define ETS_UART_INTR_DISABLE() _xt_isr_mask(1 << ETS_UART_INUM) +#define UART_INTR_MASK 0x1ff +#define UART_LINE_INV_MASK (0x3f<<19) + +typedef enum { + UART_WordLength_5b = 0x0, + UART_WordLength_6b = 0x1, + UART_WordLength_7b = 0x2, + UART_WordLength_8b = 0x3 +} UART_WordLength; + +typedef enum { + USART_StopBits_1 = 0x0, + USART_StopBits_2 = 0x1, +} UART_StopBits; + +typedef enum { + UART0 = 0x0, + UART1 = 0x1, +} UART_Port; + +typedef enum { + USART_Parity_None = 0x2, + USART_Parity_Even = 0x0, + USART_Parity_Odd = 0x1 +} UART_ParityMode; + +typedef enum { + PARITY_DIS = 0x0, + PARITY_EN = 0x2 +} UartExistParity; + +typedef enum { + BIT_RATE_300 = 300, + BIT_RATE_600 = 600, + BIT_RATE_1200 = 1200, + BIT_RATE_2400 = 2400, + BIT_RATE_4800 = 4800, + BIT_RATE_9600 = 9600, + BIT_RATE_19200 = 19200, + BIT_RATE_38400 = 38400, + BIT_RATE_57600 = 57600, + BIT_RATE_74880 = 74880, + BIT_RATE_115200 = 115200, + BIT_RATE_230400 = 230400, + BIT_RATE_460800 = 460800, + BIT_RATE_921600 = 921600, + BIT_RATE_1843200 = 1843200, + BIT_RATE_3686400 = 3686400, +} UART_BautRate; //you can add any rate you need in this range + +typedef enum { + USART_HardwareFlowControl_None = 0x0, + USART_HardwareFlowControl_RTS = 0x1, + USART_HardwareFlowControl_CTS = 0x2, + USART_HardwareFlowControl_CTS_RTS = 0x3 +} UART_HwFlowCtrl; + +//typedef enum { +// UART_None_Inverse = 0x0, +// UART_Rxd_Inverse = UART_RXD_INV, +// UART_CTS_Inverse = UART_CTS_INV, +// UART_Txd_Inverse = UART_TXD_INV, +// UART_RTS_Inverse = UART_RTS_INV, +//} UART_LineLevelInverse; + +typedef struct { + UART_BautRate baud_rate; + UART_WordLength data_bits; + UART_ParityMode parity; // chip size in byte + UART_StopBits stop_bits; + UART_HwFlowCtrl flow_ctrl; + u8 UART_RxFlowThresh ; +// u32 UART_InverseMask; +} UART_ConfigTypeDef; + +typedef struct { + u32 UART_IntrEnMask; + u8 UART_RX_TimeOutIntrThresh; + u8 UART_TX_FifoEmptyIntrThresh; //txfifo trigger level + u8 UART_RX_FifoFullIntrThresh; //rxfifo trigger level +} UART_IntrConfTypeDef; + +//======================================= + +/** \defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** @addtogroup Driver_APIs + * @{ + */ + +/** \defgroup UART_Driver_APIs UART Driver APIs + * @brief UART driver APIs + */ + +/** @addtogroup UART_Driver_APIs + * @{ + */ + +/** + * @brief Wait uart tx fifo empty, do not use it if tx flow control enabled. + * + * @param UART_Port uart_no:UART0 or UART1 + * + * @return null + */ +void UART_WaitTxFifoEmpty(UART_Port uart_no); //do not use if tx flow control enabled + +/** + * @brief Clear uart tx fifo and rx fifo. + * + * @param UART_Port uart_no : UART0 or UART1 + * + * @return null + */ +void UART_ResetFifo(UART_Port uart_no); + +/** + * @brief Clear uart interrupt flags. + * + * @param UART_Port uart_no : UART0 or UART1 + * @param u32 clr_mask : To clear the interrupt bits + * + * @return null + */ +void UART_ClearIntrStatus(UART_Port uart_no, u32 clr_mask); + +/** + * @brief Enable uart interrupts . + * + * @param UART_Port uart_no : UART0 or UART1 + * @param u32 ena_mask : To enable the interrupt bits + * + * @return null + */ +void UART_SetIntrEna(UART_Port uart_no, u32 ena_mask); + +/** + * @brief Register an application-specific interrupt handler for Uarts interrupts. + * + + * @param UART_Port uart_no : UART0 or UART1 + * @param void *fn : interrupt handler for Uart interrupts. + * @param void *arg : interrupt handler's arg. + * + * @return null + */ +void UART_intr_handler_register(UART_Port uart_no, void *fn, void *arg); + +/** + * @brief Config from which serial output printf function. + * + * @param UART_Port uart_no : UART0 or UART1 + * + * @return null + */ +void UART_SetPrintPort(UART_Port uart_no); + +/** + * @brief Config Common parameters of serial ports. + * + * @param UART_Port uart_no : UART0 or UART1 + * @param UART_ConfigTypeDef *pUARTConfig : parameters structure + * + * @return null + */ +void UART_ParamConfig(UART_Port uart_no, UART_ConfigTypeDef *pUARTConfig); + +/** + * @brief Config types of uarts. + * + * @param UART_Port uart_no : UART0 or UART1 + * @param UART_IntrConfTypeDef *pUARTIntrConf : parameters structure + * + * @return null + */ +void UART_IntrConfig(UART_Port uart_no, UART_IntrConfTypeDef *pUARTIntrConf); + +/** + * @brief Config the length of the uart communication data bits. + * + * @param UART_Port uart_no : UART0 or UART1 + * @param UART_WordLength len : the length of the uart communication data bits + * + * @return null + */ +void UART_SetWordLength(UART_Port uart_no, UART_WordLength len); + +/** + * @brief Config the length of the uart communication stop bits. + * + * @param UART_Port uart_no : UART0 or UART1 + * @param UART_StopBits bit_num : the length uart communication stop bits + * + * @return null + */ +void UART_SetStopBits(UART_Port uart_no, UART_StopBits bit_num); + +/** + * @brief Configure whether to open the parity. + * + * @param UART_Port uart_no : UART0 or UART1 + * @param UART_ParityMode Parity_mode : the enum of uart parity configuration + * + * @return null + */ +void UART_SetParity(UART_Port uart_no, UART_ParityMode Parity_mode) ; + +/** + * @brief Configure the Baud rate. + * + * @param UART_Port uart_no : UART0 or UART1 + * @param u32 baud_rate : the Baud rate + * + * @return null + */ +void UART_SetBaudrate(UART_Port uart_no, u32 baud_rate); + +/** + * @brief Configure Hardware flow control. + * + * @param UART_Port uart_no : UART0 or UART1 + * @param UART_HwFlowCtrl flow_ctrl : Hardware flow control mode + * @param u8 rx_thresh : threshold of Hardware flow control + * + * @return null + */ +void UART_SetFlowCtrl(UART_Port uart_no, UART_HwFlowCtrl flow_ctrl, u8 rx_thresh); + +/** + * @brief Configure trigging signal of uarts. + * + * @param UART_Port uart_no : UART0 or UART1 + * @param UART_LineLevelInverse inverse_mask : Choose need to flip the IO + * + * @return null + */ +//void UART_SetLineInverse(UART_Port uart_no, UART_LineLevelInverse inverse_mask) ; + +/** + * @brief An example illustrates how to configure the serial port. + * + * @param null + * + * @return null + */ +void uart_init_new(void); + + +void uart0_write_char(char c); +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_watchdog.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_watchdog.h new file mode 100644 index 00000000..4f3bc1bb --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/driver/wm_watchdog.h @@ -0,0 +1,75 @@ +/** + * @file wm_watchdog.h + * + * @brief watchdog Driver Module + * + * @author dave + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#ifndef WM_WATCHDOG_H +#define WM_WATCHDOG_H + +/** + * @defgroup Driver_APIs Driver APIs + * @brief Driver APIs + */ + +/** + * @addtogroup Driver_APIs + * @{ + */ + +/** + * @defgroup WDG_Driver_APIs WDG Driver APIs + * @brief WDG driver APIs + */ + +/** + * @addtogroup WDG_Driver_APIs + * @{ + */ + +/** + * @brief This function is used to feed the dog. + * + * @param None + * + * @return None + * + * @note None + */ +void tls_watchdog_clr(void); + +/** + * @brief This function is used to init and start the watchdog. + * + * @param[in] usec microseconds + * + * @return None + * + * @note None + */ +void tls_watchdog_init(u32 usec); + +/** + * @brief This function is used to reset the system. + * + * @param None + * + * @return None + * + * @note None + */ +void tls_sys_reset(void); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WM_WATCHDOG_H */ + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/list.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/list.h new file mode 100644 index 00000000..26880cbb --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/list.h @@ -0,0 +1,309 @@ +/* + * @file list.h + * @brief Doubly-linked list + * @copyright (c) 2009, Jouni Malinen + * + * @note This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +#ifndef LIST_H +#define LIST_H + +#include + +/** struct dl_list - Doubly-linked list */ +struct dl_list { + struct dl_list *next; /**< pointer to the next */ + struct dl_list *prev; /**< pointer to the previous */ +}; + +/** + * @defgroup System_APIs System APIs + * @brief System APIs + */ + +/** + * @addtogroup System_APIs + * @{ + */ + +/** + * @defgroup DLIST_APIs DLIST APIs + * @brief Double listed APIs + */ + +/** + * @addtogroup DLIST_APIs + * @{ + */ + +/** + * @brief reinitialize the list + * + * @param[in] *list the list + * + * @return None + * + * @note None + */ +static __inline void dl_list_init(struct dl_list *list) +{ + list->next = list; + list->prev = list; +} + +/** + * @brief Insert a new entry after the specified head + * + * @param[in] *list list head to add it after + * @param[in] *item new entry to be added + * + * @return None + * + * @note None + */ +static __inline void dl_list_add(struct dl_list *list, struct dl_list *item) +{ + item->next = list->next; + item->prev = list; + list->next->prev = item; + list->next = item; +} + +/** + * @brief Insert a new entry before the specified head + * + * @param[in] *list list head to add it after + * @param[in] *item new entry to be added + * + * @return None + * + * @note None + */ +static __inline void dl_list_add_tail(struct dl_list *list, struct dl_list *item) +{ + dl_list_add(list->prev, item); +} + +/** + * @brief deletes entry from list + * + * @param[in] *item the element to delete from the list + * + * @return None + * + * @note None + */ +static __inline void dl_list_del(struct dl_list *item) +{ + item->next->prev = item->prev; + item->prev->next = item->next; + item->next = NULL; + item->prev = NULL; +} + +/** + * @brief tests whether a list is empty + * + * @param[in] *list the list to test + * + * @retval 0 not empty + * @retval 1 empty + * + * @note None + */ +static __inline int dl_list_empty(struct dl_list *list) +{ + return list->next == list; +} + +/** + * @brief count length of the list + * + * @param[in] *list the list to count + * + * @return length + * + * @note None + */ +static __inline unsigned int dl_list_len(struct dl_list *list) +{ + struct dl_list *item; + int count = 0; + for (item = list->next; item != list; item = item->next) + count++; + return count; +} + +/** + * @} + */ + +/** + * @} + */ + +#ifndef offsetof +/** offset address of the struct member */ +#define offsetof(type, member) ((long) &((type *) 0)->member) +#endif + +/** + * @brief get the struct for this entry + * + * @param[in] item the &struct list_head pointer + * @param[in] type the type of the struct this is embedded in + * @param[in] member the name of the list_struct within the struct + * + * @return pointer to the struct for this entry + * + * @note None + */ +#define dl_list_entry(item, type, member) \ + ((type *) ((char *) item - offsetof(type, member))) + +/** + * @brief get the first element from a list + * + * @param[in] list the list head to take the element from + * @param[in] type the type of the struct this is embedded in + * @param[in] member the name of the list_struct within the struct + * + * @return pointer to the first element from a list + * + * @note None + */ +#define dl_list_first(list, type, member) \ + (dl_list_empty((list)) ? NULL : \ + dl_list_entry((list)->next, type, member)) + +/** + * @brief get the last element from a list + * + * @param[in] list the list head to take the element from + * @param[in] type the type of the struct this is embedded in + * @param[in] member the name of the list_struct within the struct + * + * @return pointer to the last element from a list + * + * @note None + */ +#define dl_list_last(list, type, member) \ + (dl_list_empty((list)) ? NULL : \ + dl_list_entry((list)->prev, type, member)) + +/** + * @brief iterate over list of given type + * + * @param[in] item a loop cursor + * @param[in] list the head for your list + * @param[in] type struct type + * @param[in] member the name of the list_struct within the struct + * + * @return None + * + * @note None + */ +#define dl_list_for_each(item, list, type, member) \ + for (item = dl_list_entry((list)->next, type, member); \ + &item->member != (list); \ + item = dl_list_entry(item->member.next, type, member)) + +/** + * @brief iterate over list of given type safe against removal of list entry + * + * @param[in] item a loop cursor + * @param[in] n temporary storage + * @param[in] list the head for your list + * @param[in] type struct type + * @param[in] member the name of the list_struct within the struct + * + * @return None + * + * @note None + */ +#define dl_list_for_each_safe(item, n, list, type, member) \ + for (item = dl_list_entry((list)->next, type, member), \ + n = dl_list_entry(item->member.next, type, member); \ + &item->member != (list); \ + item = n, n = dl_list_entry(n->member.next, type, member)) + +/** + * @brief iterate backwards over list of given type + * + * @param[in] item a loop cursor + * @param[in] list the head for your list + * @param[in] type struct type + * @param[in] member the name of the list_struct within the struct + * + * @return None + * + * @note None + */ +#define dl_list_for_each_reverse(item, list, type, member) \ + for (item = dl_list_entry((list)->prev, type, member); \ + &item->member != (list); \ + item = dl_list_entry(item->member.prev, type, member)) + +/** define the list head */ +#define DEFINE_DL_LIST(name) \ + struct dl_list name = { &(name), &(name) } + +/** + * @brief iterate over list of given type + * + * @param[in] item the type * to use as a loop cursor + * @param[in] list the head for your list + * @param[in] member the name of the list_struct within the struct + * + * @return None + * + * @note None + */ +#define __dl_list_for_each(item, list, member) \ + for (item = dl_list_entry((list)->next, typeof(*(item)), member); \ + &item->member != (list); \ + item = dl_list_entry(item->member.next, typeof(*(item)), member)) + +/** + * @brief iterate over list of given type safe against removal of list entry + * + * @param[in] item the type * to use as a loop cursor + * @param[in] n temporary storage + * @param[in] list the head for your list + * @param[in] member the name of the list_struct within the struct + * + * @return None + * + * @note None + */ +#define __dl_list_for_each_safe(item, n, list, member) \ + for (item = dl_list_entry((list)->next, typeof(*(item)), member), \ + n = dl_list_entry(item->member.next, typeof(*(item)), member); \ + &item->member != (list); \ + item = n, n = dl_list_entry(n->member.next, typeof(*(item)), member)) + +/** + * @brief iterate backwards over list of given type + * + * @param[in] item the type * to use as a loop cursor + * @param[in] list the head for your list + * @param[in] member the name of the list_struct within the struct + * + * @return None + * + * @note None + */ +#define __dl_list_for_each_reverse(item, list, member) \ + for (item = dl_list_entry((list)->prev, typeof(*(item)), member); \ + &item->member != (list); \ + item = dl_list_entry(item->member.prev, typeof(*(item)), member)) + +#endif /* LIST_H */ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/aes.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/aes.h new file mode 100644 index 00000000..e5f5a41f --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/aes.h @@ -0,0 +1,186 @@ +/** + * @file aes.h + * @brief AES functions + * @copyright (c) 2003-2006, Jouni Malinen + * + * @note This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Alternatively, this software may be distributed under the terms of BSD + * license. + * + * See README and COPYING for more details. + */ + +#ifndef AES_H +#define AES_H +//#include "crypto/cryptoApi.h" +#include +#include "wm_type_def.h" +#define USE_AES +#define PSPUBLIC +#ifndef CRYPT_INVALID_KEYSIZE +#define CRYPT_INVALID_KEYSIZE -21 +#endif +#ifndef MAXBLOCKSIZE +#define MAXBLOCKSIZE 24 +#endif + +#define STORE32H(x, y) { \ +(y)[0] = (unsigned char)(((x)>>24)&255); \ +(y)[1] = (unsigned char)(((x)>>16)&255); \ +(y)[2] = (unsigned char)(((x)>>8)&255); \ +(y)[3] = (unsigned char)((x)&255); \ +} + +#define LOAD32H(x, y) { \ +x = ((unsigned long)((y)[0] & 255)<<24) | \ +((unsigned long)((y)[1] & 255)<<16) | \ +((unsigned long)((y)[2] & 255)<<8) | \ +((unsigned long)((y)[3] & 255)); \ +} + +#define byte(x, n) (((x) >> (8 * (n))) & 255) + +#define ROR(x, y) \ + ( ((((unsigned long)(x)&0xFFFFFFFFUL)>>(unsigned long)((y)&31)) | \ + ((unsigned long)(x)<<(unsigned long)(32-((y)&31)))) & 0xFFFFFFFFUL) + +#define psTraceCrypto(x) + +/******************************************************************************/ +/* + Universal return codes +*/ +#define PS_SUCCESS 0 +#define PS_FAILURE -1 + +/* NOTE: Failure return codes MUST be < 0 */ +/* NOTE: The range for core error codes should be between -2 and -29 */ +#define PS_ARG_FAIL -6 /* Failure due to bad function param */ +#define PS_PLATFORM_FAIL -7 /* Failure as a result of system call error */ +#define PS_MEM_FAIL -8 /* Failure to allocate requested memory */ +#define PS_LIMIT_FAIL -9 /* Failure on sanity/limit tests */ +#define PS_UNSUPPORTED_FAIL -10 /* Unimplemented feature error */ +#define PS_DISABLED_FEATURE_FAIL -11 /* Incorrect #define toggle for feature */ +#define PS_PROTOCOL_FAIL -12 /* A protocol error occurred */ +#define PS_TIMEOUT_FAIL -13 /* A timeout occurred and MAY be an error */ +#define PS_INTERRUPT_FAIL -14 /* An interrupt occurred and MAY be an error */ +#define PS_PENDING -15 /* In process. Not necessarily an error */ +#define PS_EAGAIN -16 /* Try again later. Not necessarily an error */ + +#define PS_TRUE 1 +#define PS_FALSE 0 + +//typedef int int32; //璋冪敤wm_type_def.h +//typedef unsigned int uint32; +//typedef short int16; +//typedef unsigned short uint16; +//typedef unsigned char uint8; + +//typedef long long int64; +//typedef unsigned long long uint64; +//#if (GCC_COMPILE==0) +//typedef unsigned int size_t; +//#endif + + +/******************************************************************************/ +#ifdef USE_AES +/******************************************************************************/ + + +#ifndef USE_AES_CBC_EXTERNAL +typedef struct { + unsigned int eK[64], dK[64]; + int Nr; +} psAesKey_t; + +typedef struct { + int blocklen; + unsigned char IV[16]; + psAesKey_t key; +#if defined(USE_AES_GCM) || defined(USE_AES_CCM) + unsigned char EncCtr[16]; + unsigned char CtrBlock[16]; +#endif +#ifdef USE_AES_GCM + unsigned char gInit[16]; + unsigned int TagTemp[4]; + unsigned char Hash_SubKey[16]; + unsigned int ProcessedBitCount[4]; + unsigned int InputBufferCount; + unsigned int OutputBufferCount; + union + { + unsigned char Buffer[128]; + unsigned int BufferAlignment; + } Input; +#endif /* USE_AES_GCM */ +#ifdef USE_AES_CCM + unsigned int ccmTagTemp[16 / sizeof(unsigned int)]; /* 32 */ + union + { + /* Used for formatting IV. */ + unsigned char Temporary[16]; + /* Used for processing Mac. */ + unsigned char Y0[16]; + } u; /* 48 */ +#endif /* USE_AES_CCM */ +} psAesCipher_t; + +typedef union { +#ifdef USE_AES + psAesCipher_t aes; +#endif +} psAesCipherContext_t; + +#endif /* USE_AES_CBC_EXTERNAL */ + +#endif /* USE_AES */ + +#if 0 +void * aes_encrypt_init(const u8 *key, size_t len); +void aes_encrypt(void *ctx, const u8 *plain, u8 *crypt); +void aes_encrypt_deinit(void *ctx); +void * aes_decrypt_init(const u8 *key, size_t len); +void aes_decrypt(void *ctx, const u8 *crypt, u8 *plain); +void aes_decrypt_deinit(void *ctx); +#endif + +#ifndef USE_AES +#error "Must Enable USE_AES in cryptoConfig.h!" +#endif + +#ifdef USE_AES +/******************************************************************************/ +/* + CBC Mode AES +*/ +PSPUBLIC int psAesInit(psAesCipherContext_t *ctx, unsigned char *IV, + unsigned char *key, unsigned int keylen); +PSPUBLIC int psAesDecrypt(psAesCipherContext_t *ctx, unsigned char *ct, + unsigned char *pt, unsigned int len); +PSPUBLIC int psAesEncrypt(psAesCipherContext_t *ctx, unsigned char *pt, + unsigned char *ct, unsigned int len); +/* + Block Mode AES +*/ +PSPUBLIC int psAesInitKey(const unsigned char *key, unsigned int keylen, + psAesKey_t *skey); +PSPUBLIC void psAesEncryptBlock(const unsigned char *pt, unsigned char *ct, + psAesKey_t *skey); +PSPUBLIC void psAesDecryptBlock(const unsigned char *ct, unsigned char *pt, + psAesKey_t *skey); + + + +int aes_128_cbc_encrypt(const u8 *key, const u8 *iv, u8 *data, + size_t data_len); +int aes_128_cbc_decrypt(const u8 *key, const u8 *iv, u8 *data, + size_t data_len); +#endif + +#endif /* AES_H */ + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_crypto_hard.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_crypto_hard.h new file mode 100644 index 00000000..6dd273f5 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_crypto_hard.h @@ -0,0 +1,513 @@ +/** + * @file wm_crypto_hard.h + * + * @brief hard crypto module + * + * @author dave + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ + +#ifndef WM_CRYPTO_HARD_H +#define WM_CRYPTO_HARD_H + +#include "wm_type_def.h" +#include "cryptoConfig.h" +#include "digest.h" +#include "pstm.h" +#include "symmetric.h" +#include "cryptolib.h" + +#include "cryptoApi.h" + +#ifndef min + #define min(a,b) (((a) < (b)) ? (a) : (b)) +#endif /* min */ + +/** The base address of the registers of encryption/decryption module. */ +#define HR_CRYPTO_BASE_ADDR 0x40003200 +/** The address of the source text address register. */ +#define HR_CRYPTO_SRC_ADDR (HR_CRYPTO_BASE_ADDR + 0x00) +/** The address of the encrypted/decrypted text address register. */ +#define HR_CRYPTO_DEST_ADDR (HR_CRYPTO_BASE_ADDR + 0x04) +/** The address of the configuration register. */ +#define HR_CRYPTO_SEC_CFG (HR_CRYPTO_BASE_ADDR + 0x08) +/** The address of the control register. */ +#define HR_CRYPTO_SEC_CTRL (HR_CRYPTO_BASE_ADDR + 0x0C) +/** The address of the key0 register. */ +#define HR_CRYPTO_KEY0 (HR_CRYPTO_BASE_ADDR + 0x10) +/** The address of the key1 register. */ +#define HR_CRYPTO_KEY1 (HR_CRYPTO_BASE_ADDR + 0x14) +/** The address of the key2 register. */ +#define HR_CRYPTO_KEY2 (HR_CRYPTO_BASE_ADDR + 0x18) +/** The address of the key3 register. */ +#define HR_CRYPTO_KEY3 (HR_CRYPTO_BASE_ADDR + 0x1C) +/** The address of the key4 register. */ +#define HR_CRYPTO_KEY4 (HR_CRYPTO_BASE_ADDR + 0x20) +/** The address of the key5 register. */ +#define HR_CRYPTO_KEY5 (HR_CRYPTO_BASE_ADDR + 0x24) + +/** The address of the IV0 register. */ +#define HR_CRYPTO_IV0 (HR_CRYPTO_BASE_ADDR + 0x28) +/** The address of the IV1 register. */ +#define HR_CRYPTO_IV1 (HR_CRYPTO_BASE_ADDR + 0x20) + +/** The address of the encrypted/decrypted status register. */ +#define HR_CRYPTO_SEC_STS (HR_CRYPTO_BASE_ADDR + 0x30) + +/** The address of the SHA1/MD5 digest0 register. */ +#define HR_CRYPTO_SHA1_DIGEST0 (HR_CRYPTO_BASE_ADDR + 0x34) +/** The address of the SHA1/MD5 digest1 register. */ +#define HR_CRYPTO_SHA1_DIGEST1 (HR_CRYPTO_BASE_ADDR + 0x38) +/** The address of the SHA1/MD5 digest2 register. */ +#define HR_CRYPTO_SHA1_DIGEST2 (HR_CRYPTO_BASE_ADDR + 0x3C) +/** The address of the SHA1/MD5 digest3 register. */ +#define HR_CRYPTO_SHA1_DIGEST3 (HR_CRYPTO_BASE_ADDR + 0x40) +/** The address of the SHA1 digest4 and CRC in/output register. */ +#define HR_CRYPTO_SHA1_DIGEST4 (HR_CRYPTO_BASE_ADDR + 0x44) +/** The address of the RNG RESULT register. */ +#define HR_CRYPTO_RNG_RESULT (HR_CRYPTO_BASE_ADDR + 0x48) + + +/** The address of the CRC in register. */ +#define HR_CRYPTO_CRC_KEY HR_CRYPTO_SHA1_DIGEST4 +/** The address of the CRC output register. */ +#define HR_CRYPTO_CRC_RESULT HR_CRYPTO_SHA1_DIGEST4 + +#define ERR_CRY_OK 0 ///< No error, everything OK. +#define ERR_FAILURE -1 /* failure */ +#define ERR_ARG_FAIL -6 /* Failure due to bad function param */ + +//CRC +#define OUTPUT_REFLECT 1 +#define INPUT_REFLECT 2 + +typedef enum __CRYPTO_METHOD +{ + CRYPTO_METHOD_RSV=0, + CRYPTO_METHOD_RC4, + CRYPTO_METHOD_SHA1, + CRYPTO_METHOD_AES, + CRYPTO_METHOD_DES, + CRYPTO_METHOD_3DES, + CRYPTO_METHOD_CRC, ///< CRC + CRYPTO_METHOD_MD5 ///< MD5 +}CRYPTO_METHOD; + + /** + * The enum of the encryption/decryption way. + */ +typedef enum __CRYPTO_WAY +{ + CRYPTO_WAY_ENCRYPT=0, ///< Encryption + CRYPTO_WAY_DECRYPT ///< Decryption +}CRYPTO_WAY; + +typedef enum __CRYPTO_RNG_SWITCH +{ + CRYPTO_RNG_SWITCH_16 = 0, + CRYPTO_RNG_SWITCH_32 +}CRYPTO_RNG_SWITCH; + + /** + * The enum of the encryption/decryption mode, only for (aes des 3des). + */ +typedef enum __CRYPTO_MODE +{ + CRYPTO_MODE_ECB=0, ///< ECB + CRYPTO_MODE_CBC, ///< CBC + CRYPTO_MODE_CTR ///< CTR, only for AES +}CRYPTO_MODE; + /** + * The enum of the CRC type. + */ +typedef enum __CRYPTO_CRC_TYPE +{ + CRYPTO_CRC_TYPE_8=0, ///< 8 bits CRC + CRYPTO_CRC_TYPE_16_MODBUS, ///< 16 bits Modbus CRC + CRYPTO_CRC_TYPE_16_CCITT, ///< 16 bits CCITT CRC + CRYPTO_CRC_TYPE_32 ///< 32 bits CRC +}CRYPTO_CRC_TYPE; + + /** + * The struct of the CRC context. + */ +typedef struct { + u32 state; ///< The initial value input and result value output. + u8 type; ///< The type of CRC, refernec the CRYPTO_CRC_TYPE enum. + u8 mode; ///< The mode of CRC, bit0 means output reflection and bit1 means input reflection. +}psCrcContext_t; + +#if 1 + +struct hsha1_state { +#ifdef HAVE_NATIVE_INT64 + uint64 length; +#else + u32 lengthHi; + u32 lengthLo; +#endif /* HAVE_NATIVE_INT64 */ + u32 state[5], curlen; + unsigned char buf[64]; +}; +struct hmd5_state { +#ifdef HAVE_NATIVE_INT64 + uint64 length; +#else + u32 lengthHi; + u32 lengthLo; +#endif /* HAVE_NATIVE_INT64 */ + u32 state[4], curlen; + unsigned char buf[64]; +}; + +typedef union { + struct hsha1_state sha1; + struct hmd5_state md5; +} hsDigestContext_t; + +typedef u32 hstm_digit; +typedef struct { + int16 used, alloc, sign; + hstm_digit *dp; +} hstm_int; + +#endif + +/** + * @brief This function is used to stop random produce. + * + * @param[in] None + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +int tls_crypto_random_stop(void); + + +/** + * @brief This function initializes random digit seed and BIT number. + * + * @param[in] seed The random digit seed. + * @param[in] rng_switch The random digit bit number. (0: 16bit 1:32bit) + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +int tls_crypto_random_init(u32 seed, CRYPTO_RNG_SWITCH rng_switch); + + +/** + * @brief This function is used to get random digit content. + * + * @param[in] out Pointer to the output of random digit. + * @param[in] len The random digit bit number will output. + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +int tls_crypto_random_bytes(unsigned char *out, u32 len); + + +/** + * @brief This function initializes a RC4 encryption algorithm, + * i.e. fills the psCipherContext_t structure pointed to by ctx with necessary data. + * + * @param[in] ctx Pointer to the Cipher Context. + * @param[in] key Pointer to the key. + * @param[in] keylen the length of key. + * + * @retval 0 success + * @retval other failed + + * + * @note The first parameter ctx must be a structure which is allocated externally. + * And all of Context parameters in the initializing methods should be allocated externally too. + */ +int tls_crypto_rc4_init(psCipherContext_t * ctx, const unsigned char *key, u32 keylen); + +/** + * @brief This function encrypts a variable length data stream according to RC4. + * The RC4 algorithm it generates a "keystream" which is simply XORed with the plaintext to produce the ciphertext stream. + * Decryption is exactly the same as encryption. This function also decrypts a variable length data stream according to RC4. + * + * @param[in] ctx Pointer to the Cipher Context. + * @param[in] in Pointer to the input plaintext data stream(or the encrypted text data stream) of variable length. + * @param[in] out Pointer to the resulting ciphertext data stream. + * @param[in] len Length of the plaintext data stream in octets. + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +int tls_crypto_rc4(psCipherContext_t * ctx, unsigned char *in, unsigned char *out, u32 len); + +/** + * @brief This function initializes a AES encryption algorithm, i.e. fills the psCipherContext_t structure pointed to by ctx with necessary data. + * + * @param[in] ctx Pointer to the Cipher Context. + * @param[in] IV Pointer to the Initialization Vector + * @param[in] key Pointer to the key. + * @param[in] keylen the length of key. + * @param[in] cbc the encryption mode, AES supports ECB/CBC/CTR modes. + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +int tls_crypto_aes_init(psCipherContext_t * ctx, const unsigned char *IV, const unsigned char *key, u32 keylen, CRYPTO_MODE cbc); + +/** + * @brief This function encrypts or decrypts a variable length data stream according to AES. + * + * @param[in] ctx Pointer to the Cipher Context. + * @param[in] in Pointer to the input plaintext data stream(or the encrypted text data stream) of variable length. + * @param[in] out Pointer to the resulting ciphertext data stream. + * @param[in] len Length of the plaintext data stream in octets. + * @param[in] dec The cryption way which indicates encryption or decryption. + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +int tls_crypto_aes_encrypt_decrypt(psCipherContext_t * ctx, unsigned char *in, unsigned char *out, u32 len, CRYPTO_WAY dec); + +/** + * @brief This function initializes a 3DES encryption algorithm, i.e. fills the psCipherContext_t structure pointed to by ctx with necessary data. + * + * @param[in] ctx Pointer to the Cipher Context. + * @param[in] IV Pointer to the Initialization Vector + * @param[in] key Pointer to the key. + * @param[in] keylen the length of key. + * @param[in] cbc the encryption mode, 3DES supports ECB/CBC modes. + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +int tls_crypto_3des_init(psCipherContext_t * ctx, const unsigned char *IV, const unsigned char *key, u32 keylen, CRYPTO_MODE cbc); + +/** + * @brief This function encrypts or decrypts a variable length data stream according to 3DES. + * + * @param[in] ctx Pointer to the Cipher Context. + * @param[in] in Pointer to the input plaintext data stream(or the encrypted text data stream) of variable length. + * @param[in] out Pointer to the resulting ciphertext data stream. + * @param[in] len Length of the plaintext data stream in octets. + * @param[in] dec The cryption way which indicates encryption or decryption. + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +int tls_crypto_3des_encrypt_decrypt(psCipherContext_t * ctx, unsigned char *in, unsigned char *out, u32 len, CRYPTO_WAY dec); + +/** + * @brief This function initializes a DES encryption algorithm, i.e. fills the psCipherContext_t structure pointed to by ctx with necessary data. + * + * @param[in] ctx Pointer to the Cipher Context. + * @param[in] IV Pointer to the Initialization Vector + * @param[in] key Pointer to the key. + * @param[in] keylen the length of key. + * @param[in] cbc the encryption mode, DES supports ECB/CBC modes. + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +int tls_crypto_des_init(psCipherContext_t * ctx, const unsigned char *IV, const unsigned char *key, u32 keylen, CRYPTO_MODE cbc); + +/** + * @brief This function encrypts or decrypts a variable length data stream according to DES. + * + * @param[in] ctx Pointer to the Cipher Context. + * @param[in] in Pointer to the input plaintext data stream(or the encrypted text data stream) of variable length. + * @param[in] out Pointer to the resulting ciphertext data stream. + * @param[in] len Length of the plaintext data stream in octets. + * @param[in] dec The cryption way which indicates encryption or decryption. + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +int tls_crypto_des_encrypt_decrypt(psCipherContext_t * ctx, unsigned char *in, unsigned char *out, u32 len, CRYPTO_WAY dec); + +/** + * @brief This function initializes a CRC algorithm, i.e. fills the psCrcContext_t structure pointed to by ctx with necessary data. + * + * @param[in] ctx Pointer to the CRC Context. + * @param[in] key The initialization key. + * @param[in] crc_type The CRC type, supports CRC8/CRC16 MODBUS/CRC16 CCITT/CRC32 + * @param[in] mode Set input or outpu reflect. + * @param[in] dec The cryption way which indicates encryption or decryption. + * see OUTPUT_REFLECT + * see INPUT_REFLECT + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +int tls_crypto_crc_init(psCrcContext_t * ctx, u32 key, CRYPTO_CRC_TYPE crc_type, u8 mode); + +/** + * @brief This function updates the CRC value with a variable length bytes. + * This function may be called as many times as necessary, so the message may be processed in blocks. + * + * @param[in] ctx Pointer to the CRC Context. + * @param[in] in Pointer to a variable length bytes + * @param[in] len The bytes 's length + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +int tls_crypto_crc_update(psCrcContext_t * ctx, unsigned char *in, u32 len); + +/** + * @brief This function ends a CRC operation and produces a CRC value. + * + * @param[in] ctx Pointer to the CRC Context. + * @param[in] crc_val Pointer to the CRC value. + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +int tls_crypto_crc_final(psCrcContext_t * ctx, u32 *crc_val); + +/** + * @brief This function initializes Message-Diggest context for usage in SHA1 algorithm, starts a new SHA1 operation and writes a new Digest Context. + * + * @param[in] md Pointer to the SHA1 Digest Context. + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +void tls_crypto_sha1_init(psDigestContext_t * md); + +/** + * @brief Process a message block using SHA1 algorithm. + * This function performs a SHA1 block update operation. It continues an SHA1 message-digest operation, + * by processing InputLen-byte length message block pointed to by buf, and by updating the SHA1 context pointed to by md. + * This function may be called as many times as necessary, so the message may be processed in blocks. + * + * @param[in] md Pointer to the SHA1 Digest Context. + * @param[in] buf InputLen-byte length message block + * @param[in] len The buf 's length + * + * @returnl None + * + * @note None + */ +void tls_crypto_sha1_update(psDigestContext_t * md, const unsigned char *buf, u32 len); + +/** + * @brief This function ends a SHA1 operation and produces a Message-Digest. + * This function finalizes SHA1 algorithm, i.e. ends an SHA1 Message-Digest operation, + * writing the Message-Digest in the 20-byte buffer pointed to by hash in according to the information stored in context. + * + * @param[in] md Pointer to the SHA1 Digest Context. + * @param[in] hash Pointer to the Message-Digest + * + * @retval 20 success, return the hash size. + * @retval <0 failed + + * + * @note None + */ +int tls_crypto_sha1_final(psDigestContext_t * md, unsigned char *hash); + +/** + * @brief This function initializes Message-Diggest context for usage in MD5 algorithm, starts a new MD5 operation and writes a new Digest Context. + * This function begins a MD5 Message-Diggest Algorithm, i.e. fills the psDigestContext_t structure pointed to by md with necessary data. + * MD5 is the algorithm which takes as input a message of arbitrary length and produces as output a 128-bit "fingerprint" or "message digest" of the input. + * It is conjectured that it is computationally infeasible to produce two messages having the same message digest, + * or to produce any message having a given prespecified target message digest. + * + * @param[in] md MD5 Digest Context. + * + * @return None + * + * @note None + */ +void tls_crypto_md5_init(psDigestContext_t * md); + +/** + * @brief Process a message block using MD5 algorithm. + * This function performs a MD5 block update operation. It continues an MD5 message-digest operation, + * by processing InputLen-byte length message block pointed to by buf, and by updating the MD5 context pointed to by md. + * This function may be called as many times as necessary, so the message may be processed in blocks. + * + * @param[in] md MD5 Digest Context. + * @param[in] buf InputLen-byte length message block + * @param[in] len The buf 's length + * + * @return None + * + * @note None + */ +void tls_crypto_md5_update(psDigestContext_t * md, const unsigned char *buf, u32 len); + +/** + * @brief This function ends a MD5 operation and produces a Message-Digest. + * This function finalizes MD5 algorithm, i.e. ends an MD5 Message-Digest operation, + * writing the Message-Digest in the 16-byte buffer pointed to by hash in according to the information stored in context. + * + * @param[in] md MD5 Digest Context. + * @param[in] hash the Message-Digest + * + * @retval 16 success, return the hash size. + * @retval <0 failed + * + * @note None + */ +int tls_crypto_md5_final(psDigestContext_t * md, unsigned char *hash); + +/** + * @brief This function implements the large module power multiplication algorithm. + * res = a**e (mod n) + * + * @param[in] a Pointer to a bignumber. + * @param[in] e Pointer to a bignumber. + * @param[in] n Pointer to a bignumber. + * @param[out] res Pointer to the result bignumber. + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +int tls_crypto_exptmod(pstm_int *a, pstm_int *e, pstm_int *n, pstm_int *res); + +/** + * @brief This function initializes the encryption module. + * + * @param None + * + * @return None + * + * @note None + */ +void tls_crypto_init(void); + +#endif + + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_fwup.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_fwup.h new file mode 100644 index 00000000..56f903d4 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_fwup.h @@ -0,0 +1,343 @@ +/** + * @file wm_fwup.h + * + * @brief Firmware upgrade + * + * @author winnermicro + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ + +#ifndef WM_FWUP_H +#define WM_FWUP_H +#include "wm_osal.h" +#include "list.h" + +/** firmware update status */ +#define TLS_FWUP_STATUS_OK (0) +#define TLS_FWUP_STATUS_EINVALID (1) +#define TLS_FWUP_STATUS_EMEM (2) +#define TLS_FWUP_STATUS_EPERM (3) +#define TLS_FWUP_STATUS_EBUSY (4) +#define TLS_FWUP_STATUS_ESESSIONID (5) +#define TLS_FWUP_STATUS_EIO (6) +#define TLS_FWUP_STATUS_ESIGNATURE (7) +#define TLS_FWUP_STATUS_ECRC (8) +#define TLS_FWUP_STATUS_EUNDEF (9) + +/** firmware signature */ +#define TLS_FWUP_IMAGE_SIGNATURE_WORD 0x64365577 +#define TLS_FWUP_IMAGE_SIGNATURE_WORD_B 0x62161900 + +/** firmware block size for one time */ +#define TLS_FWUP_BLK_SIZE 512 + +/** firmware update request status */ +#define TLS_FWUP_REQ_STATUS_IDLE (0) +#define TLS_FWUP_REQ_STATUS_BUSY (1) +#define TLS_FWUP_REQ_STATUS_SUCCESS (2) +#define TLS_FWUP_REQ_STATUS_FIO (3) +#define TLS_FWUP_REQ_STATUS_FSIGNATURE (4) +#define TLS_FWUP_REQ_STATUS_FMEM (5) +#define TLS_FWUP_REQ_STATUS_FCRC (6) +#define TLS_FWUP_REQ_STATUS_FCOMPLETE (7) + +/** firmware update state */ +#define TLS_FWUP_STATE_UNDEF (0xffff) +#define TLS_FWUP_STATE_BUSY (1 << 0) +#define TLS_FWUP_STATE_COMPLETE (1 << 1) +#define TLS_FWUP_STATE_ERROR_IO (1 << 2) +#define TLS_FWUP_STATE_ERROR_SIGNATURE (1 << 3) +#define TLS_FWUP_STATE_ERROR_MEM (1 << 4) +#define TLS_FWUP_STATE_ERROR_CRC (1 << 5) + +#define TLS_FWUP_STATE_ERROR (TLS_FWUP_STATE_ERROR_IO | TLS_FWUP_STATE_ERROR_SIGNATURE | TLS_FWUP_STATE_ERROR_MEM | TLS_FWUP_STATE_ERROR_CRC) + +/** update type 0:firmware, 1: data */ +#define TLS_FWUP_DEST_SPECIFIC_FIRMWARE (0) +#define TLS_FWUP_DEST_SPECIFIC_DATA (1) + +enum IMAGE_TYPE_ENUM{ + IMG_TYPE_OLD_PLAIN = 0, + IMG_TYPE_FLASHBIN = 1, + IMG_TYPE_SECBOOT = 2, + IMG_TYPE_NEW_PLAIN = 3 +}; +enum { + NOT_ZIP_FILE = 0, + ZIP_FILE = 1 +}; +typedef struct __T_BOOTER +{ + unsigned int magic_no; + unsigned short img_type; + unsigned short zip_type; /** image type zip flag, 0: non-zip, 1:zip*/ + unsigned int run_img_addr; /** run area image start address */ + unsigned int run_img_len; /** run area image length */ + unsigned int run_org_checksum; /** run area image checksum */ + unsigned int upd_img_addr; /** upgrade area image start address*/ + unsigned int upd_img_len; /** upgrade area image length*/ + unsigned int upd_checksum; /** upgrade area image checksum */ + unsigned int upd_no; + unsigned char ver[16]; + unsigned int hd_checksum; +} T_BOOTER; + +/** Structure for firmware image header */ +struct tls_fwup_image_hdr { + u32 magic; + u8 crc8; + u8 dest_specific; + u16 dest_offset; // unit: 4KB, valid when dest_specific is TRUE + u32 file_len; + char time[4]; +}; + +/** Structure for one packet data */ +struct tls_fwup_block { + u16 number; //0~Sum-1 + u16 sum; + u8 data[TLS_FWUP_BLK_SIZE]; + u32 crc32; + u8 pad[8]; +}; + +/** Enumeration for image soure when firmware update */ +enum tls_fwup_image_src { + TLS_FWUP_IMAGE_SRC_LUART = 0, /**< LOW SPEED UART */ + TLS_FWUP_IMAGE_SRC_HUART, /**< HIGH SPEED UART */ + TLS_FWUP_IMAGE_SRC_HSPI, /**< HIGH SPEED SPI */ + TLS_FWUP_IMAGE_SRC_WEB /**< WEB SERVER */ +}; + +/** Structure for firmware update request */ +struct tls_fwup_request { + struct dl_list list; + u8 *data; + u32 data_len; + int status; + void (*complete)(struct tls_fwup_request *request, void *arg); + void *arg; +}; + +/** Structure for firmware update */ +struct tls_fwup { + struct dl_list wait_list; + tls_os_sem_t *list_lock; + + bool busy; + enum tls_fwup_image_src current_image_src; + u16 current_state; + u32 current_session_id; + + u32 received_len; + u32 total_len; + u32 updated_len; + u32 program_base; + u32 program_offset; + s32 received_number; +}; + +/** + * @defgroup System_APIs System APIs + * @brief System APIs + */ + +/** + * @addtogroup System_APIs + * @{ + */ + +/** + * @defgroup FWUP_APIs FWUP APIs + * @brief firmware upgrade APIs + */ + +/** + * @addtogroup FWUP_APIs + * @{ + */ + +/** + * @brief This function is used to initialize firmware update task + * + * @param[in] None + * + * @retval TLS_FWUP_STATUS_OK initial success + * @retval TLS_FWUP_STATUS_EBUSY already initialed + * @retval TLS_FWUP_STATUS_EMEM memory error + * @note None + */ +int tls_fwup_init(void); + +/** + * @brief This function is used to enter firmware update progress. + * + * @param[in] image_src image file's source, + from TLS_FWUP_IMAGE_SRC_LUART, + TLS_FWUP_IMAGE_SRC_WEB,TLS_FWUP_IMAGE_SRC_HUART, + TLS_FWUP_IMAGE_SRC_HSPI + * + * @retval non-zero successfully, return session id + * @retval 0 failed + * + * @note None + */ +u32 tls_fwup_enter(enum tls_fwup_image_src image_src); + +/** + * @brief This function is used to exit firmware update progress. + * + * @param[in] session_id session identity of firmware update progress + * + * @retval TLS_FWUP_STATUS_OK exit success + * @retval TLS_FWUP_STATUS_EPERM globle param is not initialed + * @retval TLS_FWUP_STATUS_ESESSIONID error session id + * @retval TLS_FWUP_STATUS_EBUSY update state is busy + * + * @note None + */ +int tls_fwup_exit(u32 session_id); + +/** + * @brief This function is used to start update progress + * + * @param[in] session_id current sessin id + * @param[in] *data the data want to update + * @param[in] data_len data length + * + * @retval TLS_FWUP_STATUS_OK updade success + * @retval TLS_FWUP_STATUS_EPERM globle param is not initialed + * @retval TLS_FWUP_STATUS_ESESSIONID error session id + * @retval TLS_FWUP_STATUS_EINVALID invalid param + * @retval TLS_FWUP_STATUS_EMEM memory error + * @retval TLS_FWUP_STATUS_EIO write flash error + * @retval TLS_FWUP_STATUS_ECRC crc error + * @retval TLS_FWUP_STATUS_ESIGNATURE signature error + * @retval TLS_FWUP_STATUS_EUNDEF other error + * + * @note None + */ +int tls_fwup_request_sync(u32 session_id, u8 *data, u32 data_len); + +/** + * @brief This function is used to get current update status + * + * @param[in] session_id current sessin id + * + * @retval current state TLS_FWUP_STATUS_OK to TLS_FWUP_STATUS_EUNDEF + * + * @note None + */ +u16 tls_fwup_current_state(u32 session_id); + +/** + * @brief This function is used to reset the update information + * + * @param[in] session_id current sessin id + * + * @retval TLS_FWUP_STATUS_OK reset success + * @retval TLS_FWUP_STATUS_EPERM globle param is not initialed + * @retval TLS_FWUP_STATUS_ESESSIONID error session id + * @retval TLS_FWUP_STATUS_EBUSY update state is busy + * + * @note None + */ +int tls_fwup_reset(u32 session_id); + +/** + * @brief This function is used to clear error update state + * + * @param[in] session_id current sessin id + * + * @retval TLS_FWUP_STATUS_OK reset success + * + * @note None + */ +int tls_fwup_clear_error(u32 session_id); + +/** + * @brief This function is used to set update state to + TLS_FWUP_STATE_ERROR_CRC + * + * @param[in] session_id current sessin id + * + * @retval TLS_FWUP_STATUS_OK set success + * @retval TLS_FWUP_STATUS_EPERM globle param is not initialed + * @retval TLS_FWUP_STATUS_ESESSIONID error session id + * + * @note None + */ +int tls_fwup_set_crc_error(u32 session_id); + +/** + * @brief This function is used to get progress's status + * + * @param[in] None + * + * @retval TRUE busy + * @retval FALSE idle + * + * @note None + */ +int tls_fwup_get_status(void); + +/** + * @brief This function is used to set update packet number + * + * @param[in] number + * + * @retval TLS_FWUP_STATUS_OK success + * @retval TLS_FWUP_STATE_UNDEF failed + * + * @note None + */ +int tls_fwup_set_update_numer(int number); + +/** + * @brief This function is used to get received update packet number + + * + * @param[in] None + * + * @retval return current packet number + * + * @note None + */ +int tls_fwup_get_current_update_numer(void); + + +/** + * @brief This function is used to get current session id + * + * @param[in] None + * + * @retval non-zoro session id + * @retval 0 error + * + * @note None + */ +int tls_fwup_get_current_session_id(void); + +/** + * @brief This function is used to check image header + * + * @param[in] None + * + * @retval TRUE: success + * @retval FALSE: failure + * + * @note None + */ +int tls_fwup_img_header_check(T_BOOTER *img_param); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WM_FWUP_H */ + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_mem1.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_mem1.h new file mode 100644 index 00000000..5fca0c78 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_mem1.h @@ -0,0 +1,201 @@ +/***************************************************************************** +* +* File Name : wm_mem.h +* +* Description: memory manager Module +* +* Copyright (c) 2014 Winner Micro Electronic Design Co., Ltd. +* All rights reserved. +* +* Author : dave +* +* Date : 2014-6-12 +*****************************************************************************/ + + +#ifndef WM_MEM_H +#define WM_MEM_H + + +#include "wm_type_def.h" +//#define WM_MEM_DEBUG 1 +#if WM_MEM_DEBUG + +#include "list.h" + +#define MEM_HEADER_PATTERN 0x76028412 +#define MEM_TAILER_PATTERN 0x83395627 +#define MEM_FREED_PATTERN 0x82962503 + +extern u32 alloc_heap_mem_bytes; +extern u32 alloc_heap_mem_blk_cnt; +extern u32 alloc_heap_mem_max_size; + +// +// Note: it's important that the size of MP_MEMORY_BLOCK structure +// be multiple of 16 bytes. +// +typedef struct _MEMORY_BLOCK { + + struct dl_list list; /**< Pointer to next and previous blocks */ + char *file; /**< name of the file which is doing the allocation */ + u32 pad; /**< pad to make the size of whole structure multiple of 16 bytes */ + u32 line; /**< line number where allocated */ + u32 length; /**< ulong index of trailer (=(length/4)-1 relative to data start */ + u32 header_pattern; /**< To help detect underflows. A trailer is also added to find overflows */ +} MEMORY_BLOCK, *PMEMORY_BLOCK; +typedef struct _MEMORY_PATTERN{ + u32 pattern0; + //u32 pattern1; + //u32 pattern2; + //u32 pattern3; +}MEMORY_PATTERN, *PMEMORY_PATTERN; +void mem_free_debug(void *p, char* file, int line); +#define tls_mem_free(p) mem_free_debug( p, __FILE__, __LINE__) +void *mem_alloc_debug(u32 size, char* file, int line); +void mem_free_allocated_blocks(void); +#define tls_mem_alloc(size) mem_alloc_debug(size, __FILE__, __LINE__) +void * mem_realloc_debug(void *mem_address, u32 size, char* file, int line); +#define tls_mem_realloc(mem_address, size) mem_realloc_debug(mem_address, size, __FILE__, __LINE__) + +void *mem_calloc_debug(u32 n,u32 size,char * file,int line); +#define tls_mem_calloc(n, size) mem_calloc_debug(n, size, __FILE__, __LINE__) +void tls_mem_alloc_info(void); +int is_safe_addr_debug(void* p, u32 len, char* file, int line); +#define tls_is_safe_addr(p, len) is_safe_addr_debug(p, len, __FILE__, __LINE__) +#if 1 +#define MEMCPY memcpy +#define SMEMCPY MEMCPY +#else +#define MEMCPY(dst,src,len) do { \ + if(tls_is_safe_addr(dst, len)){ \ + memcpy(dst,src,len);}}while(0) + +#define SMEMCPY(dst,src,len) do { \ + if(tls_is_safe_addr(dst, len)){ \ + memcpy(dst,src,len);}}while(0) +#endif +#else /* WM_MEM_DEBUG */ + +void * mem_alloc_debug(u32 size); +void mem_free_debug(void *p); +void * mem_realloc_debug(void *mem_address, u32 size); +void *mem_calloc_debug(u32 length, u32 size); + +/** + * @defgroup System_APIs System APIs + * @brief System APIs + */ + +/** + * @addtogroup System_APIs + * @{ + */ + +/** + * @defgroup MEM_APIs MEM APIs + * @brief memory manager APIs + */ + +/** + * @addtogroup MEM_APIs + * @{ + */ + +/** + * @brief This function is called by memory allocation + * + * @param[in] size + * + * @retval NULL malloc failed + * @retval pointer pointer to the address of the allocated memory + * + * @note None + */ +#define tls_mem_alloc(size) mem_alloc_debug(size) + +/** + * @brief This function is used to free memory + * + * @param None + * + * @return None + * + * @note None + */ +#define tls_mem_free mem_free_debug + +/** + * @brief This function is used to realloc memory + * + * @param None + * + * @retval NULL realloc failed + * @retval Pointer pointer to the address of the allocated memory + * + * @note None + */ +#define tls_mem_realloc mem_realloc_debug + +/** + * @brief This function is used to calloc memory + * + * @param None + * + * @retval NULL realloc failed + * @retval Pointer pointer to the address of the allocated memory + * + * @note None + */ +#define tls_mem_calloc mem_calloc_debug + +/** + * @brief This function is used to copy memory content from one address to another address + * + * @param[in] dst pointer to destination address + * @param[in] src pointer to source address + * @param[in] len length to copy + * + * @retval dst + * + * @note None + */ +#define MEMCPY(dst,src,len) memcpy(dst,src,len) + +/** + * @brief This function is used to copy memory content from one address to another address + * + * @param[in] dst pointer to destination address + * @param[in] src pointer to source address + * @param[in] len length to copy + * + * @retval dst + * + * @note None + */ +#define SMEMCPY(dst,src,len) memcpy(dst,src,len) + +/** + * @brief This function is used to get available memory + * + * @param[in] None + * + * @return None + * + * @note This api just can get coarse memory that is remained + */ +unsigned int tls_mem_get_avail_heapsize(void); + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WM_MEM_DEBUG */ + +#endif /* TLS_MEM_H */ + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_param.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_param.h new file mode 100644 index 00000000..51a5db7b --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_param.h @@ -0,0 +1,124 @@ +/***************************************************************************** +* +* File Name : tls_param.h +* +* Description: param manager Module +* +* Copyright (c) 2014 Winner Micro Electronic Design Co., Ltd. +* All rights reserved. +* +* Author : dave +* +* Date : 2014-6-12 +*****************************************************************************/ +#ifndef TLS_PARAM_H +#define TLS_PARAM_H +#include "wm_type_def.h" + + + +struct tls_param_quick_connect{ + bool quick_connect_en; + u8 chanId; +}; + +struct tls_sys_param { + struct tls_param_hardware_version hardware_version; + + struct tls_param_bssid bssid; + struct tls_param_ssid ssid; + u8 channel_enable; + u8 channel; + u8 wireless_region; + u8 encry; + u8 wireless_protocol; + u8 auto_create_adhoc; + u8 auto_retrycnt; + u8 auto_roam; + u8 auto_powersave; + u8 ssid_broadcast_enable; + u16 channellist; + struct tls_param_key key; + struct tls_param_bgr wbgr; + struct tls_param_wps wps; + + struct tls_param_ip ipcfg; + + u8 local_dnsname[32]; + u8 local_device_name[32]; + + struct tls_param_oray_client oray_client_setting; + + u8 upnp_enable; + + u8 always_online; + + u8 user_port_mode; + + u8 res_2; + + struct tls_param_uart uart_cfg; + + u8 auto_mode; + u8 res_3; + u16 transparent_trigger_length; + u16 transparent_trigger_period; + + struct tls_param_socket remote_socket_cfg; + + u32 debug_mode; + u32 res_4[2]; /* reserv and mark the end */ + + /*escape char*/ + u8 EscapeChar; + u8 EscReserved; + u16 EscapePeriod; /* unit: ms */ + + u8 IoMode; + u8 CmdMode; + u8 PassWord[6]; + + struct tls_webs_cfg WebsCfg; + u8 oneshotflag; + u8 oneshotres[2]; + struct tls_param_sha1 psk; + struct tls_param_original_key original_key; + struct tls_param_ssid original_ssid; + u8 auto_reconnect; + u8 res_5[3]; + + struct tls_param_quick_connect quick_connect; + + u8 key_changed; + u8 ssid_changed; + + struct tls_param_ssid apsta_ssid; + struct tls_param_sha1 apsta_psk; + u8 res_6[1]; + u8 channel4softap; + u8 encry4softap; + struct tls_param_key key4softap; + struct tls_param_ip ipcfg4softap; + struct tls_param_bgr wbgr4softap; + + char sntp_service1[32]; + char sntp_service2[32]; + char sntp_service3[32]; + struct tls_param_tem_offset params_tem; +}; + +struct tls_param_flash { + u32 magic; + u16 partition_num; + u16 modify_count; + u32 resv_1; + u16 resv_2; + u16 length; + struct tls_sys_param parameters; + u32 crc32; +}; + + +#endif /* WM_PARAM_H */ + + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_params.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_params.h new file mode 100644 index 00000000..eaf0cbb8 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_params.h @@ -0,0 +1,615 @@ +/** + * @file wm_params.h + * + * @brief param manager Module + * + * @author winnermicro + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ +#ifndef TLS_PARAMS_H +#define TLS_PARAMS_H + +#include "wm_type_def.h" + +/*************************************************************************************** + ID | Data Type +*************************************************************************************** +TLS_PARAM_ID_SSID | struct tls_param_ssid ssid +TLS_PARAM_ID_ENCRY | u8 encry +TLS_PARAM_ID_KEY | struct tls_param_key key +TLS_PARAM_ID_IP | struct tls_param_ip ipcfg +TLS_PARAM_ID_AUTOMODE | u8 auto_mode +TLS_PARAM_ID_DEFSOCKET | N/A +TLS_PARAM_ID_BSSID | struct tls_param_bssid bssid +TLS_PARAM_ID_CHANNEL | u8 channel +TLS_PARAM_ID_CHANNEL_EN | u8 channel_enable +TLS_PARAM_ID_COUNTRY_REGION | u8 wireless_region +TLS_PARAM_ID_WPROTOCOL | u8 wireless_protocol +TLS_PARAM_ID_ADHOC_AUTOCREATE | N/A +TLS_PARAM_ID_ROAMING | u8 auto_roam +TLS_PARAM_ID_AUTO_RETRY_CNT | N/A +TLS_PARAM_ID_WBGR | struct tls_param_bgr wbgr +TLS_PARAM_ID_USRINTF | N/A +TLS_PARAM_ID_AUTO_TRIGGER_LENGTH | N/A +TLS_PARAM_ID_DEBUG_MODE | N/A +TLS_PARAM_ID_HARDVERSION | struct tls_param_hardware_version hardware_v +TLS_PARAM_ID_BRDSSID | u8 ssid_broadcast_enable +TLS_PARAM_ID_DNSNAME | u8 local_dnsname[32] +TLS_PARAM_ID_DEVNAME | u8 local_device_name[32] +TLS_PARAM_ID_PSM | u8 auto_powersave +TLS_PARAM_ID_ORAY_CLIENT | N/A +TLS_PARAM_ID_UPNP | N/A +TLS_PARAM_ID_UART | struct tls_param_uart uart_cfg +TLS_PARAM_ID_WPS | struct tls_param_wps wps +TLS_PARAM_ID_AUTO_TRIGGER_PERIOD | N/A +TLS_PARAM_ID_ESCAPE_CHAR | N/A +TLS_PARAM_ID_ESCAPE_PERIOD | N/A +TLS_PARAM_ID_IO_MODE | N/A +TLS_PARAM_ID_CMD_MODE | N/A +TLS_PARAM_ID_PASSWORD | u8 PassWord[6] +TLS_PARAM_ID_CHANNEL_LIST | u16 channellist +TLS_PARAM_ID_WEBS_CONFIG | struct tls_webs_cfg WebsCfg +TLS_PARAM_ID_ONESHOT_CFG | u8 oneshotflag +TLS_PARAM_ID_SHA1 | N/A +TLS_PARAM_ID_ORIGIN_KEY | N/A +TLS_PARAM_ID_ORIGIN_SSID | N/A +TLS_PARAM_ID_AUTO_RECONNECT | u8 auto_reconnect +***************************************************************************************/ + +#define TLS_PARAM_STATUS_OK (0) +#define TLS_PARAM_STATUS_EINVALID (1) +#define TLS_PARAM_STATUS_EMEM (2) +#define TLS_PARAM_STATUS_EIO (3) +#define TLS_PARAM_STATUS_EPERM (4) +#define TLS_PARAM_STATUS_EINVALIDID (5) + +/** MACRO of Magic number initial value */ +#define TLS_PARAM_INIT_MAGIC (0xffffffff) +/** MACRO of Magic number valid value */ +#define TLS_PARAM_MAGIC (0x4947414d) + +/** MACRO of parameter partition number */ +#define TLS_PARAM_PARTITION_NUM (2) + +/** MACRO of parameter identity */ +#define TLS_PARAM_ID_ALL (-1) +#define TLS_PARAM_ID_SSID (0) +#define TLS_PARAM_ID_ENCRY (1) +#define TLS_PARAM_ID_KEY (2) +#define TLS_PARAM_ID_IP (3) +#define TLS_PARAM_ID_AUTOMODE (4) +#define TLS_PARAM_ID_DEFSOCKET (5) +#define TLS_PARAM_ID_BSSID (6) +#define TLS_PARAM_ID_CHANNEL (7) +#define TLS_PARAM_ID_CHANNEL_EN (8) +#define TLS_PARAM_ID_COUNTRY_REGION (9) +#define TLS_PARAM_ID_WPROTOCOL (10) +#define TLS_PARAM_ID_ADHOC_AUTOCREATE (11) +#define TLS_PARAM_ID_ROAMING (12) +#define TLS_PARAM_ID_AUTO_RETRY_CNT (13) +#define TLS_PARAM_ID_WBGR (14) +#define TLS_PARAM_ID_USRINTF (15) +#define TLS_PARAM_ID_AUTO_TRIGGER_LENGTH (16) +#define TLS_PARAM_ID_DEBUG_MODE (17) +#define TLS_PARAM_ID_HARDVERSION (18) +#define TLS_PARAM_ID_BRDSSID (19) +#define TLS_PARAM_ID_DNSNAME (20) +#define TLS_PARAM_ID_DEVNAME (21) +#define TLS_PARAM_ID_PSM (22) +#define TLS_PARAM_ID_ORAY_CLIENT (23) +#define TLS_PARAM_ID_UPNP (24) +#define TLS_PARAM_ID_UART (26) +#define TLS_PARAM_ID_WPS (27) +#define TLS_PARAM_ID_AUTO_TRIGGER_PERIOD (28) +#define TLS_PARAM_ID_ESCAPE_CHAR (29) +#define TLS_PARAM_ID_ESCAPE_PERIOD (30) +#define TLS_PARAM_ID_IO_MODE (31) +#define TLS_PARAM_ID_CMD_MODE (32) +#define TLS_PARAM_ID_PASSWORD (33) +#define TLS_PARAM_ID_CHANNEL_LIST (34) +#define TLS_PARAM_ID_WEBS_CONFIG (35) +#define TLS_PARAM_ID_ONESHOT_CFG (36) +#define TLS_PARAM_ID_SHA1 (37) +#define TLS_PARAM_ID_ORIGIN_KEY (38) +#define TLS_PARAM_ID_ORIGIN_SSID (39) +#define TLS_PARAM_ID_AUTO_RECONNECT (40) +#define TLS_PARAM_ID_QUICK_CONNECT (41) +#define TLS_PARAM_ID_KEY_CHANGE (42) +#define TLS_PARAM_ID_SSID_CHANGE (43) +#define TLS_PARAM_ID_SOFTAP_SSID (44) +#define TLS_PARAM_ID_SOFTAP_PSK (45) +#define TLS_PARAM_ID_SOFTAP_ENCRY (46) +#define TLS_PARAM_ID_SOFTAP_KEY (47) +#define TLS_PARAM_ID_SOFTAP_IP (48) +#define TLS_PARAM_ID_SOFTAP_CHANNEL (49) +#define TLS_PARAM_ID_SOFTAP_WBGR (50) + +#define TLS_PARAM_ID_SNTP_SERVER1 (51) +#define TLS_PARAM_ID_SNTP_SERVER2 (52) +#define TLS_PARAM_ID_SNTP_SERVER3 (53) +#define TLS_PARAM_ID_TEM_OFFSET (54) + +#define TLS_PARAM_ID_MAX (55) +/** MACRO of Physical moe of Ieee802.11 */ +#define TLS_PARAM_PHY_11BG_MIXED (0) +#define TLS_PARAM_PHY_11B (1) +#define TLS_PARAM_PHY_11BGN_MIXED (2) +/** MACRO of Ieee802.11 Tx Rate for parameter set */ +#define TLS_PARAM_TX_RATEIDX_1M (0) +#define TLS_PARAM_TX_RATEIDX_2M (1) +#define TLS_PARAM_TX_RATEIDX_5_5M (2) +#define TLS_PARAM_TX_RATEIDX_11M (3) +#define TLS_PARAM_TX_RATEIDX_6M (4) +#define TLS_PARAM_TX_RATEIDX_9M (5) +#define TLS_PARAM_TX_RATEIDX_12M (6) +#define TLS_PARAM_TX_RATEIDX_18M (7) +#define TLS_PARAM_TX_RATEIDX_24M (8) +#define TLS_PARAM_TX_RATEIDX_36M (9) +#define TLS_PARAM_TX_RATEIDX_48M (10) +#define TLS_PARAM_TX_RATEIDX_54M (11) +#define TLS_PARAM_TX_RATEIDX_MCS0 (12) +#define TLS_PARAM_TX_RATEIDX_MCS1 (13) +#define TLS_PARAM_TX_RATEIDX_MCS2 (14) +#define TLS_PARAM_TX_RATEIDX_MCS3 (15) +#define TLS_PARAM_TX_RATEIDX_MCS4 (16) +#define TLS_PARAM_TX_RATEIDX_MCS5 (17) +#define TLS_PARAM_TX_RATEIDX_MCS6 (18) +#define TLS_PARAM_TX_RATEIDX_MCS7 (19) +#define TLS_PARAM_TX_RATEIDX_MCS8 (20) +#define TLS_PARAM_TX_RATEIDX_MCS9 (21) +#define TLS_PARAM_TX_RATEIDX_MCS10 (22) +#define TLS_PARAM_TX_RATEIDX_MCS11 (23) +#define TLS_PARAM_TX_RATEIDX_MCS12 (24) +#define TLS_PARAM_TX_RATEIDX_MCS13 (25) +#define TLS_PARAM_TX_RATEIDX_MCS14 (26) +#define TLS_PARAM_TX_RATEIDX_MCS15 (27) +#define TLS_PARAM_TX_RATEIDX_MCS32 (28) + + +/** MACRO of SSID Broadcast */ +#define TLS_PARAM_SSIDBRD_DISABLE (0) +#define TLS_PARAM_SSIDBRD_ENABLE (1) + +#define TLS_PARAM_ROAM_DISABLE (0) +#define TLS_PARAM_ROAM_ENABLE (1) + +/** MACRO of Power Saving Mode */ +#define TLS_PARAM_PSM_DISABLE (0) +#define TLS_PARAM_PSM_ENABLE (1) + +#define TLS_PARAM_DDNS_DISABLE (0) +#define TLS_PARAM_DDNS_ENABLE (1) + +#define TLS_PARAM_AUTO_CREATE_ADHOC_DISABLE (0) +#define TLS_PARAM_AUTO_CREATE_ADHOC_ENABLE (1) + +#define TLS_PARAM_WPS_DISABLE (0) +#define TLS_PARAM_WPS_ENABLE (1) +#define TLS_PARAM_WPS_MODE_PIN (0) +#define TLS_PARAM_WPS_MODE_PBC (1) +#define TLS_PARAM_WPS_FLAG_NEGOTIATED (1 << 0) + +#define TLS_PARAM_UPNP_DISABLE (0) +#define TLS_PARAM_UPNP_ENABLE (1) + +/** MACRO of IEEE802.11 Work MODE */ +#define TLS_PARAM_IEEE80211_INFRA (1) +#define TLS_PARAM_IEEE80211_ADHOC (2) +#define TLS_PARAM_IEEE80211_SOFTAP (4) + +/** MACRO of Command or Transparent Mode */ +#define TLS_PARAM_MANUAL_MODE (0) +#define TLS_PARAM_AUTO_MODE (1) + +#define TLS_PARAM_ALWAYS_ONLINE_ENABLE (1) +#define TLS_PARAM_ALWAYS_ONLINE_DISABLE (0) + +/** MACRO of DHCP ENABLE or DISABLE */ +#define TLS_PARAM_DHCP_ENABLE (1) +#define TLS_PARAM_DHCP_DISABLE (0) + +/** MACRO of COUNTRY CODE for channel number */ +#define TLS_PARAM_REGION_0_BG_BAND (0) /* 1-11 */ +#define TLS_PARAM_REGION_1_BG_BAND (1) /* 1-13 */ +#define TLS_PARAM_REGION_2_BG_BAND (2) /* 10-11 */ +#define TLS_PARAM_REGION_3_BG_BAND (3) /* 10-13 */ +#define TLS_PARAM_REGION_4_BG_BAND (4) /* 14 */ +#define TLS_PARAM_REGION_5_BG_BAND (5) /* 1-14 */ +#define TLS_PARAM_REGION_6_BG_BAND (6) /* 3-9 */ +#define TLS_PARAM_REGION_7_BG_BAND (7) /* 5-13 */ +#define TLS_PARAM_REGION_MAXIMUM_BG_BAND TLS_PARAM_REGION_7_BG_BAND + +/** MACRO of ENCRYPT TYPE */ +#define TLS_PARAM_ENCRY_OPEN (0) +#define TLS_PARAM_ENCRY_WEP64 (1) +#define TLS_PARAM_ENCRY_WEP128 (2) +#define TLS_PARAM_ENCRY_WPA_PSK_TKIP (3) +#define TLS_PARAM_ENCRY_WPA_PSK_AES (4) +#define TLS_PARAM_ENCRY_WPA2_PSK_TKIP (5) +#define TLS_PARAM_ENCRY_WPA2_PSK_AES (6) + +/** MACRO of USER INTERFACE TYPE */ +#define TLS_PARAM_USR_INTF_LUART (0) +#define TLS_PARAM_USR_INTF_HUART (1) +#define TLS_PARAM_USR_INTF_HSPI (2) +#define TLS_PARAM_USR_INTF_HSDIO (3) + +/** MACRO of UART BAUDRATE */ +#define TLS_PARAM_UART_BAUDRATE_B600 (600) +#define TLS_PARAM_UART_BAUDRATE_B1200 (1200) +#define TLS_PARAM_UART_BAUDRATE_B1800 (1800) +#define TLS_PARAM_UART_BAUDRATE_B2400 (2400) +#define TLS_PARAM_UART_BAUDRATE_B4800 (4800) +#define TLS_PARAM_UART_BAUDRATE_B9600 (9600) +#define TLS_PARAM_UART_BAUDRATE_B19200 (19200) +#define TLS_PARAM_UART_BAUDRATE_B38400 (38400) +#define TLS_PARAM_UART_BAUDRATE_B57600 (57600) +#define TLS_PARAM_UART_BAUDRATE_B115200 (115200) +#define TLS_PARAM_HUART_BAUDRATE_B230400 (230400) +#define TLS_PARAM_HUART_BAUDRATE_B460800 (460800) +#define TLS_PARAM_HUART_BAUDRATE_B921600 (921600) +#define TLS_PARAM_HUART_BAUDRATE_B1000000 (1000000) +#define TLS_PARAM_HUART_BAUDRATE_B1250000 (1250000) +#define TLS_PARAM_HUART_BAUDRATE_B1500000 (1500000) +#define TLS_PARAM_HUART_BAUDRATE_B2000000 (2000000) + +/** MACRO of UART PARITY */ +#define TLS_PARAM_UART_PARITY_NONE (0) +#define TLS_PARAM_UART_PARITY_EVEN (1) +#define TLS_PARAM_UART_PARITY_ODD (2) +#define TLS_PARAM_UART_PARITY_MARK (3) +#define TLS_PARAM_UART_PARITY_SPACE (4) + +/** MACRO of UART STOP BITS */ +#define TLS_PARAM_UART_STOPBITS_1BITS (0) +#define TLS_PARAM_UART_STOPBITS_2BITS (1) + +/** MACRO of UART FLOW CONTROL */ +#define TLS_PARAM_UART_FLOW_DISABLE (0) +#define TLS_PARAM_UART_FLOW_ENABLE (1) +#define TLS_PARAM_HSPI_MAX_SCLK (33000000) +/** MACRO of SOCKET PARAMETER */ +#define TLS_PARAM_SOCKET_TCP (0) +#define TLS_PARAM_SOCKET_UDP (1) +#define TLS_PARAM_SOCKET_CLIENT (0) +#define TLS_PARAM_SOCKET_SERVER (1) +#define TLS_PARAM_SOCKET_DEFAULT_PORT (60000) + +/** Structure of hardware parameter */ +struct tls_param_hardware_version { + u8 mark; + u8 main; + u8 sub; + u8 material; + u8 year; + u8 week; + u8 res[2]; +}; + +/** Structure of specified BSSID parameter */ +struct tls_param_bssid { + u8 bssid_enable; + u8 res; + u8 bssid[6]; +}; + +/** Structure of SSID parameter */ +struct tls_param_ssid { + u8 ssid[32]; + u32 ssid_len; +}; + +/** Structure of TEM parameter */ +struct tls_param_tem_offset { + u8 offset_len; + s32 offset; +}; + +/** Structure of KEY parameter */ +struct tls_param_key { + u8 psk[64]; + u8 key_length; + u8 key_index; + u8 key_format; + u8 res; +}; + +/** Structure of original KEY parameter */ +struct tls_param_original_key { + u8 psk[64]; + u32 key_length; +}; + +/** Structure of SHA1 KEY parameter */ +struct tls_param_sha1{ + u8 psk_set; + u8 psk[32]; +}; + +/** Structure of 802.11 bgn rate parameter */ +struct tls_param_bgr { + u8 bg; + u8 max_rate; + u8 res[2]; +}; + +/** Structure of IP parameter */ +struct tls_param_ip { + u8 dhcp_enable; + u8 res[3]; + u8 ip[4]; + u8 netmask[4]; + u8 gateway[4]; + u8 dns1[4]; + u8 dns2[4]; +}; + +/** Structure of uart parameter */ +struct tls_param_uart { + u32 baudrate; + u8 stop_bits; + u8 parity; + u8 flow; + u8 charsize; +}; + +/** Structure of socket parameter */ +struct tls_param_socket { + u8 protocol; + u8 client_or_server; + u16 port_num; + u8 host[32]; +}; + +struct tls_param_wps { + u8 wps_enable; + u8 mode; + u8 flag; + u8 res; + u8 pin[8]; +}; + +/** Structure of oray client */ +struct tls_param_oray_client { + u32 oray_client_enable; + u8 oray_client_user[32]; + u8 oray_client_pass[32]; +}; + +/** Structure of web server parameter */ +struct tls_webs_cfg { + u8 AutoRun; + u8 Reserved; + u16 PortNum; +}; + +/** Structure of user default parameter */ +typedef struct tls_user_param{ + + u8 wireless_protocol; + u8 auto_mode; + u8 dhcp_enable; + u8 user_port_mode; + + u8 ip[4]; + u8 netmask[4]; + u8 gateway[4]; + u8 dns[4]; + + u32 baudrate; + + u8 socket_protocol; + u8 socket_client_or_server; + u16 socket_port_num; + u8 socket_host[32]; + u8 auto_powersave; + u8 PassWord[6]; +}ST_Wm_User_Param; + +/** + * @defgroup System_APIs System APIs + * @brief System APIs + */ + +/** + * @addtogroup System_APIs + * @{ + */ + +/** + * @defgroup Param_APIs Param APIs + * @brief Param manager APIs + */ + +/** + * @addtogroup Param_APIs + * @{ + */ + +/** + * @brief This function is used to initialize parameter's manamge module + * + * @param[in] None + * + * @retval TLS_PARAM_STATUS_OK init success + * @retval TLS_PARAM_STATUS_EMEM memory error + * @retval TLS_PARAM_STATUS_EIO io error + * @retval TLS_PARAM_STATUS_EPERM magic number error + * + * @note None + */ +int tls_param_init(void); + +/** + * @brief This function is used to load the system's default + parameters + * + * @param[in] None + * + * @return None + * + * @note This function read user defined parameters first, + if wrong, all the parameters restore factory settings + */ +void tls_param_load_factory_default(void); + +/** + * @brief This function is used to set one system parameter by its id + * + * @param[in] id param id,from TLS_PARAM_ID_SSID + to (TLS_PARAM_ID_MAX - 1) + * @param[in] *argv store parameters + * @param[in] to_flash whether the parameter is written to flash, + 1:write to flash,0:only write memory + * + * @retval TLS_PARAM_STATUS_OK set success + * @retval TLS_PARAM_STATUS_EINVALID invalid param + * + * @note None + */ +int tls_param_set(int id, void *argv, bool to_flash); + +/** + * @brief This function is used to get one system parameter by its id. + * + * @param[in] id param id,from TLS_PARAM_ID_SSID + to (TLS_PARAM_ID_MAX - 1) + * @param[in] *argv store parameters + * @param[in] from_flash whether the parameter is readed from flash, + 1 read from flash,0 read from memory + * + * @retval TLS_PARAM_STATUS_OK success + * @retval TLS_PARAM_STATUS_EINVALID invalid param + * + * @note None + */ +int tls_param_get(int id, void *argv, bool from_flash); + +/** + * @brief This function is used to write parameter into flash + * + * @param[in] id param id,from TLS_PARAM_ID_ALL + to (TLS_PARAM_ID_MAX - 1) + * + * @retval TLS_PARAM_STATUS_OK success + * @retval TLS_PARAM_STATUS_EINVALID invalid param + * @retval TLS_PARAM_STATUS_EIO read or write flash error + * + * @note None + */ +int tls_param_to_flash(int id); + +/** + * @brief This function is used to recovery the parameters from + the backup area to the parameter area,and load them into ram + * + * @param[in] None + * + * @return None + * + * @note None + */ +void tls_restore_param_from_backup(void); + +/** + * @brief This function is used to load default parametes into ram + + * + * @param[in] None + * + * @retval TLS_PARAM_STATUS_OK set success + * @retval TLS_PARAM_STATUS_EINVALID parameter wrong + * @retval TLS_PARAM_STATUS_EIO read or write falsh error + * + * @note This function read user defined parameters first, + if wrong, all the parameters restore factory settings + */ +int tls_param_to_default(void); + +/** + * @brief This function is used to write user's parameters into the + flash + * + * @param[in] None + * + * @retval TLS_PARAM_STATUS_OK success + * @retval other failed + * + * @note None + */ +int tls_param_save_user_default(void); + +/** + * @brief This function is used to modify user's default parameters, + then write them into flash + * + * @param[in] *user_param + * + * @retval TLS_PARAM_STATUS_OK success + * @retval other failed + * + * @note None + */ +int tls_param_save_user(struct tls_user_param *user_param); + +/** + * @brief This function is used to get updp mode.(updp:update user + default parameters) + * + * @param[in] None + * + * @retval update mode + * + * @note None + */ +u8 tls_param_get_updp_mode(void); + +/** + * @brief This function is used to set updp mode + * + * @param[in] mode + * + * @return None + * + * @note None + */ +void tls_param_set_updp_mode(u8 mode); + +/** + * @brief This function is used to get program param + * + * @param[in] *pBase pointer to save base address + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +int tls_param_get_program_param(u32 *pBase); + +/** + * @brief This function is used to set program base,image len,and + checksum + * + * @param[in] base base address + * @param[in] totallen total length of the image + * @param[in] checksum checksum value of the image + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +int tls_param_set_program_param(u32 base, u32 totallen, u32 checksum); + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WM_PARAM_H */ + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_wl_mbox.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_wl_mbox.h new file mode 100644 index 00000000..7ceacb42 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_wl_mbox.h @@ -0,0 +1,115 @@ +/** + * @file wm_wl_mbox.h + * + * @brief mailbox (mbox) APIs + * + * @author dave + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ +#ifndef __TLS_WL_MBOX_H__ +#define __TLS_WL_MBOX_H__ + +#include "wm_type_def.h" +#include "wm_osal.h" + +/** max value of time out */ +#define SYS_ARCH_TIMEOUT 0xffffffffUL + +/** pointer to the mailbox */ +typedef tls_os_queue_t * tls_mbox_t; + +/** + * @defgroup System_APIs System APIs + * @brief System APIs + */ + +/** + * @addtogroup System_APIs + * @{ + */ + +/** + * @defgroup MBOX_APIs MBOX APIs + * @brief Software mailbox APIs + */ + +/** + * @addtogroup MBOX_APIs + * @{ + */ + +/** + * @brief Create a malibox + * + * @param[out] *mbox pointer to the mailbox + * @param[in] size size of mailbox + * + * @retval TLS_OS_SUCCESS success + * @retval TLS_OS_ERROR failed + * + * @note None + */ +s8 tls_mbox_new(tls_mbox_t *mbox, int size); + +/** + * @brief Check if an mbox is valid/allocated + * + * @param[in] mbox pointer to the mailbox + * + * @retval 0 invalid + * @retval 1 valid + * + * @note None + */ +int tls_mbox_valid(tls_mbox_t mbox); + +/** + * @brief Sends a message to a mailbox + * + * @param[in] mbox pointer to the mailbox + * @param[in] *msg pointer to the message to be post + * + * @return None + * + * @note None + */ +void tls_mbox_post(tls_mbox_t mbox, void *msg); + +/** + * @brief Posts the msg to the mailbox. + * + * @param[in] mbox pointer to the mailbox + * @param[in] *msg pointer to the message to be post + * + * @retval TLS_OS_SUCCESS success + * @retval TLS_OS_ERROR failed + * + * @note this function have to block until the "msg" is really posted. + */ +s8 tls_mbox_trypost(tls_mbox_t mbox, void *msg); + +/** + * @brief Waits for a message within specified time + * + * @param[in] mbox pointer to the mailbox + * @param[out] **msg pointer to the message to be received + * @param[in] timeout the specified time + * + * @retval SYS_ARCH_TIMEOUT time out + * @retval other time of elapsed + * + * @note None + */ +u32 tls_arch_mbox_fetch(tls_mbox_t mbox, void **msg, u32 timeout); + +/** + * @} + */ + +/** + * @} + */ + +#endif + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_wl_task.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_wl_task.h new file mode 100644 index 00000000..a05e0901 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_wl_task.h @@ -0,0 +1,233 @@ +/** + * @file wm_wl_task.h + * + * @brief task APIs + * + * @author dave + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ +#ifndef __TLS_WL_TASK_H__ +#define __TLS_WL_TASK_H__ + +#include "wm_type_def.h" +#include "wm_wl_mbox.h" +#include "wm_wl_timers.h" +//#include "ithread.h" + +#define TLS_TASK_START_PRIO 0 +#define TASK_WL_PRIO 9 +#define TASK_WL_PRIO_MAX 12 +#define TLS_SUPPLICANT_TASK_PRIO (TASK_WL_PRIO_MAX + 1) +#define TLS_SUPPLICANT_TIMER_TASK_PRIO (TASK_WL_PRIO_MAX + 2) +#define TLS_LWIP_TASK_PRIO (TASK_WL_PRIO_MAX + 3) +#define TLS_SYS_TASK_PRIO (TASK_WL_PRIO_MAX + 5) +#define TLS_HOSTIF_TASK_PRIO (TASK_WL_PRIO_MAX + 6) +#define TLS_SPI_SCHEDULER_TASK_PRIO (TASK_WL_PRIO_MAX + 7) +#define TLS_FWUP_TASK_PRIO (TASK_WL_PRIO_MAX + 8) +#define TLS_HTTP_CLIENT_TASK_PRIO (TASK_WL_PRIO_MAX + 9) +#define AP_SOCKET_S_TASK_PRIO (TASK_WL_PRIO_MAX + 10) +#define TLS_UPNP_TASK_PRIO (TASK_WL_PRIO_MAX + 11) +#define TLS_ONESHOT_TASK_PRIO (TASK_WL_PRIO_MAX + 15) +#define TLS_ONESHOT_SPEC_TASK_PRIO (TASK_WL_PRIO_MAX + 16) + + +#define TLS_MBOX_ALL_COUNT 8 +#define TLS_MBOX_ID_WL_TASK 0 +#define TLS_MBOX_ID_HOSTIF_TASK 1 +#define TLS_MBOX_ID_JDCLOUD_SERVER 2 +#define TLS_MBOX_ID_JDCLOUD_DATA 3 +#define TLS_MBOX_ID_UPNP_HD 4 +#define TLS_MBOX_ID_UPNP_COMMON 5 +#define TLS_MBOX_ID_UPNP_GENA 6 +#define TLS_MBOX_ID_UPNP_MINISERVER 7 + +#define TLS_TIMEO_ALL_COUONT 9 +#define TLS_TIMEO_ID_NULL 0 +#define TLS_TIMEO_ID_WL_TASK 1 +#define TLS_TIMEO_ID_HOSTIF_TASK 2 +#define TLS_TIMEO_ID_JDCLOUD_SERVER 3 +#define TLS_TIMEO_ID_JDCLOUD_DATA 4 +#define TLS_TIMEO_ID_UPNP_HD 5 +#define TLS_TIMEO_ID_UPNP_COMMON 6 +#define TLS_TIMEO_ID_UPNP_GENA 7 +#define TLS_TIMEO_ID_UPNP_MINISERVER 8 + +#define TLS_MSG_ALL_COUONT 9 +#define TLS_MSG_ID_TX_MGMT_CMPLT 0 +#define TLS_MSG_ID_MLME_TASK 1 +#define TLS_MSG_ID_UART_SENT_FREE 2 +#define TLS_MSG_ID_UART0_RX 3 +#define TLS_MSG_ID_HSPI_RX_CMD 4 +#define TLS_MSG_ID_HSPI_RX_DATA 5 +#define TLS_MSG_ID_HSPI_TX_DATA 6 +#define TLS_MSG_ID_TX_DATA_CMPLT 7 +#define TLS_MSG_ID_UART1_RX 8 + +/** pointer to the semaphore */ +typedef tls_os_sem_t * tls_sem_t; + +/** Thread start routine */ +typedef void *(*start_routine)(void *arg); + +/** message type of task */ +enum task_msg_type { + TASK_MSG_TIMEOUT, + TASK_MSG_UNTIMEOUT, + TASK_MSG_CALLBACK_WITH_BLOCK, + TASK_MSG_CALLBACK, + TASK_MSG_CALLBACK_STATIC, + TASK_MSG_NULL +}; + +/** message of task */ +struct task_msg { + enum task_msg_type type; + tls_sem_t *sem; + union { + struct { + start_routine function; + void *ctx; + } cb; + struct { + start_routine function; + void *ctx; + u8 cnt; + } cbs; + struct { + u32 msecs; + tls_timeout_handler h; + void *arg; + } tmo; + } msg; +}; + +/** task parameters */ +struct task_parameter{ + u8 task_id; /**< task ID */ + const char * name; /**< task name */ + u8 *stk_start; /**< start address of task stack */ + u32 stk_size; /**< size of task stack */ + u8 mbox_size; /**< size of mailbox */ + u8 mbox_id; /**< mailbox ID */ + u8 timeo_id; /**< timer ID */ +}; + +/** + * @defgroup System_APIs System APIs + * @brief System APIs + */ + +/** + * @addtogroup System_APIs + * @{ + */ + +/** + * @defgroup Task_APIs Task APIs + * @brief Software task APIs + */ + +/** + * @addtogroup Task_APIs + * @{ + */ + +/** + * @brief Task initialized + * + * @param None + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +s8 tls_wl_task_init(void); + +/** + * @brief Running the task + * + * @param[in] *task_param pointer to the task parameters + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +s8 tls_wl_task_run(struct task_parameter *task_param); + +/** + * @brief Running the callback function + * + * @param[in] *task_param pointer to the task parameters + * @param[in] function the callback function + * @param[in] *ctx parameter of the callback function + * @param[in] block + * @param[in] msg_id + * + * @retval TLS_OS_SUCCESS success + * @retval TLS_OS_ERROR failed + * + * @note None + */ +s8 tls_wl_task_callback_static(struct task_parameter *task_param, + start_routine function, void *ctx, u8 block, u8 msg_id); + +/** + * @brief Running the callback function + * + * @param[in] *task_param pointer to the task parameters + * @param[in] function the callback function + * @param[in] *ctx parameter of the callback function + * @param[in] block + * + * @retval TLS_OS_SUCCESS success + * @retval TLS_OS_ERROR failed + * + * @note None + */ +s8 tls_wl_task_callback(struct task_parameter *task_param, + start_routine function, void *ctx, u8 block); + +/** + * @brief Add a timer to the task + * + * @param[in] *task_param pointer to the task parameters + * @param[in] msecs timer value + * @param[in] h the callback function + * @param[in] *arg parameter of the callback function + * + * @retval TLS_OS_SUCCESS success + * @retval TLS_OS_ERROR failed + * + * @note None + */ +s8 tls_wl_task_add_timeout(struct task_parameter *task_param, u32 msecs, + tls_timeout_handler h, void *arg); + +/** + * @brief Stop or delay the timer to expire. + * + * @param[in] *task_param pointer to the task parameters + * @param[in] h the callback function + * @param[in] *arg parameter of the callback function + * + * @retval TLS_OS_SUCCESS success + * @retval TLS_OS_ERROR failed + * + * @note None + */ +s8 tls_wl_task_untimeout(struct task_parameter *task_param, + tls_timeout_handler h, void *arg); + +/** + * @} + */ + +/** + * @} + */ + +#endif + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_wl_timers.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_wl_timers.h new file mode 100644 index 00000000..78baacf1 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/platform/wm_wl_timers.h @@ -0,0 +1,102 @@ +/** + * @file wm_wl_timers.h + * + * @brief task APIs + * + * @author dave + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ +#ifndef __TLS_WL_TIMERS_H__ +#define __TLS_WL_TIMERS_H__ + +#include "wm_type_def.h" +#include "wm_wl_mbox.h" + +/** callback function of time out */ +typedef void (* tls_timeout_handler)(void *arg); + +/** + * @defgroup System_APIs System APIs + * @brief System APIs + */ + +/** + * @addtogroup System_APIs + * @{ + */ + +/** + * @defgroup Timer_APIs Timer APIs + * @brief Software timer APIs + */ + +/** + * @addtogroup Timer_APIs + * @{ + */ + +/** + * @brief Create a one-shot timer (aka timeout) + * + * @param[in] timeo_assigned timer NO. by assigned + * @param[in] msecs time in milliseconds after that the timer should expire + * @param[in] handler callback function that would be called by the timeout + * @param[in] *arg callback argument that would be passed to handler + * + * @return None + * + * @note While waiting for a message using sys_timeouts_mbox_fetch() + */ +void tls_timeout_p(u8 timeo_assigned, u32 msecs, tls_timeout_handler handler, void *arg); + +/** + * @brief Go through timeout list (for this task only) and remove the first + * matching entry, even though the timeout has not been triggered yet + * + * @param[in] timeo_assigned timer NO. by assigned + * @param[in] handler callback function that would be called by the timeout + * @param[in] *arg callback argument that would be passed to handler + * + * @return None + * + * @note None + */ +void tls_untimeout_p(u8 timeo_assigned, tls_timeout_handler handler, void *arg); + +/** + * @brief Wait (forever) for a message to arrive in an mbox. + * While waiting, timeouts are processed + * + * @param[in] timeo_assigned timer NO. by assigned + * @param[in] mbox the mbox to fetch the message from + * @param[out] **msg the place to store the message + * + * @return None + * + * @note None + */ +void tls_timeouts_mbox_fetch_p(u8 timeo_assigned, tls_mbox_t mbox, void **msg); + +/** + * @brief Initialize the timer + * + * @param None + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +s8 tls_wl_timer_init(void); + +/** + * @} + */ + +/** + * @} + */ + +#endif + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/random.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/random.h new file mode 100644 index 00000000..7872f8aa --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/random.h @@ -0,0 +1,80 @@ +/* + * @file random.h + * @brief Random number generator + * @copyright (c) 2010-2011, Jouni Malinen + * + * + * @note This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * @note Alternatively, this software may be distributed under the terms of BSD + * license. + * + * @note See README and COPYING for more details. + */ + +#ifndef RANDOM_H +#define RANDOM_H + +void random_deinit(void); + +/** + * @defgroup System_APIs System APIs + * @brief System APIs + */ + +/** + * @addtogroup System_APIs + * @{ + */ + +/** + * @defgroup Random_APIs Random APIs + * @brief Random APIs + */ + +/** + * @addtogroup Random_APIs + * @{ + */ + +/** + * @brief This function is used to add number to random pool + * + * @param[in] *buf number to add + * @param[in] len number count + * + * @return None + * + * @note None + */ +void random_add_randomness(const void *buf, size_t len); +/** + * @brief This function is used to get random number with len from + random pool + * + * @param[in] *buf used to save random number + * @param[in] len length of random number + * + * @retval 0 success + * @retval other failed + * + * @note None + */ +int random_get_bytes(void *buf, size_t len); + +/** + * @} + */ + +/** + * @} + */ + +#define random_mark_pool_ready() do { } while (0) +/** random pool ready */ +#define random_pool_ready() 1 + +#endif /* RANDOM_H */ + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/wm_config.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/wm_config.h new file mode 100644 index 00000000..318468b5 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/wm_config.h @@ -0,0 +1,83 @@ +/** + * @file wm_config.h + * + * @brief w600 chip inferface configure + * + * @author dave + * + * @copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#ifndef __WM_CONFIG_H__ +#define __WM_CONFIG_H__ + +#define CFG_ON 1 +#define CFG_OFF 0 + +#define WM_CONFIG_DEBUG_UART1 CFG_OFF /*PRINTF PORT USE UART1*/ + +/**Driver Support**/ +#define TLS_CONFIG_HS_SPI CFG_ON /*High Speed SPI*/ +#define TLS_CONFIG_LS_SPI CFG_ON /*Low Speed SPI*/ +#define TLS_CONFIG_UART CFG_ON /*UART*/ + +/**Host Interface&Command**/ +#define TLS_CONFIG_HOSTIF CFG_ON +#define TLS_CONFIG_AT_CMD (CFG_ON && TLS_CONFIG_HOSTIF) +#define TLS_CONFIG_RI_CMD (CFG_ON && TLS_CONFIG_HOSTIF) +#define TLS_CONFIG_RMMS CFG_OFF + +//LWIP CONFIG +#define TLS_CONFIG_LWIP_VER2_0_3 CFG_ON +#define TLS_CONFIG_IPV4 CFG_ON //must ON +#define TLS_CONFIG_IPV6 CFG_OFF +#define TLS_CONFIG_DHCP_OPTION60 "Winnermicro:W600_01" + +/** SOCKET CONFIG **/ +#define TLS_CONFIG_SOCKET_STD CFG_ON +#define TLS_CONFIG_SOCKET_RAW CFG_ON +#define TLS_CONFIG_CMD_USE_RAW_SOCKET (CFG_ON && TLS_CONFIG_SOCKET_RAW) + + + +#define TLS_CONFIG_HARD_CRYPTO CFG_ON + +#define TLS_CONFIG_USE_POLARSSL CFG_OFF +#define TLS_CONFIG_SERVER_SIDE_SSL (CFG_OFF && TLS_CONFIG_HTTP_CLIENT_SECURE) /*MUST configure TLS_CONFIG_HTTP_CLIENT_SECURE CFG_ON */ + + +/** HTTP CLIENT **/ +/* +HTTP Lib +HTTPS Lib +SSL LIB +CRYPTO +*/ +#define TLS_CONFIG_HTTP_CLIENT (CFG_ON) +#define TLS_CONFIG_HTTP_CLIENT_PROXY CFG_OFF +#define TLS_CONFIG_HTTP_CLIENT_AUTH_BASIC CFG_OFF +#define TLS_CONFIG_HTTP_CLIENT_AUTH_DIGEST CFG_OFF +#define TLS_CONFIG_HTTP_CLIENT_AUTH (TLS_CONFIG_HTTP_CLIENT_AUTH_BASIC || TLS_CONFIG_HTTP_CLIENT_AUTH_DIGEST) +#define TLS_CONFIG_HTTP_CLIENT_SECURE CFG_OFF +#define TLS_CONFIG_HTTP_CLIENT_TASK (CFG_ON && TLS_CONFIG_HTTP_CLIENT) + + + +/**IGMP**/ +#define TLS_CONFIG_IGMP CFG_ON + +/** UPNP AND DLNA**/ +#define TLS_CONFIG_UPNP CFG_OFF +#define TLS_CONFIG_DLNA CFG_OFF && TLS_CONFIG_UPNP + + +#define TLS_CONFIG_NTP CFG_ON + + +#define VERC_DNS_OPT CFG_ON +#define VERC_LWIP_OPT CFG_ON + + + +#include "wm_ram_config.h" +#endif /*__WM_CONFIG_H__*/ + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/wm_debug.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/wm_debug.h new file mode 100644 index 00000000..6e1e73d4 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/wm_debug.h @@ -0,0 +1,127 @@ +/** + * @file wm_debug.h + * + * @brief debug Module APIs + * + * @author dave + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#ifndef WM_DEBUG_H +#define WM_DEBUG_H + +#include +#include +#include "wm_config.h" + +/* 0x00000000 - 0x80000000 */ +/** Define the debugging switch: on */ +#define TLS_DBG_ON 1 +/** Define the debugging switch: off */ +#define TLS_DBG_OFF 0 + + +/* 0x0000000F - 0x00000001 */ +/** Define the debugging level: info */ +#define TLS_DBG_LEVEL_INFO TLS_DBG_OFF +/** Define the debugging level: warning */ +#define TLS_DBG_LEVEL_WARNING TLS_DBG_OFF +/** Define the debugging level: error */ +#define TLS_DBG_LEVEL_ERR TLS_DBG_OFF +/** Define the debugging level: dump */ +#define TLS_DBG_LEVEL_DUMP TLS_DBG_OFF + +/** general debug info switch, default: off */ +#define TLS_GENERAL_DBG TLS_DBG_OFF + + +#define __TLS_DBGPRT_INFO(fmt, ...) \ +do { \ + u32 time = tls_os_get_time(); \ + printf("[WM_I] <%d.%02d> %s : "fmt, (time/100), (time%100), __func__ , ##__VA_ARGS__); \ +} while (0) + +#define __TLS_DBGPRT_WARNING(fmt, ...) \ +do { \ + u32 time = tls_os_get_time(); \ + printf("[WM_W] <%d.%02d> %s : "fmt, (time/100), (time%100), __func__ , ##__VA_ARGS__); \ +} while (0) + +#define __TLS_DBGPRT_ERR(fmt, ...) \ +do { \ + u32 time = tls_os_get_time(); \ + printf("[WM_E] <%d.%02d> %s : "fmt, (time/100), (time%100), __func__ , ##__VA_ARGS__); \ +} while (0) + + +/** + * @defgroup System_APIs System APIs + * @brief System APIs + */ + +/** + * @addtogroup System_APIs + * @{ + */ + +/** + * @defgroup DEBUG_APIs DEBUG APIs + * @brief DEBUG APIs + */ + +/** + * @addtogroup DEBUG_APIs + * @{ + */ + +#if (TLS_GENERAL_DBG && TLS_DBG_LEVEL_INFO) +/** Print information of the info level */ +#define TLS_DBGPRT_INFO(f, a...) __TLS_DBGPRT_INFO(f, ##a) +#else +/** Print information of the info level */ +#define TLS_DBGPRT_INFO(f, a...) +#endif + +#if (TLS_GENERAL_DBG && TLS_DBG_LEVEL_WARNING) +/** Print information of the warning level */ +#define TLS_DBGPRT_WARNING(f, a...) __TLS_DBGPRT_WARNING(f, ##a) +#else +/** Print information of the warning level */ +#define TLS_DBGPRT_WARNING(f, a...) +#endif + +#if (TLS_GENERAL_DBG && TLS_DBG_LEVEL_ERR) +/** Print information of the error level */ +#define TLS_DBGPRT_ERR(f, a...) __TLS_DBGPRT_ERR(f, ##a) +#else +/** Print information of the error level */ +#define TLS_DBGPRT_ERR(f, a...) +#endif + +#if (TLS_GENERAL_DBG && TLS_DBG_LEVEL_DUMP) +/** + * @brief dump memory + * + * @param[in] *p pointer the memory + * @param[in] len length of memory + * + * @return None + * + * @note None + */ +void TLS_DBGPRT_DUMP(char *p, u32 len); +#else +/** Print information of the dump level */ +#define TLS_DBGPRT_DUMP(p, len) +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif /* end of WM_DEBUG_H */ + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/wm_include.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/wm_include.h new file mode 100644 index 00000000..99fd8b26 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/wm_include.h @@ -0,0 +1,75 @@ +/** + * @file wm_include.h + * + * @brief the configuration file of sdk + * + * @author winnermicro + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#ifndef __WM_INCLUDE_H__ +#define __WM_INCLUDE_H__ + +/** + * @mainpage WinnerMicro SDK + * + * Quick Start of WinnerMicro SDK. + * + * + * HOW TO CODE ? + * + * Function UserMain(void) is the entrance function of the application: + * @code + * void UserMain(void) + * { + * printf("\n user task\n"); + * + * #if DEMO_CONSOLE + * CreateDemoTask(); + * #endif + * + * //user's task + * } + * @endcode + * + * + * \n + * HOW TO COMPILE ? + * + * To build with the SDK you can use the keil tools. + * Opening "Tools\Keil\Project\WM_SDK.uvproj" to compile. + * + * + * \n + * HOW TO DOWNLOAD THE FIRMWARE ? + * + * Download the "WM_W600.FLS" image + * + * This will download image which includes secboot & sdk into flash by ROM using xModem-protocol. + * @code + * Pulling down the bootmode pin and reset the device. Then UART0 will output: + * CCC... + * For details,please refer to the sdk manual. + * @endcode + * + * Download the "WM_W600_SEC.IMG" image + * + * This will download image which includes sdk by secboot using xmodem-protocol. + * @code + * Press "ESC" and then reset the device. Then UART0 will output: + * secboot running... + * CCC... + * For details,please refer to the sdk manual. + * @endcode + * + * \n + */ + +#include +#include +#include "wm_type_def.h" +#include "wm_gpio.h" +//#include "wm_flash.h" +#include "wm_regs.h" + +#endif diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/wm_ram_config.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/wm_ram_config.h new file mode 100644 index 00000000..6276e1c3 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/wm_ram_config.h @@ -0,0 +1,29 @@ +/** + * @file wm_ram_config.h + * + * @brief WM ram model configure + * + * @author winnermicro + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ +#ifndef __WM_RAM_CONFIG_H__ +#define __WM_RAM_CONFIG_H__ + +/*OS Task Stack's lower & upper range*/ +#define TASK_STACK_USING_MEM_LOWER_RANGE (0x20000000UL) +#define TASK_STACK_USING_MEM_UPPER_RANGE (0x20028000UL) + +/*0x20000000~MASTER_SPI_DMA_ADDR for stack,heap & data*/ + +/*Master SPI use buffer when spi use dma transfer mode*/ +#define MASTER_SPI_DMA_ADDR 0x20038000UL + +/*High speed SPI or SDIO buffer to exchange data*/ +#define SLAVE_HSPI_SDIO_ADDR 0x2003A000UL + +/*Wi-Fi use buffer to exchange data*/ +#define WIFI_MEM_START_ADDR 0x2003C000UL + +#endif /*__WM_RAM_CONFIG_H__*/ + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/wm_regs.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/wm_regs.h new file mode 100644 index 00000000..1ec325da --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/wm_regs.h @@ -0,0 +1,918 @@ +/** + * @file wm_regs.h + * + * @brief register & operation file + * + * @author winnermicro + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ +#ifndef WM_REGS_H +#define WM_REGS_H + +#define __MPU_PRESENT 1 + +#define __CM3_REV 0x0201 /*!< Core Revision r2p1 */ +#define __NVIC_PRIO_BITS 4 /*!< W600 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** Venus specific Interrupt Numbers *********************************************************/ + SDIO_RX_IRQn = 0, /*!< SDIO Receiver Interrupt */ + SDIO_TX_IRQn = 1, /*!< SDIO Transmit Interrupt */ + SDIO_RX_CMD_IRQn = 2, /*!< SDIO Command Receiver Interrupt */ + SDIO_TX_CMD_IRQn = 3, /*!< SDIO Command Transmit Interrupt */ + MAC_IRQn = 4, /*!< MAC Interrupt */ + + SEC_RX_IRQn = 6, /*!< EXTI Line0 Interrupt */ + SEC_TX_MNGT_IRQn = 7, /*!< EXTI Line1 Interrupt */ + SEC_TX_DAT_IRQn = 8, /*!< EXTI Line2 Interrupt */ + PMU_RTC_IRQn = 9, /*!< PMU RTC Interrupt */ + PMU_SLP_INTVL_IRQn = 10, /*!< PMU Sleep Interval Interrupt */ + PMU_GPIO_WAKE_IRQn = 11, /*!< PMU GPIO Wake Interrupt */ + PMU_SDIO_WAKE_IRQn = 12, /*!< PMU SDIO Wake Interrupt */ + DMA_Channel0_IRQn = 13, /*!< DMA Channel 0 global Interrupt */ + DMA_Channel1_IRQn = 14, /*!< DMA Channel 1 global Interrupt */ + DMA_Channel2_IRQn = 15, /*!< DMA Channel 2 global Interrupt */ + DMA_Channel3_IRQn = 16, /*!< DMA Channel 3 global Interrupt */ + DMA_Channel4_7_IRQn = 17, /*!< DMA Channel 4~7 global Interrupt */ + DMA_BRUST_IRQn = 18, /*!< DMA Burst global Interrupt */ + I2C_IRQn = 19, /*!< I2C Interrupts */ + ADC_IRQn = 20, /*!< ADC Convert Interrupts */ + SPI_LS_IRQn = 21, /*!< Low Speed SPI Interrupt */ + SPI_HS_IRQn = 22, /*!< High Speed SPI Interrupt */ + UART0_IRQn = 23, /*!< UART0 Interrupts */ + UART1_IRQn = 24, /*!< UART1 Interrupt */ + GPIO_IRQn = 25, /*!< GPIO Interrupt */ + TIM1_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM2_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM3_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM4_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM5_IRQn = 31, /*!< I2C1 Event Interrupt */ + WDG_IRQn = 32, /*!< Watch Dog Interrupt */ + PMU_IRQn = 33, /*!< PMU Interrupt */ + FLASH_IRQn = 34, /*!< Flash Interrupt */ + PWM_IRQn = 35, /*!< PWM Interrupt */ + I2S_IRQn = 36, /*!< I2S Interrupts */ + RSA_IRQn = 38, + CRYPTION_IRQn = 39, + GPIOB_IRQn = 40, + UART2_IRQn = 41, + +} IRQn_Type; + +#include "core_cm3.h" + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +typedef volatile unsigned int TLS_REG; /* Hardware register definition */ + +#define APB_CLK (40000000) /* 40MHz */ + +#define DEVICE_BASE_ADDR 0x40000000 + + +/*************************************************************** + * SDIO妯″潡瀵勫瓨鍣ㄥ畾涔 + ***************************************************************/ +#define HR_SDIO_BASE_ADDR DEVICE_BASE_ADDR +#define HR_SDIO_CIS0 (HR_SDIO_BASE_ADDR + 0x008) +#define HR_SDIO_CIS1 (HR_SDIO_BASE_ADDR + 0x00C) +#define HR_SDIO_CSA (HR_SDIO_BASE_ADDR + 0x010) +#define HR_SDIO_READ (HR_SDIO_BASE_ADDR + 0x014) +#define HR_SDIO_WRITE (HR_SDIO_BASE_ADDR + 0x018) +#define HR_SDIO_INTEN (HR_SDIO_BASE_ADDR + 0x030) +#define HR_SDIO_OCR (HR_SDIO_BASE_ADDR + 0x034) +#define HR_SDIO_CIA (HR_SDIO_BASE_ADDR + 0x024) +#define HR_SDIO_PROG (HR_SDIO_BASE_ADDR + 0x028) + +/*************************************************************** + * SPI妯″潡瀵勫瓨鍣ㄥ畾涔 + ***************************************************************/ +#define HR_HSPI_BASE_ADDR (DEVICE_BASE_ADDR + 0x200) +#define HR_HSPI_CLEAR_FIFO (HR_HSPI_BASE_ADDR) +#define HR_HSPI_SPI_CFG (HR_HSPI_BASE_ADDR + 0x04) +#define HR_HSPI_MODE_CFG (HR_HSPI_BASE_ADDR + 0x08) +#define HR_HSPI_INT_MASK (HR_HSPI_BASE_ADDR + 0x0C) +#define HR_HSPI_INT_STTS (HR_HSPI_BASE_ADDR + 0x10) +#define HR_HSPI_RXDAT_LEN (HR_HSPI_BASE_ADDR + 0x18) + +/*************************************************************** + * SDIO WRAPPER瀵勫瓨鍣ㄥ畾涔 + ***************************************************************/ +#define HR_SDIO_WRAPPER_BASE_ADDR (DEVICE_BASE_ADDR + 0x300) +#define HR_SDIO_INT_SRC (HR_SDIO_WRAPPER_BASE_ADDR + 0x000) +#define HR_SDIO_INT_MASK (HR_SDIO_WRAPPER_BASE_ADDR + 0x004) +#define HR_SDIO_UPCMDVALID (HR_SDIO_WRAPPER_BASE_ADDR + 0x008) +#define HR_SDIO_DOWNCMDVALID (HR_SDIO_WRAPPER_BASE_ADDR + 0x00C) +#define HR_SDIO_TXBD_LINKEN (HR_SDIO_WRAPPER_BASE_ADDR + 0x010) +#define HR_SDIO_TXBD_ADDR (HR_SDIO_WRAPPER_BASE_ADDR + 0x014) +#define HR_SDIO_TXEN (HR_SDIO_WRAPPER_BASE_ADDR + 0x018) +#define HR_SDIO_TX_STTS (HR_SDIO_WRAPPER_BASE_ADDR + 0x01C) +#define HR_SDIO_RXBD_LINKEN (HR_SDIO_WRAPPER_BASE_ADDR + 0x020) +#define HR_SDIO_RXBD_ADDR (HR_SDIO_WRAPPER_BASE_ADDR + 0x024) +#define HR_SDIO_RXEN (HR_SDIO_WRAPPER_BASE_ADDR + 0x028) +#define HR_SDIO_RX_STTS (HR_SDIO_WRAPPER_BASE_ADDR + 0x02C) +#define HR_SDIO_CMD_ADDR (HR_SDIO_WRAPPER_BASE_ADDR + 0x030) +#define HR_SDIO_CMD_SIZE (HR_SDIO_WRAPPER_BASE_ADDR + 0x034) + +/* SDIO interrupt bit definition */ +#define SDIO_WP_INT_SRC_CMD_DOWN (1UL<<3) +#define SDIO_WP_INT_SRC_CMD_UP (1UL<<2) +#define SDIO_WP_INT_SRC_DATA_DOWN (1UL<<1) +#define SDIO_WP_INT_SRC_DATA_UP (1UL<<0) + + +/*************************************************************** + * DMA妯″潡瀵勫瓨鍣ㄥ畾涔 + ***************************************************************/ +#define HR_DMA_BASE_ADDR (DEVICE_BASE_ADDR + 0x400) +#define HR_DMA_INT_MASK (HR_DMA_BASE_ADDR + 0x0) +#define HR_DMA_INT_SRC (HR_DMA_BASE_ADDR + 0x4) +#define HR_DMA_CHNL_SEL (HR_DMA_BASE_ADDR + 0x08) +#define HR_DMA_CHNL0_SRC_ADDR (HR_DMA_BASE_ADDR + 0x10) +#define HR_DMA_CHNL0_DEST_ADDR (HR_DMA_BASE_ADDR + 0x14) +#define HR_DMA_CHNL0_SRC_WRAP_ADDR (HR_DMA_BASE_ADDR + 0x18) +#define HR_DMA_CHNL0_DEST_WRAP_ADDR (HR_DMA_BASE_ADDR + 0x1C) +#define HR_DMA_CHNL0_WRAP_SIZE (HR_DMA_BASE_ADDR + 0x20) +#define HR_DMA_CHNL0_CHNL_CTRL (HR_DMA_BASE_ADDR + 0x24) +#define HR_DMA_CHNL0_DMA_MODE (HR_DMA_BASE_ADDR + 0x28) +#define HR_DMA_CHNL0_DMA_CTRL (HR_DMA_BASE_ADDR + 0x2C) +#define HR_DMA_CHNL0_DMA_STATUS (HR_DMA_BASE_ADDR + 0x30) +#define HR_DMA_CHNL0_LINK_DEST_ADDR (HR_DMA_BASE_ADDR + 0x34) +#define HR_DMA_CHNL0_CURRENT_DEST_ADDR (HR_DMA_BASE_ADDR + 0x38) + +#define DMA_STARTADDRESS (0x40000400) +#define DMA_INTMASK_REG (*(volatile unsigned int*)(DMA_STARTADDRESS+0x000)) +#define DMA_INTSRC_REG (*(volatile unsigned int*)(DMA_STARTADDRESS+0x004)) +#define DMA_CHNL_REG_BASE (DMA_STARTADDRESS+0x010) +#define DMA_SRCADDR_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /*- 1*/) +0x00)) +#define DMA_DESTADDR_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /*- 1*/) +0x04)) +#define DMA_SRCWRAPADDR_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /*- 1*/) +0x08)) +#define DMA_DESTWRAPADDR_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /*- 1*/) +0x0C)) +#define DMA_WRAPSIZE_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /*- 1*/) +0x10)) +#define DMA_CHNLCTRL_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /*- 1*/) +0x14)) +#define DMA_MODE_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /*- 1*/) +0x18)) +#define DMA_CTRL_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /*- 1*/) +0x1C)) +#define DMA_STATUS_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /*- 1*/) +0x20)) +#define DMA_CURRSRCADDR_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /*- 1*/) +0x24)) +#define DMA_CURRDESTADDR_REG(ch) (*(volatile unsigned int*)(DMA_CHNL_REG_BASE + 0x30 * (ch /*- 1*/) +0x28)) + +#define DMA_CHNL_CTRL_CHNL_ON (1<<0) +#define DMA_CHNL_CTRL_CHNL_OFF (1<<1) + +#define DMA_MODE_HARD_MODE (1<<0) +#define DMA_MODE_CHAIN_MODE (1<<1) + +/*************************************************************** + * 鑺傝兘妯″潡瀵勫瓨鍣ㄥ畾涔 + ***************************************************************/ +#define HR_PMU_BASE_ADDR (DEVICE_BASE_ADDR + 0x600) +#define HR_PMU_PS_CR (HR_PMU_BASE_ADDR + 0x00) +#define HR_PMU_TIMER0 (HR_PMU_BASE_ADDR + 0x04) +#define HR_PMU_TIMER1 (HR_PMU_BASE_ADDR + 0x08) +#define HR_PMU_RTC_CTRL1 (HR_PMU_BASE_ADDR + 0x0C) +#define HR_PMU_RTC_CTRL2 (HR_PMU_BASE_ADDR + 0x10) +#define HR_PMU_INTERRUPT_SRC (HR_PMU_BASE_ADDR + 0x14) +#define HR_PMU_INTERRUPT_MASK (HR_PMU_BASE_ADDR + 0x18) +#define HR_PMU_WLAN_STTS (HR_PMU_BASE_ADDR + 0x1C) + +/* 鑺傝兘瀵勫瓨鍣ㄤ綅瀹氫箟 */ +#define PMU_WLAN_SLEEP_EN_BIT (1UL << 0) + +#define PMU_PRETBTT_PERIOD_RSV (0xE0000000) +#define PMU_TBTT_TIMER_MASK (0x3FFFF) +#define PMU_TBTT_TIMER_SHIFT (11) +#define PMU_SLEEP_INTERVAL_MASK (0x7FF) +#define PMU_SLEEP_INTERVAL_SHIFT (0) + +#define PMU_TBTT_OFFSET_MASK (0x7FFF) +#define PMU_TBTT_OFFSET_SHIFT (17) +#define PMU_PRETBTT_TIMER_MASK (0x1FFFF) +#define PMU_PRETBTT_TIMER_SHIFT (0) +#define PMU_PRETBTT_OFFSET_DEFAULT (((30UL) << 17) | (300UL)) + +#define PMU_TIMER0_WAKEUP_EN (1UL << 3) +#define PMU_TIMER1_WAKEUP_EN (1UL << 2) +#define PMU_GPIO_WAKEUP_EN (1UL << 1) +#define PMU_SDIO_WAKEUP_EN (1UL << 0) + +#define PMU_TIMER0_NTERRUPT_SRC (1UL << 0) +#define PMU_TIMER1_NTERRUPT_SRC (1UL << 1) +#define PMU_GPIO_NTERRUPT_SRC (1UL << 2) +#define PMU_SDIO_NTERRUPT_SRC (1UL << 3) + +#define PMU_TIMER0_NTERRUPT_MASK (1UL << 0) +#define PMU_TIMER1_NTERRUPT_MASK (1UL << 1) +#define PMU_GPIO_NTERRUPT_MASK (1UL << 2) +#define PMU_SDIO_NTERRUPT_MASK (1UL << 3) + +#define PMU_WLAN_RX_IDLE_BIT (1UL << 1) +#define PMU_WLAN_TX_IDLE_BIT (1UL << 0) + +#define PMU_LDO_DAC28_BYPASS (1UL<<0) +#define PMU_LDO_SW_BYPASS (1UL<<1) +#define PMU_DLDO_BYPASS (1UL<<2) +#define PMU_LDO_PRE_BYPASS (1UL<<3) +#define PMU_LDO_ADDA_D_BYPASS (1UL<<4) +#define PMU_LDO_ADDA_A_BYPASS (1UL<<5) +#define PMU_LDO_UM_PA_BYPASS (1UL<<6) +#define PMU_LDO_CHP_BYPASS (1UL<<7) +#define PMU_LDO_DM_IF_BYPASS (1UL<<8) +#define PMU_LDO_LNA_BYPASS (1UL<<9) +#define PMU_LDO_VCO_BYPASS (1UL<<10) +#define PMU_LDO_LO_BYPASS (1UL<<11) +#define PMU_LDO_PLL_BYPASS (1UL<<15) +#define PMU_LDO_WLAN_BYPASS (1UL<<19) +#define PMU_LDO_BGR_BYPASS (1UL<<20) +#define PMU_LDO_BB_BYPASS (1UL<<21) + +/*************************************************************** + * system clock 鍜宐us clock瀵勫瓨鍣ㄥ畾涔 + ***************************************************************/ +#define HR_CLK_BASE_ADDR (DEVICE_BASE_ADDR + 0x700) +#define HR_CLK_SOFT_CLK_MASK (HR_CLK_BASE_ADDR + 0x04) +#define HR_CLK_BBP_CLT_CTRL (HR_CLK_BASE_ADDR + 0x08) +#define HR_CLK_RST_CTL (HR_CLK_BASE_ADDR + 0x0c) +#define HR_CLK_DIV_CTL (HR_CLK_BASE_ADDR + 0x10) + +#define HR_CLK_I2S_CTL (HR_CLK_BASE_ADDR + 0x18) + +#define I2S_CLK_CTL_EXT_Pos (0) +#define I2S_CLK_CTL_MCLK_Pos (1) +#define I2S_CLK_CTL_MCLKDIV_Pos (2) +#define I2S_CLK_CTL_BCLKDIV_Pos (8) + +/*************************************************************** + * 鍐呭瓨妯″潡瀵勫瓨鍣ㄥ畾涔 + ***************************************************************/ +#define HR_MEM_BASE_ADDR (DEVICE_BASE_ADDR + 0x800) +#define HR_MEM_TXBUF_BASE_ADDR (HR_MEM_BASE_ADDR + 0x00) +#define HR_MEM_RXBUF_BASE_ADDR (HR_MEM_BASE_ADDR + 0x04) +#define HR_MEM_BUF_NUM_CFG (HR_MEM_BASE_ADDR + 0x08) +#define HR_MEM_BUF_SIZE_CFG (HR_MEM_BASE_ADDR + 0x0C) +#define HR_MEM_AGGR_CFG (HR_MEM_BASE_ADDR + 0x10) +#define HR_MEM_BUF_EN (HR_MEM_BASE_ADDR + 0x14) + + +/*************************************************************** + * 涓柇妯″潡瀵勫瓨鍣ㄥ畾涔 + ***************************************************************/ +#define HR_VIC_BASE_ADDR 0xFFFFF000 +#define HR_VIC_IRQ_STATUS (HR_VIC_BASE_ADDR + 0x0) +#define HR_VIC_FIQ_STATUS (HR_VIC_BASE_ADDR + 0x4) +#define HR_VIC_RAW_INTR (HR_VIC_BASE_ADDR + 0x8) +#define HR_VIC_INT_SELECT (HR_VIC_BASE_ADDR + 0xc) +#define HR_VIC_INT_ENABLE (HR_VIC_BASE_ADDR + 0x10) +#define HR_VIC_INT_EN_CLR (HR_VIC_BASE_ADDR + 0x14) +#define HR_VIC_SOFT_INT (HR_VIC_BASE_ADDR + 0x18) +#define HR_VIC_SOFT_INT_CLR (HR_VIC_BASE_ADDR + 0x1c) +#define HR_VIC_PROTECT (HR_VIC_BASE_ADDR + 0x20) +#define HR_VIC_VECT_ADDR (HR_VIC_BASE_ADDR + 0x30) +#define HR_VIC_DEF_VECT_ADDR (HR_VIC_BASE_ADDR + 0x34) +#define HR_VIC_VECT_ENABLE (HR_VIC_BASE_ADDR + 0x100) +#define HR_VIC_VECT_BASE_ADDR (HR_VIC_BASE_ADDR + 0x104) +#define HR_VIC_INT_NUM (HR_VIC_BASE_ADDR + 0x108) +#define HR_VIC_INT_PRIO0 (HR_VIC_BASE_ADDR + 0x10C) +#define HR_VIC_INT_PRIO1 (HR_VIC_BASE_ADDR + 0x110) +#define HR_VIC_INT_PRIO2 (HR_VIC_BASE_ADDR + 0x114) +#define HR_VIC_INT_PRIO3 (HR_VIC_BASE_ADDR + 0x118) + + +/* APB鍩哄湴鍧*/ +#define HR_APB_BASE_ADDR 0x40010000 + +/*************************************************************** + * I2C妯″潡瀵勫瓨鍣ㄥ畾涔 + ***************************************************************/ +#define HR_I2C_BASE_ADDR (HR_APB_BASE_ADDR) +#define HR_I2C_PRER_LO (HR_I2C_BASE_ADDR + 0x0) +#define HR_I2C_PRER_HI (HR_I2C_BASE_ADDR + 0x04) +#define HR_I2C_CTRL (HR_I2C_BASE_ADDR + 0x08) +#define HR_I2C_TX_RX (HR_I2C_BASE_ADDR + 0x0C) +#define HR_I2C_CR_SR (HR_I2C_BASE_ADDR + 0x10) +#define HR_I2C_TXR (HR_I2C_BASE_ADDR + 0x14) +#define HR_I2C_CR (HR_I2C_BASE_ADDR + 0x18) + + +#define I2C_CTRL_INT_DISABLE (0x1UL<<6) +#define I2C_CTRL_ENABLE (0x1UL<<7) + +#define I2C_CR_STA (0x1UL<<7) +#define I2C_CR_STO (0x1UL<<6) +#define I2C_CR_RD (0x1UL<<5) +#define I2C_CR_WR (0x1UL<<4) +#define I2C_CR_NAK (0x1UL<<3) +#define I2C_CR_IACK (0x1UL) + +#define I2C_SR_NAK (0x1UL<<7) +#define I2C_SR_BUSY (0x1UL<<6) +#define I2C_SR_TIP (0x1UL<<1) +#define I2C_SR_IF (0x1UL) + + +/*************************************************************** + * SD ADC妯″潡瀵勫瓨鍣ㄥ畾涔 + ***************************************************************/ +#define HR_SD_ADC_BASE_ADDR (HR_APB_BASE_ADDR + 0x200) +#define HR_SD_ADC_RESULT_REG ((HR_SD_ADC_BASE_ADDR+0x000)) +#define HR_SD_ADC_CONFIG_REG ((HR_SD_ADC_BASE_ADDR+0x004)) +#define HR_SD_ADC_CTRL_REG ((HR_SD_ADC_BASE_ADDR+0x008)) +#define HR_SD_ADC_INT_MASK_REG ((HR_SD_ADC_BASE_ADDR+0x00C)) +#define HR_SD_ADC_INT_SOURCE_REG ((HR_SD_ADC_BASE_ADDR+0x010)) + + +/*************************************************************** + * SPI妯″潡瀵勫瓨鍣ㄥ畾涔 + ***************************************************************/ +#define HR_SPI_BASE_ADDR (HR_APB_BASE_ADDR + 0x400) +#define HR_SPI_CHCFG_REG (HR_SPI_BASE_ADDR + 0x000) +#define HR_SPI_SPICFG_REG (HR_SPI_BASE_ADDR + 0x004) +#define HR_SPI_CLKCFG_REG (HR_SPI_BASE_ADDR + 0x008) +#define HR_SPI_MODECFG_REG (HR_SPI_BASE_ADDR + 0x00C) +#define HR_SPI_INT_MASK_REG (HR_SPI_BASE_ADDR + 0x010) +#define HR_SPI_INT_STATUS_REG (HR_SPI_BASE_ADDR + 0x014) +#define HR_SPI_STATUS_REG (HR_SPI_BASE_ADDR + 0x018) +#define HR_SPI_TIMEOUT_REG (HR_SPI_BASE_ADDR + 0x01C) +#define HR_SPI_TXDATA_REG (HR_SPI_BASE_ADDR + 0x020) +#define HR_SPI_TRANSLEN_REG (HR_SPI_BASE_ADDR + 0x024) +#define HR_SPI_SLV_XMIT_LEN_REG (HR_SPI_BASE_ADDR + 0x028) +#define HR_SPI_RXDATA_REG (HR_SPI_BASE_ADDR + 0x030) + + +#define SPIM_STARTADDRESS (HR_APB_BASE_ADDR + 0x400) +#define SPIM_CHCFG_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x000)) +#define SPIM_SPICFG_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x004)) +#define SPIM_CLKCFG_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x008)) +#define SPIM_MODECFG_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x00C)) +#define SPIM_INTEN_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x010)) +#define SPIM_INTSRC_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x014)) +#define SPIM_SPISTATUS_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x018)) +#define SPIM_SPITIMEOUT_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x01C)) +#define SPIM_TXDATA_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x020)) +#define SPIM_TRANSLEN_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x024)) +#define SPIM_RXDATA_REG (*(volatile unsigned int*)(SPIM_STARTADDRESS+0x030)) + + +/*RSA瀵勫瓨鍣*/ +#define RSA_BASE_ADDRESS 0x40002200 +#define RSAXBUF (*((volatile unsigned long *) (RSA_BASE_ADDRESS + 0x0 ))) +#define RSAYBUF (*((volatile unsigned long *) (RSA_BASE_ADDRESS + 0x100 ))) +#define RSAMBUF (*((volatile unsigned long *) (RSA_BASE_ADDRESS + 0x200 ))) +#define RSADBUF (*((volatile unsigned long *) (RSA_BASE_ADDRESS + 0x300 ))) +#define RSACON (*((volatile unsigned long *) (RSA_BASE_ADDRESS + 0x400 ))) +#define RSAMC (*((volatile unsigned long *) (RSA_BASE_ADDRESS + 0x404 ))) +#define RSAN (*((volatile unsigned long *) (RSA_BASE_ADDRESS + 0x408 ))) + + + +/* Bits Definitions of "CH_CFG" */ +#define SPI_RX_INVALID_BITS(n) ((n) << 23) +#define SPI_CLEAR_FIFOS (1U << 22) +#define SPI_CONTINUE_MODE (1U << 21) +#define SPI_RX_CHANNEL_ON (1U << 20) +#define SPI_RX_CHANNEL_OFF (0U << 20) +#define SPI_TX_CHANNEL_ON (1U << 19) +#define SPI_TX_CHANNEL_OFF (0U << 19) +#define SPI_VALID_CLKS_NUM(n) ((n) << 3) +#define SPI_CS_LOW (0U << 2) +#define SPI_CS_HIGH (1U << 2) +#define SPI_FORCE_SPI_CS_OUT (1U << 1) +#define SPI_START (1U << 0) + +/* Bits Definitions of "SPI_CFG" */ +#define SPI_FRAME_FORMAT_MOTO (0U << 17) +#define SPI_FRAME_FORMAT_TI (1U << 17) +#define SPI_FRAME_FORMAT_MICROWAIRE (2U << 17) +#define SPI_TX_PIN_ALWS_DRIVER (1U << 16) +#define SPI_CS_HOLD(n) ((n) << 12) +#define CS_HOLD_1_CLKS 0 +#define CS_HOLD_2_CLKS 1 +#define CS_HOLD_4_CLKS 2 +#define CS_HOLD_8_CLKS 3 +#define CS_HOLD_16_CLKS 4 +#define CS_HOLD_32_CLKS 5 +#define CS_HOLD_64_CLKS 6 +#define CS_HOLD_127_CLKS 7 +#define SPI_CS_SETUP(n) ((n) << 9) +#define CS_SETUP_1_CLKS 0 +#define CS_SETUP_2_CLKS 1 +#define CS_SETUP_4_CLKS 2 +#define CS_SETUP_8_CLKS 3 +#define CS_SETUP_16_CLKS 4 +#define CS_SETUP_32_CLKS 5 +#define CS_SETUP_64_CLKS 6 +#define CS_SETUP_127_CLKS 7 +#define SPI_DATA_OUT_DELAY(n) ((n) << 7) +#define DATA_OUT_DELAY_1_CLKS 0 +#define DATA_OUT_DELAY_2_CLKS 1 +#define DATA_OUT_DELAY_3_CLKS 2 +#define DATA_OUT_DELAY_0_CLKS 3 +#define SPI_FRAME_DELAY(n) ((n) << 4) +#define FRAME_DELAY_1_CLKS 0 +#define FRAME_DELAY_2_CLKS 1 +#define FRAME_DELAY_4_CLKS 2 +#define FRAME_DELAY_8_CLKS 3 +#define FRAME_DELAY_16_CLKS 4 +#define FRAME_DELAY_32_CLKS 5 +#define FRAME_DELAY_64_CLKS 6 +#define FRAME_DELAY_127_CLKS 7 +#define SPI_LITTLE_ENDIAN (0 << 3) +#define SPI_BIG_ENDIAN (1 << 3) +#define SPI_SET_MASTER_SLAVE(mode) ((mode) << 2) +#define SPI_MASTER 1 +#define SPI_SLAVE 0 +#define SPI_SET_CPHA(n) ((n) << 1) +#define SPI_SET_CPOL(n) ((n) << 0) + +/* Bits Definitions of "CLK_CFG" */ +#define SPI_GET_SCLK_DIVIDER(clk) ((APB_CLK)/((clk) * 2) - 1)/*In HZ*/ +#define SPI_SCLK_DIVIDER(n) ((n) << 0) + +/* Bits Definitions of "MODE_CFG" */ +#define SPI_RX_TRIGGER_LEVEL(n) ((n) << 6) +#define SPI_TX_TRIGGER_LEVEL(n) ((n) << 2) +#define SPI_RX_DMA_ON (1 << 1) +#define SPI_RX_DMA_OFF (0 << 1) +#define SPI_TX_DMA_ON (1 << 0) +#define SPI_TX_DMA_OFF (0 << 0) + +/* Bits Definitions of SPI interrupt register(SPI_INT_MASK and SPI_INT_SOURCE) */ +#define SPI_INT_MASK_ALL 0xffU +#define SPI_INT_CLEAR_ALL 0xffU +#define SPI_INT_TIMEOUT (1U << 7) +#define SPI_INT_TRANSFER_DONE (1U << 6) +#define SPI_INT_RX_OVERRUN (1U << 5) +#define SPI_INT_RX_UNDERRUN (1U << 4) +#define SPI_INT_TX_OVERRUN (1U << 3) +#define SPI_INT_TX_UNDERRUN (1U << 2) +#define SPI_INT_RX_FIFO_RDY (1U << 1) +#define SPI_INT_TX_FIFO_RDY (1U << 0) + +/* Bits Definitions of "SPI_STATUS" */ +#define SPI_IS_BUSY(value) ((((value) & (1 << 12)) != 0) ? 1 : 0) +#define SPI_GET_RX_FIFO_CNT(value) (((value) & 0xFC0) >> 6) +#define SPI_GET_TX_FIFO_CNT(value) ((value) & 0x3F) + +/* Bits Definitions of "SPI_TIMEOUT" */ +#define SPI_TIMER_EN (1U << 31) +#define SPI_TIME_OUT(n) (((((n) * (APB_CLK)) / 1000) & ~(0x01U << 31)) << 0) + +/*************************************************************** + * UART瀵勫瓨鍣ㄥ畾涔 + ***************************************************************/ +#define HR_UART0_BASE_ADDR (HR_APB_BASE_ADDR + 0x800) +#define HR_UART1_BASE_ADDR (HR_APB_BASE_ADDR + 0xA00) +#define HR_UART2_BASE_ADDR (HR_APB_BASE_ADDR + 0x1C00) + +#define HR_UART0_LINE_CTRL (HR_UART0_BASE_ADDR + 0x0) +#define HR_UART0_FLOW_CTRL (HR_UART0_BASE_ADDR + 0x04) +#define HR_UART0_DMA_CTRL (HR_UART0_BASE_ADDR + 0x08) +#define HR_UART0_FIFO_CTRL (HR_UART0_BASE_ADDR + 0x0C) +#define HR_UART0_BAUD_RATE_CTRL (HR_UART0_BASE_ADDR + 0x10) +#define HR_UART0_INT_MASK (HR_UART0_BASE_ADDR + 0x14) +#define HR_UART0_INT_SRC (HR_UART0_BASE_ADDR + 0x18) +#define HR_UART0_FIFO_STATUS (HR_UART0_BASE_ADDR + 0x1C) +#define HR_UART0_TX_WIN (HR_UART0_BASE_ADDR + 0x20) +#define HR_UART0_RX_WIN (HR_UART0_BASE_ADDR + 0x30) + +#define HR_UART1_LINE_CTRL (HR_UART1_BASE_ADDR + 0x0) +#define HR_UART1_FLOW_CTRL (HR_UART1_BASE_ADDR + 0x04) +#define HR_UART1_DMA_CTRL (HR_UART1_BASE_ADDR + 0x08) +#define HR_UART1_FIFO_CTRL (HR_UART1_BASE_ADDR + 0x0C) +#define HR_UART1_BAUD_RATE_CTRL (HR_UART1_BASE_ADDR + 0x10) +#define HR_UART1_INT_MASK (HR_UART1_BASE_ADDR + 0x14) +#define HR_UART1_INT_SRC (HR_UART1_BASE_ADDR + 0x18) +#define HR_UART1_FIFO_STATUS (HR_UART1_BASE_ADDR + 0x1C) +#define HR_UART1_TX_WIN (HR_UART1_BASE_ADDR + 0x20) +#define HR_UART1_RX_WIN (HR_UART1_BASE_ADDR + 0x30) + +#define HR_UART2_LINE_CTRL (HR_UART2_BASE_ADDR + 0x0) +#define HR_UART2_FLOW_CTRL (HR_UART2_BASE_ADDR + 0x04) +#define HR_UART2_DMA_CTRL (HR_UART2_BASE_ADDR + 0x08) +#define HR_UART2_FIFO_CTRL (HR_UART2_BASE_ADDR + 0x0C) +#define HR_UART2_BAUD_RATE_CTRL (HR_UART2_BASE_ADDR + 0x10) +#define HR_UART2_INT_MASK (HR_UART2_BASE_ADDR + 0x14) +#define HR_UART2_INT_SRC (HR_UART2_BASE_ADDR + 0x18) +#define HR_UART2_FIFO_STATUS (HR_UART2_BASE_ADDR + 0x1C) +#define HR_UART2_TX_WIN (HR_UART2_BASE_ADDR + 0x20) +#define HR_UART2_RX_WIN (HR_UART2_BASE_ADDR + 0x30) +#define HR_UART2_GUARD_TIME (HR_UART2_BASE_ADDR + 0x40) +#define HR_UART2_WAIT_TIME (HR_UART2_BASE_ADDR + 0x44) +/* + * Line Control Register bits definition + * ULCON0 ULCON1 Register + */ +/* bit 0-1 : Word length */ +#define ULCON_WL5 0x00 +#define ULCON_WL6 0x01 +#define ULCON_WL7 0x02 +#define ULCON_WL8 0x03 +#define ULCON_WL_MASK 0x03 +/* bit 2 : Number of stop bits */ +#define ULCON_STOP_2 0x04 /* 2 stop bit */ +/* bit 3-4 : Parity mode */ +#define ULCON_PMD_MASK 0x18 +#define ULCON_PMD_EN 0x08 /* no parity */ +#define ULCON_PMD_ODD 0x18 /* odd parity */ +#define ULCON_PMD_EVEN 0x08 /* even parity */ +/* bit 6 uart tx enable */ +#define ULCON_TX_EN 0x40 +#define ULCON_RX_EN 0x80 +/* bit 6 : Infra-red mode */ +#define ULCON_INFRA_RED 0x80 + +/* + * auto flow control register bits definition + */ +#define UFC_ENABLE 0x01 +#define UFC_SW_RTS_SET 0x02 +#define UFC_RTS_TRIGGER_LVL_4_BYTE (0<<2) +#define UFC_RTS_TRIGGER_LVL_8_BYTE (1<<2) +#define UFC_RTS_TRIGGER_LVL_12_BYTE (2<<2) +#define UFC_RTS_TRIGGER_LVL_16_BYTE (3<<2) +#define UFC_RTS_TRIGGER_LVL_20_BYTE (4<<2) +#define UFC_RTS_TRIGGER_LVL_24_BYTE (5<<2) +#define UFC_RTS_TRIGGER_LVL_28_BYTE (6<<2) +#define UFC_RTS_TRIGGER_LVL_31_BYTE (7<<2) + +#define UFC_TX_FIFO_RESET 0x01 +#define UFC_RX_FIFO_RESET 0x02 +#define UFC_TX_FIFO_LVL_ZERO (0<<2) +#define UFC_TX_FIFO_LVL_4_BYTE (1<<2) +#define UFC_TX_FIFO_LVL_8_BYTE (2<<2) +#define UFC_TX_FIFO_LVL_16_BYTE (3<<2) +#define UFC_RX_FIFO_LVL_ZERO (0<<4) +#define UFC_RX_FIFO_LVL_4_BYTE (1<<4) +#define UFC_RX_FIFO_LVL_8_BYTE (2<<4) +#define UFC_RX_FIFO_LVL_16_BYTE (3<<4) + +/* dma control */ +#define UDMA_RX_FIFO_TIMEOUT (1<<2) +#define UDMA_RX_FIFO_TIMEOUT_SHIFT (3) + +/* + * uart interrupt source register bits definition + */ +#define UIS_TX_FIFO_EMPTY (1UL<<0) +#define UIS_TX_FIFO (1UL<<1) +#define UIS_RX_FIFO (1UL<<2) +#define UIS_RX_FIFO_TIMEOUT (1UL<<3) +#define UIS_CTS_CHNG (1UL<<4) +#define UIS_BREAK (1UL<<5) +#define UIS_FRM_ERR (1UL<<6) +#define UIS_PARITY_ERR (1UL<<7) +#define UIS_OVERRUN (1UL<<8) + +/* + * fifo status register bits definition + */ +/* bit 0-5 : tx fifo count */ +#define UFS_TX_FIFO_CNT_MASK 0x3F +/* bit 6-11 : rx fifo count */ +#define UFS_RX_FIFO_CNT_MASK 0x3C0 +#define UFS_CST_STS (1UL<<12) + +/*************************************************************** + * GPIO瀵勫瓨鍣ㄥ畾涔 + ***************************************************************/ +#define HR_GPIO_BASE_ADDR (HR_APB_BASE_ADDR + 0x0C00) +#define HR_GPIO_DATA (HR_GPIO_BASE_ADDR + 0x0) +#define HR_GPIO_DATA_EN (HR_GPIO_BASE_ADDR + 0x04) +#define HR_GPIO_DIR (HR_GPIO_BASE_ADDR + 0x08) +#define HR_GPIO_PULL_EN (HR_GPIO_BASE_ADDR + 0x0C) +#define HR_GPIO_AF_SEL (HR_GPIO_BASE_ADDR + 0x10) +#define HR_GPIO_AF_S1 (HR_GPIO_BASE_ADDR + 0x14) +#define HR_GPIO_AF_S0 (HR_GPIO_BASE_ADDR + 0x18) +#define HR_GPIO_IS (HR_GPIO_BASE_ADDR + 0x20) +#define HR_GPIO_IBE (HR_GPIO_BASE_ADDR + 0x24) +#define HR_GPIO_IEV (HR_GPIO_BASE_ADDR + 0x28) +#define HR_GPIO_IE (HR_GPIO_BASE_ADDR + 0x2c) +#define HR_GPIO_RIS (HR_GPIO_BASE_ADDR + 0x30) +#define HR_GPIO_MIS (HR_GPIO_BASE_ADDR + 0x34) +#define HR_GPIO_IC (HR_GPIO_BASE_ADDR + 0x38) + +#define HR_GPIOA_BASE_ADDR (HR_APB_BASE_ADDR + 0x0C00) +#define HR_GPIOA_DATA (HR_GPIOA_BASE_ADDR + 0x0) +#define HR_GPIOA_DATA_EN (HR_GPIOA_BASE_ADDR + 0x04) +#define HR_GPIOA_DATA_DIR (HR_GPIOA_BASE_ADDR + 0x08) +#define HR_GPIOA_DATA_PULLEN (HR_GPIOA_BASE_ADDR + 0x0c) +#define HR_GPIOA_AFSEL (HR_GPIOA_BASE_ADDR + 0x10) +#define HR_GPIOA_AFS1 (HR_GPIOA_BASE_ADDR + 0x14) +#define HR_GPIOA_AFS0 (HR_GPIOA_BASE_ADDR + 0x18) +#define HR_GPIOA_IS (HR_GPIOA_BASE_ADDR + 0x20) +#define HR_GPIOA_IBE (HR_GPIOA_BASE_ADDR + 0x24) +#define HR_GPIOA_IEV (HR_GPIOA_BASE_ADDR + 0x28) +#define HR_GPIOA_IE (HR_GPIOA_BASE_ADDR + 0x2C) +#define HR_GPIOA_RIS (HR_GPIOA_BASE_ADDR + 0x30) +#define HR_GPIOA_MIS (HR_GPIOA_BASE_ADDR + 0x34) +#define HR_GPIOA_IC (HR_GPIOA_BASE_ADDR + 0x38) + +#define HR_GPIOB_BASE_ADDR (HR_APB_BASE_ADDR + 0x1200) +#define HR_GPIOB_DATA (HR_GPIOB_BASE_ADDR + 0x0) +#define HR_GPIOB_DATA_EN (HR_GPIOB_BASE_ADDR + 0x04) +#define HR_GPIOB_DATA_DIR (HR_GPIOB_BASE_ADDR + 0x08) +#define HR_GPIOB_DATA_PULLEN (HR_GPIOB_BASE_ADDR + 0x0c) +#define HR_GPIOB_AFSEL (HR_GPIOB_BASE_ADDR + 0x10) +#define HR_GPIOB_AFS1 (HR_GPIOB_BASE_ADDR + 0x14) +#define HR_GPIOB_AFS0 (HR_GPIOB_BASE_ADDR + 0x18) +#define HR_GPIOB_IS (HR_GPIOB_BASE_ADDR + 0x20) +#define HR_GPIOB_IBE (HR_GPIOB_BASE_ADDR + 0x24) +#define HR_GPIOB_IEV (HR_GPIOB_BASE_ADDR + 0x28) +#define HR_GPIOB_IE (HR_GPIOB_BASE_ADDR + 0x2C) +#define HR_GPIOB_RIS (HR_GPIOB_BASE_ADDR + 0x30) +#define HR_GPIOB_MIS (HR_GPIOB_BASE_ADDR + 0x34) +#define HR_GPIOB_IC (HR_GPIOB_BASE_ADDR + 0x38) + + +#define IO_PA_BASE_ADDR (HR_APB_BASE_ADDR + 0x0C00) +#define IO_PA_DATA (*(volatile unsigned int*)(IO_PA_BASE_ADDR + 0x0)) +#define IO_PA_EN (*(volatile unsigned int*)(IO_PA_BASE_ADDR + 0x4)) +#define IO_PA_DIR (*(volatile unsigned int*)(IO_PA_BASE_ADDR + 0x8)) +#define IO_PA_REN (*(volatile unsigned int*)(IO_PA_BASE_ADDR + 0xC)) +#define IO_PA_AFSEL (*(volatile unsigned int*)(IO_PA_BASE_ADDR + 0x10)) +#define IO_PA_AFS1 (*(volatile unsigned int*)(IO_PA_BASE_ADDR + 0x14)) +#define IO_PA_AFS0 (*(volatile unsigned int*)(IO_PA_BASE_ADDR + 0x18)) + +/*************************************************************** + * TIMER瀵勫瓨鍣ㄥ畾涔 + ***************************************************************/ +#define HR_TIMER_BASE_ADDR (HR_APB_BASE_ADDR + 0x0E00) +#define HR_TIMER_CFG (HR_TIMER_BASE_ADDR + 0x0) +#define HR_TIMER0_5_CSR (HR_TIMER_BASE_ADDR + 0x04) +#define HR_TIMER0_PRD (HR_TIMER_BASE_ADDR + 0x08) +#define HR_TIMER1_PRD (HR_TIMER_BASE_ADDR + 0x0C) +#define HR_TIMER2_PRD (HR_TIMER_BASE_ADDR + 0x10) +#define HR_TIMER3_PRD (HR_TIMER_BASE_ADDR + 0x14) +#define HR_TIMER4_PRD (HR_TIMER_BASE_ADDR + 0x18) +#define HR_TIMER5_PRD (HR_TIMER_BASE_ADDR + 0x1C) +/* timer csr bits defintion */ +#define TLS_TIMER_MS_UNIT(n) (1UL<<(0+5*n)) +#define TLS_TIMER_ONE_TIME(n) (1UL<<(1+5*n)) +#define TLS_TIMER_EN(n) (1UL<<(2+5*n)) +#define TLS_TIMER_INT_EN(n) (1UL<<(3+5*n)) +#define TLS_TIMER_INT_CLR(n) (1UL<<(4+5*n)) + +/*************************************************************** + * WATCH DOG瀵勫瓨鍣ㄥ畾涔 + ***************************************************************/ +#define HR_WDG_BASE_ADDR (HR_APB_BASE_ADDR + 0x1000) +#define HR_WDG_LOAD_VALUE (HR_WDG_BASE_ADDR + 0x00) +#define HR_WDG_CUR_VALUE (HR_WDG_BASE_ADDR + 0x04) +#define HR_WDG_CTRL (HR_WDG_BASE_ADDR + 0x08) +#define HR_WDG_INT_CLR (HR_WDG_BASE_ADDR + 0x0C) +#define HR_WDG_INT_SRC (HR_WDG_BASE_ADDR + 0x10) +#define HR_WDG_INT_MIS (HR_WDG_BASE_ADDR + 0x14) +#define HR_WDG_LOCK (HR_WDG_BASE_ADDR + 0x40) + +/*************************************************************** + * IOCTL瀵勫瓨鍣ㄥ畾涔 + ***************************************************************/ +#define HR_IOCTL_BASE_ADDR (HR_APB_BASE_ADDR + 0x1200) +#define HR_IOCTL_DL_MODE (HR_IOCTL_BASE_ADDR + 0x0) +#define HR_IOCTL_GP_SDIO_I2C (HR_IOCTL_BASE_ADDR + 0x04) +#define HR_IOCTL_GP_JTAG (HR_IOCTL_BASE_ADDR + 0x08) +#define HR_IOCTL_GP_SPI (HR_IOCTL_BASE_ADDR + 0x0C) +#define HR_IOCTL_PE (HR_IOCTL_BASE_ADDR + 0x10) + + +#define IOCTRL_STARTADDRESS (HR_APB_BASE_ADDR + 0x1200) +#define IOCTRL_DOWNLOAD_MODE_REG (*(volatile unsigned *)(IOCTRL_STARTADDRESS+0x000)) +#define IOCTRL_PIN_CONFIG_REG1 (*(volatile unsigned *)(IOCTRL_STARTADDRESS+0x004)) +#define IOCTRL_PIN_CONFIG_REG2 (*(volatile unsigned *)(IOCTRL_STARTADDRESS+0x008)) +#define IOCTRL_PIN_CONFIG_REG3 (*(volatile unsigned *)(IOCTRL_STARTADDRESS+0x00C)) + + +/** bit field of the lcd gate control in CLK gating register */ +#define HR_CLK_LCD_GATE_Pos (10) + +/***********************************************************//** + * LCD瀵勫瓨鍣ㄥ畾涔 + ***************************************************************/ + +#define HR_LCD_REG_BASE (HR_APB_BASE_ADDR + 0x1600) //(0x4001 1600) +#define HR_LCD_CR (HR_LCD_REG_BASE+0x000) +#define HR_LCD_FRAME_CNT (HR_LCD_REG_BASE+0x004) +#define HR_LCD_COM0_1_SEG (HR_LCD_REG_BASE+0x008) +#define HR_LCD_COM2_3_SEG (HR_LCD_REG_BASE+0x00C) +#define HR_LCD_COM4_5_SEG (HR_LCD_REG_BASE+0x010) +#define HR_LCD_COM6_7_SEG (HR_LCD_REG_BASE+0x014) +#define HR_LCD_IO_EN (HR_LCD_REG_BASE+0x018) + +#define LCD_CR_EN_Pos (8) +#define LCD_CR_PD_Pos (9) + +#define LCD_CR_MODE_Pos (11) +#define LCD_CR_MODE_MASK (1UL<<11) +#define LCD_CR_MODE_4x20 (1UL<<11) +#define LCD_CR_MODE_8X16 (0UL<<11) + +#define LCD_EN (1UL<<8) + +#define LCD_BIAS_MASK (3UL<<6) +#define LCD_BIAS_MASK_Pos (6) +#define LCD_BIAS_ONEFOURTH (0UL<<6) +#define LCD_BIAS_ONEHALF (1UL<<6) +#define LCD_BIAS_ONETHIRD (2UL<<6) +#define LCD_BIAS_STATIC (3UL<<6) + +#define LCD_VLCD_MASK (7UL<<3) +#define LCD_VLCD_MASK_Pos (3) +#define LCD_VLCD_27 (0UL<<3) +#define LCD_VLCD_29 (1UL<<3) +#define LCD_VLCD_31 (2UL<<3) +#define LCD_VLCD_33 (3UL<<3) + + +#define LCD_DUTY_MASK (7UL<<0) +#define LCD_DUTY_MASK_Pos (0) +#define LCD_DUTY_STATIC (0UL<<0) +#define LCD_DUTY_ONEHALF (1UL<<0) +#define LCD_DUTY_ONETHIRD (2UL<<0) +#define LCD_DUTY_ONEFOURTH (3UL<<0) +#define LCD_DUTY_ONEFIFTH (4UL<<0) +#define LCD_DUTY_ONESIXTH (5UL<<0) +#define LCD_DUTY_ONESEVENTH (6UL<<0) +#define LCD_DUTY_ONEEIGHTH (7UL<<0) + + +/***********************************************************//** + * I2S瀵勫瓨鍣ㄥ畾涔 + ***************************************************************/ +#define HR_CLK_I2S_GATE_Pos (10) + + +#define HR_I2S_REG_BASE (HR_APB_BASE_ADDR+0x1A00) +#define HR_I2S_CTRL (HR_I2S_REG_BASE+0x000) +#define HR_I2S_INT_MASK (HR_I2S_REG_BASE+0x004) +#define HR_I2S_INT_SRC (HR_I2S_REG_BASE+0x008) +#define HR_I2S_STATUS (HR_I2S_REG_BASE+0x00C) +#define HR_I2S_TX (HR_I2S_REG_BASE+0x010) +#define HR_I2S_RX (HR_I2S_REG_BASE+0x014) + +/******************************************************************************/ +/* */ +/* PWM */ +/* */ +/******************************************************************************/ +#define HR_PWM_REG_BASE (HR_APB_BASE_ADDR+0x1800) +#define HR_PWM_CLKDIV01 (HR_PWM_REG_BASE+0x0000) +#define HR_PWM_CLKDIV23 (HR_PWM_REG_BASE+0x0004) +#define HR_PWM_CTL (HR_PWM_REG_BASE+0x0008) +#define HR_PWM_PERIOD (HR_PWM_REG_BASE+0x000C) +#define HR_PWM_PNUM (HR_PWM_REG_BASE+0x0010) +#define HR_PWM_CMPDAT (HR_PWM_REG_BASE+0x0014) +#define HR_PWM_DTCTL (HR_PWM_REG_BASE+0x0018) +#define HR_PWM_INTEN (HR_PWM_REG_BASE+0x001C) +#define HR_PWM_INTSTS (HR_PWM_REG_BASE+0x0020) +#define HR_PWM_CAPDAT (HR_PWM_REG_BASE+0x0024) +#define HR_PWM_BRKCTL (HR_PWM_REG_BASE+0x0028) +#define HR_PWM_CH4_REG1 (HR_PWM_REG_BASE+0x002C) +#define HR_PWM_CH4_REG2 (HR_PWM_REG_BASE+0x0030) +#define HR_PWM_CAP2DAT (HR_PWM_REG_BASE+0x0034) +#define HR_PWM_CAP2CTL (HR_PWM_REG_BASE+0x0038) + +/* EFUSE Register */ +#define HR_EFUSE_REG_BASE (0x0f001600) +#define HR_EFUSE_WDATA_PORT (HR_EFUSE_REG_BASE+0x000) +#define HR_EFUSE_PGM_CMD (HR_EFUSE_REG_BASE+0x004) +#define HR_EFUSE_PGM_STTS (HR_EFUSE_REG_BASE+0x008) +#define HR_EFUSE_CLEAR (HR_EFUSE_REG_BASE+0x00C) +#define HR_EFUSE_VDDQ_SETUP (HR_EFUSE_REG_BASE+0x010) + +/* PGM_CMD define */ +#define EFUSE_PGM_START (1UL) +#define EFUSE1_SELECT (1UL << 1) +#define EFUSE2_SELECT (1UL << 2) + +/* PGM STTS define */ +#define EFUSE_PGM_DONE (1UL) +#define EFUSE_FIFO_FREE (1UL << 1) + +/* CLEAR_EFUSE */ +#define EFUSE_RESET (1UL) + +/** + * @defgroup System_APIs System APIs + * @brief System APIs + */ + +/** + * @addtogroup System_APIs + * @{ + */ + +/** + * @defgroup REG_APIs REG APIs + * @brief Register operate APIs + */ + +/** + * @addtogroup REG_APIs + * @{ + */ + +/** + * @brief This function is used to write value to register or memory + * + * @param[in] reg address to be written + * @param[in] val value to write + * + * @return None + * + * @note None + */ +static __inline void tls_reg_write32(unsigned int reg, unsigned int val) +{ + *(TLS_REG *)reg = val; +} + + +/** + * @brief This function is used to read value from register or memory + * + * @param[in] reg address to read + * + * @retval val read from register or memory + * + * @note None + */ +static __inline unsigned int tls_reg_read32(unsigned int reg) +{ + unsigned int val = *(TLS_REG *)reg; + return val; +} + + +/** + * @brief This function is used to write specified bit through + bit-band alias region + * + * @param[in] addr 32-bit aligned byte address where the bit exists. + * @param[in] bit Bit position. + * @param[in] val The value that the bit is set to, 0 or 1. + * + * @return None + * + * @note Only when bit-band mechnism is supported, you can use it + */ +static __inline void tls_bitband_write(volatile unsigned int addr, unsigned int bit, unsigned int val) +{ + unsigned int temp; + + temp = (((unsigned int)(addr) & 0xF0000000) + 0x02000000) \ + +((((unsigned int)(addr)&0xFFFFF)<<5)\ + +( (unsigned int)(bit)<<2)); + + *((volatile unsigned int * )temp) = val; +} + +/** + * @brief This function is used to read a single bit from address + by bit-band alias region + * + * @param[in] addr 32-bit aligned byte address where the bit exists + * @param[in] bit Bit position + * + * @retval The value of the requested bit + * + * @note Only when bit-band mechnism is supported, you can use it + */ +static __inline unsigned int tls_bitband_read(volatile unsigned int addr, unsigned int bit) +{ + unsigned int temp; + + temp = (((unsigned int)(addr) & 0xF0000000) + 0x02000000) \ + +((((unsigned int)(addr)&0xFFFFF)<<5)\ + +( (unsigned int)(bit)<<2)); + + return *((volatile unsigned int *)temp); +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WM_REGS_H */ + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/wm_type_def.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/wm_type_def.h new file mode 100644 index 00000000..4915a2b8 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/include/wm_type_def.h @@ -0,0 +1,163 @@ +/** + * @file wm_type_def.h + * + * @brief WM type redefine + * + * @author winnermicro + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ +#ifndef __WM_TYPE_DEF_H__ +#define __WM_TYPE_DEF_H__ + +#ifdef bool +#undef bool +#endif +#ifdef u8 +#undef u8 +#endif +#ifdef s8 +#undef s8 +#endif +#ifdef u16 +#undef u16 +#endif +#ifdef s16 +#undef s16 +#endif +#ifdef u32 +#undef u32 +#endif +#ifdef s32 +#undef s32 +#endif +#ifdef u64 +#undef u64 +#endif +#ifdef s64 +#undef s64 +#endif + +#ifdef u_char +#undef u_char +#endif +typedef unsigned char u_char; + +#ifdef INT8U +#undef INT8U +#endif +typedef unsigned char INT8U; + +#ifdef INT8S +#undef INT8S +#endif +typedef signed char INT8S; + +typedef unsigned char bool; +typedef unsigned char u8; +typedef signed char s8; +typedef unsigned short u16; +typedef signed short s16; +typedef unsigned int u32; +typedef signed int s32; +typedef unsigned long long u64; +typedef long long s64; + +#if (GCC_COMPILE==0) +#ifdef int32_t +#undef int32_t +#endif +typedef int int32_t; + +#ifdef uint32_t +#undef uint32_t +#endif +typedef unsigned int uint32_t; + +#endif + + +#ifdef ULONG +#undef ULONG +#endif +typedef unsigned long ULONG; + +#ifdef u8_t +#undef u8_t +#endif +typedef unsigned char u8_t; + +#ifdef uint8_t +#undef uint8_t +#endif +typedef unsigned char uint8_t; + +#ifdef u16_t +#undef u16_t +#endif +typedef unsigned short u16_t; + +#ifdef uint16_t +#undef uint16_t +#endif +typedef unsigned short uint16_t; + +#ifdef u32_t +#undef u32_t +#endif +typedef unsigned int u32_t; + + +#ifdef s8_t +#undef s8_t +#endif +typedef signed char s8_t; + +#ifdef s16_t +#undef s16_t +#endif +typedef signed short s16_t; + +#ifdef s32_t +#undef s32_t +#endif +typedef signed int s32_t; +#if (GCC_COMPILE==0) +#ifdef size_t +#undef size_t +#endif +typedef unsigned int size_t; +#endif + +#ifdef err_t +#undef err_t +#endif +typedef signed char err_t; + + +#ifdef mem_ptr_t +#undef mem_ptr_t +#endif +typedef unsigned int mem_ptr_t; + +#ifdef TRUE +#undef TRUE +#endif +#define TRUE 1 + +#ifdef FALSE +#undef FALSE +#endif +#define FALSE 0 + +#define true 1 +#define false 0 + +#define WM_SUCCESS 0 +#define WM_FAILED -1 + +#ifndef IGNORE_PARAMETER +#define IGNORE_PARAMETER(x) ((x) = (x)) +#endif + +#endif diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/boot/Makefile b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/boot/Makefile new file mode 100644 index 00000000..8eb3999e --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/boot/Makefile @@ -0,0 +1,55 @@ + +############################################################# +# Required variables for each makefile +# Discard this section from all parent makefiles +# Expected variables (with automatic defaults): +# CSRCS (all "C" files in the dir) +# SUBDIRS (all subdirs with a Makefile) +# GEN_LIBS - list of libs to be generated () +# GEN_IMAGES - list of images to be generated () +# COMPONENTS_xxx - a list of libs/objs in the form +# subdir/lib to be extracted and rolled up into +# a generated lib/image xxx.a () +# +TOP_DIR = ../../ +sinclude $(TOP_DIR)/tools/tool_chain.def + +#ifndef PDIR +#UP_EXTRACT_DIR = .. +#GEN_LIBS = libboot$(LIB_EXT) + +#ifeq ($(COMPILE), gcc) +#COMPONENTS_libboot += gcc/libboot_gcc$(LIB_EXT) +#else +#COMPONENTS_libboot += armcc/libboot_armcc$(LIB_EXT) +#endif + +#endif + + +############################################################# +# Configuration i.e. compile options etc. +# Target specific stuff (defines etc.) goes in here! +# Generally values applying to a tree are captured in the +# makefile at its root level - these are then overridden +# for a subtree within the makefile rooted therein +# +#DEFINES += + +############################################################# +# Recursion Magic - Don't touch this!! +# +# Each subtree potentially has an include directory +# corresponding to the common APIs applicable to modules +# rooted at that subtree. Accordingly, the INCLUDE PATH +# of a module can only contain the include directories up +# its parent path, and not its siblings +# +# Required for each makefile to inherit from the parent +# + +sinclude $(TOP_DIR)/tools/rules.mk +INCLUDES := $(INCLUDES) -I $(PDIR)include +PDIR := ../$(PDIR) +sinclude $(PDIR)Makefile + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/boot/armcc/Makefile b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/boot/armcc/Makefile new file mode 100644 index 00000000..523273a6 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/boot/armcc/Makefile @@ -0,0 +1,48 @@ + +############################################################# +# Required variables for each makefile +# Discard this section from all parent makefiles +# Expected variables (with automatic defaults): +# CSRCS (all "C" files in the dir) +# SUBDIRS (all subdirs with a Makefile) +# GEN_LIBS - list of libs to be generated () +# GEN_IMAGES - list of images to be generated () +# COMPONENTS_xxx - a list of libs/objs in the form +# subdir/lib to be extracted and rolled up into +# a generated lib/image xxx.a () +# +ifeq ($(COMPILE), gcc) +else +TOP_DIR = ../../../ +sinclude $(TOP_DIR)/tools/tool_chain.def + +ifndef PDIR +GEN_LIBS = libboot$(LIB_EXT) +endif + + +############################################################# +# Configuration i.e. compile options etc. +# Target specific stuff (defines etc.) goes in here! +# Generally values applying to a tree are captured in the +# makefile at its root level - these are then overridden +# for a subtree within the makefile rooted therein +# +#DEFINES += + +############################################################# +# Recursion Magic - Don't touch this!! +# +# Each subtree potentially has an include directory +# corresponding to the common APIs applicable to modules +# rooted at that subtree. Accordingly, the INCLUDE PATH +# of a module can only contain the include directories up +# its parent path, and not its siblings +# +# Required for each makefile to inherit from the parent +# +sinclude $(TOP_DIR)/tools/rules.mk +INCLUDES := $(INCLUDES) -I $(PDIR)include +PDIR := ../$(PDIR) +sinclude $(PDIR)Makefile +endif \ No newline at end of file diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/boot/armcc/misc.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/boot/armcc/misc.c new file mode 100644 index 00000000..7a82bfb3 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/boot/armcc/misc.c @@ -0,0 +1,227 @@ +/** + ****************************************************************************** + * @file misc.c + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file provides all the miscellaneous firmware functions (add-on + * to CMSIS functions). + */ +#if (GCC_COMPILE!=1) + +/* Includes ------------------------------------------------------------------*/ +#include "misc.h" + +/** @addtogroup W600_Driver + * @{ + */ + +/** @defgroup MISC + * @brief MISC driver modules + * @{ + */ + +/** @defgroup MISC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Defines + * @{ + */ + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) +/** + * @} + */ + +/** @defgroup MISC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup: specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @retval None + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ +// assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ +// assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); +// assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); +// assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +void NVIC_Configration(int irqno, FunctionalState irqstatus) +{ + NVIC_InitTypeDef NVIC_InitStruct; + + NVIC_InitStruct.NVIC_IRQChannel = irqno; + NVIC_InitStruct.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStruct.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStruct.NVIC_IRQChannelCmd = irqstatus; + NVIC_Init(&NVIC_InitStruct); +} + + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM + * @arg NVIC_VectTab_FLASH + * @param Offset: Vector Table base offset field. This value must be a multiple + * of 0x200. + * @retval None + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ +// assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); +// assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND + * @arg NVIC_LP_SLEEPDEEP + * @arg NVIC_LP_SLEEPONEXIT + * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ +// assert_param(IS_NVIC_LP(LowPowerMode)); +// assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ +// assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT 2014 Winner Microelectronics Co., Ltd. *****END OF FILE****/ +#endif diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/boot/armcc/retarget.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/boot/armcc/retarget.c new file mode 100644 index 00000000..f62e43d5 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/boot/armcc/retarget.c @@ -0,0 +1,471 @@ +/******************************************************************************/ +/* RETARGET.C: 'Retarget' layer for target-dependent low level functions */ +/******************************************************************************/ + +#include +#include +#include "wm_config.h" +#include "wm_regs.h" +#include +#include +#if (GCC_COMPILE!=1) +//#pragma import(__use_no_semihosting_swi) + +static unsigned int std_libspace[__USER_LIBSPACE_SIZE]; + +void *__user_libspace(void) +{ + return (void *)&std_libspace; +} + +extern int sendchar(int ch); + +struct __FILE { int handle; /* Add whatever you need here */ }; +FILE __stdout; +FILE __stdin; + +int fputc(int ch, FILE *f) +{ + return (sendchar(ch)); +} + + +int ferror(FILE *f) +{ + /* Your implementation of ferror */ + return EOF; +} + +#if TLS_CONFIG_IOUART +int sendchar(int ch) +{ + if(ch == '\n') + iouart_tx_byte('\r'); + iouart_tx_byte((char)ch); +} +#else + +//function: 灏嗘暟鎹浆鎹㈡垚瀛楃涓 +//paramter: +//str : 杞崲涔嬪悗瀛樺湪姝uffer +//num : 瑕佽浆鎹㈢殑鏁版嵁 +//base : 鍗佽繘鍒讹紝鍗佸叚杩涘埗 +//width : 瀵归綈瀹藉害 +//opflag : 鎿嶄綔绗︼紝bit瀹氫箟濡備笅 + +#define P_ALIGN_BIT (0x01<<0) // bit=1 宸﹀榻 bit=0鍙冲榻 +#define P_FILL_BIT (0x01<<1) //bit = 1濉厖'0'锛屽惁鍒欏～鍏' ' +#define P_BIG_BIT (0x01<<2) //bit=1锛屽ぇ鍐欙紝鍚﹀垯灏忓啓 + +int Int2Str(char *str,int num,char base,char width,int opflag) +{ + char temp; + int len = 0; + signed char k = 0; + char *str_bk; + signed char k_bk; + + if(num <0) + { + num = -num; + *str='-'; + str++; + len++; + } + if(0 == num) + { + *str = '0'; + str ++; + k ++; + } + while(num) + { + temp= num%base; + if(temp > 9) // insert hexdecimal--ABCDEF-- + { + temp-=10; + if(opflag & P_BIG_BIT) + *str = temp + 'A'; + else + *str = temp + 'a'; + } + else + { + *str = temp + '0'; + } + num=num/base; + str++; + k++; + } + + if(opflag&P_ALIGN_BIT) //宸﹀榻 + { + str_bk = str; + k_bk = k; //鍏堝浠芥寚閽堝拰闀垮害锛屽掑簭涔嬪悗缁х画 + str --; + k --; + while(k>0) + { + temp = *str; + *str = *(str-k); + *(str-k) = temp; + str--; + k-=2; + } + k = k_bk; + str = str_bk; + } + + //涓嶈冻瀹藉害鐨勭敤' '琛ラ綈 + while(width>k) + { + if(opflag&P_FILL_BIT) + { + *str++ ='0'; + } + else + { + *str++ =' '; + } + k++; + } + + len=len+k; + *str-- = '\0'; + k--; + if(0 == (opflag&P_ALIGN_BIT)) //鍙冲榻 + { + //鍊掑簭 + while(k>0) + { + temp = *str; + *str = *(str-k); + *(str-k) = temp; + str--; + k-=2; + } + } + return len; +} + +static int IP2Str(unsigned char v4v6, unsigned int *inuint, char *outtxt) +{ + unsigned char i; + unsigned char j = 0; + unsigned char k; + unsigned char h; + unsigned char m; + unsigned char l; + unsigned char bit; + + if (4 == v4v6) + { + for(i = 0; i < 4; i++) + { + bit = (*inuint >> (8 * i)) & 0xff; + h = bit / 100; + if (h) + outtxt[j++] = '0' + h; + m = (bit % 100) / 10; + if (m) + { + outtxt[j++] = '0' + m; + } + else + { + if (h) + outtxt[j++] = '0'; + } + l = (bit % 100) % 10; + outtxt[j++] = '0' + l; + outtxt[j++] = '.'; + } + } + else + { + for (k = 0; k < 4; k++) + { + for(i = 0; i < 4; i++) + { + m = (*inuint >> (8 * i)) & 0xff; + h = m >> 4; + l = m & 0xf; + if (h > 9) + outtxt[j++] = 'A' + h - 10; + else + outtxt[j++]= '0' + h; + if (l > 9) + outtxt[j++] = 'A' + l - 10; + else + outtxt[j++] = '0' + l; + if (0 != (i % 2)) + outtxt[j++] = ':'; + } + inuint++; + } + } + + outtxt[j - 1] = 0; + return j - 1; +} + +static int Mac2Str(unsigned char *inchar, char *outtxt) +{ + unsigned char hbit,lbit; + unsigned int i; + + for(i = 0; i < 6; i++)/* mac length */ + { + hbit = (*(inchar + i) & 0xf0) >> 4; + lbit = *(inchar + i ) & 0x0f; + if (hbit > 9) + outtxt[3 * i] = 'A' + hbit - 10; + else + outtxt[3 * i]= '0' + hbit; + if (lbit > 9) + outtxt[3 * i + 1] = 'A' + lbit - 10; + else + outtxt[3 * i + 1] = '0' + lbit; + outtxt[3 * i + 2] = '-'; + } + + outtxt[3 * (i - 1) + 2] = 0; + + return 3 * (i - 1) + 2; +} + +int wm_vprintf(const char *fmt, va_list arg_ptr) +{ + unsigned char width=0; //淇濈暀瀹藉害 + unsigned int len; //鏁版嵁瀹藉害 + char *fp = (char *)fmt; + //va_list arg_ptr; + char *pval; + int opflag = 0; + char store[40]; + char c; + int i; + char* str; + + //va_start(arg_ptr, fmt); //arg_ptr 鎸囧悜绗竴涓弬鏁 + while (*fp !='\0') + { + c = *fp++; + if (c != '%') + { + sendchar(c); + } + else + { + width = 0; //鑾峰彇鏁版嵁瀹藉害 + opflag = 0; + if('-' == *fp) + { + opflag |= P_ALIGN_BIT;//宸﹀榻 + fp ++; + } + if('0' == *fp) //鍓嶉潰琛ラ浂 + { + opflag |= P_FILL_BIT; //琛ラ浂 + fp ++; + } + + while(*fp>='0'&&*fp<='9') + { + width = width * 10 + (*fp) - '0'; + fp++; + } + if('.' == *fp) //娴偣杩愮畻鏆傛椂娌＄敤锛屼笉澶勭悊 + { + fp ++; + while(*fp>='0'&&*fp<='9') + { + fp++; + } + } + + while('l' == *fp || 'h' == *fp) + { + fp ++; + } + + switch (*fp) + { + case 'c': + case 'C': + c = (char)va_arg(arg_ptr, int); + sendchar(c); + break; + case 'd': + case 'i': + case 'u': + i = va_arg(arg_ptr, int); + str = store; + Int2Str(store,i,10,width,opflag); + while( *str != '\0') sendchar(*str++); + break; + case 'x': + case 'X': + i = va_arg(arg_ptr, int); + str = store; + if('X' == *fp) + { + opflag |= P_BIG_BIT; + } + Int2Str(store,i,16,width,opflag); + while( *str != '\0') sendchar(*str++); + break; + case 'o': + i = va_arg(arg_ptr, int); + str = store; + Int2Str(store,i,8,width,opflag); + while( *str != '\0') sendchar(*str++); + break; + case 's': + case 'S': + pval=va_arg(arg_ptr,char*); + len = strlen(pval); + if((width > len) && (0 == (opflag&P_ALIGN_BIT))) //鍙冲榻 + { + for(i = 0;i < (width - len);i ++) //宸﹁竟琛ョ┖鏍 + { + sendchar(' '); + } + } + for(i=0;i < len;i++) + { + sendchar(pval[i]); + } + if((width > len) && (opflag&P_ALIGN_BIT)) //宸﹀榻 + { + for(i = 0;i < (width - len);i ++) //鍙宠竟琛ョ┖鏍 + { + sendchar(' '); + } + } + break; + case 'v':/* ip v4 address */ + i = va_arg(arg_ptr, int); + len = IP2Str(4, (unsigned int *)&i, store); + if((width > len) && (0 == (opflag&P_ALIGN_BIT))) //鍙冲榻 + { + for(i = 0;i < (width - len);i ++) //宸﹁竟琛ョ┖鏍 + { + sendchar(' '); + } + } + str = store; + while( *str != '\0') sendchar(*str++); + if((width > len) && (opflag&P_ALIGN_BIT)) //宸﹀榻 + { + for(i = 0;i < (width - len);i ++) //鍙宠竟琛ョ┖鏍 + { + sendchar(' '); + } + } + break; + case 'V':/* ip v6 address */ + pval=va_arg(arg_ptr,char*); + len = IP2Str(6, (unsigned int *)pval, store); + if((width > len) && (0 == (opflag&P_ALIGN_BIT))) //鍙冲榻 + { + for(i = 0;i < (width - len);i ++) //宸﹁竟琛ョ┖鏍 + { + sendchar(' '); + } + } + str = store; + while( *str != '\0') sendchar(*str++); + if((width > len) && (opflag&P_ALIGN_BIT)) //宸﹀榻 + { + for(i = 0;i < (width - len);i ++) //鍙宠竟琛ョ┖鏍 + { + sendchar(' '); + } + } + break; + case 'M':/* mac address */ + pval = va_arg(arg_ptr, char*); + len = Mac2Str((unsigned char *)pval, store); + if((width > len) && (0 == (opflag&P_ALIGN_BIT))) //鍙冲榻 + { + for(i = 0;i < (width - len);i ++) //宸﹁竟琛ョ┖鏍 + { + sendchar(' '); + } + } + str = store; + while( *str != '\0') sendchar(*str++); + if((width > len) && (opflag&P_ALIGN_BIT)) //宸﹀榻 + { + for(i = 0;i < (width - len);i ++) //鍙宠竟琛ョ┖鏍 + { + sendchar(' '); + } + } + break; + case '%': + sendchar('%'); + break; + default: + break; + } + fp++; + } + } + //va_end(arg_ptr); + return 0; + +} + +int wm_printf(const char *fmt,...) +{ + va_list ap; + + va_start(ap, fmt); + wm_vprintf(fmt,ap); + va_end(ap); + return 0; +} + + + +int sendchar(int ch) +{ +#if WM_CONFIG_DEBUG_UART1 + tls_reg_write32(HR_UART1_INT_MASK, 0x3); + if(ch == '\n') + { + while (tls_reg_read32(HR_UART1_FIFO_STATUS)&0x3F); + tls_reg_write32(HR_UART1_TX_WIN, '\r'); + } + while(tls_reg_read32(HR_UART1_FIFO_STATUS)&0x3F); + tls_reg_write32(HR_UART1_TX_WIN, (char)ch); + tls_reg_write32(HR_UART1_INT_MASK, 0x0); +#else + tls_reg_write32(HR_UART0_INT_MASK, 0x3); + // if(ch == '\n') + // { + // while (tls_reg_read32(HR_UART0_FIFO_STATUS)&0x3F); + // tls_reg_write32(HR_UART0_TX_WIN, '\r'); + // } + while(tls_reg_read32(HR_UART0_FIFO_STATUS)&0x3F); + tls_reg_write32(HR_UART0_TX_WIN, (char)ch); + tls_reg_write32(HR_UART0_INT_MASK, 0x0); +#endif + return ch; +} +#endif + +void _ttywrch(int ch) +{ + sendchar(ch); +} + +void _sys_exit(int return_code) +{ +label: + goto label; /* endless loop */ +} + +#endif diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/boot/armcc/startup.s b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/boot/armcc/startup.s new file mode 100644 index 00000000..9d9f07de --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/boot/armcc/startup.s @@ -0,0 +1,310 @@ +;******************** Copyright (c) 2014 Winner Micro Electronic Design Co., Ltd. ******************** +;* File Name : startup_venus.s +;* Author : +;* Version : +;* Date : +;* Description : +; Stack Configuration +; Stack Size (in Bytes) +; + +Stack_Size EQU 0x00000400 + + AREA |.bss|, BSS, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes):at least 80Kbyte +; + +Heap_Size EQU 0 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT PendSV_Handler + IMPORT OS_CPU_SysTickHandler +; IMPORT UART0_IRQHandler +; IMPORT UART1_IRQHandler +; IMPORT tls_wl_rx_isr +; IMPORT tls_wl_mgmt_tx_isr +; IMPORT tls_wl_data_tx_isr +; IMPORT tls_wl_mac_isr + IMPORT TIM0_IRQHandler + IMPORT TIM1_IRQHandler + IMPORT TIM2_IRQHandler + IMPORT TIM3_IRQHandler + IMPORT TIM4_IRQHandler + IMPORT TIM5_IRQHandler +; IMPORT WDG_IRQHandler + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD OS_CPU_SysTickHandler ; SysTick Handler + + ; External Interrupts + DCD SDIO_RX_IRQHandler ; Window Watchdog + DCD SDIO_TX_IRQHandler ; PVD through EXTI Line detect + DCD SDIO_RX_CMD_IRQHandler ; Tamper + DCD SDIO_TX_CMD_IRQHandler ; RTC + DCD tls_wl_mac_isr ; Flash + DCD 0 ; rf_cfg + DCD tls_wl_rx_isr ; EXTI Line 0 + DCD tls_wl_mgmt_tx_isr ; EXTI Line 1 + DCD tls_wl_data_tx_isr ; EXTI Line 2 + DCD PMU_TIMER1_IRQHandler ; pmu_timer1 + DCD PMU_TIMER0_IRQHandler ; pmu_timer0 + DCD PMU_GPIO_WAKE_IRQHandler ; gpio + DCD PMU_SDIO_WAKE_IRQHandler ; sdio + DCD DMA_Channel0_IRQHandler ; DMA1 Channel 3 + DCD DMA_Channel1_IRQHandler ; DMA1 Channel 4 + DCD DMA_Channel2_IRQHandler ; DMA1 Channel 5 + DCD DMA_Channel3_IRQHandler ; DMA1 Channel 6 + DCD DMA_Channel4_7_IRQHandler ; DMA1 Channel 7 + DCD DMA_BRUST_IRQHandler ; ADC1 & ADC2 + DCD I2C_IRQHandler ; USB High Priority or CAN1 TX + DCD ADC_IRQHandler ; USB Low Priority or CAN1 RX0 + DCD SPI_LS_IRQHandler ; CAN1 RX1 + DCD SPI_HS_IRQHandler ; CAN1 SCE + DCD UART0_IRQHandler ; EXTI Line 9..5 + DCD UART1_IRQHandler ; TIM1 Break + DCD WM_GPIOA_IRQHandler ; TIM1 Update + DCD TIM0_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD TIM5_IRQHandler ; I2C1 Event + DCD WDG_IRQHandler ; watch dog handle + DCD PMU_IRQHandler ; I2C2 Event + DCD FLASH_IRQHandler ; I2C2 Error + DCD PWM_IRQHandler ; SPI1 + DCD I2S_IRQHandler ; SPI2 + DCD PMU_RTC_IRQHandler + DCD RSA_IRQHandler + DCD CRYPTION_IRQHandler ;CRYPTION + DCD WM_GPIOB_IRQHandler ; GBIOB + DCD UART2_IRQHandler ; USART1 + DCD 0 ; +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +;PendSV_Handler PROC +; EXPORT PendSV_Handler [WEAK] +; B . +; ENDP +;SysTick_Handler PROC +; EXPORT SysTick_Handler [WEAK] +; B . +; ENDP +tls_wl_mac_isr\ + PROC + EXPORT tls_wl_mac_isr [WEAK] + B . + ENDP +tls_wl_rx_isr\ + PROC + EXPORT tls_wl_rx_isr [WEAK] + B . + ENDP +tls_wl_mgmt_tx_isr\ + PROC + EXPORT tls_wl_mgmt_tx_isr [WEAK] + B . + ENDP +tls_wl_data_tx_isr\ + PROC + EXPORT tls_wl_data_tx_isr [WEAK] + B . + ENDP +Default_Handler PROC + + EXPORT SDIO_RX_IRQHandler [WEAK] + EXPORT SDIO_TX_IRQHandler [WEAK] + EXPORT SDIO_RX_CMD_IRQHandler [WEAK] + EXPORT SDIO_TX_CMD_IRQHandler [WEAK] + EXPORT RSV_IRQHandler [WEAK] + EXPORT PMU_RTC_IRQHandler [WEAK] + EXPORT PMU_TIMER1_IRQHandler [WEAK]; pmu_timer1 + EXPORT PMU_TIMER0_IRQHandler [WEAK]; pmu_timer0 + EXPORT PMU_GPIO_WAKE_IRQHandler [WEAK]; gpio + EXPORT PMU_SDIO_WAKE_IRQHandler [WEAK] + EXPORT DMA_Channel0_IRQHandler [WEAK] + EXPORT DMA_Channel1_IRQHandler [WEAK] + EXPORT DMA_Channel2_IRQHandler [WEAK] + EXPORT DMA_Channel3_IRQHandler [WEAK] + EXPORT DMA_Channel4_7_IRQHandler [WEAK] + EXPORT DMA_BRUST_IRQHandler [WEAK] + EXPORT I2C_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT SPI_LS_IRQHandler [WEAK] + EXPORT SPI_HS_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT WM_GPIOA_IRQHandler [WEAK] +; EXPORT TIM0_IRQHandler [WEAK] +; EXPORT TIM1_IRQHandler [WEAK] +; EXPORT TIM2_IRQHandler [WEAK] +; EXPORT TIM3_IRQHandler [WEAK] +; EXPORT TIM4_IRQHandler [WEAK] +; EXPORT TIM5_IRQHandler [WEAK] + EXPORT WDG_IRQHandler [WEAK] + EXPORT PMU_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT PWM_IRQHandler [WEAK] + EXPORT I2S_IRQHandler [WEAK] + EXPORT PMU_6IRQHandler [WEAK] + EXPORT RSA_IRQHandler [WEAK] + EXPORT CRYPTION_IRQHandler [WEAK] + EXPORT WM_GPIOB_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + +SDIO_RX_IRQHandler +SDIO_TX_IRQHandler +SDIO_RX_CMD_IRQHandler +SDIO_TX_CMD_IRQHandler +;MAC_IRQHandler +RSV_IRQHandler +;SEC_RX_IRQHandler +;SEC_TX_MNGT_IRQHandler +;SEC_TX_DAT_IRQHandler +PMU_RTC_IRQHandler +PMU_TIMER1_IRQHandler +PMU_TIMER0_IRQHandler +PMU_GPIO_WAKE_IRQHandler +PMU_SDIO_WAKE_IRQHandler +DMA_Channel0_IRQHandler +DMA_Channel1_IRQHandler +DMA_Channel2_IRQHandler +DMA_Channel3_IRQHandler +DMA_Channel4_7_IRQHandler +DMA_BRUST_IRQHandler +I2C_IRQHandler +ADC_IRQHandler +SPI_LS_IRQHandler +SPI_HS_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +WM_GPIOA_IRQHandler +;TIM0_IRQHandler +;TIM1_IRQHandler +;TIM2_IRQHandler +;TIM3_IRQHandler +;TIM4_IRQHandler +;TIM5_IRQHandler +WDG_IRQHandler +PMU_IRQHandler +FLASH_IRQHandler +PWM_IRQHandler +I2S_IRQHandler +PMU_6IRQHandler +RSA_IRQHandler +CRYPTION_IRQHandler +WM_GPIOB_IRQHandler +UART2_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* Copyright (c) 2014 Winner Micro Electronic Design Co., Ltd. *****END OF FILE***** diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/VS10XX.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/VS10XX.c new file mode 100644 index 00000000..0cd47ee8 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/VS10XX.c @@ -0,0 +1,261 @@ +/** + * @file VS10XX.c + * + * @brief VS10XX driver + * + * @author dave + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ +#include +#include "VS10XX.h" +#include "wm_hostspi.h" +#include "wm_gpio.h" +#include "wm_config.h" + +#if CODEC_VS1053 +extern void delay_us(unsigned int time); +extern int gSpiCsFlag; +void codec_data_cs_low(void) +{ + while (0 == tls_gpio_read(SPI_CS_PIN)) + { +// printf("\nflash is busy,codec data cs wait...\n"); + tls_os_time_delay(1); + } + gSpiCsFlag = 1; + tls_gpio_cfg(VS_XDCS, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_FLOATING); + tls_gpio_write(VS_XDCS, 0); +} + +void codec_data_cs_high(void) +{ + tls_gpio_cfg(VS_XDCS, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_FLOATING); + tls_gpio_write(VS_XDCS, 1); + gSpiCsFlag = 0; +} + +void codec_cmd_cs_low(void) +{ + while (0 == tls_gpio_read(SPI_CS_PIN)) + { +// printf("\nflash is busy,codec cmd cs wait...\n"); + tls_os_time_delay(1); + } + gSpiCsFlag = 1; + tls_gpio_cfg(VS_XCS, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_FLOATING); + tls_gpio_write(VS_XCS, 0); +} + +void codec_cmd_cs_high(void) +{ + tls_gpio_cfg(VS_XCS, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_FLOATING); + tls_gpio_write(VS_XCS, 1); + gSpiCsFlag = 0; +} + +int VS_Wait_Timeout(void) +{ + u16 retry = 0; + + while ((tls_gpio_read(VS_DQ) == 0) && (retry < 0xFFFE)) + { + retry++; + // delay_us(50); + } + if (retry >= 0xFFFE) + { + printf("VS1053 wait timeout\r\n"); + return 1; + } + return 0; +} + +const u16 wav_plugin[40] = /* Compressed plugin */ +{ + 0x0007, 0x0001, 0x8010, 0x0006, 0x001c, 0x3e12, 0xb817, 0x3e14, /* 0 */ + 0xf812, 0x3e01, 0xb811, 0x0007, 0x9717, 0x0020, 0xffd2, 0x0030, /* 8 */ + 0x11d1, 0x3111, 0x8024, 0x3704, 0xc024, 0x3b81, 0x8024, 0x3101, /* 10 */ + 0x8024, 0x3b81, 0x8024, 0x3f04, 0xc024, 0x2808, 0x4800, 0x36f1, /* 18 */ + 0x9811, 0x0007, 0x0001, 0x8028, 0x0006, 0x0002, 0x2a00, 0x040e, +}; + +//vs10xx瑁呰浇patch. +//patch锛歱atch棣栧湴鍧 +//len锛歱atch闀垮害 +void VS_Load_Patch(u16 * patch, u16 len) +{ + u16 i; + u16 addr, n, val; + + for (i = 0; i < len;) + { + addr = patch[i++]; + n = patch[i++]; + if (n & 0x8000U) // RLE run, replicate n samples + { + n &= 0x7FFF; + val = patch[i++]; + while (n--) + { + VS_WR_Cmd(addr, val); + } + } + else // copy run, copy n sample + { + while (n--) + { + val = patch[i++]; + VS_WR_Cmd(addr, val); + } + } + } +} + +//纭浣峂P3 +u8 VS_HD_Reset(void) +{ + tls_gpio_write(VS_XDCS, 1); // 鍙栨秷鏁版嵁浼犺緭 + tls_gpio_write(VS_XCS, 1); + tls_gpio_write(VS_RST, 0); + tls_os_time_delay(10); + tls_gpio_write(VS_RST, 1); + return VS_Wait_Timeout(); +} + +//杞浣峍S10XX +void VS_Soft_Reset(void) +{ + tls_spi_setup(TLS_SPI_MODE_0, TLS_SPI_CS_LOW, VS_SPI_CLK_LOW); + VS_WR_Cmd(SPI_MODE, 0x0816); + VS_WR_Cmd(SPI_CLOCKF, 0x9800); + VS_WR_Cmd(SPI_DECODE_TIME, 0x0000); + VS_WR_Cmd(SPI_DECODE_TIME, 0x0000); +} + +//鍚慥S10XX鍐欏懡浠 +//address:鍛戒护鍦板潃 +//data:鍛戒护鏁版嵁 +void VS_WR_Cmd(u8 address, u16 data) +{ + u8 temp[5]; + + if (VS_Wait_Timeout()) + { + return; + } + codec_cmd_cs_low(); + temp[0] = VS_WRITE_COMMAND; + temp[1] = address; + temp[2] = data >> 8; + temp[3] = data & 0xff; + tls_spi_write(temp, 4); + codec_cmd_cs_high(); +} + +//璇籚S10XX鐨勫瘎瀛樺櫒 +//娉ㄦ剰涓嶈鐢ㄥ嶉熻鍙,浼氬嚭閿 +u16 VS_RD_Reg(u8 address) +{ + u8 txbuf[2]; + u8 rxbuf[2]; + + if (VS_Wait_Timeout()) + { + return; + } + codec_cmd_cs_low(); + txbuf[0] = VS_READ_COMMAND; + txbuf[1] = address; + tls_spi_read_with_cmd(txbuf, 2, rxbuf, 2); + codec_cmd_cs_high(); + return ((rxbuf[0] << 8) | rxbuf[1]); +} + +//寰楀埌mp3鐨勬挱鏀炬椂闂磏 sec +u16 VS_Get_DecodeTime(void) +{ + tls_spi_setup(TLS_SPI_MODE_0, TLS_SPI_CS_LOW, VS_SPI_CLK_LOW); + return VS_RD_Reg(SPI_DECODE_TIME); +} + +void vs_set_vol(int vol) +{ + int tmp; + u16 volt = 0; + + tmp = vol; + if (vol >= 0 && vol <= 100) + { + volt = tmp << 8; + volt += tmp; + printf("\nvolt==%x\n", volt); + tls_spi_setup(TLS_SPI_MODE_0, TLS_SPI_CS_LOW, VS_SPI_CLK_LOW); + VS_WR_Cmd(SPI_VOL, volt); // 璁鹃煶閲 + } +} + +void vs_mute(void) +{ + tls_spi_setup(TLS_SPI_MODE_0, TLS_SPI_CS_LOW, VS_SPI_CLK_LOW); + VS_WR_Cmd(SPI_VOL, 0xfefe); // 璁鹃煶閲 +} + +//婵娲籔CM 褰曢煶妯″紡 +//agc:0,鑷姩澧炵泭.1024鐩稿綋浜1鍊,512鐩稿綋浜0.5鍊,鏈澶у65535=64鍊 +void VS_Rec_Mode(u16 agc) +{ + tls_spi_setup(TLS_SPI_MODE_0, TLS_SPI_CS_LOW, VS_SPI_CLK_LOW); + VS_WR_Cmd(SPI_BASS, 0x0000); + VS_WR_Cmd(SPI_AICTRL0, 8000); // 璁剧疆閲囨牱鐜,璁剧疆涓8Khz + VS_WR_Cmd(SPI_AICTRL1, agc); // 璁剧疆澧炵泭,0,鑷姩澧炵泭.1024鐩稿綋浜1鍊,512鐩稿綋浜0.5鍊,鏈澶у65535=64鍊 + // + VS_WR_Cmd(SPI_AICTRL2, 0); // 璁剧疆澧炵泭鏈澶у,0,浠ｈ〃鏈澶у65536=64X + VS_WR_Cmd(SPI_AICTRL3, 6); // 宸﹂氶亾(MIC鍗曞０閬撹緭鍏) + VS_WR_Cmd(SPI_CLOCKF, 0X2000); // 璁剧疆VS10XX鐨勬椂閽,MULT:2鍊嶉;ADD:涓嶅厑璁;CLK:12.288Mhz + VS_WR_Cmd(SPI_MODE, 0x1804); // MIC,褰曢煶婵娲 + tls_os_time_delay(1); // 绛夊緟鑷冲皯1.35ms + VS_Load_Patch((u16 *) wav_plugin, 40); // VS1053鐨刉AV褰曢煶闇瑕乸atch +} + +int VS_Rec_GetData(char *recbuf) +{ + int datalen, idx; + u16 data; + + tls_spi_setup(TLS_SPI_MODE_0, TLS_SPI_CS_LOW, VS_SPI_CLK_HIGH); + datalen = VS_RD_Reg(SPI_HDAT1); + if ((datalen >= VS_REC_PKG_SIZE) && (datalen < 896)) + { + idx = 0; + while (idx < VS_REC_PKG_SIZE) + { + data = VS_RD_Reg(SPI_HDAT0); + recbuf[idx++] = data & 0XFF; + recbuf[idx++] = data >> 8; + } + return 1; + } + else if (datalen >= 896) + { + printf("#%d\r\n", datalen); + } + return 0; +} + +//鍒濆鍖朧S10XX鐨処O鍙 +void VS_Init(void) +{ + tls_gpio_cfg(VS_RST, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_FLOATING); + tls_gpio_write(VS_RST, 1); + + tls_gpio_cfg(VS_XCS, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_FLOATING); + tls_gpio_write(VS_XCS, 1); + + tls_gpio_cfg(VS_XDCS, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_FLOATING); + tls_gpio_write(VS_XDCS, 1); + + tls_gpio_cfg(VS_DQ, WM_GPIO_DIR_INPUT, WM_GPIO_ATTR_PULLHIGH); +} + +#endif diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_7816.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_7816.c new file mode 100644 index 00000000..3d7428e6 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_7816.c @@ -0,0 +1,291 @@ +/**************************************************************************//** + * @file wm_i2s.c + * @author + * @version + * @date + * @brief + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. All rights reserved. + *****************************************************************************/ + +#include +#include +#include +#include "wm_regs.h" +#include "wm_7816.h" +#include "wm_gpio.h" +#include "wm_uart.h" +#include "wm_cpu.h" + +#include "wm_osal.h" + +#define DEBUG_7816 1 + +#if DEBUG_7816 +#define PRINT_DEBUG(fmt, args...) do{(printf("[DEBUG] "), printf(fmt, ##args));}while(0) +#else +#define PRINT_DEBUG(fmt, args...) +#endif + +#define SYS_CLK (40000000) + +sc_io_map sc_io; + +/** + * @brief + * This function is used to config the pin in gpio or 7816 mode for the 7816 power on timing + * @param[in] mode : 1--gpio mode ; 0--7816 mode + * @retval + */ +void wm_sc_io_clk_config(uint8_t mode) +{ + if (sc_io.initialed == 0) + { + printf("error : 7816 io map must init....\r\n"); + return ; + } + if (mode) //gpio mode + { + tls_io_cfg_set(sc_io.clk_pin_num, WM_IO_OPTION5); + tls_io_cfg_set(sc_io.io_pin_num, WM_IO_OPTION5); + tls_gpio_cfg(sc_io.clk_pin_num, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_PULLHIGH); + tls_gpio_cfg(sc_io.io_pin_num, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_PULLHIGH); + } + else //7816 mode + { + tls_io_cfg_set(sc_io.clk_pin_num, sc_io.clk_opt); + tls_io_cfg_set(sc_io.io_pin_num, sc_io.io_opt); + } +} + +/** + * @brief + * This function is used to config the block guard time param in 7816 mode + * @param[in] bgt : the value of blcok guard time will be set + * @retval + */ +void wm_sc_set_bgt(uint8_t bgt) +{ + uint32_t reg; + bgt = (bgt > 0x1f) ? 0x1F : bgt; + reg = tls_reg_read32(HR_UART2_LINE_CTRL); + reg &= ~(0x1f << 11); + reg |= (bgt << 11); + tls_reg_write32(HR_UART2_LINE_CTRL, reg); +} + +/** + * @brief + * This function is used to config the tx retry count when detect err signal + * @param[in] count : the value of retry time will be set 7 for max + * @retval + */ +void wm_sc_tx_retry_times(uint8_t count) +{ + uint32_t reg; + reg = tls_reg_read32(HR_UART2_LINE_CTRL); + reg &= ~(0x7 << 16); + tls_reg_write32(HR_UART2_LINE_CTRL, reg|(count<<16)); + tls_bitband_write(HR_UART2_LINE_CTRL, 23, 1); +} + +/** + * @brief + * This function is used to config the rx retry count when detect parity error + * @param[in] count : the value of retry time will be set 7 for max + * @retval + */ +void wm_sc_rx_retry_times(uint8_t count) +{ + uint32_t reg; + reg = tls_reg_read32(HR_UART2_LINE_CTRL); + reg &= ~(0x7 << 20); + tls_reg_write32(HR_UART2_LINE_CTRL, reg|(count<<20)); + tls_bitband_write(HR_UART2_LINE_CTRL, 19, 1); +} + +/** + * @brief + * This function is used to config the etu param + * @param[in] etu : the value of etu will be set + * @retval + */ +void wm_sc_set_etu(uint16_t etu) +{ + uint32_t reg; + + reg = tls_reg_read32(HR_UART2_BAUD_RATE_CTRL); + reg &= ~ 0xFFFF; + reg |= etu; + tls_reg_write32(HR_UART2_BAUD_RATE_CTRL, reg); +} + +/** + * @brief + * This function config the module clock freq + * @param[in] freq : the value of clock freq + * @retval + */ +void wm_sc_set_frequency(uint32_t freq) +{ + uint32_t reg; + uint8_t div; + tls_sys_clk clk; + + tls_sys_clk_get(&clk); + + div = (clk.apbclk * 1000000 + freq)/(2 * freq) - 1; + + reg = tls_reg_read32(HR_UART2_BAUD_RATE_CTRL); + reg &= ~ 0x3F0000; + reg |= (div<<16); + tls_reg_write32(HR_UART2_BAUD_RATE_CTRL, reg); +} + +/** + * @brief + * close af to use PB29 and PB30(uart2_rx as default if af is on) as gpio + * @retval + */ +void wm_sc_powerInit(void) +{ +#ifdef WM_SC_PWR_PIN + u32 regValue; + + // PB29 AF close, used as GPIO + regValue = tls_reg_read32(HR_GPIOB_AFSEL); + regValue &= ~0x20000000; + tls_reg_write32(HR_GPIOB_AFSEL, regValue); + + // PB30 AF close, used as GPIO + regValue = tls_reg_read32(HR_GPIOB_AFSEL); + regValue &= ~0x40000000; + tls_reg_write32(HR_GPIOB_AFSEL, regValue); +#endif +} + +/** + * @brief + * power on the 7816 device if power is controled by GPIO + * @retval + */ +void wm_sc_poweron(void) +{ +#ifdef WM_SC_PWR_PIN + tls_gpio_cfg(WM_SC_PWR_PIN, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_PULLHIGH); + tls_gpio_write(WM_SC_PWR_PIN, 1); +#endif +} + +/** + * @brief + * power off the 7816 device if power is controled by GPIO + * @retval + */ +void wm_sc_poweroff(void) +{ +#ifdef WM_SC_PWR_PIN + tls_gpio_cfg(WM_SC_PWR_PIN, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_PULLHIGH); + tls_gpio_write(WM_SC_PWR_PIN, 0); +#endif +} + +/** + * @brief + * driver the reset gpio in low level + * @retval + */ +void wm_sc_rst_low(void) +{ +#ifdef WM_SC_RST_PIN + tls_gpio_cfg(WM_SC_RST_PIN, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_PULLHIGH); + tls_gpio_write(WM_SC_RST_PIN, 0); +#endif +} + +/** + * @brief + * driver the reset gpio in high level + * @retval + */ +void wm_sc_rst_high(void) +{ +#ifdef WM_SC_RST_PIN + tls_gpio_cfg(WM_SC_RST_PIN, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_PULLHIGH); + tls_gpio_write(WM_SC_RST_PIN, 1); +#endif +} + +/** + * @brief + * hotrest the 7816 device obey the 7816-3 timing + * @retval + */ +void wm_sc_hotreset(void) +{ + uint32_t delay = 0xffff; + + /* set the rst pin to low */ + wm_sc_rst_low(); + /* delay */ + while(delay--); + /* set f/d to default 372 */ + wm_sc_set_etu(WM_SC_DEFAULT_FD); + /* set the rst pin to high */ + wm_sc_rst_high(); +} + +/** + * @brief + * colreset the 7816 device obey the 7816-3 timing + * @retval + */ +void wm_sc_colreset(void) +{ + /* power down */ + wm_sc_poweroff(); + /* select the clk io in gpio mode */ + wm_sc_io_clk_config(1); + /* reset the clk pin */ + tls_gpio_write(sc_io.clk_pin_num, 0); + /* reset the io pin */ + tls_gpio_write(sc_io.io_pin_num, 0); + /* set the ret pin to low */ + wm_sc_rst_low(); + /* power on the card */ + wm_sc_poweron(); + /* config the model in 7816 mode */ + wm_sc_7816_mode(1); + /* select the clk io pin in 7816 mode */ + wm_sc_io_clk_config(0); + /* config the output clock freq*/ + wm_sc_set_frequency(5000000); + /* set the F/D to default (372)*/ + wm_sc_set_etu(WM_SC_DEFAULT_FD); + /* set the rst pin to high */ + wm_sc_rst_high(); +} + +/** + * @brief + * deactive the 7816 device obey the 7816-3 timing + * @retval + */ +void wm_sc_deactive(void) +{ + /* set the rst pin in low level*/ + wm_sc_rst_low(); + /* select the clk and io pin to 7816 mode */ + wm_sc_io_clk_config(0); + /* disable the output clock */ + wm_sc_clk_enable(0); + /* select the clk and io pin to gpio mode */ + wm_sc_io_clk_config(1); + /* set the clk pin to low */ + tls_gpio_write(sc_io.clk_pin_num, 0); + /* set the io pin to low */ + tls_gpio_write(sc_io.io_pin_num, 0); + /* set the power pin to low */ + wm_sc_poweroff(); +} + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_adc.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_adc.c new file mode 100644 index 00000000..16fad7ac --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_adc.c @@ -0,0 +1,503 @@ + +/***************************************************************************** +* +* File Name : wm_adc.c +* +* Description: adc Driver Module +* +* Copyright (c) 2014 Winner Microelectronics Co., Ltd. +* All rights reserved. +* +* Author : dave +* +* Date : 2014-8-15 +*****************************************************************************/ +#include +#include +#include +#include "wm_regs.h" +#include "wm_adc.h" +#include "wm_dma.h" +#include "misc.h" +#include "wm_io.h" +#include "wm_irq.h" + + +static u16 adc_offset = 0; + +volatile ST_ADC gst_adc; +volatile u8 adc_irq_flag = 0; +void ADC_IRQHandler(void) +{ + u16 adcvalue; + int reg; + + reg = tls_reg_read32(HR_SD_ADC_CONFIG_REG); + if(reg & CONFIG_ADC_INT) //ADC涓柇 + { + adc_irq_flag = 1; + tls_adc_clear_irq(ADC_INT_TYPE_ADC); + adcvalue = tls_read_adc_result(); + if(gst_adc.adc_cb) + gst_adc.adc_cb(&adcvalue,1); + } + if(reg & CONFIG_ADC_INT_CMP) + { + tls_adc_clear_irq(ADC_INT_TYPE_ADC_COMP); + if(gst_adc.adc_bigger_cb) + gst_adc.adc_bigger_cb(NULL, 0); + } + +} + +static void adc_dma_isr_callbk(void) +{ + if(gst_adc.adc_dma_cb) + gst_adc.adc_dma_cb((u16 *)(ADC_DEST_BUFFER_DMA), gst_adc.valuelen); +} + + +void tls_adc_init(u8 ifusedma,u8 dmachannel) +{ + tls_reg_write32(HR_SD_ADC_CONFIG_REG, 0x0); + tls_irq_enable(ADC_IRQn); + +//娉ㄥ唽涓柇鍜宑hannel鏈夊叧锛屾墍浠ラ渶瑕佸厛璇锋眰 + if(ifusedma) + { + gst_adc.dmachannel = tls_dma_request(dmachannel, NULL); //璇锋眰dma锛屼笉瑕佺洿鎺ユ寚瀹氾紝鍥犱负璇锋眰鐨刣ma鍙兘浼氳鍒殑浠诲姟浣跨敤 + tls_dma_irq_register(gst_adc.dmachannel, (void(*)(void*))adc_dma_isr_callbk, NULL, TLS_DMA_IRQ_TRANSFER_DONE); + } + + //printf("\ndma channel = %d\n",gst_adc.dmachannel); +} + +void tls_adc_clear_irq(int inttype) +{ + int reg; + reg = tls_reg_read32(HR_SD_ADC_CONFIG_REG); + if(ADC_INT_TYPE_ADC == inttype) + { + reg |= CONFIG_ADC_INT; + tls_reg_write32(HR_SD_ADC_CONFIG_REG, reg); + } + else if(ADC_INT_TYPE_ADC_COMP== inttype) + { + reg |= CONFIG_ADC_INT_CMP; + tls_reg_write32(HR_SD_ADC_CONFIG_REG, reg); + } + else if(ADC_INT_TYPE_DMA == inttype) + { + tls_dma_irq_clr(gst_adc.dmachannel, TLS_DMA_IRQ_TRANSFER_DONE); + } +} + +void tls_adc_irq_register(int inttype, void (*callback)(u16 *buf, u16 len)) +{ + if(ADC_INT_TYPE_ADC == inttype) + { + gst_adc.adc_cb = callback; + } + else if(ADC_INT_TYPE_DMA == inttype) + { + gst_adc.adc_dma_cb = callback; + } + else if(ADC_INT_TYPE_ADC_COMP == inttype) + { + gst_adc.adc_bigger_cb = callback; + } +} + +u16 tls_read_adc_result(void) +{ + u32 value; + u16 ret; + + value = tls_reg_read32(HR_SD_ADC_RESULT_REG); + ret = value&0x3fff; + + return ret; +} + +void tls_adc_start_with_cpu(int Channel) +{ + u32 value; + + Channel &= CONFIG_ADC_CHL_MASK; + + /* Stop adc first */ + value = tls_reg_read32(HR_SD_ADC_CONFIG_REG); + value &= ~CONFIG_ADC_DMA_MASK; + value &= ~CONFIG_ADC_START; + value |= Channel; + + tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); + + value = tls_reg_read32(HR_SD_ADC_CONFIG_REG); + value |= CONFIG_ADC_START; + value |= CONFIG_ADC_INT_MASK; + if(Channel < 8) + { + value |= CONFIG_ADC_G_CTRL12; + value &= ~ CONFIG_ADC_VCM(0x3F); + value |= CONFIG_ADC_VCM(0x1F); + } + tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); +} + + +void tls_adc_enable_calibration_buffer_offset(void) +{ + u32 value; + + /* Stop adc first */ + value = tls_reg_read32(HR_SD_ADC_CONFIG_REG); + value &= ~CONFIG_ADC_DMA_MASK; + value &= ~CONFIG_ADC_START; + tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); + + value = tls_reg_read32(HR_SD_ADC_CONFIG_REG); + value |= CONFIG_ADC_CHL_OFFSET; + value |= CONFIG_ADC_START; + value |= CONFIG_ADC_INT_MASK; + value |= CONFIG_ADC_EN_CAL; + value |= CONFIG_ADC_G_CTRL12; + tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); +} + +void tls_adc_temp_offset_with_cpu(u8 calTemp12) +{ + u32 value; + + value = tls_reg_read32(HR_SD_ADC_CONFIG_REG); + value &= ~CONFIG_ADC_DMA_MASK; + value &= ~CONFIG_ADC_START; + + tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); + + value = tls_reg_read32(HR_SD_ADC_CONFIG_REG); + value |= CONFIG_ADC_CHL_TEMP; + value |= CONFIG_ADC_START; + value |= CONFIG_ADC_INT_MASK; + if(calTemp12) + { + value |= CONFIG_ADC_CAL_OFFSET_TEMP12; + } + else + { + value &= ~CONFIG_ADC_CAL_OFFSET_TEMP12; + } + value &= ~CONFIG_ADC_G_CTRL12; + value |= CONFIG_ADC_TEMP_ON; + value |= CONFIG_ADC_G_TEMP12(3); + tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); /*start adc*/ +} + +void tls_adc_voltage_start_with_cpu(void) +{ + u32 value; + + value = tls_reg_read32(HR_SD_ADC_CONFIG_REG); + value &= ~CONFIG_ADC_DMA_MASK; + value &= ~CONFIG_ADC_START; + tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); + + value = tls_reg_read32(HR_SD_ADC_CONFIG_REG); + value |= CONFIG_ADC_CHL_VOLT; + value |= CONFIG_ADC_START; + value |= CONFIG_ADC_INT_MASK; + value |= CONFIG_ADC_G_CTRL12; + tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); /*start adc*/ +} + +void tls_adc_start_with_dma(int Channel, int Length) +{ + u32 value; + int len; + + if(Channel < 0 || Channel > 11) + return; + + if(Length > ADC_DEST_BUFFER_SIZE) + len = ADC_DEST_BUFFER_SIZE; + else + len = Length; + + gst_adc.valuelen = len; + + Channel &= CONFIG_ADC_CHL_MASK; + + value = tls_reg_read32(HR_SD_ADC_CONFIG_REG); + value &= ~CONFIG_ADC_START; //stop + tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); + + /* Stop dma if necessary */ + while(DMA_CHNLCTRL_REG(gst_adc.dmachannel) & 1) + { + DMA_CHNLCTRL_REG(gst_adc.dmachannel) = 2; + } + + DMA_SRCADDR_REG(gst_adc.dmachannel) = HR_SD_ADC_RESULT_REG; + DMA_DESTADDR_REG(gst_adc.dmachannel) = ADC_DEST_BUFFER_DMA; + /* Hard, Normal, adc_req */ + value = tls_reg_read32(HR_SD_ADC_CONFIG_REG); + if (Channel == 8){ + DMA_MODE_REG(gst_adc.dmachannel) = (0x01 | (0+6)<<2); + value |= (0x1 << 11); + } + else if (Channel == 9){ + DMA_MODE_REG(gst_adc.dmachannel) = (0x01 | (2+6)<<2); + value |= (0x1 << 13); + } + else if (Channel == 10){ + DMA_MODE_REG(gst_adc.dmachannel) = (0x01 | (4+6)<<2); + value |= (0x1 << 15); + } + else if (Channel == 11){ + DMA_MODE_REG(gst_adc.dmachannel) = (0x01 | (6+6)<<2); + value |= (0x1 << 17); + } + else{ + DMA_MODE_REG(gst_adc.dmachannel) = (0x01 | (Channel+6)<<2); + value |= (0x1 << (11 + Channel)); + } + tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); + /* Dest_add_inc, halfword, */ + DMA_CTRL_REG(gst_adc.dmachannel) = (1<<3)|(1<<5)|((len*2)<<8); + DMA_INTMASK_REG &= ~(0x01 << (gst_adc.dmachannel *2 + 1)); + DMA_CHNLCTRL_REG(gst_adc.dmachannel) = 1; /* Enable dma */ + + value = tls_reg_read32(HR_SD_ADC_CONFIG_REG); + value |= CONFIG_ADC_START; + value |= Channel; + if(Channel < 8) + { + value |= CONFIG_ADC_G_CTRL12; + value &= ~ CONFIG_ADC_VCM(0x3F); + value |= CONFIG_ADC_VCM(0x1F); + } +// printf("config value==%x\n", value); + tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); /*start adc*/ +} + +void tls_adc_stop(int ifusedma) +{ + u32 value; + + value = tls_reg_read32(HR_SD_ADC_CONFIG_REG); + value &= ~CONFIG_ADC_START; + tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); + + if(ifusedma) + tls_dma_free(gst_adc.dmachannel); +} + +void tls_adc_config_cmp_reg(int cmp_data, int cmp_pol) +{ + u32 value; + + cmp_data &= 0x3FFF; + value = tls_reg_read32(HR_SD_ADC_RESULT_REG); + value &= ~(0x3FFF<<14); + value |= (cmp_data<<14); + tls_reg_write32(HR_SD_ADC_RESULT_REG, value); + + value = tls_reg_read32(HR_SD_ADC_CONFIG_REG); + value |= CONFIG_ADC_CMP_INT_MASK; + if(cmp_pol) + { + value |= CONFIG_ADC_CMP_POL; + } + else + { + value &= ~CONFIG_ADC_CMP_POL; + } + tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); +} + +void tls_adc_cmp_start(int Channel, int cmp_data, int cmp_pol) +{ + u32 value; + + Channel &= CONFIG_ADC_CHL_MASK; + + /* Stop adc first */ + value = tls_reg_read32(HR_SD_ADC_CONFIG_REG); + value &= ~CONFIG_ADC_DMA_MASK; + value &= ~CONFIG_ADC_START; + value |= Channel; + tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); + + tls_adc_config_cmp_reg(cmp_data, cmp_pol); + + value = tls_reg_read32(HR_SD_ADC_CONFIG_REG); + value |= CONFIG_ADC_START; + if(Channel < 8) + { + value |= CONFIG_ADC_G_CTRL12; + value &= ~ CONFIG_ADC_VCM(0x3F); + value |= CONFIG_ADC_VCM(0x1F); + } + tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); /*start adc*/ +} + + +void tls_adc_reference_sel(int ref) +{ + u32 value; + + value = tls_reg_read32(HR_SD_ADC_CONFIG_REG); + if(ADC_REFERENCE_EXTERNAL == ref) + { + value &= ~CONFIG_ADC_REF_SEL; + value |= CONFIG_ADC_BUF_BYPASS; + } + else if(ADC_REFERENCE_INTERNAL == ref) + { + value |= CONFIG_ADC_REF_SEL; + value &= ~CONFIG_ADC_BUF_BYPASS; + } + tls_reg_write32(HR_SD_ADC_CONFIG_REG, value); +} + +void tls_adc_set_clk(int div) +{ + u32 value; + + value = tls_reg_read32(HR_CLK_DIV_CTL); + value &= ~(0xffff<<12); + value |= (div << 12); + value |= ((u32)0x1<<31); + tls_reg_write32(HR_CLK_DIV_CTL, value); +} + +void signedToUnsignedData(u16 *adcValue, u16 *offset) +{ +// s16 temp = 0; + if(*adcValue >= 8192) + { + *adcValue -= 8192; + } + else + { + *adcValue += 8192; + } + +/* if (*offset >=8192) + { + temp =((*offset-1)&0x1FFF) - 8192; + }else{ + temp = *offset; + } + + *adcValue -= temp; +*/ +} + +static void waitForAdcDone(void) +{ + while(1) + { + if(adc_irq_flag) //ADC涓柇 + { + adc_irq_flag = 0; + break; + } + } +} + +u16 adc_get_offset(void) +{ + tls_adc_init(0, 0); + tls_adc_reference_sel(ADC_REFERENCE_INTERNAL); + adc_irq_flag = 0; + tls_adc_enable_calibration_buffer_offset(); //浣胯兘鏍″噯鍔熻兘 + waitForAdcDone(); + adc_offset = tls_read_adc_result(); //鑾峰彇adc杞崲缁撴灉 + tls_adc_stop(0); + + //printf("\r\noffset:%d", adc_offset); + return adc_offset; +} + +u32 adc_get_interTemp(void) +{ + u16 code2, code1, realCode; + u32 tem; + + tls_adc_init(0, 0); + tls_adc_reference_sel(ADC_REFERENCE_INTERNAL); + adc_irq_flag = 0; + tls_adc_temp_offset_with_cpu(1); //code2 + waitForAdcDone(); + code2 = tls_read_adc_result(); + tls_adc_stop(0); + signedToUnsignedData(&code2, &adc_offset); + + adc_irq_flag = 0; + tls_adc_temp_offset_with_cpu(0); //code1 + waitForAdcDone(); + code1 = tls_read_adc_result(); + tls_adc_stop(0); + signedToUnsignedData(&code1, &adc_offset); + + realCode = ( (code1-code2)/2+8192 ); + //printf("\r\nTEMP:%.1f", realCode*0.12376-1294.58); + //return (realCode*0.12376-1294.58); + tem = realCode*124-1294580; + return tem; +} + +u16 adc_get_inputVolt(u8 channel) +{ + u16 average = 0; + + /*calibration*/ + adc_get_offset(); + /*get value*/ + tls_adc_init(0, 0); + tls_adc_reference_sel(ADC_REFERENCE_INTERNAL); + adc_irq_flag = 0; + tls_adc_start_with_cpu(channel); + waitForAdcDone(); + average = tls_read_adc_result(); + tls_adc_stop(0); + + signedToUnsignedData(&average, &adc_offset); + + //printf("ch[%d]inputVolt:%.3f\r\n", channel+1, ((average-8192.0)/8192*2.25/1.2 + 1.584)); + return average; +} + +u16 adc_get_interVolt(void) +{ + u16 voltValue; + + /*calibration*/ + adc_get_offset(); + /*get value*/ + tls_adc_init(0, 0); + tls_adc_reference_sel(ADC_REFERENCE_INTERNAL); + + adc_irq_flag = 0; + tls_adc_voltage_start_with_cpu(); + waitForAdcDone(); + voltValue = tls_read_adc_result(); + tls_adc_stop(0); + + signedToUnsignedData(&voltValue, &adc_offset); + float voltage = ( 1.214 - ((float)voltValue-8192)/8192*2.25/1.2 )*2; + //printf("\r\ninterVolt:%.2f", voltage); + return voltValue; +} + +u32 adc_temp(void) +{ + u32 tem; + adc_get_offset(); + tem = adc_get_interTemp(); + return tem; +} + + + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_cpu.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_cpu.c new file mode 100644 index 00000000..9eb2d5d6 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_cpu.c @@ -0,0 +1,72 @@ +/** + * @file wm_cpu.c + * + * @brief cpu driver module + * + * @author kevin + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#include "wm_debug.h" +#include "wm_regs.h" +#include "wm_irq.h" +#include "wm_cpu.h" +#include "wm_pwm.h" + +/** + * @brief This function is used to set cpu clock + * + * @param[in] clk select cpu clock + * clk == CPU_CLK_80M 80M + * clk == CPU_CLK_40M 40M + * + * @return None + * + * @note None + */ +void tls_sys_clk_set(u32 clk) +{ + u32 RegValue; + u8 wlanDiv, cpuDiv; + + RegValue = tls_reg_read32(HR_CLK_DIV_CTL); + wlanDiv = (RegValue>>4)&0x0F; + RegValue &= 0xFFFFF000; + RegValue |= 0x80000000; + switch(clk) + { + case CPU_CLK_40M: + cpuDiv = 4; + break; + + default: + cpuDiv = 2; + break; + } + RegValue |= ((wlanDiv*4/cpuDiv)<<8) | (wlanDiv<<4) | cpuDiv; + tls_reg_write32(HR_CLK_DIV_CTL, RegValue); + + return; +} + + +/** + * @brief This function is used to get cpu clock + * + * @param[out] *sysclk point to the addr for system clk output + * + * @return None + * + * @note None + */ +void tls_sys_clk_get(tls_sys_clk *sysclk) +{ + u32 value; + value = tls_reg_read32(HR_CLK_DIV_CTL); + sysclk->apbclk = W600_PLL_CLK_MHZ/4/((value>>4)&0x0F); + sysclk->cpuclk = W600_PLL_CLK_MHZ/(value&0x0F); + sysclk->wlanclk = W600_PLL_CLK_MHZ/((value>>4)&0x0F); +} + + + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_dma.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_dma.c new file mode 100644 index 00000000..be821e2e --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_dma.c @@ -0,0 +1,389 @@ +/** + * @file wm_dma.c + * + * @brief DMA Driver Module + * + * @author dave + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#include +#include +#include + + +#include "misc.h" +#include "wm_dma.h" +#include "wm_regs.h" +#include "wm_irq.h" +#include "wm_osal.h" + + +struct tls_dma_channels { + unsigned char channels[8]; /* list of channels */ +}; + +typedef void (*dma_irq_callback)(void *p); + +struct dma_irq_context { + u8 flags; + dma_irq_callback burst_done_pf; + void *burst_done_priv; + dma_irq_callback transfer_done_pf; + void *transfer_done_priv; +}; + +static struct dma_irq_context dma_context[8]; +static struct tls_dma_channels channels; + +extern void wm_delay_ticks(uint32_t ticks); + +static void dma_irq_proc(void *p) +{ + unsigned char ch; + unsigned int int_src; + + ch = (unsigned char)(unsigned long)p; + int_src = tls_reg_read32(HR_DMA_INT_SRC); + + if (ch > 3) + { + for (ch = 4; ch < 8; ch++) + { + if (int_src & (TLS_DMA_IRQ_BOTH_DONE << ch * 2)) + break; + } + + if (8 == ch) + return; + } + + if ((int_src & (TLS_DMA_IRQ_BOTH_DONE << ch * 2)) && + (TLS_DMA_IRQ_BOTH_DONE == dma_context[ch].flags)) + { + tls_dma_irq_clr(ch, TLS_DMA_IRQ_BOTH_DONE); + if (dma_context[ch].burst_done_pf) + dma_context[ch].burst_done_pf(dma_context[ch].burst_done_priv); + } + else if ((int_src & (TLS_DMA_IRQ_BURST_DONE << ch * 2)) && + (TLS_DMA_IRQ_BURST_DONE == dma_context[ch].flags)) + { + tls_dma_irq_clr(ch, TLS_DMA_IRQ_BOTH_DONE); + if (dma_context[ch].burst_done_pf) + dma_context[ch].burst_done_pf(dma_context[ch].burst_done_priv); + } + else if ((int_src & (TLS_DMA_IRQ_TRANSFER_DONE << ch * 2)) && + (TLS_DMA_IRQ_TRANSFER_DONE == dma_context[ch].flags)) + { + tls_dma_irq_clr(ch, TLS_DMA_IRQ_BOTH_DONE); + if (dma_context[ch].transfer_done_pf) + dma_context[ch].transfer_done_pf(dma_context[ch].transfer_done_priv); + } + return; +} + +void DMA_Channel0_IRQHandler(void) +{ + dma_irq_proc((void *)0); +} +void DMA_Channel1_IRQHandler(void) +{ + dma_irq_proc((void *)1); +} +void DMA_Channel2_IRQHandler(void) +{ + dma_irq_proc((void *)2); +} +void DMA_Channel3_IRQHandler(void) +{ + dma_irq_proc((void *)3); +} +void DMA_Channel4_7_IRQHandler(void) +{ + dma_irq_proc((void *)4); +} + +/** + * @brief This function is used to clear dma interrupt flag. + * + * @param[in] ch Channel no.[0~7] + * @param[in] flags Flags setted to TLS_DMA_IRQ_BURST_DONE, TLS_DMA_IRQ_TRANSFER_DONE, TLS_DMA_IRQ_BOTH_DONE. + * + * @return None + * + * @note None + */ +void tls_dma_irq_clr(unsigned char ch, unsigned char flags) +{ + unsigned int int_src = 0; + + int_src |= flags << 2 * ch; + + tls_reg_write32(HR_DMA_INT_SRC, int_src); + + return; +} + +/** + * @brief This function is used to register dma interrupt callback function. + * + * @param[in] ch Channel no.[0~7] + * @param[in] callback is the dma interrupt call back function. + * @param[in] arg the param of the callback function. + * @param[in] flags Flags setted to TLS_DMA_IRQ_BURST_DONE, TLS_DMA_IRQ_TRANSFER_DONE, TLS_DMA_IRQ_BOTH_DONE. + * + * @return None + * + * @note None + */void tls_dma_irq_register(unsigned char ch, void (*callback)(void *p), void *arg, unsigned char flags) +{ + unsigned int mask; + + mask = tls_reg_read32(HR_DMA_INT_MASK); + mask |= TLS_DMA_IRQ_BOTH_DONE << 2 * ch; + mask &= ~(flags << 2 * ch); + tls_reg_write32(HR_DMA_INT_MASK, mask); + + dma_context[ch].flags = flags; + if (flags & TLS_DMA_IRQ_BURST_DONE) + { + dma_context[ch].burst_done_pf = callback; + dma_context[ch].burst_done_priv = arg; + } + if (flags & TLS_DMA_IRQ_TRANSFER_DONE) + { + dma_context[ch].transfer_done_pf = callback; + dma_context[ch].transfer_done_priv = arg; + } + + if (ch > 3) + ch = 4; + + tls_irq_enable(DMA0_INT + ch); + + return; +} + +/** + * @brief This function is used to Wait until DMA operation completes + * + * @param[in] ch channel no + * + * @retval 0 completed + * @retval -1 failed + * + * @note None + */ +int tls_dma_wait_complt(unsigned char ch) +{ + unsigned long timeout = 0; + + while(DMA_CHNLCTRL_REG(ch) & DMA_CHNL_CTRL_CHNL_ON) + { + tls_os_time_delay(1); + timeout ++; + if(timeout > 500) + return -1; + } + return 0; +} + +/** + * @brief This function is used to Start the DMA controller by Wrap + * + * @param[in] ch channel no + * @param[in] dma_desc pointer to DMA channel descriptor structure + * @param[in] auto_reload does restart when current transfer complete + * @param[in] src_zize dource address size + * @param[in] dest_zize destination address size + * + * @retval 1 success + * @retval 0 failed + * + * @note + * DMA Descriptor: + * +--------------------------------------------------------------+ + * |Vld[31] | RSV | + * +--------------------------------------------------------------+ + * | RSV | Dma_Ctrl[16:0] | + * +--------------------------------------------------------------+ + * | Src_Addr[31:0] | + * +--------------------------------------------------------------+ + * | Dest_Addr[31:0] | + * +--------------------------------------------------------------+ + * | Next_Desc_Add[31:0] | + * +--------------------------------------------------------------+ + */ +unsigned char tls_dma_start_by_wrap(unsigned char ch, struct tls_dma_descriptor *dma_desc, + unsigned char auto_reload, + unsigned short src_zize, + unsigned short dest_zize) +{ + if((ch > 7) && !dma_desc) return 1; + + DMA_SRCWRAPADDR_REG(ch) = dma_desc->src_addr; + DMA_DESTWRAPADDR_REG(ch) = dma_desc->dest_addr; + DMA_WRAPSIZE_REG(ch) = (dest_zize << 16) | src_zize; + DMA_CTRL_REG(ch) = ((dma_desc->dma_ctrl & 0x1ffff) << 1) | (auto_reload ? 0x1: 0x0); + DMA_CHNLCTRL_REG(ch) |= DMA_CHNL_CTRL_CHNL_ON; + + return 0; +} + +/** + * @brief This function is used to Start the DMA controller + * + * @param[in] ch channel no + * @param[in] dma_desc pointer to DMA channel descriptor structure + * @param[in] auto_reload does restart when current transfer complete + * + * @retval 1 success + * @retval 0 failed + * + * @note + * DMA Descriptor: + * +--------------------------------------------------------------+ + * |Vld[31] | RSV | + * +--------------------------------------------------------------+ + * | RSV | Dma_Ctrl[16:0] | + * +--------------------------------------------------------------+ + * | Src_Addr[31:0] | + * +--------------------------------------------------------------+ + * | Dest_Addr[31:0] | + * +--------------------------------------------------------------+ + * | Next_Desc_Add[31:0] | + * +--------------------------------------------------------------+ + */ +unsigned char tls_dma_start(unsigned char ch, struct tls_dma_descriptor *dma_desc, unsigned char auto_reload) +{ + if((ch > 7) && !dma_desc) return 1; + + DMA_SRCADDR_REG(ch) = dma_desc->src_addr; + DMA_DESTADDR_REG(ch) = dma_desc->dest_addr; + DMA_CTRL_REG(ch) = ((dma_desc->dma_ctrl & 0x7fffff) << 1) | (auto_reload ? 0x1: 0x0); + DMA_CHNLCTRL_REG(ch) |= DMA_CHNL_CTRL_CHNL_ON; + + return 0; +} + +/** + * @brief This function is used to To stop current DMA channel transfer + * + * @param[in] ch channel no. to be stopped + * + * @retval 0 success + * @retval 1 failed + * + * @note + * If channel stop, DMA_CHNL_CTRL_CHNL_ON bit in DMA_CHNLCTRL_REG is cleared. + */ +unsigned char tls_dma_stop(unsigned char ch) +{ + if(ch > 7) return 1; + if(DMA_CHNLCTRL_REG(ch) & DMA_CHNL_CTRL_CHNL_ON) + { + DMA_CHNLCTRL_REG(ch) |= DMA_CHNL_CTRL_CHNL_OFF; + + while(DMA_CHNLCTRL_REG(ch) & DMA_CHNL_CTRL_CHNL_ON); + } + + return 0; +} + +/** + * @brief This function is used to Request a free dma channel + * + * @param[in] ch channel no. + * @param[in] flags flags setted to selected channel + * + * @return Channel no. that is free now + * + * @note + * If ch is 0, the function will select a random free channel, + * else return the selected channel no. + */ +unsigned char tls_dma_request(unsigned char ch, unsigned char flags) +{ + + unsigned char freeCh = 0; + int i = 0; + + if (ch == 0) + { + for (i = 0; i < 8; i++) + { + if (!(channels.channels[i] & TLS_DMA_FLAGS_CHANNEL_VALID)) + { + freeCh = i; + break; + } + } + + if (8 == i) + { + printf("!!!there is no free DMA channel.!!!\n"); + freeCh = 0; + } + } + else if ((ch >0) && (ch < 8)) + { + if (!(channels.channels[ch] & TLS_DMA_FLAGS_CHANNEL_VALID)) + { + freeCh = ch; + } + else + { + printf("!!!there is no free DMA channel.!!!\n"); + freeCh = 0; + } + } + + //if(freeCh != 0) + { + channels.channels[freeCh] = flags | TLS_DMA_FLAGS_CHANNEL_VALID; + DMA_MODE_REG(freeCh) = flags; + } + return freeCh; +} + +/** + * @brief This function is used to Free the DMA channel when not use + * + * @param[in] ch channel no. that is ready to free + * + * @return None + * + * @note None + */ +void tls_dma_free(unsigned char ch) +{ + if(ch < 8) + { + tls_dma_stop(ch); + + DMA_SRCADDR_REG(ch) = 0; + DMA_DESTADDR_REG(ch) = 0; + DMA_MODE_REG(ch) = 0; + DMA_CTRL_REG(ch) = 0; +// DMA_INTSRC_REG = 0xffff; + DMA_INTSRC_REG |= 0x03<<(ch*2); + + channels.channels[ch] = 0x00; + } +} + +/** + * @brief This function is used to Initialize DMA Control + * + * @param[in] None + * + * @return None + * + * @note None + */ +void tls_dma_init(void) +{ + DMA_INTMASK_REG = 0xffff; + DMA_INTSRC_REG = 0xffff; +} + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_efuse.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_efuse.c new file mode 100644 index 00000000..b194611a --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_efuse.c @@ -0,0 +1,575 @@ +/************************************************************************** + * File Name : tls_efuse.c + * Author : + * Version : + * Date : + * Description : Use Flash Addr as virtual efuse + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + * All rights reserved. + * + ***************************************************************************/ +#include +#include +#include +#include "wm_debug.h" +#include "wm_regs.h" +#include "wm_efuse.h" +#include "wm_config.h" +#include "list.h" +#include "wm_internal_flash.h" +#include "wm_crypto_hard.h" +#include "wm_timer.h" +#include "wm_cpu.h" +#include "wm_irq.h" +#include "wm_flash_map.h" + +extern void flashSRRW(unsigned long offset,unsigned char *buf,unsigned long sz, unsigned char *backbuf, unsigned int backlen, unsigned int rd); + + +#define FT_MAGICNUM_ADDR (FLASH_BASE_ADDR) +#define MAGICNUM_LEN (4) +#define FT_CHECKSUM_ADDR (FT_MAGICNUM_ADDR + MAGICNUM_LEN) +#define CHECKSUM_LEN (4) +#define FT_DATALEN_ADDR (FT_CHECKSUM_ADDR + CHECKSUM_LEN) +#define FT_DATALEN_LEN (4) +#define FT_MAC_ADDR (FT_DATALEN_ADDR + FT_DATALEN_LEN) +#define MAC_ADDR_LEN (8) +#define FT_TX_DC_OFFSET_ADDR (FT_MAC_ADDR + MAC_ADDR_LEN) +#define TX_DC_OFFSET_LEN (4) +#define FT_RX_DC_OFFSET_ADDR (FT_TX_DC_OFFSET_ADDR + TX_DC_OFFSET_LEN) +#define RX_DC_OFFSET_LEN (4) +#define FT_TX_IQ_GAIN_ADDR (FT_RX_DC_OFFSET_ADDR + RX_DC_OFFSET_LEN) +#define TX_IQ_GAIN_LEN (4) +#define FT_RX_IQ_GAIN_ADDR (FT_TX_IQ_GAIN_ADDR + TX_IQ_GAIN_LEN) +#define RX_IQ_GAIN_LEN (4) +#define FT_TX_IQ_PHASE_ADDR (FT_RX_IQ_GAIN_ADDR + RX_IQ_GAIN_LEN) +#define TX_IQ_PHASE_LEN (4) +#define FT_RX_IQ_PHASE_ADDR (FT_TX_IQ_PHASE_ADDR + TX_IQ_PHASE_LEN) +#define RX_IQ_PHASE_LEN (4) +#define FT_GAIN_ADDR (FT_RX_IQ_PHASE_ADDR + RX_IQ_PHASE_LEN) +#define FT_GAIN_LEN (84) +#define FT_FIX_DATA_LEN (MAC_ADDR_LEN + TX_DC_OFFSET_LEN + RX_DC_OFFSET_LEN + TX_IQ_GAIN_LEN + RX_IQ_GAIN_LEN \ + + TX_IQ_PHASE_LEN \ + + RX_IQ_PHASE_LEN) + + +/* key paramater area -- begin -- */ +/** PHY parameter area **/ +#define PHY_BASE_ADDR (FLASH_BASE_ADDR) +#define PHY_AREA_LEN (0x1000) + +/** QFlash parameter area **/ +#define QFLASH_BASE_ADDR (PHY_BASE_ADDR + PHY_AREA_LEN) +#define QFLASH_AREA_LEN (0x1000) +#define QFLASH_HDR_BASE_ADDR (QFLASH_BASE_ADDR) +#define QFLASH_HDR_LEN (12) +#define QFLASH_Sec_Level_BASE_ADDR (QFLASH_HDR_BASE_ADDR + QFLASH_HDR_LEN) +#define QFLASH_Sec_Level_LEN (4) +#define QFLASH_CHIP_ID_BASE_ADDR (QFLASH_Sec_Level_BASE_ADDR + QFLASH_Sec_Level_LEN) +#define QFLASH_CHIP_ID_LEN (16) + +/* key parameter area -- end -- */ + +typedef struct FT_PARAM +{ + unsigned int magic_no; + unsigned int checksum; + unsigned int data_len; + unsigned char mac_addr[MAC_ADDR_LEN]; + unsigned int tx_dcoffset; + unsigned int rx_dcoffset; + unsigned int tx_iq_gain; + unsigned int rx_iq_gain; + unsigned int tx_iq_phase; + unsigned int rx_iq_phase; + unsigned char tx_gain[FT_GAIN_LEN]; +}FT_PARAM_ST; + +static u8 default_mac[6] = {0x00,0x25,0x08,0x09,0x01,0x0F}; + +FT_PARAM_ST gftParam; +int tls_ft_param_init(void) +{ + int i = 0; + int usedcnt[2] = {0, 0}; + u32 crcvalue = 0; + psCrcContext_t ctx; + u8 *pmem = NULL; + FT_PARAM_ST *pft = NULL; + + if (gftParam.magic_no == SIGNATURE_WORD) + { + return TRUE; + } + + pmem = tls_mem_alloc(512); + if (pmem == NULL) + { + return FALSE; + } + + pft = tls_mem_alloc(sizeof(FT_PARAM_ST)); + if (pft == NULL) + { + return FALSE; + } + + + for (i = 0; i < 2; i++) + { + if (i == 0) + { + tls_fls_read(FT_MAGICNUM_ADDR, (unsigned char *)pft, sizeof(FT_PARAM_ST)); + }else{ + flashSRRW(0, (unsigned char *)pft, sizeof(FT_PARAM_ST), pmem, 512, 1); + } + if (pft->magic_no == SIGNATURE_WORD) + { + tls_crypto_init(); + tls_crypto_crc_init(&ctx, 0xFFFFFFFF, CRYPTO_CRC_TYPE_32, INPUT_REFLECT | OUTPUT_REFLECT); + tls_crypto_crc_update(&ctx, (unsigned char *)pft + 12, sizeof(FT_PARAM_ST) - 12); + tls_crypto_crc_final(&ctx, &crcvalue); + if ((pft->checksum != crcvalue)) + { + usedcnt[i] = -1; + continue; + } + + if (gftParam.magic_no != SIGNATURE_WORD) + { + memcpy(&gftParam, pft, sizeof(FT_PARAM_ST)); + } + }else{ + usedcnt[i] = -1; + } + } + + if ((usedcnt[0] + usedcnt[1]) == -2) + { + /*Use default ft param*/ + } + else if (usedcnt[0] < 0) /*flash param destroyed*/ + { + tls_flash_unlock(); + tls_fls_write(FT_MAGICNUM_ADDR, (unsigned char *)&gftParam, sizeof(gftParam)); + tls_flash_lock(); + } + else if (usedcnt[1] < 0) /*SR param destroyed*/ + { + flashSRRW(0, (unsigned char *)&gftParam, sizeof(FT_PARAM_ST), pmem, 512, 0); + } + else + { + if (gftParam.checksum != pft->checksum) + { + flashSRRW(0, (unsigned char *)&gftParam, sizeof(FT_PARAM_ST), pmem, 512, 0); + } + } + + tls_mem_free(pmem); + tls_mem_free(pft); + + return TRUE; +} + +int tls_ft_param_get(unsigned int opnum, void *data, unsigned int rdlen) +{ + //FT_PARAM_ST ft; + + //tls_fls_read(FT_MAGICNUM_ADDR, (unsigned char *)&ft, sizeof(ft)); + switch (opnum) + { + case CMD_MAC: /*MAC*/ + if ((gftParam.mac_addr[0]&0x1) + ||(0 == (gftParam.mac_addr[0]|gftParam.mac_addr[1]|gftParam.mac_addr[2]|gftParam.mac_addr[3]|gftParam.mac_addr[4]|gftParam.mac_addr[5]))) + { + memcpy(data, default_mac, rdlen); + } + else + { + memcpy(data, gftParam.mac_addr, rdlen); + } + break; + + case CMD_TX_DC: /*tx_dcoffset*/ + *(unsigned int *)data = gftParam.tx_dcoffset; + break; + + case CMD_RX_DC: /*rx_dcoffset*/ + *(unsigned int *)data = gftParam.rx_dcoffset; + break; + + case CMD_TX_IQ_GAIN: + *(unsigned int *)data = gftParam.tx_iq_gain; + break; + + case CMD_RX_IQ_GAIN: + *(unsigned int *)data = gftParam.rx_iq_gain; + break; + + case CMD_TX_IQ_PHASE: + *(unsigned int *)data = gftParam.tx_iq_phase; + break; + + case CMD_RX_IQ_PHASE: + *(unsigned int *)data = gftParam.rx_iq_phase; + break; + + case CMD_TX_GAIN: /*gain*/ + if (rdlen < FT_GAIN_LEN) + { + memcpy(data, gftParam.tx_gain, rdlen); + } + else + { + memcpy(data, gftParam.tx_gain, FT_GAIN_LEN); + } + break; + + default: + return -1; + } + return 0; +} + +int tls_ft_param_set(unsigned int opnum, void *data, unsigned int len) +{ + psCrcContext_t ctx; + unsigned int writelen = 0; + u8 *pmem = NULL; + + + + if (!data || !len) + { + return -1; + } + //tls_fls_read(FT_MAGICNUM_ADDR, (unsigned char *)&gftParam, sizeof(gftParam)); + switch (opnum) + { + case CMD_MAC: /*MAC*/ + memcpy(gftParam.mac_addr, (unsigned char *)data, len); + break; + + case CMD_TX_DC: /*tx_dcoffset*/ + gftParam.tx_dcoffset = *(unsigned int *)data; + break; + + case CMD_RX_DC: /*rx_dcoffset*/ + gftParam.rx_dcoffset = *(unsigned int *)data; + break; + + case CMD_TX_IQ_GAIN: + gftParam.tx_iq_gain = *(unsigned int *)data; + break; + + case CMD_RX_IQ_GAIN: + gftParam.rx_iq_gain = *(unsigned int *) data; + break; + + case CMD_TX_IQ_PHASE: + gftParam.tx_iq_phase = *(unsigned int *)data; + break; + + case CMD_RX_IQ_PHASE: + gftParam.rx_iq_phase = *(unsigned int *) data; + break; + + case CMD_TX_GAIN: /*gain*/ + if (len >= FT_GAIN_LEN) + { + writelen = FT_GAIN_LEN; + } + else + { + writelen = len; + } + memcpy(gftParam.tx_gain, data, writelen); + break; + + default: + return -1; + } + + tls_crypto_init(); + tls_crypto_crc_init(&ctx, 0xFFFFFFFF, CRYPTO_CRC_TYPE_32, INPUT_REFLECT | OUTPUT_REFLECT); + gftParam.magic_no = SIGNATURE_WORD; + tls_crypto_crc_update(&ctx, (unsigned char *)&gftParam + 12, sizeof(gftParam) -12); + tls_crypto_crc_final(&ctx, &gftParam.checksum); + tls_flash_unlock(); + tls_fls_write(FT_MAGICNUM_ADDR, (unsigned char *)&gftParam, sizeof(gftParam)); + tls_flash_lock(); + pmem = tls_mem_alloc(512); + if (pmem) + { + flashSRRW(0, (unsigned char *)&gftParam, sizeof(gftParam), pmem, 512, 0); + tls_mem_free(pmem); + } + return 0; +} + + +/********************************************************************************************************** +* Description: This function is used to get mac addr. +* +* Arguments : mac mac addr,6 byte +* +* Returns : TLS_EFUSE_STATUS_OK get success +* TLS_EFUSE_STATUS_EIO get failed +**********************************************************************************************************/ +int tls_get_mac_addr(u8 *mac) +{ + return tls_ft_param_get(CMD_MAC, mac, 6); +} + +/********************************************************************************************************** +* Description: This function is used to set mac addr. +* +* Arguments : mac mac addr,6 byte +* +* Returns : TLS_EFUSE_STATUS_OK get success +* TLS_EFUSE_STATUS_EIO get failed +**********************************************************************************************************/ +int tls_set_mac_addr(u8 *mac) +{ + return tls_ft_param_set(CMD_MAC, mac, 6); +} + + +/********************************************************************************************************** +* Description: This function is used to get tx lod. +* +* Arguments : *txlo +* +* Returns : TLS_EFUSE_STATUS_OK get success +* TLS_EFUSE_STATUS_EIO get failed +**********************************************************************************************************/ +int tls_get_tx_lo(u8 *txlo) +{ + return tls_ft_param_get(CMD_TX_DC, txlo, 4); +} + +/********************************************************************************************************** +* Description: This function is used to set tx lo. +* +* Arguments : txlo +* +* Returns : TLS_EFUSE_STATUS_OK set success +* TLS_EFUSE_STATUS_EIO set failed +**********************************************************************************************************/ +int tls_set_tx_lo(u8 *txlo) +{ + return tls_ft_param_set(CMD_TX_DC, txlo, 4); +} + +/********************************************************************************************************** +* Description: This function is used to get tx iq gain. +* +* Arguments : txGain +* +* Returns : TLS_EFUSE_STATUS_OK set success +* TLS_EFUSE_STATUS_EIO set failed +**********************************************************************************************************/ +int tls_get_tx_iq_gain(u8 *txGain) +{ + return tls_ft_param_get(CMD_TX_IQ_GAIN, txGain, 4); +} + +/********************************************************************************************************** +* Description: This function is used to set tx iq gain. +* +* Arguments : txGain +* +* Returns : TLS_EFUSE_STATUS_OK set success +* TLS_EFUSE_STATUS_EIO set failed +**********************************************************************************************************/ +int tls_set_tx_iq_gain(u8 *txGain) +{ + return tls_ft_param_set(CMD_TX_IQ_GAIN, txGain, 4); +} + +/********************************************************************************************************** +* Description: This function is used to get rx iq gain. +* +* Arguments : rxGain +* +* Returns : TLS_EFUSE_STATUS_OK set success +* TLS_EFUSE_STATUS_EIO set failed +**********************************************************************************************************/ +int tls_get_rx_iq_gain(u8 *rxGain) +{ + return tls_ft_param_get(CMD_RX_IQ_GAIN, rxGain, 4); +} + +/********************************************************************************************************** +* Description: This function is used to set rx iq gain. +* +* Arguments : rxGain +* +* Returns : TLS_EFUSE_STATUS_OK set success +* TLS_EFUSE_STATUS_EIO set failed +**********************************************************************************************************/ +int tls_set_rx_iq_gain(u8 *rxGain) +{ + return tls_ft_param_set(CMD_RX_IQ_GAIN, rxGain, 4); +} + +/********************************************************************************************************** +* Description: This function is used to get tx iq phase. +* +* Arguments : txPhase +* +* Returns : TLS_EFUSE_STATUS_OK set success +* TLS_EFUSE_STATUS_EIO set failed +**********************************************************************************************************/ +int tls_get_tx_iq_phase(u8 *txPhase) +{ + return tls_ft_param_get(CMD_TX_IQ_PHASE, txPhase, 4); +} + +/********************************************************************************************************** +* Description: This function is used to set tx iq phase. +* +* Arguments : txPhase +* +* Returns : TLS_EFUSE_STATUS_OK set success +* TLS_EFUSE_STATUS_EIO set failed +**********************************************************************************************************/ +int tls_set_tx_iq_phase(u8 *txPhase) +{ + return tls_ft_param_set(CMD_TX_IQ_PHASE, txPhase, 4); +} + +/********************************************************************************************************** +* Description: This function is used to get rx iq phase. +* +* Arguments : rxPhase +* +* Returns : TLS_EFUSE_STATUS_OK set success +* TLS_EFUSE_STATUS_EIO set failed +**********************************************************************************************************/ +int tls_get_rx_iq_phase(u8 *rxPhase) +{ + return tls_ft_param_get(CMD_RX_IQ_PHASE, rxPhase, 4); +} + +/********************************************************************************************************** +* Description: This function is used to set tx iq phase. +* +* Arguments : rxPhase +* +* Returns : TLS_EFUSE_STATUS_OK set success +* TLS_EFUSE_STATUS_EIO set failed +**********************************************************************************************************/ +int tls_set_rx_iq_phase(u8 *rxPhase) +{ + return tls_ft_param_set(CMD_RX_IQ_PHASE, rxPhase, 4); +} + + +int tls_freq_err_op(u8 *freqerr, u8 flag) +{ + tls_flash_unlock(); + if (flag){ + tls_fls_write(FT_MAGICNUM_ADDR + sizeof(FT_PARAM_ST), freqerr, 4); + } + else + { + tls_fls_read(FT_MAGICNUM_ADDR + sizeof(FT_PARAM_ST), freqerr, 4); + } + tls_flash_lock(); + return TLS_EFUSE_STATUS_OK; +} + +int tls_rf_vcg_ctrl_op(u8 *vcg, u8 flag) +{ + tls_flash_unlock(); + if (flag){ + tls_fls_write(VCG_ADDR, vcg, VCG_LEN); + } + else + { + tls_fls_read(VCG_ADDR, vcg, VCG_LEN); + } + tls_flash_lock(); + return TLS_EFUSE_STATUS_OK; +} + +/********************************************************************************************************** +* Description: This function is used to get tx gain. +* +* Arguments : txgain tx gain +* +* Returns : TLS_EFUSE_STATUS_OK get success +* TLS_EFUSE_STATUS_EIO get failed +**********************************************************************************************************/ +int tls_get_tx_gain(u8 *txgain) +{ + + tls_ft_param_get(CMD_TX_GAIN, txgain, TX_GAIN_LEN); + + return TLS_EFUSE_STATUS_OK; +} + +/********************************************************************************************************** +* Description: This function is used to set tx gain. +* +* Arguments : txgain tx gain +* +* Returns : TLS_EFUSE_STATUS_OK set success +* TLS_EFUSE_STATUS_EIO set failed +**********************************************************************************************************/ +int tls_set_tx_gain(u8 *txgain) +{ + + tls_ft_param_set(CMD_TX_GAIN, txgain, TX_GAIN_LEN); + + return TLS_EFUSE_STATUS_OK; +} + +#define FF_n16 0xff, 0xff, 0xff, 0xff, \ + 0xff, 0xff, 0xff, 0xff, \ + 0xff, 0xff, 0xff, 0xff, \ + 0xff, 0xff, 0xff, 0xff + +int tls_get_chipid(u8 chip_id[QFLASH_CHIP_ID_LEN]) +{ + int ret = 0; + static u8 _chip_id[QFLASH_CHIP_ID_LEN] = { FF_n16 }; + u8 zero[QFLASH_CHIP_ID_LEN] = { FF_n16 }; + + if (!memcmp(_chip_id, zero, QFLASH_CHIP_ID_LEN)) + { + ret = tls_fls_read(QFLASH_CHIP_ID_BASE_ADDR, _chip_id, QFLASH_CHIP_ID_LEN); + } + if (0 == ret) + { + memcpy(chip_id, _chip_id, QFLASH_CHIP_ID_LEN); + } + return ret; +} + +#undef FF_n16 + +unsigned int tls_sleep(unsigned int seconds) +{ + int ret = 0; + ret = tls_msleep(seconds * 1000); + return ret; +} + + +int tls_msleep(unsigned int msec) +{ + int ret = 0; + ret = tls_delay_via_timer(msec, TIMER_MS_UNIT_FLAG); + return ret; +} + +int tls_usleep(unsigned int /*useconds_t*/ usec) +{ + int ret = 0; + ret = tls_delay_via_timer(usec, TIMER_US_UNIT_FLAG); + return ret; +} diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_fls.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_fls.c new file mode 100644 index 00000000..6a809eda --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_fls.c @@ -0,0 +1,542 @@ +/** + * @file wm_fls.c + * + * @brief flash Driver Module + * + * @author dave + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ +#include +#include +#include + +#include "list.h" +#include "wm_hostspi.h" +#include "wm_flash.h" +#include "wm_dbg.h" +#include "wm_mem.h" +#include "wm_fls_gd25qxx.h" + + +static struct tls_fls *spi_fls = NULL; + +int tls_spifls_read_id(u32 * id) +{ + u32 cmd; + int err; + + cmd = FLS_CMD_READ_DEV_ID; + *id = 0; + + err = tls_spi_read_with_cmd((const u8 *) &cmd, 4, (u8 *) id, 3); + + if (err != TLS_SPI_STATUS_OK) + { + TLS_DBGPRT_ERR("flash read ID fail(%d)!\n", err); + return TLS_FLS_STATUS_EIO; + } + + TLS_DBGPRT_FLASH_INFO("flash ID - 0x%x.\n", *id); + + return TLS_FLS_STATUS_OK; +} + + +/** + * @brief This function is used to read data from the flash. + * + * @param[in] addr is byte offset addr for read from the flash. + * @param[in] buf is user for data buffer of flash read + * @param[in] len is byte length for read. + * + * @retval TLS_FLS_STATUS_OK if read sucsess + * @retval TLS_FLS_STATUS_EIO if read fail + * + * @note None + */ +int tls_spifls_read(u32 addr, u8 * buf, u32 len) +{ + int err; + u32 read_bytes; + struct tls_fls_drv *drv; + + if (spi_fls == NULL) + { + TLS_DBGPRT_ERR("flash driver module not beed installed!\n"); + return TLS_FLS_STATUS_EPERM; + } + + if (spi_fls->current_drv == NULL) + { + TLS_DBGPRT_ERR("the current spi flash driver not installed!\n"); + return TLS_FLS_STATUS_ENODRV; + } + + if ((addr >= spi_fls->current_drv->total_size) || (len == 0) + || (buf == NULL)) + { + return TLS_FLS_STATUS_EINVAL; + } + tls_os_sem_acquire(spi_fls->fls_lock, 0); + drv = spi_fls->current_drv; + read_bytes = + ((addr + len) > drv->total_size) ? (drv->total_size - addr) : len; + + err = TLS_FLS_STATUS_OK; + + err = drv->read(addr, buf, read_bytes); + tls_os_sem_release(spi_fls->fls_lock); + return err; +} + +int tls_spifls_fast_read(u32 addr, u8 * buf, u32 len) +{ + int err; + u32 read_bytes; + struct tls_fls_drv *drv; + + if (spi_fls == NULL) + { + TLS_DBGPRT_ERR("flash driver module not beed installed!\n"); + return TLS_FLS_STATUS_EPERM; + } + + if (spi_fls->current_drv == NULL) + { + TLS_DBGPRT_ERR("the current spi flash driver not installed!\n"); + return TLS_FLS_STATUS_ENODRV; + } + + if ((addr >= spi_fls->current_drv->total_size) || (len == 0) + || (buf == NULL)) + { + return TLS_FLS_STATUS_EINVAL; + } + if ((spi_fls->current_drv->flags & TLS_FLS_FLAG_FAST_READ) != + TLS_FLS_FLAG_FAST_READ) + { + return TLS_FLS_STATUS_ENOSUPPORT; + } + + drv = spi_fls->current_drv; + read_bytes = + ((addr + len) > drv->total_size) ? (drv->total_size - addr) : len; + + err = TLS_FLS_STATUS_OK; + + err = drv->fast_read(addr, buf, read_bytes); + + return err; +} + +int tls_spifls_page_write(u32 page, u8 * buf, u32 page_cnt) +{ + int err; + u32 write_pages; + u32 i; + struct tls_fls_drv *drv; + + if (spi_fls == NULL) + { + TLS_DBGPRT_ERR("flash driver module not beed installed!\n"); + return TLS_FLS_STATUS_EPERM; + } + + if (spi_fls->current_drv == NULL) + { + TLS_DBGPRT_ERR("the current spi flash driver not installed!\n"); + return TLS_FLS_STATUS_ENODRV; + } + + if ((page >= (spi_fls->current_drv->total_size / spi_fls->current_drv->page_size)) + || (page_cnt == 0) || (buf == NULL)) + { + return TLS_FLS_STATUS_EINVAL; + } + + drv = spi_fls->current_drv; + write_pages = ((page + page_cnt) > (drv->total_size / drv->page_size)) ? + ((drv->total_size / drv->page_size) -page) : page_cnt; + + err = TLS_FLS_STATUS_OK; + + for (i = 0; i < write_pages; i++) + { + err = drv->page_write(page + i, buf + i * drv->page_size); + if (err != TLS_FLS_STATUS_OK) + { + TLS_DBGPRT_ERR("flash page write fail(page %d)!\n", (page + i)); + break; + } + } + + return err; +} + +/** + * @brief This function is used to write data to the flash. + * + * @param[in] addr is byte offset addr for write to the flash + * @param[in] buf is the data buffer want to write to flash + * @param[in] len is the byte length want to write + * + * @retval TLS_FLS_STATUS_OK if write flash success + * @retval TLS_FLS_STATUS_EPERM if flash struct point is null + * @retval TLS_FLS_STATUS_ENODRV if flash driver is not installed + * @retval TLS_FLS_STATUS_EINVAL if argument is invalid + * @retval TLS_FLS_STATUS_EIO if io error + * + * @note None + */ +int tls_spifls_write(u32 addr, u8 * buf, u32 len) +{ + u8 *cache; + int err; + u32 sector_addr; + u32 sector_num; + u32 write_bytes; + u32 i; + struct tls_fls_drv *drv; + + if (spi_fls == NULL) + { + TLS_DBGPRT_ERR("flash driver module not beed installed!\n"); + return TLS_FLS_STATUS_EPERM; + } + + if (spi_fls->current_drv == NULL) + { + TLS_DBGPRT_ERR("the current spi flash driver not installed!\n"); + return TLS_FLS_STATUS_ENODRV; + } + + if ((addr >= spi_fls->current_drv->total_size) || (len == 0) + || (buf == NULL)) + { + return TLS_FLS_STATUS_EINVAL; + } + tls_os_sem_acquire(spi_fls->fls_lock, 0); + drv = spi_fls->current_drv; + write_bytes = + ((addr + len) > drv->total_size) ? (drv->total_size - addr) : len; + sector_addr = addr / drv->sector_size; + sector_num = (addr + write_bytes - 1) / drv->sector_size - sector_addr + 1; + + TLS_DBGPRT_FLASH_INFO + ("write to flash: sector address - %d, sectors - %d.\n", sector_addr, + sector_num); + + err = TLS_FLS_STATUS_OK; + + cache = tls_mem_alloc(drv->sector_size); + if (cache == NULL) + { + tls_os_sem_release(spi_fls->fls_lock); + TLS_DBGPRT_ERR("allocate sector cache memory(%dB) fail!\n", + drv->sector_size); + return TLS_FLS_STATUS_ENOMEM; + } + + for (i = 0; i < sector_num; i++) + { + TLS_DBGPRT_FLASH_INFO("firstly, read the sector - %d to cache.\n", + sector_addr + i); + err = drv->read((sector_addr + i) * drv->sector_size, cache, drv->sector_size); + if (err != TLS_FLS_STATUS_OK) + { + tls_os_sem_release(spi_fls->fls_lock); + TLS_DBGPRT_ERR("flash read fail(sector %d)!\n", (sector_addr + i)); + break; + } + + if (1 == sector_num){/*flash write only in one sector*/ + MEMCPY(cache + (addr%drv->sector_size), buf, write_bytes); + buf += write_bytes; + write_bytes = 0; + }else{/*flash write through some sectors*/ + if (0 == i) { + MEMCPY(cache+(addr%drv->sector_size), buf, drv->sector_size - (addr%drv->sector_size)); + buf += drv->sector_size - (addr%drv->sector_size); + write_bytes -= drv->sector_size - (addr%drv->sector_size); + } else if (i == (sector_num - 1)) { + MEMCPY(cache, buf, write_bytes); + buf += write_bytes; + write_bytes = 0; + } else { + MEMCPY(cache, buf, drv->sector_size); + buf += drv->sector_size; + write_bytes -= drv->sector_size; + } + } + + TLS_DBGPRT_FLASH_INFO("second, erase the sector - %d.\n", + sector_addr + i); + err = drv->erase(sector_addr + i); + if (err != TLS_FLS_STATUS_OK) + { + tls_os_sem_release(spi_fls->fls_lock); + TLS_DBGPRT_ERR("flash erase fail(sector %d)!\n", (sector_addr + i)); + break; + } + + TLS_DBGPRT_FLASH_INFO + ("finnaly, write the data in cache to the sector - %d.\n", + sector_addr + i); + err = tls_spifls_page_write((sector_addr +i) * (drv->sector_size / drv->page_size), + cache, drv->sector_size / drv->page_size); + if (err != TLS_FLS_STATUS_OK) + { + tls_os_sem_release(spi_fls->fls_lock); + TLS_DBGPRT_ERR("flash write fail(sector %d)!\n", (sector_addr + i)); + break; + } + } + + tls_mem_free(cache); + tls_os_sem_release(spi_fls->fls_lock); + return err; +} + + +int tls_spifls_erase(u32 sector) +{ + int err; + struct tls_fls_drv *drv; + + if (spi_fls == NULL) + { + TLS_DBGPRT_ERR("flash driver module not beed installed!\n"); + return TLS_FLS_STATUS_EPERM; + } + + if (spi_fls->current_drv == NULL) + { + TLS_DBGPRT_ERR("the current spi flash driver not installed!\n"); + return TLS_FLS_STATUS_ENODRV; + } + + if (sector >= (spi_fls->current_drv->total_size / spi_fls->current_drv->sector_size)) + { + TLS_DBGPRT_ERR("the sector to be erase overflow!\n"); + return TLS_FLS_STATUS_EINVAL; + } + tls_os_sem_acquire(spi_fls->fls_lock, 0); + drv = spi_fls->current_drv; + + err = TLS_FLS_STATUS_OK; + + err = drv->erase(sector); + tls_os_sem_release(spi_fls->fls_lock); + return err; +} + +int tls_spifls_chip_erase(void) +{ + int err; + struct tls_fls_drv *drv; + + if (spi_fls == NULL) + { + TLS_DBGPRT_ERR("flash driver module not beed installed!\n"); + return TLS_FLS_STATUS_EPERM; + } + + if (spi_fls->current_drv == NULL) + { + TLS_DBGPRT_ERR("the current spi flash driver not installed!\n"); + return TLS_FLS_STATUS_ENODRV; + } + + drv = spi_fls->current_drv; + + err = TLS_FLS_STATUS_OK; + + err = drv->chip_erase(); + + return err; +} + +int tls_spifls_get_param(u8 type, void *param) +{ + int err; + struct tls_fls_drv *drv; + + if (spi_fls == NULL) + { + TLS_DBGPRT_ERR("flash driver module not beed installed!\n"); + return TLS_FLS_STATUS_EPERM; + } + + if (spi_fls->current_drv == NULL) + { + TLS_DBGPRT_ERR("the current spi flash driver not installed!\n"); + return TLS_FLS_STATUS_ENODRV; + } + + if (param == NULL) + { + return TLS_FLS_STATUS_EINVAL; + } + tls_os_sem_acquire(spi_fls->fls_lock, 0); + drv = spi_fls->current_drv; + err = TLS_FLS_STATUS_OK; + switch (type) + { + case TLS_FLS_PARAM_TYPE_ID: + *((u32 *) param) = drv->id; + break; + + case TLS_FLS_PARAM_TYPE_SIZE: + *((u32 *) param) = drv->total_size; + break; + + case TLS_FLS_PARAM_TYPE_PAGE_SIZE: + *((u32 *) param) = drv->page_size; + break; + + case TLS_FLS_PARAM_TYPE_PROG_SIZE: + *((u32 *) param) = drv->program_size; + break; + + case TLS_FLS_PARAM_TYPE_SECTOR_SIZE: + *((u32 *) param) = drv->sector_size; + break; + + default: + TLS_DBGPRT_WARNING("invalid parameter ID!\n"); + err = TLS_FLS_STATUS_EINVAL; + break; + } + tls_os_sem_release(spi_fls->fls_lock); + return err; +} + +int tls_spifls_drv_register(struct tls_fls_drv *fls_drv) +{ + u32 cpu_sr; + struct tls_fls_drv *drv; + + if (fls_drv == NULL) + { + TLS_DBGPRT_ERR("flash driver module not beed installed!\n"); + return TLS_FLS_STATUS_EINVAL; + } + + dl_list_for_each(drv, &spi_fls->fls_drvs, struct tls_fls_drv, drv_list) + { + if (drv->id == fls_drv->id) + { + TLS_DBGPRT_WARNING + ("corresponding spi flash driver has registered!\n"); + return TLS_FLS_STATUS_EEXIST; + } + } + + cpu_sr = tls_os_set_critical(); + dl_list_add_tail((struct dl_list *) &spi_fls->fls_drvs, + (struct dl_list *) &fls_drv->drv_list); + tls_os_release_critical(cpu_sr); + + TLS_DBGPRT_FLASH_INFO("the spi flash driver is registered successfully!\n"); + + return TLS_FLS_STATUS_OK; +} + +int tls_spifls_drv_unregister(struct tls_fls_drv *fls_drv) +{ + TLS_DBGPRT_WARNING + ("unregister spi flash driver operation is not supported!\n"); + return TLS_FLS_STATUS_EPERM; +} + +int tls_spifls_probe(void) +{ + int err; + u32 id; + struct tls_fls_drv *drv; + + if (spi_fls == NULL) + { + TLS_DBGPRT_ERR("flash driver module not beed installed!\n"); + return TLS_FLS_STATUS_EPERM; + } + if (spi_fls->current_drv != NULL) + { + TLS_DBGPRT_ERR("the current spi flash has fount the matched driver!\n"); + return TLS_FLS_STATUS_EBUSY; + } + + TLS_DBGPRT_FLASH_INFO("try to read the current spi flash ID.\n"); + err = tls_spifls_read_id(&id); + if (err != TLS_FLS_STATUS_OK) + { + return err; + } + + TLS_DBGPRT_FLASH_INFO("current spi flash ID - 0x%x.\n", id); + + dl_list_for_each(drv, &spi_fls->fls_drvs, struct tls_fls_drv, drv_list) + { + err = drv->probe(id); + if (err != TLS_FLS_STATUS_OK) + { + return err; + } + + tls_spi_setup(drv->mode, drv->cs_active, drv->clock); + + TLS_DBGPRT_FLASH_INFO("matched the spi flash driver.\n"); + spi_fls->current_drv = drv; + break; + } + + if (spi_fls->current_drv == NULL) + { + TLS_DBGPRT_WARNING("not found the matched spi flash driver!\n"); + return TLS_FLS_STATUS_ENODRV; + } + + return TLS_FLS_STATUS_OK; +} + +int tls_spifls_init(void) +{ + struct tls_fls *fls; + int err; + + if (spi_fls != NULL) + { + TLS_DBGPRT_ERR("flash driver module has been installed!\n"); + return TLS_FLS_STATUS_EBUSY; + } + + fls = (struct tls_fls *) tls_mem_alloc(sizeof(struct tls_fls)); + if (fls == NULL) + { + TLS_DBGPRT_ERR("allocate @spi_fls fail!\n"); + return TLS_FLS_STATUS_ENOMEM; + } + + memset(fls, 0, sizeof(*fls)); + dl_list_init((struct dl_list *) &fls->fls_drvs); + err = tls_os_sem_create(&fls->fls_lock, 1); + if (err != TLS_OS_SUCCESS) + { + tls_mem_free(fls); + TLS_DBGPRT_ERR("create semaphore @fls_lock fail!\n"); + return TLS_FLS_STATUS_ENOMEM; + } + spi_fls = fls; + + tls_spifls_drv_install(); + + return TLS_FLS_STATUS_OK; +} + +int tls_spifls_exit(void) +{ + TLS_DBGPRT_FLASH_INFO("Not support flash driver module uninstalled!\n"); + return TLS_FLS_STATUS_EPERM; +} + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_fls_gd25qxx.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_fls_gd25qxx.c new file mode 100644 index 00000000..341b3650 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_fls_gd25qxx.c @@ -0,0 +1,308 @@ +/** + * @file wm_fls_gd25qxx.c + * + * @brief gd25qxx flash Driver Module + * + * @author dave + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ + +#include +#include +#include "wm_type_def.h" +#include "wm_flash.h" +#include "wm_hostspi.h" +#include "wm_fls_gd25qxx.h" +#include "wm_debug.h" +#include "wm_gpio.h" +#include "VS10XX.h" + +static int tls_spifls_drv_read(u32 addr, u8 * buf, u32 len); +static int tls_spifls_drv_fast_read(u32 addr, u8 * buf, u32 len); +static int tls_spifls_drv_page_write(u32 page, u8 * buf); +static int tls_spifls_drv_erase(u32 sector); +static int tls_spifls_drv_chip_erase(void); +static int tls_spifls_drv_probe(u32 id); +static void tls_spifls_drv_remove(void); + +static struct tls_fls_drv exspi_fls = { + .drv_list = {NULL, NULL}, + .clock = SPI_SCLK, + .mode = TLS_SPI_MODE_0, + .cs_active = TLS_SPI_CS_LOW, + .flags = 0, + .read = tls_spifls_drv_read, + .fast_read = tls_spifls_drv_fast_read, + .page_write = tls_spifls_drv_page_write, + .erase = tls_spifls_drv_erase, + .chip_erase = tls_spifls_drv_chip_erase, + .probe = tls_spifls_drv_probe, + .remove = tls_spifls_drv_remove +}; + +static struct tls_fls_drv *exspifls_drv = NULL; + + +static unsigned int swap32(unsigned int v) +{ + return ((v & 0xff) << 24) | ((v & 0xff00) << 8) | + ((v & 0xff0000) >> 8) | (v >> 24); +} + +static int tls_spifls_drv_write_enable(void) +{ + u8 cmd; + int err; + + cmd = EXSPIFLASH_WRITE_ENABLE; + + err = tls_spi_write((const u8 *) &cmd, 1); + if (err != TLS_SPI_STATUS_OK) + { + return TLS_FLS_STATUS_EIO; + } + + return TLS_FLS_STATUS_OK; +} + +static int tls_spifls_drv_wait_write_enable(void) +{ + u8 cmd; + u8 sr; + int err; + + cmd = EXSPIFLASH_READ_SR1; + sr = 0; + do + { + err = tls_spi_read_with_cmd((const u8 *) &cmd, 1, &sr, 1); + if (err != TLS_SPI_STATUS_OK) + { + return TLS_FLS_STATUS_EIO; + } + + if (sr & FLASH_STATUS_WEL) + { + break; + } + } + while (1); + + return TLS_FLS_STATUS_OK; +} + +static int tls_spifls_drv_wait_flash_ready(void) +{ + u8 cmd; + u8 sr; + int err; + + cmd = EXSPIFLASH_READ_SR1; + sr = 0; + do + { + err = tls_spi_read_with_cmd((const u8 *) &cmd, 1, &sr, 1); + if (err != TLS_SPI_STATUS_OK) + { + return TLS_FLS_STATUS_EIO; + } + + if ((sr & FLASH_STATUS_BUSY) == 0x00) + { + break; + } + } + while (1); + + return TLS_FLS_STATUS_OK; +} + +static int tls_spifls_drv_read(u32 addr, u8 * buf, u32 len) +{ + u32 cmd; + int err; + + cmd = 0; + cmd |= EXSPIFLASH_DATA_READ; + cmd |= swap32(addr) & 0xffffff00; + err = tls_spi_read_with_cmd((const u8 *) &cmd, 4, buf, len); + if (err != TLS_SPI_STATUS_OK) + { + return TLS_FLS_STATUS_EIO; + } + + return TLS_FLS_STATUS_OK; +} + +static int tls_spifls_drv_fast_read(u32 addr, u8 * buf, u32 len) +{ + return TLS_FLS_STATUS_ENOSUPPORT; +} + +static int tls_spifls_drv_page_write(u32 page, u8 * buf) +{ + u32 cmd; + int err; + + err = tls_spifls_drv_write_enable(); + if (err != TLS_SPI_STATUS_OK) + { + return TLS_FLS_STATUS_EIO; + } + + err = tls_spifls_drv_wait_write_enable(); + if (err != TLS_SPI_STATUS_OK) + { + return TLS_FLS_STATUS_EIO; + } + + cmd = 0; + cmd |= EXSPIFLASH_PAGE_PROGRAM; + cmd |= swap32(page * exspifls_drv->page_size) & 0xffffff00; + err = tls_spi_write_with_cmd((const u8 *) &cmd, 4, (const u8 *) buf, + exspifls_drv->page_size); + if (err != TLS_SPI_STATUS_OK) + { + return TLS_FLS_STATUS_EIO; + } + + err = tls_spifls_drv_wait_flash_ready(); + if (err != TLS_SPI_STATUS_OK) + { + return TLS_FLS_STATUS_EIO; + } + + return TLS_FLS_STATUS_OK; +} + +static int tls_spifls_drv_erase(u32 sector) +{ + u32 cmd; + int err; + + err = tls_spifls_drv_write_enable(); + if (err != TLS_SPI_STATUS_OK) + { + return TLS_FLS_STATUS_EIO; + } + err = tls_spifls_drv_wait_write_enable(); + if (err != TLS_SPI_STATUS_OK) + { + return TLS_FLS_STATUS_EIO; + } + cmd = 0; + cmd |= EXSPIFLASH_SECTOR_ERASE; + cmd |= swap32(sector * exspifls_drv->sector_size) & 0xffffff00; + err = tls_spi_write((const u8 *) &cmd, 4); + if (err != TLS_SPI_STATUS_OK) + { + return TLS_FLS_STATUS_EIO; + } + tls_os_time_delay(6); + err = tls_spifls_drv_wait_flash_ready(); + if (err != TLS_SPI_STATUS_OK) + { + return TLS_FLS_STATUS_EIO; + } + return TLS_FLS_STATUS_OK; +} + +static int tls_spifls_drv_chip_erase(void) +{ + u8 cmd; + int err; + + err = tls_spifls_drv_write_enable(); + if (err != TLS_SPI_STATUS_OK) + { + return TLS_FLS_STATUS_EIO; + } + + err = tls_spifls_drv_wait_write_enable(); + if (err != TLS_SPI_STATUS_OK) + { + return TLS_FLS_STATUS_EIO; + } + + cmd = EXSPIFLASH_CHIP_ERASE; + err = tls_spi_write((const u8 *) &cmd, 1); + if (err != TLS_SPI_STATUS_OK) + { + return TLS_FLS_STATUS_EIO; + } + + err = tls_spifls_drv_wait_flash_ready(); + if (err != TLS_SPI_STATUS_OK) + { + return TLS_FLS_STATUS_EIO; + } + + return TLS_FLS_STATUS_OK; +} + +static int tls_spifls_drv_probe(u32 id) +{ +// int i = 0; + + + if (!id) + { + return TLS_FLS_STATUS_EINVAL; + } + + exspi_fls.id = id; + if ((id>>16)&0xFF) + { + exspi_fls.total_size = 1 << (id>>16); + }else{ + exspi_fls.total_size = FLASH_TOTAL_SIZE; /*1MByte*/ + } + + exspi_fls.page_size = PAGE_SIZE; + exspi_fls.program_size = PROGRAM_SIZE; + exspi_fls.sector_size = SECTOR_SIZE; + + + exspifls_drv = &exspi_fls; + return TLS_FLS_STATUS_OK; +} + +static void tls_spifls_drv_remove(void) +{ + exspifls_drv = NULL; +} + + +/** + * @brief This function is used to install gd25qxx driver. + * + * @param[in] None + * + * @retval TLS_FLS_STATUS_OK if write flash success + * @retval TLS_FLS_STATUS_EPERM if flash struct point is null + * @retval TLS_FLS_STATUS_ENODRV if flash driver is not installed + * @retval TLS_FLS_STATUS_EINVAL if argument is invalid + * @retval TLS_FLS_STATUS_EIO if io error + * @retval TLS_FLS_STATUS_EEXIST if driver is already existed + * + * @note None + */ +int tls_spifls_drv_install(void) +{ + int err; + extern int tls_spifls_probe(void); + extern int tls_spifls_drv_register(struct tls_fls_drv *fls_drv); + + err = tls_spifls_drv_register((struct tls_fls_drv *) &exspi_fls); + if (err == TLS_FLS_STATUS_EEXIST) + { + return err; + } + TLS_DBGPRT_INFO("register the spi flash driver - %d.\n", err); + + err = tls_spifls_probe(); + TLS_DBGPRT_INFO("probe spi flash - %d.\n", err); + + return err; +} diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_gpio.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_gpio.c new file mode 100644 index 00000000..2d711388 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_gpio.c @@ -0,0 +1,420 @@ +/** + * @file wm_gpio.c + * + * @brief GPIO Driver Module + * + * @author dave + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#include "wm_gpio.h" +#include "wm_regs.h" +#include "wm_irq.h" +//#include "wm_osal.h" +#include "tls_common.h" +#include "stdio.h" + +struct gpio_irq_context{ + tls_gpio_irq_callback callback; + void *arg; +}; + + +static struct gpio_irq_context gpio_context[WM_IO_PB_30 - WM_IO_PA_00 + 1] = {{0,0}}; + + +void GPIOA_IRQHandler(void) +{ + u8 i = 0; + u8 found = 0; + u32 reg = 0; + + reg = tls_reg_read32(HR_GPIO_MIS); + + for (i = 0; i <= WM_IO_PA_15; i++) + { + if (reg & BIT(i)) + { + found = 1; + break; + } + } + + if (found) + { + if (NULL != gpio_context[i].callback) + gpio_context[i].callback(gpio_context[i].arg); + } + return; + +} + +void GPIOB_IRQHandler(void) + { + u8 i = 0; + u8 found = 0; + u32 reg = 0; + + reg = tls_reg_read32(HR_GPIO_MIS + TLS_IO_AB_OFFSET); + + + for (i = WM_IO_PB_00; i <= WM_IO_PB_31; i++) + { + if (reg & BIT(i - WM_IO_PB_00)) + { + found = 1; + break; + } + } + + if (found) + { + if (NULL != gpio_context[i].callback) + gpio_context[i].callback(gpio_context[i].arg); + } + + return; +} + +/** + * @brief This function is used to config gpio function + * + * @param[in] gpio_pin gpio pin num + * @param[in] dir gpio direction + * @param[in] attr gpio attribute + * + * @return None + * + * @note + * From gpio3 to gpio7,attribute can set to WM_GPIO_ATTR_PULLHIGH, + * but can not set to WM_GPIO_ATTR_PULLLOW, + * the default attribute is WM_GPIO_ATTR_PULLHIGH. + * Other gpio can set to WM_GPIO_ATTR_PULLLOW,but can not set to WM_GPIO_ATTR_PULLHIGH,the deault + * attribute is WM_GPIO_ATTR_PULLLOW. + * all gpio can set to WM_GPIO_ATTR_FLOATING + */ +void tls_gpio_cfg(enum tls_io_name gpio_pin, enum tls_gpio_dir dir, enum tls_gpio_attr attr) +{ + u8 pin; + u16 offset; + + if (gpio_pin >= WM_IO_PB_00) + { + pin = gpio_pin - WM_IO_PB_00; + offset = TLS_IO_AB_OFFSET; + } + else + { + pin = gpio_pin; + offset = 0; + } + + /* enable gpio function */ + tls_io_cfg_set(gpio_pin, WM_IO_OPT5_GPIO); + + /* gpio direction */ + if (WM_GPIO_DIR_OUTPUT == dir) + tls_reg_write32(HR_GPIO_DIR + offset, tls_reg_read32(HR_GPIO_DIR + offset) | BIT(pin)); /* 1 set output */ + else if (WM_GPIO_DIR_INPUT == dir) + tls_reg_write32(HR_GPIO_DIR + offset, tls_reg_read32(HR_GPIO_DIR + offset) & (~BIT(pin))); /* 0 set input */ + + /* gpio pull attribute */ + if (WM_GPIO_ATTR_FLOATING == attr) + tls_reg_write32(HR_GPIO_PULL_EN + offset, tls_reg_read32(HR_GPIO_PULL_EN + offset) | BIT(pin)); /* 1 disable pull */ + if ((WM_GPIO_ATTR_PULLHIGH == attr) || (WM_GPIO_ATTR_PULLLOW == attr)) + tls_reg_write32(HR_GPIO_PULL_EN + offset, tls_reg_read32(HR_GPIO_PULL_EN + offset) & (~BIT(pin))); /* 0 enable pull */ +} + +/** + * @brief This function is used to read gpio status + * + * @param[in] gpio_pin gpio pin num + * + * @retval 0 power level is low + * @retval 1 power level is high + * + * @note None + */ +u8 tls_gpio_read(enum tls_io_name gpio_pin) +{ + u32 reg_en; + u32 reg; + u8 pin; + u16 offset; + + if (gpio_pin >= WM_IO_PB_00) + { + pin = gpio_pin - WM_IO_PB_00; + offset = TLS_IO_AB_OFFSET; + } + else + { + pin = gpio_pin; + offset = 0; + } + + reg_en = tls_reg_read32(HR_GPIO_DATA_EN + offset); + tls_reg_write32(HR_GPIO_DATA_EN + offset, reg_en | (1 << pin)); + reg = tls_reg_read32(HR_GPIO_DATA + offset); + tls_reg_write32(HR_GPIO_DATA_EN + offset, reg_en); + if(reg & (0x1 << pin)) + return 1; + else + return 0; +} + +/** + * @brief This function is used to modify gpio status + * + * @param[in] gpio_pin gpio pin num + * @param[in] value power level + * 0: low power level + * 1: high power level + * + * @return None + * + * @note None + */ +void tls_gpio_write(enum tls_io_name gpio_pin, u8 value) +{ +// u32 cpu_sr = 0; + u32 reg; + u32 reg_en; + u8 pin; + u16 offset; + + if (gpio_pin >= WM_IO_PB_00) + { + pin = gpio_pin - WM_IO_PB_00; + offset = TLS_IO_AB_OFFSET; + } + else + { + pin = gpio_pin; + offset = 0; + } + + + //cpu_sr = tls_os_set_critical(); + + reg_en = tls_reg_read32(HR_GPIO_DATA_EN + offset); + tls_reg_write32(HR_GPIO_DATA_EN + offset, reg_en | (1 << pin)); + + reg = tls_reg_read32(HR_GPIO_DATA + offset); + if(value) + tls_reg_write32(HR_GPIO_DATA + offset, reg | (1 << pin)); /* write high */ + else + tls_reg_write32(HR_GPIO_DATA + offset, reg & (~(1 << pin)));/* write low */ + + tls_reg_write32(HR_GPIO_DATA_EN + offset, reg_en); + + //tls_os_release_critical(cpu_sr); +} + +/** + * @brief This function is used to config gpio interrupt + * + * @param[in] gpio_pin gpio pin num + * @param[in] mode interrupt trigger type + * + * @return None + * + * @note None + */ +void tls_gpio_irq_enable(enum tls_io_name gpio_pin, enum tls_gpio_irq_trig mode) +{ + u32 reg; + u8 pin; + u16 offset; + u8 vec_no; + + if (gpio_pin >= WM_IO_PB_00) + { + pin = gpio_pin - WM_IO_PB_00; + offset = TLS_IO_AB_OFFSET; + vec_no = GPIOB_INT; + } + else + { + pin = gpio_pin; + offset = 0; + vec_no = GPIO_INT; + } + +// TLS_DBGPRT_INFO("\r\ntls_gpio_int_enable gpio pin =%d,mode==%d\r\n",gpio_pin,mode); + + switch(mode) + { + case WM_GPIO_IRQ_TRIG_RISING_EDGE: + reg = tls_reg_read32(HR_GPIO_IS + offset); + reg &= (~(0x1 << pin)); + // TLS_DBGPRT_INFO("\r\nrising edge is ret=%x\r\n",reg); + tls_reg_write32(HR_GPIO_IS + offset, reg); /* 0 edge trigger */ + reg = tls_reg_read32(HR_GPIO_IBE + offset); + reg &= (~(0x1 << pin)); + // TLS_DBGPRT_INFO("\r\nrising edge ibe ret=%x\r\n",reg); + tls_reg_write32(HR_GPIO_IBE + offset, reg); /* 0 edge trigger */ + reg = tls_reg_read32(HR_GPIO_IEV + offset); + reg |= (0x1 << pin); + // TLS_DBGPRT_INFO("\r\nrising edge iev ret=%x\r\n",reg); + tls_reg_write32(HR_GPIO_IEV + offset, reg); /* 1 rising edge trigger */ + break; + case WM_GPIO_IRQ_TRIG_FALLING_EDGE: + reg = tls_reg_read32(HR_GPIO_IS + offset); + reg &= (~(0x1 << pin)); + // TLS_DBGPRT_INFO("\falling edge is ret=%x\n",reg); + tls_reg_write32(HR_GPIO_IS + offset, reg); /* 0 edge trigger */ + reg = tls_reg_read32(HR_GPIO_IBE + offset); + reg &= (~(0x1 << pin)); + // TLS_DBGPRT_INFO("\falling edge ibe ret=%x\n",reg); + tls_reg_write32(HR_GPIO_IBE + offset, reg); /* 0 edge trigger */ + reg = tls_reg_read32(HR_GPIO_IEV + offset); + reg &= (~(0x1 << pin)); + // TLS_DBGPRT_INFO("\falling edge iev ret=%x\n",reg); + tls_reg_write32(HR_GPIO_IEV + offset, reg); /* 0 falling edge trigger */ + break; + case WM_GPIO_IRQ_TRIG_DOUBLE_EDGE: + reg = tls_reg_read32(HR_GPIO_IS + offset); + tls_reg_write32(HR_GPIO_IS + offset, reg & (~(0x1 << pin))); /* 0 edge trigger */ + reg = tls_reg_read32(HR_GPIO_IBE + offset); + tls_reg_write32(HR_GPIO_IBE + offset, reg | (0x1 << pin)); /* 1 double edge trigger */ + break; + case WM_GPIO_IRQ_TRIG_HIGH_LEVEL: + reg = tls_reg_read32(HR_GPIO_IS + offset); + tls_reg_write32(HR_GPIO_IS + offset, reg | (0x1 << pin)); /* 1 level trigger */ + reg = tls_reg_read32(HR_GPIO_IEV + offset); + tls_reg_write32(HR_GPIO_IEV + offset, reg | (0x1 << pin)); /* 1 high level trigger */ + break; + case WM_GPIO_IRQ_TRIG_LOW_LEVEL: + reg = tls_reg_read32(HR_GPIO_IS + offset); + tls_reg_write32(HR_GPIO_IS + offset, reg | (0x1 << pin)); /* 1 level trigger */ + reg = tls_reg_read32(HR_GPIO_IEV + offset); + tls_reg_write32(HR_GPIO_IEV + offset, reg & (~(0x1 << pin))); /* 0 low level trigger */ + break; + } + + reg = tls_reg_read32(HR_GPIO_IE + offset); + reg |= (0x1 << pin); +// TLS_DBGPRT_INFO("\nie ret=%x\n",reg); + tls_reg_write32(HR_GPIO_IE + offset, reg); /* enable interrupt */ + + tls_irq_enable(vec_no); +} + +/** + * @brief This function is used to disable gpio interrupt + * + * @param[in] gpio_pin gpio pin num + * + * @return None + * + * @note None + */ +void tls_gpio_irq_disable(enum tls_io_name gpio_pin) +{ + u32 reg; + u8 pin; + u16 offset; + + if (gpio_pin >= WM_IO_PB_00) + { + pin = gpio_pin - WM_IO_PB_00; + offset = TLS_IO_AB_OFFSET; + } + else + { + pin = gpio_pin; + offset = 0; + } + + reg = tls_reg_read32(HR_GPIO_IE + offset); + tls_reg_write32(HR_GPIO_IE + offset, reg & (~(0x1 << pin))); /* disable interrupt */ + tls_irq_disable(GPIO_INT); +} + +/** + * @brief This function is used to get gpio interrupt status + * + * @param[in] gpio_pin gpio pin num + * + * @retval 0 no interrupt happened + * @retval 1 interrupt happened + * + * @note None + */ +u8 tls_get_gpio_irq_status(enum tls_io_name gpio_pin) +{ + u32 reg; + u8 pin; + u16 offset; + + if (gpio_pin >= WM_IO_PB_00) + { + pin = gpio_pin - WM_IO_PB_00; + offset = TLS_IO_AB_OFFSET; + } + else + { + pin = gpio_pin; + offset = 0; + } + + reg = tls_reg_read32(HR_GPIO_RIS + offset); + if(reg & (0x1 << pin)) + return 1; + else + return 0; +} + +/** + * @brief This function is used to clear gpio interrupt flag + * + * @param[in] gpio_pin gpio pin num + * + * @return None + * + * @note None + */ +void tls_clr_gpio_irq_status(enum tls_io_name gpio_pin) +{ + u32 reg; + u8 pin; + u16 offset; + + if (gpio_pin >= WM_IO_PB_00) + { + pin = gpio_pin - WM_IO_PB_00; + offset = TLS_IO_AB_OFFSET; + } + else + { + pin = gpio_pin; + offset = 0; + } + + reg = tls_reg_read32(HR_GPIO_IC + offset); + tls_reg_write32(HR_GPIO_IC + offset, reg | (0x1 << pin)); /* 1 clear interrupt status */ +} + +/** + * @brief This function is used to register gpio interrupt + * + * @param[in] gpio_pin gpio pin num + * @param[in] callback the gpio interrupt call back function + * @param[in] arg parammeter for the callback + * + * @return None + * + * @note + * gpio callback function is called in interrupt, + * so can not operate the critical data in the callback fuuction, + * recommendation to send messages to other tasks to operate it. + */ +void tls_gpio_isr_register(enum tls_io_name gpio_pin, + tls_gpio_irq_callback callback, + void *arg) +{ + gpio_context[gpio_pin].callback = callback; + gpio_context[gpio_pin].arg = arg; +} + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_gpio_afsel.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_gpio_afsel.c new file mode 100644 index 00000000..2526d2fd --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_gpio_afsel.c @@ -0,0 +1,964 @@ +/** + * @file wm_gpio.c + * + * @brief GPIO Driver Module + * + * @author dave + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#include "wm_gpio.h" +#include "wm_regs.h" +#include "wm_irq.h" +//#include "wm_osal.h" +#include "tls_common.h" +#include "wm_gpio_afsel.h" +#include "wm_debug.h" + + +void wm_hspi_gpio_config(uint8_t numsel) +{ + switch(numsel) + { + case 0: + tls_io_cfg_set(WM_IO_PB_14, WM_IO_OPTION1); + tls_io_cfg_set(WM_IO_PB_15, WM_IO_OPTION1); + tls_io_cfg_set(WM_IO_PB_16, WM_IO_OPTION1); + tls_io_cfg_set(WM_IO_PB_17, WM_IO_OPTION1); + tls_io_cfg_set(WM_IO_PB_18, WM_IO_OPTION1); + break; + + case 1: + tls_io_cfg_set(WM_IO_PB_08, WM_IO_OPTION2); + tls_io_cfg_set(WM_IO_PB_09, WM_IO_OPTION2); + tls_io_cfg_set(WM_IO_PB_10, WM_IO_OPTION2); + tls_io_cfg_set(WM_IO_PB_11, WM_IO_OPTION2); + tls_io_cfg_set(WM_IO_PB_12, WM_IO_OPTION2); + break; + + default: + TLS_DBGPRT_ERR("highspeed spi gpio config error!"); + break; + } +} + +void wm_spi_ck_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_01: + tls_io_cfg_set(WM_IO_PA_01, WM_IO_OPTION3); + break; + + case WM_IO_PB_16: + tls_io_cfg_set(WM_IO_PB_16, WM_IO_OPTION3); + break; + + case WM_IO_PB_27: + tls_io_cfg_set(WM_IO_PB_27, WM_IO_OPTION1); + break; + + case WM_IO_PA_11: + tls_io_cfg_set(WM_IO_PA_11, WM_IO_OPTION4); + break; + + default: + TLS_DBGPRT_ERR("spi ck afsel config error!"); + break; + } +} + +void wm_spi_cs_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_02: + tls_io_cfg_set(WM_IO_PA_02, WM_IO_OPTION3); + break; + + case WM_IO_PB_15: + tls_io_cfg_set(WM_IO_PB_15, WM_IO_OPTION3); + break; + + case WM_IO_PB_00: + tls_io_cfg_set(WM_IO_PB_00, WM_IO_OPTION1); + break; + + case WM_IO_PB_07: + tls_io_cfg_set(WM_IO_PB_07, WM_IO_OPTION4); + break; + + case WM_IO_PA_12: + tls_io_cfg_set(WM_IO_PA_12, WM_IO_OPTION4); + break; + + default: + TLS_DBGPRT_ERR("spi cs afsel config error!"); + break; + } +} + + +void wm_spi_di_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_03: + tls_io_cfg_set(WM_IO_PA_03, WM_IO_OPTION3); + break; + + case WM_IO_PB_17: + tls_io_cfg_set(WM_IO_PB_17, WM_IO_OPTION3); + break; + + case WM_IO_PB_01: + tls_io_cfg_set(WM_IO_PB_01, WM_IO_OPTION1); + break; + + case WM_IO_PA_05: + tls_io_cfg_set(WM_IO_PA_05, WM_IO_OPTION3); + break; + + case WM_IO_PA_10: + tls_io_cfg_set(WM_IO_PA_10, WM_IO_OPTION4); + break; + + default: + TLS_DBGPRT_ERR("spi di afsel config error!"); + break; + } +} + +void wm_spi_do_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PB_18: + tls_io_cfg_set(WM_IO_PB_18, WM_IO_OPTION3); + break; + + case WM_IO_PB_02: + tls_io_cfg_set(WM_IO_PB_02, WM_IO_OPTION1); + break; + + case WM_IO_PA_04: + tls_io_cfg_set(WM_IO_PA_04, WM_IO_OPTION3); + break; + + case WM_IO_PA_09: + tls_io_cfg_set(WM_IO_PA_09, WM_IO_OPTION4); + break; + + case WM_IO_PA_10: + tls_io_cfg_set(WM_IO_PA_10, WM_IO_OPTION4); + break; + + default: + TLS_DBGPRT_ERR("spi do afsel config error!"); + break; + } +} + +void wm_sdio_config(uint8_t numsel) +{ + switch(numsel) + { + case 0: + tls_io_cfg_set(WM_IO_PB_08, WM_IO_OPTION3); + tls_io_cfg_set(WM_IO_PB_09, WM_IO_OPTION3); + tls_io_cfg_set(WM_IO_PB_10, WM_IO_OPTION3); + tls_io_cfg_set(WM_IO_PB_11, WM_IO_OPTION3); + tls_io_cfg_set(WM_IO_PB_12, WM_IO_OPTION3); + break; + + default: + TLS_DBGPRT_ERR("sdio afsel config error!"); + break; + } +} + +void wm_sdio_cmd_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_06: + tls_io_cfg_set(WM_IO_PA_06, WM_IO_OPTION3); + break; + + case WM_IO_PB_07: + tls_io_cfg_set(WM_IO_PB_07, WM_IO_OPTION3); + break; + + case WM_IO_PB_13: + tls_io_cfg_set(WM_IO_PB_13, WM_IO_OPTION4); + break; + + default: + TLS_DBGPRT_ERR("sdio cmd afsel config error!"); + break; + } +} + +void wm_uart0_tx_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_04: + tls_io_cfg_set(WM_IO_PA_04, WM_IO_OPTION1); + break; + + case WM_IO_PA_08: + tls_io_cfg_set(WM_IO_PA_08, WM_IO_OPTION3); + break; + + case WM_IO_PB_07: + tls_io_cfg_set(WM_IO_PB_07, WM_IO_OPTION2); + break; + + case WM_IO_PB_26: + tls_io_cfg_set(WM_IO_PB_26, WM_IO_OPTION2); + break; + + default: + TLS_DBGPRT_ERR("uart0 tx afsel config error!"); + break; + } +} + +void wm_uart0_rx_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_05: + tls_io_cfg_set(WM_IO_PA_05, WM_IO_OPTION1); + tls_bitband_write(HR_GPIOA_DATA_PULLEN, 5, 0); + break; + + case WM_IO_PA_09: + tls_io_cfg_set(WM_IO_PA_09, WM_IO_OPTION3); + tls_bitband_write(HR_GPIOA_DATA_PULLEN, 9, 0); + break; + + case WM_IO_PB_06: + tls_io_cfg_set(WM_IO_PB_06, WM_IO_OPTION2); + tls_bitband_write(HR_GPIOB_DATA_PULLEN, 6, 0); + break; + + case WM_IO_PB_25: + tls_io_cfg_set(WM_IO_PB_25, WM_IO_OPTION2); + tls_bitband_write(HR_GPIOB_DATA_PULLEN, 25, 0); + break; + + default: + TLS_DBGPRT_ERR("uart0 rx afsel config error!"); + break; + } +} + +void wm_uart0_rts_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_13: + tls_io_cfg_set(WM_IO_PA_13, WM_IO_OPTION1); + break; + + case WM_IO_PB_04: + tls_io_cfg_set(WM_IO_PB_04, WM_IO_OPTION2); + break; + + case WM_IO_PB_24: + tls_io_cfg_set(WM_IO_PB_24, WM_IO_OPTION2); + break; + + default: + TLS_DBGPRT_ERR("uart0 rts afsel config error!"); + break; + } +} + +void wm_uart0_cts_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_14: + tls_io_cfg_set(WM_IO_PA_14, WM_IO_OPTION1); + break; + + case WM_IO_PB_05: + tls_io_cfg_set(WM_IO_PB_05, WM_IO_OPTION2); + break; + + case WM_IO_PB_23: + tls_io_cfg_set(WM_IO_PB_23, WM_IO_OPTION2); + break; + + default: + TLS_DBGPRT_ERR("uart0 cts afsel config error!"); + break; + } +} + +void wm_uart1_tx_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PB_12: + tls_io_cfg_set(WM_IO_PB_12, WM_IO_OPTION1); + break; + + case WM_IO_PB_18: + tls_io_cfg_set(WM_IO_PB_18, WM_IO_OPTION4); + break; + + default: + TLS_DBGPRT_ERR("uart1 tx afsel config error!"); + break; + } +} + +void wm_uart1_rx_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PB_11: + tls_io_cfg_set(WM_IO_PB_11, WM_IO_OPTION1); + tls_bitband_write(HR_GPIOB_DATA_PULLEN, 11, 0); + break; + + case WM_IO_PB_17: + tls_io_cfg_set(WM_IO_PB_17, WM_IO_OPTION4); + tls_bitband_write(HR_GPIOB_DATA_PULLEN, 17, 0); + break; + + default: + TLS_DBGPRT_ERR("uart1 rx afsel config error!"); + break; + } +} + +void wm_uart1_rts_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PB_10: + tls_io_cfg_set(WM_IO_PB_10, WM_IO_OPTION1); + break; + + default: + TLS_DBGPRT_ERR("uart1 rts afsel config error!"); + break; + } +} + +void wm_uart1_cts_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PB_09: + tls_io_cfg_set(WM_IO_PB_09, WM_IO_OPTION1); + break; + + default: + TLS_DBGPRT_ERR("uart1 cts afsel config error!"); + break; + } +} + +void wm_uart2_tx_scio_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_01: + tls_io_cfg_set(WM_IO_PA_01, WM_IO_OPTION1); + break; + + case WM_IO_PA_11: + tls_io_cfg_set(WM_IO_PA_11, WM_IO_OPTION3); + break; + + case WM_IO_PB_02: + tls_io_cfg_set(WM_IO_PB_02, WM_IO_OPTION2); + break; + + case WM_IO_PB_20: + tls_io_cfg_set(WM_IO_PB_20, WM_IO_OPTION2); + break; + + default: + TLS_DBGPRT_ERR("uart2 tx afsel config error!"); + break; + } +} + +void wm_uart2_rx_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_00: + tls_io_cfg_set(WM_IO_PA_00, WM_IO_OPTION1); + tls_bitband_write(HR_GPIOA_DATA_PULLEN, 0, 0); + break; + + case WM_IO_PA_10: + tls_io_cfg_set(WM_IO_PA_10, WM_IO_OPTION3); + tls_bitband_write(HR_GPIOA_DATA_PULLEN, 10, 0); + break; + + case WM_IO_PB_03: + tls_io_cfg_set(WM_IO_PB_03, WM_IO_OPTION2); + tls_bitband_write(HR_GPIOB_DATA_PULLEN, 3, 0); + break; + + case WM_IO_PB_19: + tls_io_cfg_set(WM_IO_PB_19, WM_IO_OPTION2); + tls_bitband_write(HR_GPIOB_DATA_PULLEN, 19, 0); + break; + + case WM_IO_PB_30: + tls_io_cfg_set(WM_IO_PB_30, WM_IO_OPTION1); + tls_bitband_write(HR_GPIOB_DATA_PULLEN, 30, 0); + break; + + default: + TLS_DBGPRT_ERR("uart2 rx afsel config error!"); + break; + } +} + +void wm_uart2_rts_scclk_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_02: + tls_io_cfg_set(WM_IO_PA_02, WM_IO_OPTION1); + break; + + case WM_IO_PA_12: + tls_io_cfg_set(WM_IO_PA_12, WM_IO_OPTION3); + break; + + case WM_IO_PB_01: + tls_io_cfg_set(WM_IO_PB_01, WM_IO_OPTION2); + break; + + case WM_IO_PB_21: + tls_io_cfg_set(WM_IO_PB_21, WM_IO_OPTION2); + break; + + case WM_IO_PB_06: + tls_io_cfg_set(WM_IO_PB_06, WM_IO_OPTION4); + break; + + default: + TLS_DBGPRT_ERR("uart2 rts afsel config error!"); + break; + } +} + +void wm_uart2_cts_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_03: + tls_io_cfg_set(WM_IO_PA_03, WM_IO_OPTION1); + break; + + case WM_IO_PB_28: + tls_io_cfg_set(WM_IO_PB_28, WM_IO_OPTION2); + break; + + case WM_IO_PB_00: + tls_io_cfg_set(WM_IO_PB_00, WM_IO_OPTION2); + break; + + case WM_IO_PB_22: + tls_io_cfg_set(WM_IO_PB_22, WM_IO_OPTION2); + break; + + default: + TLS_DBGPRT_ERR("uart2 cts afsel config error!"); + break; + } +} + +void wm_i2s_m_ck_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_04: + tls_io_cfg_set(WM_IO_PA_04, WM_IO_OPTION4); + break; + + case WM_IO_PA_08: + tls_io_cfg_set(WM_IO_PA_08, WM_IO_OPTION1); + break; + + case WM_IO_PB_08: + tls_io_cfg_set(WM_IO_PB_08, WM_IO_OPTION4); + break; + + default: + TLS_DBGPRT_ERR("i2s master ck afsel config error!"); + break; + } +} + +void wm_i2s_m_ws_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_13: + tls_io_cfg_set(WM_IO_PA_13, WM_IO_OPTION2); + break; + + case WM_IO_PA_09: + tls_io_cfg_set(WM_IO_PA_09, WM_IO_OPTION1); + break; + + case WM_IO_PB_10: + tls_io_cfg_set(WM_IO_PB_10, WM_IO_OPTION4); + break; + + default: + TLS_DBGPRT_ERR("i2s master ws afsel config error!"); + break; + } +} + +void wm_i2s_m_do_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_03: + tls_io_cfg_set(WM_IO_PA_03, WM_IO_OPTION4); + break; + + case WM_IO_PA_07: + tls_io_cfg_set(WM_IO_PA_07, WM_IO_OPTION1); + break; + + case WM_IO_PB_09: + tls_io_cfg_set(WM_IO_PB_09, WM_IO_OPTION4); + break; + + default: + TLS_DBGPRT_ERR("i2s master do afsel config error!"); + break; + } +} + +void wm_i2s_s_ck_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_15: + tls_io_cfg_set(WM_IO_PA_15, WM_IO_OPTION2); + break; + + case WM_IO_PA_11: + tls_io_cfg_set(WM_IO_PA_11, WM_IO_OPTION1); + break; + + case WM_IO_PB_15: + tls_io_cfg_set(WM_IO_PB_15, WM_IO_OPTION4); + break; + + case WM_IO_PB_04: + tls_io_cfg_set(WM_IO_PB_04, WM_IO_OPTION4); + break; + + default: + TLS_DBGPRT_ERR("i2s slave ck afsel config error!"); + break; + } +} + +void wm_i2s_s_ws_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_06: + tls_io_cfg_set(WM_IO_PA_06, WM_IO_OPTION2); + break; + + case WM_IO_PA_12: + tls_io_cfg_set(WM_IO_PA_12, WM_IO_OPTION1); + break; + + case WM_IO_PB_16: + tls_io_cfg_set(WM_IO_PB_16, WM_IO_OPTION4); + break; + + case WM_IO_PB_05: + tls_io_cfg_set(WM_IO_PB_05, WM_IO_OPTION4); + break; + + default: + TLS_DBGPRT_ERR("i2s slave ws afsel config error!"); + break; + } +} + +void wm_i2s_s_di_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_14: + tls_io_cfg_set(WM_IO_PA_14, WM_IO_OPTION2); + break; + + case WM_IO_PA_10: + tls_io_cfg_set(WM_IO_PA_10, WM_IO_OPTION1); + break; + + case WM_IO_PB_14: + tls_io_cfg_set(WM_IO_PB_14, WM_IO_OPTION4); + break; + + case WM_IO_PB_03: + tls_io_cfg_set(WM_IO_PB_03, WM_IO_OPTION4); + break; + + default: + TLS_DBGPRT_ERR("i2s slave di afsel config error!"); + break; + } +} + +void wm_i2s_mclk_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_02: + tls_io_cfg_set(WM_IO_PA_02, WM_IO_OPTION4); + break; + + case WM_IO_PB_28: + tls_io_cfg_set(WM_IO_PB_28, WM_IO_OPTION1); + break; + + case WM_IO_PB_31: + tls_io_cfg_set(WM_IO_PB_31, WM_IO_OPTION1); + break; + + default: + TLS_DBGPRT_ERR("i2s mclk afsel config error!"); + break; + } +} + +void wm_i2s_extclk_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_05: + tls_io_cfg_set(WM_IO_PA_05, WM_IO_OPTION4); + break; + + default: + TLS_DBGPRT_ERR("i2s extclk afsel config error!"); + break; + } +} + +void wm_i2c_scl_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_06: + tls_io_cfg_set(WM_IO_PA_06, WM_IO_OPTION1); + break; + + case WM_IO_PA_08: + tls_io_cfg_set(WM_IO_PA_08, WM_IO_OPTION4); + break; + + case WM_IO_PB_13: + tls_io_cfg_set(WM_IO_PB_13, WM_IO_OPTION3); + break; + + case WM_IO_PB_11: + tls_io_cfg_set(WM_IO_PB_11, WM_IO_OPTION4); + break; + + case WM_IO_PB_21: + tls_io_cfg_set(WM_IO_PB_21, WM_IO_OPTION3); + break; + + default: + TLS_DBGPRT_ERR("i2c scl afsel config error!"); + break; + } +} + +void wm_i2c_sda_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_15: + tls_io_cfg_set(WM_IO_PA_15, WM_IO_OPTION1); + break; + + case WM_IO_PA_07: + tls_io_cfg_set(WM_IO_PA_07, WM_IO_OPTION4); + break; + + case WM_IO_PB_14: + tls_io_cfg_set(WM_IO_PB_14, WM_IO_OPTION3); + break; + + case WM_IO_PB_12: + tls_io_cfg_set(WM_IO_PB_12, WM_IO_OPTION4); + break; + + case WM_IO_PB_22: + tls_io_cfg_set(WM_IO_PB_22, WM_IO_OPTION3); + break; + + default: + TLS_DBGPRT_ERR("i2c sda afsel config error!"); + break; + } +} + +void wm_pwm1_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_00: + tls_io_cfg_set(WM_IO_PA_00, WM_IO_OPTION2); + break; + + case WM_IO_PB_18: + tls_io_cfg_set(WM_IO_PB_18, WM_IO_OPTION2); + break; + + case WM_IO_PB_05: + tls_io_cfg_set(WM_IO_PB_05, WM_IO_OPTION3); + break; + + case WM_IO_PA_05: + tls_io_cfg_set(WM_IO_PA_05, WM_IO_OPTION2); + break; + + case WM_IO_PB_19: + tls_io_cfg_set(WM_IO_PB_19, WM_IO_OPTION1); + break; + + case WM_IO_PB_30: + tls_io_cfg_set(WM_IO_PB_30, WM_IO_OPTION2); + break; + + default: + TLS_DBGPRT_ERR("pwm1 afsel config error!"); + break; + } +} + + +void wm_pwm2_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_01: + tls_io_cfg_set(WM_IO_PA_01, WM_IO_OPTION2); + break; + + case WM_IO_PB_17: + tls_io_cfg_set(WM_IO_PB_17, WM_IO_OPTION2); + break; + + case WM_IO_PB_04: + tls_io_cfg_set(WM_IO_PB_04, WM_IO_OPTION3); + break; + + case WM_IO_PA_07: + tls_io_cfg_set(WM_IO_PA_07, WM_IO_OPTION2); + break; + + case WM_IO_PB_13: + tls_io_cfg_set(WM_IO_PB_13, WM_IO_OPTION1); + break; + + case WM_IO_PB_20: + tls_io_cfg_set(WM_IO_PB_20, WM_IO_OPTION1); + break; + + default: + TLS_DBGPRT_ERR("pwm2 afsel config error!"); + break; + } +} + +void wm_pwm3_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_02: + tls_io_cfg_set(WM_IO_PA_02, WM_IO_OPTION2); + break; + + case WM_IO_PB_16: + tls_io_cfg_set(WM_IO_PB_16, WM_IO_OPTION2); + break; + + case WM_IO_PB_03: + tls_io_cfg_set(WM_IO_PB_03, WM_IO_OPTION3); + break; + + case WM_IO_PA_08: + tls_io_cfg_set(WM_IO_PA_08, WM_IO_OPTION2); + break; + + case WM_IO_PB_21: + tls_io_cfg_set(WM_IO_PB_21, WM_IO_OPTION1); + break; + + default: + TLS_DBGPRT_ERR("pwm3 afsel config error!"); + break; + } +} + +void wm_pwm4_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_03: + tls_io_cfg_set(WM_IO_PA_03, WM_IO_OPTION2); + break; + + case WM_IO_PB_15: + tls_io_cfg_set(WM_IO_PB_15, WM_IO_OPTION2); + break; + + case WM_IO_PB_02: + tls_io_cfg_set(WM_IO_PB_02, WM_IO_OPTION3); + break; + + case WM_IO_PA_09: + tls_io_cfg_set(WM_IO_PA_09, WM_IO_OPTION2); + break; + + case WM_IO_PB_22: + tls_io_cfg_set(WM_IO_PB_22, WM_IO_OPTION1); + break; + + case WM_IO_PB_06: + tls_io_cfg_set(WM_IO_PB_06, WM_IO_OPTION3); + break; + + default: + TLS_DBGPRT_ERR("pwm4 afsel config error!"); + break; + } +} + +void wm_pwm5_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PA_04: + tls_io_cfg_set(WM_IO_PA_04, WM_IO_OPTION2); + break; + + case WM_IO_PB_14: + tls_io_cfg_set(WM_IO_PB_14, WM_IO_OPTION2); + break; + + case WM_IO_PB_01: + tls_io_cfg_set(WM_IO_PB_01, WM_IO_OPTION3); + break; + + case WM_IO_PA_10: + tls_io_cfg_set(WM_IO_PA_10, WM_IO_OPTION2); + break; + + case WM_IO_PB_23: + tls_io_cfg_set(WM_IO_PB_23, WM_IO_OPTION1); + break; + + case WM_IO_PB_08: + tls_io_cfg_set(WM_IO_PB_08, WM_IO_OPTION1); + break; + + default: + TLS_DBGPRT_ERR("pwm5 afsel config error!"); + break; + } +} + +void wm_pwmbrk_config(enum tls_io_name io_name) +{ + switch(io_name) + { + case WM_IO_PB_24: + tls_io_cfg_set(WM_IO_PB_24, WM_IO_OPTION1); + break; + + case WM_IO_PB_29: + tls_io_cfg_set(WM_IO_PB_29, WM_IO_OPTION2); + break; + + case WM_IO_PB_00: + tls_io_cfg_set(WM_IO_PB_00, WM_IO_OPTION3); + break; + + case WM_IO_PA_11: + tls_io_cfg_set(WM_IO_PA_11, WM_IO_OPTION2); + break; + + default: + TLS_DBGPRT_ERR("pwmbrk afsel config error!"); + break; + } +} + +void wm_swd_config(bool enable) +{ + if (enable) + { + tls_io_cfg_set(WM_IO_PB_06, WM_IO_OPTION1); + tls_io_cfg_set(WM_IO_PB_07, WM_IO_OPTION1); + } + else + { + tls_io_cfg_set(WM_IO_PB_06, WM_IO_OPTION5); + tls_io_cfg_set(WM_IO_PB_07, WM_IO_OPTION5); + } +} + +void wm_adc_config(u8 Channel) +{ + switch(Channel) + { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + tls_io_cfg_set((enum tls_io_name)(WM_IO_PB_19+Channel), WM_IO_OPTION6); + break; + case 8: + case 9: + case 10: + case 11: + tls_io_cfg_set((enum tls_io_name)(WM_IO_PB_19+(Channel-8)*2), WM_IO_OPTION6); + tls_io_cfg_set((enum tls_io_name)(WM_IO_PB_19+(Channel-8)*2+1), WM_IO_OPTION6); + break; + + default: + break; + } +} + +void wm_gpio_af_disable(void) +{ + tls_reg_write32(HR_GPIOA_AFSEL, 0x0); + tls_reg_write32(HR_GPIOB_AFSEL, BIT(6) | BIT(7));//only enable swd +} + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_hostspi.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_hostspi.c new file mode 100644 index 00000000..d858946c --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_hostspi.c @@ -0,0 +1,1372 @@ +/** + * @file wm_hostspi.c + * + * @brief host spi Driver Module + * + * @author dave + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ +#include +#include +#include +#include "wm_regs.h" +#include "wm_irq.h" +#include "wm_gpio.h" +#include "wm_hostspi.h" +#include "wm_dma.h" +#include "wm_dbg.h" +//#include "wm_mem.h" +#include "wm_cpu.h" +#include "wm_spi_hal.h" +//#include "wm_wl_task.h" +#include "tls_common.h" + +static struct tls_spi_port *spi_port = NULL; + +#define MSG_QUEUE_SIZE (8) + +#define SPI_SCHEDULER_STK_SIZE (128) +static u32 spi_scheduler_stk[SPI_SCHEDULER_STK_SIZE]; + +#define SPI_SCHED_MSG_START_ENGINE (1) +#define SPI_SCHED_MSG_TX_FIFO_READY (2) +#define SPI_SCHED_MSG_RX_FIFO_READY (3) +#define SPI_SCHED_MSG_TRANSFER_COMPLETE (4) +#define SPI_SCHED_MSG_EXIT (5) +#define SPI_SCHED_MSG_END (6) +static void spi_start_transfer(u32 transfer_bytes); + +int tls_spi_async(struct tls_spi_message *message); +int tls_spi_sync(struct tls_spi_message *message); + +#ifdef SPI_USE_DMA +static void SpiMasterInit(u8 mode, u8 cs_active, u32 fclk) +{ + tls_sys_clk sysclk; + + SPIM_CHCFG_REG = SPI_CLEAR_FIFOS; + while (SPIM_CHCFG_REG & SPI_CLEAR_FIFOS); + + tls_sys_clk_get(&sysclk); //鑾峰彇瀹為檯棰戠巼 + + SPIM_CLKCFG_REG = sysclk.apbclk*UNIT_MHZ/(fclk*2) - 1;; + SPIM_SPICFG_REG = 0; + SPIM_SPICFG_REG = SPI_FRAME_FORMAT_MOTO | SPI_SET_MASTER_SLAVE(SPI_MASTER) | mode; + SPIM_INTEN_REG = 0xff; /* Disable INT */ + + tls_dma_init(); +} + +int spiWaitIdle(void) +{ + unsigned long regVal; + unsigned long timeout = 0; + + do + { + timeout++; + if (timeout > 0x4FFFFF) // 5s + return TLS_SPI_STATUS_EBUSY; + regVal = SPIM_SPISTATUS_REG; + } + while (regVal & (1 << 12)); + + return TLS_SPI_STATUS_OK; +} + +static int SpiDmaBlockWrite(u8 * data, u32 len, u8 ifusecmd, u32 cmd) +{ + unsigned char dmaCh = 0; + struct tls_dma_descriptor DmaDesc; + u32 txlen, txlenbk; + u32 i, blocknum, blocksize = 0; + int ret = TLS_SPI_STATUS_OK; + int txcmdover = 0; + + if (NULL == data) + { + return TLS_SPI_STATUS_EINVAL; + } + if (spiWaitIdle()) + return TLS_SPI_STATUS_EBUSY; + SPIM_CHCFG_REG = SPI_CLEAR_FIFOS; + while (SPIM_CHCFG_REG & SPI_CLEAR_FIFOS); + + if (ifusecmd) + SPIM_TXDATA_REG = cmd; + + if (len % 4) + { + txlen = len & 0xfffffffc; // 涓嶅瀛楃殑鏈鍚庡崟鐙彂 + } + else + { + txlen = len; + } + + txlenbk = txlen; + if (txlen > 0) + { + blocknum = txlen / SPI_DMA_MAX_TRANS_SIZE; + + /* Request DMA Channel */ + dmaCh = tls_dma_request(1,TLS_DMA_FLAGS_CHANNEL_SEL(TLS_DMA_SEL_LSSPI_TX) | + TLS_DMA_FLAGS_HARD_MODE); + for (i = 0; i <= blocknum; i++) + { + DmaDesc.src_addr = (int) (data + i * SPI_DMA_MAX_TRANS_SIZE); + DmaDesc.dest_addr = HR_SPI_TXDATA_REG; + blocksize = (txlen > SPI_DMA_MAX_TRANS_SIZE) ? SPI_DMA_MAX_TRANS_SIZE : txlen; + + if (0 == blocksize) + break; + DmaDesc.dma_ctrl = TLS_DMA_DESC_CTRL_SRC_ADD_INC | + TLS_DMA_DESC_CTRL_DATA_SIZE_WORD | + TLS_DMA_DESC_CTRL_TOTAL_BYTES(blocksize); + DmaDesc.valid = TLS_DMA_DESC_VALID; + DmaDesc.next = NULL; + tls_dma_start(dmaCh, &DmaDesc, 0); + /* Enable SPI TX DMA */ + SPIM_MODECFG_REG = SPI_RX_TRIGGER_LEVEL(0) | SPI_TX_TRIGGER_LEVEL(0) | SPI_TX_DMA_ON; + SPIM_SPITIMEOUT_REG = SPI_TIMER_EN | SPI_TIME_OUT((u32) 0xffff); + + if (ifusecmd && 0 == i) + { + SPIM_CHCFG_REG = SPI_FORCE_SPI_CS_OUT | SPI_TX_CHANNEL_ON | + SPI_CONTINUE_MODE | SPI_START | + SPI_VALID_CLKS_NUM(((blocksize + 4) * 8)); + txcmdover = 1; + } + else + SPIM_CHCFG_REG = SPI_FORCE_SPI_CS_OUT | SPI_TX_CHANNEL_ON | SPI_CONTINUE_MODE | + SPI_START | SPI_VALID_CLKS_NUM((blocksize * 8)); + + if (spiWaitIdle()) + { + ret = TLS_SPI_STATUS_EBUSY; + break; + } + /* Wait Dma Channel Complete and Free Dma channel */ + if (tls_dma_wait_complt(dmaCh)) + { + ret = TLS_SPI_STATUS_EBUSY; + break; + } + txlen -= blocksize; + } + tls_dma_free(dmaCh); + } + // tx 涓嶅涓涓暣瀛楃殑鍑犱釜瀛楄妭 + if (len > txlenbk) + { + u32 word32 = 0; + int temp = 0; + for (i = 0; i < (len - txlenbk); i++) + { + word32 |= (data[txlenbk + i] << (i * 8)); + } + SPIM_TXDATA_REG = word32; + SPIM_MODECFG_REG = SPI_RX_TRIGGER_LEVEL(0) | SPI_TX_TRIGGER_LEVEL(0); + SPIM_SPITIMEOUT_REG = SPI_TIMER_EN | SPI_TIME_OUT((u32) 0xffff); + if (ifusecmd && 0 == txcmdover) // 闇瑕佸彂閫佸懡浠わ紝浣嗘槸鍛戒护杩樻病鏈夊彂閫佸嚭鍘伙紝鍙戦佺殑瀛楄妭鏁伴渶瑕佸鍔4 + temp = 4; + SPIM_CHCFG_REG = SPI_FORCE_SPI_CS_OUT | SPI_TX_CHANNEL_ON | SPI_CONTINUE_MODE | + SPI_START | SPI_VALID_CLKS_NUM(((temp + len - txlenbk) * 8)); + if (spiWaitIdle()) + { + ret = TLS_SPI_STATUS_EBUSY; + } + } + SPIM_CHCFG_REG = 0x00000000; + SPIM_MODECFG_REG = 0x00000000; + SPIM_SPITIMEOUT_REG = 0x00000000; + + return ret; +} + +static int SpiDmaBlockRead(u8 * data, u32 len, u8 * txdata, u8 txlen) +{ + unsigned char dmaCh = 0; + struct tls_dma_descriptor DmaDesc; + u32 word32 = 0; + u32 i; + u32 rxlen, rxlenbk; + u8 blocknum; + u32 blocksize = 0; + int ret = TLS_SPI_STATUS_OK; + +// printf("\nentry SpiDmaBlockRead\n"); + if (NULL == data) + { + return TLS_SPI_STATUS_EINVAL; + } + if (spiWaitIdle()) + { + return TLS_SPI_STATUS_EBUSY; + } + + SPIM_CHCFG_REG = SPI_CLEAR_FIFOS; + while (SPIM_CHCFG_REG & SPI_CLEAR_FIFOS); + + if (len % 4) + { + rxlen = len & 0xfffffffc; // 涓嶅瀛楃殑鏈鍚庡崟鐙彇 + } + else + { + rxlen = len; + } + rxlenbk = rxlen; + blocknum = rxlen / SPI_DMA_MAX_TRANS_SIZE; + + if (txlen > 0 && txlen <= 32) + { + for (i = 0; i < txlen; i++) + { + if ((i > 0) && (0 == i % 4)) + { + SPIM_TXDATA_REG = word32; + word32 = 0; + } + word32 |= (txdata[i] << ((i % 4) * 8)); + } + SPIM_TXDATA_REG = word32; + } + +/* Request DMA Channel */ + dmaCh = tls_dma_request(1,TLS_DMA_FLAGS_CHANNEL_SEL(TLS_DMA_SEL_LSSPI_RX) | + TLS_DMA_FLAGS_HARD_MODE); + DmaDesc.src_addr = HR_SPI_RXDATA_REG; + for (i = 0; i <= blocknum; i++) + { + if (rxlenbk > 0) + { + // 璇存槑鎺ユ敹鐨勬暟鎹ぇ浜4 + // printf("\ni =%d\n",i); + DmaDesc.dest_addr = (int) (data + i * SPI_DMA_MAX_TRANS_SIZE); + blocksize = (rxlen > SPI_DMA_MAX_TRANS_SIZE) ? SPI_DMA_MAX_TRANS_SIZE : rxlen; + if (0 == blocksize) + break; + // printf("\nblocksize= %d\n",blocksize); + DmaDesc.dma_ctrl = + TLS_DMA_DESC_CTRL_DEST_ADD_INC | TLS_DMA_DESC_CTRL_BURST_SIZE1 | + TLS_DMA_DESC_CTRL_DATA_SIZE_WORD | + TLS_DMA_DESC_CTRL_TOTAL_BYTES(blocksize); + // word32 = DmaDesc.dma_ctrl; + // printf("\ndma ctrl = %x\n",DmaDesc.dma_ctrl); + DmaDesc.valid = TLS_DMA_DESC_VALID; + DmaDesc.next = NULL; + tls_dma_start(dmaCh, &DmaDesc, 0); + /* Enable SPI RX DMA */ + SPIM_MODECFG_REG = SPI_RX_TRIGGER_LEVEL(0) | SPI_TX_TRIGGER_LEVEL(0) | + SPI_RX_DMA_ON; + } + else + { + SPIM_MODECFG_REG = SPI_RX_TRIGGER_LEVEL(0) | SPI_TX_TRIGGER_LEVEL(0); // rx鏁版嵁灏戜簬4涓猙yte锛屼笉鐢ㄥ紑DMA + } + SPIM_SPITIMEOUT_REG = SPI_TIMER_EN | SPI_TIME_OUT((u32) 0xffff); + if (0 == blocknum) + { + SPIM_CHCFG_REG = + SPI_FORCE_SPI_CS_OUT | SPI_RX_CHANNEL_ON | SPI_TX_CHANNEL_ON | + SPI_CONTINUE_MODE | SPI_START | + SPI_VALID_CLKS_NUM(((len + txlen) * 8)) | SPI_RX_INVALID_BITS(txlen *8); + } + else + { + if (0 == i) // 绗竴娆￠渶瑕佹墦寮TX + { + SPIM_CHCFG_REG = + SPI_FORCE_SPI_CS_OUT | SPI_RX_CHANNEL_ON | SPI_TX_CHANNEL_ON + | SPI_CONTINUE_MODE | SPI_START | + SPI_VALID_CLKS_NUM(((blocksize + txlen) *8)) | SPI_RX_INVALID_BITS(txlen * 8); + } + else if (i == blocknum) + { + SPIM_CHCFG_REG = + SPI_FORCE_SPI_CS_OUT | SPI_RX_CHANNEL_ON | SPI_CONTINUE_MODE + | SPI_START | SPI_VALID_CLKS_NUM((blocksize + len - rxlenbk) * 8); + } + else + { + SPIM_CHCFG_REG = + SPI_FORCE_SPI_CS_OUT | SPI_RX_CHANNEL_ON | SPI_CONTINUE_MODE + | SPI_START | SPI_VALID_CLKS_NUM(blocksize * 8); + } + } + if (spiWaitIdle()) + { + ret = TLS_SPI_STATUS_EBUSY; + break; + } + + /* Wait Dma Channel Complete and Free Dma channel */ + if (tls_dma_wait_complt(dmaCh)) + { + ret = TLS_SPI_STATUS_EBUSY; + break; + } + rxlen -= blocksize; + } + tls_dma_free(dmaCh); + + if (len > rxlenbk) // 鍙栨渶鍚庣殑涓嶅涓涓瓧鐨勫嚑涓猙yte + { + word32 = SPIM_RXDATA_REG; + *((int *) data + rxlenbk / 4) = word32; + } + SPIM_CHCFG_REG = 0x00000000; + SPIM_MODECFG_REG = 0x00000000; + SPIM_SPITIMEOUT_REG = 0x00000000; + return ret; +} +#endif + + +/** + * @brief This function is used to set SPI transfer mode. + * + * @param[in] type is the transfer type. + * type == SPI_BYTE_TRANSFER byte transfer + * type == SPI_WORD_TRANSFER word transfer + * type == SPI_DMA_TRANSFER DMA transfer + * + * @return None + * + * @note None + */ +void tls_spi_trans_type(u8 type) +{ + + spi_port->transtype = type; + if (SPI_WORD_TRANSFER == type) + { + spi_set_endian(0); + } + else if (SPI_DMA_TRANSFER == type) + { +#ifdef SPI_USE_DMA + SpiMasterInit(spi_port->mode, TLS_SPI_CS_LOW, spi_port->speed_hz); +#endif + } +} + +static void spi_message_init(struct tls_spi_message *m) +{ + memset(m, 0, sizeof(*m)); + dl_list_init(&m->transfers); +} + + +static void spi_complete(void *arg) +{ + tls_os_sem_t *sem; + + sem = (tls_os_sem_t *) arg; + tls_os_sem_release(sem); +} + +static u32 spi_fill_txfifo(struct tls_spi_transfer *current_transfer, + u32 current_remaining_bytes) +{ + u8 fifo_level; + u16 rw_words; + u16 rw_bytes; + u8 data8; + u8 i; + u32 data32 = 0; + u32 tx_remaining_bytes; + if ((current_transfer == NULL) || (current_remaining_bytes == 0)) + return 0; + + tx_remaining_bytes = current_remaining_bytes; + +// printf("ready to write to fifo size - %d.\n", tx_remaining_bytes); + spi_get_status(NULL, NULL, &fifo_level); + +// TLS_DBGPRT_SPI("\nfifo_level 0= %d\n",fifo_level); + rw_words = + ((fifo_level > tx_remaining_bytes) ? tx_remaining_bytes : fifo_level) / 4; + rw_bytes = + ((fifo_level > tx_remaining_bytes) ? tx_remaining_bytes : fifo_level) % 4; + +// TLS_DBGPRT_SPI("write to spi fifo words - %d, bytes - %d.\n", rw_words, +// rw_bytes); + +//涓嬮潰浠ｇ爜17us + for (i = 0; i < rw_words; i++) + { + if (current_transfer->tx_buf) + { + if (SPI_BYTE_TRANSFER == spi_port->transtype) + { + data32 = 0; + data32 |= ((u8 *) current_transfer->tx_buf + + (current_transfer->len - tx_remaining_bytes))[0] << 24; + data32 |= ((u8 *) current_transfer->tx_buf + + (current_transfer->len - tx_remaining_bytes))[1] << 16; + data32 |= ((u8 *) current_transfer->tx_buf + + (current_transfer->len - tx_remaining_bytes))[2] << 8; + data32 |= ((u8 *) current_transfer->tx_buf + + (current_transfer->len - tx_remaining_bytes))[3] << 0; + } + else if (SPI_WORD_TRANSFER == spi_port->transtype) + { + data32 = *((u32 *) ((u8 *) current_transfer->tx_buf + + current_transfer->len - tx_remaining_bytes)); + } + } + else + { + data32 = 0xffffffff; + } + // TLS_DBGPRT_SPI("write to spi fifo word[%d]: 0x%x.\n", i, data32); + spi_data_put(data32); + tx_remaining_bytes -= 4; + } + + if (rw_bytes) + { + data32 = 0; + for (i = 0; i < rw_bytes; i++) + { + if (current_transfer->tx_buf) + { + data8 = ((u8 *) current_transfer->tx_buf)[current_transfer->len - + tx_remaining_bytes]; + } + else + { + data8 = 0xff; + } + if (SPI_BYTE_TRANSFER == spi_port->transtype) + data32 |= data8 << ((3 - i) * 8); + else if (SPI_WORD_TRANSFER == spi_port->transtype) + { + data32 |= data8 << (i * 8); + } + tx_remaining_bytes -= 1; + } + // TLS_DBGPRT_SPI("write to spi fifo word: 0x%x.\n", data32); + spi_data_put(data32); + } + + return (current_remaining_bytes - tx_remaining_bytes); +} + +static u32 spi_get_rxfifo(struct tls_spi_transfer *current_transfer, + u32 current_remaining_bytes) +{ + u8 fifo_level; + u8 rw_words; + u8 rw_bytes; + u8 data8 = 0; + u8 i; + u32 data32; + u32 rx_remaining_bytes; + + if ((current_transfer == NULL) || (current_remaining_bytes == 0)) + return 0; + + rx_remaining_bytes = current_remaining_bytes; + spi_get_status(NULL, &fifo_level, NULL); +// TLS_DBGPRT_SPI("rx fifo level: %d.\n", fifo_level); + + rw_words = fifo_level / 4; + rw_bytes = fifo_level % 4; + +// TLS_DBGPRT_SPI("rx data: %d words, %d bytes.\n", rw_words, rw_bytes); + +//涓嬮潰浠ｇ爜澶ф10us + for (i = 0; i < rw_words; i++) + { + + data32 = spi_data_get(); + + // TLS_DBGPRT_SPI("rx data[%d](w): 0x%08x.\n", i, data32); + if (current_transfer->rx_buf) + { + + if (SPI_BYTE_TRANSFER == spi_port->transtype) + { + data32 = swap_32(data32); + (((u8 *) current_transfer->rx_buf + + (current_transfer->len - rx_remaining_bytes)))[0] = (u8) data32; + (((u8 *) current_transfer->rx_buf + + (current_transfer->len - rx_remaining_bytes)))[1] = (u8) (data32 >> 8); + (((u8 *) current_transfer->rx_buf + + (current_transfer->len - rx_remaining_bytes)))[2] = (u8) (data32 >> 16); + (((u8 *) current_transfer->rx_buf + + (current_transfer->len - rx_remaining_bytes)))[3] = (u8) (data32 >> 24); + } + else if (SPI_WORD_TRANSFER == spi_port->transtype) + { + *((u32 *) ((u8 *) current_transfer->rx_buf + + current_transfer->len - rx_remaining_bytes)) = data32; + } + } + rx_remaining_bytes -= 4; + + } + + if (rw_bytes) + { + data32 = spi_data_get(); + // TLS_DBGPRT_SPI("\nrx data=%x\n",data32); + if (current_transfer->rx_buf) + { + for (i = 0; i < rw_bytes; i++) + { + if (SPI_BYTE_TRANSFER == spi_port->transtype) + data8 = (u8) (data32 >> ((3 - i) * 8)); + else if (SPI_WORD_TRANSFER == spi_port->transtype) + data8 = (u8) (data32 >> (i * 8)); + + // TLS_DBGPRT_SPI("rx data[%d](b): 0x%02x.\n", i, data8); + ((u8 *) current_transfer->rx_buf)[current_transfer->len -rx_remaining_bytes] = data8; + rx_remaining_bytes -= 1; + } + } + else + { + rx_remaining_bytes -= rw_bytes; + } + } + + return (current_remaining_bytes - rx_remaining_bytes); +} + +static struct tls_spi_transfer *spi_next_transfer(struct tls_spi_message + *current_message) +{ + if (current_message == NULL) + { + return NULL; + } + + return dl_list_first(¤t_message->transfers, struct tls_spi_transfer, transfer_list); +} + +static struct tls_spi_message *spi_next_message(void) +{ + struct tls_spi_message *current_message; + + current_message = + dl_list_first(&spi_port->wait_queue, struct tls_spi_message, queue); + if (current_message == NULL) + { + return NULL; + } + + spi_port->current_transfer = spi_next_transfer(current_message); + current_message->status = SPI_MESSAGE_STATUS_INPROGRESS; + + return current_message; +} + +int gSpiCsFlag = 0; +static void spi_start_transfer(u32 transfer_bytes) +{ + if (spi_port->reconfig) + { + TLS_DBGPRT_SPI_INFO("reconfig the spi master controller.\n"); + spi_set_mode(spi_port->mode); + spi_set_chipselect_mode(spi_port->cs_active); + spi_set_sclk(spi_port->speed_hz); + + spi_port->reconfig = 0; + } + + spi_set_sclk_length(transfer_bytes * 8, 0); +// if(0 == gSpiCsFlag) + { + spi_set_chipselect_mode(SPI_CS_ACTIVE_MODE); + } + spi_sclk_start(); +} + +static void spi_continue_transfer(void) +{ + struct tls_spi_message *current_message; + struct tls_spi_transfer *current_transfer; + u32 transfer_bytes; + + current_message = spi_port->current_message; + current_transfer = spi_port->current_transfer; + if ((current_message == NULL) || (current_transfer == NULL)) + { + return; + } + transfer_bytes = + spi_get_rxfifo(current_transfer, spi_port->current_remaining_bytes); + + spi_port->current_remaining_bytes -= transfer_bytes; + if (spi_port->current_remaining_bytes == 0) + { + tls_os_sem_acquire(spi_port->lock, 0); + + dl_list_del(¤t_transfer->transfer_list); + spi_port->current_transfer = + spi_next_transfer(spi_port->current_message); + if (spi_port->current_transfer == NULL) + { +// tls_sys_clk_set(CPU_CLK_40M); + spi_set_chipselect_mode(SPI_CS_INACTIVE_MODE); + current_message->status = SPI_MESSAGE_STATUS_DONE; + dl_list_del(¤t_message->queue); + spi_port->current_message = spi_next_message(); + } + + tls_os_sem_release(spi_port->lock); + + // TLS_DBGPRT_SPI("get the next spi transfer pair.\n"); + current_transfer = spi_port->current_transfer; + if (current_transfer != NULL) + { + spi_port->current_remaining_bytes = current_transfer->len; + } + } + + transfer_bytes = + spi_fill_txfifo(current_transfer, spi_port->current_remaining_bytes); + + if (transfer_bytes) + { + spi_start_transfer(transfer_bytes); + } + + if (current_message->status == SPI_MESSAGE_STATUS_DONE) + { + // TLS_DBGPRT_SPI("current spi transaction finish and notify the + // submitter.\n"); + current_message->complete(current_message->context); + } +} + +static void spi_scheduler(void *data) +{ + u8 err; + u32 msg; + u32 transfer_bytes; + struct tls_spi_transfer *current_transfer; + + while (1) + { + err = tls_os_queue_receive(spi_port->msg_queue, (void **) &msg, 4, 0); + if (err == TLS_OS_SUCCESS) + { + switch (msg) + { + case SPI_SCHED_MSG_START_ENGINE: +// tls_sys_clk_set(CPU_CLK_80M); //80MHZ + if (spi_port->current_message) + { + TLS_DBGPRT_WARNING + ("spi transaction scheduler is running now!\n"); + break; + } + + TLS_DBGPRT_SPI_INFO + ("acquire the first transaction message in waiting queue.\n"); + tls_os_sem_acquire(spi_port->lock, 0); + + spi_port->current_message = spi_next_message(); + + tls_os_sem_release(spi_port->lock); + + // TLS_DBGPRT_SPI("acquire the first transfer pair in the + // current transaction message.\n"); + current_transfer = spi_port->current_transfer; + if (current_transfer == NULL) + { + break; + } + spi_port->current_remaining_bytes = current_transfer->len; + + // TLS_DBGPRT_SPI("current transfer lenght - %d.\n", + // spi_port->current_remaining_bytes); + + // TLS_DBGPRT_SPI("fill the tx fifo.\n"); + + transfer_bytes = + spi_fill_txfifo(current_transfer, spi_port->current_remaining_bytes); + + // printf("start the spi transfer - %d.\n", transfer_bytes); + spi_start_transfer(transfer_bytes); + + break; + + case SPI_SCHED_MSG_TX_FIFO_READY: + TLS_DBGPRT_SPI_INFO("process SPI_SCHED_MSG_TX_FIFO_READY.\n"); + break; + + case SPI_SCHED_MSG_RX_FIFO_READY: + TLS_DBGPRT_SPI_INFO("process SPI_SCHED_MSG_RX_FIFO_READY.\n"); + break; + + case SPI_SCHED_MSG_TRANSFER_COMPLETE: + spi_continue_transfer(); + break; + + case SPI_SCHED_MSG_EXIT: + break; + + default: + break; + } + } + } +} + +void SPI_LS_IRQHandler(void) +{ + + u32 int_status; + u32 int_mask; + int_status = spi_get_int_status(); +// printf("\nspi int sta=%x\n",int_status); + spi_clear_int_status(int_status); + + int_mask = spi_int_mask(); + int_status &= ~int_mask; + +// printf("spi interrupt - 0x%x.\n", int_status); + + if (int_status & SPI_INT_TX_FIFO_RDY) + { + tls_os_queue_send(spi_port->msg_queue, + (void *) SPI_SCHED_MSG_TX_FIFO_READY, 4); + } + + if (int_status & SPI_INT_RX_FIFO_RDY) + { + tls_os_queue_send(spi_port->msg_queue, + (void *) SPI_SCHED_MSG_RX_FIFO_READY, 4); + } + + if (int_status & SPI_INT_TRANSFER_DONE) + { + if (SPI_WORD_TRANSFER == spi_port->transtype) + spi_continue_transfer(); + else + tls_os_queue_send(spi_port->msg_queue, + (void *) SPI_SCHED_MSG_TRANSFER_COMPLETE, 4); + + } +} + + + /** + * @brief This function is used to setup the spi CPOL,CPHA,cs signal and clock. + * + * @param[in] mode is CPOL and CPHA type defined in TLS_SPI_MODE_0 to TLS_SPI_MODE_3 + * @param[in] cs_active is cs mode, defined as TLS_SPI_CS_LOW or TLS_SPI_CS_HIGH + * @param[in] fclk is spi clock,the unit is HZ. + * + * @retval TLS_SPI_STATUS_OK if setup success + * @retval TLS_SPI_STATUS_EMODENOSUPPORT if mode is not support + * @retval TLS_SPI_STATUS_EINVAL if cs_active is not support + * @retval TLS_SPI_STATUS_ECLKNOSUPPORT if fclk is not support + * + * @note None + */ +int tls_spi_setup(u8 mode, u8 cs_active, u32 fclk) +{ + tls_sys_clk sysclk; + + if ((spi_port->mode == mode) && (spi_port->cs_active == cs_active) + && (spi_port->speed_hz == fclk)) + { + TLS_DBGPRT_WARNING + ("@mode, @cs_activer, @fclk is the same as settings of the current spi master driver!\n"); + return TLS_SPI_STATUS_OK; + } + + switch (mode) + { + case TLS_SPI_MODE_0: + case TLS_SPI_MODE_1: + case TLS_SPI_MODE_2: + case TLS_SPI_MODE_3: + spi_port->mode = mode; + break; + + default: + TLS_DBGPRT_ERR("@mode is invalid!\n"); + return TLS_SPI_STATUS_EMODENOSUPPORT; + } + + if ((cs_active != TLS_SPI_CS_HIGH) && (cs_active != TLS_SPI_CS_LOW)) + { + TLS_DBGPRT_ERR("@cs_active is invalid!\n"); + return TLS_SPI_STATUS_EINVAL; + } + else + { + spi_port->cs_active = cs_active; + } + + tls_sys_clk_get(&sysclk); + + if ((fclk < TLS_SPI_FCLK_MIN) || (fclk > sysclk.apbclk*UNIT_MHZ/2)) //TLS_SPI_FCLK_MAX + { + TLS_DBGPRT_ERR("@fclk is invalid!\n"); + return TLS_SPI_STATUS_ECLKNOSUPPORT; + } + else + { + spi_port->speed_hz = fclk; + } + +#ifdef SPI_USE_DMA + if (SPI_DMA_TRANSFER == spi_port->transtype) + { + SpiMasterInit(mode, TLS_SPI_CS_LOW, fclk); + return TLS_SPI_STATUS_OK; + } +#endif + + spi_port->reconfig = 1; + + return TLS_SPI_STATUS_OK; +} + + +/** + * @brief This function is used to synchronous write command then read data by SPI. + * + * @param[in] txbuf is the write data buffer. + * @param[in] n_tx is the write data length. + * @param[in] rxbuf is the read data buffer. + * @param[in] n_rx is the read data length. + * + * @retval TLS_SPI_STATUS_OK if write success. + * @retval TLS_SPI_STATUS_EINVAL if argument is invalid. + * @retval TLS_SPI_STATUS_ENOMEM if there is no enough memory. + * @retval TLS_SPI_STATUS_ESHUTDOWN if SPI driver does not installed. + * + * @note None + */ +int tls_spi_read_with_cmd(const u8 * txbuf, u32 n_tx, u8 * rxbuf, u32 n_rx) +{ + int status; + struct tls_spi_message message; + struct tls_spi_transfer x[2]; + + if ((txbuf == NULL) || (n_tx == 0) || (rxbuf == NULL) || (n_rx == 0)) + { + return TLS_SPI_STATUS_EINVAL; + } + +#ifdef SPI_USE_DMA + if (SPI_DMA_TRANSFER == spi_port->transtype) + { + if (n_rx > SPI_DMA_BUF_MAX_SIZE || n_tx > SPI_DMA_CMD_MAX_SIZE) + { + TLS_DBGPRT_ERR("\nread length too long\n"); + return TLS_SPI_STATUS_EINVAL; + } + tls_os_sem_acquire(spi_port->lock, 0); + MEMCPY((u8 *) SPI_DMA_CMD_ADDR, txbuf, n_tx); + SpiDmaBlockRead((u8 *) SPI_DMA_BUF_ADDR, n_rx, (u8 *) SPI_DMA_CMD_ADDR, + n_tx); + MEMCPY(rxbuf, (u8 *) SPI_DMA_BUF_ADDR, n_rx); + tls_os_sem_release(spi_port->lock); + return TLS_SPI_STATUS_OK; + } +#endif + + spi_message_init(&message); + + memset(x, 0, sizeof(x)); + if (n_tx) + { + x[0].len = n_tx; + x[0].tx_buf = txbuf; + dl_list_add_tail(&message.transfers, &x[0].transfer_list); + } + if (n_rx) + { + x[1].len = n_rx; + x[1].rx_buf = rxbuf; + dl_list_add_tail(&message.transfers, &x[1].transfer_list); + } + +/* do the i/o. */ + status = tls_spi_sync(&message); + + return status; +} + +/** + * @brief This function is used to synchronous read data by SPI. + * + * @param[in] buf is the buffer for saving SPI data. + * @param[in] len is the data length. + * + * @retval TLS_SPI_STATUS_OK if write success. + * @retval TLS_SPI_STATUS_EINVAL if argument is invalid. + * @retval TLS_SPI_STATUS_ENOMEM if there is no enough memory. + * @retval TLS_SPI_STATUS_ESHUTDOWN if SPI driver does not installed. + * + * @note None + */ +int tls_spi_read(u8 * buf, u32 len) +{ + struct tls_spi_transfer t; + struct tls_spi_message m; + + if ((buf == NULL) || (len == 0)) + { + return TLS_SPI_STATUS_EINVAL; + } + +#ifdef SPI_USE_DMA + if (SPI_DMA_TRANSFER == spi_port->transtype) + { + u32 data32 = 0; + u16 rxBitLen; + u32 rdval1 = 0; + u32 i; + tls_os_sem_acquire(spi_port->lock, 0); + // 鐩存帴浼犺緭锛岃繖鏍峰仛鐨勫師鍥犳槸DMA涓嶈兘杩炵画璇诲彇4涓瓧鑺備互鍐呯殑鏁版嵁,SPI FIFO璇诲彇鍗曚綅涓簑ord + if (len <= 4) + { + SPIM_CHCFG_REG = SPI_CLEAR_FIFOS; + while (SPIM_CHCFG_REG & SPI_CLEAR_FIFOS); + + rxBitLen = 8 * len; + rdval1 = + SPI_FORCE_SPI_CS_OUT | SPI_CS_LOW | SPI_TX_CHANNEL_ON | + SPI_RX_CHANNEL_ON | SPI_CONTINUE_MODE | SPI_START | + SPI_VALID_CLKS_NUM(rxBitLen); + SPIM_CHCFG_REG = rdval1; + spiWaitIdle(); + SPIM_CHCFG_REG |= SPI_CS_HIGH; + + data32 = SPIM_RXDATA_REG; + + for (i = 0; i < len; i++) + { + *(buf + i) = (u8) (data32 >> i * 8); + } + SPIM_CHCFG_REG = 0x00000000; + SPIM_MODECFG_REG = 0x00000000; + } + else // DMA浼犺緭 + { + if (len > SPI_DMA_BUF_MAX_SIZE) + { + TLS_DBGPRT_ERR("\nread len too long\n"); + tls_os_sem_release(spi_port->lock); + return TLS_SPI_STATUS_EINVAL; + } + SpiDmaBlockRead((u8 *) SPI_DMA_BUF_ADDR, len, NULL, 0); + MEMCPY(buf, (u8 *) SPI_DMA_BUF_ADDR, len); + } + tls_os_sem_release(spi_port->lock); + return TLS_SPI_STATUS_OK; + } +#endif + + memset(&t, 0, sizeof(t)); + t.rx_buf = buf; + t.len = len; + + spi_message_init(&m); + + dl_list_add_tail(&m.transfers, &t.transfer_list); + + return tls_spi_sync(&m); +} + +/** + * @brief This function is used to synchronous write data by SPI. + * + * @param[in] buf is the user data. + * @param[in] len is the data length. + * + * @retval TLS_SPI_STATUS_OK if write success. + * @retval TLS_SPI_STATUS_EINVAL if argument is invalid. + * @retval TLS_SPI_STATUS_ENOMEM if there is no enough memory. + * @retval TLS_SPI_STATUS_ESHUTDOWN if SPI driver does not installed. + * + * @note None + */ +int tls_spi_write(const u8 * buf, u32 len) +{ + struct tls_spi_transfer t; + struct tls_spi_message m; + + if ((buf == NULL) || (len == 0)) + { + return TLS_SPI_STATUS_EINVAL; + } + +#ifdef SPI_USE_DMA + if (SPI_DMA_TRANSFER == spi_port->transtype) + { + u32 data32 = 0; + u16 txBitLen; + u32 rdval1 = 0; + u32 i; + tls_os_sem_acquire(spi_port->lock, 0); + if (len <= 4) // 鐩存帴浼犺緭锛岃繖鏍峰仛鐨勫師鍥犳槸DMA涓嶈兘杩炵画浼犺緭灏戜簬4涓瓧鑺傜殑鏁版嵁锛孲PI + { + SPIM_CHCFG_REG = SPI_CLEAR_FIFOS; + while (SPIM_CHCFG_REG & SPI_CLEAR_FIFOS); + for (i = 0; i < len; i++) + { + data32 |= (((u8) (buf[i])) << (i * 8)); + } + SPIM_TXDATA_REG = data32; + txBitLen = 8 * len; + rdval1 = + SPI_FORCE_SPI_CS_OUT | SPI_CS_LOW | SPI_TX_CHANNEL_ON | + SPI_RX_CHANNEL_ON | SPI_CONTINUE_MODE | SPI_START | + SPI_VALID_CLKS_NUM(txBitLen); + SPIM_CHCFG_REG = rdval1; + spiWaitIdle(); + SPIM_CHCFG_REG |= SPI_CS_HIGH; + + SPIM_CHCFG_REG = 0x00000000; + SPIM_MODECFG_REG = 0x00000000; + } + else // DMA浼犺緭 + { + if (len > SPI_DMA_BUF_MAX_SIZE) + { + TLS_DBGPRT_ERR("\nwrite len too long\n"); + tls_os_sem_release(spi_port->lock); + return TLS_SPI_STATUS_EINVAL; + } + MEMCPY((u8 *) SPI_DMA_BUF_ADDR, buf, len); + SpiDmaBlockWrite((u8 *) SPI_DMA_BUF_ADDR, len, 0, 0); + } + tls_os_sem_release(spi_port->lock); + return TLS_SPI_STATUS_OK; + } + +#endif + memset(&t, 0, sizeof(t)); + t.tx_buf = buf; + t.len = len; + + spi_message_init(&m); + + dl_list_add_tail(&m.transfers, &t.transfer_list); + + return tls_spi_sync(&m); +} + +/** + * @brief This function is used to synchronous write 32bit command then write data by SPI. + * + * @param[in] cmd is the command data. + * @param[in] n_cmd is the command len,can not bigger than four + * @param[in] txbuf is the write data buffer. + * @param[in] n_tx is the write data length. + * + * @retval TLS_SPI_STATUS_OK if write success. + * @retval TLS_SPI_STATUS_EINVAL if argument is invalid. + * @retval TLS_SPI_STATUS_ENOMEM if there is no enough memory. + * @retval TLS_SPI_STATUS_ESHUTDOWN if SPI driver does not installed. + * + * @note None + */ +int tls_spi_write_with_cmd(const u8 * cmd, u32 n_cmd, const u8 * txbuf, + u32 n_tx) +{ + int status; + struct tls_spi_message message; + struct tls_spi_transfer x[2]; + + if ((cmd == NULL) || (n_cmd == 0) || (txbuf == NULL) || (n_tx == 0)) + { + return TLS_SPI_STATUS_EINVAL; + } + +#ifdef SPI_USE_DMA + if (SPI_DMA_TRANSFER == spi_port->transtype) + { + if (n_tx > SPI_DMA_BUF_MAX_SIZE) + { + TLS_DBGPRT_ERR("\nwriten len too long\n"); + return TLS_SPI_STATUS_EINVAL; + } + tls_os_sem_acquire(spi_port->lock, 0); + MEMCPY((u8 *) SPI_DMA_BUF_ADDR, (u8 *) cmd, n_cmd); + MEMCPY((u8 *) (SPI_DMA_BUF_ADDR + n_cmd), txbuf, n_tx); + SpiDmaBlockWrite((u8 *) SPI_DMA_BUF_ADDR, (n_cmd + n_tx), 0, 0); + tls_os_sem_release(spi_port->lock); + return TLS_SPI_STATUS_OK; + } +#endif + + spi_message_init(&message); + + memset(x, 0, sizeof(x)); + if (n_cmd) + { + x[0].len = n_cmd; + x[0].tx_buf = (const void *) cmd; + dl_list_add_tail(&message.transfers, &x[0].transfer_list); + } + if (n_tx) + { + x[1].len = n_tx; + x[1].tx_buf = txbuf; + dl_list_add_tail(&message.transfers, &x[1].transfer_list); + } + +/* do the i/o. */ + status = tls_spi_sync(&message); + + return status; +} + +/** + * @brief + * + * @param message + * + * @return + */ +int tls_spi_sync(struct tls_spi_message *message) +{ + int status; + u8 err; + tls_os_sem_t *sem; + + err = tls_os_sem_create(&sem, 0); + if (err != TLS_OS_SUCCESS) + { + TLS_DBGPRT_ERR + ("create spi transaction synchronizing semaphore fail!\n"); + return TLS_SPI_STATUS_ENOMEM; + } + + message->context = (void *) sem; + message->complete = spi_complete; + + status = tls_spi_async(message); + if (status == TLS_SPI_STATUS_OK) + { + TLS_DBGPRT_SPI_INFO("waiting spi transaction finishing!\n"); + tls_os_sem_acquire(sem, 0); + } + + tls_os_sem_delete(sem); + message->context = NULL; + message->complete = NULL; + + return status; +} + +/** + * @brief + * + * @param message + * + * @return + */ +int tls_spi_async(struct tls_spi_message *message) +{ + u8 need_sched; + struct tls_spi_transfer *transfer; + + if (spi_port == NULL) + { + TLS_DBGPRT_ERR("spi master driver module not beed installed!\n"); + return TLS_SPI_STATUS_ESHUTDOWN; + } + + if ((message == NULL) || (dl_list_empty(&message->transfers))) + { + TLS_DBGPRT_ERR("@message is NULL or @message->transfers is empty!\n"); + return TLS_SPI_STATUS_EINVAL; + } + + dl_list_for_each(transfer, &message->transfers, struct tls_spi_transfer, + transfer_list) + { + if (transfer->len == 0) + { + TLS_DBGPRT_ERR("\"@transfer->len\" belong to @message is 0!\n"); + return TLS_SPI_STATUS_EINVAL; + } + } + + tls_os_sem_acquire(spi_port->lock, 0); + + if (dl_list_empty(&spi_port->wait_queue)) + { + need_sched = 1; + } + else + { + need_sched = 0; + } + message->status = SPI_MESSAGE_STATUS_IDLE; + dl_list_add_tail(&spi_port->wait_queue, &message->queue); + + tls_os_sem_release(spi_port->lock); + + if (need_sched == 1) + { + tls_os_queue_send(spi_port->msg_queue, + (void *) SPI_SCHED_MSG_START_ENGINE, 4); + } + + return TLS_SPI_STATUS_OK; +} + + +/** + * @brief This function is used to initialize the SPI master driver. + * + * @param[in] None + * + * @retval TLS_SPI_STATUS_OK if initialize success + * @retval TLS_SPI_STATUS_EBUSY if SPI is already initialized + * @retval TLS_SPI_STATUS_ENOMEM if malloc SPI memory fail + * + * @note None + */ +int tls_spi_init(void) +{ + u8 err; + struct tls_spi_port *port; + + + if (spi_port != NULL) + { + TLS_DBGPRT_ERR("spi driver module has been installed!\n"); + return TLS_SPI_STATUS_EBUSY; + } + + TLS_DBGPRT_SPI_INFO("initialize spi master driver module.\n"); + + port = (struct tls_spi_port *) tls_mem_alloc(sizeof(struct tls_spi_port)); + if (port == NULL) + { + TLS_DBGPRT_ERR("allocate \"struct tls_spi_port\" fail!\n"); + return TLS_SPI_STATUS_ENOMEM; + } + + err = tls_os_sem_create(&port->lock, 1); + if (err != TLS_OS_SUCCESS) + { + TLS_DBGPRT_ERR("create semaphore @spi_port->lock fail!\n"); + tls_mem_free(port); + return TLS_SPI_STATUS_ENOMEM; + } + + err = tls_os_queue_create(&port->msg_queue, MSG_QUEUE_SIZE); + if (err != TLS_OS_SUCCESS) + { + TLS_DBGPRT_ERR("create message queue @spi_port->msg_queue fail!\n"); + tls_os_sem_delete(port->lock); + tls_mem_free(port); + return TLS_SPI_STATUS_ENOMEM; + } + + err = tls_os_task_create(NULL, "hostspi", + spi_scheduler, + (void *) spi_port, + (void *) &spi_scheduler_stk, + SPI_SCHEDULER_STK_SIZE * sizeof(u32), + TLS_SPI_SCHEDULER_TASK_PRIO, 0); + if (err != TLS_OS_SUCCESS) + { + TLS_DBGPRT_ERR("create spi master driver scheduler task fail!\n"); + tls_os_sem_delete(port->lock); + tls_os_queue_delete(port->msg_queue); + tls_mem_free(port); + return TLS_SPI_STATUS_ENOMEM; + } + + port->speed_hz = SPI_DEFAULT_SPEED; /* 榛樿2M */ + port->cs_active = SPI_CS_ACTIVE_MODE; + port->mode = SPI_DEFAULT_MODE; /* CPHA = 0,CPOL = 0 */ + port->reconfig = 0; + + dl_list_init(&port->wait_queue); + + port->current_message = NULL; + port->current_remaining_transfer = 0; + port->current_transfer = NULL; + port->current_remaining_bytes = 0; + + spi_port = port; + + TLS_DBGPRT_SPI_INFO("initialize spi master controller.\n"); + + spi_clear_fifo(); + spi_set_endian(1); + tls_spi_trans_type(SPI_BYTE_TRANSFER); + spi_set_mode(spi_port->mode); + spi_set_chipselect_mode(SPI_CS_INACTIVE_MODE); /* cs=1 ,鐗囬夋棤鏁 */ + spi_force_cs_out(1); /* 鐗囬夌敱杞欢鎺у埗 */ + spi_set_sclk(spi_port->speed_hz); + + spi_set_tx_trigger_level(0); + spi_set_rx_trigger_level(7); + + spi_set_rx_channel(1); + spi_set_tx_channel(1); + spi_unmask_int(SPI_INT_TRANSFER_DONE /* | SPI_INT_RX_FIFO_RDY |SPI_INT_TX_FIFO_RDY */ ); + + + TLS_DBGPRT_SPI_INFO("register spi master interrupt handler.\n"); + + tls_irq_enable(SPI0_INT); + + TLS_DBGPRT_SPI_INFO("spi master driver module initialization finish.\n"); + + return TLS_SPI_STATUS_OK; +} + +/** + * @brief + * + * @return + */ +int tls_spi_exit(void) +{ + TLS_DBGPRT_SPI_INFO("Not support spi master driver module uninstalled!\n"); + return TLS_SPI_STATUS_EPERM; +} + + + +/********************************************************************************************************** +* Description: This function is used to select SPI slave type. +* +* Arguments : slave is the slave type,defined as follow: +* slave == SPI_SLAVE_FLASH :flash +* slave == SPI_SLAVE_CARD : sd card +* +* Returns : Before communicate with different SPI device, must call the function. +**********************************************************************************************************/ +void tls_spi_slave_sel(u16 slave) +{ +// u16 ret; +/*gpio0鎺у埗cs淇″彿*/ + tls_gpio_cfg((enum tls_io_name) SPI_SLAVE_CONTROL_PIN, WM_GPIO_DIR_OUTPUT, + WM_GPIO_ATTR_FLOATING); + if (SPI_SLAVE_FLASH == slave) + { + tls_gpio_write((enum tls_io_name) SPI_SLAVE_CONTROL_PIN, 0); + // ret = tls_gpio_read(SPI_SLAVE_CONTROL_PIN); + // printf("\nflash gpio 0 ===%d\n",ret); + } + else if (SPI_SLAVE_CARD == slave) + { + tls_gpio_write((enum tls_io_name) SPI_SLAVE_CONTROL_PIN, 1); + // ret = tls_gpio_read(SPI_SLAVE_CONTROL_PIN); + // printf("\ncard gpio 0 ===%d\n",ret); + } +} diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_hspi.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_hspi.c new file mode 100644 index 00000000..91567de9 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_hspi.c @@ -0,0 +1,493 @@ +/** + * @file wm_hspi.c + * + * @brief High speed spi slave Module + * + * @author dave + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ + +#include +#include +#include +#include "wm_hspi.h" +#include "wm_regs.h" +#include "wm_config.h" +#include "wm_mem.h" +#include "wm_osal.h" +#include "wm_irq.h" +#include "lwip/mem.h" +#include "wm_io.h" + +#if TLS_CONFIG_HS_SPI + +struct tls_slave_hspi g_slave_hspi; +#define SET_BIT(x) (1UL << (x)) +void hspi_free_rxdesc(struct tls_hspi_rx_desc *rx_desc); + + +void hspi_rx_init(struct tls_slave_hspi *hspi) +{ + struct tls_hspi_rx_desc *hspi_rx_desc; + int i; + +/* set current availble rx desc pointer */ + hspi_rx_desc = (struct tls_hspi_rx_desc *) HSPI_RX_DESC_BASE_ADDR; + hspi->curr_rx_desc = hspi_rx_desc; + +/* initialize rx descriptor content */ + for (i = 0; i < HSPI_RX_DESC_NUM; i++) + { + /* initialize tx descriptors */ + if (i < HSPI_RXBUF_NUM) + { + hspi_rx_desc->valid_ctrl = SET_BIT(31); + hspi_rx_desc->buf_addr = HSPI_RXBUF_BASE_ADDR + i * HSPI_RXBUF_SIZE; + } + else + { + /* indicate this descriptor is can't use by hspi */ + hspi_rx_desc->valid_ctrl = 0; + /* point to null */ + hspi_rx_desc->buf_addr = 0x0; + } + + if (i == (HSPI_RX_DESC_NUM - 1)) + { + hspi_rx_desc->next_desc_addr = (u32) HSPI_RX_DESC_BASE_ADDR; + } + else + { + hspi_rx_desc->next_desc_addr = (u32) (hspi_rx_desc + 1); + } + hspi_rx_desc++; + } +} + +void hspi_tx_init(struct tls_slave_hspi *hspi) +{ + struct tls_hspi_tx_desc *hspi_tx_desc; + int i; + + hspi_tx_desc = (struct tls_hspi_tx_desc *) HSPI_TX_DESC_BASE_ADDR; + + hspi->curr_tx_desc = hspi_tx_desc; + + for (i = 0; i < HSPI_TX_DESC_NUM; i++) + { + hspi_tx_desc->valid_ctrl = 0; + hspi_tx_desc->buf_info = 0; +#if HSPI_TX_MEM_MALLOC + hspi_tx_desc->txbuf_addr = NULL; + hspi_tx_desc->buf_addr[0] = 0; +#else + hspi_tx_desc->buf_addr[0] = HSPI_TXBUF_BASE_ADDR + i * HSPI_TXBUF_SIZE; +#endif + hspi_tx_desc->buf_addr[1] = 0; + hspi_tx_desc->buf_addr[2] = 0; + if (i == (HSPI_TX_DESC_NUM - 1)) + { + hspi_tx_desc->next_desc_addr = (u32) HSPI_TX_DESC_BASE_ADDR; + } + else + { + hspi_tx_desc->next_desc_addr = (u32) (hspi_tx_desc + 1); + } + hspi_tx_desc++; + } + +} + +static int slave_spi_rx_data(struct tls_slave_hspi *hspi) +{ + struct tls_hspi_rx_desc *rx_desc; + +/* get rx descriptor */ + rx_desc = hspi->curr_rx_desc; + + while (!(rx_desc->valid_ctrl & SET_BIT(31))) + { + if (hspi->rx_data_callback) + hspi->rx_data_callback((char *) rx_desc->buf_addr); + hspi_free_rxdesc(rx_desc); + + rx_desc = (struct tls_hspi_rx_desc *) rx_desc->next_desc_addr; + hspi->curr_rx_desc = rx_desc; + } + + return 0; + +} + + +void SDIO_RX_IRQHandler(void) +{ + struct tls_slave_hspi *hspi = (struct tls_slave_hspi *) &g_slave_hspi; + +#if HSPI_TX_MEM_MALLOC + hspi->txdoneflag = 1; +#endif + if (hspi->tx_data_callback) + hspi->tx_data_callback((char *) hspi->curr_tx_desc->buf_addr); +/* clear interrupt */ + tls_reg_write32(HR_SDIO_INT_SRC, SDIO_WP_INT_SRC_DATA_UP); +} + +void SDIO_TX_IRQHandler(void) +{ + struct tls_slave_hspi *hspi = (struct tls_slave_hspi *) &g_slave_hspi; + +//鐢ㄦ埛妯″紡涓嬶紝鐩存帴缁欏嚭鏁版嵁锛岄摼琛ㄧ殑鎿嶄綔涓嶅澶栧紑鏀撅紝閬垮厤閫犳垚閾捐〃鎿嶄綔閿欒 + if (hspi->ifusermode) + { + slave_spi_rx_data(hspi); + } + else + { + if (hspi->rx_data_callback) + hspi->rx_data_callback((char *) hspi->curr_rx_desc->buf_addr); + } + +/* clear interrupt */ + tls_reg_write32(HR_SDIO_INT_SRC, SDIO_WP_INT_SRC_DATA_DOWN); +} + + +void SDIO_TX_CMD_IRQHandler(void) +{ + struct tls_slave_hspi *hspi = (struct tls_slave_hspi *) &g_slave_hspi; + + if (hspi->rx_cmd_callback) + hspi->rx_cmd_callback((char *) SDIO_CMD_RXBUF_ADDR); + + if (hspi->ifusermode) // 鐢ㄦ埛妯″紡涓嬶紝鏁版嵁缁欏嚭鍘讳箣鍚庯紝瀵勫瓨鍣ㄧ敱椹卞姩鑷繁鎿嶄綔 + { + tls_reg_write32(HR_SDIO_DOWNCMDVALID, 0x1); + } + +/* clear interrupt */ + tls_reg_write32(HR_SDIO_INT_SRC, SDIO_WP_INT_SRC_CMD_DOWN); +} + + +void SPI_HS_IRQHandler(void) +{ + printf("spi HS irqhandle\n"); +} + +void hspi_free_rxdesc(struct tls_hspi_rx_desc *rx_desc) +{ + rx_desc->valid_ctrl = SET_BIT(31); +/* 璁剧疆hspi/sdio tx enable瀵勫瓨鍣紝璁﹕dio纭欢鐭ラ亾鏈夊彲鐢ㄧ殑tx descriptor */ + tls_reg_write32(HR_SDIO_TXEN, SET_BIT(0)); +} + + +void hspi_regs_cfg(void) +{ + tls_reg_write32(HR_HSPI_CLEAR_FIFO, 0x1); /* Clear data up&down interrput + */ + tls_reg_write32(HR_HSPI_SPI_CFG, 0); /* CPOL=0, CPHA=0, Small-Endian */ + tls_reg_write32(HR_HSPI_MODE_CFG, 0x0); + tls_reg_write32(HR_HSPI_INT_MASK, 0x03); + tls_reg_write32(HR_HSPI_INT_STTS, 0x03); +} + +void sdio_init_cis(void) +{ + tls_reg_write32(FN0_TPL_FUNCID, 0x000C0221); + tls_reg_write32(FN0_TPL_FUNCE, 0x00000422); + tls_reg_write32(FN0_TPL_FUNCE_MAXBLK, 0x04203208); + tls_reg_write32(FN0_TPL_MANFID_MID, 0x53470296); + tls_reg_write32(FN0_TPL_END, 0x000000ff); + + tls_reg_write32(FN1_TPL_FUNCID, 0x000C0221); + tls_reg_write32(FN1_TPL_FUNCE, 0x01012a22); + tls_reg_write32(FN1_TPL_FUNCE_VER, 0x00000011); + tls_reg_write32(FN1_TPL_FUNCE_NSN, 0x02000000); + tls_reg_write32(FN1_TPL_FUNCE_CSASIZE, 0x08000300); + tls_reg_write32(FN1_TPL_FUNCE_OCR, 0x00FF8000); + tls_reg_write32(FN1_TPL_FUNCE_MINPWR, 0x010f0a08); + tls_reg_write32(FN1_TPL_FUNCE_STANDBY, 0x00000101); + tls_reg_write32(FN1_TPL_FUNCE_OPTBW, 0x00000000); + tls_reg_write32(FN1_TPL_FUNCE_NTIMEOUT, 0x00000000); + tls_reg_write32(FN1_TPL_FUNCE_AVGPWR, 0x00000000); + tls_reg_write32(FN1_TPL_FUNCE_AVGPWR + 4, 0x00000000); + tls_reg_write32(FN1_TPL_END, 0x000000ff); +} + +void hsdio_regs_cfg(void) +{ + u32 v; + + sdio_init_cis(); + tls_reg_write32(HR_SDIO_CIS0, SDIO_CIS0_ADDR - 0x1000); + tls_reg_write32(HR_SDIO_CIS1, SDIO_CIS1_ADDR - 0x2000); + + v = tls_reg_read32(HR_SDIO_CIA); + tls_reg_write32(HR_SDIO_CIA, (v & 0xFFFFF000) | 0x232); + +/* set sdio ready */ + tls_reg_write32(HR_SDIO_PROG, 0x02FD); +} + + +/** + * @brief This function is used to initial HSPI register. + * + * @param[in] None + * + * @retval 0 success + * @retval other failed + * + * @note When the system is initialized, the function has been called, so users can not call the function. + */ +int tls_slave_spi_init(void) +{ + struct tls_slave_hspi *hspi; + + hspi = &g_slave_hspi; + memset(hspi, 0, sizeof(struct tls_slave_hspi)); + + hspi_rx_init(hspi); + hspi_tx_init(hspi); +// tls_set_high_speed_interface_type(HSPI_INTERFACE_SPI); +/* regiseter hspi tx rx cmd interrupt handler */ + +/* setting hw interrupt module isr enable regiset */ + tls_irq_enable(SDIO_TX_DATA_INT); + tls_irq_enable(SDIO_RX_DATA_INT); + tls_irq_enable(SDIO_TX_CMD_INT); + tls_irq_enable(SPI1_INT); + + /******************************************** + * setting hspi wrapper registers + *********************************************/ +/* hspi data down(rx) */ + tls_reg_write32(HR_SDIO_TXBD_ADDR, HSPI_RX_DESC_BASE_ADDR); + tls_reg_write32(HR_SDIO_TXBD_LINKEN, 1); + tls_reg_write32(HR_SDIO_TXEN, 1); +/* hspi data up (tx) */ + tls_reg_write32(HR_SDIO_RXBD_ADDR, HSPI_TX_DESC_BASE_ADDR); + tls_reg_write32(HR_SDIO_RXBD_LINKEN, 1); + +/* hspi cmd down */ + tls_reg_write32(HR_SDIO_CMD_ADDR, SDIO_CMD_RXBUF_ADDR); + tls_reg_write32(HR_SDIO_CMD_SIZE, SDIO_CMD_RXBUF_SIZE); + tls_reg_write32(HR_SDIO_DOWNCMDVALID, 0x1); + +/* enable sdio module register */ + tls_reg_write32(HR_SDIO_INT_MASK, 0x00); + + return 0; +} + + +/** + * @brief This function is used to set high speed interface type. + * + * @param[in] type is the interface type. HSPI_INTERFACE_SPI or HSPI_INTERFACE_SDIO + * + * @return None + * + * @note None + */ +void tls_set_high_speed_interface_type(int type) +{ + + + if (HSPI_INTERFACE_SPI == type) + { +#if 0 +#if (HSPI_IO_REUSE_NUM == 0) + tls_io_cfg_set(WM_IO_PB_14, WM_IO_OPTION1); + tls_io_cfg_set(WM_IO_PB_15, WM_IO_OPTION1); + tls_io_cfg_set(WM_IO_PB_16, WM_IO_OPTION1); + tls_io_cfg_set(WM_IO_PB_17, WM_IO_OPTION1); + tls_io_cfg_set(WM_IO_PB_18, WM_IO_OPTION1); +#else + if(WM_IO_OPTION1 == tls_io_cfg_get(WM_IO_PB_14)) + tls_io_cfg_set(WM_IO_PB_14, WM_IO_OPTION5); + if(WM_IO_OPTION1 == tls_io_cfg_get(WM_IO_PB_15)) + tls_io_cfg_set(WM_IO_PB_15, WM_IO_OPTION5); + if(WM_IO_OPTION1 == tls_io_cfg_get(WM_IO_PB_16)) + tls_io_cfg_set(WM_IO_PB_16, WM_IO_OPTION5); + if(WM_IO_OPTION1 == tls_io_cfg_get(WM_IO_PB_17)) + tls_io_cfg_set(WM_IO_PB_17, WM_IO_OPTION5); + if(WM_IO_OPTION1 == tls_io_cfg_get(WM_IO_PB_18)) + tls_io_cfg_set(WM_IO_PB_18, WM_IO_OPTION5); + tls_io_cfg_set(WM_IO_PB_08, WM_IO_OPTION2); + tls_io_cfg_set(WM_IO_PB_09, WM_IO_OPTION2); + tls_io_cfg_set(WM_IO_PB_10, WM_IO_OPTION2); + tls_io_cfg_set(WM_IO_PB_11, WM_IO_OPTION2); + tls_io_cfg_set(WM_IO_PB_12, WM_IO_OPTION2); +#endif +#endif + hspi_regs_cfg(); + } + else if (HSPI_INTERFACE_SDIO == type) + { +#if 0 + if(WM_IO_OPTION1 == tls_io_cfg_get(WM_IO_PB_16)) //HSPI_CK,as sdio need close + tls_io_cfg_set(WM_IO_PB_16, WM_IO_OPTION5); + if(WM_IO_OPTION2 == tls_io_cfg_get(WM_IO_PB_08)) //HSPI_CK,as sdio need close + tls_io_cfg_set(WM_IO_PB_08, WM_IO_OPTION5); + tls_io_cfg_set(WM_IO_PB_08, WM_IO_OPTION3); + tls_io_cfg_set(WM_IO_PB_09, WM_IO_OPTION3); + tls_io_cfg_set(WM_IO_PB_10, WM_IO_OPTION3); + tls_io_cfg_set(WM_IO_PB_11, WM_IO_OPTION3); + tls_io_cfg_set(WM_IO_PB_12, WM_IO_OPTION3); +#if (SDIO_IO_REUSE_NUM == 0) + tls_io_cfg_set(WM_IO_PA_06, WM_IO_OPTION3); +#elif (SDIO_IO_REUSE_NUM == 1) + tls_io_cfg_set(WM_IO_PB_07, WM_IO_OPTION3); +#else + tls_io_cfg_set(WM_IO_PB_13, WM_IO_OPTION4); +#endif +#endif + hsdio_regs_cfg(); + } +} + +/** + * @brief This function is used to enable or disable user mode. + * + * @param[in] ifenable TRUE or FALSE + * + * @return None + * + * @note If the user enables the user mode, RICM instruction in the system will not be used by SPI. + * If the user wants to use the SPI interface as other use, need to enable the user mode. + * This function must be called before the register function. + */ +void tls_set_hspi_user_mode(u8 ifenable) +{ + struct tls_slave_hspi *hspi = &g_slave_hspi; + + hspi->ifusermode = ifenable; + + if (ifenable) + { + hspi->rx_cmd_callback = NULL; + hspi->rx_data_callback = NULL; + hspi->tx_data_callback = NULL; + } +} + +/** + * @brief This function is used to register hspi rx command interrupt. + * + * @param[in] rx_cmd_callback is the hspi rx interrupt call back function. + * + * @return None + * + * @note None + */ + void tls_hspi_rx_cmd_callback_register(s16(*rx_cmd_callback) (char *buf)) +{ + g_slave_hspi.rx_cmd_callback = rx_cmd_callback; +} + +/** + * @brief This function is used to register hspi rx data interrupt. + * + * @param[in] rx_data_callback is the hspi rx interrupt call back function. + * + * @return None + * + * @note None + */ +void tls_hspi_rx_data_callback_register(s16(*rx_data_callback) (char *buf)) +{ + g_slave_hspi.rx_data_callback = rx_data_callback; +} + +/** + * @brief This function is used to register hspi tx data interrupt. + * + * @param[in] tx_data_callback is the hspi tx interrupt call back function. + * + * @return None + * + * @note None + */ +void tls_hspi_tx_data_callback_register(s16(*tx_data_callback) (char *buf)) +{ + g_slave_hspi.tx_data_callback = tx_data_callback; +} + +/** + * @brief This function is used to transfer data. + * + * @param[in] txbuf is a buf for saving user data. + * @param[in] len is the data length. + * + * @retval transfer data len success + * @retval 0 failed + * + * @note None + */ +int tls_hspi_tx_data(char *txbuf, int len) +{ + struct tls_hspi_tx_desc *tx_desc; + int totallen = len; + int txlen; + + if (NULL == txbuf || len <= 0 || len > (HSPI_TXBUF_SIZE * HSPI_TX_DESC_NUM)) + { + printf("\nhspi tx param error\n"); + return 0; + } + tx_desc = g_slave_hspi.curr_tx_desc; + while (1) + { + // printf("---\n"); + if ((tx_desc->valid_ctrl & SET_BIT(31)) == 0) + break; + tls_os_time_delay(1); + } + while (!(tx_desc->valid_ctrl & SET_BIT(31))) + { + txlen = (totallen > HSPI_TXBUF_SIZE) ? HSPI_TXBUF_SIZE : totallen; +#if HSPI_TX_MEM_MALLOC + if (tx_desc->txbuf_addr != NULL) + { + printf("\nhspi txbuf not null,error %x\n", tx_desc->txbuf_addr); + if (tx_desc->txbuf_addr == tx_desc->buf_addr[0]) + { + mem_free((void *) tx_desc->txbuf_addr); + tx_desc->txbuf_addr = NULL; + } + else // 涓嶅簲璇ュ嚭鐜 + { + printf("\nhspi tx mem error\n"); + break; + } + } + + tx_desc->txbuf_addr = (u32) mem_malloc(txlen + 1); + if (NULL == tx_desc->txbuf_addr) + { + printf("\nhspi tx data malloc error\n"); + break; + } + tx_desc->buf_addr[0] = tx_desc->txbuf_addr; +#endif + MEMCPY((char *) tx_desc->buf_addr[0], txbuf, txlen); + tx_desc->buf_info = txlen << 12; + tx_desc->valid_ctrl = SET_BIT(31); + tls_reg_write32(HR_SDIO_RXEN, 0x01); + tx_desc = (struct tls_hspi_tx_desc *) tx_desc->next_desc_addr; + g_slave_hspi.curr_tx_desc = tx_desc; + totallen -= txlen; + if (totallen <= 0) + break; + } + + return (len - totallen); +} + +#endif + + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_i2c.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_i2c.c new file mode 100644 index 00000000..8e190aaf --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_i2c.c @@ -0,0 +1,319 @@ +/**************************************************************************//** + * @file wm_i2c.c + * @author + * @version + * @date + * @brief + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. All rights reserved. + *****************************************************************************/ + +#include +#include +#include +#include "wm_regs.h" +#include "wm_i2c.h" +#include "wm_cpu.h" +#include "wm_irq.h" + +#define I2C_FREQ_MAX (400000) +#define I2C_FREQ_MIN (100000) +#define I2C_WRITE (0x80) +#define I2C_READ (0x00) +typedef struct { + uint8_t addr; + uint8_t dev_addr; + uint8_t state; + uint8_t *buf; + uint16_t len; + uint16_t cnt; + uint8_t cmd; + void (*transfer_done)(void); +} i2c_desc; +enum { + START, + RESTART, + TRANSMIT, + PRERECEIVE, + RECEIVE, + STOP, + DONE, + IDLE, +}; +static i2c_desc i2c_transfer; + +void tls_i2c_init(u32 freq) +{ + u32 div = 0; + tls_sys_clk clk; + + if (freq < I2C_FREQ_MIN) + { + freq = I2C_FREQ_MIN; + } + else if (freq > I2C_FREQ_MAX) + { + freq = I2C_FREQ_MAX; + } + tls_sys_clk_get(&clk); + + div = (clk.apbclk * 1000000)/(5 * freq) - 1; + tls_reg_write32(HR_I2C_PRER_LO, div & 0xff); + tls_reg_write32(HR_I2C_PRER_HI, (div>>8) & 0xff); + + /** enable I2C | Disable Int*/ + tls_reg_write32(HR_I2C_CTRL, I2C_CTRL_INT_DISABLE | I2C_CTRL_ENABLE); + tls_irq_enable(I2C_IRQn); +} + +/** + * @brief send stop signal + * + */ +void tls_i2c_stop(void) +{ + tls_reg_write32(HR_I2C_CR_SR, I2C_CR_STO); + while(tls_reg_read32(HR_I2C_CR_SR) & I2C_SR_TIP); +} + +/** + * @brief waiting for ack signal + * @retval + * - \ref WM_FAILED + * - \ref WM_SUCCESS + */ +int tls_i2c_wait_ack(void) +{ + u16 errtime=0; + u32 value; + + while(tls_reg_read32(HR_I2C_CR_SR) & I2C_SR_TIP); + value = tls_reg_read32(HR_I2C_CR_SR); + while(value & I2C_SR_NAK) + { + errtime ++; + if(errtime > 512) + { + printf("wait ack err\n"); + tls_i2c_stop(); + return WM_FAILED; + } + value = tls_reg_read32(HR_I2C_CR_SR); + } + + return WM_SUCCESS; +} + + +/** + * @brief writes the data to data register of I2C module + * when \ifstart one the start signal will be sent followed by the \data + * when \ifstart zero only the \data will be send + * @param[in] data the data will be write to the data register of I2C module + * @param[in] ifstart when one send start signal, when zero don't + * @retval + * + */ +void tls_i2c_write_byte(u8 data,u8 ifstart) +{ + tls_reg_write32(HR_I2C_TX_RX, data); + if(ifstart) + tls_reg_write32(HR_I2C_CR_SR, I2C_CR_STA | I2C_CR_WR); + else + tls_reg_write32(HR_I2C_CR_SR, I2C_CR_WR); + while(tls_reg_read32(HR_I2C_CR_SR) & I2C_SR_TIP); +} + + +/** + * @brief get the data stored in data register of I2C module + * @param[in] ifack when one send ack after reading the data register,when zero don't + * @param[in] ifstop when one send stop signal after read, when zero do not send stop + * @retval the received data + */ +u8 tls_i2c_read_byte(u8 ifack,u8 ifstop) +{ + u8 data; + u32 value = I2C_CR_RD; + + if(!ifack) + value |= I2C_CR_NAK; + if(ifstop) + value |= I2C_CR_STO; + + tls_reg_write32(HR_I2C_CR_SR, value); + /** Waiting finish */ + while(tls_reg_read32(HR_I2C_CR_SR) & I2C_SR_TIP); + data = tls_reg_read32(HR_I2C_TX_RX); + + return data; +} + +/** + * @brief start write through int mode + * @param[in] devaddr the device address + * @param[in] wordaddr when one send stop signal after read, when zero do not send stop + * @param[in] buf the address point where data shoule be stored + * @param[in] len the length of data will be received + * @retval + * - \ref WM_FAILED + * - \ref WM_SUCCESS + */ +int wm_i2c_start_write_it(uint8_t devaddr, uint8_t wordaddr, uint8_t * buf, uint16_t len) +{ + if (buf == NULL) + { + return WM_FAILED; + } + I2C->TX_RX = devaddr; + i2c_transfer.dev_addr = devaddr; + i2c_transfer.state = START; + i2c_transfer.cmd = I2C_WRITE; + i2c_transfer.buf = buf; + i2c_transfer.len = len; + i2c_transfer.cnt = 0; + i2c_transfer.addr = wordaddr; + I2C->CR_SR = I2C_CR_STA | I2C_CR_WR; + return WM_SUCCESS; +} + +/** + * @brief start read through int mode + * @param[in] devaddr the device address + * @param[in] wordaddr when one send stop signal after read, when zero do not send stop + * @param[in] buf the address point where data shoule be stored + * @param[in] len the length of data will be received + * @retval + * - \ref WM_FAILED + * - \ref WM_SUCCESS + */ +int wm_i2c_start_read_it(uint8_t devaddr, uint8_t wordaddr, uint8_t * buf, uint16_t len) +{ + if (buf == NULL) + { + return WM_FAILED; + } + I2C->TX_RX = devaddr; + i2c_transfer.dev_addr = devaddr; + i2c_transfer.state = START; + i2c_transfer.cmd = I2C_READ; + i2c_transfer.buf = buf; + i2c_transfer.len = len; + i2c_transfer.cnt = 0; + i2c_transfer.addr = wordaddr; + I2C->CR_SR = I2C_CR_STA | I2C_CR_WR; + + return WM_SUCCESS; +} + +/** + * @brief This function is used to register i2c transfer done callback function. + * @param[in] done is the i2c transfer done callback function. + * @retval None + * @note None + */ +void wm_i2c_transfer_done_register(void (*done)(void)) +{ + i2c_transfer.transfer_done = done; +} + + +void I2C_IRQHandler(void) +{ + int i2c_sr; + i2c_sr = I2C->CR_SR; + I2C->CR_SR = 1; + if (i2c_sr & 0x20) + { + printf("I2C AL lost\r\n"); + } + if (i2c_sr & 0x01) + { + if ((i2c_sr & 0x80) == 0) + { + switch(i2c_transfer.state) + { + case START: + I2C->TX_RX = i2c_transfer.addr; + I2C->CR_SR = I2C_CR_WR; + if ((i2c_transfer.cmd & I2C_WRITE) == I2C_WRITE) + { + i2c_transfer.state = TRANSMIT; + } + else + { + i2c_transfer.state = RESTART; + } + break; + + case RESTART: + I2C->TX_RX = (i2c_transfer.dev_addr | 0x01); + I2C->CR_SR = (I2C_CR_STA | I2C_CR_WR); + i2c_transfer.state = PRERECEIVE; + break; + + case TRANSMIT: + I2C->TX_RX = i2c_transfer.buf[i2c_transfer.cnt++]; + I2C->CR_SR = I2C_CR_WR; + if (i2c_transfer.cnt == i2c_transfer.len) + { + i2c_transfer.state = STOP; + } + break; + + case PRERECEIVE: + i2c_transfer.state = RECEIVE; + I2C->CR_SR = I2C_CR_RD; + break; + case RECEIVE: + i2c_transfer.buf[i2c_transfer.cnt++] = I2C->TX_RX; + if (i2c_transfer.cnt == (i2c_transfer.len - 1)) + { + I2C->CR_SR = (I2C_CR_STO | I2C_CR_NAK | I2C_CR_RD); + i2c_transfer.state = STOP; + } + else if (i2c_transfer.len == 1) + { + I2C->CR_SR = (I2C_CR_STO | I2C_CR_NAK | I2C_CR_RD); + i2c_transfer.state = DONE; + if (i2c_transfer.transfer_done) + { + i2c_transfer.transfer_done(); + } + } + else + { + I2C->CR_SR = I2C_CR_RD; + } + break; + + case STOP: + I2C->CR_SR = I2C_CR_STO; + i2c_transfer.state = DONE; + if (i2c_transfer.transfer_done) + { + i2c_transfer.transfer_done(); + } + break; + } + } + else + { + if ((i2c_transfer.state == STOP) && i2c_transfer.cmd != I2C_WRITE) + { + i2c_transfer.buf[i2c_transfer.cnt] = I2C->TX_RX; + i2c_transfer.state = DONE; + if (i2c_transfer.transfer_done) + { + i2c_transfer.transfer_done(); + } + } + } + } +// if ((i2c_sr & 0x40) == 0) +// { +// i2c_transfer.state = IDLE; +// } +} + +/*** (C) COPYRIGHT 2014 Winner Microelectronics Co., Ltd. ***/ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_i2s.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_i2s.c new file mode 100644 index 00000000..272b902e --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_i2s.c @@ -0,0 +1,584 @@ +/**************************************************************************//** + * @file wm_i2s.c + * @author + * @version + * @date + * @brief + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. All rights reserved. + *****************************************************************************/ + +#define TLS_CONFIG_I2S 1 + +#if TLS_CONFIG_I2S + +#include "wm_i2s.h" +#include "string.h" +#include "wm_debug.h" +#include "wm_irq.h" +#include "wm_config.h" +#include "wm_mem.h" + +#define I2S_CLK (160000000) + +#define WM_I2S_FIFO_LEN (8) +static tls_i2s_port_t tls_i2s_port; + +static void tls_i2s_fill_txfifo(void); + +/** + * @brief This function is used to initial i2s port. + * @param[in] opts the i2s setting options,if this param is NULL,this function will use the default options. + * @retval + * - \ref WM_SUCCESS + * - \ref WM_FAILED + * + */ +int tls_i2s_port_init(tls_i2s_options_t *opts) +{ + tls_i2s_options_t opt; + + tls_i2s_port.regs = I2S; + + if(NULL == opts) + { + memset(&opt, 0, sizeof(tls_i2s_options_t)); + opt.data_width = I2S_CTRL_DATABIT_16; + opt.format = I2S_CTRL_FORMAT_I2S; + opt.stereo_mono = I2S_CTRL_STERO; + opt.sample_rate = 8000; + opt.tx_en = 1; + tls_i2s_config(&opt); + } + else + { + tls_i2s_config(opts); + } + /* enable i2s interrupt */ + NVIC_ClearPendingIRQ(I2S_IRQn); + tls_irq_enable(I2S_INT); + + return WM_SUCCESS; +} + +/** + * @brief This function is used to initial i2s port. + * @param[in] opts the i2s setting options,if this param is NULL,this function will use the default options. + * + * @retval + * + * @note + */ +void tls_i2s_config(tls_i2s_options_t *opts) +{ + tls_i2s_port.regs->CTRL &= ~(I2S_CTRL_FORMAT_MASK | \ + I2S_CTRL_DATABIT_MASK | \ + I2S_CTRL_STEREO_MONO_MASK); + tls_i2s_port.regs->CTRL = opts->data_width | opts->format | opts->stereo_mono; + if (opts->rx_en) + { + TLS_I2S_RX_ENABLE(); + TLS_I2S_RX_FIFO_CLEAR(); + } + if (opts->tx_en) + { + TLS_I2S_TX_ENABLE(); + TLS_I2S_TX_FIFO_CLEAR(); + } + tls_i2s_set_freq(opts->sample_rate); +} + +/** + * @brief + * set the frequency of the i2s port. + * + * @param[in] freq + * the required frequency of the i2s module + * + * @retval + * + */ +void tls_i2s_set_freq(uint32_t freq) +{ + uint32_t div; + uint32_t reg; + uint8_t width, stereo; + + reg = I2S->CTRL; + width = (((reg>>4)&0x03)+1)<<3; + stereo = tls_bitband_read(HR_I2S_CTRL, I2S_CTRL_STEREO_MONO_Pos) ? 1:2; + div = (I2S_CLK + freq * width * stereo)/(freq * width * stereo) - 1; + + *(volatile uint32_t *)HR_CLK_I2S_CTL &= ~0xFF00; + *(volatile uint32_t *)HR_CLK_I2S_CTL |= (uint32_t)div<<8; +} + +/** + * @brief + * set the frequency of the i2s port. + * + * @param[in] freq + * the required frequency of the i2s module + * @param[in] exclk + * the frequency of the ext clock + * + * @retval + * + * @note + * this function will be called after tls_i2s_port_init function + */ +void wm_i2s_set_freq_exclk(uint32_t freq, uint32_t exclk) +{ + uint32_t div; + uint32_t temp; + uint8_t wdwidth, stereo; + temp = I2S->CTRL; + wdwidth = (((temp>>4)&0x03)+1)<<3; + stereo = tls_bitband_read(HR_I2S_CTRL, 22) ? 1:2; + div = (exclk * 2 + freq * wdwidth * stereo)/(2* freq * wdwidth * stereo) - 1; + *(volatile uint32_t *)0x40000718 &= ~0x3FF00; + *(volatile uint32_t *)0x40000718 |= (uint32_t)div<<8; + *(volatile uint32_t *)0x40000718 |= 0x01; +} +void I2S_IRQHandler(void) +{ + uint8_t rx_fifocnt; + + /** LZC */ + if (tls_bitband_read(HR_I2S_INT_SRC, I2S_FLAG_LZC_Pos) && !tls_bitband_read(HR_I2S_INT_MASK, I2S_FLAG_LZC_Pos)) + { + tls_reg_write32(HR_I2S_INT_SRC, I2S_FLAG_LZC); + } + /** RZC */ + if (tls_bitband_read(HR_I2S_INT_SRC, I2S_FLAG_RZC_Pos) && !tls_bitband_read(HR_I2S_INT_MASK, I2S_FLAG_RZC_Pos)) + { + tls_reg_write32(HR_I2S_INT_SRC, I2S_FLAG_RZC); + } + /** Tx Done*/ + if (tls_bitband_read(HR_I2S_INT_SRC, I2S_FLAG_TXDONE_Pos) && !tls_bitband_read(HR_I2S_INT_MASK, I2S_FLAG_TXDONE_Pos)) + { + tls_reg_write32(HR_I2S_INT_SRC, I2S_FLAG_TXDONE); + } + /** TxTH*/ + if (tls_bitband_read(HR_I2S_INT_SRC, I2S_FLAG_TXTH_Pos)&& !tls_bitband_read(HR_I2S_INT_MASK, I2S_FLAG_TXTH_Pos)) + { + tls_reg_write32(HR_I2S_INT_SRC, I2S_FLAG_TXTH); + tls_i2s_fill_txfifo(); + } + /** TXOV*/ + if (tls_bitband_read(HR_I2S_INT_SRC, I2S_FLAG_TXOV_Pos) && !tls_bitband_read(HR_I2S_INT_MASK, I2S_FLAG_TXOV_Pos)) + { + tls_reg_write32(HR_I2S_INT_SRC, I2S_FLAG_TXOV); + } + /** TXUD*/ + if (tls_bitband_read(HR_I2S_INT_SRC, I2S_FLAG_TXUD_Pos) && !tls_bitband_read(HR_I2S_INT_MASK, I2S_FLAG_TXUD_Pos)) + { + tls_reg_write32(HR_I2S_INT_SRC, I2S_FLAG_TXUD); + } + /** Rx Done*/ + if (tls_bitband_read(HR_I2S_INT_SRC, I2S_FLAG_RXDONE_Pos) && !tls_bitband_read(HR_I2S_INT_MASK, I2S_FLAG_RXDONE_Pos)) + { + tls_reg_write32(HR_I2S_INT_SRC, I2S_FLAG_RXDONE); + } + /** RxTH */ + if (tls_bitband_read(HR_I2S_INT_SRC, I2S_FLAG_RXTH_Pos)&& !tls_bitband_read(HR_I2S_INT_MASK, I2S_FLAG_RXTH_Pos)) + { + tls_reg_write32(HR_I2S_INT_SRC, I2S_FLAG_RXTH); + rx_fifocnt = tls_i2s_port.regs->INT_STATUS & I2S_RX_FIFO_CNT_MASK; + if (tls_i2s_port.rx_buf.buf != NULL) + { + while(rx_fifocnt-- > 0) + { + tls_i2s_port.rx_buf.buf[tls_i2s_port.rx_buf.index] = tls_i2s_port.regs->RX; + tls_i2s_port.rx_buf.index++; + } + if (tls_i2s_port.rx_buf.index >= (tls_i2s_port.rx_buf.len)) + { + tls_i2s_port.rx_buf.buf = NULL; + tls_i2s_int_config(I2S_INT_MASK_RXTH, 0); + if (tls_i2s_port.rx_callback != NULL) + { + tls_i2s_port.rx_callback(tls_i2s_port.rx_buf.len); + } + tls_i2s_port.rx_buf.index = 0; + } + } + + } + /** RXOV*/ + if (tls_bitband_read(HR_I2S_INT_SRC, I2S_FLAG_RXOV_Pos) && !tls_bitband_read(HR_I2S_INT_MASK, I2S_FLAG_RXOV_Pos)) + { + tls_reg_write32(HR_I2S_INT_SRC, I2S_FLAG_RXOV); + } + /** RXUD*/ + if (tls_bitband_read(HR_I2S_INT_SRC, I2S_FLAG_RXUD_Pos) && !tls_bitband_read(HR_I2S_INT_MASK, I2S_FLAG_RXUD_Pos)) + { + tls_reg_write32(HR_I2S_INT_SRC, I2S_FLAG_RXUD); + } +} + +/** + * @brief + * This function is used to register i2s rx interrupt. + * + * @param[in] rx_callback + * is the i2s interrupt call back function. + * + * @retval + * + */ + +void tls_i2s_rx_register( void (*rx_callback)(u16 len)) +{ + tls_i2s_port.rx_callback = rx_callback; +} + +/** + * @brief + * This function is used to register i2s tx interrupt. + * + * @param[in] tx_callback + * is the i2s interrupt call back function. + * + * @retval + * + */ +void tls_i2s_tx_register(void (* tx_callback)(u16 len)) +{ + tls_i2s_port.tx_callback = tx_callback; +} + +static void tls_i2s_fill_txfifo() +{ + s8 fifo_left = 0; + + if (tls_i2s_port.tx_buf.index < tls_i2s_port.tx_buf.len) + { + fifo_left = I2S_MAX_RXTXFIFO_LEVEL - ((tls_i2s_port.regs->INT_STATUS & I2S_TX_FIFO_CNT_MASK)>>4); + while (fifo_left--) + { + tls_i2s_port.regs->TX = *(uint32_t *)(tls_i2s_port.tx_buf.buf + tls_i2s_port.tx_buf.index); + tls_i2s_port.tx_buf.index ++; + } + if(tls_i2s_port.tx_buf.index >= tls_i2s_port.tx_buf.len) + { + while((tls_i2s_port.regs->INT_STATUS & I2S_TX_FIFO_CNT_MASK)>>4); + if(tls_i2s_port.tx_sem) + { + memset(&tls_i2s_port.tx_buf, 0, sizeof(tls_i2s_buf)); + tls_os_sem_release(tls_i2s_port.tx_sem); + return; + } + if (tls_i2s_port.tx_callback) + { + tls_i2s_port.tx_callback(tls_i2s_port.tx_buf.len); + } + } + } +} + +/** + * @brief + * This function is used to transfer data in blocking mode. + * + * @param[in] buf + * pointer to the transfering data. + * + * @param[in] len + * is the data length. + * + * @retval + * + */ +int tls_i2s_tx_block(uint32_t *buf, uint16_t len) +{ + uint8_t err; + + + err = tls_os_sem_create(&tls_i2s_port.tx_sem, 0); + if (err != TLS_OS_SUCCESS) + { + TLS_DBGPRT_ERR("\ni2s tx sem create fail\n"); + return WM_FAILED; + } + TLS_I2S_TX_FIFO_CLEAR(); + tls_reg_write32(HR_I2S_INT_SRC, 0x1FF); + NVIC_ClearPendingIRQ(I2S_IRQn); + + tls_i2s_port.tx_buf.buf = buf; + tls_i2s_port.tx_buf.len = len; + tls_i2s_port.tx_buf.index = 0; + + tls_i2s_set_txth(5); + tls_i2s_int_config(I2S_INT_MASK_TXTH, 1); + TLS_I2S_TX_ENABLE(); + TLS_I2S_ENABLE(); + + tls_os_sem_acquire(tls_i2s_port.tx_sem, 0); + tls_os_sem_delete(tls_i2s_port.tx_sem); + tls_i2s_port.tx_sem = NULL; + TLS_I2S_TX_DISABLE(); + + return WM_SUCCESS; +} + +/** + * @brief + * This function is used to transfer data in non blocking mode. + * + * @param[in] buf + * is a buf for user data. + * + * @param[in] len + * is the data length. + * + * @param[in] tx_callback + * a function pointer,which will be called when the designated data sent + * + * @retval + * + * @note the \ref len in words + */ +int tls_i2s_tx_nonblock(uint32_t *buf, uint16_t len, void (*tx_callback)(u16 len)) +{ + tls_i2s_port.tx_buf.buf = (uint32_t *)buf; + tls_i2s_port.tx_buf.len = len; + tls_i2s_port.tx_buf.index = 0; + + tls_i2s_set_txth(5); + tls_i2s_int_config(I2S_INT_MASK_TXTH, 1); + tls_i2s_tx_register( tx_callback); + + TLS_I2S_TX_FIFO_CLEAR(); + TLS_I2S_TX_ENABLE(); + TLS_I2S_ENABLE(); + return WM_SUCCESS; +} + +/** + * @brief + * This function is used to receiver data in non blocking mode. + * + * @param[in] buf + * the buffer for storing the received data. + * + * @param[in] len + * the length of the data will be receiving + * + * @param[in] rx_callback + * a function pointer,which will be called when the demanded data have been received + * + * @retval + * + */ +int tls_i2s_rx_nonblock(uint32_t *buf, uint16_t len, void (*rx_callback)(u16 len)) +{ + tls_i2s_port.rx_buf.buf = buf; + tls_i2s_port.rx_buf.len = len; + tls_i2s_port.rx_buf.index = 0; + + tls_i2s_set_rxth(5); + tls_i2s_int_config(I2S_INT_MASK_RXTH, 1); + tls_i2s_rx_register( rx_callback); + + TLS_I2S_RX_FIFO_CLEAR(); + NVIC_ClearPendingIRQ(I2S_IRQn); + TLS_I2S_RX_ENABLE(); + TLS_I2S_ENABLE(); + + return WM_SUCCESS; +} + +/** + * @brief + * This function is used to the tx DMA configuration of the I2S module. + * + * @param[in] dma_channel + * the free dma channel number which returned by calling function tls_dma_request() + * + * @param[in] addr + * point to the data buffer will be sent + * + * @param[in] len + * length of the data to be transfered in bytes + * + * @retval + */ +void tls_i2s_tx_dma_config(uint8_t dma_channel, uint32_t * addr, uint16_t len) +{ + + struct tls_dma_descriptor DmaDesc; + + TLS_I2S_TX_DISABLE(); + TLS_I2S_TX_FIFO_CLEAR(); + /** Mask i2s txth interrupt*/ + tls_i2s_set_txth(4); + tls_i2s_int_config(I2S_INT_MASK_TXTH, 0); + DmaDesc.src_addr = (unsigned int) addr; + DmaDesc.dest_addr = (unsigned int)HR_I2S_TX; + + DmaDesc.dma_ctrl = TLS_DMA_DESC_CTRL_SRC_ADD_INC | TLS_DMA_DESC_CTRL_DATA_SIZE_WORD | + (len << 7); + DmaDesc.valid = TLS_DMA_DESC_VALID; + DmaDesc.next = NULL; + tls_dma_start(dma_channel, &DmaDesc, 0); + +} + +/** + * @brief + * datas transmit throuth DMA + * + * @param[in] addr + * point to the data buffer will be sent + * @param[in] len + * length of the data to be transfered in bytes + * @param[in] callback + * the callback function when datas transfer finished + * + * @retval + * + * @note the \ref len in bytes + */ +int tls_i2s_tx_dma(uint32_t * addr, uint16_t len, tls_i2s_callback callback) +{ + uint8_t tx_channel; + + TLS_I2S_TX_FIFO_CLEAR(); + tls_reg_write32(HR_I2S_INT_SRC, 0x1FF); + NVIC_ClearPendingIRQ(I2S_IRQn); + + TLS_I2S_TX_FIFO_CLEAR(); + + tx_channel = tls_dma_request(WM_I2S_TX_DMA_CHANNEL, TLS_DMA_FLAGS_CHANNEL_SEL(TLS_DMA_SEL_I2S_TX) | TLS_DMA_FLAGS_HARD_MODE); + if (tx_channel == 0) + { + return WM_FAILED; + } + if (tls_dma_stop(tx_channel)) + { + return WM_FAILED; + } + tls_i2s_tx_dma_config(tx_channel, addr, len); + tls_dma_irq_register(tx_channel, callback, NULL, TLS_DMA_IRQ_TRANSFER_DONE); + TLS_I2S_TXDMA_ENABLE(); + TLS_I2S_TX_ENABLE(); + TLS_I2S_ENABLE(); + + return WM_SUCCESS; +} + +/** + * @brief + * This function is used to the rx DMA configuration of the I2S module. + * + * @param[in] addr + * point to the storge buffer of the received data + * + * @param[in] len + * the storge buffer length in bytes + * + * @retval + */ +void tls_i2s_rx_dma_config(uint8_t dma_channel, uint32_t * addr, uint16_t len) +{ + + struct tls_dma_descriptor DmaDesc; + + tls_i2s_int_config(I2S_INT_MASK_RXTH, 0); + TLS_I2S_RX_DISABLE(); + TLS_I2S_RXDMA_DISABLE(); + TLS_I2S_RX_FIFO_CLEAR(); + /** Mask i2s rxth interrupt*/ + tls_i2s_set_rxth(4); + + tls_i2s_int_config(I2S_INT_MASK_RXTH, 0); + DmaDesc.src_addr = (int)HR_I2S_RX; + DmaDesc.dest_addr = (int)addr; + + DmaDesc.dma_ctrl = TLS_DMA_DESC_CTRL_DEST_ADD_INC | TLS_DMA_DESC_CTRL_DATA_SIZE_WORD | + (len << 7); + DmaDesc.valid = TLS_DMA_DESC_VALID; + DmaDesc.next = NULL; + tls_dma_start(dma_channel, &DmaDesc, 0); +} + +int tls_i2s_rx_dma(uint32_t * addr, uint16_t len, tls_i2s_callback callback) +{ + uint8_t rx_channel; + + rx_channel = tls_dma_request(WM_I2S_RX_DMA_CHANNEL, TLS_DMA_FLAGS_CHANNEL_SEL(TLS_DMA_SEL_I2S_RX) | TLS_DMA_FLAGS_HARD_MODE); + if (rx_channel == 0) + { + return WM_FAILED; + } + if (tls_dma_stop(rx_channel)) + { + return WM_FAILED; + } + tls_i2s_rx_dma_config(rx_channel, addr, len); + tls_dma_irq_register(rx_channel, callback, NULL, TLS_DMA_IRQ_TRANSFER_DONE); + TLS_I2S_RXDMA_ENABLE(); + NVIC_ClearPendingIRQ(I2S_IRQn); + TLS_I2S_RX_ENABLE(); + TLS_I2S_ENABLE(); + + return WM_SUCCESS; +} +#if 1 +uint8_t tst_flag = 0; + +void tls_i2s_tx_dma_callback() +{ + I2S->TX = 0x00; + while(!tls_bitband_read(HR_I2S_INT_SRC, 7)); + TLS_I2S_TX_DISABLE(); + DMA_CHNLCTRL_REG(WM_I2S_TX_DMA_CHANNEL) |= DMA_CHNL_CTRL_CHNL_OFF; + tls_dma_free(WM_I2S_TX_DMA_CHANNEL); + tst_flag = 1; +} +void tls_i2s_rx_dma_callback() +{ + TLS_I2S_RX_DISABLE(); + DMA_CHNLCTRL_REG(WM_I2S_RX_DMA_CHANNEL) |= DMA_CHNL_CTRL_CHNL_OFF; + tls_dma_free(WM_I2S_RX_DMA_CHANNEL); + tst_flag = 1; +} +void tls_i2s_rx_callback() +{ + TLS_I2S_RX_DISABLE(); + tst_flag = 1; +} +void tls_i2s_test() +{ + uint32_t *ptr = NULL; + uint32_t len; + uint32_t * i2s_tx_test = tls_mem_alloc(1024); + tls_i2s_port.opts.data_width = I2S_CTRL_DATABIT_16; + tls_i2s_port.opts.format = I2S_CTRL_FORMAT_I2S; + tls_i2s_port.opts.tx_en = 1; + tls_i2s_port.opts.sample_rate = 8000; + tls_i2s_port.opts.stereo_mono = I2S_CTRL_STERO; + tls_i2s_port_init(&tls_i2s_port.opts); + if (i2s_tx_test == NULL) + { + return; + } + ptr = i2s_tx_test; + for (len = 0; len < 256; len++) + { + *ptr++ = 0xABCD0200 + len; + } + i2s_tx_test[255] = 0xABCD02FA; + tls_i2s_tx_dma(i2s_tx_test, 1024,tls_i2s_tx_dma_callback); + while(!tst_flag); + tst_flag = 0; + tls_i2s_tx_dma(i2s_tx_test, 1024,tls_i2s_tx_dma_callback); + while(!tst_flag); + tst_flag = 0; +} +#endif +#endif /** TLS_CONFIG_I2S */ + + +/*** (C) COPYRIGHT 2014 Winner Microelectronics Co., Ltd. ***/ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_internal_fls.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_internal_fls.c new file mode 100644 index 00000000..bb9c3b63 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_internal_fls.c @@ -0,0 +1,1057 @@ +/** + * @file wm_internal_fls.c + * + * @brief flash Driver Module + * + * @author dave + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ +#include +#include +#include +#include "wm_dbg.h" +#include "wm_mem.h" +#include "list.h" +#include "wm_flash_map.h" +#include "wm_internal_flash.h" +#include "wm_flash.h" + +static struct tls_inside_fls *inside_fls = NULL; +static u32 inner1flashsize = 0; /*first inner flash size*/ +static u32 inner2flashsize = 0; /*second inner flash size*/ + +u32 flashtotalsize = 0; + +unsigned char com_mem[4096]; + + +static void writeEnable(void) +{ + M32(0x40002000) = 0x6; + M32(0x40002004) = 0x10000000; +} + +unsigned char readRID(void) +{ + M32(0x40002000) = 0x2c09F; + M32(0x40002004) = 0x10000000; + return M32(0x40002200)&0xFF; +} + +void writeGDBpBit(char cmp, char bp4, char bp3, char bp2, char bp1, char bp0) +{ + int status = 0; + int bpstatus = 0; + + M32(0x40002000) = 0x0C005; + M32(0x40002004) = 0x10000000; + status = M32(0x40002200)&0xFF; + + M32(0x40002000) = 0x0C035; + M32(0x40002004) = 0x10000000; + status |= (M32(0x40002200)&0xFF)<<8; + + /*Write Enable*/ + M32(0x40002000) = 0x6; + M32(0x40002004) = 0x10000000; + + bpstatus = (bp4<<6)|(bp3<<5)|(bp2<<4)|(bp1<<3)|(bp0<<2); + status = (status&0xBF83)|bpstatus|(cmp<<14); + + M32(0x40002200) = status; + M32(0x40002000) = 0x1A001; + M32(0x40002004) = 0x10000000; +} + +void writeESMTBpBit(char cmp, char bp4, char bp3, char bp2, char bp1, char bp0) +{ + int status = 0; + int bpstatus = 0; + + M32(0x40002000) = 0x0C005; + M32(0x40002004) = 0x10000000; + status = M32(0x40002200)&0xFF; + bpstatus = (bp4<<6)|(bp3<<5)|(bp2<<4)|(bp1<<3)|(bp0<<2); + status = (status&0x83)|bpstatus; + + /*Write Enable*/ + M32(0x40002000) = 0x6; + M32(0x40002004) = 0x10000000; + + bpstatus = (bp4<<6)|(bp3<<5)|(bp2<<4)|(bp1<<3)|(bp0<<2); + status = (status&0x83)|bpstatus|(cmp<<14); + + M32(0x40002200) = status; + M32(0x40002000) = 0x0A001; + M32(0x40002004) = 0x10000000; + + + M32(0x40002000) = 0x0C085; + M32(0x40002004) = 0x10000000; + status = M32(0x40002200)&0xFF; + + /*Write Enable*/ + M32(0x40002000) = 0x6; + M32(0x40002004) = 0x10000000; + + status = (status&0xBF)|(cmp<<6); + M32(0x40002200) = status; + M32(0x40002000) = 0x0A0C1; + M32(0x40002004) = 0x10000000; +} + +int flashunlock(void) +{ + switch(readRID()) + { + case SPIFLASH_MID_GD: + case SPIFLASH_MID_PUYA: + writeGDBpBit(0,0,0,0,0,0); + break; + case SPIFLASH_MID_ESMT: + writeESMTBpBit(0,0,0,0,0,0); + break; + default: + return -1; + } + return 0; +} + +int flashlock(void) +{ + switch(readRID()) + { + case SPIFLASH_MID_GD: + case SPIFLASH_MID_PUYA: + writeGDBpBit(0,1,1,0,1,0); + break; + case SPIFLASH_MID_ESMT: + writeESMTBpBit(0,1,1,0,1,0); + break; + default: + return -1;/*do not clear QIO Mode*/ + } + return 0; +} + +static int programSR(unsigned int cmd, unsigned long addr, unsigned char *buf, unsigned int sz) +{ + unsigned long base_addr = 0; + unsigned int size = 0; + + + if (sz > INSIDE_FLS_PAGE_SIZE) + { + sz = INSIDE_FLS_PAGE_SIZE; + } + + base_addr = 0x40002200; + size = sz; + while(size) + { + M32(base_addr) = *((unsigned long *)buf); + base_addr += 4; + buf += 4; + size -= 4; + } + + writeEnable(); + M32(0x40002000) = cmd | ((sz-1) << 16); + M32(0x40002004) = 0x10000000 | ((addr&0xFFFFF) << 8); + + return 0; +} + + +static int programPage (unsigned long adr, unsigned long sz, unsigned char *buf) +{ + programSR(0x80009002, adr, buf, sz); + return(0); +} + +static int eraseSR(unsigned int cmd, unsigned long addr) +{ + /*Write Enable*/ + writeEnable(); + M32(0x40002000) = cmd; + M32(0x40002004) = 0x10000000|((addr&0xFFFFF)<<8); + + return 0; +} + +static int eraseSector (unsigned long adr) +{ + eraseSR(0x80000820, adr); + + return (0); // Finished without Errors +} + +static unsigned int getFlashDensity(void) +{ + unsigned char density = 0; + + M32(0x40002000) = 0x2c09F; + M32(0x40002004) = 0x10000000; + + density = ((M32(0x40002200)&0xFFFFFF)>>16)&0xFF; + if ((density == 0x14) ||(density == 0x13)) + { + return (1< 0) + { + M32(buf) = M32(addr_read); + buf += 3; //point last byte + while(byte) + { + *buf = 0; + buf --; + byte --; + } + } + + return 0; +} + +void flashSRRW(unsigned long offset,unsigned char *buf,unsigned long sz, unsigned char *backbuf, unsigned int backlen, unsigned int rd) +{ +#define SR_TOTAL_SZ (512) +#define SR_PROGRAM_SZE (256) + unsigned int i; + unsigned int j; + unsigned int baseaddr = 0; + unsigned int sectoroffset = 0; + unsigned int sectorsize = 0; + unsigned int sectornum = 0; + unsigned int remainsz; + unsigned int erasecmd = 0; + unsigned int readcmd = 0; + unsigned int writecmd = 0; + + unsigned char flashid = 0; + if (!buf ||((rd == 0)&&( !backbuf || (backlen < 512)))) + { + return; + } + + flashid = readRID(); + switch(flashid) + { + case SPIFLASH_MID_GD: + baseaddr = 0x0; + sectoroffset = 256; + sectorsize = 256; + sectornum = 2; + erasecmd = 0x80000844; + readcmd = 0xBC00C048; + writecmd = 0x80009042; + break; + + case SPIFLASH_MID_ESMT: + { + baseaddr = 0xFF000; + sectoroffset = 0; + sectorsize = 512; + sectornum = 1; + erasecmd = 0x80000820; + readcmd = 0xBC00C00B; + writecmd = 0x80009002; + + M32(0x40002000) = 0x3A; /*enter OTP*/ + M32(0x40002004) = 0x10000000; + } + break; + + case SPIFLASH_MID_PUYA: + baseaddr = 0x1000; + sectoroffset = 0; + sectorsize = 512; + sectornum = 1; + erasecmd = 0x80000844; + readcmd = 0xBC00C048; + writecmd = 0x80009042; + + break; + + default: + { + } + break; + } + + for (i =0 ; i < sectornum; i++) + { + readSR(readcmd, baseaddr + sectoroffset*i, backbuf+i*sectorsize, sectorsize); + } + + if (rd) + { + for(i=0;i 0) + { + M32(buf) = M32(addr_read); + buf += 3; //point last byte + byte = 4 - byte; + while(byte) + { + *buf = 0; + buf --; + byte --; + } + } + + return 0; +} + +int flashRead(unsigned long addr, unsigned char *buf, unsigned long sz) +{ +#define FLASH_READ_BUF_SIZE (256) + + unsigned int flash_addr; + unsigned int sz_1k = 0; + unsigned int sz_remain = 0; + int i = 0; + int page_offset = addr&(FLASH_READ_BUF_SIZE - 1); + + char *cache = NULL; + + cache = tls_mem_alloc(INSIDE_FLS_SECTOR_SIZE); + if (cache == NULL) + { + TLS_DBGPRT_ERR("allocate sector cache memory fail!\n"); + return TLS_FLS_STATUS_ENOMEM; + } + flash_addr = addr&~(FLASH_READ_BUF_SIZE - 1); + readByCMD(flash_addr, (unsigned char*)cache, FLASH_READ_BUF_SIZE, 0); + if (sz > FLASH_READ_BUF_SIZE - page_offset){ + MEMCPY(buf, cache+page_offset, FLASH_READ_BUF_SIZE - page_offset); + buf += FLASH_READ_BUF_SIZE - page_offset; + flash_addr += FLASH_READ_BUF_SIZE; + + sz_1k = (sz -(FLASH_READ_BUF_SIZE - page_offset)) /FLASH_READ_BUF_SIZE; + sz_remain = (sz -(FLASH_READ_BUF_SIZE - page_offset))%FLASH_READ_BUF_SIZE; + for (i = 0; i < sz_1k; i++) + { + + readByCMD(flash_addr, (unsigned char*)cache, FLASH_READ_BUF_SIZE, 0); + MEMCPY(buf, cache, FLASH_READ_BUF_SIZE); + buf += FLASH_READ_BUF_SIZE; + flash_addr += FLASH_READ_BUF_SIZE; + } + + if (sz_remain) + { + readByCMD(flash_addr, (unsigned char*)cache, sz_remain, 0); + MEMCPY(buf, cache, sz_remain); + } + }else{ + MEMCPY(buf, cache+page_offset, sz); + } + tls_mem_free(cache); + + return 0; +} + +/** + * @brief This function is used to unlock flash protect area [0x0~0x2000]. + * + * @param None + * + * @return None + * + * @note None + */ +int tls_flash_unlock(void) +{ + return flashunlock(); +} + +/** + * @brief This function is used to lock flash protect area [0x0~0x2000]. + * + * @param None + * + * @return None + * + * @note None + */ +int tls_flash_lock(void) +{ + return flashlock(); +} + + +/** + * @brief This function is used to semaphore protect. + * + * @param None + * + * @return None + * + * @note None + */ +void tls_fls_sem_lock(void) +{ + if (inside_fls == NULL) + { + return; + } + tls_os_sem_acquire(inside_fls->fls_lock, 0); +} + + +/** + * @brief This function is used to semaphore protect cancel. + * + * @param None + * + * @return None + * + * @note None + */ +void tls_fls_sem_unlock(void) +{ + if (inside_fls == NULL) + { + return; + } + tls_os_sem_release(inside_fls->fls_lock); +} + + +/** + * @brief This function is used to read data from the flash. + * + * @param[in] addr is byte offset addr for read from the flash. + * @param[in] buf is user for data buffer of flash read + * @param[in] len is byte length for read. + * + * @retval TLS_FLS_STATUS_OK if read sucsess + * @retval TLS_FLS_STATUS_EIO if read fail + * + * @note None + */ +int tls_fls_read(u32 addr, u8 * buf, u32 len) +{ + int err = TLS_FLS_STATUS_EINVAL; + u32 addrfor1M = 0; + u32 lenfor1M = 0; + u32 addrfor2M = 0; + u32 lenfor2M = 0; + + addrfor1M = addr < FLASH_1M_END_ADDR ? addr:0xFFFFFFFF; + if (addrfor1M != 0xFFFFFFFF) + { + lenfor1M = (addr + len ) <= FLASH_1M_END_ADDR ? len : (FLASH_1M_END_ADDR - addr); + if (inside_fls == NULL) + { + TLS_DBGPRT_ERR("flash driver module not beed installed!\n"); + return TLS_FLS_STATUS_EPERM; + } + + if (((addrfor1M&(INSIDE_FLS_BASE_ADDR-1)) >= inner1flashsize) || (lenfor1M == 0) || (buf == NULL)) + { + return TLS_FLS_STATUS_EINVAL; + } + + tls_os_sem_acquire(inside_fls->fls_lock, 0); + + flashRead(addrfor1M, buf, lenfor1M); + + err = TLS_FLS_STATUS_OK; + tls_os_sem_release(inside_fls->fls_lock); + } + + if (inner2flashsize) + { + addrfor2M = addr >= FLASH_1M_END_ADDR ? addr : ((addr + len ) >= FLASH_1M_END_ADDR ? FLASH_1M_END_ADDR : 0xFFFFFFFF); + if (addrfor2M != 0xFFFFFFFF) + { + lenfor2M = len - lenfor1M; + lenfor2M = (addrfor2M + lenfor2M) <= (FLASH_BASE_ADDR | flashtotalsize) ? lenfor2M : ((FLASH_BASE_ADDR | flashtotalsize) - addrfor2M); + return tls_spifls_read(addrfor2M&0xFFFFF, buf+lenfor1M, lenfor2M); + } + } + + return err; +} + +/** + * @brief This function is used to write data to the flash. + * + * @param[in] addr is byte offset addr for write to the flash + * @param[in] buf is the data buffer want to write to flash + * @param[in] len is the byte length want to write + * + * @retval TLS_FLS_STATUS_OK if write flash success + * @retval TLS_FLS_STATUS_EPERM if flash struct point is null + * @retval TLS_FLS_STATUS_ENODRV if flash driver is not installed + * @retval TLS_FLS_STATUS_EINVAL if argument is invalid + * @retval TLS_FLS_STATUS_EIO if io error + * + * @note None + */ +int tls_fls_write(u32 addr, u8 * buf, u32 len) +{ + u8 *cache; + unsigned int secpos; + unsigned int secoff; + unsigned int secremain; + unsigned int i; + unsigned int offaddr; + + u32 addrfor1M = 0; + u32 lenfor1M = 0; + u32 addrfor2M = 0; + u32 lenfor2M = 0; + + addrfor1M = addr < FLASH_1M_END_ADDR ? addr:0xFFFFFFFF; + if (addrfor1M != 0xFFFFFFFF) + { + lenfor1M = (addr + len ) <= FLASH_1M_END_ADDR ? len : (FLASH_1M_END_ADDR - addr); + + if (inside_fls == NULL) + { + TLS_DBGPRT_ERR("flash driver module not beed installed!\n"); + return TLS_FLS_STATUS_EPERM; + } + + if (((addrfor1M&(INSIDE_FLS_BASE_ADDR-1)) >= inner1flashsize) || (lenfor1M == 0) || (buf == NULL)) + { + return TLS_FLS_STATUS_EINVAL; + } + + tls_os_sem_acquire(inside_fls->fls_lock, 0); + + cache = tls_mem_alloc(INSIDE_FLS_SECTOR_SIZE); + if (cache == NULL) + { + tls_os_sem_release(inside_fls->fls_lock); + TLS_DBGPRT_ERR("allocate sector cache memory fail!\n"); + return TLS_FLS_STATUS_ENOMEM; + } + + offaddr = addrfor1M&(INSIDE_FLS_BASE_ADDR -1); //Offset of 0X08000000 + secpos = offaddr/INSIDE_FLS_SECTOR_SIZE; //Section addr + secoff = (offaddr%INSIDE_FLS_SECTOR_SIZE); //Offset in section + secremain = INSIDE_FLS_SECTOR_SIZE - secoff; // 鎵囧尯鍓╀綑绌洪棿澶у皬 + + if(lenfor1M<=secremain) + { + secremain=lenfor1M; //Not bigger with remain size in section + } + while (1) + { + flashRead(secpos*INSIDE_FLS_SECTOR_SIZE, cache, INSIDE_FLS_SECTOR_SIZE); + + eraseSector(secpos*INSIDE_FLS_SECTOR_SIZE); + for (i = 0; i < secremain; i++) // 澶嶅埗 + { + cache[i + secoff] = buf[i]; + } + for (i = 0; i < (INSIDE_FLS_SECTOR_SIZE / INSIDE_FLS_PAGE_SIZE); i++) + { + programPage(secpos*INSIDE_FLS_SECTOR_SIZE + i*INSIDE_FLS_PAGE_SIZE, INSIDE_FLS_PAGE_SIZE, &cache[i*INSIDE_FLS_PAGE_SIZE]); //Write + } + if(lenfor1M == secremain) + { + break; // 鍐欏叆缁撴潫浜 + } + else // 鍐欏叆鏈粨鏉 + { + secpos++; // 鎵囧尯鍦板潃澧1 + secoff = 0; // 鍋忕Щ浣嶇疆涓0 + buf += secremain; // 鎸囬拡鍋忕Щ + lenfor1M -= secremain; + if(lenfor1M > (INSIDE_FLS_SECTOR_SIZE)) + secremain = INSIDE_FLS_SECTOR_SIZE; // 涓嬩竴涓墖鍖鸿繕鏄啓涓嶅畬 + else + secremain = lenfor1M; //Next section will finish + } + } + + tls_mem_free(cache); + tls_os_sem_release(inside_fls->fls_lock); + } + + if (inner2flashsize) + { + addrfor2M = addr >= FLASH_1M_END_ADDR ? addr : ((addr + len ) >= FLASH_1M_END_ADDR ? FLASH_1M_END_ADDR : 0xFFFFFFFF); + if (addrfor2M != 0xFFFFFFFF) + { + lenfor2M = len - lenfor1M; + lenfor2M = (addrfor2M + lenfor2M) <= (FLASH_BASE_ADDR | flashtotalsize)? lenfor2M : ((FLASH_BASE_ADDR | flashtotalsize) - addrfor2M); + return tls_spifls_write((addrfor2M&0xFFFFF), buf + lenfor1M, lenfor2M); + } + } + return TLS_FLS_STATUS_OK; +} + +/** + * @brief This function is used to erase the appoint sector + * + * @param[in] sector sector num of the flash, 4K byte a sector + * + * @retval TLS_FLS_STATUS_OK if read sucsess + * @retval other if read fail + * + * @note None + */ +int tls_fls_erase(u32 sector) +{ + u32 addr; + if (sector < (inner1flashsize/INSIDE_FLS_SECTOR_SIZE + INSIDE_FLS_BASE_ADDR/INSIDE_FLS_SECTOR_SIZE)) + { + if (inside_fls == NULL) + { + TLS_DBGPRT_ERR("flash driver module not beed installed!\n"); + return TLS_FLS_STATUS_EPERM; + } + + tls_os_sem_acquire(inside_fls->fls_lock, 0); + + addr = sector*INSIDE_FLS_SECTOR_SIZE; + + eraseSector(addr); + + tls_os_sem_release(inside_fls->fls_lock); + } + else if (sector < (flashtotalsize/INSIDE_FLS_SECTOR_SIZE + INSIDE_FLS_BASE_ADDR/INSIDE_FLS_SECTOR_SIZE)) + { + return tls_spifls_erase(sector&0xFF); + } + + return TLS_FLS_STATUS_OK; +} + + +static u8 *gsflscache = NULL; +//static u32 gsSecOffset = 0; +static u32 gsSector = 0; + + +/** + * @brief This function is used to flush the appoint sector + * + * @param None + * + * @return None + * + * @note The caller should use fls_lock semphore to protect flash operation! + */ +static void tls_fls_flush_sector(void) +{ + int i; + u32 addr; + if (gsSector < (inner1flashsize/INSIDE_FLS_SECTOR_SIZE + INSIDE_FLS_BASE_ADDR/INSIDE_FLS_SECTOR_SIZE)) + { + addr = gsSector*INSIDE_FLS_SECTOR_SIZE; + + eraseSector(addr); + for (i = 0; i < INSIDE_FLS_SECTOR_SIZE / INSIDE_FLS_PAGE_SIZE; i++) + { + programPage(gsSector * INSIDE_FLS_SECTOR_SIZE + + i * INSIDE_FLS_PAGE_SIZE, INSIDE_FLS_PAGE_SIZE, + &gsflscache[i * INSIDE_FLS_PAGE_SIZE]); + } + } + else if (gsSector < (flashtotalsize/INSIDE_FLS_SECTOR_SIZE + INSIDE_FLS_BASE_ADDR/INSIDE_FLS_SECTOR_SIZE)) + { + addr = gsSector*INSIDE_FLS_SECTOR_SIZE; + tls_spifls_write(addr&0xFFFFF, gsflscache, INSIDE_FLS_SECTOR_SIZE); + } + //gsSecOffset = 0; + +} + + +/** + * @brief This function is used to fast write flash initialize + * + * @param None + * + * @retval TLS_FLS_STATUS_OK sucsess + * @retval other fail + * + * @note None + */ +int tls_fls_fast_write_init(void) +{ + + if (inside_fls == NULL) + { + TLS_DBGPRT_ERR("flash driver module not beed installed!\n"); + return TLS_FLS_STATUS_EPERM; + } + if (NULL != gsflscache) + { + TLS_DBGPRT_ERR("tls_fls_fast_write_init installed!\n"); + return -1; + } + gsflscache = tls_mem_alloc(INSIDE_FLS_SECTOR_SIZE); + if (NULL == gsflscache) + { + TLS_DBGPRT_ERR("tls_fls_fast_write_init malloc err!\n"); + return -1; + } + return TLS_FLS_STATUS_OK; +} + +/** + * @brief This function is used to destroy fast write flash + * + * @param None + * + * @return None + * + * @note None + */ +void tls_fls_fast_write_destroy(void) +{ + if (NULL != gsflscache) + { + if (inside_fls == NULL) + { + TLS_DBGPRT_ERR("flash driver module not beed installed!\n"); + return; + }else{ + tls_os_sem_acquire(inside_fls->fls_lock, 0); + tls_fls_flush_sector(); + tls_os_sem_release(inside_fls->fls_lock); + } + + tls_mem_free(gsflscache); + gsflscache = NULL; + } +} + +/** + * @brief This function is used to fast write data to the flash. + * + * @param[in] addr is byte offset addr for write to the flash + * @param[in] buf is the data buffer want to write to flash + * @param[in] length is the byte length want to write + * + * @retval TLS_FLS_STATUS_OK success + * @retval other fail + * + * @note None + */ +int tls_fls_fast_write(u32 addr, u8 * buf, u32 length) +{ + + u32 sector, offset, maxlen, len; + + if (inside_fls == NULL) + { + TLS_DBGPRT_ERR("flash driver module not beed installed!\n"); + return TLS_FLS_STATUS_EPERM; + } + + if(((addr&(INSIDE_FLS_BASE_ADDR-1)) >= flashtotalsize) || (length == 0) || (buf == NULL)) + { + return TLS_FLS_STATUS_EINVAL; + } + tls_os_sem_acquire(inside_fls->fls_lock, 0); + + sector = addr / INSIDE_FLS_SECTOR_SIZE; + offset = addr % INSIDE_FLS_SECTOR_SIZE; + maxlen = INSIDE_FLS_SECTOR_SIZE; + + if ((sector != gsSector) && (gsSector != 0)) + { + tls_fls_flush_sector(); + } + gsSector = sector; + if (offset > 0) + { + maxlen -= offset; + } + while (length > 0) + { + len = (length > maxlen) ? maxlen : length; + MEMCPY(gsflscache + offset, buf, len); + if (offset + len >= INSIDE_FLS_SECTOR_SIZE) + { + tls_fls_flush_sector(); + gsSector++; + } + offset = 0; + maxlen = INSIDE_FLS_SECTOR_SIZE; + sector++; + buf += len; + length -= len; + } + + tls_os_sem_release(inside_fls->fls_lock); + + return TLS_FLS_STATUS_OK; +} + + +/** + * @brief This function is used to erase flash all chip + * + * @param None + * + * @retval TLS_FLS_STATUS_OK sucsess + * @retval other fail + * + * @note None + */ +int tls_fls_chip_erase(void) +{ + int i,j; + u8 *cache; + + if (inside_fls == NULL) + { + TLS_DBGPRT_ERR("flash driver module not beed installed!\n"); + return TLS_FLS_STATUS_EPERM; + } + + tls_os_sem_acquire(inside_fls->fls_lock, 0); + + cache = tls_mem_alloc(INSIDE_FLS_SECTOR_SIZE); + if (cache == NULL) + { + tls_os_sem_release(inside_fls->fls_lock); + TLS_DBGPRT_ERR("allocate sector cache memory fail!\n"); + return TLS_FLS_STATUS_ENOMEM; + } + + + for( i = 0; i < ( inner1flashsize - (INSIDE_FLS_SECBOOT_ADDR&0xFFFFF))/INSIDE_FLS_SECTOR_SIZE; i ++) + { + flashRead(INSIDE_FLS_SECBOOT_ADDR + i*INSIDE_FLS_SECTOR_SIZE, cache, INSIDE_FLS_SECTOR_SIZE); + for (j = 0;j < INSIDE_FLS_SECTOR_SIZE; j++) + { + if (cache[j] != 0xFF) + { + eraseSector(INSIDE_FLS_SECBOOT_ADDR + i*INSIDE_FLS_SECTOR_SIZE); + break; + } + } + } + + if (inner2flashsize) + { + tls_spifls_chip_erase(); + } + + tls_mem_free(cache); + + tls_os_sem_release(inside_fls->fls_lock); + + return TLS_FLS_STATUS_OK; +} + + +/** + * @brief This function is used to get flash param + * + * @param[in] type the type of the param need to get + * @param[out] param point to addr of out param + * + * @retval TLS_FLS_STATUS_OK sucsess + * @retval other fail + * + * @note None + */ +int tls_fls_get_param(u8 type, void *param) +{ + int err; + + + if (inside_fls == NULL) + { + TLS_DBGPRT_ERR("flash driver module not beed installed!\n"); + return TLS_FLS_STATUS_EPERM; + } + + if (param == NULL) + { + return TLS_FLS_STATUS_EINVAL; + } + tls_os_sem_acquire(inside_fls->fls_lock, 0); + err = TLS_FLS_STATUS_OK; + switch (type) + { + case TLS_FLS_PARAM_TYPE_ID: + *((u32 *) param) = 0x2013; + break; + + case TLS_FLS_PARAM_TYPE_SIZE: + *((u32 *) param) = flashtotalsize; + break; + + case TLS_FLS_PARAM_TYPE_PAGE_SIZE: + *((u32 *) param) = INSIDE_FLS_PAGE_SIZE; + break; + + case TLS_FLS_PARAM_TYPE_PROG_SIZE: + *((u32 *) param) = INSIDE_FLS_PAGE_SIZE; + break; + + case TLS_FLS_PARAM_TYPE_SECTOR_SIZE: + *((u32 *) param) = INSIDE_FLS_SECTOR_SIZE; + break; + + default: + TLS_DBGPRT_WARNING("invalid parameter ID!\n"); + err = TLS_FLS_STATUS_EINVAL; + break; + } + tls_os_sem_release(inside_fls->fls_lock); + return err; +} + +/** + * @brief This function is used to initialize the flash module + * + * @param None + * + * @retval TLS_FLS_STATUS_OK sucsess + * @retval other fail + * + * @note None + */ +int tls_fls_init(void) +{ + struct tls_inside_fls *fls; + int err; + u32 id = 0; + + if (inside_fls != NULL) + { + TLS_DBGPRT_ERR("flash driver module has been installed!\n"); + return TLS_FLS_STATUS_EBUSY; + } + + fls = (struct tls_inside_fls *) tls_mem_alloc(sizeof(struct tls_inside_fls)); + if (fls == NULL) + { + TLS_DBGPRT_ERR("allocate @inside_fls fail!\n"); + return TLS_FLS_STATUS_ENOMEM; + } + + memset(fls, 0, sizeof(*fls)); + err = tls_os_sem_create(&fls->fls_lock, 1); + if (err != TLS_OS_SUCCESS) + { + tls_mem_free(fls); + TLS_DBGPRT_ERR("create semaphore @fls_lock fail!\n"); + return TLS_FLS_STATUS_ENOMEM; + } + inside_fls = fls; + + inner1flashsize = getFlashDensity(); + if (TLS_FLS_STATUS_OK == tls_spifls_read_id(&id)) + { + id = (id>>16)&0xFF; + inner2flashsize = (id ?(1<= WM_IO_PB_00) + { + pin = name - WM_IO_PB_00; + offset = TLS_IO_AB_OFFSET; + } + else + { + pin = name; + offset = 0; + } + + tls_reg_write32(HR_GPIO_AF_SEL + offset, tls_reg_read32(HR_GPIO_AF_SEL + offset) | BIT(pin)); /* gpio function */ + tls_reg_write32(HR_GPIO_AF_S1 + offset, tls_reg_read32(HR_GPIO_AF_S1 + offset) & (~BIT(pin))); + tls_reg_write32(HR_GPIO_AF_S0 + offset, tls_reg_read32(HR_GPIO_AF_S0 + offset) & (~BIT(pin))); + + return; +} + +static void io_cfg_option2(enum tls_io_name name) +{ + u8 pin; + u16 offset; + + if ( (WM_IO_PB_13 == name) || (WM_IO_PB_27 == name) || + (WM_IO_PB_31 == name) ) + { + TLS_DBGPRT_IO_ERR("io %u have no option2.\r\n", name); + return; + } + + if (name >= WM_IO_PB_00) + { + pin = name - WM_IO_PB_00; + offset = TLS_IO_AB_OFFSET; + } + else + { + pin = name; + offset = 0; + } + + tls_reg_write32(HR_GPIO_AF_SEL + offset, tls_reg_read32(HR_GPIO_AF_SEL + offset) | BIT(pin)); /* gpio function */ + tls_reg_write32(HR_GPIO_AF_S1 + offset, tls_reg_read32(HR_GPIO_AF_S1 + offset) & (~BIT(pin))); + tls_reg_write32(HR_GPIO_AF_S0 + offset, tls_reg_read32(HR_GPIO_AF_S0 + offset) | BIT(pin)); + + return; +} + +static void io_cfg_option3(enum tls_io_name name) +{ + u8 pin; + u16 offset; + + if ( (name == WM_IO_PB_19) || (name == WM_IO_PB_20) || + (name >= WM_IO_PB_23) || (name == WM_IO_PA_00) || + (name == WM_IO_PA_07) || + ((name >= WM_IO_PA_13) && (name <= WM_IO_PA_15)) ) + { + TLS_DBGPRT_IO_ERR("io %u have no option3.\r\n", name); + return; + } + + if (name >= WM_IO_PB_00) + { + pin = name - WM_IO_PB_00; + offset = TLS_IO_AB_OFFSET; + } + else + { + pin = name; + offset = 0; + } + + tls_reg_write32(HR_GPIO_AF_SEL + offset, tls_reg_read32(HR_GPIO_AF_SEL + offset) | BIT(pin)); /* gpio function */ + tls_reg_write32(HR_GPIO_AF_S1 + offset, tls_reg_read32(HR_GPIO_AF_S1 + offset) | BIT(pin)); + tls_reg_write32(HR_GPIO_AF_S0 + offset, tls_reg_read32(HR_GPIO_AF_S0 + offset) & (~BIT(pin))); + + return; +} + +static void io_cfg_option4(enum tls_io_name name) +{ + u8 pin; + u16 offset; + + if( (name == WM_IO_PA_00) || (name == WM_IO_PA_01) || + (name == WM_IO_PA_06) || + ((name >= WM_IO_PA_13) && (name <= WM_IO_PA_15)) || + ((name >= WM_IO_PB_00) && (name <= WM_IO_PB_02)) || + (name >= WM_IO_PB_19) ) + { + TLS_DBGPRT_IO_ERR("io %u have no option4.\r\n", name); + return; + } + + if (name >= WM_IO_PB_00) + { + pin = name - WM_IO_PB_00; + offset = TLS_IO_AB_OFFSET; + } + else + { + pin = name; + offset = 0; + } + + tls_reg_write32(HR_GPIO_AF_SEL + offset, tls_reg_read32(HR_GPIO_AF_SEL + offset) | BIT(pin)); /* gpio function */ + tls_reg_write32(HR_GPIO_AF_S1 + offset, tls_reg_read32(HR_GPIO_AF_S1 + offset) | BIT(pin)); + tls_reg_write32(HR_GPIO_AF_S0 + offset, tls_reg_read32(HR_GPIO_AF_S0 + offset) | BIT(pin)); + + return; +} + +static void io_cfg_option5(enum tls_io_name name) +{ + u8 pin; + u16 offset; + + if (name >= WM_IO_PB_00) + { + pin = name - WM_IO_PB_00; + offset = TLS_IO_AB_OFFSET; + } + else + { + pin = name; + offset = 0; + } + + tls_reg_write32(HR_GPIO_AF_SEL + offset, tls_reg_read32(HR_GPIO_AF_SEL + offset) & (~BIT(pin))); /* disable gpio function */ + + return; +} + +static void io_cfg_option6(enum tls_io_name name) +{ + u8 pin; + u16 offset; + + if( ((name >= WM_IO_PB_06)&&(name <= WM_IO_PB_18)) || + ((name >= WM_IO_PB_29)&&(name <= WM_IO_PB_31))) + { + TLS_DBGPRT_IO_ERR("io %u have no option6.\r\n", name); + return; + } + + if (name >= WM_IO_PB_00) + { + pin = name - WM_IO_PB_00; + offset = TLS_IO_AB_OFFSET; + } + else + { + pin = name; + offset = 0; + } + + tls_reg_write32(HR_GPIO_AF_SEL + offset, tls_reg_read32(HR_GPIO_AF_SEL + offset) & (~BIT(pin))); /* disable gpio function */ + tls_reg_write32(HR_GPIO_DIR + offset, tls_reg_read32(HR_GPIO_DIR + offset) & (~BIT(pin))); + tls_reg_write32(HR_GPIO_PULL_EN + offset, tls_reg_read32(HR_GPIO_PULL_EN + offset) & (~BIT(pin))); + + return; +} + +/** + * @brief This function is used to config io function + * + * @param[in] name io name + * @param[in] option io function option, value is WM_IO_OPT*_*, also is WM_IO_OPTION1-6 + * + * @return None + * + * @note None + */ +void tls_io_cfg_set(enum tls_io_name name, u8 option) +{ + if (WM_IO_OPTION1 == option) + io_cfg_option1(name); + else if (WM_IO_OPTION2 == option) + io_cfg_option2(name); + else if (WM_IO_OPTION3 == option) + io_cfg_option3(name); + else if (WM_IO_OPTION4 == option) + io_cfg_option4(name); + else if (WM_IO_OPTION5 == option) + io_cfg_option5(name); + else if (WM_IO_OPTION6 == option) + io_cfg_option6(name); + else + TLS_DBGPRT_IO_ERR("invalid io option.\r\n"); + + return; +} + +/** + * @brief This function is used to get io function config + * + * @param[in] name io name + * + * @retval WM_IO_OPTION1~6 Mapping io function + * + * @note None + */ +int tls_io_cfg_get(enum tls_io_name name) +{ + u8 pin; + u16 offset; + u32 afsel,afs1,afs0,dir,pullen; + + + if (name >= WM_IO_PB_00) + { + pin = name - WM_IO_PB_00; + offset = TLS_IO_AB_OFFSET; + } + else + { + pin = name; + offset = 0; + } + + afsel = tls_reg_read32(HR_GPIO_AF_SEL + offset); + afs1 = tls_reg_read32(HR_GPIO_AF_S1 + offset); + afs0 = tls_reg_read32(HR_GPIO_AF_S0 + offset); + dir = tls_reg_read32(HR_GPIO_DIR + offset); + pullen = tls_reg_read32(HR_GPIO_PULL_EN + offset); + + if(afsel&BIT(pin)) + { + if((0==(afs1&BIT(pin))) && (0==(afs0&BIT(pin)))) + return WM_IO_OPTION1; + else if((0==(afs1&BIT(pin))) && (afs0&BIT(pin))) + return WM_IO_OPTION2; + else if((afs1&BIT(pin)) && (0==(afs0&BIT(pin)))) + return WM_IO_OPTION3; + else if((afs1&BIT(pin)) && (afs0&BIT(pin))) + return WM_IO_OPTION4; + } + else + { + if((!(dir&BIT(pin))) && (pullen&BIT(pin))) + return WM_IO_OPTION6; + else + return WM_IO_OPTION5; + } + + return 0; +} + + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_iouart.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_iouart.c new file mode 100644 index 00000000..ff4770ff --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_iouart.c @@ -0,0 +1,332 @@ +/** + * @file wm_iouart.c + * + * @brief IO uart Driver Module + * + * @author dave + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ + +#include +//#include "wm_iouart.h" +#include "wm_debug.h" +#include "wm_irq.h" +#include "wm_config.h" +#include "wm_mem.h" +#include "wm_gpio.h" +#include "wm_timer.h" + +#if TLS_CONFIG_IOUART +struct tls_io_uart io_uart; +#if !IO_UART_FOR_PRINT +void iouart_timer_cb(void) +{ + static int i = 0; + int value; + u16 bit = -1; + static u8 ch = 0; + + value = tls_reg_read32(HR_TIMER1_CSR); + value |= 1 << 4; + tls_reg_write32(HR_TIMER1_CSR, value); + +// if(io_uart.ifrx) + { + if (0 == io_uart.bitnum) // 璧峰浣 + { + io_uart.bit[io_uart.bitcnt++] = tls_gpio_read(IO_UART_RX); + if (io_uart.bit[0] != 0) + { + io_uart.bitcnt = 0; + tls_gpio_write(IO_UART_TX, 1); + return; + } + if (1 /* IO_UART_ONEBITE_SAMPLE_NUM == io_uart.bitcnt */ ) + { + bit = io_uart.bit[0] /* | io_uart.bit[1] | io_uart.bit[2] */ ; + // printf("\nbit + // cnt=%d,bit=%d,%d,%d,%d\n",io_uart.bitcnt,io_uart.bit[0],io_uart.bit[1],io_uart.bit[2],bit); + if (bit != 0) + { + printf("\nstart bit err\n"); + // tls_timer_stop(); + // tls_gpio_int_enable(IO_UART_RX, + // TLS_GPIO_INT_TRIG_LOW_LEVEL); + io_uart.bitnum = 0; + } + else + { + io_uart.bitnum++; + i = 8; + tls_gpio_write(IO_UART_TX, 0); + } + io_uart.bitcnt = 0; + } + } + else if (io_uart.bitnum >= 1 && io_uart.bitnum <= 8) // 鏁版嵁浣 + { + i--; + if (i <= 0) + { + io_uart.bit[io_uart.bitcnt++] = tls_gpio_read(IO_UART_RX); + if (IO_UART_ONEBITE_SAMPLE_NUM == io_uart.bitcnt) + { + bit = io_uart.bit[0] | io_uart.bit[1] | io_uart.bit[2]; + // printf("\nbit[%d]=[%d]\n",io_uart.bitnum,bit); + if (1 == bit) + { + ch |= (1 << (io_uart.bitnum - 1)); + } + io_uart.bitnum++; + i = 6; + io_uart.bitcnt = 0; + } + } + } + else if (9 == io_uart.bitnum) // 鍋滄浣 + { + i--; + if (i <= 0) + { + io_uart.bit[io_uart.bitcnt++] = tls_gpio_read(IO_UART_RX); + if (IO_UART_ONEBITE_SAMPLE_NUM == io_uart.bitcnt) + { + bit = io_uart.bit[0] | io_uart.bit[1] | io_uart.bit[2]; + if (1 == bit) // 姝ｅ父鐨勫仠姝綅 + { +#if 0 + if (CIRC_SPACE + (io_uart.recv.head, io_uart.recv.tail, + TLS_IO_UART_RX_BUF_SIZE) <= 1) + { + printf("\nrx buf overrun\n"); + io_uart.bitnum = 0; + io_uart.bitcnt = 0; + return; + } +#endif + tls_gpio_write(IO_UART_TX, 1); + io_uart.recv.buf[io_uart.recv.head] = ch; + io_uart.recv.head = + (io_uart.recv.head + 1) & (TLS_IO_UART_RX_BUF_SIZE - + 1); + } + else + { + printf("\nstop bit err\n"); + } + io_uart.bitnum = 0; + io_uart.bitcnt = 0; + ch = 0; + io_uart.ifrx = 0; + // tls_timer_stop(); + // tls_gpio_int_enable(IO_UART_RX, + // TLS_GPIO_INT_TRIG_LOW_LEVEL); + } + } + } + } + +} + + +void iouart_gpio_isr_callback(void *context) +{ + u16 ret; + + ret = tls_get_gpio_int_flag(IO_UART_RX); + if (ret) + { + tls_clr_gpio_int_flag(IO_UART_RX); + if (0 == io_uart.iftx) + { + tls_gpio_int_disable(IO_UART_RX); + tls_timer_start(io_uart.timercnt); + io_uart.ifrx = 1; + } + } +} +#endif + +void iouart_delay(int time) +{ + int value; +#ifndef WM_W600 + tls_reg_write32(HR_TIMER1_CSR, TLS_TIMER_INT_CLR); + tls_reg_write32(HR_TIMER1_CSR, + time << TLS_TIMER_VALUE_S | TLS_TIMER_INT_EN | TLS_TIMER_EN + | TLS_TIMER_ONE_TIME); + + while (1) + { + value = tls_reg_read32(HR_TIMER1_CSR); + if (value & TLS_TIMER_INT_CLR) + { + tls_reg_write32(HR_TIMER1_CSR, TLS_TIMER_INT_CLR); + break; + } + } +#else + tls_reg_write32(HR_TIMER0_5_CSR, TLS_TIMER_INT_CLR(1)); + tls_reg_write32(HR_TIMER1_PRD, time); + tls_reg_write32(HR_TIMER0_5_CSR, + TLS_TIMER_INT_EN(1) | TLS_TIMER_EN(1) | + TLS_TIMER_ONE_TIME(1)); + while (1) + { + value = tls_reg_read32(HR_TIMER0_5_CSR); + if (value & TLS_TIMER_INT_CLR(1)) + { + tls_reg_write32(HR_TIMER0_5_CSR, TLS_TIMER_INT_CLR(1)); + break; + } + } + +#endif +} + +void iouart_tx_byte(u8 datatoSend) +{ + u8 i, tmp; + u32 cpu_sr = 0; + + cpu_sr = tls_os_set_critical(); // 鍙戦佷竴涓猙yte鐨勮繃绋嬩腑涓嶈兘琚墦鏂紝鍚﹀垯鍙兘浼氭湁閿欒鐮 +/* Start bit */ + tls_gpio_write(TLS_GPIO_TYPE_A, IO_UART_TX, 0); +#if IO_UART_FOR_PRINT + iouart_delay(io_uart.timercnt - 3); +#else + iouart_delay(io_uart.timercnt * IO_UART_RATE_MUL); +#endif + for (i = 0; i < 8; i++) + { + tmp = (datatoSend >> i) & 0x01; + + if (tmp == 0) + { + tls_gpio_write(TLS_GPIO_TYPE_A, IO_UART_TX, 0); + } + else + { + tls_gpio_write(TLS_GPIO_TYPE_A, IO_UART_TX, 1); + } +#if IO_UART_FOR_PRINT + iouart_delay(io_uart.timercnt - 3); +#else + iouart_delay(io_uart.timercnt * IO_UART_RATE_MUL); +#endif + } + +/* Stop bit */ + tls_gpio_write(TLS_GPIO_TYPE_A, IO_UART_TX, 1); +#if IO_UART_FOR_PRINT + iouart_delay(io_uart.timercnt - 3); +#else + iouart_delay(io_uart.timercnt * IO_UART_RATE_MUL); +#endif + + tls_os_release_critical(cpu_sr); +} + +int tls_iouart_init(int bandrate) +{ + char *bufrx, *buftx; + + memset(&io_uart, 0, sizeof(struct tls_io_uart)); +#if !IO_UART_FOR_PRINT + bufrx = tls_mem_alloc(TLS_IO_UART_RX_BUF_SIZE); + if (!bufrx) + return WM_FAILED; + memset(bufrx, 0, TLS_IO_UART_RX_BUF_SIZE); + io_uart.recv.buf = (u8 *) bufrx; + io_uart.recv.head = 0; + io_uart.recv.tail = 0; +#endif + + tls_gpio_cfg(TLS_GPIO_TYPE_A, IO_UART_TX, TLS_GPIO_DIR_OUTPUT, + TLS_GPIO_ATTR_FLOATING); + tls_gpio_write(TLS_GPIO_TYPE_A, IO_UART_TX, 1); + + tls_gpio_cfg(TLS_GPIO_TYPE_A, IO_UART_RX, TLS_GPIO_DIR_INPUT, + TLS_GPIO_ATTR_PULLLOW); + +// tls_gpio_isr_register(iouart_gpio_isr_callback,NULL); +// tls_gpio_int_enable(IO_UART_RX, TLS_GPIO_INT_TRIG_LOW_LEVEL); + io_uart.timercnt = 1000000 / bandrate; +#if !IO_UART_FOR_PRINT + io_uart.timercnt = 1000000 / bandrate / IO_UART_RATE_MUL; + + tls_timer_irq_register(iouart_timer_cb); + tls_timer_start(io_uart.timercnt); +#endif +} + +#if !IO_UART_FOR_PRINT +int tls_iouart_destroy(void) +{ + tls_gpio_int_disable(IO_UART_RX); + tls_timer_stop(); + tls_mem_free(io_uart.recv.buf); +} + + +int tls_iouart_read(u8 * buf, int bufsize) +{ + int data_cnt, buflen, bufcopylen; + + if (NULL == buf) + return WM_FAILED; + + data_cnt = + CIRC_CNT(io_uart.recv.head, io_uart.recv.tail, TLS_IO_UART_RX_BUF_SIZE); +// TLS_DBGPRT_INFO("\ndata cnt=%d\n",data_cnt); + if (data_cnt >= bufsize) + { + buflen = bufsize; + } + else + { + buflen = data_cnt; + } + if ((io_uart.recv.tail + buflen) > TLS_IO_UART_RX_BUF_SIZE) + { + bufcopylen = (TLS_IO_UART_RX_BUF_SIZE - io_uart.recv.tail); + MEMCPY(buf, io_uart.recv.buf + io_uart.recv.tail, bufcopylen); + MEMCPY(buf + bufcopylen, io_uart.recv.buf, buflen - bufcopylen); + } + else + { + MEMCPY(buf, io_uart.recv.buf + io_uart.recv.tail, buflen); + } + io_uart.recv.tail = + (io_uart.recv.tail + buflen) & (TLS_IO_UART_RX_BUF_SIZE - 1); + return buflen; +} + + +int tls_iouart_write(u8 * buf, int bufsize) +{ + + + if (NULL == buf || bufsize <= 0 || 1 == io_uart.ifrx) + return WM_FAILED; + + io_uart.iftx = 1; + + while (bufsize) + { + iouart_tx_byte(*buf); + bufsize--; + buf++; + } + + io_uart.iftx = 0; +#if !IO_UART_FOR_PRINT + tls_timer_start(io_uart.timercnt); +#endif + return WM_SUCCESS; +} +#endif +#endif +//TLS_CONFIG_IOUART diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_irq.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_irq.c new file mode 100644 index 00000000..1f0c5040 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_irq.c @@ -0,0 +1,137 @@ +/** + * @file wm_irq.c + * + * @brief interupt driver module + * + * @author dave + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ + +#include +#include +#include "wm_regs.h" +#include "wm_irq.h" +#include "wm_config.h" +//#include "wm_mem.h" +void tls_irq_handler_dummy(void *data) +{ +} + + +tls_irq_handler_t *intr_handler_vect[INTR_CNT]; + +u8 intr_counter; + +/** + * @brief This function is used to initial system interrupt. + * + * @param[in] None + * + * @return None + * + * @note None + */ +void tls_irq_init(void) +{ +#if 0 + int i; + + for (i = 0; i < INTR_CNT; i++) + { + intr_handler_vect[i].handler = tls_irq_handler_dummy; + intr_handler_vect[i].data = NULL; + intr_handler_vect[i].name = "intr_dummy"; + intr_handler_vect[i].counter = 0; + } +#endif + intr_counter = 0; + +/* initailize VIC */ + tls_reg_write32(HR_VIC_INT_SELECT, 0); + tls_reg_write32(HR_VIC_VECT_ENABLE, 0); /* disable vector interrupt */ + tls_reg_write32(HR_VIC_INT_EN_CLR, 0xFFFFFFFF); +} + + +/** + * @brief This function is used to register interrupt. + * + * @param[in] vec_no interrupt no + * @param[in] handler + * @param[in] *data + * + * @return None + * + * @note None + */ +void tls_irq_register_handler(u8 vec_no, intr_handler_func handler, void *data) +{ +// ASSERT (vec_no >= 0 && vec_no <= 0x1f); + if (NULL == intr_handler_vect[vec_no]) + { + intr_handler_vect[vec_no] = malloc(sizeof(tls_irq_handler_t)); + } + if (intr_handler_vect[vec_no]) + { + intr_handler_vect[vec_no]->handler = handler; + intr_handler_vect[vec_no]->data = data; + // intr_handler_vect[vec_no].name = NULL; + intr_handler_vect[vec_no]->counter = 0; + } + +} + +extern void NVIC_Configration(int irqno, FunctionalState irqstatus); + +/** + * @brief This function is used to enable interrupt. + * + * @param[in] vec_no interrupt no + * + * @return None + * + * @note None + */ +void tls_irq_enable(u8 vec_no) +{ + NVIC_ClearPendingIRQ((IRQn_Type)vec_no); + NVIC_Configration(vec_no, ENABLE); +} + +/** + * @brief This function is used to disable interrupt. + * + * @param[in] vec_no interrupt no + * + * @return None + * + * @note None + */ +void tls_irq_disable(u8 vec_no) +{ + NVIC_Configration(vec_no, DISABLE); +} + +void OS_CPU_IRQ_ISR_Handler(void) +{ + u32 irq_status = tls_reg_read32(HR_VIC_IRQ_STATUS); + int i = 0; + intr_counter++; + + for (i = 0; i < INTR_CNT; i++) + { + if (irq_status & (1UL << i)) + { + intr_handler_vect[i]->handler((void *) intr_handler_vect[i]->data); + intr_handler_vect[i]->counter++; + } + } + intr_counter--; +/* clear interrupt */ + tls_reg_write32(HR_VIC_VECT_ADDR, 0); +} + +void UART1_IRQHandler(void) +{ +} diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_lcd.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_lcd.c new file mode 100644 index 00000000..e165a903 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_lcd.c @@ -0,0 +1,187 @@ +/**************************************************************************//** + * @file wm_lcd.c + * @author + * @version + * @date + * @brief + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. All rights reserved. + *****************************************************************************/ + +#include "wm_lcd.h" + +#define RTC_CLK (32000UL) + +/** + * @brief Initialize LCD Frame Counter + * @param[in] freq LCD reference refresh frequency in Hz that will be used + */ +void tls_lcd_fresh_ratio(uint16_t freq) +{ + uint8_t com_num; + + if (freq == 0) + { + freq = 60; + } + + com_num = tls_bitband_read(HR_LCD_CR, LCD_CR_MODE_Pos) ? 4 : 8; + LCD->FRAMECNT = RTC_CLK/(com_num * freq); +} + +/** + * @brief + * Turn on or clear a segment + * + * @param[in] com + * Which COM line to update + * + * @param[in] bit + * Bit index of which field to change + * + * @param[in] enable + * When one will set segment, when zero will clear segment + * + * @param[in] mode + * when one max configuration is 4x20, when zero max configuration is 8x16 + * + */ +void tls_lcd_seg_set(int com, int bit, int on_off) +{ + int mode; + + /** get the mode congfig when one max configuration is 4x20, when zero max configuration is 8x16 */ + mode = tls_bitband_read(HR_LCD_CR, LCD_CR_MODE_Pos); + + if (!mode && (com < 0 || com > 7) && (bit < 0 || bit > 15)) + { + return ; + } + if (mode && (com < 0 || com > 3) && (bit < 0 || bit > 19)) + { + return ; + } + + switch(com) + { + /** COM0 */ + case 0: + tls_bitband_write(HR_LCD_COM0_1_SEG, bit, on_off); + break; + + /** COM1 */ + case 1: + if (mode) + tls_bitband_write(HR_LCD_COM2_3_SEG, bit, on_off); + else + { + bit += 16; + tls_bitband_write(HR_LCD_COM0_1_SEG, bit, on_off); + } + break; + + /** COM2 */ + case 2: + if (mode) + tls_bitband_write(HR_LCD_COM4_5_SEG, bit, on_off); + else + tls_bitband_write(HR_LCD_COM2_3_SEG, bit, on_off); + break; + + /** COM3 */ + case 3: + if (mode) + tls_bitband_write(HR_LCD_COM6_7_SEG, bit, on_off); + else + { + bit += 16; + tls_bitband_write(HR_LCD_COM2_3_SEG, bit, on_off); + } + break; + + /** COM4 */ + case 4: + tls_bitband_write(HR_LCD_COM4_5_SEG, bit, on_off); + break; + + /** COM5 */ + case 5: + bit += 16; + tls_bitband_write(HR_LCD_COM4_5_SEG, bit, on_off); + break; + + /** COM6 */ + case 6: + tls_bitband_write(HR_LCD_COM6_7_SEG, bit, on_off); + break; + + /** COM7 */ + case 7: + bit += 16; + tls_bitband_write(HR_LCD_COM6_7_SEG, bit, on_off); + break; + + default: + break; + } +} + +/** + * @brief enable or disable the LCD module gpio + * + * @param[in] the config value per bit for one LCD gpio, set enable gpio output ,clear disabled + * + */ +void tls_lcd_io_config(unsigned int val) +{ + tls_reg_write32(HR_LCD_IO_EN, val); +} + +/** + * @brief + * select the voltage of LCD module + * + */ +void tls_lcd_vlcd_sel(LCD_VlcdDef vlcd) +{ + LCD->CTRL &= ~LCD_VLCD_MASK; + LCD->CTRL |= vlcd; +} + + +/** + * @brief + * set the duty of LCD module + * + */ +void tls_lcd_duty_set(LCD_DutyDef duty) +{ + LCD->CTRL &= ~LCD_DUTY_MASK; + LCD->CTRL |= duty; +} + + +/** + * @brief + * set the bias of LCD module + * + */ +void tls_lcd_bias_set(LCD_BiasDef bias) +{ + LCD->CTRL &= ~LCD_BIAS_MASK; + LCD->CTRL |= bias; +} + +/** + * @brief + * initialize the lcd module + * + */ +void tls_lcd_init(tls_lcd_options_t *opts) +{ + LCD->CTRL = 0; + LCD->CTRL = opts->mode | opts->bias | opts->duty | opts->vlcd | (1 << 12); + tls_lcd_fresh_ratio(opts->fresh_rate); + TLS_LCD_ENABLE(opts->enable); + TLS_LCD_POWERDOWM(0); +} diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_pmu.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_pmu.c new file mode 100644 index 00000000..b15a4fd9 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_pmu.c @@ -0,0 +1,333 @@ +#include +#include "wm_debug.h" +#include "wm_regs.h" +#include "wm_irq.h" +#include "wm_pwm.h" +#include "wm_gpio.h" +#include "wm_timer.h" +#include "wm_cpu.h" +#include "tls_common.h" +#include "wm_pmu.h" +//#include "wm_wifi.h" +#include "wm_io.h" + +struct pmu_irq_context { + tls_pmu_irq_callback callback; + void *arg; +}; + +static struct pmu_irq_context pmu_timer1_context = {0}; +static struct pmu_irq_context pmu_timer0_context = {0}; +static struct pmu_irq_context pmu_gpio_wake_context = {0}; +static struct pmu_irq_context pmu_sdio_wake_context = {0}; + + +void PMU_TIMER1_IRQHandler(void) +{ + if (tls_reg_read32(HR_PMU_INTERRUPT_SRC) & BIT(1)) /* timer1 interrupt */ + { + tls_reg_write32(HR_PMU_INTERRUPT_SRC, tls_reg_read32(HR_PMU_INTERRUPT_SRC) | BIT(1)); /* clear timer1 interrupt */ + + if (NULL != pmu_timer1_context.callback) + pmu_timer1_context.callback(pmu_timer1_context.arg); + } + return; +} + +void PMU_TIMER0_IRQHandler(void) +{ + if (tls_reg_read32(HR_PMU_INTERRUPT_SRC) & BIT(0)) /* timer0 interrupt */ + { + tls_reg_write32(HR_PMU_INTERRUPT_SRC, tls_reg_read32(HR_PMU_INTERRUPT_SRC) | BIT(0)); /* clear timer0 interrupt */ + tls_reg_write32(HR_PMU_TIMER0, tls_reg_read32(HR_PMU_TIMER0) & (~BIT(16))); + + if (NULL != pmu_timer0_context.callback) + pmu_timer0_context.callback(pmu_timer0_context.arg); + } + return; +} + +void PMU_GPIO_WAKE_IRQHandler(void) +{ + if (tls_reg_read32(HR_PMU_INTERRUPT_SRC) & BIT(2)) /* gpio wake interrupt */ + { + tls_reg_write32(HR_PMU_INTERRUPT_SRC, tls_reg_read32(HR_PMU_INTERRUPT_SRC) | BIT(2)); /* clear gpio wake interrupt */ + + if (NULL != pmu_gpio_wake_context.callback) + pmu_gpio_wake_context.callback(pmu_gpio_wake_context.arg); + } + return; +} + +void PMU_SDIO_WAKE_IRQHandler(void) +{ + if (tls_reg_read32(HR_PMU_INTERRUPT_SRC) & BIT(3)) /* sdio wake interrupt */ + { + tls_reg_write32(HR_PMU_INTERRUPT_SRC, tls_reg_read32(HR_PMU_INTERRUPT_SRC) | BIT(3)); /* clear sdio wake interrupt */ + + if (NULL != pmu_sdio_wake_context.callback) + pmu_sdio_wake_context.callback(pmu_sdio_wake_context.arg); + } + return; +} + + +/** + * @brief This function is used to register pmu timer1 interrupt + * + * @param[in] callback the pmu timer1 interrupt call back function + * @param[in] arg parameter of call back function + * + * @return None + * + * @note + * user not need clear interrupt flag. + * pmu timer1 callback function is called in interrupt, + * so can not operate the critical data in the callback fuuction, + * recommendation to send messages to other tasks to operate it. + */ +void tls_pmu_timer1_isr_register(tls_pmu_irq_callback callback, void *arg) +{ + pmu_timer1_context.callback = callback; + pmu_timer1_context.arg = arg; + + tls_irq_enable(PMU_TIMER1_INT); + + return; +} + + +/** + * @brief This function is used to register pmu timer0 interrupt + * + * @param[in] callback the pmu timer0 interrupt call back function + * @param[in] arg parameter of call back function + * + * @return None + * + * @note + * user not need clear interrupt flag. + * pmu timer0 callback function is called in interrupt, + * so can not operate the critical data in the callback fuuction, + * recommendation to send messages to other tasks to operate it. + */ +void tls_pmu_timer0_isr_register(tls_pmu_irq_callback callback, void *arg) +{ + pmu_timer0_context.callback = callback; + pmu_timer0_context.arg = arg; + + tls_irq_enable(PMU_TIMER0_INT); + + return; +} + + +/** + * @brief This function is used to register pmu gpio interrupt + * + * @param[in] callback the pmu gpio interrupt call back function + * @param[in] arg parameter of call back function + * + * @return None + * + * @note + * user not need clear interrupt flag. + * pmu gpio callback function is called in interrupt, + * so can not operate the critical data in the callback fuuction, + * recommendation to send messages to other tasks to operate it. + */ +void tls_pmu_gpio_isr_register(tls_pmu_irq_callback callback, void *arg) +{ + pmu_gpio_wake_context.callback = callback; + pmu_gpio_wake_context.arg = arg; + + tls_irq_enable(PMU_GPIO_WAKEUP_INT); + + return; +} + + +/** + * @brief This function is used to register pmu sdio interrupt + * + * @param[in] callback the pmu sdio interrupt call back function + * @param[in] arg parameter of call back function + * + * @return None + * + * @note + * user not need clear interrupt flag. + * pmu sdio callback function is called in interrupt, + * so can not operate the critical data in the callback fuuction, + * recommendation to send messages to other tasks to operate it. + */ +void tls_pmu_sdio_isr_register(tls_pmu_irq_callback callback, void *arg) +{ + pmu_sdio_wake_context.callback = callback; + pmu_sdio_wake_context.arg = arg; + + tls_irq_enable(PMU_SDIO_WAKEUP_INT); + + return; +} + +/** + * @brief This function is used to select pmu clk + * + * @param[in] bypass pmu clk whether or not use bypass mode + * ohter pmu clk use 32K by 40MHZ + * 0 pmu clk 32K by calibration circuit + * + * @return None + * + * @note None + */ +void tls_pmu_clk_select(u8 bypass) +{ + u32 val; + + val = tls_reg_read32(HR_PMU_PS_CR); + if(bypass) + { + val |= BIT(3); + } + else + { + val &= ~BIT(3); + } + val |= BIT(2); + tls_reg_write32(HR_PMU_PS_CR, val); +} + + +/** + * @brief This function is used to start pmu timer0 + * + * @param[in] second vlaue of timer0 count[s] + * + * @return None + * + * @note None + */ +void tls_pmu_timer0_start(u16 second) +{ + u32 val; + + val = second; + val |= BIT(16); + tls_reg_write32(HR_PMU_TIMER0, val); +} + + +/** + * @brief This function is used to stop pmu timer0 + * + * @param None + * + * @return None + * + * @note None + */ +void tls_pmu_timer0_stop(void) +{ + u32 val; + + val = tls_reg_read32(HR_PMU_TIMER0); + val &= ~BIT(16); + tls_reg_write32(HR_PMU_TIMER0, val); +} + + + +/** + * @brief This function is used to start pmu timer1 + * + * @param[in] second vlaue of timer1 count[ms] + * + * @return None + * + * @note None + */ +void tls_pmu_timer1_start(u16 msec) +{ + u32 val; + //榛樿閲囩敤鏈灏忓崟浣1ms + val = (msec-1) | (1<<16) | (1<<17) | (0<<20) | (0<<24); + tls_reg_write32(HR_PMU_TIMER1, val); +} + + +/** + * @brief This function is used to stop pmu timer1 + * + * @param None + * + * @return None + * + * @note None + */ +void tls_pmu_timer1_stop(void) +{ + u32 val; + val = tls_reg_read32(HR_PMU_TIMER1); + val &= ~BIT(16); + val &= ~BIT(17); + tls_reg_write32(HR_PMU_TIMER1, val); +} + + + +/** + * @brief This function is used to start pmu goto standby + * + * @param None + * + * @return None + * + * @note None + */ +void tls_pmu_standby_start(void) +{ + u32 val; + + tls_irq_enable(PMU_GPIO_WAKEUP_INT); //榛樿鎵撳紑涓柇涓轰簡娓呮IO鍞ら啋鐨勪腑鏂爣璁 + + val = tls_reg_read32(HR_PMU_PS_CR); + TLS_DBGPRT_INFO("goto standby here\n"); + val |= BIT(0); + tls_reg_write32(HR_PMU_PS_CR, val); +} + +/** + * @brief This function is used to close peripheral's clock + * + * @param[in] devices peripherals + * + * @return None + * + * @note None + */ +void tls_close_peripheral_clock(tls_peripheral_type_s devices) +{ + tls_reg_write32(HR_CLK_BASE_ADDR, tls_reg_read32(HR_CLK_BASE_ADDR) & ~(devices)); + + return; +} + +/** + * @brief This function is used to open peripheral's clock + * + * @param[in] devices peripherals + * + * @return None + * + * @note None + */ +void tls_open_peripheral_clock(tls_peripheral_type_s devices) +{ + tls_reg_write32(HR_CLK_BASE_ADDR, tls_reg_read32(HR_CLK_BASE_ADDR) | devices); + + return; +} + + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_pwm.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_pwm.c new file mode 100644 index 00000000..4193fdcf --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_pwm.c @@ -0,0 +1,920 @@ +/** + * @file wm_pwm.c + * + * @brief pwm driver module + * + * @author dave + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#include + +#include "wm_debug.h" +#include "wm_regs.h" +#include "wm_irq.h" +#include "wm_pwm.h" +#include "wm_gpio.h" +#include "wm_cpu.h" +#include "tls_common.h" + + +typedef void (*pwm_irq_callback)(void); +static pwm_irq_callback pwm_callback; + +void PWM_IRQHandler(void) +{ + if (pwm_callback) + pwm_callback(); +} + +/** + * @brief This function is used to register the pwm interrupt callback function + * + * @param[in] callback the pwm interrupt callback function + * + * @return None + * + * @note None + */ +void tls_pwm_isr_register(void (*callback)(void)) +{ + pwm_callback = callback; + tls_irq_enable(PWM_INT); +} + +/** + * @brief This function is used to set duty ratio + * + * @param[in] channel pwm channel NO.,range form 0 to 4 + * @param[in] duty Number of active levels + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_duty_config(u8 channel, u8 duty) +{ + u32 temp = 0; + + if(channel > (PWM_CHANNEL_MAX_NUM - 1)) + { + TLS_DBGPRT_ERR("duty param err\n"); + return WM_FAILED; + } + + if (4 == channel) + { + temp = tls_reg_read32(HR_PWM_CH4_REG2) & ~0x0000FF00; + temp |= (duty << 8); + tls_reg_write32(HR_PWM_CH4_REG2, temp); /* duty radio */ + } + else + { + temp = tls_reg_read32(HR_PWM_CMPDAT) & ~(0xFF << channel * 8); + temp |= (duty << (channel * 8)); + tls_reg_write32(HR_PWM_CMPDAT, temp); /* duty radio */ + } + + return WM_SUCCESS; +} + +/** + * @brief This function is used to set frequency + * + * @param[in] channel pwm channel NO., range form 0 to 4 + * @param[in] clkdiv clock divider, range 0 to 65535 + * @param[in] period the number of the counting clock cycle + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_freq_config(u8 channel, u16 clkdiv, u8 period) +{ + u32 temp = 0; + + if(channel > (PWM_CHANNEL_MAX_NUM - 1)) + { + TLS_DBGPRT_ERR("freq param err\n"); + return WM_FAILED; + } + + if (4 == channel) + { + temp = tls_reg_read32(HR_PWM_CH4_REG1) & ~0xFFFF0000; + temp |= (clkdiv << 16); + tls_reg_write32(HR_PWM_CH4_REG1, temp);/* clock divider */ + + temp = tls_reg_read32(HR_PWM_CH4_REG1) & ~0x0000FF00; + temp |= (period << 8); + tls_reg_write32(HR_PWM_CH4_REG1, temp); /* the number of the counting clock cycle */ + } + else + { + temp = tls_reg_read32(HR_PWM_CLKDIV01 + (channel / 2) * 4) & ~(0xFFFF << ((channel % 2) * 16)); + temp |= (clkdiv << ((channel % 2) * 16)); + tls_reg_write32(HR_PWM_CLKDIV01 + (channel / 2) * 4, temp);/* clock divider */ + + temp = tls_reg_read32(HR_PWM_PERIOD) & ~(0xFF << channel * 8); + temp |= (period << (channel * 8)); + tls_reg_write32(HR_PWM_PERIOD, temp);/* the number of the counting clock cycle */ + } + + return WM_SUCCESS; +} + +/** + * @brief This function is used to set the output mode + * + * @param[in] channel pwm channel NO.,range form 0 to 4 + * @param[in] mode pwm work mode for signal generate + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_out_mode_config(u8 channel, enum tls_pwm_out_mode mode) +{ + if(channel > (PWM_CHANNEL_MAX_NUM - 1)) + return WM_FAILED; + + if (WM_PWM_OUT_MODE_BRAKE == mode) + tls_reg_write32(HR_PWM_BRKCTL, tls_reg_read32(HR_PWM_BRKCTL) | BIT(11 + channel));/* the brake mode */ + else if (WM_PWM_OUT_MODE_ALLSYC == mode) + { + if (channel != 0) + return WM_FAILED; + tls_reg_write32(HR_PWM_BRKCTL, tls_reg_read32(HR_PWM_BRKCTL) & ~0xF800); /* disable the brake mode */ + tls_reg_write32(HR_PWM_CTL, tls_reg_read32(HR_PWM_CTL) | BIT(6)); /* enable the all synchronous mode mode */ + } + else if (WM_PWM_OUT_MODE_2SYC == mode) + { + if (channel != 0 && channel != 2) + return WM_FAILED; + tls_reg_write32(HR_PWM_BRKCTL, tls_reg_read32(HR_PWM_BRKCTL) & ~(0x1800< (PWM_CHANNEL_MAX_NUM - 1)) + return WM_FAILED; + + if (4 == channel) + { + if (WM_PWM_CNT_TYPE_EDGE_ALLGN_CAP == cnt_type) + { + tls_reg_write32(HR_PWM_CH4_REG2, tls_reg_read32(HR_PWM_CH4_REG2) & (~BIT(4))); + tls_reg_write32(HR_PWM_CH4_REG2, tls_reg_read32(HR_PWM_CH4_REG2) & (~BIT(3))); + } + if (WM_PWM_CNT_TYPE_EDGE_ALIGN_OUT == cnt_type) + { + tls_reg_write32(HR_PWM_CH4_REG2, tls_reg_read32(HR_PWM_CH4_REG2) & (~BIT(4))); + tls_reg_write32(HR_PWM_CH4_REG2, tls_reg_read32(HR_PWM_CH4_REG2) | BIT(3)); + } + else if (WM_PWM_CNT_TYPE_CENTER_ALIGN == cnt_type) + { + tls_reg_write32(HR_PWM_CH4_REG2, tls_reg_read32(HR_PWM_CH4_REG2) | BIT(4)); + tls_reg_write32(HR_PWM_CH4_REG2, tls_reg_read32(HR_PWM_CH4_REG2) & (~BIT(3))); + } + + } + else + { + if (WM_PWM_CNT_TYPE_EDGE_ALLGN_CAP == cnt_type && channel == 0) + { + tls_reg_write32(HR_PWM_CTL, tls_reg_read32(HR_PWM_CTL) & (~BIT(17))); + tls_reg_write32(HR_PWM_CTL, tls_reg_read32(HR_PWM_CTL) & (~BIT(16))); + } + if (WM_PWM_CNT_TYPE_EDGE_ALIGN_OUT == cnt_type) + { + tls_reg_write32(HR_PWM_CTL, tls_reg_read32(HR_PWM_CTL) & (~BIT(17 + channel * 2))); + tls_reg_write32(HR_PWM_CTL, tls_reg_read32(HR_PWM_CTL) | BIT(16 + channel * 2)); + } + else if (WM_PWM_CNT_TYPE_CENTER_ALIGN == cnt_type) + { + tls_reg_write32(HR_PWM_CTL, tls_reg_read32(HR_PWM_CTL) | BIT(17 + channel * 2)); + tls_reg_write32(HR_PWM_CTL, tls_reg_read32(HR_PWM_CTL) & (~BIT(16 + channel * 2))); + } + else + return WM_FAILED; + } + + return WM_SUCCESS; +} + +/** + * @brief This function is used to set whether to loop + * + * @param[in] channel pwm channel NO.,range form 0 to 4 + * @param[in] loop_mode whether to loop + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_loop_mode_config(u8 channel, enum tls_pwm_loop_type loop_mode) +{ + if(channel > (PWM_CHANNEL_MAX_NUM - 1)) + return WM_FAILED; + + if (4 == channel) + { + if (WM_PWM_LOOP_TYPE_LOOP == loop_mode) + tls_reg_write32(HR_PWM_CH4_REG2, tls_reg_read32(HR_PWM_CH4_REG2) | BIT(1)); + else + tls_reg_write32(HR_PWM_CH4_REG2, tls_reg_read32(HR_PWM_CH4_REG2) & (~BIT(1))); + } + else + { + if (WM_PWM_LOOP_TYPE_LOOP == loop_mode) + tls_reg_write32(HR_PWM_CTL, tls_reg_read32(HR_PWM_CTL) | BIT(8 + channel)); + else + tls_reg_write32(HR_PWM_CTL, tls_reg_read32(HR_PWM_CTL) & (~BIT(8 + channel))); + } + + return WM_SUCCESS; +} + +/** + * @brief This function is used to set whether to inverse the output + * + * @param[in] channel pwm channel NO.,range form 0 to 4 + * @param[in] en ENABLE or DISABLE + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_out_inverse_cmd(u8 channel, bool en) +{ + if(channel > (PWM_CHANNEL_MAX_NUM - 1)) + return WM_FAILED; + + if (4 == channel) + { + if (ENABLE == en) + tls_reg_write32(HR_PWM_CH4_REG2, tls_reg_read32(HR_PWM_CH4_REG2) | BIT(0)); + else + tls_reg_write32(HR_PWM_CH4_REG2, tls_reg_read32(HR_PWM_CH4_REG2) & (~BIT(0))); + } + else + { + if (ENABLE == en) + tls_reg_write32(HR_PWM_CTL, tls_reg_read32(HR_PWM_CTL) | BIT(2 + channel)); + else + tls_reg_write32(HR_PWM_CTL, tls_reg_read32(HR_PWM_CTL) & (~BIT(2 + channel))); + } + + return WM_SUCCESS; +} + +/** + * @brief This function is used to set the number of period to be generated + * + * @param[in] channel pwm channel NO.,range form 0 to 4 + * @param[in] pnum the number of period to be generated,range from 0 to 255 + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_stoptime_by_period_config(u8 channel, u8 pnum) +{ + u32 temp = 0; + + if(channel > (PWM_CHANNEL_MAX_NUM - 1)) + return WM_FAILED; + + if (4 == channel) + { + temp = tls_reg_read32(HR_PWM_CH4_REG1) & ~0x000000FF; + temp |= pnum; + tls_reg_write32(HR_PWM_CH4_REG1, temp); + } + else + { + temp = tls_reg_read32(HR_PWM_PNUM) & ~(0xFF << channel * 8); + temp |= (pnum << (channel * 8)); + tls_reg_write32(HR_PWM_PNUM, temp); + + } + + return WM_SUCCESS; +} + +/** + * @brief This function is used to set output enable + * + * @param[in] channel pwm channel NO.,channel 0 or channel 4 + * @param[in] en ENABLE or DISABLE + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_output_en_cmd(u8 channel, bool en) +{ + if(channel != 0 && channel != 4) + return WM_FAILED; + + if (4 == channel) + { + if (ENABLE == en) + tls_reg_write32(HR_PWM_CAP2CTL, tls_reg_read32(HR_PWM_CAP2CTL) & (~BIT(2))); + else + tls_reg_write32(HR_PWM_CAP2CTL, tls_reg_read32(HR_PWM_CAP2CTL) | BIT(2)); + } + else + { + if (ENABLE == en) + tls_reg_write32(HR_PWM_CTL, tls_reg_read32(HR_PWM_CTL) & (~BIT(12))); + else + tls_reg_write32(HR_PWM_CTL, tls_reg_read32(HR_PWM_CTL) | BIT(12)); + } + + return WM_SUCCESS; +} + +/** + * @brief This function is used to set the dead time + * + * @param[in] channel pwm channel NO.,channel 0 or channel 2 + * @param[in] dten whether enalbe the deat time, ENABLE or DISABLE + * @param[in] dtclkdiv dead zone clock divider, range 0 to 3 + * @param[in] dtcnt the number of the counting clock cycle, range 0 to 255 + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_deadzone_config(u8 channel, bool dten, u8 dtclkdiv, u8 dtcnt) +{ + u32 temp = 0; + + if ((channel !=0 && channel != 2) || dtclkdiv > 3) + return WM_FAILED; + + if(ENABLE == dten) + { + temp = tls_reg_read32(HR_PWM_DTCTL) & ~0x00030000; + temp |= (dtclkdiv<<16); + tls_reg_write32(HR_PWM_DTCTL, temp);/* dead zone clock divider */ + + if (channel == 0 || channel == 1) + { + temp = tls_reg_read32(HR_PWM_DTCTL) & ~0x000000FF; + temp |= dtcnt; + tls_reg_write32(HR_PWM_DTCTL, temp);/* the number of the counting clock cycle */ + + tls_reg_write32(HR_PWM_DTCTL, tls_reg_read32(HR_PWM_CTL) | BIT(20)); /* whether enalbe the deat time */ + + } + else if (channel == 2 || channel == 3) + { + temp = tls_reg_read32(HR_PWM_DTCTL) & ~0x0000FF00; + temp |= (dtcnt<<8); + tls_reg_write32(HR_PWM_DTCTL, temp);/* the number of the counting clock cycle */ + + tls_reg_write32(HR_PWM_DTCTL, tls_reg_read32(HR_PWM_CTL) | BIT(21)); /* whether enalbe the deat time */ + } + } + else + { + if (channel == 0 || channel == 1) + { + tls_reg_write32(HR_PWM_DTCTL, tls_reg_read32(HR_PWM_CTL) & (~BIT(20))); /* whether enalbe the deat time */ + } + else if (channel == 2 || channel == 3) + { + tls_reg_write32(HR_PWM_DTCTL, tls_reg_read32(HR_PWM_CTL) & (~BIT(21))); /* whether enalbe the deat time */ + } + } + + return WM_SUCCESS; +} + +/** + * @brief This function is used to set whether to inverse the capture input + * + * @param[in] channel pwm channel NO.,channel 0 or channel 4 + * @param[in] en ENABLE or DISABLE + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_capture_inverse_cmd(u8 channel, bool en) +{ + if (channel != 0 && channel != 4) + return WM_FAILED; + + if (channel == 0) + { + if (ENABLE == en) + tls_reg_write32(HR_PWM_CTL, tls_reg_read32(HR_PWM_CTL) | BIT(25)); + else + tls_reg_write32(HR_PWM_CTL, tls_reg_read32(HR_PWM_CTL) & (~BIT(25))); + } + else + { + if (ENABLE == en) + tls_reg_write32(HR_PWM_CAP2CTL, tls_reg_read32(HR_PWM_CAP2CTL) | BIT(0)); + else + tls_reg_write32(HR_PWM_CAP2CTL, tls_reg_read32(HR_PWM_CAP2CTL) & (~BIT(0))); + } + + return WM_SUCCESS; +} + +/** + * @brief This function is used to set break mode + * + * @param[in] channel pwm channel NO.,channel 0 or channel 4 + * @param[in] en whether enable the break mode,ENABLE or DISABLE + * @param[in] brok when break + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_brake_mode_config(u8 channel, bool en, enum tls_pwm_brake_out_level brok) +{ + if(channel > (PWM_CHANNEL_MAX_NUM - 1)) + return WM_FAILED; + + if (ENABLE == en) + { + if (WM_PWM_BRAKE_OUT_HIGH == brok) + tls_reg_write32(HR_PWM_BRKCTL, tls_reg_read32(HR_PWM_BRKCTL) | BIT(3+channel)); + else + tls_reg_write32(HR_PWM_BRKCTL, tls_reg_read32(HR_PWM_BRKCTL) & (~BIT(3+channel))); + tls_reg_write32(HR_PWM_BRKCTL, tls_reg_read32(HR_PWM_BRKCTL) | BIT(11+channel)); + } + else + { + tls_reg_write32(HR_PWM_BRKCTL, tls_reg_read32(HR_PWM_BRKCTL) & (~BIT(11+channel))); + } + + return WM_SUCCESS; +} + +/** + * @brief This function is used to enable the capture mode + * + * @param[in] channel pwm channel NO.,channel 0 or channel 4 + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_capture_mode_config(u8 channel) +{ + if (channel != 0 && channel != 4) + return WM_FAILED; + if (channel == 0) + { + tls_reg_write32(HR_PWM_CTL, tls_reg_read32(HR_PWM_CTL) | BIT(24)); + } + else + { + tls_reg_write32(HR_PWM_CAP2CTL, tls_reg_read32(HR_PWM_CAP2CTL) | BIT(1)); + } + + return WM_SUCCESS; +} + +/** + * @brief This function is used to set the interrupt about the number of period + * + * @param[in] channel pwm channel,range from 0 to 4 + * @param[in] en enble or disable + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_stoptime_irq_cmd(u8 channel, bool en) +{ + if(channel > (PWM_CHANNEL_MAX_NUM - 1)) + return WM_FAILED; + + if (4 == channel) + { + if (en) + tls_reg_write32(HR_PWM_INTEN, tls_reg_read32(HR_PWM_INTEN) | BIT(4)); + else + tls_reg_write32(HR_PWM_INTEN, tls_reg_read32(HR_PWM_INTEN) & (~BIT(4))); + } + else + { + if (en) + tls_reg_write32(HR_PWM_INTEN, tls_reg_read32(HR_PWM_INTEN) | BIT(channel)); + else + tls_reg_write32(HR_PWM_INTEN, tls_reg_read32(HR_PWM_INTEN) & (~BIT(channel))); + } + + return WM_SUCCESS; +} + +/** + * @brief This function is used to set the interrupt about the + capture + * + * @param[in] channel pwm channel,channel 0 or channel 4 + * @param[in] int_type interrupt type + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_capture_irq_type_config(u8 channel, enum tls_pwm_cap_int_type int_type) +{ + if (channel != 0 && channel != 4) + return WM_FAILED; + + if (0 == channel) + { + if (WM_PWM_CAP_RISING_FALLING_EDGE_INT == int_type) + { + tls_reg_write32(HR_PWM_INTEN, tls_reg_read32(HR_PWM_INTEN) | BIT(5)); + tls_reg_write32(HR_PWM_INTEN, tls_reg_read32(HR_PWM_INTEN) | BIT(6)); + tls_reg_write32(HR_PWM_INTEN, tls_reg_read32(HR_PWM_INTEN) & (~BIT(7))); + } + else if (WM_PWM_CAP_RISING_EDGE_INT == int_type) + { + tls_reg_write32(HR_PWM_INTEN, tls_reg_read32(HR_PWM_INTEN) | BIT(5)); + tls_reg_write32(HR_PWM_INTEN, tls_reg_read32(HR_PWM_INTEN) & (~BIT(6))); + tls_reg_write32(HR_PWM_INTEN, tls_reg_read32(HR_PWM_INTEN) & (~BIT(7))); + } + else if (WM_PWM_CAP_FALLING_EDGE_INT == int_type) + { + tls_reg_write32(HR_PWM_INTEN, tls_reg_read32(HR_PWM_INTEN) | BIT(6)); + tls_reg_write32(HR_PWM_INTEN, tls_reg_read32(HR_PWM_INTEN) & (~BIT(5))); + tls_reg_write32(HR_PWM_INTEN, tls_reg_read32(HR_PWM_INTEN) & (~BIT(7))); + } + else if(WM_PWM_CAP_DMA_INT == int_type) + { + tls_reg_write32(HR_PWM_INTEN, tls_reg_read32(HR_PWM_INTEN) | BIT(7)); + tls_reg_write32(HR_PWM_INTEN, tls_reg_read32(HR_PWM_INTEN) & (~BIT(5))); + tls_reg_write32(HR_PWM_INTEN, tls_reg_read32(HR_PWM_INTEN) & (~BIT(6))); + } + } + else if (4 == channel) + { + if (WM_PWM_CAP_RISING_FALLING_EDGE_INT == int_type) + { + tls_reg_write32(HR_PWM_CAP2CTL, tls_reg_read32(HR_PWM_CAP2CTL) | BIT(8)); + tls_reg_write32(HR_PWM_CAP2CTL, tls_reg_read32(HR_PWM_CAP2CTL) | BIT(9)); + tls_reg_write32(HR_PWM_CAP2CTL, tls_reg_read32(HR_PWM_CAP2CTL) & (~BIT(10))); + } + else if (WM_PWM_CAP_RISING_EDGE_INT == int_type) + { + tls_reg_write32(HR_PWM_CAP2CTL, tls_reg_read32(HR_PWM_CAP2CTL) | BIT(8)); + tls_reg_write32(HR_PWM_CAP2CTL, tls_reg_read32(HR_PWM_CAP2CTL) & (~BIT(9))); + tls_reg_write32(HR_PWM_CAP2CTL, tls_reg_read32(HR_PWM_CAP2CTL) & (~BIT(10))); + } + else if (WM_PWM_CAP_FALLING_EDGE_INT == int_type) + { + tls_reg_write32(HR_PWM_CAP2CTL, tls_reg_read32(HR_PWM_CAP2CTL) | BIT(9)); + tls_reg_write32(HR_PWM_CAP2CTL, tls_reg_read32(HR_PWM_CAP2CTL) & (~BIT(8))); + tls_reg_write32(HR_PWM_CAP2CTL, tls_reg_read32(HR_PWM_CAP2CTL) & (~BIT(10))); + } + else if(WM_PWM_CAP_DMA_INT == int_type) + { + tls_reg_write32(HR_PWM_CAP2CTL, tls_reg_read32(HR_PWM_CAP2CTL) | BIT(10)); + tls_reg_write32(HR_PWM_CAP2CTL, tls_reg_read32(HR_PWM_CAP2CTL) & (~BIT(8))); + tls_reg_write32(HR_PWM_CAP2CTL, tls_reg_read32(HR_PWM_CAP2CTL) & (~BIT(9))); + } + } + + return WM_SUCCESS; +} + +/** + * @brief This function is used to initial pwm(out mode) + * + * @param[in] pwm_param structure containing the initialization parameters + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_out_init(pwm_init_param pwm_param) +{ + int ret=0; + int pwm_status = 0; + + if (pwm_param.channel > (PWM_CHANNEL_MAX_NUM - 1)) + return WM_FAILED; + + if(tls_reg_read32(HR_PWM_CTL) & BIT(27 + pwm_param.channel)) + { + tls_pwm_stop(pwm_param.channel); + pwm_status = 1; + } + + /* set output mode */ + ret = tls_pwm_out_mode_config(pwm_param.channel, pwm_param.mode); + if (ret!=WM_SUCCESS) + return WM_FAILED; + + if (WM_PWM_OUT_MODE_MC == pwm_param.mode) + { + /* set dead time */ + ret = tls_pwm_deadzone_config(pwm_param.channel, pwm_param.dten, pwm_param.dtclkdiv, pwm_param.dtcnt); + if (ret!=WM_SUCCESS) + return WM_FAILED; + } + + /* set count type */ + tls_pwm_cnt_type_config(pwm_param.channel, pwm_param.cnt_type); + + /* set period value and duty radio */ + tls_pwm_freq_config(pwm_param.channel, pwm_param.clkdiv, pwm_param.period); + tls_pwm_duty_config(pwm_param.channel, pwm_param.duty); + + /* set cycle type */ + tls_pwm_loop_mode_config(pwm_param.channel, pwm_param.loop_type); + + /* set output whether is inverse */ + tls_pwm_out_inverse_cmd(pwm_param.channel, pwm_param.inverse_en); + + /* set period number of generating */ + tls_pwm_stoptime_by_period_config(pwm_param.channel, pwm_param.pnum); + + /* set interrupt of period number whether is enable */ + tls_pwm_stoptime_irq_cmd(pwm_param.channel, pwm_param.pnum_int); + + /* set output status */ + if (pwm_param.channel == 0 || pwm_param.channel == 4) + tls_pwm_output_en_cmd(pwm_param.channel, WM_PWM_OUT_EN_STATE_OUT); + if (pwm_param.mode == WM_PWM_OUT_MODE_ALLSYC && pwm_param.channel == 0) + tls_pwm_output_en_cmd(4, WM_PWM_OUT_EN_STATE_OUT); + if(pwm_status) + { + tls_pwm_start(pwm_param.channel); + } + return WM_SUCCESS; +} + +/** + * @brief This function is used to initial pwm(capture mode) + * + * @param[in] channel pwm channel, channel 0 or channel 4 + * @param[in] clkdiv clock divider, range 0 to 65535 + * @param[in] inverse_en whether the input signal is reversed + * @param[in] int_type interrupt type + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_cap_init(u8 channel, u16 clkdiv, bool inverse_en, enum tls_pwm_cap_int_type int_type) +{ + if (channel != 0 && channel != 4) + return WM_FAILED; + + /* set clock divider and period value */ + tls_pwm_freq_config(channel, clkdiv, 0xFF); + + /* set input of capture mode whether is inverse */ + tls_pwm_capture_inverse_cmd(channel, inverse_en); + + /* set the capture mode */ + tls_pwm_capture_mode_config(channel); + + /* set count type (only edge alignment in the capture mode) */ + tls_pwm_cnt_type_config(channel, WM_PWM_CNT_TYPE_EDGE_ALLGN_CAP); + + /* set output status */ + tls_pwm_output_en_cmd(channel, WM_PWM_OUT_EN_STATE_TRI); + + /* set cycle mode (must be set int the capture mode) */ + tls_pwm_loop_mode_config(channel, WM_PWM_LOOP_TYPE_LOOP); + + /* set interrupt type */ + tls_pwm_capture_irq_type_config(channel, int_type); + + return WM_SUCCESS; +} + +/** + * @brief This function is used to start pwm + * + * @param[in] channel pwm channel, range from 0 to 4 + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_start(u8 channel) +{ + if(channel > (PWM_CHANNEL_MAX_NUM - 1)) + return WM_FAILED; + + tls_reg_write32(HR_PWM_CTL, tls_reg_read32(HR_PWM_CTL) | BIT(27 + channel)); /* start counter */ + + return WM_SUCCESS; +} + +/** + * @brief This function is used to stop pwm + * + * @param[in] channel pwm channel, range from 0 to 4 + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_stop(u8 channel) +{ + if(channel > (PWM_CHANNEL_MAX_NUM - 1)) + return WM_FAILED; + + tls_reg_write32(HR_PWM_CTL, tls_reg_read32(HR_PWM_CTL) & (~BIT(27 + channel)));/* stop counter */ + + return WM_SUCCESS; +} + +/** + * @brief This function is used to stop pwm + * + * @param[in] channel pwm channel no, range form 0 to 4 + * @param[in] freq frequency, range from 1 to 156250 + * + * @return None + * + * @note None + */ +void tls_pwm_freq_set(u8 channel, u32 freq) +{ + u16 clkdiv=0; + tls_sys_clk sysclk; + + if(channel > (PWM_CHANNEL_MAX_NUM - 1)) + return; + + tls_sys_clk_get(&sysclk); + + clkdiv = sysclk.apbclk*UNIT_MHZ/256/freq; + tls_pwm_stop(channel); + tls_pwm_freq_config(channel, clkdiv, 255); + tls_pwm_start(channel); +} + +/** + * @brief This function is used to set duty radio + * + * @param[in] channel pwm channel NO., range form 0 to 4 + * @param[in] duty duty radio, range from 0 to 255 + * + * @return None + * + * @note None + */ +void tls_pwm_duty_set(u8 channel, u8 duty) +{ + if(channel > (PWM_CHANNEL_MAX_NUM - 1)) + return; + + tls_pwm_duty_config(channel, duty); +} + +/** + * @brief This function is used to initial pwm + * + * @param[in] channel pwm channel, range from 0 to 4 + * @param[in] freq freq range from 1 to 156250 + * @param[in] duty duty range from 0 to 255 + * @param[in] pnum period num,range from 0 to 255 + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note None + */ +int tls_pwm_init(u8 channel,u32 freq, u8 duty, u8 pnum) +{ + pwm_init_param pwm_param; + int ret=-1; + tls_sys_clk sysclk; + + tls_sys_clk_get(&sysclk); + + memset(&pwm_param, 0, sizeof(pwm_init_param)); + pwm_param.period = 255; + pwm_param.cnt_type = WM_PWM_CNT_TYPE_EDGE_ALIGN_OUT; + pwm_param.loop_type = WM_PWM_LOOP_TYPE_LOOP; + pwm_param.mode = WM_PWM_OUT_MODE_INDPT; + pwm_param.inverse_en = DISABLE; + pwm_param.pnum = pnum; + pwm_param.pnum_int = DISABLE; + pwm_param.duty = duty; + pwm_param.channel = channel; + pwm_param.clkdiv = sysclk.apbclk*UNIT_MHZ/256/freq; +// printf("clkdiv:%d\n", pwm_param.clkdiv); + ret = tls_pwm_out_init(pwm_param); +// tls_pwm_start(channel); + + return ret; +} +/** + * @brief This function is used to get pwm info + * + * @param[in] channel pwm channel, range from 0 to 4 + * @param[in] clkdiv is a pointer to clkdiv, clkdiv range from 1 to 65535 + * @param[in] duty is a pointer to duty, duty range from 0 to 255 + * @param[in] period is a pointer to period, period range from 0 to 255 + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + */ +int tls_pwm_get_info(u8 channel, u32 *clkdiv, u8 *duty, u8 *period) +{ + u32 temp = 0; + + if(channel > (PWM_CHANNEL_MAX_NUM - 1)) + return WM_FAILED; + + if (4 == channel) + { + temp = tls_reg_read32(HR_PWM_CH4_REG1) & 0xFFFF0000; + *clkdiv = (temp >> 16); + + temp = tls_reg_read32(HR_PWM_CH4_REG2) & 0x0000FF00; + *duty = (temp >> 8); + + temp = tls_reg_read32(HR_PWM_CH4_REG1) & 0x0000FF00; + *period = (temp >> 8); + } + else + { + temp = tls_reg_read32(HR_PWM_CLKDIV01 + (channel / 2) * 4) & (0xFFFF << ((channel % 2) * 16)); + *clkdiv = (temp >> ((channel % 2) * 16)); + + temp = tls_reg_read32(HR_PWM_CMPDAT) & (0xFF << channel * 8); + *duty = (temp >> (channel * 8)); + + temp = tls_reg_read32(HR_PWM_PERIOD) & (0xFF << channel * 8); + *period = (temp >> (channel * 8)); + } + + return WM_SUCCESS; +} + + + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_reflector.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_reflector.c new file mode 100644 index 00000000..0b515aee --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_reflector.c @@ -0,0 +1,60 @@ +/** + * @file wm_reflector.c + * + * @brief reflector driver + * + * @author dave + * + * Copyright (c) 2016 Winner Microelectronics Co., Ltd. + */ +#include +#include +#include +#include "wm_regs.h" +#include "wm_gpio.h" + +/** + * @brief This function is used to initial the reflector. + * + * @param[in] ctr_io ctrl io + * + * @return None + * + * @note None + */ +void tls_reflector_open(int ctr_io) +{ + tls_gpio_cfg((enum tls_io_name)ctr_io, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_FLOATING); + tls_gpio_write((enum tls_io_name)ctr_io, 1); +} + +/** + * @brief This function is used to close the reflector. + * + * @param[in] ctr_io ctrl io + * + * @return None + * + * @note None + */ +void tls_reflector_close(int ctr_io) +{ + tls_gpio_cfg((enum tls_io_name)ctr_io, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_FLOATING); + tls_gpio_write((enum tls_io_name)ctr_io, 0); +} + +/** + * @brief This function is used to read reflector output status. + * + * @param[in] out_io output io + * + * @retval output status + * + * @note None + */ +int tls_reflector_output_status(int out_io) +{ + tls_gpio_cfg((enum tls_io_name)out_io, WM_GPIO_DIR_INPUT, WM_GPIO_ATTR_FLOATING); + return tls_gpio_read((enum tls_io_name)out_io); +} + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_rtc.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_rtc.c new file mode 100644 index 00000000..504a7887 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_rtc.c @@ -0,0 +1,170 @@ +/** + * @file wm_rtc.c + * + * @brief rtc Driver Module + * + * @author dave + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#include +#include +#include +#include "wm_regs.h" +#include "wm_rtc.h" + +#include "wm_irq.h" +#include "tls_common.h" + +struct rtc_irq_context { + tls_rtc_irq_callback callback; + void *arg; +}; + +static struct rtc_irq_context rtc_context = {0}; + + +/** + * @brief This function is used to set pmu rtc time + * + * @param[in] tblock time value + * + * @return None + * + * @note None + */ +void tls_set_rtc(struct tm *tblock) +{ + int ctrl1 = 0; + int ctrl2 = 0; + + ctrl2 = tls_reg_read32(HR_PMU_RTC_CTRL2); /* disable */ + ctrl2 &= ~(1 << 16); + tls_reg_write32(HR_PMU_RTC_CTRL2, ctrl2); + + ctrl1 |= tblock->tm_sec; + ctrl1 |= tblock->tm_min << 8; + ctrl1 |= tblock->tm_hour << 16; + ctrl1 |= tblock->tm_mday << 24; + tls_reg_write32(HR_PMU_RTC_CTRL1, ctrl1); + + ctrl2 = 0; + ctrl2 |= tblock->tm_mon; + ctrl2 |= tblock->tm_year << 8; + tls_reg_write32(HR_PMU_RTC_CTRL2, ctrl2); + + ctrl2 = tls_reg_read32(HR_PMU_RTC_CTRL2); /* enable */ + ctrl2 |= (1 << 16); + tls_reg_write32(HR_PMU_RTC_CTRL2, ctrl2); +} + +/** + * @brief This function is used to get pmu rtc time + * + * @param[out] tblock time value + * + * @return None + * + * @note None + */ +void tls_get_rtc(struct tm *tblock) +{ + int ctrl1 = 0; + int ctrl2 = 0; + + ctrl1 = tls_reg_read32(HR_PMU_RTC_CTRL1); + ctrl2 = tls_reg_read32(HR_PMU_RTC_CTRL2); + tblock->tm_year = ((int)((int)ctrl2 & 0x00007f00) >> 8); + tblock->tm_mon = (ctrl2 & 0x0000000f); + tblock->tm_mday = (ctrl1 & 0x1f000000) >> 24; + tblock->tm_hour = (ctrl1 & 0x001f0000) >> 16; + tblock->tm_min = (ctrl1 & 0x00003f00) >> 8; + tblock->tm_sec = ctrl1 & 0x0000003f; +} + +void PMU_RTC_IRQHandler(void) +{ + if (tls_reg_read32(HR_PMU_INTERRUPT_SRC) & BIT(5)) /* rtc interrupt */ + { + tls_reg_write32(HR_PMU_INTERRUPT_SRC, BIT(5)); /* clear rtc interrupt */ + + if (NULL != rtc_context.callback) + rtc_context.callback(rtc_context.arg); + } + return; +} + +/** + * @brief This function is used to register pmu rtc interrupt + * + * @param[in] callback the rtc interrupt call back function + * @param[in] arg parameter of call back function + * + * @return None + * + * @note + * user not need clear interrupt flag. + * rtc callback function is called in interrupt, + * so can not operate the critical data in the callback fuuction, + * recommendation to send messages to other tasks to operate it. + */ +void tls_rtc_isr_register(tls_rtc_irq_callback callback, void *arg) +{ + rtc_context.callback = callback; + rtc_context.arg = arg; + +// tls_reg_write32(HR_PMU_INTERRUPT_MASK, tls_reg_read32(HR_PMU_INTERRUPT_MASK) & (~BIT(4))); + + tls_irq_enable(PMU_RTC_INT); + + return; +} + +/** + * @brief This function is used to start pmu rtc timer + * + * @param[in] tblock timer value + * + * @return None + * + * @note None + */ +void tls_rtc_timer_start(struct tm *tblock) +{ + int ctrl1 = 0; + int ctrl2 = 0; + + tls_irq_enable(PMU_RTC_INT); + + ctrl1 |= tblock->tm_sec; + ctrl1 |= tblock->tm_min << 8; + ctrl1 |= tblock->tm_hour << 16; + ctrl1 |= tblock->tm_mday << 24; + + ctrl2 |= tblock->tm_mon; + ctrl2 |= tblock->tm_year << 8; + tls_reg_write32(HR_PMU_RTC_CTRL2, ctrl2 | BIT(16)); + + tls_reg_write32(HR_PMU_RTC_CTRL1, ctrl1 | BIT(31));/* must set the enable */ + + return; +} + +/** + * @brief This function is used to stop pmu rtc timer + * + * @param None + * + * @return None + * + * @note This function also is used to clear rtc timer interrupt + */ +void tls_rtc_timer_stop(void) +{ + tls_reg_write32(HR_PMU_RTC_CTRL1, tls_reg_read32(HR_PMU_RTC_CTRL1) & (~BIT(31))); + + tls_irq_disable(PMU_RTC_INT); + + return; +} + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_timer.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_timer.c new file mode 100644 index 00000000..c749a5b9 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_timer.c @@ -0,0 +1,287 @@ +/** + * @file wm_timer.c + * + * @brief Timer Driver Module + * + * @author dave + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#include "wm_type_def.h" +#include "wm_timer.h" +#include "wm_regs.h" +#include "wm_irq.h" +#include "wm_cpu.h" +#include "stdio.h" +#include "tls_common.h" + +enum tls_timer_id{ + TLS_TIMER_ID_0 = 0, // used by delay (sleep, msleep, usleep) + TLS_TIMER_ID_1, + TLS_TIMER_ID_2, + TLS_TIMER_ID_3, + TLS_TIMER_ID_4, + TLS_TIMER_ID_5, + TLS_TIMER_ID_MAX +}; + +#define TIM0_USED_BY_DELAY 0 + +struct timer_irq_context { + tls_timer_irq_callback callback; + void *arg; +}; + +static struct timer_irq_context timer_context[TLS_TIMER_ID_MAX] = {{0,0}}; +static u8 wm_timer_bitmap = 0; + +static void timer_clear_irq(int timer_id) +{ + //printf("timer_clear_irq\r\n"); + tls_reg_write32(HR_TIMER0_5_CSR, tls_reg_read32(HR_TIMER0_5_CSR)|TLS_TIMER_INT_CLR(timer_id)); +} + +static void timer_irq_callback(void *p) +{ + u8 timer_id; + + timer_id = (u8)(u32)p; + + //printf("timer_irq_callback\r\n"); + timer_clear_irq(timer_id); + + if (NULL != timer_context[timer_id].callback) + timer_context[timer_id].callback(timer_context[timer_id].arg); + + return; +} + +void TIM0_IRQHandler(void) +{ + timer_irq_callback((void *)TLS_TIMER_ID_0); +} +void TIM1_IRQHandler(void) +{ + timer_irq_callback((void *)TLS_TIMER_ID_1); +} +void TIM2_IRQHandler(void) +{ + timer_irq_callback((void *)TLS_TIMER_ID_2); +} +void TIM3_IRQHandler(void) +{ + timer_irq_callback((void *)TLS_TIMER_ID_3); +} +void TIM4_IRQHandler(void) +{ + timer_irq_callback((void *)TLS_TIMER_ID_4); +} +void TIM5_IRQHandler(void) +{ + timer_irq_callback((void *)TLS_TIMER_ID_5); +} + +/** + * @brief This function is used to create the timer + * + * @param[in] cfg timer configuration + * + * @retval WM_TIMER_ID_INVALID failed + * @retval other timer id[0~5] + * + * @note + * user not need clear interrupt flag. + * timer callback function is called in interrupt, + * so can not operate the critical data in the callback fuuction, + * recommendation to send messages to other tasks to operate it. + */ +u8 tls_timer_create(struct tls_timer_cfg *cfg) +{ + u8 i; + int timer_csr; + + for (i = TLS_TIMER_ID_1; i < TLS_TIMER_ID_MAX; i++) + { + if (!(wm_timer_bitmap & BIT(i))) + break; + } + + if (TLS_TIMER_ID_MAX == i) + return WM_TIMER_ID_INVALID; + + wm_timer_bitmap |= BIT(i); + timer_context[i].callback = cfg->callback; + timer_context[i].arg = cfg->arg; + + tls_sys_clk sysclk; + + tls_sys_clk_get(&sysclk); + tls_reg_write32(HR_TIMER_CFG, sysclk.apbclk-1); + + timer_csr = tls_reg_read32(HR_TIMER0_5_CSR); + if (!cfg->is_repeat) + timer_csr |= TLS_TIMER_ONE_TIME(i); + else + timer_csr &= ~(TLS_TIMER_ONE_TIME(i)); + if (TLS_TIMER_UNIT_MS == cfg->unit) + timer_csr |= TLS_TIMER_MS_UNIT(i); + else + timer_csr &= ~(TLS_TIMER_MS_UNIT(i)); + tls_reg_write32(HR_TIMER0_5_CSR, timer_csr | TLS_TIMER_INT_CLR(i)); + if(cfg->timeout){ + tls_reg_write32(HR_TIMER0_PRD + 0x04 * i, cfg->timeout); + } + + tls_irq_enable(TIMER0_INT + i); + + return i; +} + +/** + * @brief This function is used to start the timer + * + * @param[in] timer_id timer id[0~5] + * + * @return None + * + * @note None + */ +void tls_timer_start(u8 timer_id) +{ + if (!(wm_timer_bitmap & BIT(timer_id))) + return; + + tls_reg_write32(HR_TIMER0_5_CSR, tls_reg_read32(HR_TIMER0_5_CSR)|TLS_TIMER_INT_EN(timer_id)| TLS_TIMER_EN(timer_id)); + + return; +} + +/** + * @brief This function is used to stop the timer + * + * @param[in] timer_id timer id[0~5] + * + * @return None + * + * @note None + */ +void tls_timer_stop(u8 timer_id) +{ + if (!(wm_timer_bitmap & BIT(timer_id))) + return; + + tls_reg_write32(HR_TIMER0_5_CSR, tls_reg_read32(HR_TIMER0_5_CSR)|TLS_TIMER_INT_CLR(timer_id)); + tls_reg_write32(HR_TIMER0_5_CSR, tls_reg_read32(HR_TIMER0_5_CSR) &~ TLS_TIMER_EN(timer_id)); + + return; +} + +/** + * @brief This function is used to change a timer wait time + * + * @param[in] timer_id timer id[0~5] + * + * @param[in] newtime new wait time + * + * @retval None + * + * @note If the timer does not start, this function will start the timer + */ +void tls_timer_change(u8 timer_id, u32 newtime) +{ + if (!(wm_timer_bitmap & BIT(timer_id))) + return; + + tls_timer_stop(timer_id); + if (newtime) + tls_reg_write32(HR_TIMER0_PRD + 0x04 * timer_id, newtime); + tls_timer_start(timer_id); + + return; +} + +/** + * @brief This function is used to delete the timer + * + * @param[in] timer_id timer id[0~5] + * + * @return None + * + * @note None + */ +void tls_timer_destroy(u8 timer_id) +{ + if (!(wm_timer_bitmap & BIT(timer_id))) + return; + + tls_timer_stop(timer_id); + + timer_context[timer_id].callback = NULL; + timer_context[timer_id].arg = NULL; + + wm_timer_bitmap &= ~BIT(timer_id); + + return; +} + +/** + * @brief This function is create a delay to elapse + * + * @param[in] timeout the value writed into TMR0_PRD + * @param[in] m_flag millisecond flag in TIMER0 + * + * @return None + * + * @note None + */ +int tls_delay_via_timer(unsigned int timeout, unsigned int m_flag) +{ + int ret = 0; + tls_sys_clk sysclk; + int timer_csr = 0; + + if (0 == timeout) + return ret; + + /* + * no lock + * + */ + tls_irq_disable(TIMER0_INT + TIM0_USED_BY_DELAY); + tls_reg_write32(HR_TIMER0_PRD + 0x04 * TIM0_USED_BY_DELAY, + timeout); + + tls_sys_clk_get(&sysclk); + tls_reg_write32(HR_TIMER_CFG, sysclk.apbclk-1); + + timer_csr = tls_reg_read32(HR_TIMER0_5_CSR); + //printf("%d\r\n",timer_csr); + + + if (TIMER_MS_UNIT_FLAG == m_flag) + timer_csr |= TLS_TIMER_MS_UNIT(TIM0_USED_BY_DELAY); + else if (TIMER_US_UNIT_FLAG == m_flag) + timer_csr &= ~(TLS_TIMER_MS_UNIT(TIM0_USED_BY_DELAY)); + + timer_csr |= TLS_TIMER_ONE_TIME(TIM0_USED_BY_DELAY); + timer_csr |= TLS_TIMER_INT_CLR(TIM0_USED_BY_DELAY); + timer_csr |= (TLS_TIMER_INT_EN(TIM0_USED_BY_DELAY)); + timer_csr |= TLS_TIMER_EN(TIM0_USED_BY_DELAY); + + tls_reg_write32(HR_TIMER0_5_CSR, timer_csr); + //printf("wait\r\n"); + while (!(tls_reg_read32(HR_TIMER0_5_CSR) + & (TLS_TIMER_INT_CLR(TIM0_USED_BY_DELAY)))) + ; + //printf("timeout\r\n"); + timer_csr |= TLS_TIMER_INT_CLR(TIM0_USED_BY_DELAY); + tls_reg_write32(HR_TIMER0_5_CSR, timer_csr); + tls_irq_enable(TIMER0_INT + TIM0_USED_BY_DELAY); + /* + * no unlock + * + */ + + return ret; +} + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_uart.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_uart.c new file mode 100644 index 00000000..99e24d8f --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_uart.c @@ -0,0 +1,1542 @@ +/** + * @file wm_uart.c + * + * @brief uart Driver Module + * + * @author dave + * + * Copyright (c) 2015 Winner Microelectronics Co., Ltd. + */ + +#include +#include "wm_regs.h" +#include "wm_uart.h" +#include "wm_debug.h" +#include "wm_irq.h" +#include "wm_config.h" +//#include "wm_mem.h" +#include "wm_dma.h" +#include "wm_cpu.h" + +#include "misc.h" + +#if TLS_CONFIG_UART + +#define DEBUG_RX_LEN 0 +#define RX_CACHE_LIMIT 128 + +struct tls_uart_port uart_port[3]; +//void (*tx_sent_callback)(struct tls_uart_port *port) = NULL; +static void tls_uart_tx_chars(struct tls_uart_port *port); +extern s16 uart_tx_sent_callback(struct tls_uart_port *port); +void tls_uart_tx_callback_register(u16 uart_no, + s16(*tx_callback) (struct tls_uart_port * + port)); + +const u32 baud_rates[] = { + 2000000, 1500000, 1250000, + 1000000, 921600, 460800, + 230400, 115200, 57600, 38400, + 19200, 9600, 4800, 2400, + 1800, 1200, 600 +}; + +static void tls_uart_tx_enable(struct tls_uart_port *port); +static void tls_uart_tx_chars(struct tls_uart_port *port); + +void Uart0Init(void) +{ + u32 bd; + + u32 apbclk; + tls_sys_clk sysclk; + + tls_sys_clk_get(&sysclk); + apbclk = sysclk.apbclk * 1000000; + +/* baud rate register value = apb_clk/(16*115200) */ +/* 濡傛灉APB鏃堕挓鏄40MHz锛 */ +/* 娉㈢壒鐜囧瘎瀛樺櫒鐨勫艰缃负 115200 : 21 */ +/* 9600bps : 260 */ + { + bd = (apbclk / (16 * 115200) - + 1) | (((apbclk % (115200 * 16)) * 16 / (115200 * 16)) << 16); + tls_reg_write32(HR_UART0_BAUD_RATE_CTRL, bd); + /* Line control register : Normal,No parity,1 stop,8 bits, only use tx */ + tls_reg_write32(HR_UART0_LINE_CTRL, ULCON_WL8 | ULCON_TX_EN); + + /* disable auto flow control */ + tls_reg_write32(HR_UART0_FLOW_CTRL, 0); + /* disable dma */ + tls_reg_write32(HR_UART0_DMA_CTRL, 0); + /* one byte tx */ + tls_reg_write32(HR_UART0_FIFO_CTRL, 0); + /* disable interrupt */ + tls_reg_write32(HR_UART0_INT_MASK, 0xFF); + } +} + +void UartRegInit(int uart_no) +{ + u32 bd; + u32 apbclk; + tls_sys_clk sysclk; + + tls_sys_clk_get(&sysclk); + apbclk = sysclk.apbclk * 1000000; + +/* baud rate register value = apb_clk/(16*115200) */ +/* 濡傛灉APB鏃堕挓鏄40MHz锛 */ +/* 娉㈢壒鐜囧瘎瀛樺櫒鐨勫艰缃负 115200 : 21 */ +/* 9600bps : 260 */ + if (TLS_UART_0 == uart_no) + { + bd = (apbclk / (16 * 115200) - 1) | (((apbclk % (115200 * 16)) * 16 / (115200 * 16)) << 16); + tls_reg_write32(HR_UART0_BAUD_RATE_CTRL, bd); + /* Line control register : Normal,No parity,1 stop,8 bits, only use tx */ + tls_reg_write32(HR_UART0_LINE_CTRL, ULCON_WL8 | ULCON_TX_EN); + + /* disable auto flow control */ + tls_reg_write32(HR_UART0_FLOW_CTRL, 0); + /* disable dma */ + tls_reg_write32(HR_UART0_DMA_CTRL, 0); + /* one byte tx */ + tls_reg_write32(HR_UART0_FIFO_CTRL, 0); + /* disable interrupt */ + tls_reg_write32(HR_UART0_INT_MASK, 0xFF); + } + + if (TLS_UART_1 == uart_no) + { + /* 4 byte tx, 8 bytes rx */ + tls_reg_write32(HR_UART1_FIFO_CTRL, (0x01 << 2) | (0x02 << 4)); + /* enable rx timeout, disable rx dma, disable tx dma */ + tls_reg_write32(HR_UART1_DMA_CTRL, (8 << 3) | (1 << 2)); + /* enable rx/timeout interrupt */ + tls_reg_write32(HR_UART1_INT_MASK, ~(3 << 2)); + + // uart1 + } + if (TLS_UART_2 == uart_no) + { + /* 4 byte tx, 8 bytes rx */ + tls_reg_write32(HR_UART2_FIFO_CTRL, (0x01 << 2) | (0x02 << 4)); + /* enable rx timeout, disable rx dma, disable tx dma */ + tls_reg_write32(HR_UART2_DMA_CTRL, (8 << 3) | (1 << 2)); + /* enable rx/timeout interrupt */ + tls_reg_write32(HR_UART2_INT_MASK, ~(3 << 2)); + } +} + +int tls_uart_check_baudrate(u32 baudrate) +{ + int i; + + for (i = 0; i < sizeof(baud_rates) / sizeof(u32); i++) + { + if (baudrate == baud_rates[i]) + return 1; + } +/* not found match baudrate */ + return -1; +} + +u32 tls_uart_get_baud_rate(struct tls_uart_port * port) +{ + if ((port != NULL) && (port->regs != NULL)) + return port->opts.baudrate; + else + return 0; +} + +int tls_uart_set_baud_rate_inside(struct tls_uart_port *port, u32 baudrate) +{ + int index; + u32 value; + u32 apbclk; + tls_sys_clk sysclk; + + + index = tls_uart_check_baudrate(baudrate); + if (index < 0) + return WM_FAILED; + tls_sys_clk_get(&sysclk); + apbclk = sysclk.apbclk * 1000000; + value = (apbclk / (16 * baudrate) - 1) | + (((apbclk % (baudrate * 16)) * 16 / (baudrate * 16)) << 16); + TLS_DBGPRT_INFO("value = 0x%x\n", value); + port->regs->UR_BD = value; + + port->opts.baudrate = baudrate; + TLS_DBGPRT_INFO("UR_BR = 0x%x\n", port->regs->UR_BD); + + return WM_SUCCESS; +} + + +int tls_uart_set_parity_inside(struct tls_uart_port *port, + TLS_UART_PMODE_T paritytype) +{ + if (port == NULL) + return WM_FAILED; + + port->opts.paritytype = paritytype; + + if (paritytype == TLS_UART_PMODE_DISABLED) + port->regs->UR_LC &= ~ULCON_PMD_EN; + else if (paritytype == TLS_UART_PMODE_EVEN) + { + port->regs->UR_LC &= ~ULCON_PMD_MASK; + port->regs->UR_LC |= ULCON_PMD_EVEN; + } + else if (paritytype == TLS_UART_PMODE_ODD) + { + port->regs->UR_LC &= ~ULCON_PMD_MASK; + port->regs->UR_LC |= ULCON_PMD_ODD; + } + else + return WM_FAILED; + + return WM_SUCCESS; + +} + +TLS_UART_PMODE_T tls_uart_get_parity(struct tls_uart_port * port) +{ + return port->opts.paritytype; +} + +int tls_uart_set_data_bits(struct tls_uart_port *port, + TLS_UART_CHSIZE_T charlength) +{ + if (!port) + return WM_FAILED; + + port->opts.charlength = charlength; + + port->regs->UR_LC &= ~ULCON_WL_MASK; + + if (charlength == TLS_UART_CHSIZE_5BIT) + port->regs->UR_LC |= ULCON_WL5; + else if (charlength == TLS_UART_CHSIZE_6BIT) + port->regs->UR_LC |= ULCON_WL6; + else if (charlength == TLS_UART_CHSIZE_7BIT) + port->regs->UR_LC |= ULCON_WL7; + else if (charlength == TLS_UART_CHSIZE_8BIT) + port->regs->UR_LC |= ULCON_WL8; + else + return WM_FAILED; + + return WM_SUCCESS; +} + +TLS_UART_CHSIZE_T tls_uart_get_data_bits(struct tls_uart_port * port) +{ + return port->opts.charlength; +} + +int tls_uart_set_stop_bits_inside(struct tls_uart_port *port, + TLS_UART_STOPBITS_T stopbits) +{ + if (!port) + return WM_FAILED; + + port->opts.stopbits = stopbits; + + if (stopbits == TLS_UART_TWO_STOPBITS) + port->regs->UR_LC |= ULCON_STOP_2; + else + port->regs->UR_LC &= ~ULCON_STOP_2; + + return WM_SUCCESS; +} + +TLS_UART_STOPBITS_T tls_uart_get_stop_bits(struct tls_uart_port * port) +{ + return port->opts.stopbits; +} + +TLS_UART_STATUS_T tls_uart_set_flow_ctrl(struct tls_uart_port * port, + TLS_UART_FLOW_CTRL_MODE_T flow_ctrl) +{ + TLS_UART_STATUS_T status = TLS_UART_STATUS_OK; + + if (!port) + return TLS_UART_STATUS_ERROR; + +// port->opts.flow_ctrl = flow_ctrl; +// //涓嶈兘鍦ㄨ繖閲屼慨鏀癸紝涓轰簡閰嶅悎閫忎紶鍜孉T鎸囦护锛岃蒋浠朵細鑷繁淇敼flowctrl閰嶇疆锛屼絾鏄弬鏁拌繕鏄浐瀹氫笉鍙樼殑 +//printf("\nport %d flow ctrl==%d\n",port->uart_no,flow_ctrl); + switch (flow_ctrl) + { + case TLS_UART_FLOW_CTRL_NONE: + port->regs->UR_FC = 0; + break; + case TLS_UART_FLOW_CTRL_HARDWARE: + if (TLS_UART_FLOW_CTRL_HARDWARE == port->opts.flow_ctrl) + { + port->regs->UR_FC = (1UL << 0) | (6UL << 2); + } + break; + default: + return TLS_UART_STATUS_ERROR; + } + + return status; +} + +void tls_uart_set_fc_status(int uart_no, TLS_UART_FLOW_CTRL_MODE_T status) +{ + struct tls_uart_port *port; + + if (TLS_UART_0 == uart_no) + { + port = &uart_port[0]; + } + else if (TLS_UART_1 == uart_no) + { + port = &uart_port[1]; + } + else + { + port = &uart_port[2]; + } + + port->fcStatus = status; + //printf("\nset fc status=%d\n",status); + tls_uart_set_flow_ctrl(port, status); + if (TLS_UART_FLOW_CTRL_HARDWARE == port->opts.flow_ctrl && 0 == status && port->hw_stopped) // 鍑嗗鍏抽棴娴佹帶鏃讹紝鍙戠幇tx宸茬粡鍋滄锛岄渶瑕佸啀鎵撳紑tx + { + tls_uart_tx_enable(port); + tls_uart_tx_chars(port); + port->hw_stopped = 0; + } +} + +void tls_uart_rx_disable(struct tls_uart_port *port) +{ + u32 ucon; + + ucon = port->regs->UR_LC; + ucon &= ~ULCON_RX_EN; + port->regs->UR_LC = ucon; +} + +void tls_uart_rx_enable(struct tls_uart_port *port) +{ + port->regs->UR_LC |= ULCON_RX_EN; +} + +static void tls_uart_tx_enable(struct tls_uart_port *port) +{ + u32 ucon; + +// printf("tx e\n"); + ucon = port->regs->UR_LC; + ucon |= ULCON_TX_EN; + port->regs->UR_LC = ucon; +} + +static void tls_uart_tx_disable(struct tls_uart_port *port) +{ + u32 ucon; + +// printf("tx d\n"); + ucon = port->regs->UR_LC; + ucon &= ~ULCON_TX_EN; + port->regs->UR_LC = ucon; +} + + +int tls_uart_config(struct tls_uart_port *port, struct tls_uart_options *opts) +{ + if (NULL == port || NULL == opts) + return WM_FAILED; +/* set the baud rate */ + tls_uart_set_baud_rate_inside(port, opts->baudrate); +/* set the parity */ + tls_uart_set_parity_inside(port, opts->paritytype); +/* set the number of data bits */ + tls_uart_set_data_bits(port, opts->charlength); +/* set the number of stop bits */ + tls_uart_set_stop_bits_inside(port, opts->stopbits); +/* Set flow control */ + port->opts.flow_ctrl = opts->flow_ctrl; + tls_uart_set_flow_ctrl(port, opts->flow_ctrl); + +/* config uart interrupt register */ +/* if (port->uart_mode == TLS_UART_MODE_INT) */// 榛樿浣跨敤涓柇鐨勬柟寮 + { + /* clear interrupt */ + port->regs->UR_INTS = 0xFFFFFFFF; + /* enable interupt */ + port->regs->UR_INTM = 0x0; + port->regs->UR_DMAC = + (4UL << UDMA_RX_FIFO_TIMEOUT_SHIFT) | UDMA_RX_FIFO_TIMEOUT; + } + +/* config FIFO control */ + port->regs->UR_FIFOC = UFC_TX_FIFO_LVL_16_BYTE | UFC_RX_FIFO_LVL_16_BYTE | + UFC_TX_FIFO_RESET | UFC_RX_FIFO_RESET; + port->regs->UR_LC &= ~(ULCON_TX_EN | ULCON_RX_EN); + port->regs->UR_LC |= ULCON_RX_EN | ULCON_TX_EN; + + return WM_SUCCESS; +} + +/** + * @brief handle a change of clear-to-send state + * @param[in] port: uart_port structure for the open port + * @param[in] status: new clear to send status, nonzero if active + */ +static void uart_handle_cts_change(struct tls_uart_port *port, + unsigned int status) +{ +//printf("\ncts change port->fcStatus=%d,port->opts.flow_ctrl=%d,status=%d\n",port->fcStatus,port->opts.flow_ctrl,status); + if (((1 == port->fcStatus) + && (port->opts.flow_ctrl == TLS_UART_FLOW_CTRL_HARDWARE)) + && (port->uart_no == TLS_UART_1)) + { + if (port->hw_stopped) + { + if (status) + { + port->hw_stopped = 0; + tls_uart_tx_enable(port); + tls_uart_tx_chars(port); + } + } + else + { + if (!status) + { + port->hw_stopped = 1; + tls_uart_tx_disable(port); + } + } + } +} + +int tls_uart_poll_put_char(struct tls_uart_port *port, int ch) +{ + if (ch == '\n') + { + while (port->regs->UR_FIFOS & 0x3F) /* wait THR is empty */ + ; + port->regs->UR_TXW = '\r'; /* output CR */ + } + while (port->regs->UR_FIFOS & 0x3F) /* wait THR is empty */ + ; + port->regs->UR_TXW = (char) ch; + + return ch; +} + +int tls_uart_poll_get_char(struct tls_uart_port *port) +{ + while ((port->regs->UR_FIFOS & UFS_RX_FIFO_CNT_MASK) >> 6) + return (int) port->regs->UR_RXW; + return 0; +} + +static void uart_tx_finish_callback(void *arg) +{ + if (arg) + { + tls_mem_free(arg); + } +} + +int tls_uart_tx_remain_len(struct tls_uart_port *port) +{ + tls_uart_tx_msg_t *tx_msg = NULL; + u16 buf_len = 0; + u32 cpu_sr; + cpu_sr = tls_os_set_critical(); + dl_list_for_each(tx_msg, &port->tx_msg_pending_list, tls_uart_tx_msg_t, + list) + { + buf_len += tx_msg->buflen; + } + tls_os_release_critical(cpu_sr); + return TLS_UART_TX_BUF_SIZE - buf_len; +} + +/** + * @brief This function is used to fill tx buffer. + * @param[in] port: is the uart port. + * @param[in] buf: is the user buffer. + * @param[in] count: is the user data length + * @retval + */ +int tls_uart_fill_buf(struct tls_uart_port *port, char *buf, u32 count) +{ + tls_uart_tx_msg_t *uart_tx_msg; +// int c; + int ret = 0; + u32 cpu_sr; + + uart_tx_msg = tls_mem_alloc(sizeof(tls_uart_tx_msg_t)); + if (uart_tx_msg == NULL) + { + TLS_DBGPRT_ERR("mem err\n"); + return -1; + } + dl_list_init(&uart_tx_msg->list); + uart_tx_msg->buf = tls_mem_alloc(count); + if (uart_tx_msg->buf == NULL) + { + tls_mem_free(uart_tx_msg); + TLS_DBGPRT_ERR("mem err 1 count=%d\n", count); + return -1; + } + memcpy(uart_tx_msg->buf, buf, count); + uart_tx_msg->buflen = count; + uart_tx_msg->offset = 0; + uart_tx_msg->finish_callback = uart_tx_finish_callback; + uart_tx_msg->callback_arg = uart_tx_msg->buf; + cpu_sr = tls_os_set_critical(); + dl_list_add_tail(&port->tx_msg_pending_list, &uart_tx_msg->list); + tls_os_release_critical(cpu_sr); + return ret; +} + +/** + * @brief free the data buffer has been transmitted. + * @param[in] port: is the uart port. + * @retval + */ +s16 tls_uart_free_tx_sent_data(struct tls_uart_port *port) +{ + tls_uart_tx_msg_t *tx_msg = NULL; + u32 cpu_sr = tls_os_set_critical(); + while (!dl_list_empty(&port->tx_msg_to_be_freed_list)) + { + tx_msg = dl_list_first(&port->tx_msg_to_be_freed_list, tls_uart_tx_msg_t, list); + dl_list_del(&tx_msg->list); + tls_os_release_critical(cpu_sr); + // printf("tx_msg=%p\n", tx_msg); + if (tx_msg->buf != NULL) + { + tx_msg->buf = NULL; + if (tx_msg->finish_callback) + tx_msg->finish_callback(tx_msg->callback_arg); + tls_mem_free(tx_msg); + } + cpu_sr = tls_os_set_critical(); + } + tls_os_release_critical(cpu_sr); + return 0; +} + +/** + * @brief This function is used to start transfer data. + * @param[in] port: is the uart port. + * @retval + */ +void tls_uart_tx_chars_start(struct tls_uart_port *port) +{ + struct dl_list *pending_list = &port->tx_msg_pending_list; + tls_uart_tx_msg_t *tx_msg = NULL; + int tx_count; + u32 cpu_sr; + +/* send some chars */ + tx_count = 32; + cpu_sr = tls_os_set_critical(); + if (!dl_list_empty(pending_list)) + { + tx_msg = dl_list_first(pending_list, tls_uart_tx_msg_t, list); + while (tx_count-- > 0 && tx_msg->offset < tx_msg->buflen) + { + /* 妫鏌x fifo鏄惁宸叉弧 */ + if ((port->regs->UR_FIFOS & UFS_TX_FIFO_CNT_MASK) == + port->tx_fifofull) + { + break; + } + port->regs->UR_TXW = tx_msg->buf[tx_msg->offset]; + tx_msg->offset++; + port->icount.tx++; + } + + if (tx_msg->offset >= tx_msg->buflen) + { + dl_list_del(&tx_msg->list); + dl_list_add_tail(&port->tx_msg_to_be_freed_list, &tx_msg->list); + tls_os_release_critical(cpu_sr); + + // if(tx_sent_callback) + // tx_sent_callback(port); + if (port->tx_callback) + port->tx_callback(port); + }else{ + tls_os_release_critical(cpu_sr); + } + }else{ + tls_os_release_critical(cpu_sr); + + if (port->tx_sem) + tls_os_sem_release(port->tx_sem); + + } + + return; +} + +/** + * @brief This function is used to continue transfer data. + * @param[in] port: is the uart port. + * @retval + */ +static void tls_uart_tx_chars(struct tls_uart_port *port) +{ + struct dl_list *pending_list = &port->tx_msg_pending_list; + tls_uart_tx_msg_t *tx_msg = NULL; + int tx_count = 64; +// int len; +// u32 cpu_sr; + u8 fifofull = 0; + + if (dl_list_empty(pending_list)) + { + // tls_uart_tx_disable(port); + + if (port->tx_sem) + tls_os_sem_release(port->tx_sem); + + return; + } + +// cpu_sr = tls_os_set_critical(); + while (!dl_list_empty(pending_list) && !fifofull) + { + tx_msg = dl_list_first(pending_list, tls_uart_tx_msg_t, list); + while (tx_count-- > 0 && tx_msg->offset < tx_msg->buflen) + { + /* 妫鏌x fifo鏄惁宸叉弧 */ + if ((port->regs->UR_FIFOS & UFS_TX_FIFO_CNT_MASK) == + port->tx_fifofull) + { + fifofull = 1; + break; + } + port->regs->UR_TXW = tx_msg->buf[tx_msg->offset]; + tx_msg->offset++; + port->icount.tx++; + } + if (tx_msg->offset >= tx_msg->buflen) + { + // cpu_sr = tls_os_set_critical(); + dl_list_del(&tx_msg->list); + dl_list_add_tail(&port->tx_msg_to_be_freed_list, &tx_msg->list); + // tls_os_release_critical(cpu_sr); + // if(tx_sent_callback) + // tx_sent_callback(port); + + if (port->tx_callback) + port->tx_callback(port); + } + } +// tls_os_release_critical(cpu_sr); +#if 0 + len = uart_circ_chars_pending(xmit); + if (len < WAKEUP_CHARS) + { + if (port->tx_callback) + port->tx_callback(port); + } + + + if (uart_circ_empty(xmit)) + tls_uart_tx_disable(port); +#endif +} + +#if DEBUG_RX_LEN +static int tls_rx_len = 0; + +int get_rx_len(void) +{ + return tls_rx_len; +} + +void clear_rx_len(void) +{ + tls_rx_len = 0; +} +#endif + +void tls_set_uart_rx_status(int uart_no, int status) +{ + u32 cpu_sr; + struct tls_uart_port *port; + + if (TLS_UART_1 == uart_no) + { + port = &uart_port[1]; + // TLS_DBGPRT_INFO("port%d set rx status=%d,prev + // rxstatus=%d\n",uart_no,status,port->rxstatus); + if ((TLS_UART_RX_DISABLE == port->rxstatus + && TLS_UART_RX_DISABLE == status) + || (TLS_UART_RX_ENABLE == port->rxstatus + && TLS_UART_RX_ENABLE == status)) + return; + + if (TLS_UART_RX_DISABLE == status) + { + // TLS_DBGPRT_INFO("\nopts + // flowctrl=%d,fcstatus=%d\n",port->opts.flow_ctrl,port->fcStatus); + if ((TLS_UART_FLOW_CTRL_HARDWARE == port->opts.flow_ctrl) + && (TLS_UART_FLOW_CTRL_HARDWARE == port->fcStatus)) + { + cpu_sr = tls_os_set_critical(); + // 鍏硆xfifo trigger level interrupt鍜宱verrun error + port->regs->UR_INTM |= ((0x1 << 2) | (0x01 << 8)); + port->rxstatus = TLS_UART_RX_DISABLE; + tls_os_release_critical(cpu_sr); + // TLS_DBGPRT_INFO(" rx int mask status=%d\n",port->rxstatus); + } + } + else + { + // TLS_DBGPRT_INFO("start unmask\n"); + cpu_sr = tls_os_set_critical(); + uart_port[1].regs->UR_INTM &= ~((0x1 << 2) | (0x01 << 8)); + port->rxstatus = TLS_UART_RX_ENABLE; + tls_os_release_critical(cpu_sr); + // TLS_DBGPRT_INFO("rx int unmask status=%d\n",port->rxstatus); + } + } +} + +void UART0_IRQHandler(void) +{ + struct tls_uart_port *port = &uart_port[0]; + struct tls_uart_circ_buf *recv = &port->recv; + u32 intr_src; + u32 rx_fifocnt; + u32 fifos; + u8 ch; + u32 rxlen = 0; + +/* check interrupt status */ + intr_src = port->regs->UR_INTS; + port->regs->UR_INTS = intr_src; + + if ((intr_src & UART_RX_INT_FLAG) && (0 == (port->regs->UR_INTM & UIS_RX_FIFO))) + { + rx_fifocnt = (port->regs->UR_FIFOS >> 6) & 0x3F; +#if DEBUG_RX_LEN + tls_rx_len += rx_fifocnt; +#endif + while (rx_fifocnt-- > 0) + { + ch = (u8) port->regs->UR_RXW; + if (intr_src & UART_RX_ERR_INT_FLAG) + { + port->regs->UR_INTS |= UART_RX_ERR_INT_FLAG; + TLS_DBGPRT_INFO("\nrx err=%x,c=%d,ch=%x\n", intr_src, rx_fifocnt, ch); + /* not insert to buffer */ + continue; + } + if (CIRC_SPACE(recv->head, recv->tail, TLS_UART_RX_BUF_SIZE) <= 2) + { + TLS_DBGPRT_INFO("\nrx buf overrun int_src=%x\n", intr_src); + if (TLS_UART_FLOW_CTRL_HARDWARE == port->fcStatus) + { + tls_set_uart_rx_status(port->uart_no, TLS_UART_RX_DISABLE); + rx_fifocnt = 0; // 濡傛灉鏈夌‖浠舵祦鎺э紝鍏抽棴鎺ユ敹锛屾妸鏈鍚庝竴涓瓧绗︽斁杩涚幆褰uffer涓 + } + else + break; + } + + /* insert the character into the buffer */ + recv->buf[recv->head] = ch; + recv->head = (recv->head + 1) & (TLS_UART_RX_BUF_SIZE - 1); + rxlen++; + } + if (port->rx_callback != NULL) + { + port->rx_callback((u16) rxlen); + } + } + + if (intr_src & UART_TX_INT_FLAG) + { + tls_uart_tx_chars(port); + } + + if (intr_src & UIS_CTS_CHNG) + { + fifos = port->regs->UR_FIFOS; + uart_handle_cts_change(port, fifos & UFS_CST_STS); + } + return; +} + +void UART1_IRQHandler(void) +{ + struct tls_uart_port *port = &uart_port[1]; + struct tls_uart_circ_buf *recv = &port->recv; + u32 intr_src; + u32 rx_fifocnt; + u32 fifos; + u8 ch = 0; + u8 escapefifocnt = 0; + u32 rxlen = 0; + +/* check interrupt status */ + intr_src = port->regs->UR_INTS; + port->regs->UR_INTS = intr_src; + + if (intr_src & UIS_OVERRUN) + { + port->regs->UR_INTS |= UIS_OVERRUN; + if(port->tx_dma_on) + { + tls_reg_write32((int)&port->regs->UR_DMAC, (tls_reg_read32((int)&port->regs->UR_DMAC) & ~0x01)); + tls_reg_write32((int)&port->regs->UR_DMAC, (tls_reg_read32((int)&port->regs->UR_DMAC) | 0x01)); + } + } + if ((intr_src & UART_RX_INT_FLAG) && (0 == (port->regs->UR_INTM & UIS_RX_FIFO))) + { + rx_fifocnt = (port->regs->UR_FIFOS >> 6) & 0x3F; +#if DEBUG_RX_LEN + tls_rx_len += rx_fifocnt; +#endif + escapefifocnt = rx_fifocnt; + port->plus_char_cnt = 0; + rxlen = rx_fifocnt; + + if (CIRC_SPACE(recv->head, recv->tail, TLS_UART_RX_BUF_SIZE) <= RX_CACHE_LIMIT) + { + recv->tail = (recv->tail + RX_CACHE_LIMIT) & (TLS_UART_RX_BUF_SIZE - 1); + } + + while (rx_fifocnt-- > 0) + { + ch = (u8) port->regs->UR_RXW; + if (intr_src & UART_RX_ERR_INT_FLAG) + { + port->regs->UR_INTS |= UART_RX_ERR_INT_FLAG; + TLS_DBGPRT_INFO("\nrx err=%x,c=%d,ch=%x\n", intr_src, rx_fifocnt, ch); + continue; + } + recv->buf[recv->head] = ch; + recv->head = (recv->head + 1) & (TLS_UART_RX_BUF_SIZE - 1); + } + + if( escapefifocnt==3 && ch=='+') + { + switch(recv->head-1) + { + case 0: + if(recv->buf[TLS_UART_RX_BUF_SIZE-1]=='+' && recv->buf[TLS_UART_RX_BUF_SIZE-2]=='+') + port->plus_char_cnt = 3; + break; + case 1: + if(recv->buf[0]=='+' && recv->buf[TLS_UART_RX_BUF_SIZE-1]=='+') + port->plus_char_cnt = 3; + break; + default: + if(recv->buf[recv->head-2]=='+' && recv->buf[recv->head-3]=='+') + port->plus_char_cnt = 3; + break; + } + } + if (port->rx_callback!=NULL) + { + port->rx_callback((u16) rxlen); + } + } + if (intr_src & UART_TX_INT_FLAG) + { + tls_uart_tx_chars(port); + } + if (intr_src & UIS_CTS_CHNG) + { + fifos = port->regs->UR_FIFOS; + uart_handle_cts_change(port, fifos & UFS_CST_STS); + } + return; +} + +void UART2_IRQHandler(void) +{ + struct tls_uart_port *port = &uart_port[2]; + struct tls_uart_circ_buf *recv = &port->recv; + u32 intr_src; + u32 rx_fifocnt; + u32 fifos; + u8 ch; + u32 rxlen = 0; + +/* check interrupt status */ + intr_src = port->regs->UR_INTS; + port->regs->UR_INTS = intr_src; + + if (intr_src & UIS_OVERRUN) + { + port->regs->UR_INTS |= UIS_OVERRUN; + if(port->tx_dma_on) + { + tls_reg_write32((int)&port->regs->UR_DMAC, (tls_reg_read32((int)&port->regs->UR_DMAC) & ~0x01)); + tls_reg_write32((int)&port->regs->UR_DMAC, (tls_reg_read32((int)&port->regs->UR_DMAC) | 0x01)); + } + } + if ((intr_src & UART_RX_INT_FLAG) && (0 == (port->regs->UR_INTM & UIS_RX_FIFO))) + { + rx_fifocnt = (port->regs->UR_FIFOS >> 6) & 0x3F; +#if DEBUG_RX_LEN + tls_rx_len += rx_fifocnt; +#endif + while (rx_fifocnt-- > 0) + { + ch = (u8) port->regs->UR_RXW; + /* break, stop bit error parity error, not include overrun err */ + if (intr_src & UART_RX_ERR_INT_FLAG) + { + port->regs->UR_INTS |= UART_RX_ERR_INT_FLAG; + TLS_DBGPRT_INFO("\nrx err=%x,c=%d,ch=%x\n", intr_src, rx_fifocnt, ch); + /* not insert to buffer */ + continue; + } + // if (CIRC_SPACE(recv->head, recv->tail, TLS_UART_RX_BUF_SIZE) == 0) + if (CIRC_SPACE(recv->head, recv->tail, TLS_UART_RX_BUF_SIZE) <= 2) + { + TLS_DBGPRT_INFO("\nrx buf overrun int_src=%x\n", intr_src); + if (TLS_UART_FLOW_CTRL_HARDWARE == port->fcStatus) + { + tls_set_uart_rx_status(port->uart_no, TLS_UART_RX_DISABLE); + rx_fifocnt = 0; // 濡傛灉鏈夌‖浠舵祦鎺э紝鍏抽棴鎺ユ敹锛屾妸鏈鍚庝竴涓瓧绗︽斁杩涚幆褰uffer涓 + } + else + break; + } + + /* insert the character into the buffer */ + recv->buf[recv->head] = ch; + recv->head = (recv->head + 1) & (TLS_UART_RX_BUF_SIZE - 1); + rxlen++; + } + if(port->rx_callback != NULL && rxlen) + { + port->rx_callback((u16) rxlen); + } + + } + + if (intr_src & UART_TX_INT_FLAG) + { + tls_uart_tx_chars(port); + } + + if (intr_src & UIS_CTS_CHNG) + { + fifos = port->regs->UR_FIFOS; + uart_handle_cts_change(port, fifos & UFS_CST_STS); + } + return; +} + +/** + * @brief This function is used to initial uart port. + * + * @param[in] uart_no: is the uart number. + * - \ref TLS_UART_0 + * - \ref TLS_UART_1 + * - \ref TLS_UART_2 + * @param[in] opts: is the uart setting options,if this param is NULL,this function will use the default options. + * @param[in] modeChoose:; choose uart2 mode or 7816 mode when uart_no is TLS_UART_2, 0 for uart2 mode and 1 for 7816 mode. + * + * @retval + * - \ref WM_SUCCESS + * - \ref WM_FAILED + * + * @note When the system is initialized, the function has been called, so users can not call the function. + */ +int tls_uart_port_init(u16 uart_no, tls_uart_options_t * opts, u8 modeChoose) +{ + struct tls_uart_port *port; + int ret; + char *bufrx; // ,*buftx + tls_uart_options_t opt; + + + + UartRegInit(uart_no); + + if (TLS_UART_0 == uart_no) + { + memset(&uart_port[0], 0, sizeof(struct tls_uart_port)); + port = &uart_port[0]; + port->regs = (TLS_UART_REGS_T *) HR_UART0_BASE_ADDR; + } + else if (TLS_UART_1 == uart_no) + { + memset(&uart_port[1], 0, sizeof(struct tls_uart_port)); + port = &uart_port[1]; + port->regs = (TLS_UART_REGS_T *) HR_UART1_BASE_ADDR; + } + else if (TLS_UART_2 == uart_no) + { + memset(&uart_port[2], 0, sizeof(struct tls_uart_port)); + port = &uart_port[2]; + port->regs = (TLS_UART_REGS_T *) HR_UART2_BASE_ADDR; + (modeChoose == 1)?(port->regs->UR_LC |= (1 << 24)):(port->regs->UR_LC &= ~(0x1000000)); + } + else + { + return WM_FAILED; + } + + port->uart_no = uart_no; + + if (NULL == opts) + { + opt.baudrate = UART_BAUDRATE_B115200; + opt.charlength = TLS_UART_CHSIZE_8BIT; + opt.flow_ctrl = TLS_UART_FLOW_CTRL_NONE; + opt.paritytype = TLS_UART_PMODE_DISABLED; + opt.stopbits = TLS_UART_ONE_STOPBITS; + ret = tls_uart_config(port, &opt); + } + else + { + ret = tls_uart_config(port, opts); + } + + if (ret != WM_SUCCESS) + return WM_FAILED; + port->rxstatus = TLS_UART_RX_ENABLE; + port->uart_irq_no = (uart_no == TLS_UART_0) ? UART0_INT : ((uart_no == TLS_UART_1) ? UART1_INT : UART2_INT); + tls_irq_disable(port->uart_irq_no); + + if (port->recv.buf == NULL){ + bufrx = tls_mem_alloc(TLS_UART_RX_BUF_SIZE); + if (!bufrx) + return WM_FAILED; + memset(bufrx, 0, TLS_UART_RX_BUF_SIZE); + port->recv.buf = (u8 *) bufrx; + } + port->recv.head = 0; + port->recv.tail = 0; + port->tx_fifofull = 16; + dl_list_init(&port->tx_msg_pending_list); + dl_list_init(&port->tx_msg_to_be_freed_list); + tls_uart_tx_callback_register(uart_no, tls_uart_free_tx_sent_data); + +/* enable uart interrupt */ + tls_irq_enable(port->uart_irq_no); + return WM_SUCCESS; +} + +/** + * @brief This function is used to register uart rx interrupt. + * + * @param[in] uart_no: is the uart numer. + * @param[in] callback: is the uart rx interrupt call back function. + * + * @retval + * + * @note This function should be called after the fucntion tls_uart_port_init() or it won't work. + */ +void tls_uart_rx_callback_register(u16 uart_no, s16(*rx_callback) (u16 len)) +{ + if (TLS_UART_0 == uart_no) + uart_port[0].rx_callback = rx_callback; + else if (TLS_UART_1 == uart_no) + uart_port[1].rx_callback = rx_callback; + else if (TLS_UART_2 == uart_no) + uart_port[2].rx_callback = rx_callback; +} + +/** + * @brief This function is used to register uart tx interrupt. + * + * @param[in] uart_no: is the uart numer. + * @param[in] callback: is the uart tx interrupt call back function. + * + * @retval + */ +void tls_uart_tx_callback_register(u16 uart_no, + s16(*tx_callback) (struct tls_uart_port * + port)) +{ + if (TLS_UART_0 == uart_no) + uart_port[0].tx_callback = tx_callback; + else if (TLS_UART_1 == uart_no) + uart_port[1].tx_callback = tx_callback; + else if (TLS_UART_2 == uart_no) + uart_port[2].tx_callback = tx_callback; +} + +//void tls_uart_tx_sent_register(void (*tx_sent_callbk)(struct tls_uart_port *port)) +//{ +// tx_sent_callback = tx_sent_callbk; +//} + +/** + * @brief This function is used to copy circular buffer data to user buffer. + * @param[in] uart_no: is the uart numer. + * @param[in] buf: is the user buffer. + * @param[in] readsize: is the user read size. + * @retval + */ +int tls_uart_read(u16 uart_no, u8 * buf, u16 readsize) +{ + int data_cnt, buflen, bufcopylen; + struct tls_uart_port *port = NULL; + struct tls_uart_circ_buf *recv; + + if (NULL == buf || readsize < 1) + return WM_FAILED; + + if (TLS_UART_0 == uart_no) + port = &uart_port[0]; + else if (TLS_UART_1 == uart_no) + port = &uart_port[1]; + else if (TLS_UART_2 == uart_no) + port = &uart_port[2]; + + recv = &port->recv; + data_cnt = CIRC_CNT(recv->head, recv->tail, TLS_UART_RX_BUF_SIZE); + if (data_cnt >= readsize) + { + buflen = readsize; + } + else // 濡傛灉鏁版嵁涓嶅锛岀洿鎺ヨ繑鍥0 + { + return 0; + } + if ((recv->tail + buflen) > TLS_UART_RX_BUF_SIZE) + { + bufcopylen = (TLS_UART_RX_BUF_SIZE - recv->tail); + MEMCPY(buf, recv->buf + recv->tail, bufcopylen); + MEMCPY(buf + bufcopylen, recv->buf, buflen - bufcopylen); + } + else + { + MEMCPY(buf, recv->buf + recv->tail, buflen); + } + recv->tail = (recv->tail + buflen) & (TLS_UART_RX_BUF_SIZE - 1); + return buflen; +} + + +u8 *testbuf; +u16 flag = 0; +u16 datalen = 0; + +#ifdef TEST_UART +/********************************************************************************************************** +* Description: This function is used to receive uart data. +* +* Arguments : buf is a buf for saving received data. +* +* Returns : Return received data length. +* Notes : +**********************************************************************************************************/ +s16 tls_uart_rx_test(u16 len) +{ + + if (datalen < (4096 - len)) + { + // MEMCPY(testbuf + datalen, buf, len); + tls_uart_read(TLS_UART_1, testbuf + datalen, len); + flag = 1; + datalen += len; + } + else + { + TLS_DBGPRT_INFO("\rx buffer over\n"); + } + return WM_SUCCESS; +} + + +void tls_uart_test(void) +{ + int len = 0; + + TLS_DBGPRT_INFO("\nentry tls_uart_test\n"); + testbuf = tls_mem_alloc(4096); + if (!testbuf) + return; + memset(testbuf, 0, 4096); +// tls_uart_cfg_user_mode(); + tls_uart_rx_callback_register(TLS_UART_1, tls_uart_rx_test); +#if 0 + tls_user_uart_set_baud_rate(UART_BAUDRATE_B38400); + tls_user_uart_set_stop_bits(TLS_UART_ONE_STOPBITS); + tls_user_uart_set_parity(TLS_UART_PMODE_DISABLED); +#endif + TLS_DBGPRT_INFO("\nentry while\n"); + while (1) + { + // TLS_DBGPRT_INFO("\n==============flag=%d\n",flag); + + OSTimeDly(0x100); + if (flag) + { + TLS_DBGPRT_INFO("\n\rrx data len = %d\n%s\n\r", datalen, testbuf); + // tls_uart_tx("\n\r",2); + tls_uart_write_sync(TLS_UART_1, testbuf, datalen); + len = tls_uart_tx_length(TLS_UART_1); + printf("\ntx len=%d\n", len); + + len = tls_uart_tx_length(); + printf("\ntx len 0=%d\n", len); + // tls_uart_tx("\n\r",2); + tls_uart_write(TLS_UART_1, "abcde", 5); + len = tls_uart_tx_length(TLS_UART_1); + printf("\ntx len 1=%d\n", len); + flag = 0; + datalen = 0; + } + // len = tls_uart_tx_length(); + // printf("\ntx len 2=%d\n",len); + + } + +} + +#endif +/********************************************************************************************************** +* Description: This function is used to config uart port for user mode. +* +* Arguments : +* +* Returns : +* Notes : If user want to use uart function,must call this function. +**********************************************************************************************************/ +#if 0 +void tls_uart_cfg_user_mode(void) +{ + struct tls_uart_port *port = &uart_port[1]; + + port->ifusermode = 1; + memset(port->recv.buf, 0, TLS_UART_RX_BUF_SIZE); + port->recv.head = 0; + port->recv.tail = 0; + port->icount.rx = 0; + + port->rx_callback_bk = port->rx_callback; + port->rx_callback = NULL; + + port->tx_callback_bk = port->tx_callback; + port->tx_callback = NULL; +} +#endif +/********************************************************************************************************** +* Description: This function is used to disable uart user mode. +* +* Arguments : +* +* Returns : +* Notes : If user want to resume uart old function for AT commond,must call this function. +**********************************************************************************************************/ +#if 0 +void tls_uart_disable_user_mode(void) +{ + struct tls_uart_port *port = &uart_port[1]; + + port->ifusermode = 0; + memset(port->recv.buf, 0, TLS_UART_RX_BUF_SIZE); + port->recv.head = 0; + port->recv.tail = 0; + + port->rx_callback = port->rx_callback_bk; + port->rx_callback_bk = NULL; + + port->tx_callback = port->tx_callback_bk; + port->tx_callback_bk = NULL; +} +#endif + +#if 0 +static s16 tls_uart_tx_cb(struct tls_uart_port *port) +{ + int ret_len = 0; + + if (NULL == port) + return WM_FAILED; + if (port->buf_len > 0) // uart1,缂撳啿鍖烘暟鎹紶杈撳畬鎴愪箣鍚庯紝鍓╀綑鐨勫緟浼犵殑鏁版嵁鍐嶆斁鍏ョ紦鍐插尯 + { + ret_len = tls_uart_fill_buf(port, port->buf_ptr, port->buf_len); + // TLS_DBGPRT_INFO("\ntx cb write len=%d",ret_len); + + if (ret_len >= 0) + { + if (port->buf_len >= ret_len) + { + port->buf_len -= ret_len; + port->buf_ptr += ret_len; + } + } + } + + return WM_SUCCESS; +} +#endif + + +/** + * @brief This function is used to transfer data throuth DMA. + * + * @param[in] buf is a buf for saving user data + * @param[in] writesize is the user data length + * @param[in] cmpl_callback function point,when the transfer is completed, the function will be called. + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note Only uart1 support DMA transfer. + */ +int tls_uart_dma_write(char *buf, u16 writesize, void (*cmpl_callback) (void *p), u16 uart_no) +{ + unsigned char dmaCh = 0; + struct tls_dma_descriptor DmaDesc; + struct tls_uart_port *port = &uart_port[uart_no]; + + if (NULL == buf || writesize < 1 || writesize >= 4096) + { + TLS_DBGPRT_ERR("param err\n"); + return WM_FAILED; + } + if (port->tx_dma_on) + { + TLS_DBGPRT_ERR("transmiting,wait\n"); + return WM_FAILED; + } +// port->tx_dma_cmpl_callbk = cmpl_callback; + + tls_reg_write32(HR_DMA_CHNL_SEL, uart_no); + +/* Request DMA Channel */ + dmaCh = tls_dma_request(2, + TLS_DMA_FLAGS_CHANNEL_SEL(TLS_DMA_SEL_UART_TX) | TLS_DMA_FLAGS_HARD_MODE); + if (dmaCh != 2) + { + TLS_DBGPRT_ERR("dma request err\n"); + return WM_FAILED; + } + tls_reg_write32((int)&port->regs->UR_DMAC, (tls_reg_read32((int)&port->regs->UR_DMAC) & ~0x01)); + tls_dma_irq_register(dmaCh, cmpl_callback, (void *)uart_no, TLS_DMA_IRQ_TRANSFER_DONE); + DmaDesc.src_addr = (int) buf; + DmaDesc.dest_addr = (int)&port->regs->UR_TXW; + DmaDesc.dma_ctrl = TLS_DMA_DESC_CTRL_SRC_ADD_INC | TLS_DMA_DESC_CTRL_DATA_SIZE_BYTE | + (writesize << 7); + DmaDesc.valid = TLS_DMA_DESC_VALID; + DmaDesc.next = NULL; + tls_dma_start(dmaCh, &DmaDesc, 0); + /* Enable uart TX DMA */ + port->tx_dma_on = TRUE; + tls_reg_write32((int)&port->regs->UR_DMAC, (tls_reg_read32((int)&port->regs->UR_DMAC) | 0x01)); + tls_reg_write32(HR_DMA_INT_MASK, + (tls_reg_read32(HR_DMA_INT_MASK) & ~(0x01 << 5))); + +/* enable dma interrupt */ + tls_irq_enable(DMA2_INT); + + return WM_SUCCESS; +} + +/** + * @brief This function is used to transfer data asynchronous. + * + * @param[in] uart_no is the uart number + * @param[in] buf is a buf for saving user data. + * @param[in] writesize is the data length + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note The function only start transmission, fill buffer in the callback function. + */ +int tls_uart_write_async(u16 uart_no, char *buf, u16 writesize) +{ + struct tls_uart_port *port = NULL; + int ret; + + if (NULL == buf || writesize < 1) + { + TLS_DBGPRT_ERR("param err\n"); + return WM_FAILED; + } + + if (TLS_UART_1 == uart_no) + port = &uart_port[1]; + else if (TLS_UART_0 == uart_no) + port = &uart_port[0]; + else if (TLS_UART_2 == uart_no) + port = &uart_port[2]; + + ret = tls_uart_fill_buf(port, buf, writesize); + + if (0 == ret) + { + tls_uart_tx_chars_start(port); + } + + return ret; +} + +/** + * @brief get the data length has been transmitted. + * + * @param[in] uart_no is the uart number + * + * @retval the length has been transmitted + * + */ +int tls_uart_tx_length(u16 uart_no) +{ + struct tls_uart_port *port = &uart_port[uart_no]; + + return port->icount.tx; +} + +/** + * @brief This function is used to transfer data synchronous. + * + * @param[in] uart_no is the uart number + * @param[in] buf is a buf for saving user data. + * @param[in] writesize is the data length + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + * @note The function only start transmission, fill buffer in the callback function. + */ +int tls_uart_write(u16 uart_no, char *buf, u16 writesize) +{ + struct tls_uart_port *port = NULL; + u8 err; + int ret = 0; + + if (TLS_UART_1 == uart_no) + port = &uart_port[1]; + else if (TLS_UART_0 == uart_no) + port = &uart_port[0]; + else if (TLS_UART_2 == uart_no) + port = &uart_port[2]; + + err = tls_os_sem_create(&port->tx_sem, 0); + if (err != TLS_OS_SUCCESS) + { + TLS_DBGPRT_ERR("\ntx sem create fail\n"); + return WM_FAILED; + } + + ret = tls_uart_write_async(uart_no, buf, writesize); + if (0 == ret) + { + tls_os_sem_acquire(port->tx_sem, 0); + } + tls_os_sem_delete(port->tx_sem); + port->tx_sem = NULL; + + return WM_SUCCESS; +} + + +/********************************************************************************************************** +* Description: This function is used to register uart rx interrupt. +* +* Arguments : callback is the uart rx interrupt call back function. +* +* Returns : +* +**********************************************************************************************************/ +#if 0 +void tls_user_uart_rx_register(s16(*rx_callback) (char *buf, u16 len)) +{ + tls_uart_rx_callback_register(TLS_UART_1, rx_callback); +} +#endif +/********************************************************************************************************** +* Description: This function is used to register uart tx interrupt. +* +* Arguments : callback is the uart tx interrupt call back function. +* +* Returns : +* +**********************************************************************************************************/ +#if 0 +void tls_user_uart_tx_register(s16(*tx_callback) (struct tls_uart_port * port)) +{ + tls_uart_tx_callback_register(TLS_UART_1, tx_callback); +} +#endif +/** + * @brief This function is used to set uart parity. + * + * @param[in] paritytype is a parity type defined in TLS_UART_PMODE_T + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + */ +int tls_uart_set_parity(u16 uart_no, TLS_UART_PMODE_T paritytype) +{ + if (TLS_UART_1 == uart_no) + return tls_uart_set_parity_inside(&uart_port[1], paritytype); + else if (TLS_UART_0 == uart_no) + return tls_uart_set_parity_inside(&uart_port[0], paritytype); + else if (TLS_UART_2 == uart_no) + return tls_uart_set_parity_inside(&uart_port[2], paritytype); + return WM_FAILED; +} + +/** + * @brief This function is used to set uart baudrate. + * + * @param[in] uart_no is the uart number + * @param[in] baudrate is the baudrate user want used,the unit is HZ. + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + */ +int tls_uart_set_baud_rate(u16 uart_no, u32 baudrate) +{ + if (TLS_UART_1 == uart_no) + return tls_uart_set_baud_rate_inside(&uart_port[1], baudrate); + else if (TLS_UART_0 == uart_no) + return tls_uart_set_baud_rate_inside(&uart_port[0], baudrate); + else if (TLS_UART_2 == uart_no) + return tls_uart_set_baud_rate_inside(&uart_port[2], baudrate); + return WM_FAILED; +} + +/** + * @brief This function is used to set uart stop bits. + * + * @param[in] uart_no is the uart number + * @param[in] stopbits is a stop bit type defined in TLS_UART_STOPBITS_T. + * + * @retval WM_SUCCESS success + * @retval WM_FAILED failed + * + */ +int tls_uart_set_stop_bits(u16 uart_no, TLS_UART_STOPBITS_T stopbits) +{ + if (TLS_UART_1 == uart_no) + return tls_uart_set_stop_bits_inside(&uart_port[1], stopbits); + else if (TLS_UART_0 == uart_no) + return tls_uart_set_stop_bits_inside(&uart_port[0], stopbits); + else if (TLS_UART_2 == uart_no) + return tls_uart_set_stop_bits_inside(&uart_port[2], stopbits); + return WM_FAILED; +} + +int tls_uart_dma_off(u16 uart_no) +{ + uart_port[uart_no].tx_dma_on = FALSE; + return WM_SUCCESS; +} +#endif +//TLS_CONFIG_UART diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_uart_new.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_uart_new.c new file mode 100644 index 00000000..7f11edae --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_uart_new.c @@ -0,0 +1,284 @@ +/* + * ESPRSSIF MIT License + * + * Copyright (c) 2015 + * + * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case, + * it is free of charge, to any person obtaining a copy of this software and associated + * documentation files (the "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the Software is furnished + * to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all copies or + * substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +//#include "esp_common.h" +#include "wm_type_def.h" +#include "wm_uart_new.h" +#include "wm_uart.h" +#include "wm_regs.h" +#include "wm_cpu.h" +#include "wm_gpio_afsel.h" + + +enum { + UART_EVENT_RX_CHAR, + UART_EVENT_MAX +}; + +typedef struct _os_event_ { + u32 event; + u32 param; +} os_event_t; + +typedef void(*uart_callback) (void); + +uart_callback uart0_callback_func = NULL; +uart_callback uart1_callback_func = NULL; + +static u8 +uart_tx_one_char(u8 uart, u8 TxChar) +{ + while (true) { + u32 fifo_cnt = (tls_reg_read32(HR_UART0_FIFO_STATUS + uart*0x200) & 0x3F); + + if (fifo_cnt < 60) { + break; + } + } + tls_reg_write32(HR_UART0_TX_WIN + uart*0x200, (char)TxChar); + return 0; +} + +void +uart1_write_char(char c) +{ + if (c == '\n') { + uart_tx_one_char(UART1, '\r'); + uart_tx_one_char(UART1, '\n'); + } else if (c == '\r') { + } else { + uart_tx_one_char(UART1, c); + } +} + +void +uart0_write_char(char c) +{ + if (c == '\n') { + uart_tx_one_char(UART0, '\r'); + uart_tx_one_char(UART0, '\n'); + } else if (c == '\r') { + } else { + uart_tx_one_char(UART0, c); + } +} + +void +UART_SetWordLength(UART_Port uart_no, UART_WordLength len) +{ + tls_bitband_write(HR_UART0_LINE_CTRL + uart_no*0x200, 0, (len >> 0) & 0x01); + tls_bitband_write(HR_UART0_LINE_CTRL + uart_no*0x200, 1, (len >> 1) & 0x01); +} + +void +UART_SetStopBits(UART_Port uart_no, UART_StopBits bit_num) +{ + tls_bitband_write(HR_UART0_LINE_CTRL + uart_no*0x200, 2, bit_num); +} + + +void +UART_SetParity(UART_Port uart_no, UART_ParityMode Parity_mode) +{ + + if (Parity_mode == USART_Parity_None) { + tls_bitband_write(HR_UART0_LINE_CTRL + uart_no*0x200, 3, 0); + } else { + tls_bitband_write(HR_UART0_LINE_CTRL + uart_no*0x200, 3, 1); + tls_bitband_write(HR_UART0_LINE_CTRL + uart_no*0x200, 4, Parity_mode); + } +} + +void +UART_SetBaudrate(UART_Port uart_no, u32 baud_rate) +{ + u32 value, apbclk; + tls_sys_clk sysclk; + + tls_sys_clk_get(&sysclk); + apbclk = sysclk.apbclk * 1000000; + value = (apbclk / (16 * baud_rate) - 1) | (((apbclk % (baud_rate * 16)) * 16 / (baud_rate * 16)) << 16); + tls_reg_write32(HR_UART0_BAUD_RATE_CTRL + uart_no*0x200, value); +} + +//only when USART_HardwareFlowControl_RTS is set , will the rx_thresh value be set. +void +UART_SetFlowCtrl(UART_Port uart_no, UART_HwFlowCtrl flow_ctrl, u8 rx_thresh) +{ + rx_thresh = rx_thresh; + switch (flow_ctrl) + { + case USART_HardwareFlowControl_None: + tls_reg_write32(HR_UART0_FLOW_CTRL + uart_no*0x200, 0); + break; + + case USART_HardwareFlowControl_RTS: + case USART_HardwareFlowControl_CTS: + case USART_HardwareFlowControl_CTS_RTS: + tls_reg_write32(HR_UART0_FLOW_CTRL + uart_no*0x200, (1UL << 0) | ((rx_thresh/4-1) << 2)); + break; + + default: + break; + } +} + +void +UART_WaitTxFifoEmpty(UART_Port uart_no) //do not use if tx flow control enabled +{ + while(tls_reg_read32(HR_UART0_FIFO_STATUS + uart_no*0x200) & 0x3F); +} + +void +UART_ResetFifo(UART_Port uart_no) +{ + tls_bitband_write(HR_UART0_FIFO_CTRL + uart_no*0x200, 0, 1); + tls_bitband_write(HR_UART0_FIFO_CTRL + uart_no*0x200, 1, 1); +} + +void +UART_ClearIntrStatus(UART_Port uart_no, u32 clr_mask) +{ + tls_reg_write32(HR_UART0_INT_SRC + uart_no*0x200, clr_mask); +} + +void +UART_SetIntrEna(UART_Port uart_no, u32 ena_mask) +{ + tls_reg_write32(HR_UART0_INT_MASK + uart_no*0x200, ena_mask); +} + +void +UART_intr_handler_register(UART_Port uart_no, void *fn, void *arg) +{ + arg = arg; + if( uart_no==UART0 ) + { + uart0_callback_func = (uart_callback)fn; + } + else if( uart_no==UART1 ) + { + uart1_callback_func = (uart_callback)fn; + } +} + +//void +//UART_SetPrintPort(UART_Port uart_no) +//{ +// if (uart_no == 1) { +// os_install_putc1(uart1_write_char); +// } else { +// os_install_putc1(uart0_write_char); +// } +//} + +void +UART_ParamConfig(UART_Port uart_no, UART_ConfigTypeDef *pUARTConfig) +{ + if (uart_no == UART1) { + wm_uart1_tx_config(WM_IO_PB_12); + wm_uart1_rx_config(WM_IO_PB_11); + } else { + wm_uart0_tx_config(WM_IO_PA_04); + wm_uart0_rx_config(WM_IO_PA_05); + } + + UART_SetFlowCtrl(uart_no, pUARTConfig->flow_ctrl, pUARTConfig->UART_RxFlowThresh); + UART_SetBaudrate(uart_no, pUARTConfig->baud_rate); + UART_SetParity(uart_no, pUARTConfig->parity); + UART_SetStopBits(uart_no, pUARTConfig->stop_bits); + UART_SetWordLength(uart_no, pUARTConfig->data_bits); + UART_SetFlowCtrl(uart_no, pUARTConfig->flow_ctrl, 28); + UART_ResetFifo(uart_no); +} + +void +UART_IntrConfig(UART_Port uart_no, UART_IntrConfTypeDef *pUARTIntrConf) +{ + u32 reg1_val = 0, reg2_val = 0; + UART_ClearIntrStatus(uart_no, UART_INTR_MASK); + + reg1_val = tls_reg_read32(HR_UART0_DMA_CTRL + uart_no*0x200); + reg1_val |= (((pUARTIntrConf->UART_IntrEnMask & UIS_RX_FIFO_TIMEOUT) == 0) ? (pUARTIntrConf->UART_RX_TimeOutIntrThresh) : 0); + reg1_val |= (((pUARTIntrConf->UART_IntrEnMask & UIS_RX_FIFO_TIMEOUT) == 0) ? (UDMA_RX_FIFO_TIMEOUT) : 0); + tls_reg_write32(HR_UART0_DMA_CTRL + uart_no*0x200, reg1_val); + + reg2_val = tls_reg_read32(HR_UART0_FIFO_CTRL + uart_no*0x200); + reg2_val |= (((pUARTIntrConf->UART_IntrEnMask & UIS_RX_FIFO) == 0) ? (pUARTIntrConf->UART_RX_FifoFullIntrThresh) : 0); + reg2_val |= (((pUARTIntrConf->UART_IntrEnMask & UIS_TX_FIFO) == 0) ? (pUARTIntrConf->UART_TX_FifoEmptyIntrThresh) : 0); + tls_reg_write32(HR_UART0_FIFO_CTRL + uart_no*0x200, reg2_val); + + tls_reg_write32(HR_UART0_INT_MASK + uart_no*0x200, 0); + tls_reg_write32(HR_UART0_INT_MASK + uart_no*0x200, pUARTIntrConf->UART_IntrEnMask); + tls_bitband_write(HR_UART0_LINE_CTRL + uart_no*0x200, 6, 1); //tx en + tls_bitband_write(HR_UART0_LINE_CTRL + uart_no*0x200, 7, 1); //rx en +} + + + +//void UART0_IRQHandler(void) +//{ +// if( uart0_callback_func != NULL ) +// { +// uart0_callback_func(); +// } +//} + +void UART1_IRQHandler(void) +{ + if( uart1_callback_func != NULL ) + { + uart1_callback_func(); + } +} + + +void +uart_init_new(void) +{ + UART_WaitTxFifoEmpty(UART0); + UART_WaitTxFifoEmpty(UART1); + + UART_ConfigTypeDef uart_config; + uart_config.baud_rate = BIT_RATE_115200; + uart_config.data_bits = UART_WordLength_8b; + uart_config.parity = USART_Parity_None; + uart_config.stop_bits = USART_StopBits_1; + uart_config.flow_ctrl = USART_HardwareFlowControl_None; + uart_config.UART_RxFlowThresh = 120; +// uart_config.UART_InverseMask = UART_None_Inverse; + UART_ParamConfig(UART0, &uart_config); + + UART_IntrConfTypeDef uart_intr; + uart_intr.UART_IntrEnMask = ~(UIS_RX_FIFO_TIMEOUT | UIS_FRM_ERR | UIS_RX_FIFO | UIS_TX_FIFO_EMPTY); + uart_intr.UART_RX_FifoFullIntrThresh = UFC_RX_FIFO_LVL_8_BYTE; + uart_intr.UART_RX_TimeOutIntrThresh = (4 << UDMA_RX_FIFO_TIMEOUT_SHIFT); + uart_intr.UART_TX_FifoEmptyIntrThresh = UFC_TX_FIFO_LVL_8_BYTE; + UART_IntrConfig(UART0, &uart_intr); + + //UART_SetPrintPort(UART0); + + tls_irq_enable(UART0_INT); + +} diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_watchdog.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_watchdog.c new file mode 100644 index 00000000..5ae328fd --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/drivers/wm_watchdog.c @@ -0,0 +1,74 @@ +/** + * @file wm_watchdog.c + * + * @brief watchdog Driver Module + * + * @author kevin + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + */ +#include "wm_debug.h" +#include "wm_regs.h" +#include "wm_irq.h" +#include "wm_cpu.h" +#include "wm_watchdog.h" + + +void WDG_IRQHandler(void) +{ + printf("WDG IRQ\n"); +} + +/** + * @brief This function is used to clear watchdog + * + * @param None + * + * @return None + * + * @note None + */ +void tls_watchdog_clr(void) +{ + tls_reg_write32(HR_WDG_INT_CLR, 0x01); +// printf("FEED WDG\n"); +} + +/** + * @brief This function is used to init watchdog + * + * @param[in] usec microseconds + * + * @return None + * + * @note None + */ +void tls_watchdog_init(u32 usec) +{ + + tls_sys_clk sysclk; + + tls_sys_clk_get(&sysclk); + tls_irq_enable(WATCHDOG_INT); + + tls_reg_write32(HR_WDG_LOAD_VALUE, sysclk.apbclk * usec); /* 40M dominant frequency: 40 * 10^6 * (usec / 10^6) */ + tls_reg_write32(HR_WDG_CTRL, 0x3); /* enable irq & reset */ +} + +/** + * @brief This function is used to reset system + * + * @param None + * + * @return None + * + * @note None + */ +void tls_sys_reset(void) +{ + tls_reg_write32(HR_WDG_LOCK, 0x1ACCE551); + tls_reg_write32(HR_WDG_LOAD_VALUE, 0x100); + tls_reg_write32(HR_WDG_CTRL, 0x3); + tls_reg_write32(HR_WDG_LOCK, 1); +} + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/inc/bitops.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/inc/bitops.h new file mode 100644 index 00000000..82f8b34e --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/inc/bitops.h @@ -0,0 +1,116 @@ + +#ifndef BITOPS_H +#define BITOPS_H + +#include "wm_osal.h" + +/* + * These functions are the basis of our bit ops. + * + * First, the atomic bitops. These use native endian. + */ +static __inline void set_bit(unsigned int bit, volatile unsigned long *p) +{ + u32 cpu_sr; + unsigned long mask = 1 << (bit & 31); + + p += bit >> 5; + + cpu_sr = tls_os_set_critical(); + *p |= mask; + tls_os_release_critical(cpu_sr); +} + +static __inline void clear_bit(unsigned int bit, volatile unsigned long *p) +{ + u32 cpu_sr; + unsigned long mask = 1 << (bit & 31); + + p += bit >> 5; + + cpu_sr = tls_os_set_critical(); + *p &= ~mask; + tls_os_release_critical(cpu_sr); +} + +static __inline void change_bit(unsigned int bit, volatile unsigned long *p) +{ + u32 cpu_sr; + unsigned long mask = 1 << (bit & 31); + + p += bit >> 5; + + cpu_sr = tls_os_set_critical(); + *p ^= mask; + tls_os_release_critical(cpu_sr); +} + +static __inline int +test_and_set_bit(unsigned int bit, volatile unsigned long *p) +{ + u32 cpu_sr; + unsigned int res; + unsigned long mask = 1 << (bit & 31); + + p += bit >> 5; + + cpu_sr = tls_os_set_critical(); + res = *p; + *p = res | mask; + tls_os_release_critical(cpu_sr); + + return res & mask; +} + +static __inline int +test_and_clear_bit(unsigned int bit, volatile unsigned long *p) +{ + u32 cpu_sr; + unsigned int res; + unsigned long mask = 1 << (bit & 31); + + p += bit >> 5; + + cpu_sr = tls_os_set_critical(); + res = *p; + *p = res & ~mask; + tls_os_release_critical(cpu_sr); + + return res & mask; +} + +static __inline int +test_bit(unsigned int bit, volatile unsigned long *p) +{ + u32 cpu_sr; + unsigned int res; + unsigned long mask = 1 << (bit & 31); + + p += bit >> 5; + + cpu_sr = tls_os_set_critical(); + res = *p; + tls_os_release_critical(cpu_sr); + + return res & mask; +} + +static __inline int +test_and_change_bit(unsigned int bit, volatile unsigned long *p) +{ + u32 cpu_sr; + unsigned int res; + unsigned long mask = 1 << (bit & 31); + + p += bit >> 5; + + cpu_sr = tls_os_set_critical(); + res = *p; + *p = res ^ mask; + tls_os_release_critical(cpu_sr); + + return res & mask; +} + + +#endif /* BITOPS_H */ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/inc/misc.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/inc/misc.h new file mode 100644 index 00000000..fe61bcda --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/inc/misc.h @@ -0,0 +1,206 @@ +/** + ****************************************************************************** + * @file misc.h + * @author MCD Application Team + * @version V3.6.1 + * @date 05-March-2012 + * @brief This file contains all the functions prototypes for the miscellaneous + * firmware library functions (add-on to CMSIS functions). + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MISC_H +#define __MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "wm_regs.h" + +/** @addtogroup W600_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/** @defgroup MISC_Exported_Types + * @{ + */ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup NVIC_Priority_Table + * @{ + */ + +/** +@code + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + ============================================================================================================================ + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ============================================================================================================================ + NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority + | | | 4 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + | | | 3 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bits for subpriority + ============================================================================================================================ +@endcode +*/ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @} + */ + +/** @defgroup SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Functions + * @{ + */ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT 2014 Winner Microelectronics Co., Ltd. *****END OF FILE****/ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/inc/tls_common.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/inc/tls_common.h new file mode 100644 index 00000000..782d1bd7 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/inc/tls_common.h @@ -0,0 +1,254 @@ +#ifndef TLS_COMMON_H +#define TLS_COMMON_H + +#include +#include "wm_type_def.h" +#include "wm_config.h" + +#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5] +#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x" + +#define BIT(x) (1UL << (x)) + +#define time_after(a, b) ((long)(b) - (long)(a) < 0) +#define time_before(a,b) time_after(b,a) + +/* + * These are the defined Ethernet Protocol ID's. + */ + +#define ETH_P_LOOP 0x0060 /* Ethernet Loopback packet */ +#define ETH_P_PUP 0x0200 /* Xerox PUP packet */ +#define ETH_P_PUPAT 0x0201 /* Xerox PUP Addr Trans packet */ +#define ETH_P_IP 0x0800 /* Internet Protocol packet */ +#define ETH_P_X25 0x0805 /* CCITT X.25 */ +#define ETH_P_ARP 0x0806 /* Address Resolution packet */ +#define ETH_P_BPQ 0x08FF /* G8BPQ AX.25 Ethernet Packet [ NOT AN OFFICIALLY REGISTERED ID ] */ +#define ETH_P_IEEEPUP 0x0a00 /* Xerox IEEE802.3 PUP packet */ +#define ETH_P_IEEEPUPAT 0x0a01 /* Xerox IEEE802.3 PUP Addr Trans packet */ +#define ETH_P_DEC 0x6000 /* DEC Assigned proto */ +#define ETH_P_DNA_DL 0x6001 /* DEC DNA Dump/Load */ +#define ETH_P_DNA_RC 0x6002 /* DEC DNA Remote Console */ +#define ETH_P_DNA_RT 0x6003 /* DEC DNA Routing */ +#define ETH_P_LAT 0x6004 /* DEC LAT */ +#define ETH_P_DIAG 0x6005 /* DEC Diagnostics */ +#define ETH_P_CUST 0x6006 /* DEC Customer use */ +#define ETH_P_SCA 0x6007 /* DEC Systems Comms Arch */ +#define ETH_P_TEB 0x6558 /* Trans Ether Bridging */ +#define ETH_P_RARP 0x8035 /* Reverse Addr Res packet */ +#define ETH_P_ATALK 0x809B /* Appletalk DDP */ +#define ETH_P_AARP 0x80F3 /* Appletalk AARP */ +#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ +#define ETH_P_IPX 0x8137 /* IPX over DIX */ +#define ETH_P_IPV6 0x86DD /* IPv6 over bluebook */ +#define ETH_P_PAUSE 0x8808 /* IEEE Pause frames. See 802.3 31B */ +#define ETH_P_SLOW 0x8809 /* Slow Protocol. See 802.3ad 43B */ +#define ETH_P_WCCP 0x883E /* Web-cache coordination protocol + * defined in draft-wilson-wrec-wccp-v2-00.txt */ +#define ETH_P_PPP_DISC 0x8863 /* PPPoE discovery messages */ +#define ETH_P_PPP_SES 0x8864 /* PPPoE session messages */ +#define ETH_P_MPLS_UC 0x8847 /* MPLS Unicast traffic */ +#define ETH_P_MPLS_MC 0x8848 /* MPLS Multicast traffic */ +#define ETH_P_ATMMPOA 0x884c /* MultiProtocol Over ATM */ +#define ETH_P_ATMFATE 0x8884 /* Frame-based ATM Transport + * over Ethernet + */ +#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */ +#define ETH_P_WAPI 0x88B4 /* WAPI authentication */ +#define ETH_P_AOE 0x88A2 /* ATA over Ethernet */ +#define ETH_P_TIPC 0x88CA /* TIPC */ +#define ETH_P_FCOE 0x8906 /* Fibre Channel over Ethernet */ +#define ETH_P_EDSA 0xDADA /* Ethertype DSA [ NOT AN OFFICIALLY REGISTERED ID ] */ + +#define ETH_HLEN 14 /* Total octets in header. */ + +#ifndef ETH_ALEN +#define ETH_ALEN 6 +#endif +#ifndef IFNAMSIZ +#define IFNAMSIZ 16 +#endif +#ifndef ETH_P_ALL +#define ETH_P_ALL 0x0003 +#endif +#ifndef ETH_P_80211_ENCAP +#define ETH_P_80211_ENCAP 0x890d /* TDLS comes under this category */ +#endif +#ifndef ETH_P_PAE +#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */ +#endif /* ETH_P_PAE */ +#ifndef ETH_P_EAPOL +#define ETH_P_EAPOL ETH_P_PAE +#endif /* ETH_P_EAPOL */ +#ifndef ETH_P_RSN_PREAUTH +#define ETH_P_RSN_PREAUTH 0x88c7 +#endif /* ETH_P_RSN_PREAUTH */ +#ifndef ETH_P_RRB +#define ETH_P_RRB 0x890D +#endif /* ETH_P_RRB */ + +#define PRINTF_FORMAT(a,b) __attribute__ ((format (printf, (a), (b)))) +#define STRUCT_PACKED __attribute__ ((packed)) + +#define broadcast_ether_addr (const u8 *) "\xff\xff\xff\xff\xff\xff" + +/** + * compare_ether_addr - Compare two Ethernet addresses + * @addr1: Pointer to a six-byte array containing the Ethernet address + * @addr2: Pointer other six-byte array containing the Ethernet address + * + * Compare two ethernet addresses, returns 0 if equal + */ +static __inline unsigned compare_ether_addr(const u8 *addr1, const u8 *addr2) +{ + return !((addr1[0] == addr2[0]) && (addr1[1] == addr2[1]) && (addr1[2] == addr2[2]) && \ + (addr1[3] == addr2[3]) && (addr1[4] == addr2[4]) && (addr1[5] == addr2[5])); +} + +static __inline int is_zero_ether_addr(const u8 *a) +{ + return !(a[0] | a[1] | a[2] | a[3] | a[4] | a[5]); +} + +static __inline int is_broadcast_ether_addr(const u8 *a) +{ + return (a[0] & a[1] & a[2] & a[3] & a[4] & a[5]) == 0xff; +} + +static __inline int is_multicast_ether_addr(const u8 *addr) +{ + return (0x01 & addr[0]); +} + +static __inline unsigned short swap_16(unsigned short v) +{ + return ((v & 0xff) << 8) | (v >> 8); +} + +static __inline unsigned int swap_32(unsigned int v) +{ + return ((v & 0xff) << 24) | ((v & 0xff00) << 8) | + ((v & 0xff0000) >> 8) | (v >> 24); +} + +#define le_to_host16(n) (n) +#define host_to_le16(n) (n) +#define be_to_host16(n) swap_16(n) +#define host_to_be16(n) swap_16(n) +#define le_to_host32(n) (n) +#define le_to_host64(n) (n) +#define be_to_host32(n) swap_32(n) +#define host_to_be32(n) swap_32(n) + +static __inline u16 get_unaligned_le16(const u8 *p) +{ + return p[0] | p[1] << 8; +} + +static __inline u32 get_unaligned_le32(const u8 *p) +{ + return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24; +} + +static __inline void put_unaligned_le16(u16 val, u8 *p) +{ + *p++ = val; + *p++ = val >> 8; +} + +static __inline void put_unaligned_le32(u32 val, u8 *p) +{ + put_unaligned_le16(val >> 16, p + 2); + put_unaligned_le16(val, p); +} + +static __inline u16 get_unaligned_be16(const u8 *p) +{ + return be_to_host16(get_unaligned_le16(p)); +} + +static __inline u32 get_unaligned_be32(const u8 *p) +{ + return be_to_host32(get_unaligned_le32(p)); +} + +static __inline void put_unaligned_be16(u16 val, u8 *p) +{ + *p++ = val >> 8; + *p++ = val; +} + +static __inline void put_unaligned_be32(u32 val, u8 *p) +{ + put_unaligned_be16(val >> 16, p); + put_unaligned_be16(val, p + 2); +} + + +#ifdef __CHECKER__ +#define __force __attribute__((force)) +#define __bitwise __attribute__((bitwise)) +#else +#define __force +#define __bitwise +#endif + +typedef u16 __bitwise be16; +typedef u16 __bitwise le16; +typedef u32 __bitwise be32; +typedef u32 __bitwise le32; +typedef u64 __bitwise be64; +typedef u64 __bitwise le64; + +/* + * This is an Ethernet frame header. + */ +struct ethhdr { + unsigned char h_dest[ETH_ALEN]; /* destination eth addr */ + unsigned char h_source[ETH_ALEN]; /* source ether addr */ + unsigned short h_proto; /* packet type ID field */ +} __attribute__((packed)); + + + +typedef struct { + volatile int counter; +} atomic_t; + +struct kref { + atomic_t refcount; +}; + +//static __inline int atomic_sub_return(int i, atomic_t *v) +//{ +// u32 cpu_sr; +// int val; + +// cpu_sr = tls_os_set_critical(); +// val = v->counter; +// v->counter = val -= i; +// tls_os_release_critical(cpu_sr); + +// return val; +//} + +//static __inline int atomic_add_return(int i, atomic_t *v) +//{ +// u32 cpu_sr; +// int val; + +// cpu_sr = tls_os_set_critical(); +// val = v->counter; +// v->counter = val += i; +// tls_os_release_critical(cpu_sr); + +// return val; +//} + + +//#define atomic_set(v,i) (((v)->counter) = (i)) +//#define atomic_dec_and_test(v) (atomic_sub_return(1, v) == 0) +//#define atomic_inc(v) (void) atomic_add_return(1, v) +//#define atomic_dec(v) (void) atomic_sub_return(1, v) + +#endif /* end of TLS_COMMON_H */ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/inc/utils.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/inc/utils.h new file mode 100644 index 00000000..9a226a94 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/inc/utils.h @@ -0,0 +1,37 @@ +/************************************************************************** + * File Name : utils.h + * Author : + * Version : 1.0 + * Date : + * Description : + * + * Copyright (c) 2014 Winner Microelectronics Co., Ltd. + * All rights reserved. + * + ***************************************************************************/ +#ifndef UTILS_H +#define UTILS_H + +int chk_crc8(u8 *ptr, u32 len); +u8 get_crc8(u8 *ptr, u32 len); +u8 calculate_crc8(u8 crc8, u8 *ptr, u32 len); +u32 get_crc32(u8 *data, u32 data_size); +u32 checksum(u32 *data, u32 length, u32 init); +int atodec(char ch); +int strtodec(int *dec, char *str); +int atohex(char ch); +int strtohex(u32 *hex, char *str); +int strtohexarray(u8 array[], int cnt, char *str); +int strtoip(u32 *ipadr, char * str); +void iptostr(u32 ip, char *str); +void mactostr(u8 mac[], char *str); + +int hex_to_digit(int c); +int digit_to_hex(int c); +int hexstr_to_unit(char *buf, u32 *d); +int string_to_uint(char *buf, u32 *d); +int string_to_ipaddr(const char *buf, u8 *addr); +char * strdup(const char *s); +char * strndup(const char *s, size_t len); + +#endif /* UTILS_H */ diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/inc/wm_dbg.h b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/inc/wm_dbg.h new file mode 100644 index 00000000..c9661032 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/inc/wm_dbg.h @@ -0,0 +1,93 @@ +#ifndef __WM_DBG_H__ +#define __WM_DBG_H__ + +#include "wm_debug.h" + +/* Define the module switcher */ +#define TLS_FLASH_DBG TLS_DBG_OFF +#define TLS_SPI_DBG TLS_DBG_OFF +#define TLS_IO_DBG TLS_DBG_OFF +#define TLS_DMA_DBG TLS_DBG_OFF +#define TLS_WL_DBG TLS_DBG_OFF +#define TLS_WPA_DBG TLS_DBG_OFF + +/* flash info */ +#if (TLS_FLASH_DBG && TLS_DBG_LEVEL_INFO) +#define TLS_DBGPRT_FLASH_INFO(f, a...) __TLS_DBGPRT_INFO(f, ##a) +#else +#define TLS_DBGPRT_FLASH_INFO(f, a...) +#endif + +/* flash warnning */ +#if (TLS_FLASH_DBG && TLS_DBG_LEVEL_WARNING) +#define TLS_DBGPRT_FLASH_WARNING(f, a...) __TLS_DBGPRT_WARNING(f, ##a) +#else +#define TLS_DBGPRT_FLASH_WARNING(f, a...) +#endif + +/* flash error */ +#if (TLS_FLASH_DBG && TLS_DBG_LEVEL_ERR) +#define TLS_DBGPRT_FLASH_ERR(f, a...) __TLS_DBGPRT_ERR(f, ##a) +#else +#define TLS_DBGPRT_FLASH_ERR(f, a...) +#endif + + +#if (TLS_SPI_DBG && TLS_DBG_LEVEL_INFO) +#define TLS_DBGPRT_SPI_INFO(f, a...) __TLS_DBGPRT_INFO(f, ##a) +#else +#define TLS_DBGPRT_SPI_INFO(f, a...) +#endif + +#if (TLS_SPI_DBG && TLS_DBG_LEVEL_WARNING) +#define TLS_DBGPRT_SPI_WARNING(f, a...) __TLS_DBGPRT_WARNING(f, ##a) +#else +#define TLS_DBGPRT_SPI_WARNING(f, a...) +#endif + +#if (TLS_SPI_DBG && TLS_DBG_LEVEL_ERR) +#define TLS_DBGPRT_SPI_ERR(f, a...) __TLS_DBGPRT_ERR(f, ##a) +#else +#define TLS_DBGPRT_SPI_ERR(f, a...) +#endif + + +#if (TLS_IO_DBG && TLS_DBG_LEVEL_INFO) +#define TLS_DBGPRT_IO_INFO(f, a...) __TLS_DBGPRT_INFO(f, ##a) +#else +#define TLS_DBGPRT_IO_INFO(f, a...) +#endif + +#if (TLS_IO_DBG && TLS_DBG_LEVEL_WARNING) +#define TLS_DBGPRT_IO_WARNING(f, a...) __TLS_DBGPRT_WARNING(f, ##a) +#else +#define TLS_DBGPRT_IO_WARNING(f, a...) +#endif + +#if (TLS_IO_DBG && TLS_DBG_LEVEL_ERR) +#define TLS_DBGPRT_IO_ERR(f, a...) __TLS_DBGPRT_ERR(f, ##a) +#else +#define TLS_DBGPRT_IO_ERR(f, a...) +#endif + + +#if (TLS_DMA_DBG && TLS_DBG_LEVEL_INFO) +#define TLS_DBGPRT_DMA_INFO(f, a...) __TLS_DBGPRT_INFO(f, ##a) +#else +#define TLS_DBGPRT_DMA_INFO(f, a...) +#endif + +#if (TLS_DMA_DBG && TLS_DBG_LEVEL_WARNING) +#define TLS_DBGPRT_DMA_WARNING(f, a...) __TLS_DBGPRT_WARNING(f, ##a) +#else +#define TLS_DBGPRT_DMA_WARNING(f, a...) +#endif + +#if (TLS_DMA_DBG && TLS_DBG_LEVEL_ERR) +#define TLS_DBGPRT_DMA_ERR(f, a...) __TLS_DBGPRT_ERR(f, ##a) +#else +#define TLS_DBGPRT_DMA_ERR(f, a...) +#endif + +#endif /* __DBG_H__ */ + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/make_platform_a.sh b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/make_platform_a.sh new file mode 100644 index 00000000..eee7d0e1 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/make_platform_a.sh @@ -0,0 +1,16 @@ +#!/bin/bash +set -e + +export SDK_PATH=$(dirname $(pwd)) + +echo "make_lib.sh version 20150924" +echo "" + +for dir in common drivers sys; do + cd $dir + make clean + make COMPILE=gcc + echo "move lib$dir.lib to lib folder" + cp .output/w600/lib/lib$dir.a ../../lib/lib$dir.a + cd .. +done; \ No newline at end of file diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/make_platform_lib.sh b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/make_platform_lib.sh new file mode 100644 index 00000000..1d192fe9 --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/make_platform_lib.sh @@ -0,0 +1,14 @@ +#!/bin/bash +set -e + +echo "make_lib.sh" +echo "" + +for dir in common drivers sys; do + cd $dir + make clean + make COMPILE=armcc + echo "move lib$dir.lib to lib folder" + cp .output/w600/lib/lib$dir.lib ../../lib/lib$dir.lib + cd .. +done; \ No newline at end of file diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/sys/Makefile b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/sys/Makefile new file mode 100644 index 00000000..141995be --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/sys/Makefile @@ -0,0 +1,47 @@ + +############################################################# +# Required variables for each makefile +# Discard this section from all parent makefiles +# Expected variables (with automatic defaults): +# CSRCS (all "C" files in the dir) +# SUBDIRS (all subdirs with a Makefile) +# GEN_LIBS - list of libs to be generated () +# GEN_IMAGES - list of images to be generated () +# COMPONENTS_xxx - a list of libs/objs in the form +# subdir/lib to be extracted and rolled up into +# a generated lib/image xxx.a () +# +TOP_DIR = ../../ +sinclude $(TOP_DIR)/tools/tool_chain.def + +ifndef PDIR +GEN_LIBS = libsys$(LIB_EXT) +endif + + +############################################################# +# Configuration i.e. compile options etc. +# Target specific stuff (defines etc.) goes in here! +# Generally values applying to a tree are captured in the +# makefile at its root level - these are then overridden +# for a subtree within the makefile rooted therein +# +#DEFINES += + +############################################################# +# Recursion Magic - Don't touch this!! +# +# Each subtree potentially has an include directory +# corresponding to the common APIs applicable to modules +# rooted at that subtree. Accordingly, the INCLUDE PATH +# of a module can only contain the include directories up +# its parent path, and not its siblings +# +# Required for each makefile to inherit from the parent +# + +sinclude $(TOP_DIR)/tools/rules.mk +INCLUDES := $(INCLUDES) -I $(PDIR)include +PDIR := ../$(PDIR) +sinclude $(PDIR)Makefile + diff --git a/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/sys/wm_main.c b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/sys/wm_main.c new file mode 100644 index 00000000..a401d32c --- /dev/null +++ b/platform/vendor_bsp/WinnerMicro/w601/WMLIB/platform/sys/wm_main.c @@ -0,0 +1,137 @@ +/***************************************************************************** +* +* File Name : wm_main.c +* +* Description: wm main +* +* Copyright (c) 2014 Winner Micro Electronic Design Co., Ltd. +* All rights reserved. +* +* Author : +* +* Date : 2014-6-14 +*****************************************************************************/ +#include +#include "wm_regs.h" +#include "wm_type_def.h" +#include "wm_cpu.h" +#include "wm_io.h" +#include "misc.h" +#include "wm_gpio_afsel.h" + +#define FW_MAJOR_VER 0x03 +#define FW_MINOR_VER 0x02 +#define FW_PATCH_VER 0x00 + +//const char FirmWareVer[4] = { +// 'G', +// FW_MAJOR_VER, /* Main version */ +// FW_MINOR_VER, /* Subversion */ +// FW_PATCH_VER /* Internal version */ +// }; +//const char HwVer[6] = { +// 'H', +// 0x1, +// 0x0, +// 0x0, +// 0x0, +// 0x0 +//}; +extern const char WiFiVer[]; +extern u8 tx_gain_group[]; +extern void *tls_wl_init(u8 *tx_gain, u8* mac_addr, u8 *hwver); +extern int wpa_supplicant_init(u8 *mac_addr); +extern void tls_sys_auto_mode_run(void); +extern void tls_spi_slave_sel(u16 slave); +extern void UserMain(void); +extern void tls_fls_layout_init(void); + + +void Uart0Init(void) +{ +// u32 bd; + +// u32 apbclk; +// tls_sys_clk sysclk; + +// tls_sys_clk_get(&sysclk); +// apbclk = sysclk.apbclk * 1000000; + +///* baud rate register value = apb_clk/(16*115200) */ +///* 如果APB时钟是40MHz， */ +///* 波特率寄存器的值设置为 115200 : 21 */ +///* 9600bps : 260 */ +// { +// bd = (apbclk / (16 * 115200) - +// 1) | (((apbclk % (115200 * 16)) * 16 / (115200 * 16)) << 16); +// tls_reg_write32(HR_UART0_BAUD_RATE_CTRL, bd); +// /* Line control register : Normal,No parity,1 stop,8 bits, only use tx */ +// tls_reg_write32(HR_UART0_LINE_CTRL, ULCON_WL8 | ULCON_TX_EN); + +// /* disable auto flow control */ +// tls_reg_write32(HR_UART0_FLOW_CTRL, 0); +// /* disable dma */ +// tls_reg_write32(HR_UART0_DMA_CTRL, 0); +// /* one byte tx */ +// tls_reg_write32(HR_UART0_FIFO_CTRL, 0); +// /* disable interrupt */ +// tls_reg_write32(HR_UART0_INT_MASK, 0xFF); +// } +} +/****************/ +/* main program */ +/****************/ + +//void vApplicationIdleHook( void ) +//{ +// /* clear watch dog interrupt */ + +//#if !defined(__CC_ARM) +// __asm volatile ("wfi"); +//#else +// __WFI(); +//#endif + +// return; +//} + + +void wm_gpio_config() +{ + /* must call first */ + wm_gpio_af_disable(); + +// /* UART0_TX-PA04 UART0_RX-PA05 */ +// wm_uart0_tx_config(WM_IO_PA_04); +// wm_uart0_rx_config(WM_IO_PA_05); + + /* UART1_RX-PB11 UART1_TX-PB12 */ + wm_uart1_rx_config(WM_IO_PB_11); + wm_uart1_tx_config(WM_IO_PB_12); + + /*MASTER SPI configuratioin*/ +// wm_spi_cs_config(WM_IO_PA_02); +// wm_spi_ck_config(WM_IO_PA_11); +// wm_spi_di_config(WM_IO_PA_03); +// wm_spi_do_config(WM_IO_PA_09); +} + +//int main(void) +//{ +// tls_sys_clk_set(CPU_CLK_80M); +// +// //tls_pmu_clk_select(0); +// +// //tls_sys_clk sysclk; +// +// //tls_sys_clk_get(&sysclk); +// //SysTick_Config(sysclk.cpuclk*UNIT_MHZ/500); + +// //NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4); +// //NVIC_SystemLPConfig(NVIC_LP_SLEEPDEEP, ENABLE); +// +// wm_gpio_config(); + +// UserMain(); +//} +